target/arm/translate-a64.h

   1 /*
   2  *  AArch64 translation, common definitions.
   3  *
   4  * This library is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU Lesser General Public
   6  * License as published by the Free Software Foundation; either
   7  * version 2.1 of the License, or (at your option) any later version.
   8  *
   9  * This library is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  12  * Lesser General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU Lesser General Public
  15  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #ifndef TARGET_ARM_TRANSLATE_A64_H
  19 #define TARGET_ARM_TRANSLATE_A64_H
  20
  21 TCGv_i64 new_tmp_a64(DisasContext *s);
  22 TCGv_i64 new_tmp_a64_local(DisasContext *s);
  23 TCGv_i64 new_tmp_a64_zero(DisasContext *s);
  24 TCGv_i64 cpu_reg(DisasContext *s, int reg);
  25 TCGv_i64 cpu_reg_sp(DisasContext *s, int reg);
  26 TCGv_i64 read_cpu_reg(DisasContext *s, int reg, int sf);
  27 TCGv_i64 read_cpu_reg_sp(DisasContext *s, int reg, int sf);
  28 void write_fp_dreg(DisasContext *s, int reg, TCGv_i64 v);
  29 bool logic_imm_decode_wmask(uint64_t *result, unsigned int immn,
  30                             unsigned int imms, unsigned int immr);
  31 bool sve_access_check(DisasContext *s);
  32 TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i64 addr);
  33 TCGv_i64 gen_mte_check1(DisasContext *s, TCGv_i64 addr, bool is_write,
  34                         bool tag_checked, int log2_size);
  35 TCGv_i64 gen_mte_checkN(DisasContext *s, TCGv_i64 addr, bool is_write,
  36                         bool tag_checked, int size);
  37
  38 /* We should have at some point before trying to access an FP register
  39  * done the necessary access check, so assert that
  40  * (a) we did the check and
  41  * (b) we didn't then just plough ahead anyway if it failed.
  42  * Print the instruction pattern in the abort message so we can figure
  43  * out what we need to fix if a user encounters this problem in the wild.
  44  */
  45 static inline void assert_fp_access_checked(DisasContext *s)
  46 {
  47 #ifdef CONFIG_DEBUG_TCG
  48     if (unlikely(!s->fp_access_checked || s->fp_excp_el)) {
  49         fprintf(stderr, "target-arm: FP access check missing for "
  50                 "instruction 0x%08x\n", s->insn);
  51         abort();
  52     }
  53 #endif
  54 }
  55
  56 /* Return the offset into CPUARMState of an element of specified
  57  * size, 'element' places in from the least significant end of
  58  * the FP/vector register Qn.
  59  */
  60 static inline int vec_reg_offset(DisasContext *s, int regno,
  61                                  int element, MemOp size)
  62 {
  63     int element_size = 1 << size;
  64     int offs = element * element_size;
  65 #if HOST_BIG_ENDIAN
  66     /* This is complicated slightly because vfp.zregs[n].d[0] is
  67      * still the lowest and vfp.zregs[n].d[15] the highest of the
  68      * 256 byte vector, even on big endian systems.
  69      *
  70      * Calculate the offset assuming fully little-endian,
  71      * then XOR to account for the order of the 8-byte units.
  72      *
  73      * For 16 byte elements, the two 8 byte halves will not form a
  74      * host int128 if the host is bigendian, since they're in the
  75      * wrong order.  However the only 16 byte operation we have is
  76      * a move, so we can ignore this for the moment.  More complicated
  77      * operations will have to special case loading and storing from
  78      * the zregs array.
  79      */
  80     if (element_size < 8) {
  81         offs ^= 8 - element_size;
  82     }
  83 #endif
  84     offs += offsetof(CPUARMState, vfp.zregs[regno]);
  85     assert_fp_access_checked(s);
  86     return offs;
  87 }
  88
  89 /* Return the offset info CPUARMState of the "whole" vector register Qn.  */
  90 static inline int vec_full_reg_offset(DisasContext *s, int regno)
  91 {
  92     assert_fp_access_checked(s);
  93     return offsetof(CPUARMState, vfp.zregs[regno]);
  94 }
  95
  96 /* Return a newly allocated pointer to the vector register.  */
  97 static inline TCGv_ptr vec_full_reg_ptr(DisasContext *s, int regno)
  98 {
  99     TCGv_ptr ret = tcg_temp_new_ptr();
 100     tcg_gen_addi_ptr(ret, cpu_env, vec_full_reg_offset(s, regno));
 101     return ret;
 102 }
 103
 104 /* Return the byte size of the "whole" vector register, VL / 8.  */
 105 static inline int vec_full_reg_size(DisasContext *s)
 106 {
 107     return s->sve_len;
 108 }
 109
 110 bool disas_sve(DisasContext *, uint32_t);
 111
 112 void gen_gvec_rax1(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
 113                    uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
 114 void gen_gvec_xar(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
 115                   uint32_t rm_ofs, int64_t shift,
 116                   uint32_t opr_sz, uint32_t max_sz);
 117
 118 #endif /* TARGET_ARM_TRANSLATE_A64_H */