?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
target/arm: Enable FEAT_ECV for 'max' CPU
[qemu/armbru.git] / target / arm / tcg / cpu64.c
blob9f7a9f3d2cc6ce824f89e915a331632ee1b99082
1 /*
2 * QEMU AArch64 TCG CPUs
3 *
4 * Copyright (c) 2013 Linaro Ltd
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
19 */
20
21 #include "qemu/osdep.h"
22 #include "qapi/error.h"
23 #include "cpu.h"
24 #include "qemu/module.h"
25 #include "qapi/visitor.h"
26 #include "hw/qdev-properties.h"
27 #include "qemu/units.h"
28 #include "internals.h"
29 #include "cpu-features.h"
30 #include "cpregs.h"
31
32 static uint64_t make_ccsidr64(unsigned assoc, unsigned linesize,
33 unsigned cachesize)
34 {
35 unsigned lg_linesize = ctz32(linesize);
36 unsigned sets;
37
38 /*
39 * The 64-bit CCSIDR_EL1 format is:
40 * [55:32] number of sets - 1
41 * [23:3] associativity - 1
42 * [2:0] log2(linesize) - 4
43 * so 0 == 16 bytes, 1 == 32 bytes, 2 == 64 bytes, etc
44 */
45 assert(assoc != 0);
46 assert(is_power_of_2(linesize));
47 assert(lg_linesize >= 4 && lg_linesize <= 7 + 4);
48
49 /* sets * associativity * linesize == cachesize. */
50 sets = cachesize / (assoc * linesize);
51 assert(cachesize % (assoc * linesize) == 0);
52
53 return ((uint64_t)(sets - 1) << 32)
54 | ((assoc - 1) << 3)
55 | (lg_linesize - 4);
56 }
57
58 static void aarch64_a35_initfn(Object *obj)
59 {
60 ARMCPU *cpu = ARM_CPU(obj);
61
62 cpu->dtb_compatible = "arm,cortex-a35";
63 set_feature(&cpu->env, ARM_FEATURE_V8);
64 set_feature(&cpu->env, ARM_FEATURE_NEON);
65 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
66 set_feature(&cpu->env, ARM_FEATURE_AARCH64);
67 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
68 set_feature(&cpu->env, ARM_FEATURE_EL2);
69 set_feature(&cpu->env, ARM_FEATURE_EL3);
70 set_feature(&cpu->env, ARM_FEATURE_PMU);
71
72 /* From B2.2 AArch64 identification registers. */
73 cpu->midr = 0x411fd040;
74 cpu->revidr = 0;
75 cpu->ctr = 0x84448004;
76 cpu->isar.id_pfr0 = 0x00000131;
77 cpu->isar.id_pfr1 = 0x00011011;
78 cpu->isar.id_dfr0 = 0x03010066;
79 cpu->id_afr0 = 0;
80 cpu->isar.id_mmfr0 = 0x10201105;
81 cpu->isar.id_mmfr1 = 0x40000000;
82 cpu->isar.id_mmfr2 = 0x01260000;
83 cpu->isar.id_mmfr3 = 0x02102211;
84 cpu->isar.id_isar0 = 0x02101110;
85 cpu->isar.id_isar1 = 0x13112111;
86 cpu->isar.id_isar2 = 0x21232042;
87 cpu->isar.id_isar3 = 0x01112131;
88 cpu->isar.id_isar4 = 0x00011142;
89 cpu->isar.id_isar5 = 0x00011121;
90 cpu->isar.id_aa64pfr0 = 0x00002222;
91 cpu->isar.id_aa64pfr1 = 0;
92 cpu->isar.id_aa64dfr0 = 0x10305106;
93 cpu->isar.id_aa64dfr1 = 0;
94 cpu->isar.id_aa64isar0 = 0x00011120;
95 cpu->isar.id_aa64isar1 = 0;
96 cpu->isar.id_aa64mmfr0 = 0x00101122;
97 cpu->isar.id_aa64mmfr1 = 0;
98 cpu->clidr = 0x0a200023;
99 cpu->dcz_blocksize = 4;
100
101 /* From B2.4 AArch64 Virtual Memory control registers */
102 cpu->reset_sctlr = 0x00c50838;
103
104 /* From B2.10 AArch64 performance monitor registers */
105 cpu->isar.reset_pmcr_el0 = 0x410a3000;
106
107 /* From B2.29 Cache ID registers */
108 cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */
109 cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */
110 cpu->ccsidr[2] = 0x703fe03a; /* 512KB L2 cache */
111
112 /* From B3.5 VGIC Type register */
113 cpu->gic_num_lrs = 4;
114 cpu->gic_vpribits = 5;
115 cpu->gic_vprebits = 5;
116 cpu->gic_pribits = 5;
117
118 /* From C6.4 Debug ID Register */
119 cpu->isar.dbgdidr = 0x3516d000;
120 /* From C6.5 Debug Device ID Register */
121 cpu->isar.dbgdevid = 0x00110f13;
122 /* From C6.6 Debug Device ID Register 1 */
123 cpu->isar.dbgdevid1 = 0x2;
124
125 /* From Cortex-A35 SIMD and Floating-point Support r1p0 */
126 /* From 3.2 AArch32 register summary */
127 cpu->reset_fpsid = 0x41034043;
128
129 /* From 2.2 AArch64 register summary */
130 cpu->isar.mvfr0 = 0x10110222;
131 cpu->isar.mvfr1 = 0x12111111;
132 cpu->isar.mvfr2 = 0x00000043;
133
134 /* These values are the same with A53/A57/A72. */
135 define_cortex_a72_a57_a53_cp_reginfo(cpu);
136 }
137
138 static void cpu_max_get_sve_max_vq(Object *obj, Visitor *v, const char *name,
139 void *opaque, Error **errp)
140 {
141 ARMCPU *cpu = ARM_CPU(obj);
142 uint32_t value;
143
144 /* All vector lengths are disabled when SVE is off. */
145 if (!cpu_isar_feature(aa64_sve, cpu)) {
146 value = 0;
147 } else {
148 value = cpu->sve_max_vq;
149 }
150 visit_type_uint32(v, name, &value, errp);
151 }
152
153 static void cpu_max_set_sve_max_vq(Object *obj, Visitor *v, const char *name,
154 void *opaque, Error **errp)
155 {
156 ARMCPU *cpu = ARM_CPU(obj);
157 uint32_t max_vq;
158
159 if (!visit_type_uint32(v, name, &max_vq, errp)) {
160 return;
161 }
162
163 if (max_vq == 0 || max_vq > ARM_MAX_VQ) {
164 error_setg(errp, "unsupported SVE vector length");
165 error_append_hint(errp, "Valid sve-max-vq in range [1-%d]\n",
166 ARM_MAX_VQ);
167 return;
168 }
169
170 cpu->sve_max_vq = max_vq;
171 }
172
173 static bool cpu_arm_get_rme(Object *obj, Error **errp)
174 {
175 ARMCPU *cpu = ARM_CPU(obj);
176 return cpu_isar_feature(aa64_rme, cpu);
177 }
178
179 static void cpu_arm_set_rme(Object *obj, bool value, Error **errp)
180 {
181 ARMCPU *cpu = ARM_CPU(obj);
182 uint64_t t;
183
184 t = cpu->isar.id_aa64pfr0;
185 t = FIELD_DP64(t, ID_AA64PFR0, RME, value);
186 cpu->isar.id_aa64pfr0 = t;
187 }
188
189 static void cpu_max_set_l0gptsz(Object *obj, Visitor *v, const char *name,
190 void *opaque, Error **errp)
191 {
192 ARMCPU *cpu = ARM_CPU(obj);
193 uint32_t value;
194
195 if (!visit_type_uint32(v, name, &value, errp)) {
196 return;
197 }
198
199 /* Encode the value for the GPCCR_EL3 field. */
200 switch (value) {
201 case 30:
202 case 34:
203 case 36:
204 case 39:
205 cpu->reset_l0gptsz = value - 30;
206 break;
207 default:
208 error_setg(errp, "invalid value for l0gptsz");
209 error_append_hint(errp, "valid values are 30, 34, 36, 39\n");
210 break;
211 }
212 }
213
214 static void cpu_max_get_l0gptsz(Object *obj, Visitor *v, const char *name,
215 void *opaque, Error **errp)
216 {
217 ARMCPU *cpu = ARM_CPU(obj);
218 uint32_t value = cpu->reset_l0gptsz + 30;
219
220 visit_type_uint32(v, name, &value, errp);
221 }
222
223 static Property arm_cpu_lpa2_property =
224 DEFINE_PROP_BOOL("lpa2", ARMCPU, prop_lpa2, true);
225
226 static void aarch64_a55_initfn(Object *obj)
227 {
228 ARMCPU *cpu = ARM_CPU(obj);
229
230 cpu->dtb_compatible = "arm,cortex-a55";
231 set_feature(&cpu->env, ARM_FEATURE_V8);
232 set_feature(&cpu->env, ARM_FEATURE_NEON);
233 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
234 set_feature(&cpu->env, ARM_FEATURE_AARCH64);
235 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
236 set_feature(&cpu->env, ARM_FEATURE_EL2);
237 set_feature(&cpu->env, ARM_FEATURE_EL3);
238 set_feature(&cpu->env, ARM_FEATURE_PMU);
239
240 /* Ordered by B2.4 AArch64 registers by functional group */
241 cpu->clidr = 0x82000023;
242 cpu->ctr = 0x84448004; /* L1Ip = VIPT */
243 cpu->dcz_blocksize = 4; /* 64 bytes */
244 cpu->isar.id_aa64dfr0 = 0x0000000010305408ull;
245 cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
246 cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
247 cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull;
248 cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
249 cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
250 cpu->isar.id_aa64pfr0 = 0x0000000010112222ull;
251 cpu->isar.id_aa64pfr1 = 0x0000000000000010ull;
252 cpu->id_afr0 = 0x00000000;
253 cpu->isar.id_dfr0 = 0x04010088;
254 cpu->isar.id_isar0 = 0x02101110;
255 cpu->isar.id_isar1 = 0x13112111;
256 cpu->isar.id_isar2 = 0x21232042;
257 cpu->isar.id_isar3 = 0x01112131;
258 cpu->isar.id_isar4 = 0x00011142;
259 cpu->isar.id_isar5 = 0x01011121;
260 cpu->isar.id_isar6 = 0x00000010;
261 cpu->isar.id_mmfr0 = 0x10201105;
262 cpu->isar.id_mmfr1 = 0x40000000;
263 cpu->isar.id_mmfr2 = 0x01260000;
264 cpu->isar.id_mmfr3 = 0x02122211;
265 cpu->isar.id_mmfr4 = 0x00021110;
266 cpu->isar.id_pfr0 = 0x10010131;
267 cpu->isar.id_pfr1 = 0x00011011;
268 cpu->isar.id_pfr2 = 0x00000011;
269 cpu->midr = 0x412FD050; /* r2p0 */
270 cpu->revidr = 0;
271
272 /* From B2.23 CCSIDR_EL1 */
273 cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */
274 cpu->ccsidr[1] = 0x200fe01a; /* 32KB L1 icache */
275 cpu->ccsidr[2] = 0x703fe07a; /* 512KB L2 cache */
276
277 /* From B2.96 SCTLR_EL3 */
278 cpu->reset_sctlr = 0x30c50838;
279
280 /* From B4.45 ICH_VTR_EL2 */
281 cpu->gic_num_lrs = 4;
282 cpu->gic_vpribits = 5;
283 cpu->gic_vprebits = 5;
284 cpu->gic_pribits = 5;
285
286 cpu->isar.mvfr0 = 0x10110222;
287 cpu->isar.mvfr1 = 0x13211111;
288 cpu->isar.mvfr2 = 0x00000043;
289
290 /* From D5.4 AArch64 PMU register summary */
291 cpu->isar.reset_pmcr_el0 = 0x410b3000;
292 }
293
294 static void aarch64_a72_initfn(Object *obj)
295 {
296 ARMCPU *cpu = ARM_CPU(obj);
297
298 cpu->dtb_compatible = "arm,cortex-a72";
299 set_feature(&cpu->env, ARM_FEATURE_V8);
300 set_feature(&cpu->env, ARM_FEATURE_NEON);
301 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
302 set_feature(&cpu->env, ARM_FEATURE_AARCH64);
303 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
304 set_feature(&cpu->env, ARM_FEATURE_EL2);
305 set_feature(&cpu->env, ARM_FEATURE_EL3);
306 set_feature(&cpu->env, ARM_FEATURE_PMU);
307 cpu->midr = 0x410fd083;
308 cpu->revidr = 0x00000000;
309 cpu->reset_fpsid = 0x41034080;
310 cpu->isar.mvfr0 = 0x10110222;
311 cpu->isar.mvfr1 = 0x12111111;
312 cpu->isar.mvfr2 = 0x00000043;
313 cpu->ctr = 0x8444c004;
314 cpu->reset_sctlr = 0x00c50838;
315 cpu->isar.id_pfr0 = 0x00000131;
316 cpu->isar.id_pfr1 = 0x00011011;
317 cpu->isar.id_dfr0 = 0x03010066;
318 cpu->id_afr0 = 0x00000000;
319 cpu->isar.id_mmfr0 = 0x10201105;
320 cpu->isar.id_mmfr1 = 0x40000000;
321 cpu->isar.id_mmfr2 = 0x01260000;
322 cpu->isar.id_mmfr3 = 0x02102211;
323 cpu->isar.id_isar0 = 0x02101110;
324 cpu->isar.id_isar1 = 0x13112111;
325 cpu->isar.id_isar2 = 0x21232042;
326 cpu->isar.id_isar3 = 0x01112131;
327 cpu->isar.id_isar4 = 0x00011142;
328 cpu->isar.id_isar5 = 0x00011121;
329 cpu->isar.id_aa64pfr0 = 0x00002222;
330 cpu->isar.id_aa64dfr0 = 0x10305106;
331 cpu->isar.id_aa64isar0 = 0x00011120;
332 cpu->isar.id_aa64mmfr0 = 0x00001124;
333 cpu->isar.dbgdidr = 0x3516d000;
334 cpu->isar.dbgdevid = 0x01110f13;
335 cpu->isar.dbgdevid1 = 0x2;
336 cpu->isar.reset_pmcr_el0 = 0x41023000;
337 cpu->clidr = 0x0a200023;
338 cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
339 cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
340 cpu->ccsidr[2] = 0x707fe07a; /* 1MB L2 cache */
341 cpu->dcz_blocksize = 4; /* 64 bytes */
342 cpu->gic_num_lrs = 4;
343 cpu->gic_vpribits = 5;
344 cpu->gic_vprebits = 5;
345 cpu->gic_pribits = 5;
346 define_cortex_a72_a57_a53_cp_reginfo(cpu);
347 }
348
349 static void aarch64_a76_initfn(Object *obj)
350 {
351 ARMCPU *cpu = ARM_CPU(obj);
352
353 cpu->dtb_compatible = "arm,cortex-a76";
354 set_feature(&cpu->env, ARM_FEATURE_V8);
355 set_feature(&cpu->env, ARM_FEATURE_NEON);
356 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
357 set_feature(&cpu->env, ARM_FEATURE_AARCH64);
358 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
359 set_feature(&cpu->env, ARM_FEATURE_EL2);
360 set_feature(&cpu->env, ARM_FEATURE_EL3);
361 set_feature(&cpu->env, ARM_FEATURE_PMU);
362
363 /* Ordered by B2.4 AArch64 registers by functional group */
364 cpu->clidr = 0x82000023;
365 cpu->ctr = 0x8444C004;
366 cpu->dcz_blocksize = 4;
367 cpu->isar.id_aa64dfr0 = 0x0000000010305408ull;
368 cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
369 cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
370 cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull;
371 cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
372 cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
373 cpu->isar.id_aa64pfr0 = 0x1100000010111112ull; /* GIC filled in later */
374 cpu->isar.id_aa64pfr1 = 0x0000000000000010ull;
375 cpu->id_afr0 = 0x00000000;
376 cpu->isar.id_dfr0 = 0x04010088;
377 cpu->isar.id_isar0 = 0x02101110;
378 cpu->isar.id_isar1 = 0x13112111;
379 cpu->isar.id_isar2 = 0x21232042;
380 cpu->isar.id_isar3 = 0x01112131;
381 cpu->isar.id_isar4 = 0x00010142;
382 cpu->isar.id_isar5 = 0x01011121;
383 cpu->isar.id_isar6 = 0x00000010;
384 cpu->isar.id_mmfr0 = 0x10201105;
385 cpu->isar.id_mmfr1 = 0x40000000;
386 cpu->isar.id_mmfr2 = 0x01260000;
387 cpu->isar.id_mmfr3 = 0x02122211;
388 cpu->isar.id_mmfr4 = 0x00021110;
389 cpu->isar.id_pfr0 = 0x10010131;
390 cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */
391 cpu->isar.id_pfr2 = 0x00000011;
392 cpu->midr = 0x414fd0b1; /* r4p1 */
393 cpu->revidr = 0;
394
395 /* From B2.18 CCSIDR_EL1 */
396 cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */
397 cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */
398 cpu->ccsidr[2] = 0x707fe03a; /* 512KB L2 cache */
399
400 /* From B2.93 SCTLR_EL3 */
401 cpu->reset_sctlr = 0x30c50838;
402
403 /* From B4.23 ICH_VTR_EL2 */
404 cpu->gic_num_lrs = 4;
405 cpu->gic_vpribits = 5;
406 cpu->gic_vprebits = 5;
407 cpu->gic_pribits = 5;
408
409 /* From B5.1 AdvSIMD AArch64 register summary */
410 cpu->isar.mvfr0 = 0x10110222;
411 cpu->isar.mvfr1 = 0x13211111;
412 cpu->isar.mvfr2 = 0x00000043;
413
414 /* From D5.1 AArch64 PMU register summary */
415 cpu->isar.reset_pmcr_el0 = 0x410b3000;
416 }
417
418 static void aarch64_a64fx_initfn(Object *obj)
419 {
420 ARMCPU *cpu = ARM_CPU(obj);
421
422 cpu->dtb_compatible = "arm,a64fx";
423 set_feature(&cpu->env, ARM_FEATURE_V8);
424 set_feature(&cpu->env, ARM_FEATURE_NEON);
425 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
426 set_feature(&cpu->env, ARM_FEATURE_AARCH64);
427 set_feature(&cpu->env, ARM_FEATURE_EL2);
428 set_feature(&cpu->env, ARM_FEATURE_EL3);
429 set_feature(&cpu->env, ARM_FEATURE_PMU);
430 cpu->midr = 0x461f0010;
431 cpu->revidr = 0x00000000;
432 cpu->ctr = 0x86668006;
433 cpu->reset_sctlr = 0x30000180;
434 cpu->isar.id_aa64pfr0 = 0x0000000101111111; /* No RAS Extensions */
435 cpu->isar.id_aa64pfr1 = 0x0000000000000000;
436 cpu->isar.id_aa64dfr0 = 0x0000000010305408;
437 cpu->isar.id_aa64dfr1 = 0x0000000000000000;
438 cpu->id_aa64afr0 = 0x0000000000000000;
439 cpu->id_aa64afr1 = 0x0000000000000000;
440 cpu->isar.id_aa64mmfr0 = 0x0000000000001122;
441 cpu->isar.id_aa64mmfr1 = 0x0000000011212100;
442 cpu->isar.id_aa64mmfr2 = 0x0000000000001011;
443 cpu->isar.id_aa64isar0 = 0x0000000010211120;
444 cpu->isar.id_aa64isar1 = 0x0000000000010001;
445 cpu->isar.id_aa64zfr0 = 0x0000000000000000;
446 cpu->clidr = 0x0000000080000023;
447 cpu->ccsidr[0] = 0x7007e01c; /* 64KB L1 dcache */
448 cpu->ccsidr[1] = 0x2007e01c; /* 64KB L1 icache */
449 cpu->ccsidr[2] = 0x70ffe07c; /* 8MB L2 cache */
450 cpu->dcz_blocksize = 6; /* 256 bytes */
451 cpu->gic_num_lrs = 4;
452 cpu->gic_vpribits = 5;
453 cpu->gic_vprebits = 5;
454 cpu->gic_pribits = 5;
455
456 /* The A64FX supports only 128, 256 and 512 bit vector lengths */
457 aarch64_add_sve_properties(obj);
458 cpu->sve_vq.supported = (1 << 0) /* 128bit */
459 | (1 << 1) /* 256bit */
460 | (1 << 3); /* 512bit */
461
462 cpu->isar.reset_pmcr_el0 = 0x46014040;
463
464 /* TODO: Add A64FX specific HPC extension registers */
465 }
466
467 static CPAccessResult access_actlr_w(CPUARMState *env, const ARMCPRegInfo *r,
468 bool read)
469 {
470 if (!read) {
471 int el = arm_current_el(env);
472
473 /* Because ACTLR_EL2 is constant 0, writes below EL2 trap to EL2. */
474 if (el < 2 && arm_is_el2_enabled(env)) {
475 return CP_ACCESS_TRAP_EL2;
476 }
477 /* Because ACTLR_EL3 is constant 0, writes below EL3 trap to EL3. */
478 if (el < 3 && arm_feature(env, ARM_FEATURE_EL3)) {
479 return CP_ACCESS_TRAP_EL3;
480 }
481 }
482 return CP_ACCESS_OK;
483 }
484
485 static const ARMCPRegInfo neoverse_n1_cp_reginfo[] = {
486 { .name = "ATCR_EL1", .state = ARM_CP_STATE_AA64,
487 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 7, .opc2 = 0,
488 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
489 /* Traps and enables are the same as for TCR_EL1. */
490 .accessfn = access_tvm_trvm, .fgt = FGT_TCR_EL1, },
491 { .name = "ATCR_EL2", .state = ARM_CP_STATE_AA64,
492 .opc0 = 3, .opc1 = 4, .crn = 15, .crm = 7, .opc2 = 0,
493 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
494 { .name = "ATCR_EL3", .state = ARM_CP_STATE_AA64,
495 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 7, .opc2 = 0,
496 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
497 { .name = "ATCR_EL12", .state = ARM_CP_STATE_AA64,
498 .opc0 = 3, .opc1 = 5, .crn = 15, .crm = 7, .opc2 = 0,
499 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
500 { .name = "AVTCR_EL2", .state = ARM_CP_STATE_AA64,
501 .opc0 = 3, .opc1 = 4, .crn = 15, .crm = 7, .opc2 = 1,
502 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
503 { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64,
504 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 0,
505 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
506 .accessfn = access_actlr_w },
507 { .name = "CPUACTLR2_EL1", .state = ARM_CP_STATE_AA64,
508 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 1,
509 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
510 .accessfn = access_actlr_w },
511 { .name = "CPUACTLR3_EL1", .state = ARM_CP_STATE_AA64,
512 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 2,
513 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
514 .accessfn = access_actlr_w },
515 /*
516 * Report CPUCFR_EL1.SCU as 1, as we do not implement the DSU
517 * (and in particular its system registers).
518 */
519 { .name = "CPUCFR_EL1", .state = ARM_CP_STATE_AA64,
520 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 0, .opc2 = 0,
521 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 4 },
522 { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64,
523 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 4,
524 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0x961563010,
525 .accessfn = access_actlr_w },
526 { .name = "CPUPCR_EL3", .state = ARM_CP_STATE_AA64,
527 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 1,
528 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
529 { .name = "CPUPMR_EL3", .state = ARM_CP_STATE_AA64,
530 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 3,
531 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
532 { .name = "CPUPOR_EL3", .state = ARM_CP_STATE_AA64,
533 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 2,
534 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
535 { .name = "CPUPSELR_EL3", .state = ARM_CP_STATE_AA64,
536 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 0,
537 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
538 { .name = "CPUPWRCTLR_EL1", .state = ARM_CP_STATE_AA64,
539 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 7,
540 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
541 .accessfn = access_actlr_w },
542 { .name = "ERXPFGCDN_EL1", .state = ARM_CP_STATE_AA64,
543 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 2,
544 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
545 .accessfn = access_actlr_w },
546 { .name = "ERXPFGCTL_EL1", .state = ARM_CP_STATE_AA64,
547 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 1,
548 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
549 .accessfn = access_actlr_w },
550 { .name = "ERXPFGF_EL1", .state = ARM_CP_STATE_AA64,
551 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 0,
552 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
553 .accessfn = access_actlr_w },
554 };
555
556 static void define_neoverse_n1_cp_reginfo(ARMCPU *cpu)
557 {
558 define_arm_cp_regs(cpu, neoverse_n1_cp_reginfo);
559 }
560
561 static const ARMCPRegInfo neoverse_v1_cp_reginfo[] = {
562 { .name = "CPUECTLR2_EL1", .state = ARM_CP_STATE_AA64,
563 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 5,
564 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
565 .accessfn = access_actlr_w },
566 { .name = "CPUPPMCR_EL3", .state = ARM_CP_STATE_AA64,
567 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 2, .opc2 = 0,
568 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
569 { .name = "CPUPPMCR2_EL3", .state = ARM_CP_STATE_AA64,
570 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 2, .opc2 = 1,
571 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
572 { .name = "CPUPPMCR3_EL3", .state = ARM_CP_STATE_AA64,
573 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 2, .opc2 = 6,
574 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
575 };
576
577 static void define_neoverse_v1_cp_reginfo(ARMCPU *cpu)
578 {
579 /*
580 * The Neoverse V1 has all of the Neoverse N1's IMPDEF
581 * registers and a few more of its own.
582 */
583 define_arm_cp_regs(cpu, neoverse_n1_cp_reginfo);
584 define_arm_cp_regs(cpu, neoverse_v1_cp_reginfo);
585 }
586
587 static void aarch64_neoverse_n1_initfn(Object *obj)
588 {
589 ARMCPU *cpu = ARM_CPU(obj);
590
591 cpu->dtb_compatible = "arm,neoverse-n1";
592 set_feature(&cpu->env, ARM_FEATURE_V8);
593 set_feature(&cpu->env, ARM_FEATURE_NEON);
594 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
595 set_feature(&cpu->env, ARM_FEATURE_AARCH64);
596 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
597 set_feature(&cpu->env, ARM_FEATURE_EL2);
598 set_feature(&cpu->env, ARM_FEATURE_EL3);
599 set_feature(&cpu->env, ARM_FEATURE_PMU);
600
601 /* Ordered by B2.4 AArch64 registers by functional group */
602 cpu->clidr = 0x82000023;
603 cpu->ctr = 0x8444c004;
604 cpu->dcz_blocksize = 4;
605 cpu->isar.id_aa64dfr0 = 0x0000000110305408ull;
606 cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
607 cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
608 cpu->isar.id_aa64mmfr0 = 0x0000000000101125ull;
609 cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
610 cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
611 cpu->isar.id_aa64pfr0 = 0x1100000010111112ull; /* GIC filled in later */
612 cpu->isar.id_aa64pfr1 = 0x0000000000000020ull;
613 cpu->id_afr0 = 0x00000000;
614 cpu->isar.id_dfr0 = 0x04010088;
615 cpu->isar.id_isar0 = 0x02101110;
616 cpu->isar.id_isar1 = 0x13112111;
617 cpu->isar.id_isar2 = 0x21232042;
618 cpu->isar.id_isar3 = 0x01112131;
619 cpu->isar.id_isar4 = 0x00010142;
620 cpu->isar.id_isar5 = 0x01011121;
621 cpu->isar.id_isar6 = 0x00000010;
622 cpu->isar.id_mmfr0 = 0x10201105;
623 cpu->isar.id_mmfr1 = 0x40000000;
624 cpu->isar.id_mmfr2 = 0x01260000;
625 cpu->isar.id_mmfr3 = 0x02122211;
626 cpu->isar.id_mmfr4 = 0x00021110;
627 cpu->isar.id_pfr0 = 0x10010131;
628 cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */
629 cpu->isar.id_pfr2 = 0x00000011;
630 cpu->midr = 0x414fd0c1; /* r4p1 */
631 cpu->revidr = 0;
632
633 /* From B2.23 CCSIDR_EL1 */
634 cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */
635 cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */
636 cpu->ccsidr[2] = 0x70ffe03a; /* 1MB L2 cache */
637
638 /* From B2.98 SCTLR_EL3 */
639 cpu->reset_sctlr = 0x30c50838;
640
641 /* From B4.23 ICH_VTR_EL2 */
642 cpu->gic_num_lrs = 4;
643 cpu->gic_vpribits = 5;
644 cpu->gic_vprebits = 5;
645 cpu->gic_pribits = 5;
646
647 /* From B5.1 AdvSIMD AArch64 register summary */
648 cpu->isar.mvfr0 = 0x10110222;
649 cpu->isar.mvfr1 = 0x13211111;
650 cpu->isar.mvfr2 = 0x00000043;
651
652 /* From D5.1 AArch64 PMU register summary */
653 cpu->isar.reset_pmcr_el0 = 0x410c3000;
654
655 define_neoverse_n1_cp_reginfo(cpu);
656 }
657
658 static void aarch64_neoverse_v1_initfn(Object *obj)
659 {
660 ARMCPU *cpu = ARM_CPU(obj);
661
662 cpu->dtb_compatible = "arm,neoverse-v1";
663 set_feature(&cpu->env, ARM_FEATURE_V8);
664 set_feature(&cpu->env, ARM_FEATURE_NEON);
665 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
666 set_feature(&cpu->env, ARM_FEATURE_AARCH64);
667 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
668 set_feature(&cpu->env, ARM_FEATURE_EL2);
669 set_feature(&cpu->env, ARM_FEATURE_EL3);
670 set_feature(&cpu->env, ARM_FEATURE_PMU);
671
672 /* Ordered by 3.2.4 AArch64 registers by functional group */
673 cpu->clidr = 0x82000023;
674 cpu->ctr = 0xb444c004; /* With DIC and IDC set */
675 cpu->dcz_blocksize = 4;
676 cpu->id_aa64afr0 = 0x00000000;
677 cpu->id_aa64afr1 = 0x00000000;
678 cpu->isar.id_aa64dfr0 = 0x000001f210305519ull;
679 cpu->isar.id_aa64dfr1 = 0x00000000;
680 cpu->isar.id_aa64isar0 = 0x1011111110212120ull; /* with FEAT_RNG */
681 cpu->isar.id_aa64isar1 = 0x0111000001211032ull;
682 cpu->isar.id_aa64mmfr0 = 0x0000000000101125ull;
683 cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
684 cpu->isar.id_aa64mmfr2 = 0x0220011102101011ull;
685 cpu->isar.id_aa64pfr0 = 0x1101110120111112ull; /* GIC filled in later */
686 cpu->isar.id_aa64pfr1 = 0x0000000000000020ull;
687 cpu->id_afr0 = 0x00000000;
688 cpu->isar.id_dfr0 = 0x15011099;
689 cpu->isar.id_isar0 = 0x02101110;
690 cpu->isar.id_isar1 = 0x13112111;
691 cpu->isar.id_isar2 = 0x21232042;
692 cpu->isar.id_isar3 = 0x01112131;
693 cpu->isar.id_isar4 = 0x00010142;
694 cpu->isar.id_isar5 = 0x11011121;
695 cpu->isar.id_isar6 = 0x01100111;
696 cpu->isar.id_mmfr0 = 0x10201105;
697 cpu->isar.id_mmfr1 = 0x40000000;
698 cpu->isar.id_mmfr2 = 0x01260000;
699 cpu->isar.id_mmfr3 = 0x02122211;
700 cpu->isar.id_mmfr4 = 0x01021110;
701 cpu->isar.id_pfr0 = 0x21110131;
702 cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */
703 cpu->isar.id_pfr2 = 0x00000011;
704 cpu->midr = 0x411FD402; /* r1p2 */
705 cpu->revidr = 0;
706
707 /*
708 * The Neoverse-V1 r1p2 TRM lists 32-bit format CCSIDR_EL1 values,
709 * but also says it implements CCIDX, which means they should be
710 * 64-bit format. So we here use values which are based on the textual
711 * information in chapter 2 of the TRM:
712 *
713 * L1: 4-way set associative 64-byte line size, total size 64K.
714 * L2: 8-way set associative, 64 byte line size, either 512K or 1MB.
715 * L3: No L3 (this matches the CLIDR_EL1 value).
716 */
717 cpu->ccsidr[0] = make_ccsidr64(4, 64, 64 * KiB); /* L1 dcache */
718 cpu->ccsidr[1] = cpu->ccsidr[0]; /* L1 icache */
719 cpu->ccsidr[2] = make_ccsidr64(8, 64, 1 * MiB); /* L2 cache */
720
721 /* From 3.2.115 SCTLR_EL3 */
722 cpu->reset_sctlr = 0x30c50838;
723
724 /* From 3.4.8 ICC_CTLR_EL3 and 3.4.23 ICH_VTR_EL2 */
725 cpu->gic_num_lrs = 4;
726 cpu->gic_vpribits = 5;
727 cpu->gic_vprebits = 5;
728 cpu->gic_pribits = 5;
729
730 /* From 3.5.1 AdvSIMD AArch64 register summary */
731 cpu->isar.mvfr0 = 0x10110222;
732 cpu->isar.mvfr1 = 0x13211111;
733 cpu->isar.mvfr2 = 0x00000043;
734
735 /* From 3.7.5 ID_AA64ZFR0_EL1 */
736 cpu->isar.id_aa64zfr0 = 0x0000100000100000;
737 cpu->sve_vq.supported = (1 << 0) /* 128bit */
738 | (1 << 1); /* 256bit */
739
740 /* From 5.5.1 AArch64 PMU register summary */
741 cpu->isar.reset_pmcr_el0 = 0x41213000;
742
743 define_neoverse_v1_cp_reginfo(cpu);
744
745 aarch64_add_pauth_properties(obj);
746 aarch64_add_sve_properties(obj);
747 }
748
749 static const ARMCPRegInfo cortex_a710_cp_reginfo[] = {
750 { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64,
751 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 0,
752 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
753 .accessfn = access_actlr_w },
754 { .name = "CPUACTLR2_EL1", .state = ARM_CP_STATE_AA64,
755 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 1,
756 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
757 .accessfn = access_actlr_w },
758 { .name = "CPUACTLR3_EL1", .state = ARM_CP_STATE_AA64,
759 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 2,
760 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
761 .accessfn = access_actlr_w },
762 { .name = "CPUACTLR4_EL1", .state = ARM_CP_STATE_AA64,
763 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 3,
764 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
765 .accessfn = access_actlr_w },
766 { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64,
767 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 4,
768 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
769 .accessfn = access_actlr_w },
770 { .name = "CPUECTLR2_EL1", .state = ARM_CP_STATE_AA64,
771 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 5,
772 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
773 .accessfn = access_actlr_w },
774 { .name = "CPUPPMCR_EL3", .state = ARM_CP_STATE_AA64,
775 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 4,
776 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
777 { .name = "CPUPWRCTLR_EL1", .state = ARM_CP_STATE_AA64,
778 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 7,
779 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
780 .accessfn = access_actlr_w },
781 { .name = "ATCR_EL1", .state = ARM_CP_STATE_AA64,
782 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 7, .opc2 = 0,
783 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
784 { .name = "CPUACTLR5_EL1", .state = ARM_CP_STATE_AA64,
785 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 8, .opc2 = 0,
786 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
787 .accessfn = access_actlr_w },
788 { .name = "CPUACTLR6_EL1", .state = ARM_CP_STATE_AA64,
789 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 8, .opc2 = 1,
790 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
791 .accessfn = access_actlr_w },
792 { .name = "CPUACTLR7_EL1", .state = ARM_CP_STATE_AA64,
793 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 8, .opc2 = 2,
794 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
795 .accessfn = access_actlr_w },
796 { .name = "ATCR_EL2", .state = ARM_CP_STATE_AA64,
797 .opc0 = 3, .opc1 = 4, .crn = 15, .crm = 7, .opc2 = 0,
798 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
799 { .name = "AVTCR_EL2", .state = ARM_CP_STATE_AA64,
800 .opc0 = 3, .opc1 = 4, .crn = 15, .crm = 7, .opc2 = 1,
801 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
802 { .name = "CPUPPMCR_EL3", .state = ARM_CP_STATE_AA64,
803 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 2, .opc2 = 0,
804 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
805 { .name = "CPUPPMCR2_EL3", .state = ARM_CP_STATE_AA64,
806 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 2, .opc2 = 1,
807 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
808 { .name = "CPUPPMCR4_EL3", .state = ARM_CP_STATE_AA64,
809 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 2, .opc2 = 4,
810 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
811 { .name = "CPUPPMCR5_EL3", .state = ARM_CP_STATE_AA64,
812 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 2, .opc2 = 5,
813 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
814 { .name = "CPUPPMCR6_EL3", .state = ARM_CP_STATE_AA64,
815 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 2, .opc2 = 6,
816 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
817 { .name = "CPUACTLR_EL3", .state = ARM_CP_STATE_AA64,
818 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 4, .opc2 = 0,
819 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
820 { .name = "ATCR_EL3", .state = ARM_CP_STATE_AA64,
821 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 7, .opc2 = 0,
822 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
823 { .name = "CPUPSELR_EL3", .state = ARM_CP_STATE_AA64,
824 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 0,
825 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
826 { .name = "CPUPCR_EL3", .state = ARM_CP_STATE_AA64,
827 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 1,
828 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
829 { .name = "CPUPOR_EL3", .state = ARM_CP_STATE_AA64,
830 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 2,
831 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
832 { .name = "CPUPMR_EL3", .state = ARM_CP_STATE_AA64,
833 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 3,
834 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
835 { .name = "CPUPOR2_EL3", .state = ARM_CP_STATE_AA64,
836 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 4,
837 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
838 { .name = "CPUPMR2_EL3", .state = ARM_CP_STATE_AA64,
839 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 5,
840 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
841 { .name = "CPUPFR_EL3", .state = ARM_CP_STATE_AA64,
842 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 6,
843 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
844 /*
845 * Report CPUCFR_EL1.SCU as 1, as we do not implement the DSU
846 * (and in particular its system registers).
847 */
848 { .name = "CPUCFR_EL1", .state = ARM_CP_STATE_AA64,
849 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 0, .opc2 = 0,
850 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 4 },
851
852 /*
853 * Stub RAMINDEX, as we don't actually implement caches, BTB,
854 * or anything else with cpu internal memory.
855 * "Read" zeros into the IDATA* and DDATA* output registers.
856 */
857 { .name = "RAMINDEX_EL3", .state = ARM_CP_STATE_AA64,
858 .opc0 = 1, .opc1 = 6, .crn = 15, .crm = 0, .opc2 = 0,
859 .access = PL3_W, .type = ARM_CP_CONST, .resetvalue = 0 },
860 { .name = "IDATA0_EL3", .state = ARM_CP_STATE_AA64,
861 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 0, .opc2 = 0,
862 .access = PL3_R, .type = ARM_CP_CONST, .resetvalue = 0 },
863 { .name = "IDATA1_EL3", .state = ARM_CP_STATE_AA64,
864 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 0, .opc2 = 1,
865 .access = PL3_R, .type = ARM_CP_CONST, .resetvalue = 0 },
866 { .name = "IDATA2_EL3", .state = ARM_CP_STATE_AA64,
867 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 0, .opc2 = 2,
868 .access = PL3_R, .type = ARM_CP_CONST, .resetvalue = 0 },
869 { .name = "DDATA0_EL3", .state = ARM_CP_STATE_AA64,
870 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 1, .opc2 = 0,
871 .access = PL3_R, .type = ARM_CP_CONST, .resetvalue = 0 },
872 { .name = "DDATA1_EL3", .state = ARM_CP_STATE_AA64,
873 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 1, .opc2 = 1,
874 .access = PL3_R, .type = ARM_CP_CONST, .resetvalue = 0 },
875 { .name = "DDATA2_EL3", .state = ARM_CP_STATE_AA64,
876 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 1, .opc2 = 2,
877 .access = PL3_R, .type = ARM_CP_CONST, .resetvalue = 0 },
878 };
879
880 static void aarch64_a710_initfn(Object *obj)
881 {
882 ARMCPU *cpu = ARM_CPU(obj);
883
884 cpu->dtb_compatible = "arm,cortex-a710";
885 set_feature(&cpu->env, ARM_FEATURE_V8);
886 set_feature(&cpu->env, ARM_FEATURE_NEON);
887 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
888 set_feature(&cpu->env, ARM_FEATURE_AARCH64);
889 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
890 set_feature(&cpu->env, ARM_FEATURE_EL2);
891 set_feature(&cpu->env, ARM_FEATURE_EL3);
892 set_feature(&cpu->env, ARM_FEATURE_PMU);
893
894 /* Ordered by Section B.4: AArch64 registers */
895 cpu->midr = 0x412FD471; /* r2p1 */
896 cpu->revidr = 0;
897 cpu->isar.id_pfr0 = 0x21110131;
898 cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */
899 cpu->isar.id_dfr0 = 0x16011099;
900 cpu->id_afr0 = 0;
901 cpu->isar.id_mmfr0 = 0x10201105;
902 cpu->isar.id_mmfr1 = 0x40000000;
903 cpu->isar.id_mmfr2 = 0x01260000;
904 cpu->isar.id_mmfr3 = 0x02122211;
905 cpu->isar.id_isar0 = 0x02101110;
906 cpu->isar.id_isar1 = 0x13112111;
907 cpu->isar.id_isar2 = 0x21232042;
908 cpu->isar.id_isar3 = 0x01112131;
909 cpu->isar.id_isar4 = 0x00010142;
910 cpu->isar.id_isar5 = 0x11011121; /* with Crypto */
911 cpu->isar.id_mmfr4 = 0x21021110;
912 cpu->isar.id_isar6 = 0x01111111;
913 cpu->isar.mvfr0 = 0x10110222;
914 cpu->isar.mvfr1 = 0x13211111;
915 cpu->isar.mvfr2 = 0x00000043;
916 cpu->isar.id_pfr2 = 0x00000011;
917 cpu->isar.id_aa64pfr0 = 0x1201111120111112ull; /* GIC filled in later */
918 cpu->isar.id_aa64pfr1 = 0x0000000000000221ull;
919 cpu->isar.id_aa64zfr0 = 0x0000110100110021ull; /* with Crypto */
920 cpu->isar.id_aa64dfr0 = 0x000011f010305619ull;
921 cpu->isar.id_aa64dfr1 = 0;
922 cpu->id_aa64afr0 = 0;
923 cpu->id_aa64afr1 = 0;
924 cpu->isar.id_aa64isar0 = 0x0221111110212120ull; /* with Crypto */
925 cpu->isar.id_aa64isar1 = 0x0010111101211052ull;
926 cpu->isar.id_aa64mmfr0 = 0x0000022200101122ull;
927 cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
928 cpu->isar.id_aa64mmfr2 = 0x1221011110101011ull;
929 cpu->clidr = 0x0000001482000023ull;
930 cpu->gm_blocksize = 4;
931 cpu->ctr = 0x000000049444c004ull;
932 cpu->dcz_blocksize = 4;
933 /* TODO FEAT_MPAM: mpamidr_el1 = 0x0000_0001_0006_003f */
934
935 /* Section B.5.2: PMCR_EL0 */
936 cpu->isar.reset_pmcr_el0 = 0xa000; /* with 20 counters */
937
938 /* Section B.6.7: ICH_VTR_EL2 */
939 cpu->gic_num_lrs = 4;
940 cpu->gic_vpribits = 5;
941 cpu->gic_vprebits = 5;
942 cpu->gic_pribits = 5;
943
944 /* Section 14: Scalable Vector Extensions support */
945 cpu->sve_vq.supported = 1 << 0; /* 128bit */
946
947 /*
948 * The cortex-a710 TRM does not list CCSIDR values. The layout of
949 * the caches are in text in Table 7-1, Table 8-1, and Table 9-1.
950 *
951 * L1: 4-way set associative 64-byte line size, total either 32K or 64K.
952 * L2: 8-way set associative 64 byte line size, total either 256K or 512K.
953 */
954 cpu->ccsidr[0] = make_ccsidr64(4, 64, 64 * KiB); /* L1 dcache */
955 cpu->ccsidr[1] = cpu->ccsidr[0]; /* L1 icache */
956 cpu->ccsidr[2] = make_ccsidr64(8, 64, 512 * KiB); /* L2 cache */
957
958 /* FIXME: Not documented -- copied from neoverse-v1 */
959 cpu->reset_sctlr = 0x30c50838;
960
961 define_arm_cp_regs(cpu, cortex_a710_cp_reginfo);
962
963 aarch64_add_pauth_properties(obj);
964 aarch64_add_sve_properties(obj);
965 }
966
967 /* Extra IMPDEF regs in the N2 beyond those in the A710 */
968 static const ARMCPRegInfo neoverse_n2_cp_reginfo[] = {
969 { .name = "CPURNDBR_EL3", .state = ARM_CP_STATE_AA64,
970 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 3, .opc2 = 0,
971 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
972 { .name = "CPURNDPEID_EL3", .state = ARM_CP_STATE_AA64,
973 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 3, .opc2 = 1,
974 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
975 };
976
977 static void aarch64_neoverse_n2_initfn(Object *obj)
978 {
979 ARMCPU *cpu = ARM_CPU(obj);
980
981 cpu->dtb_compatible = "arm,neoverse-n2";
982 set_feature(&cpu->env, ARM_FEATURE_V8);
983 set_feature(&cpu->env, ARM_FEATURE_NEON);
984 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
985 set_feature(&cpu->env, ARM_FEATURE_AARCH64);
986 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
987 set_feature(&cpu->env, ARM_FEATURE_EL2);
988 set_feature(&cpu->env, ARM_FEATURE_EL3);
989 set_feature(&cpu->env, ARM_FEATURE_PMU);
990
991 /* Ordered by Section B.5: AArch64 ID registers */
992 cpu->midr = 0x410FD493; /* r0p3 */
993 cpu->revidr = 0;
994 cpu->isar.id_pfr0 = 0x21110131;
995 cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */
996 cpu->isar.id_dfr0 = 0x16011099;
997 cpu->id_afr0 = 0;
998 cpu->isar.id_mmfr0 = 0x10201105;
999 cpu->isar.id_mmfr1 = 0x40000000;
1000 cpu->isar.id_mmfr2 = 0x01260000;
1001 cpu->isar.id_mmfr3 = 0x02122211;
1002 cpu->isar.id_isar0 = 0x02101110;
1003 cpu->isar.id_isar1 = 0x13112111;
1004 cpu->isar.id_isar2 = 0x21232042;
1005 cpu->isar.id_isar3 = 0x01112131;
1006 cpu->isar.id_isar4 = 0x00010142;
1007 cpu->isar.id_isar5 = 0x11011121; /* with Crypto */
1008 cpu->isar.id_mmfr4 = 0x01021110;
1009 cpu->isar.id_isar6 = 0x01111111;
1010 cpu->isar.mvfr0 = 0x10110222;
1011 cpu->isar.mvfr1 = 0x13211111;
1012 cpu->isar.mvfr2 = 0x00000043;
1013 cpu->isar.id_pfr2 = 0x00000011;
1014 cpu->isar.id_aa64pfr0 = 0x1201111120111112ull; /* GIC filled in later */
1015 cpu->isar.id_aa64pfr1 = 0x0000000000000221ull;
1016 cpu->isar.id_aa64zfr0 = 0x0000110100110021ull; /* with Crypto */
1017 cpu->isar.id_aa64dfr0 = 0x000011f210305619ull;
1018 cpu->isar.id_aa64dfr1 = 0;
1019 cpu->id_aa64afr0 = 0;
1020 cpu->id_aa64afr1 = 0;
1021 cpu->isar.id_aa64isar0 = 0x1221111110212120ull; /* with Crypto and FEAT_RNG */
1022 cpu->isar.id_aa64isar1 = 0x0011111101211052ull;
1023 cpu->isar.id_aa64mmfr0 = 0x0000022200101125ull;
1024 cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
1025 cpu->isar.id_aa64mmfr2 = 0x1221011112101011ull;
1026 cpu->clidr = 0x0000001482000023ull;
1027 cpu->gm_blocksize = 4;
1028 cpu->ctr = 0x00000004b444c004ull;
1029 cpu->dcz_blocksize = 4;
1030 /* TODO FEAT_MPAM: mpamidr_el1 = 0x0000_0001_001e_01ff */
1031
1032 /* Section B.7.2: PMCR_EL0 */
1033 cpu->isar.reset_pmcr_el0 = 0x3000; /* with 6 counters */
1034
1035 /* Section B.8.9: ICH_VTR_EL2 */
1036 cpu->gic_num_lrs = 4;
1037 cpu->gic_vpribits = 5;
1038 cpu->gic_vprebits = 5;
1039 cpu->gic_pribits = 5;
1040
1041 /* Section 14: Scalable Vector Extensions support */
1042 cpu->sve_vq.supported = 1 << 0; /* 128bit */
1043
1044 /*
1045 * The Neoverse N2 TRM does not list CCSIDR values. The layout of
1046 * the caches are in text in Table 7-1, Table 8-1, and Table 9-1.
1047 *
1048 * L1: 4-way set associative 64-byte line size, total 64K.
1049 * L2: 8-way set associative 64 byte line size, total either 512K or 1024K.
1050 */
1051 cpu->ccsidr[0] = make_ccsidr64(4, 64, 64 * KiB); /* L1 dcache */
1052 cpu->ccsidr[1] = cpu->ccsidr[0]; /* L1 icache */
1053 cpu->ccsidr[2] = make_ccsidr64(8, 64, 512 * KiB); /* L2 cache */
1054
1055 /* FIXME: Not documented -- copied from neoverse-v1 */
1056 cpu->reset_sctlr = 0x30c50838;
1057
1058 /*
1059 * The Neoverse N2 has all of the Cortex-A710 IMPDEF registers,
1060 * and a few more RNG related ones.
1061 */
1062 define_arm_cp_regs(cpu, cortex_a710_cp_reginfo);
1063 define_arm_cp_regs(cpu, neoverse_n2_cp_reginfo);
1064
1065 aarch64_add_pauth_properties(obj);
1066 aarch64_add_sve_properties(obj);
1067 }
1068
1069 /*
1070 * -cpu max: a CPU with as many features enabled as our emulation supports.
1071 * The version of '-cpu max' for qemu-system-arm is defined in cpu32.c;
1072 * this only needs to handle 64 bits.
1073 */
1074 void aarch64_max_tcg_initfn(Object *obj)
1075 {
1076 ARMCPU *cpu = ARM_CPU(obj);
1077 uint64_t t;
1078 uint32_t u;
1079
1080 /*
1081 * Reset MIDR so the guest doesn't mistake our 'max' CPU type for a real
1082 * one and try to apply errata workarounds or use impdef features we
1083 * don't provide.
1084 * An IMPLEMENTER field of 0 means "reserved for software use";
1085 * ARCHITECTURE must be 0xf indicating "v7 or later, check ID registers
1086 * to see which features are present";
1087 * the VARIANT, PARTNUM and REVISION fields are all implementation
1088 * defined and we choose to define PARTNUM just in case guest
1089 * code needs to distinguish this QEMU CPU from other software
1090 * implementations, though this shouldn't be needed.
1091 */
1092 t = FIELD_DP64(0, MIDR_EL1, IMPLEMENTER, 0);
1093 t = FIELD_DP64(t, MIDR_EL1, ARCHITECTURE, 0xf);
1094 t = FIELD_DP64(t, MIDR_EL1, PARTNUM, 'Q');
1095 t = FIELD_DP64(t, MIDR_EL1, VARIANT, 0);
1096 t = FIELD_DP64(t, MIDR_EL1, REVISION, 0);
1097 cpu->midr = t;
1098
1099 /*
1100 * We're going to set FEAT_S2FWB, which mandates that CLIDR_EL1.{LoUU,LoUIS}
1101 * are zero.
1102 */
1103 u = cpu->clidr;
1104 u = FIELD_DP32(u, CLIDR_EL1, LOUIS, 0);
1105 u = FIELD_DP32(u, CLIDR_EL1, LOUU, 0);
1106 cpu->clidr = u;
1107
1108 /*
1109 * Set CTR_EL0.DIC and IDC to tell the guest it doesnt' need to
1110 * do any cache maintenance for data-to-instruction or
1111 * instruction-to-guest coherence. (Our cache ops are nops.)
1112 */
1113 t = cpu->ctr;
1114 t = FIELD_DP64(t, CTR_EL0, IDC, 1);
1115 t = FIELD_DP64(t, CTR_EL0, DIC, 1);
1116 cpu->ctr = t;
1117
1118 t = cpu->isar.id_aa64isar0;
1119 t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* FEAT_PMULL */
1120 t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1); /* FEAT_SHA1 */
1121 t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* FEAT_SHA512 */
1122 t = FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1); /* FEAT_CRC32 */
1123 t = FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2); /* FEAT_LSE */
1124 t = FIELD_DP64(t, ID_AA64ISAR0, RDM, 1); /* FEAT_RDM */
1125 t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1); /* FEAT_SHA3 */
1126 t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 1); /* FEAT_SM3 */
1127 t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1); /* FEAT_SM4 */
1128 t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1); /* FEAT_DotProd */
1129 t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1); /* FEAT_FHM */
1130 t = FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* FEAT_FlagM2 */
1131 t = FIELD_DP64(t, ID_AA64ISAR0, TLB, 2); /* FEAT_TLBIRANGE */
1132 t = FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1); /* FEAT_RNG */
1133 cpu->isar.id_aa64isar0 = t;
1134
1135 t = cpu->isar.id_aa64isar1;
1136 t = FIELD_DP64(t, ID_AA64ISAR1, DPB, 2); /* FEAT_DPB2 */
1137 t = FIELD_DP64(t, ID_AA64ISAR1, APA, PauthFeat_FPACCOMBINED);
1138 t = FIELD_DP64(t, ID_AA64ISAR1, API, 1);
1139 t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1); /* FEAT_JSCVT */
1140 t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1); /* FEAT_FCMA */
1141 t = FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2); /* FEAT_LRCPC2 */
1142 t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1); /* FEAT_FRINTTS */
1143 t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1); /* FEAT_SB */
1144 t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); /* FEAT_SPECRES */
1145 t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 1); /* FEAT_BF16 */
1146 t = FIELD_DP64(t, ID_AA64ISAR1, DGH, 1); /* FEAT_DGH */
1147 t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); /* FEAT_I8MM */
1148 cpu->isar.id_aa64isar1 = t;
1149
1150 t = cpu->isar.id_aa64isar2;
1151 t = FIELD_DP64(t, ID_AA64ISAR2, MOPS, 1); /* FEAT_MOPS */
1152 t = FIELD_DP64(t, ID_AA64ISAR2, BC, 1); /* FEAT_HBC */
1153 cpu->isar.id_aa64isar2 = t;
1154
1155 t = cpu->isar.id_aa64pfr0;
1156 t = FIELD_DP64(t, ID_AA64PFR0, FP, 1); /* FEAT_FP16 */
1157 t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); /* FEAT_FP16 */
1158 t = FIELD_DP64(t, ID_AA64PFR0, RAS, 2); /* FEAT_RASv1p1 + FEAT_DoubleFault */
1159 t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
1160 t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */
1161 t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */
1162 t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 2); /* FEAT_CSV2_2 */
1163 t = FIELD_DP64(t, ID_AA64PFR0, CSV3, 1); /* FEAT_CSV3 */
1164 cpu->isar.id_aa64pfr0 = t;
1165
1166 t = cpu->isar.id_aa64pfr1;
1167 t = FIELD_DP64(t, ID_AA64PFR1, BT, 1); /* FEAT_BTI */
1168 t = FIELD_DP64(t, ID_AA64PFR1, SSBS, 2); /* FEAT_SSBS2 */
1169 /*
1170 * Begin with full support for MTE. This will be downgraded to MTE=0
1171 * during realize if the board provides no tag memory, much like
1172 * we do for EL2 with the virtualization=on property.
1173 */
1174 t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3); /* FEAT_MTE3 */
1175 t = FIELD_DP64(t, ID_AA64PFR1, RAS_FRAC, 0); /* FEAT_RASv1p1 + FEAT_DoubleFault */
1176 t = FIELD_DP64(t, ID_AA64PFR1, SME, 1); /* FEAT_SME */
1177 t = FIELD_DP64(t, ID_AA64PFR1, CSV2_FRAC, 0); /* FEAT_CSV2_2 */
1178 cpu->isar.id_aa64pfr1 = t;
1179
1180 t = cpu->isar.id_aa64mmfr0;
1181 t = FIELD_DP64(t, ID_AA64MMFR0, PARANGE, 6); /* FEAT_LPA: 52 bits */
1182 t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16, 1); /* 16k pages supported */
1183 t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16_2, 2); /* 16k stage2 supported */
1184 t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN64_2, 2); /* 64k stage2 supported */
1185 t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN4_2, 2); /* 4k stage2 supported */
1186 t = FIELD_DP64(t, ID_AA64MMFR0, FGT, 1); /* FEAT_FGT */
1187 t = FIELD_DP64(t, ID_AA64MMFR0, ECV, 2); /* FEAT_ECV */
1188 cpu->isar.id_aa64mmfr0 = t;
1189
1190 t = cpu->isar.id_aa64mmfr1;
1191 t = FIELD_DP64(t, ID_AA64MMFR1, HAFDBS, 2); /* FEAT_HAFDBS */
1192 t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* FEAT_VMID16 */
1193 t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1); /* FEAT_VHE */
1194 t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 2); /* FEAT_HPDS2 */
1195 t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1); /* FEAT_LOR */
1196 t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 3); /* FEAT_PAN3 */
1197 t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* FEAT_XNX */
1198 t = FIELD_DP64(t, ID_AA64MMFR1, ETS, 1); /* FEAT_ETS */
1199 t = FIELD_DP64(t, ID_AA64MMFR1, HCX, 1); /* FEAT_HCX */
1200 t = FIELD_DP64(t, ID_AA64MMFR1, TIDCP1, 1); /* FEAT_TIDCP1 */
1201 cpu->isar.id_aa64mmfr1 = t;
1202
1203 t = cpu->isar.id_aa64mmfr2;
1204 t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* FEAT_TTCNP */
1205 t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); /* FEAT_UAO */
1206 t = FIELD_DP64(t, ID_AA64MMFR2, IESB, 1); /* FEAT_IESB */
1207 t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */
1208 t = FIELD_DP64(t, ID_AA64MMFR2, NV, 2); /* FEAT_NV2 */
1209 t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* FEAT_TTST */
1210 t = FIELD_DP64(t, ID_AA64MMFR2, AT, 1); /* FEAT_LSE2 */
1211 t = FIELD_DP64(t, ID_AA64MMFR2, IDS, 1); /* FEAT_IDST */
1212 t = FIELD_DP64(t, ID_AA64MMFR2, FWB, 1); /* FEAT_S2FWB */
1213 t = FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */
1214 t = FIELD_DP64(t, ID_AA64MMFR2, BBM, 2); /* FEAT_BBM at level 2 */
1215 t = FIELD_DP64(t, ID_AA64MMFR2, EVT, 2); /* FEAT_EVT */
1216 t = FIELD_DP64(t, ID_AA64MMFR2, E0PD, 1); /* FEAT_E0PD */
1217 cpu->isar.id_aa64mmfr2 = t;
1218
1219 t = cpu->isar.id_aa64zfr0;
1220 t = FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 1);
1221 t = FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* FEAT_SVE_PMULL128 */
1222 t = FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1); /* FEAT_SVE_BitPerm */
1223 t = FIELD_DP64(t, ID_AA64ZFR0, BFLOAT16, 1); /* FEAT_BF16 */
1224 t = FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1); /* FEAT_SVE_SHA3 */
1225 t = FIELD_DP64(t, ID_AA64ZFR0, SM4, 1); /* FEAT_SVE_SM4 */
1226 t = FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1); /* FEAT_I8MM */
1227 t = FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1); /* FEAT_F32MM */
1228 t = FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1); /* FEAT_F64MM */
1229 cpu->isar.id_aa64zfr0 = t;
1230
1231 t = cpu->isar.id_aa64dfr0;
1232 t = FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 9); /* FEAT_Debugv8p4 */
1233 t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 6); /* FEAT_PMUv3p5 */
1234 t = FIELD_DP64(t, ID_AA64DFR0, HPMN0, 1); /* FEAT_HPMN0 */
1235 cpu->isar.id_aa64dfr0 = t;
1236
1237 t = cpu->isar.id_aa64smfr0;
1238 t = FIELD_DP64(t, ID_AA64SMFR0, F32F32, 1); /* FEAT_SME */
1239 t = FIELD_DP64(t, ID_AA64SMFR0, B16F32, 1); /* FEAT_SME */
1240 t = FIELD_DP64(t, ID_AA64SMFR0, F16F32, 1); /* FEAT_SME */
1241 t = FIELD_DP64(t, ID_AA64SMFR0, I8I32, 0xf); /* FEAT_SME */
1242 t = FIELD_DP64(t, ID_AA64SMFR0, F64F64, 1); /* FEAT_SME_F64F64 */
1243 t = FIELD_DP64(t, ID_AA64SMFR0, I16I64, 0xf); /* FEAT_SME_I16I64 */
1244 t = FIELD_DP64(t, ID_AA64SMFR0, FA64, 1); /* FEAT_SME_FA64 */
1245 cpu->isar.id_aa64smfr0 = t;
1246
1247 /* Replicate the same data to the 32-bit id registers. */
1248 aa32_max_features(cpu);
1249
1250 #ifdef CONFIG_USER_ONLY
1251 /*
1252 * For usermode -cpu max we can use a larger and more efficient DCZ
1253 * blocksize since we don't have to follow what the hardware does.
1254 */
1255 cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */
1256 cpu->dcz_blocksize = 7; /* 512 bytes */
1257 #endif
1258 cpu->gm_blocksize = 6; /* 256 bytes */
1259
1260 cpu->sve_vq.supported = MAKE_64BIT_MASK(0, ARM_MAX_VQ);
1261 cpu->sme_vq.supported = SVE_VQ_POW2_MAP;
1262
1263 aarch64_add_pauth_properties(obj);
1264 aarch64_add_sve_properties(obj);
1265 aarch64_add_sme_properties(obj);
1266 object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_max_vq,
1267 cpu_max_set_sve_max_vq, NULL, NULL);
1268 object_property_add_bool(obj, "x-rme", cpu_arm_get_rme, cpu_arm_set_rme);
1269 object_property_add(obj, "x-l0gptsz", "uint32", cpu_max_get_l0gptsz,
1270 cpu_max_set_l0gptsz, NULL, NULL);
1271 qdev_property_add_static(DEVICE(obj), &arm_cpu_lpa2_property);
1272 }
1273
1274 static const ARMCPUInfo aarch64_cpus[] = {
1275 { .name = "cortex-a35", .initfn = aarch64_a35_initfn },
1276 { .name = "cortex-a55", .initfn = aarch64_a55_initfn },
1277 { .name = "cortex-a72", .initfn = aarch64_a72_initfn },
1278 { .name = "cortex-a76", .initfn = aarch64_a76_initfn },
1279 { .name = "cortex-a710", .initfn = aarch64_a710_initfn },
1280 { .name = "a64fx", .initfn = aarch64_a64fx_initfn },
1281 { .name = "neoverse-n1", .initfn = aarch64_neoverse_n1_initfn },
1282 { .name = "neoverse-v1", .initfn = aarch64_neoverse_v1_initfn },
1283 { .name = "neoverse-n2", .initfn = aarch64_neoverse_n2_initfn },
1284 };
1285
1286 static void aarch64_cpu_register_types(void)
1287 {
1288 size_t i;
1289
1290 for (i = 0; i < ARRAY_SIZE(aarch64_cpus); ++i) {
1291 aarch64_cpu_register(&aarch64_cpus[i]);
1292 }
1293 }
1294
1295 type_init(aarch64_cpu_register_types)
armbru's QEMU hackery