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1 .. _Arm Emulation:
3 A-profile CPU architecture support
4 ==================================
6 QEMU's TCG emulation includes support for the Armv5, Armv6, Armv7 and
7 Armv8 versions of the A-profile architecture. It also has support for
8 the following architecture extensions:
10 - FEAT_AA32BF16 (AArch32 BFloat16 instructions)
11 - FEAT_AA32HPD (AArch32 hierarchical permission disables)
12 - FEAT_AA32I8MM (AArch32 Int8 matrix multiplication instructions)
13 - FEAT_AES (AESD and AESE instructions)
14 - FEAT_BBM at level 2 (Translation table break-before-make levels)
15 - FEAT_BF16 (AArch64 BFloat16 instructions)
16 - FEAT_BTI (Branch Target Identification)
17 - FEAT_CRC32 (CRC32 instructions)
18 - FEAT_CSV2 (Cache speculation variant 2)
19 - FEAT_CSV2_1p1 (Cache speculation variant 2, version 1.1)
20 - FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2)
21 - FEAT_CSV2_2 (Cache speculation variant 2, version 2)
22 - FEAT_CSV3 (Cache speculation variant 3)
23 - FEAT_DGH (Data gathering hint)
24 - FEAT_DIT (Data Independent Timing instructions)
25 - FEAT_DPB (DC CVAP instruction)
26 - FEAT_Debugv8p2 (Debug changes for v8.2)
27 - FEAT_Debugv8p4 (Debug changes for v8.4)
28 - FEAT_DotProd (Advanced SIMD dot product instructions)
29 - FEAT_DoubleFault (Double Fault Extension)
30 - FEAT_E0PD (Preventing EL0 access to halves of address maps)
31 - FEAT_ECV (Enhanced Counter Virtualization)
32 - FEAT_EPAC (Enhanced pointer authentication)
33 - FEAT_ETS (Enhanced Translation Synchronization)
34 - FEAT_EVT (Enhanced Virtualization Traps)
35 - FEAT_FCMA (Floating-point complex number instructions)
36 - FEAT_FGT (Fine-Grained Traps)
37 - FEAT_FHM (Floating-point half-precision multiplication instructions)
38 - FEAT_FP16 (Half-precision floating-point data processing)
39 - FEAT_FPAC (Faulting on AUT* instructions)
40 - FEAT_FPACCOMBINE (Faulting on combined pointer authentication instructions)
41 - FEAT_FRINTTS (Floating-point to integer instructions)
42 - FEAT_FlagM (Flag manipulation instructions v2)
43 - FEAT_FlagM2 (Enhancements to flag manipulation instructions)
44 - FEAT_GTG (Guest translation granule size)
45 - FEAT_HAFDBS (Hardware management of the access flag and dirty bit state)
46 - FEAT_HBC (Hinted conditional branches)
47 - FEAT_HCX (Support for the HCRX_EL2 register)
48 - FEAT_HPDS (Hierarchical permission disables)
49 - FEAT_HPDS2 (Translation table page-based hardware attributes)
50 - FEAT_HPMN0 (Setting of MDCR_EL2.HPMN to zero)
51 - FEAT_I8MM (AArch64 Int8 matrix multiplication instructions)
52 - FEAT_IDST (ID space trap handling)
53 - FEAT_IESB (Implicit error synchronization event)
54 - FEAT_JSCVT (JavaScript conversion instructions)
55 - FEAT_LOR (Limited ordering regions)
56 - FEAT_LPA (Large Physical Address space)
57 - FEAT_LPA2 (Large Physical and virtual Address space v2)
58 - FEAT_LRCPC (Load-acquire RCpc instructions)
59 - FEAT_LRCPC2 (Load-acquire RCpc instructions v2)
60 - FEAT_LSE (Large System Extensions)
61 - FEAT_LSE2 (Large System Extensions v2)
62 - FEAT_LVA (Large Virtual Address space)
63 - FEAT_MOPS (Standardization of memory operations)
64 - FEAT_MTE (Memory Tagging Extension)
65 - FEAT_MTE2 (Memory Tagging Extension)
66 - FEAT_MTE3 (MTE Asymmetric Fault Handling)
67 - FEAT_NV (Nested Virtualization)
68 - FEAT_NV2 (Enhanced nested virtualization support)
69 - FEAT_PACIMP (Pointer authentication - IMPLEMENTATION DEFINED algorithm)
70 - FEAT_PACQARMA3 (Pointer authentication - QARMA3 algorithm)
71 - FEAT_PACQARMA5 (Pointer authentication - QARMA5 algorithm)
72 - FEAT_PAN (Privileged access never)
73 - FEAT_PAN2 (AT S1E1R and AT S1E1W instruction variants affected by PSTATE.PAN)
74 - FEAT_PAN3 (Support for SCTLR_ELx.EPAN)
75 - FEAT_PAuth (Pointer authentication)
76 - FEAT_PAuth2 (Enhancements to pointer authentication)
77 - FEAT_PMULL (PMULL, PMULL2 instructions)
78 - FEAT_PMUv3p1 (PMU Extensions v3.1)
79 - FEAT_PMUv3p4 (PMU Extensions v3.4)
80 - FEAT_PMUv3p5 (PMU Extensions v3.5)
81 - FEAT_RAS (Reliability, availability, and serviceability)
82 - FEAT_RASv1p1 (RAS Extension v1.1)
83 - FEAT_RDM (Advanced SIMD rounding double multiply accumulate instructions)
84 - FEAT_RME (Realm Management Extension) (NB: support status in QEMU is experimental)
85 - FEAT_RNG (Random number generator)
86 - FEAT_S2FWB (Stage 2 forced Write-Back)
87 - FEAT_SB (Speculation Barrier)
88 - FEAT_SEL2 (Secure EL2)
89 - FEAT_SHA1 (SHA1 instructions)
90 - FEAT_SHA256 (SHA256 instructions)
91 - FEAT_SHA3 (Advanced SIMD SHA3 instructions)
92 - FEAT_SHA512 (Advanced SIMD SHA512 instructions)
93 - FEAT_SM3 (Advanced SIMD SM3 instructions)
94 - FEAT_SM4 (Advanced SIMD SM4 instructions)
95 - FEAT_SME (Scalable Matrix Extension)
96 - FEAT_SME_FA64 (Full A64 instruction set in Streaming SVE mode)
97 - FEAT_SME_F64F64 (Double-precision floating-point outer product instructions)
98 - FEAT_SME_I16I64 (16-bit to 64-bit integer widening outer product instructions)
99 - FEAT_SPECRES (Speculation restriction instructions)
100 - FEAT_SSBS (Speculative Store Bypass Safe)
101 - FEAT_TIDCP1 (EL0 use of IMPLEMENTATION DEFINED functionality)
102 - FEAT_TLBIOS (TLB invalidate instructions in Outer Shareable domain)
103 - FEAT_TLBIRANGE (TLB invalidate range instructions)
104 - FEAT_TTCNP (Translation table Common not private translations)
105 - FEAT_TTL (Translation Table Level)
106 - FEAT_TTST (Small translation tables)
107 - FEAT_UAO (Unprivileged Access Override control)
108 - FEAT_VHE (Virtualization Host Extensions)
109 - FEAT_VMID16 (16-bit VMID)
110 - FEAT_XNX (Translation table stage 2 Unprivileged Execute-never)
111 - SVE (The Scalable Vector Extension)
112 - SVE2 (The Scalable Vector Extension v2)
114 For information on the specifics of these extensions, please refer
115 to the `Armv8-A Arm Architecture Reference Manual
116 <https://developer.arm.com/documentation/ddi0487/latest>`_.
118 When a specific named CPU is being emulated, only those features which
119 are present in hardware for that CPU are emulated. (If a feature is
120 not in the list above then it is not supported, even if the real
121 hardware should have it.) The ``max`` CPU enables all features.
123 R-profile CPU architecture support
124 ==================================
126 QEMU's TCG emulation support for R-profile CPUs is currently limited.
127 We emulate only the Cortex-R5 and Cortex-R5F CPUs.
129 M-profile CPU architecture support
130 ==================================
132 QEMU's TCG emulation includes support for Armv6-M, Armv7-M, Armv8-M, and
133 Armv8.1-M versions of the M-profile architucture. It also has support
134 for the following architecture extensions:
136 - FP (Floating-point Extension)
137 - FPCXT (FPCXT access instructions)
138 - HP (Half-precision floating-point instructions)
139 - LOB (Low Overhead loops and Branch future)
140 - M (Main Extension)
141 - MPU (Memory Protection Unit Extension)
142 - PXN (Privileged Execute Never)
143 - RAS (Reliability, Serviceability and Availability): "minimum RAS Extension" only
144 - S (Security Extension)
145 - ST (System Timer Extension)
147 For information on the specifics of these extensions, please refer
148 to the `Armv8-M Arm Architecture Reference Manual
149 <https://developer.arm.com/documentation/ddi0553/latest>`_.
151 When a specific named CPU is being emulated, only those features which
152 are present in hardware for that CPU are emulated. (If a feature is
153 not in the list above then it is not supported, even if the real
154 hardware should have it.) There is no equivalent of the ``max`` CPU for
155 M-profile.