2 * ARM V2M MPS2 board emulation.
4 * Copyright (c) 2017 Linaro Limited
5 * Written by Peter Maydell
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 or
9 * (at your option) any later version.
12 /* The MPS2 and MPS2+ dev boards are FPGA based (the 2+ has a bigger
13 * FPGA but is otherwise the same as the 2). Since the CPU itself
14 * and most of the devices are in the FPGA, the details of the board
15 * as seen by the guest depend significantly on the FPGA image.
16 * We model the following FPGA images:
17 * "mps2-an385" -- Cortex-M3 as documented in ARM Application Note AN385
18 * "mps2-an511" -- Cortex-M3 'DesignStart' as documented in AN511
20 * Links to the TRM for the board itself and to the various Application
21 * Notes which document the FPGA images can be found here:
22 * https://developer.arm.com/products/system-design/development-boards/cortex-m-prototyping-system
25 #include "qemu/osdep.h"
26 #include "qemu/units.h"
27 #include "qemu/cutils.h"
28 #include "qapi/error.h"
29 #include "qemu/error-report.h"
30 #include "hw/arm/boot.h"
31 #include "hw/arm/armv7m.h"
32 #include "hw/or-irq.h"
33 #include "hw/boards.h"
34 #include "exec/address-spaces.h"
35 #include "sysemu/sysemu.h"
36 #include "hw/misc/unimp.h"
37 #include "hw/char/cmsdk-apb-uart.h"
38 #include "hw/timer/cmsdk-apb-timer.h"
39 #include "hw/timer/cmsdk-apb-dualtimer.h"
40 #include "hw/misc/mps2-scc.h"
41 #include "hw/net/lan9118.h"
44 typedef enum MPS2FPGAType
{
51 MPS2FPGAType fpga_type
;
60 MemoryRegion ssram1_m
;
62 MemoryRegion ssram23_m
;
63 MemoryRegion blockram
;
64 MemoryRegion blockram_m1
;
65 MemoryRegion blockram_m2
;
66 MemoryRegion blockram_m3
;
68 /* FPGA APB subsystem */
70 /* CMSDK APB subsystem */
71 CMSDKAPBDualTimer dualtimer
;
74 #define TYPE_MPS2_MACHINE "mps2"
75 #define TYPE_MPS2_AN385_MACHINE MACHINE_TYPE_NAME("mps2-an385")
76 #define TYPE_MPS2_AN511_MACHINE MACHINE_TYPE_NAME("mps2-an511")
78 #define MPS2_MACHINE(obj) \
79 OBJECT_CHECK(MPS2MachineState, obj, TYPE_MPS2_MACHINE)
80 #define MPS2_MACHINE_GET_CLASS(obj) \
81 OBJECT_GET_CLASS(MPS2MachineClass, obj, TYPE_MPS2_MACHINE)
82 #define MPS2_MACHINE_CLASS(klass) \
83 OBJECT_CLASS_CHECK(MPS2MachineClass, klass, TYPE_MPS2_MACHINE)
85 /* Main SYSCLK frequency in Hz */
86 #define SYSCLK_FRQ 25000000
88 /* Initialize the auxiliary RAM region @mr and map it into
89 * the memory map at @base.
91 static void make_ram(MemoryRegion
*mr
, const char *name
,
92 hwaddr base
, hwaddr size
)
94 memory_region_init_ram(mr
, NULL
, name
, size
, &error_fatal
);
95 memory_region_add_subregion(get_system_memory(), base
, mr
);
98 /* Create an alias of an entire original MemoryRegion @orig
99 * located at @base in the memory map.
101 static void make_ram_alias(MemoryRegion
*mr
, const char *name
,
102 MemoryRegion
*orig
, hwaddr base
)
104 memory_region_init_alias(mr
, NULL
, name
, orig
, 0,
105 memory_region_size(orig
));
106 memory_region_add_subregion(get_system_memory(), base
, mr
);
109 static void mps2_common_init(MachineState
*machine
)
111 MPS2MachineState
*mms
= MPS2_MACHINE(machine
);
112 MPS2MachineClass
*mmc
= MPS2_MACHINE_GET_CLASS(machine
);
113 MemoryRegion
*system_memory
= get_system_memory();
114 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
115 DeviceState
*armv7m
, *sccdev
;
118 if (strcmp(machine
->cpu_type
, mc
->default_cpu_type
) != 0) {
119 error_report("This board can only be used with CPU %s",
120 mc
->default_cpu_type
);
124 if (machine
->ram_size
!= mc
->default_ram_size
) {
125 char *sz
= size_to_str(mc
->default_ram_size
);
126 error_report("Invalid RAM size, should be %s", sz
);
131 /* The FPGA images have an odd combination of different RAMs,
132 * because in hardware they are different implementations and
133 * connected to different buses, giving varying performance/size
134 * tradeoffs. For QEMU they're all just RAM, though. We arbitrarily
135 * call the 16MB our "system memory", as it's the largest lump.
137 * Common to both boards:
138 * 0x21000000..0x21ffffff : PSRAM (16MB)
140 * 0x00000000 .. 0x003fffff : ZBT SSRAM1
141 * 0x00400000 .. 0x007fffff : mirror of ZBT SSRAM1
142 * 0x20000000 .. 0x203fffff : ZBT SSRAM 2&3
143 * 0x20400000 .. 0x207fffff : mirror of ZBT SSRAM 2&3
144 * 0x01000000 .. 0x01003fff : block RAM (16K)
145 * 0x01004000 .. 0x01007fff : mirror of above
146 * 0x01008000 .. 0x0100bfff : mirror of above
147 * 0x0100c000 .. 0x0100ffff : mirror of above
149 * 0x00000000 .. 0x0003ffff : FPGA block RAM
150 * 0x00400000 .. 0x007fffff : ZBT SSRAM1
151 * 0x20000000 .. 0x2001ffff : SRAM
152 * 0x20400000 .. 0x207fffff : ZBT SSRAM 2&3
154 * The AN385 has a feature where the lowest 16K can be mapped
155 * either to the bottom of the ZBT SSRAM1 or to the block RAM.
156 * This is of no use for QEMU so we don't implement it (as if
157 * zbt_boot_ctrl is always zero).
159 memory_region_add_subregion(system_memory
, 0x21000000, machine
->ram
);
161 switch (mmc
->fpga_type
) {
163 make_ram(&mms
->ssram1
, "mps.ssram1", 0x0, 0x400000);
164 make_ram_alias(&mms
->ssram1_m
, "mps.ssram1_m", &mms
->ssram1
, 0x400000);
165 make_ram(&mms
->ssram23
, "mps.ssram23", 0x20000000, 0x400000);
166 make_ram_alias(&mms
->ssram23_m
, "mps.ssram23_m",
167 &mms
->ssram23
, 0x20400000);
168 make_ram(&mms
->blockram
, "mps.blockram", 0x01000000, 0x4000);
169 make_ram_alias(&mms
->blockram_m1
, "mps.blockram_m1",
170 &mms
->blockram
, 0x01004000);
171 make_ram_alias(&mms
->blockram_m2
, "mps.blockram_m2",
172 &mms
->blockram
, 0x01008000);
173 make_ram_alias(&mms
->blockram_m3
, "mps.blockram_m3",
174 &mms
->blockram
, 0x0100c000);
177 make_ram(&mms
->blockram
, "mps.blockram", 0x0, 0x40000);
178 make_ram(&mms
->ssram1
, "mps.ssram1", 0x00400000, 0x00800000);
179 make_ram(&mms
->sram
, "mps.sram", 0x20000000, 0x20000);
180 make_ram(&mms
->ssram23
, "mps.ssram23", 0x20400000, 0x400000);
183 g_assert_not_reached();
186 object_initialize_child(OBJECT(mms
), "armv7m", &mms
->armv7m
, TYPE_ARMV7M
);
187 armv7m
= DEVICE(&mms
->armv7m
);
188 switch (mmc
->fpga_type
) {
190 qdev_prop_set_uint32(armv7m
, "num-irq", 32);
193 qdev_prop_set_uint32(armv7m
, "num-irq", 64);
196 g_assert_not_reached();
198 qdev_prop_set_string(armv7m
, "cpu-type", machine
->cpu_type
);
199 qdev_prop_set_bit(armv7m
, "enable-bitband", true);
200 object_property_set_link(OBJECT(&mms
->armv7m
), OBJECT(system_memory
),
201 "memory", &error_abort
);
202 sysbus_realize(SYS_BUS_DEVICE(&mms
->armv7m
), &error_fatal
);
204 create_unimplemented_device("zbtsmram mirror", 0x00400000, 0x00400000);
205 create_unimplemented_device("RESERVED 1", 0x00800000, 0x00800000);
206 create_unimplemented_device("Block RAM", 0x01000000, 0x00010000);
207 create_unimplemented_device("RESERVED 2", 0x01010000, 0x1EFF0000);
208 create_unimplemented_device("RESERVED 3", 0x20800000, 0x00800000);
209 create_unimplemented_device("PSRAM", 0x21000000, 0x01000000);
210 /* These three ranges all cover multiple devices; we may implement
211 * some of them below (in which case the real device takes precedence
212 * over the unimplemented-region mapping).
214 create_unimplemented_device("CMSDK APB peripheral region @0x40000000",
215 0x40000000, 0x00010000);
216 create_unimplemented_device("CMSDK AHB peripheral region @0x40010000",
217 0x40010000, 0x00010000);
218 create_unimplemented_device("Extra peripheral region @0x40020000",
219 0x40020000, 0x00010000);
221 create_unimplemented_device("RESERVED 4", 0x40030000, 0x001D0000);
222 create_unimplemented_device("VGA", 0x41000000, 0x0200000);
224 switch (mmc
->fpga_type
) {
227 /* The overflow IRQs for UARTs 0, 1 and 2 are ORed together.
228 * Overflow for UARTs 4 and 5 doesn't trigger any interrupt.
231 DeviceState
*orgate_dev
;
233 orgate
= object_new(TYPE_OR_IRQ
);
234 object_property_set_int(orgate
, 6, "num-lines", &error_fatal
);
235 qdev_realize(DEVICE(orgate
), NULL
, &error_fatal
);
236 orgate_dev
= DEVICE(orgate
);
237 qdev_connect_gpio_out(orgate_dev
, 0, qdev_get_gpio_in(armv7m
, 12));
239 for (i
= 0; i
< 5; i
++) {
240 static const hwaddr uartbase
[] = {0x40004000, 0x40005000,
241 0x40006000, 0x40007000,
243 /* RX irq number; TX irq is always one greater */
244 static const int uartirq
[] = {0, 2, 4, 18, 20};
245 qemu_irq txovrint
= NULL
, rxovrint
= NULL
;
248 txovrint
= qdev_get_gpio_in(orgate_dev
, i
* 2);
249 rxovrint
= qdev_get_gpio_in(orgate_dev
, i
* 2 + 1);
252 cmsdk_apb_uart_create(uartbase
[i
],
253 qdev_get_gpio_in(armv7m
, uartirq
[i
] + 1),
254 qdev_get_gpio_in(armv7m
, uartirq
[i
]),
257 serial_hd(i
), SYSCLK_FRQ
);
263 /* The overflow IRQs for all UARTs are ORed together.
264 * Tx and Rx IRQs for each UART are ORed together.
267 DeviceState
*orgate_dev
;
269 orgate
= object_new(TYPE_OR_IRQ
);
270 object_property_set_int(orgate
, 10, "num-lines", &error_fatal
);
271 qdev_realize(DEVICE(orgate
), NULL
, &error_fatal
);
272 orgate_dev
= DEVICE(orgate
);
273 qdev_connect_gpio_out(orgate_dev
, 0, qdev_get_gpio_in(armv7m
, 12));
275 for (i
= 0; i
< 5; i
++) {
276 /* system irq numbers for the combined tx/rx for each UART */
277 static const int uart_txrx_irqno
[] = {0, 2, 45, 46, 56};
278 static const hwaddr uartbase
[] = {0x40004000, 0x40005000,
279 0x4002c000, 0x4002d000,
282 DeviceState
*txrx_orgate_dev
;
284 txrx_orgate
= object_new(TYPE_OR_IRQ
);
285 object_property_set_int(txrx_orgate
, 2, "num-lines", &error_fatal
);
286 qdev_realize(DEVICE(txrx_orgate
), NULL
, &error_fatal
);
287 txrx_orgate_dev
= DEVICE(txrx_orgate
);
288 qdev_connect_gpio_out(txrx_orgate_dev
, 0,
289 qdev_get_gpio_in(armv7m
, uart_txrx_irqno
[i
]));
290 cmsdk_apb_uart_create(uartbase
[i
],
291 qdev_get_gpio_in(txrx_orgate_dev
, 0),
292 qdev_get_gpio_in(txrx_orgate_dev
, 1),
293 qdev_get_gpio_in(orgate_dev
, i
* 2),
294 qdev_get_gpio_in(orgate_dev
, i
* 2 + 1),
296 serial_hd(i
), SYSCLK_FRQ
);
301 g_assert_not_reached();
303 for (i
= 0; i
< 4; i
++) {
304 static const hwaddr gpiobase
[] = {0x40010000, 0x40011000,
305 0x40012000, 0x40013000};
306 create_unimplemented_device("cmsdk-ahb-gpio", gpiobase
[i
], 0x1000);
309 /* CMSDK APB subsystem */
310 cmsdk_apb_timer_create(0x40000000, qdev_get_gpio_in(armv7m
, 8), SYSCLK_FRQ
);
311 cmsdk_apb_timer_create(0x40001000, qdev_get_gpio_in(armv7m
, 9), SYSCLK_FRQ
);
312 object_initialize_child(OBJECT(mms
), "dualtimer", &mms
->dualtimer
,
313 TYPE_CMSDK_APB_DUALTIMER
);
314 qdev_prop_set_uint32(DEVICE(&mms
->dualtimer
), "pclk-frq", SYSCLK_FRQ
);
315 sysbus_realize(SYS_BUS_DEVICE(&mms
->dualtimer
), &error_fatal
);
316 sysbus_connect_irq(SYS_BUS_DEVICE(&mms
->dualtimer
), 0,
317 qdev_get_gpio_in(armv7m
, 10));
318 sysbus_mmio_map(SYS_BUS_DEVICE(&mms
->dualtimer
), 0, 0x40002000);
319 object_initialize_child(OBJECT(mms
), "watchdog", &mms
->watchdog
,
320 TYPE_CMSDK_APB_WATCHDOG
);
321 qdev_prop_set_uint32(DEVICE(&mms
->watchdog
), "wdogclk-frq", SYSCLK_FRQ
);
322 sysbus_realize(SYS_BUS_DEVICE(&mms
->watchdog
), &error_fatal
);
323 sysbus_connect_irq(SYS_BUS_DEVICE(&mms
->watchdog
), 0,
324 qdev_get_gpio_in_named(armv7m
, "NMI", 0));
325 sysbus_mmio_map(SYS_BUS_DEVICE(&mms
->watchdog
), 0, 0x40008000);
327 /* FPGA APB subsystem */
328 object_initialize_child(OBJECT(mms
), "scc", &mms
->scc
, TYPE_MPS2_SCC
);
329 sccdev
= DEVICE(&mms
->scc
);
330 qdev_prop_set_uint32(sccdev
, "scc-cfg4", 0x2);
331 qdev_prop_set_uint32(sccdev
, "scc-aid", 0x00200008);
332 qdev_prop_set_uint32(sccdev
, "scc-id", mmc
->scc_id
);
333 sysbus_realize(SYS_BUS_DEVICE(&mms
->scc
), &error_fatal
);
334 sysbus_mmio_map(SYS_BUS_DEVICE(sccdev
), 0, 0x4002f000);
336 /* In hardware this is a LAN9220; the LAN9118 is software compatible
337 * except that it doesn't support the checksum-offload feature.
339 lan9118_init(&nd_table
[0], 0x40200000,
340 qdev_get_gpio_in(armv7m
,
341 mmc
->fpga_type
== FPGA_AN385
? 13 : 47));
343 system_clock_scale
= NANOSECONDS_PER_SECOND
/ SYSCLK_FRQ
;
345 armv7m_load_kernel(ARM_CPU(first_cpu
), machine
->kernel_filename
,
349 static void mps2_class_init(ObjectClass
*oc
, void *data
)
351 MachineClass
*mc
= MACHINE_CLASS(oc
);
353 mc
->init
= mps2_common_init
;
355 mc
->default_ram_size
= 16 * MiB
;
356 mc
->default_ram_id
= "mps.ram";
359 static void mps2_an385_class_init(ObjectClass
*oc
, void *data
)
361 MachineClass
*mc
= MACHINE_CLASS(oc
);
362 MPS2MachineClass
*mmc
= MPS2_MACHINE_CLASS(oc
);
364 mc
->desc
= "ARM MPS2 with AN385 FPGA image for Cortex-M3";
365 mmc
->fpga_type
= FPGA_AN385
;
366 mc
->default_cpu_type
= ARM_CPU_TYPE_NAME("cortex-m3");
367 mmc
->scc_id
= 0x41043850;
370 static void mps2_an511_class_init(ObjectClass
*oc
, void *data
)
372 MachineClass
*mc
= MACHINE_CLASS(oc
);
373 MPS2MachineClass
*mmc
= MPS2_MACHINE_CLASS(oc
);
375 mc
->desc
= "ARM MPS2 with AN511 DesignStart FPGA image for Cortex-M3";
376 mmc
->fpga_type
= FPGA_AN511
;
377 mc
->default_cpu_type
= ARM_CPU_TYPE_NAME("cortex-m3");
378 mmc
->scc_id
= 0x41045110;
381 static const TypeInfo mps2_info
= {
382 .name
= TYPE_MPS2_MACHINE
,
383 .parent
= TYPE_MACHINE
,
385 .instance_size
= sizeof(MPS2MachineState
),
386 .class_size
= sizeof(MPS2MachineClass
),
387 .class_init
= mps2_class_init
,
390 static const TypeInfo mps2_an385_info
= {
391 .name
= TYPE_MPS2_AN385_MACHINE
,
392 .parent
= TYPE_MPS2_MACHINE
,
393 .class_init
= mps2_an385_class_init
,
396 static const TypeInfo mps2_an511_info
= {
397 .name
= TYPE_MPS2_AN511_MACHINE
,
398 .parent
= TYPE_MPS2_MACHINE
,
399 .class_init
= mps2_an511_class_init
,
402 static void mps2_machine_init(void)
404 type_register_static(&mps2_info
);
405 type_register_static(&mps2_an385_info
);
406 type_register_static(&mps2_an511_info
);
409 type_init(mps2_machine_init
);