| blob | 6528e1ae31e04e0cd4f4ae050748bb7638ca3016 |
1 /*** VSX extension ***/
3 static inline void get_cpu_vsr(TCGv_i64 dst, int n, bool high)
4 {
5 tcg_gen_ld_i64(dst, cpu_env, vsr64_offset(n, high));
6 }
8 static inline void set_cpu_vsr(int n, TCGv_i64 src, bool high)
9 {
10 tcg_gen_st_i64(src, cpu_env, vsr64_offset(n, high));
11 }
13 static inline TCGv_ptr gen_vsr_ptr(int reg)
14 {
15 TCGv_ptr r = tcg_temp_new_ptr();
16 tcg_gen_addi_ptr(r, cpu_env, vsr_full_offset(reg));
17 return r;
18 }
20 #define VSX_LOAD_SCALAR(name, operation) \
21 static void gen_##name(DisasContext *ctx) \
22 { \
23 TCGv EA; \
24 TCGv_i64 t0; \
25 if (unlikely(!ctx->vsx_enabled)) { \
26 gen_exception(ctx, POWERPC_EXCP_VSXU); \
27 return; \
28 } \
29 t0 = tcg_temp_new_i64(); \
30 gen_set_access_type(ctx, ACCESS_INT); \
31 EA = tcg_temp_new(); \
32 gen_addr_reg_index(ctx, EA); \
33 gen_qemu_##operation(ctx, t0, EA); \
34 set_cpu_vsr(xT(ctx->opcode), t0, true); \
35 /* NOTE: cpu_vsrl is undefined */ \
36 tcg_temp_free(EA); \
37 tcg_temp_free_i64(t0); \
38 }
40 VSX_LOAD_SCALAR(lxsdx, ld64_i64)
41 VSX_LOAD_SCALAR(lxsiwax, ld32s_i64)
42 VSX_LOAD_SCALAR(lxsibzx, ld8u_i64)
43 VSX_LOAD_SCALAR(lxsihzx, ld16u_i64)
44 VSX_LOAD_SCALAR(lxsiwzx, ld32u_i64)
45 VSX_LOAD_SCALAR(lxsspx, ld32fs)
47 static void gen_lxvd2x(DisasContext *ctx)
48 {
49 TCGv EA;
50 TCGv_i64 t0;
51 if (unlikely(!ctx->vsx_enabled)) {
52 gen_exception(ctx, POWERPC_EXCP_VSXU);
53 return;
54 }
55 t0 = tcg_temp_new_i64();
56 gen_set_access_type(ctx, ACCESS_INT);
57 EA = tcg_temp_new();
58 gen_addr_reg_index(ctx, EA);
59 gen_qemu_ld64_i64(ctx, t0, EA);
60 set_cpu_vsr(xT(ctx->opcode), t0, true);
61 tcg_gen_addi_tl(EA, EA, 8);
62 gen_qemu_ld64_i64(ctx, t0, EA);
63 set_cpu_vsr(xT(ctx->opcode), t0, false);
64 tcg_temp_free(EA);
65 tcg_temp_free_i64(t0);
66 }
68 static void gen_lxvw4x(DisasContext *ctx)
69 {
70 TCGv EA;
71 TCGv_i64 xth;
72 TCGv_i64 xtl;
73 if (unlikely(!ctx->vsx_enabled)) {
74 gen_exception(ctx, POWERPC_EXCP_VSXU);
75 return;
76 }
77 xth = tcg_temp_new_i64();
78 xtl = tcg_temp_new_i64();
80 gen_set_access_type(ctx, ACCESS_INT);
81 EA = tcg_temp_new();
83 gen_addr_reg_index(ctx, EA);
84 if (ctx->le_mode) {
85 TCGv_i64 t0 = tcg_temp_new_i64();
86 TCGv_i64 t1 = tcg_temp_new_i64();
88 tcg_gen_qemu_ld_i64(t0, EA, ctx->mem_idx, MO_LEUQ);
89 tcg_gen_shri_i64(t1, t0, 32);
90 tcg_gen_deposit_i64(xth, t1, t0, 32, 32);
91 tcg_gen_addi_tl(EA, EA, 8);
92 tcg_gen_qemu_ld_i64(t0, EA, ctx->mem_idx, MO_LEUQ);
93 tcg_gen_shri_i64(t1, t0, 32);
94 tcg_gen_deposit_i64(xtl, t1, t0, 32, 32);
95 tcg_temp_free_i64(t0);
96 tcg_temp_free_i64(t1);
97 } else {
98 tcg_gen_qemu_ld_i64(xth, EA, ctx->mem_idx, MO_BEUQ);
99 tcg_gen_addi_tl(EA, EA, 8);
100 tcg_gen_qemu_ld_i64(xtl, EA, ctx->mem_idx, MO_BEUQ);
101 }
102 set_cpu_vsr(xT(ctx->opcode), xth, true);
103 set_cpu_vsr(xT(ctx->opcode), xtl, false);
104 tcg_temp_free(EA);
105 tcg_temp_free_i64(xth);
106 tcg_temp_free_i64(xtl);
107 }
109 static void gen_lxvwsx(DisasContext *ctx)
110 {
111 TCGv EA;
112 TCGv_i32 data;
114 if (xT(ctx->opcode) < 32) {
115 if (unlikely(!ctx->vsx_enabled)) {
116 gen_exception(ctx, POWERPC_EXCP_VSXU);
117 return;
118 }
119 } else {
120 if (unlikely(!ctx->altivec_enabled)) {
121 gen_exception(ctx, POWERPC_EXCP_VPU);
122 return;
123 }
124 }
126 gen_set_access_type(ctx, ACCESS_INT);
127 EA = tcg_temp_new();
129 gen_addr_reg_index(ctx, EA);
131 data = tcg_temp_new_i32();
132 tcg_gen_qemu_ld_i32(data, EA, ctx->mem_idx, DEF_MEMOP(MO_UL));
133 tcg_gen_gvec_dup_i32(MO_UL, vsr_full_offset(xT(ctx->opcode)), 16, 16, data);
135 tcg_temp_free(EA);
136 tcg_temp_free_i32(data);
137 }
139 static void gen_lxvdsx(DisasContext *ctx)
140 {
141 TCGv EA;
142 TCGv_i64 data;
144 if (unlikely(!ctx->vsx_enabled)) {
145 gen_exception(ctx, POWERPC_EXCP_VSXU);
146 return;
147 }
149 gen_set_access_type(ctx, ACCESS_INT);
150 EA = tcg_temp_new();
152 gen_addr_reg_index(ctx, EA);
154 data = tcg_temp_new_i64();
155 tcg_gen_qemu_ld_i64(data, EA, ctx->mem_idx, DEF_MEMOP(MO_UQ));
156 tcg_gen_gvec_dup_i64(MO_UQ, vsr_full_offset(xT(ctx->opcode)), 16, 16, data);
158 tcg_temp_free(EA);
159 tcg_temp_free_i64(data);
160 }
162 static void gen_bswap16x8(TCGv_i64 outh, TCGv_i64 outl,
163 TCGv_i64 inh, TCGv_i64 inl)
164 {
165 TCGv_i64 mask = tcg_const_i64(0x00FF00FF00FF00FF);
166 TCGv_i64 t0 = tcg_temp_new_i64();
167 TCGv_i64 t1 = tcg_temp_new_i64();
169 /* outh = ((inh & mask) << 8) | ((inh >> 8) & mask) */
170 tcg_gen_and_i64(t0, inh, mask);
171 tcg_gen_shli_i64(t0, t0, 8);
172 tcg_gen_shri_i64(t1, inh, 8);
173 tcg_gen_and_i64(t1, t1, mask);
174 tcg_gen_or_i64(outh, t0, t1);
176 /* outl = ((inl & mask) << 8) | ((inl >> 8) & mask) */
177 tcg_gen_and_i64(t0, inl, mask);
178 tcg_gen_shli_i64(t0, t0, 8);
179 tcg_gen_shri_i64(t1, inl, 8);
180 tcg_gen_and_i64(t1, t1, mask);
181 tcg_gen_or_i64(outl, t0, t1);
183 tcg_temp_free_i64(t0);
184 tcg_temp_free_i64(t1);
185 tcg_temp_free_i64(mask);
186 }
188 static void gen_bswap32x4(TCGv_i64 outh, TCGv_i64 outl,
189 TCGv_i64 inh, TCGv_i64 inl)
190 {
191 TCGv_i64 hi = tcg_temp_new_i64();
192 TCGv_i64 lo = tcg_temp_new_i64();
194 tcg_gen_bswap64_i64(hi, inh);
195 tcg_gen_bswap64_i64(lo, inl);
196 tcg_gen_shri_i64(outh, hi, 32);
197 tcg_gen_deposit_i64(outh, outh, hi, 32, 32);
198 tcg_gen_shri_i64(outl, lo, 32);
199 tcg_gen_deposit_i64(outl, outl, lo, 32, 32);
201 tcg_temp_free_i64(hi);
202 tcg_temp_free_i64(lo);
203 }
204 static void gen_lxvh8x(DisasContext *ctx)
205 {
206 TCGv EA;
207 TCGv_i64 xth;
208 TCGv_i64 xtl;
210 if (unlikely(!ctx->vsx_enabled)) {
211 gen_exception(ctx, POWERPC_EXCP_VSXU);
212 return;
213 }
214 xth = tcg_temp_new_i64();
215 xtl = tcg_temp_new_i64();
216 gen_set_access_type(ctx, ACCESS_INT);
218 EA = tcg_temp_new();
219 gen_addr_reg_index(ctx, EA);
220 tcg_gen_qemu_ld_i64(xth, EA, ctx->mem_idx, MO_BEUQ);
221 tcg_gen_addi_tl(EA, EA, 8);
222 tcg_gen_qemu_ld_i64(xtl, EA, ctx->mem_idx, MO_BEUQ);
223 if (ctx->le_mode) {
224 gen_bswap16x8(xth, xtl, xth, xtl);
225 }
226 set_cpu_vsr(xT(ctx->opcode), xth, true);
227 set_cpu_vsr(xT(ctx->opcode), xtl, false);
228 tcg_temp_free(EA);
229 tcg_temp_free_i64(xth);
230 tcg_temp_free_i64(xtl);
231 }
233 static void gen_lxvb16x(DisasContext *ctx)
234 {
235 TCGv EA;
236 TCGv_i64 xth;
237 TCGv_i64 xtl;
239 if (unlikely(!ctx->vsx_enabled)) {
240 gen_exception(ctx, POWERPC_EXCP_VSXU);
241 return;
242 }
243 xth = tcg_temp_new_i64();
244 xtl = tcg_temp_new_i64();
245 gen_set_access_type(ctx, ACCESS_INT);
246 EA = tcg_temp_new();
247 gen_addr_reg_index(ctx, EA);
248 tcg_gen_qemu_ld_i64(xth, EA, ctx->mem_idx, MO_BEUQ);
249 tcg_gen_addi_tl(EA, EA, 8);
250 tcg_gen_qemu_ld_i64(xtl, EA, ctx->mem_idx, MO_BEUQ);
251 set_cpu_vsr(xT(ctx->opcode), xth, true);
252 set_cpu_vsr(xT(ctx->opcode), xtl, false);
253 tcg_temp_free(EA);
254 tcg_temp_free_i64(xth);
255 tcg_temp_free_i64(xtl);
256 }
258 #ifdef TARGET_PPC64
259 #define VSX_VECTOR_LOAD_STORE_LENGTH(name) \
260 static void gen_##name(DisasContext *ctx) \
261 { \
262 TCGv EA; \
263 TCGv_ptr xt; \
264 \
265 if (xT(ctx->opcode) < 32) { \
266 if (unlikely(!ctx->vsx_enabled)) { \
267 gen_exception(ctx, POWERPC_EXCP_VSXU); \
268 return; \
269 } \
270 } else { \
271 if (unlikely(!ctx->altivec_enabled)) { \
272 gen_exception(ctx, POWERPC_EXCP_VPU); \
273 return; \
274 } \
275 } \
276 EA = tcg_temp_new(); \
277 xt = gen_vsr_ptr(xT(ctx->opcode)); \
278 gen_set_access_type(ctx, ACCESS_INT); \
279 gen_addr_register(ctx, EA); \
280 gen_helper_##name(cpu_env, EA, xt, cpu_gpr[rB(ctx->opcode)]); \
281 tcg_temp_free(EA); \
282 tcg_temp_free_ptr(xt); \
283 }
285 VSX_VECTOR_LOAD_STORE_LENGTH(lxvl)
286 VSX_VECTOR_LOAD_STORE_LENGTH(lxvll)
287 VSX_VECTOR_LOAD_STORE_LENGTH(stxvl)
288 VSX_VECTOR_LOAD_STORE_LENGTH(stxvll)
289 #endif
291 #define VSX_LOAD_SCALAR_DS(name, operation) \
292 static void gen_##name(DisasContext *ctx) \
293 { \
294 TCGv EA; \
295 TCGv_i64 xth; \
296 \
297 if (unlikely(!ctx->altivec_enabled)) { \
298 gen_exception(ctx, POWERPC_EXCP_VPU); \
299 return; \
300 } \
301 xth = tcg_temp_new_i64(); \
302 gen_set_access_type(ctx, ACCESS_INT); \
303 EA = tcg_temp_new(); \
304 gen_addr_imm_index(ctx, EA, 0x03); \
305 gen_qemu_##operation(ctx, xth, EA); \
306 set_cpu_vsr(rD(ctx->opcode) + 32, xth, true); \
307 /* NOTE: cpu_vsrl is undefined */ \
308 tcg_temp_free(EA); \
309 tcg_temp_free_i64(xth); \
310 }
312 VSX_LOAD_SCALAR_DS(lxsd, ld64_i64)
313 VSX_LOAD_SCALAR_DS(lxssp, ld32fs)
315 #define VSX_STORE_SCALAR(name, operation) \
316 static void gen_##name(DisasContext *ctx) \
317 { \
318 TCGv EA; \
319 TCGv_i64 t0; \
320 if (unlikely(!ctx->vsx_enabled)) { \
321 gen_exception(ctx, POWERPC_EXCP_VSXU); \
322 return; \
323 } \
324 t0 = tcg_temp_new_i64(); \
325 gen_set_access_type(ctx, ACCESS_INT); \
326 EA = tcg_temp_new(); \
327 gen_addr_reg_index(ctx, EA); \
328 get_cpu_vsr(t0, xS(ctx->opcode), true); \
329 gen_qemu_##operation(ctx, t0, EA); \
330 tcg_temp_free(EA); \
331 tcg_temp_free_i64(t0); \
332 }
334 VSX_STORE_SCALAR(stxsdx, st64_i64)
336 VSX_STORE_SCALAR(stxsibx, st8_i64)
337 VSX_STORE_SCALAR(stxsihx, st16_i64)
338 VSX_STORE_SCALAR(stxsiwx, st32_i64)
339 VSX_STORE_SCALAR(stxsspx, st32fs)
341 static void gen_stxvd2x(DisasContext *ctx)
342 {
343 TCGv EA;
344 TCGv_i64 t0;
345 if (unlikely(!ctx->vsx_enabled)) {
346 gen_exception(ctx, POWERPC_EXCP_VSXU);
347 return;
348 }
349 t0 = tcg_temp_new_i64();
350 gen_set_access_type(ctx, ACCESS_INT);
351 EA = tcg_temp_new();
352 gen_addr_reg_index(ctx, EA);
353 get_cpu_vsr(t0, xS(ctx->opcode), true);
354 gen_qemu_st64_i64(ctx, t0, EA);
355 tcg_gen_addi_tl(EA, EA, 8);
356 get_cpu_vsr(t0, xS(ctx->opcode), false);
357 gen_qemu_st64_i64(ctx, t0, EA);
358 tcg_temp_free(EA);
359 tcg_temp_free_i64(t0);
360 }
362 static void gen_stxvw4x(DisasContext *ctx)
363 {
364 TCGv EA;
365 TCGv_i64 xsh;
366 TCGv_i64 xsl;
368 if (unlikely(!ctx->vsx_enabled)) {
369 gen_exception(ctx, POWERPC_EXCP_VSXU);
370 return;
371 }
372 xsh = tcg_temp_new_i64();
373 xsl = tcg_temp_new_i64();
374 get_cpu_vsr(xsh, xS(ctx->opcode), true);
375 get_cpu_vsr(xsl, xS(ctx->opcode), false);
376 gen_set_access_type(ctx, ACCESS_INT);
377 EA = tcg_temp_new();
378 gen_addr_reg_index(ctx, EA);
379 if (ctx->le_mode) {
380 TCGv_i64 t0 = tcg_temp_new_i64();
381 TCGv_i64 t1 = tcg_temp_new_i64();
383 tcg_gen_shri_i64(t0, xsh, 32);
384 tcg_gen_deposit_i64(t1, t0, xsh, 32, 32);
385 tcg_gen_qemu_st_i64(t1, EA, ctx->mem_idx, MO_LEUQ);
386 tcg_gen_addi_tl(EA, EA, 8);
387 tcg_gen_shri_i64(t0, xsl, 32);
388 tcg_gen_deposit_i64(t1, t0, xsl, 32, 32);
389 tcg_gen_qemu_st_i64(t1, EA, ctx->mem_idx, MO_LEUQ);
390 tcg_temp_free_i64(t0);
391 tcg_temp_free_i64(t1);
392 } else {
393 tcg_gen_qemu_st_i64(xsh, EA, ctx->mem_idx, MO_BEUQ);
394 tcg_gen_addi_tl(EA, EA, 8);
395 tcg_gen_qemu_st_i64(xsl, EA, ctx->mem_idx, MO_BEUQ);
396 }
397 tcg_temp_free(EA);
398 tcg_temp_free_i64(xsh);
399 tcg_temp_free_i64(xsl);
400 }
402 static void gen_stxvh8x(DisasContext *ctx)
403 {
404 TCGv EA;
405 TCGv_i64 xsh;
406 TCGv_i64 xsl;
408 if (unlikely(!ctx->vsx_enabled)) {
409 gen_exception(ctx, POWERPC_EXCP_VSXU);
410 return;
411 }
412 xsh = tcg_temp_new_i64();
413 xsl = tcg_temp_new_i64();
414 get_cpu_vsr(xsh, xS(ctx->opcode), true);
415 get_cpu_vsr(xsl, xS(ctx->opcode), false);
416 gen_set_access_type(ctx, ACCESS_INT);
417 EA = tcg_temp_new();
418 gen_addr_reg_index(ctx, EA);
419 if (ctx->le_mode) {
420 TCGv_i64 outh = tcg_temp_new_i64();
421 TCGv_i64 outl = tcg_temp_new_i64();
423 gen_bswap16x8(outh, outl, xsh, xsl);
424 tcg_gen_qemu_st_i64(outh, EA, ctx->mem_idx, MO_BEUQ);
425 tcg_gen_addi_tl(EA, EA, 8);
426 tcg_gen_qemu_st_i64(outl, EA, ctx->mem_idx, MO_BEUQ);
427 tcg_temp_free_i64(outh);
428 tcg_temp_free_i64(outl);
429 } else {
430 tcg_gen_qemu_st_i64(xsh, EA, ctx->mem_idx, MO_BEUQ);
431 tcg_gen_addi_tl(EA, EA, 8);
432 tcg_gen_qemu_st_i64(xsl, EA, ctx->mem_idx, MO_BEUQ);
433 }
434 tcg_temp_free(EA);
435 tcg_temp_free_i64(xsh);
436 tcg_temp_free_i64(xsl);
437 }
439 static void gen_stxvb16x(DisasContext *ctx)
440 {
441 TCGv EA;
442 TCGv_i64 xsh;
443 TCGv_i64 xsl;
445 if (unlikely(!ctx->vsx_enabled)) {
446 gen_exception(ctx, POWERPC_EXCP_VSXU);
447 return;
448 }
449 xsh = tcg_temp_new_i64();
450 xsl = tcg_temp_new_i64();
451 get_cpu_vsr(xsh, xS(ctx->opcode), true);
452 get_cpu_vsr(xsl, xS(ctx->opcode), false);
453 gen_set_access_type(ctx, ACCESS_INT);
454 EA = tcg_temp_new();
455 gen_addr_reg_index(ctx, EA);
456 tcg_gen_qemu_st_i64(xsh, EA, ctx->mem_idx, MO_BEUQ);
457 tcg_gen_addi_tl(EA, EA, 8);
458 tcg_gen_qemu_st_i64(xsl, EA, ctx->mem_idx, MO_BEUQ);
459 tcg_temp_free(EA);
460 tcg_temp_free_i64(xsh);
461 tcg_temp_free_i64(xsl);
462 }
464 #define VSX_STORE_SCALAR_DS(name, operation) \
465 static void gen_##name(DisasContext *ctx) \
466 { \
467 TCGv EA; \
468 TCGv_i64 xth; \
469 \
470 if (unlikely(!ctx->altivec_enabled)) { \
471 gen_exception(ctx, POWERPC_EXCP_VPU); \
472 return; \
473 } \
474 xth = tcg_temp_new_i64(); \
475 get_cpu_vsr(xth, rD(ctx->opcode) + 32, true); \
476 gen_set_access_type(ctx, ACCESS_INT); \
477 EA = tcg_temp_new(); \
478 gen_addr_imm_index(ctx, EA, 0x03); \
479 gen_qemu_##operation(ctx, xth, EA); \
480 /* NOTE: cpu_vsrl is undefined */ \
481 tcg_temp_free(EA); \
482 tcg_temp_free_i64(xth); \
483 }
485 VSX_STORE_SCALAR_DS(stxsd, st64_i64)
486 VSX_STORE_SCALAR_DS(stxssp, st32fs)
488 static void gen_mfvsrwz(DisasContext *ctx)
489 {
490 if (xS(ctx->opcode) < 32) {
491 if (unlikely(!ctx->fpu_enabled)) {
492 gen_exception(ctx, POWERPC_EXCP_FPU);
493 return;
494 }
495 } else {
496 if (unlikely(!ctx->altivec_enabled)) {
497 gen_exception(ctx, POWERPC_EXCP_VPU);
498 return;
499 }
500 }
501 TCGv_i64 tmp = tcg_temp_new_i64();
502 TCGv_i64 xsh = tcg_temp_new_i64();
503 get_cpu_vsr(xsh, xS(ctx->opcode), true);
504 tcg_gen_ext32u_i64(tmp, xsh);
505 tcg_gen_trunc_i64_tl(cpu_gpr[rA(ctx->opcode)], tmp);
506 tcg_temp_free_i64(tmp);
507 tcg_temp_free_i64(xsh);
508 }
510 static void gen_mtvsrwa(DisasContext *ctx)
511 {
512 if (xS(ctx->opcode) < 32) {
513 if (unlikely(!ctx->fpu_enabled)) {
514 gen_exception(ctx, POWERPC_EXCP_FPU);
515 return;
516 }
517 } else {
518 if (unlikely(!ctx->altivec_enabled)) {
519 gen_exception(ctx, POWERPC_EXCP_VPU);
520 return;
521 }
522 }
523 TCGv_i64 tmp = tcg_temp_new_i64();
524 TCGv_i64 xsh = tcg_temp_new_i64();
525 tcg_gen_extu_tl_i64(tmp, cpu_gpr[rA(ctx->opcode)]);
526 tcg_gen_ext32s_i64(xsh, tmp);
527 set_cpu_vsr(xT(ctx->opcode), xsh, true);
528 tcg_temp_free_i64(tmp);
529 tcg_temp_free_i64(xsh);
530 }
532 static void gen_mtvsrwz(DisasContext *ctx)
533 {
534 if (xS(ctx->opcode) < 32) {
535 if (unlikely(!ctx->fpu_enabled)) {
536 gen_exception(ctx, POWERPC_EXCP_FPU);
537 return;
538 }
539 } else {
540 if (unlikely(!ctx->altivec_enabled)) {
541 gen_exception(ctx, POWERPC_EXCP_VPU);
542 return;
543 }
544 }
545 TCGv_i64 tmp = tcg_temp_new_i64();
546 TCGv_i64 xsh = tcg_temp_new_i64();
547 tcg_gen_extu_tl_i64(tmp, cpu_gpr[rA(ctx->opcode)]);
548 tcg_gen_ext32u_i64(xsh, tmp);
549 set_cpu_vsr(xT(ctx->opcode), xsh, true);
550 tcg_temp_free_i64(tmp);
551 tcg_temp_free_i64(xsh);
552 }
554 #if defined(TARGET_PPC64)
555 static void gen_mfvsrd(DisasContext *ctx)
556 {
557 TCGv_i64 t0;
558 if (xS(ctx->opcode) < 32) {
559 if (unlikely(!ctx->fpu_enabled)) {
560 gen_exception(ctx, POWERPC_EXCP_FPU);
561 return;
562 }
563 } else {
564 if (unlikely(!ctx->altivec_enabled)) {
565 gen_exception(ctx, POWERPC_EXCP_VPU);
566 return;
567 }
568 }
569 t0 = tcg_temp_new_i64();
570 get_cpu_vsr(t0, xS(ctx->opcode), true);
571 tcg_gen_mov_i64(cpu_gpr[rA(ctx->opcode)], t0);
572 tcg_temp_free_i64(t0);
573 }
575 static void gen_mtvsrd(DisasContext *ctx)
576 {
577 TCGv_i64 t0;
578 if (xS(ctx->opcode) < 32) {
579 if (unlikely(!ctx->fpu_enabled)) {
580 gen_exception(ctx, POWERPC_EXCP_FPU);
581 return;
582 }
583 } else {
584 if (unlikely(!ctx->altivec_enabled)) {
585 gen_exception(ctx, POWERPC_EXCP_VPU);
586 return;
587 }
588 }
589 t0 = tcg_temp_new_i64();
590 tcg_gen_mov_i64(t0, cpu_gpr[rA(ctx->opcode)]);
591 set_cpu_vsr(xT(ctx->opcode), t0, true);
592 tcg_temp_free_i64(t0);
593 }
595 static void gen_mfvsrld(DisasContext *ctx)
596 {
597 TCGv_i64 t0;
598 if (xS(ctx->opcode) < 32) {
599 if (unlikely(!ctx->vsx_enabled)) {
600 gen_exception(ctx, POWERPC_EXCP_VSXU);
601 return;
602 }
603 } else {
604 if (unlikely(!ctx->altivec_enabled)) {
605 gen_exception(ctx, POWERPC_EXCP_VPU);
606 return;
607 }
608 }
609 t0 = tcg_temp_new_i64();
610 get_cpu_vsr(t0, xS(ctx->opcode), false);
611 tcg_gen_mov_i64(cpu_gpr[rA(ctx->opcode)], t0);
612 tcg_temp_free_i64(t0);
613 }
615 static void gen_mtvsrdd(DisasContext *ctx)
616 {
617 TCGv_i64 t0;
618 if (xT(ctx->opcode) < 32) {
619 if (unlikely(!ctx->vsx_enabled)) {
620 gen_exception(ctx, POWERPC_EXCP_VSXU);
621 return;
622 }
623 } else {
624 if (unlikely(!ctx->altivec_enabled)) {
625 gen_exception(ctx, POWERPC_EXCP_VPU);
626 return;
627 }
628 }
630 t0 = tcg_temp_new_i64();
631 if (!rA(ctx->opcode)) {
632 tcg_gen_movi_i64(t0, 0);
633 } else {
634 tcg_gen_mov_i64(t0, cpu_gpr[rA(ctx->opcode)]);
635 }
636 set_cpu_vsr(xT(ctx->opcode), t0, true);
638 tcg_gen_mov_i64(t0, cpu_gpr[rB(ctx->opcode)]);
639 set_cpu_vsr(xT(ctx->opcode), t0, false);
640 tcg_temp_free_i64(t0);
641 }
643 static void gen_mtvsrws(DisasContext *ctx)
644 {
645 TCGv_i64 t0;
646 if (xT(ctx->opcode) < 32) {
647 if (unlikely(!ctx->vsx_enabled)) {
648 gen_exception(ctx, POWERPC_EXCP_VSXU);
649 return;
650 }
651 } else {
652 if (unlikely(!ctx->altivec_enabled)) {
653 gen_exception(ctx, POWERPC_EXCP_VPU);
654 return;
655 }
656 }
658 t0 = tcg_temp_new_i64();
659 tcg_gen_deposit_i64(t0, cpu_gpr[rA(ctx->opcode)],
660 cpu_gpr[rA(ctx->opcode)], 32, 32);
661 set_cpu_vsr(xT(ctx->opcode), t0, false);
662 set_cpu_vsr(xT(ctx->opcode), t0, true);
663 tcg_temp_free_i64(t0);
664 }
666 #endif
668 #define OP_ABS 1
669 #define OP_NABS 2
670 #define OP_NEG 3
671 #define OP_CPSGN 4
672 #define SGN_MASK_DP 0x8000000000000000ull
673 #define SGN_MASK_SP 0x8000000080000000ull
675 #define VSX_SCALAR_MOVE(name, op, sgn_mask) \
676 static void glue(gen_, name)(DisasContext *ctx) \
677 { \
678 TCGv_i64 xb, sgm; \
679 if (unlikely(!ctx->vsx_enabled)) { \
680 gen_exception(ctx, POWERPC_EXCP_VSXU); \
681 return; \
682 } \
683 xb = tcg_temp_new_i64(); \
684 sgm = tcg_temp_new_i64(); \
685 get_cpu_vsr(xb, xB(ctx->opcode), true); \
686 tcg_gen_movi_i64(sgm, sgn_mask); \
687 switch (op) { \
688 case OP_ABS: { \
689 tcg_gen_andc_i64(xb, xb, sgm); \
690 break; \
691 } \
692 case OP_NABS: { \
693 tcg_gen_or_i64(xb, xb, sgm); \
694 break; \
695 } \
696 case OP_NEG: { \
697 tcg_gen_xor_i64(xb, xb, sgm); \
698 break; \
699 } \
700 case OP_CPSGN: { \
701 TCGv_i64 xa = tcg_temp_new_i64(); \
702 get_cpu_vsr(xa, xA(ctx->opcode), true); \
703 tcg_gen_and_i64(xa, xa, sgm); \
704 tcg_gen_andc_i64(xb, xb, sgm); \
705 tcg_gen_or_i64(xb, xb, xa); \
706 tcg_temp_free_i64(xa); \
707 break; \
708 } \
709 } \
710 set_cpu_vsr(xT(ctx->opcode), xb, true); \
711 set_cpu_vsr(xT(ctx->opcode), tcg_constant_i64(0), false); \
712 tcg_temp_free_i64(xb); \
713 tcg_temp_free_i64(sgm); \
714 }
716 VSX_SCALAR_MOVE(xsabsdp, OP_ABS, SGN_MASK_DP)
717 VSX_SCALAR_MOVE(xsnabsdp, OP_NABS, SGN_MASK_DP)
718 VSX_SCALAR_MOVE(xsnegdp, OP_NEG, SGN_MASK_DP)
719 VSX_SCALAR_MOVE(xscpsgndp, OP_CPSGN, SGN_MASK_DP)
721 #define VSX_SCALAR_MOVE_QP(name, op, sgn_mask) \
722 static void glue(gen_, name)(DisasContext *ctx) \
723 { \
724 int xa; \
725 int xt = rD(ctx->opcode) + 32; \
726 int xb = rB(ctx->opcode) + 32; \
727 TCGv_i64 xah, xbh, xbl, sgm, tmp; \
728 \
729 if (unlikely(!ctx->vsx_enabled)) { \
730 gen_exception(ctx, POWERPC_EXCP_VSXU); \
731 return; \
732 } \
733 xbh = tcg_temp_new_i64(); \
734 xbl = tcg_temp_new_i64(); \
735 sgm = tcg_temp_new_i64(); \
736 tmp = tcg_temp_new_i64(); \
737 get_cpu_vsr(xbh, xb, true); \
738 get_cpu_vsr(xbl, xb, false); \
739 tcg_gen_movi_i64(sgm, sgn_mask); \
740 switch (op) { \
741 case OP_ABS: \
742 tcg_gen_andc_i64(xbh, xbh, sgm); \
743 break; \
744 case OP_NABS: \
745 tcg_gen_or_i64(xbh, xbh, sgm); \
746 break; \
747 case OP_NEG: \
748 tcg_gen_xor_i64(xbh, xbh, sgm); \
749 break; \
750 case OP_CPSGN: \
751 xah = tcg_temp_new_i64(); \
752 xa = rA(ctx->opcode) + 32; \
753 get_cpu_vsr(tmp, xa, true); \
754 tcg_gen_and_i64(xah, tmp, sgm); \
755 tcg_gen_andc_i64(xbh, xbh, sgm); \
756 tcg_gen_or_i64(xbh, xbh, xah); \
757 tcg_temp_free_i64(xah); \
758 break; \
759 } \
760 set_cpu_vsr(xt, xbh, true); \
761 set_cpu_vsr(xt, xbl, false); \
762 tcg_temp_free_i64(xbl); \
763 tcg_temp_free_i64(xbh); \
764 tcg_temp_free_i64(sgm); \
765 tcg_temp_free_i64(tmp); \
766 }
768 VSX_SCALAR_MOVE_QP(xsabsqp, OP_ABS, SGN_MASK_DP)
769 VSX_SCALAR_MOVE_QP(xsnabsqp, OP_NABS, SGN_MASK_DP)
770 VSX_SCALAR_MOVE_QP(xsnegqp, OP_NEG, SGN_MASK_DP)
771 VSX_SCALAR_MOVE_QP(xscpsgnqp, OP_CPSGN, SGN_MASK_DP)
773 #define VSX_VECTOR_MOVE(name, op, sgn_mask) \
774 static void glue(gen_, name)(DisasContext *ctx) \
775 { \
776 TCGv_i64 xbh, xbl, sgm; \
777 if (unlikely(!ctx->vsx_enabled)) { \
778 gen_exception(ctx, POWERPC_EXCP_VSXU); \
779 return; \
780 } \
781 xbh = tcg_temp_new_i64(); \
782 xbl = tcg_temp_new_i64(); \
783 sgm = tcg_temp_new_i64(); \
784 get_cpu_vsr(xbh, xB(ctx->opcode), true); \
785 get_cpu_vsr(xbl, xB(ctx->opcode), false); \
786 tcg_gen_movi_i64(sgm, sgn_mask); \
787 switch (op) { \
788 case OP_ABS: { \
789 tcg_gen_andc_i64(xbh, xbh, sgm); \
790 tcg_gen_andc_i64(xbl, xbl, sgm); \
791 break; \
792 } \
793 case OP_NABS: { \
794 tcg_gen_or_i64(xbh, xbh, sgm); \
795 tcg_gen_or_i64(xbl, xbl, sgm); \
796 break; \
797 } \
798 case OP_NEG: { \
799 tcg_gen_xor_i64(xbh, xbh, sgm); \
800 tcg_gen_xor_i64(xbl, xbl, sgm); \
801 break; \
802 } \
803 case OP_CPSGN: { \
804 TCGv_i64 xah = tcg_temp_new_i64(); \
805 TCGv_i64 xal = tcg_temp_new_i64(); \
806 get_cpu_vsr(xah, xA(ctx->opcode), true); \
807 get_cpu_vsr(xal, xA(ctx->opcode), false); \
808 tcg_gen_and_i64(xah, xah, sgm); \
809 tcg_gen_and_i64(xal, xal, sgm); \
810 tcg_gen_andc_i64(xbh, xbh, sgm); \
811 tcg_gen_andc_i64(xbl, xbl, sgm); \
812 tcg_gen_or_i64(xbh, xbh, xah); \
813 tcg_gen_or_i64(xbl, xbl, xal); \
814 tcg_temp_free_i64(xah); \
815 tcg_temp_free_i64(xal); \
816 break; \
817 } \
818 } \
819 set_cpu_vsr(xT(ctx->opcode), xbh, true); \
820 set_cpu_vsr(xT(ctx->opcode), xbl, false); \
821 tcg_temp_free_i64(xbh); \
822 tcg_temp_free_i64(xbl); \
823 tcg_temp_free_i64(sgm); \
824 }
826 VSX_VECTOR_MOVE(xvabsdp, OP_ABS, SGN_MASK_DP)
827 VSX_VECTOR_MOVE(xvnabsdp, OP_NABS, SGN_MASK_DP)
828 VSX_VECTOR_MOVE(xvnegdp, OP_NEG, SGN_MASK_DP)
829 VSX_VECTOR_MOVE(xvcpsgndp, OP_CPSGN, SGN_MASK_DP)
830 VSX_VECTOR_MOVE(xvabssp, OP_ABS, SGN_MASK_SP)
831 VSX_VECTOR_MOVE(xvnabssp, OP_NABS, SGN_MASK_SP)
832 VSX_VECTOR_MOVE(xvnegsp, OP_NEG, SGN_MASK_SP)
833 VSX_VECTOR_MOVE(xvcpsgnsp, OP_CPSGN, SGN_MASK_SP)
835 #define VSX_CMP(name, op1, op2, inval, type) \
836 static void gen_##name(DisasContext *ctx) \
837 { \
838 TCGv_i32 ignored; \
839 TCGv_ptr xt, xa, xb; \
840 if (unlikely(!ctx->vsx_enabled)) { \
841 gen_exception(ctx, POWERPC_EXCP_VSXU); \
842 return; \
843 } \
844 xt = gen_vsr_ptr(xT(ctx->opcode)); \
845 xa = gen_vsr_ptr(xA(ctx->opcode)); \
846 xb = gen_vsr_ptr(xB(ctx->opcode)); \
847 if ((ctx->opcode >> (31 - 21)) & 1) { \
848 gen_helper_##name(cpu_crf[6], cpu_env, xt, xa, xb); \
849 } else { \
850 ignored = tcg_temp_new_i32(); \
851 gen_helper_##name(ignored, cpu_env, xt, xa, xb); \
852 tcg_temp_free_i32(ignored); \
853 } \
854 gen_helper_float_check_status(cpu_env); \
855 tcg_temp_free_ptr(xt); \
856 tcg_temp_free_ptr(xa); \
857 tcg_temp_free_ptr(xb); \
858 }
860 VSX_CMP(xvcmpeqdp, 0x0C, 0x0C, 0, PPC2_VSX)
861 VSX_CMP(xvcmpgedp, 0x0C, 0x0E, 0, PPC2_VSX)
862 VSX_CMP(xvcmpgtdp, 0x0C, 0x0D, 0, PPC2_VSX)
863 VSX_CMP(xvcmpnedp, 0x0C, 0x0F, 0, PPC2_ISA300)
864 VSX_CMP(xvcmpeqsp, 0x0C, 0x08, 0, PPC2_VSX)
865 VSX_CMP(xvcmpgesp, 0x0C, 0x0A, 0, PPC2_VSX)
866 VSX_CMP(xvcmpgtsp, 0x0C, 0x09, 0, PPC2_VSX)
867 VSX_CMP(xvcmpnesp, 0x0C, 0x0B, 0, PPC2_VSX)
869 static bool trans_XSCVQPDP(DisasContext *ctx, arg_X_tb_rc *a)
870 {
871 TCGv_i32 ro;
872 TCGv_ptr xt, xb;
874 REQUIRE_INSNS_FLAGS2(ctx, ISA300);
875 REQUIRE_VSX(ctx);
877 ro = tcg_const_i32(a->rc);
879 xt = gen_avr_ptr(a->rt);
880 xb = gen_avr_ptr(a->rb);
881 gen_helper_XSCVQPDP(cpu_env, ro, xt, xb);
882 tcg_temp_free_i32(ro);
883 tcg_temp_free_ptr(xt);
884 tcg_temp_free_ptr(xb);
886 return true;
887 }
889 #define GEN_VSX_HELPER_2(name, op1, op2, inval, type) \
890 static void gen_##name(DisasContext *ctx) \
891 { \
892 TCGv_i32 opc; \
893 if (unlikely(!ctx->vsx_enabled)) { \
894 gen_exception(ctx, POWERPC_EXCP_VSXU); \
895 return; \
896 } \
897 opc = tcg_const_i32(ctx->opcode); \
898 gen_helper_##name(cpu_env, opc); \
899 tcg_temp_free_i32(opc); \
900 }
902 #define GEN_VSX_HELPER_X3(name, op1, op2, inval, type) \
903 static void gen_##name(DisasContext *ctx) \
904 { \
905 TCGv_ptr xt, xa, xb; \
906 if (unlikely(!ctx->vsx_enabled)) { \
907 gen_exception(ctx, POWERPC_EXCP_VSXU); \
908 return; \
909 } \
910 xt = gen_vsr_ptr(xT(ctx->opcode)); \
911 xa = gen_vsr_ptr(xA(ctx->opcode)); \
912 xb = gen_vsr_ptr(xB(ctx->opcode)); \
913 gen_helper_##name(cpu_env, xt, xa, xb); \
914 tcg_temp_free_ptr(xt); \
915 tcg_temp_free_ptr(xa); \
916 tcg_temp_free_ptr(xb); \
917 }
919 #define GEN_VSX_HELPER_X2(name, op1, op2, inval, type) \
920 static void gen_##name(DisasContext *ctx) \
921 { \
922 TCGv_ptr xt, xb; \
923 if (unlikely(!ctx->vsx_enabled)) { \
924 gen_exception(ctx, POWERPC_EXCP_VSXU); \
925 return; \
926 } \
927 xt = gen_vsr_ptr(xT(ctx->opcode)); \
928 xb = gen_vsr_ptr(xB(ctx->opcode)); \
929 gen_helper_##name(cpu_env, xt, xb); \
930 tcg_temp_free_ptr(xt); \
931 tcg_temp_free_ptr(xb); \
932 }
934 #define GEN_VSX_HELPER_X2_AB(name, op1, op2, inval, type) \
935 static void gen_##name(DisasContext *ctx) \
936 { \
937 TCGv_i32 opc; \
938 TCGv_ptr xa, xb; \
939 if (unlikely(!ctx->vsx_enabled)) { \
940 gen_exception(ctx, POWERPC_EXCP_VSXU); \
941 return; \
942 } \
943 opc = tcg_const_i32(ctx->opcode); \
944 xa = gen_vsr_ptr(xA(ctx->opcode)); \
945 xb = gen_vsr_ptr(xB(ctx->opcode)); \
946 gen_helper_##name(cpu_env, opc, xa, xb); \
947 tcg_temp_free_i32(opc); \
948 tcg_temp_free_ptr(xa); \
949 tcg_temp_free_ptr(xb); \
950 }
952 #define GEN_VSX_HELPER_X1(name, op1, op2, inval, type) \
953 static void gen_##name(DisasContext *ctx) \
954 { \
955 TCGv_i32 opc; \
956 TCGv_ptr xb; \
957 if (unlikely(!ctx->vsx_enabled)) { \
958 gen_exception(ctx, POWERPC_EXCP_VSXU); \
959 return; \
960 } \
961 opc = tcg_const_i32(ctx->opcode); \
962 xb = gen_vsr_ptr(xB(ctx->opcode)); \
963 gen_helper_##name(cpu_env, opc, xb); \
964 tcg_temp_free_i32(opc); \
965 tcg_temp_free_ptr(xb); \
966 }
968 #define GEN_VSX_HELPER_R3(name, op1, op2, inval, type) \
969 static void gen_##name(DisasContext *ctx) \
970 { \
971 TCGv_i32 opc; \
972 TCGv_ptr xt, xa, xb; \
973 if (unlikely(!ctx->vsx_enabled)) { \
974 gen_exception(ctx, POWERPC_EXCP_VSXU); \
975 return; \
976 } \
977 opc = tcg_const_i32(ctx->opcode); \
978 xt = gen_vsr_ptr(rD(ctx->opcode) + 32); \
979 xa = gen_vsr_ptr(rA(ctx->opcode) + 32); \
980 xb = gen_vsr_ptr(rB(ctx->opcode) + 32); \
981 gen_helper_##name(cpu_env, opc, xt, xa, xb); \
982 tcg_temp_free_i32(opc); \
983 tcg_temp_free_ptr(xt); \
984 tcg_temp_free_ptr(xa); \
985 tcg_temp_free_ptr(xb); \
986 }
988 #define GEN_VSX_HELPER_R2(name, op1, op2, inval, type) \
989 static void gen_##name(DisasContext *ctx) \
990 { \
991 TCGv_i32 opc; \
992 TCGv_ptr xt, xb; \
993 if (unlikely(!ctx->vsx_enabled)) { \
994 gen_exception(ctx, POWERPC_EXCP_VSXU); \
995 return; \
996 } \
997 opc = tcg_const_i32(ctx->opcode); \
998 xt = gen_vsr_ptr(rD(ctx->opcode) + 32); \
999 xb = gen_vsr_ptr(rB(ctx->opcode) + 32); \
1000 gen_helper_##name(cpu_env, opc, xt, xb); \
1001 tcg_temp_free_i32(opc); \
1002 tcg_temp_free_ptr(xt); \
1003 tcg_temp_free_ptr(xb); \
1004 }
1006 #define GEN_VSX_HELPER_R2_AB(name, op1, op2, inval, type) \
1007 static void gen_##name(DisasContext *ctx) \
1008 { \
1009 TCGv_i32 opc; \
1010 TCGv_ptr xa, xb; \
1011 if (unlikely(!ctx->vsx_enabled)) { \
1012 gen_exception(ctx, POWERPC_EXCP_VSXU); \
1013 return; \
1014 } \
1015 opc = tcg_const_i32(ctx->opcode); \
1016 xa = gen_vsr_ptr(rA(ctx->opcode) + 32); \
1017 xb = gen_vsr_ptr(rB(ctx->opcode) + 32); \
1018 gen_helper_##name(cpu_env, opc, xa, xb); \
1019 tcg_temp_free_i32(opc); \
1020 tcg_temp_free_ptr(xa); \
1021 tcg_temp_free_ptr(xb); \
1022 }
1024 #define GEN_VSX_HELPER_XT_XB_ENV(name, op1, op2, inval, type) \
1025 static void gen_##name(DisasContext *ctx) \
1026 { \
1027 TCGv_i64 t0; \
1028 TCGv_i64 t1; \
1029 if (unlikely(!ctx->vsx_enabled)) { \
1030 gen_exception(ctx, POWERPC_EXCP_VSXU); \
1031 return; \
1032 } \
1033 t0 = tcg_temp_new_i64(); \
1034 t1 = tcg_temp_new_i64(); \
1035 get_cpu_vsr(t0, xB(ctx->opcode), true); \
1036 gen_helper_##name(t1, cpu_env, t0); \
1037 set_cpu_vsr(xT(ctx->opcode), t1, true); \
1038 set_cpu_vsr(xT(ctx->opcode), tcg_constant_i64(0), false); \
1039 tcg_temp_free_i64(t0); \
1040 tcg_temp_free_i64(t1); \
1041 }
1043 GEN_VSX_HELPER_X3(xsadddp, 0x00, 0x04, 0, PPC2_VSX)
1044 GEN_VSX_HELPER_R3(xsaddqp, 0x04, 0x00, 0, PPC2_ISA300)
1045 GEN_VSX_HELPER_X3(xssubdp, 0x00, 0x05, 0, PPC2_VSX)
1046 GEN_VSX_HELPER_X3(xsmuldp, 0x00, 0x06, 0, PPC2_VSX)
1047 GEN_VSX_HELPER_R3(xsmulqp, 0x04, 0x01, 0, PPC2_ISA300)
1048 GEN_VSX_HELPER_X3(xsdivdp, 0x00, 0x07, 0, PPC2_VSX)
1049 GEN_VSX_HELPER_R3(xsdivqp, 0x04, 0x11, 0, PPC2_ISA300)
1050 GEN_VSX_HELPER_X2(xsredp, 0x14, 0x05, 0, PPC2_VSX)
1051 GEN_VSX_HELPER_X2(xssqrtdp, 0x16, 0x04, 0, PPC2_VSX)
1052 GEN_VSX_HELPER_X2(xsrsqrtedp, 0x14, 0x04, 0, PPC2_VSX)
1053 GEN_VSX_HELPER_X2_AB(xstdivdp, 0x14, 0x07, 0, PPC2_VSX)
1054 GEN_VSX_HELPER_X1(xstsqrtdp, 0x14, 0x06, 0, PPC2_VSX)
1055 GEN_VSX_HELPER_X3(xscmpeqdp, 0x0C, 0x00, 0, PPC2_ISA300)
1056 GEN_VSX_HELPER_X3(xscmpgtdp, 0x0C, 0x01, 0, PPC2_ISA300)
1057 GEN_VSX_HELPER_X3(xscmpgedp, 0x0C, 0x02, 0, PPC2_ISA300)
1058 GEN_VSX_HELPER_X3(xscmpnedp, 0x0C, 0x03, 0, PPC2_ISA300)
1059 GEN_VSX_HELPER_X2_AB(xscmpexpdp, 0x0C, 0x07, 0, PPC2_ISA300)
1060 GEN_VSX_HELPER_R2_AB(xscmpexpqp, 0x04, 0x05, 0, PPC2_ISA300)
1061 GEN_VSX_HELPER_X2_AB(xscmpodp, 0x0C, 0x05, 0, PPC2_VSX)
1062 GEN_VSX_HELPER_X2_AB(xscmpudp, 0x0C, 0x04, 0, PPC2_VSX)
1063 GEN_VSX_HELPER_R2_AB(xscmpoqp, 0x04, 0x04, 0, PPC2_VSX)
1064 GEN_VSX_HELPER_R2_AB(xscmpuqp, 0x04, 0x14, 0, PPC2_VSX)
1065 GEN_VSX_HELPER_X3(xsmaxdp, 0x00, 0x14, 0, PPC2_VSX)
1066 GEN_VSX_HELPER_X3(xsmindp, 0x00, 0x15, 0, PPC2_VSX)
1067 GEN_VSX_HELPER_X2(xscvdphp, 0x16, 0x15, 0x11, PPC2_ISA300)
1068 GEN_VSX_HELPER_X2(xscvdpsp, 0x12, 0x10, 0, PPC2_VSX)
1069 GEN_VSX_HELPER_R2(xscvdpqp, 0x04, 0x1A, 0x16, PPC2_ISA300)
1070 GEN_VSX_HELPER_XT_XB_ENV(xscvdpspn, 0x16, 0x10, 0, PPC2_VSX207)
1071 GEN_VSX_HELPER_R2(xscvqpsdz, 0x04, 0x1A, 0x19, PPC2_ISA300)
1072 GEN_VSX_HELPER_R2(xscvqpswz, 0x04, 0x1A, 0x09, PPC2_ISA300)
1073 GEN_VSX_HELPER_R2(xscvqpudz, 0x04, 0x1A, 0x11, PPC2_ISA300)
1074 GEN_VSX_HELPER_R2(xscvqpuwz, 0x04, 0x1A, 0x01, PPC2_ISA300)
1075 GEN_VSX_HELPER_X2(xscvhpdp, 0x16, 0x15, 0x10, PPC2_ISA300)
1076 GEN_VSX_HELPER_R2(xscvsdqp, 0x04, 0x1A, 0x0A, PPC2_ISA300)
1077 GEN_VSX_HELPER_X2(xscvspdp, 0x12, 0x14, 0, PPC2_VSX)
1078 GEN_VSX_HELPER_XT_XB_ENV(xscvspdpn, 0x16, 0x14, 0, PPC2_VSX207)
1079 GEN_VSX_HELPER_X2(xscvdpsxds, 0x10, 0x15, 0, PPC2_VSX)
1080 GEN_VSX_HELPER_X2(xscvdpsxws, 0x10, 0x05, 0, PPC2_VSX)
1081 GEN_VSX_HELPER_X2(xscvdpuxds, 0x10, 0x14, 0, PPC2_VSX)
1082 GEN_VSX_HELPER_X2(xscvdpuxws, 0x10, 0x04, 0, PPC2_VSX)
1083 GEN_VSX_HELPER_X2(xscvsxddp, 0x10, 0x17, 0, PPC2_VSX)
1084 GEN_VSX_HELPER_R2(xscvudqp, 0x04, 0x1A, 0x02, PPC2_ISA300)
1085 GEN_VSX_HELPER_X2(xscvuxddp, 0x10, 0x16, 0, PPC2_VSX)
1086 GEN_VSX_HELPER_X2(xsrdpi, 0x12, 0x04, 0, PPC2_VSX)
1087 GEN_VSX_HELPER_X2(xsrdpic, 0x16, 0x06, 0, PPC2_VSX)
1088 GEN_VSX_HELPER_X2(xsrdpim, 0x12, 0x07, 0, PPC2_VSX)
1089 GEN_VSX_HELPER_X2(xsrdpip, 0x12, 0x06, 0, PPC2_VSX)
1090 GEN_VSX_HELPER_X2(xsrdpiz, 0x12, 0x05, 0, PPC2_VSX)
1091 GEN_VSX_HELPER_XT_XB_ENV(xsrsp, 0x12, 0x11, 0, PPC2_VSX207)
1092 GEN_VSX_HELPER_R2(xsrqpi, 0x05, 0x00, 0, PPC2_ISA300)
1093 GEN_VSX_HELPER_R2(xsrqpxp, 0x05, 0x01, 0, PPC2_ISA300)
1094 GEN_VSX_HELPER_R2(xssqrtqp, 0x04, 0x19, 0x1B, PPC2_ISA300)
1095 GEN_VSX_HELPER_R3(xssubqp, 0x04, 0x10, 0, PPC2_ISA300)
1096 GEN_VSX_HELPER_X3(xsaddsp, 0x00, 0x00, 0, PPC2_VSX207)
1097 GEN_VSX_HELPER_X3(xssubsp, 0x00, 0x01, 0, PPC2_VSX207)
1098 GEN_VSX_HELPER_X3(xsmulsp, 0x00, 0x02, 0, PPC2_VSX207)
1099 GEN_VSX_HELPER_X3(xsdivsp, 0x00, 0x03, 0, PPC2_VSX207)
1100 GEN_VSX_HELPER_X2(xsresp, 0x14, 0x01, 0, PPC2_VSX207)
1101 GEN_VSX_HELPER_X2(xssqrtsp, 0x16, 0x00, 0, PPC2_VSX207)
1102 GEN_VSX_HELPER_X2(xsrsqrtesp, 0x14, 0x00, 0, PPC2_VSX207)
1103 GEN_VSX_HELPER_X2(xscvsxdsp, 0x10, 0x13, 0, PPC2_VSX207)
1104 GEN_VSX_HELPER_X2(xscvuxdsp, 0x10, 0x12, 0, PPC2_VSX207)
1105 GEN_VSX_HELPER_X1(xststdcsp, 0x14, 0x12, 0, PPC2_ISA300)
1106 GEN_VSX_HELPER_2(xststdcdp, 0x14, 0x16, 0, PPC2_ISA300)
1107 GEN_VSX_HELPER_2(xststdcqp, 0x04, 0x16, 0, PPC2_ISA300)
1109 GEN_VSX_HELPER_X3(xvadddp, 0x00, 0x0C, 0, PPC2_VSX)
1110 GEN_VSX_HELPER_X3(xvsubdp, 0x00, 0x0D, 0, PPC2_VSX)
1111 GEN_VSX_HELPER_X3(xvmuldp, 0x00, 0x0E, 0, PPC2_VSX)
1112 GEN_VSX_HELPER_X3(xvdivdp, 0x00, 0x0F, 0, PPC2_VSX)
1113 GEN_VSX_HELPER_X2(xvredp, 0x14, 0x0D, 0, PPC2_VSX)
1114 GEN_VSX_HELPER_X2(xvsqrtdp, 0x16, 0x0C, 0, PPC2_VSX)
1115 GEN_VSX_HELPER_X2(xvrsqrtedp, 0x14, 0x0C, 0, PPC2_VSX)
1116 GEN_VSX_HELPER_X2_AB(xvtdivdp, 0x14, 0x0F, 0, PPC2_VSX)
1117 GEN_VSX_HELPER_X1(xvtsqrtdp, 0x14, 0x0E, 0, PPC2_VSX)
1118 GEN_VSX_HELPER_X3(xvmaxdp, 0x00, 0x1C, 0, PPC2_VSX)
1119 GEN_VSX_HELPER_X3(xvmindp, 0x00, 0x1D, 0, PPC2_VSX)
1120 GEN_VSX_HELPER_X2(xvcvdpsp, 0x12, 0x18, 0, PPC2_VSX)
1121 GEN_VSX_HELPER_X2(xvcvdpsxds, 0x10, 0x1D, 0, PPC2_VSX)
1122 GEN_VSX_HELPER_X2(xvcvdpsxws, 0x10, 0x0D, 0, PPC2_VSX)
1123 GEN_VSX_HELPER_X2(xvcvdpuxds, 0x10, 0x1C, 0, PPC2_VSX)
1124 GEN_VSX_HELPER_X2(xvcvdpuxws, 0x10, 0x0C, 0, PPC2_VSX)
1125 GEN_VSX_HELPER_X2(xvcvsxddp, 0x10, 0x1F, 0, PPC2_VSX)
1126 GEN_VSX_HELPER_X2(xvcvuxddp, 0x10, 0x1E, 0, PPC2_VSX)
1127 GEN_VSX_HELPER_X2(xvcvsxwdp, 0x10, 0x0F, 0, PPC2_VSX)
1128 GEN_VSX_HELPER_X2(xvcvuxwdp, 0x10, 0x0E, 0, PPC2_VSX)
1129 GEN_VSX_HELPER_X2(xvrdpi, 0x12, 0x0C, 0, PPC2_VSX)
1130 GEN_VSX_HELPER_X2(xvrdpic, 0x16, 0x0E, 0, PPC2_VSX)
1131 GEN_VSX_HELPER_X2(xvrdpim, 0x12, 0x0F, 0, PPC2_VSX)
1132 GEN_VSX_HELPER_X2(xvrdpip, 0x12, 0x0E, 0, PPC2_VSX)
1133 GEN_VSX_HELPER_X2(xvrdpiz, 0x12, 0x0D, 0, PPC2_VSX)
1135 GEN_VSX_HELPER_X3(xvaddsp, 0x00, 0x08, 0, PPC2_VSX)
1136 GEN_VSX_HELPER_X3(xvsubsp, 0x00, 0x09, 0, PPC2_VSX)
1137 GEN_VSX_HELPER_X3(xvmulsp, 0x00, 0x0A, 0, PPC2_VSX)
1138 GEN_VSX_HELPER_X3(xvdivsp, 0x00, 0x0B, 0, PPC2_VSX)
1139 GEN_VSX_HELPER_X2(xvresp, 0x14, 0x09, 0, PPC2_VSX)
1140 GEN_VSX_HELPER_X2(xvsqrtsp, 0x16, 0x08, 0, PPC2_VSX)
1141 GEN_VSX_HELPER_X2(xvrsqrtesp, 0x14, 0x08, 0, PPC2_VSX)
1142 GEN_VSX_HELPER_X2_AB(xvtdivsp, 0x14, 0x0B, 0, PPC2_VSX)
1143 GEN_VSX_HELPER_X1(xvtsqrtsp, 0x14, 0x0A, 0, PPC2_VSX)
1144 GEN_VSX_HELPER_X3(xvmaxsp, 0x00, 0x18, 0, PPC2_VSX)
1145 GEN_VSX_HELPER_X3(xvminsp, 0x00, 0x19, 0, PPC2_VSX)
1146 GEN_VSX_HELPER_X2(xvcvspdp, 0x12, 0x1C, 0, PPC2_VSX)
1147 GEN_VSX_HELPER_X2(xvcvhpsp, 0x16, 0x1D, 0x18, PPC2_ISA300)
1148 GEN_VSX_HELPER_X2(xvcvsphp, 0x16, 0x1D, 0x19, PPC2_ISA300)
1149 GEN_VSX_HELPER_X2(xvcvspsxds, 0x10, 0x19, 0, PPC2_VSX)
1150 GEN_VSX_HELPER_X2(xvcvspsxws, 0x10, 0x09, 0, PPC2_VSX)
1151 GEN_VSX_HELPER_X2(xvcvspuxds, 0x10, 0x18, 0, PPC2_VSX)
1152 GEN_VSX_HELPER_X2(xvcvspuxws, 0x10, 0x08, 0, PPC2_VSX)
1153 GEN_VSX_HELPER_X2(xvcvsxdsp, 0x10, 0x1B, 0, PPC2_VSX)
1154 GEN_VSX_HELPER_X2(xvcvuxdsp, 0x10, 0x1A, 0, PPC2_VSX)
1155 GEN_VSX_HELPER_X2(xvcvsxwsp, 0x10, 0x0B, 0, PPC2_VSX)
1156 GEN_VSX_HELPER_X2(xvcvuxwsp, 0x10, 0x0A, 0, PPC2_VSX)
1157 GEN_VSX_HELPER_X2(xvrspi, 0x12, 0x08, 0, PPC2_VSX)
1158 GEN_VSX_HELPER_X2(xvrspic, 0x16, 0x0A, 0, PPC2_VSX)
1159 GEN_VSX_HELPER_X2(xvrspim, 0x12, 0x0B, 0, PPC2_VSX)
1160 GEN_VSX_HELPER_X2(xvrspip, 0x12, 0x0A, 0, PPC2_VSX)
1161 GEN_VSX_HELPER_X2(xvrspiz, 0x12, 0x09, 0, PPC2_VSX)
1162 GEN_VSX_HELPER_2(xvtstdcsp, 0x14, 0x1A, 0, PPC2_VSX)
1163 GEN_VSX_HELPER_2(xvtstdcdp, 0x14, 0x1E, 0, PPC2_VSX)
1165 static bool trans_XXPERM(DisasContext *ctx, arg_XX3 *a)
1166 {
1167 TCGv_ptr xt, xa, xb;
1169 REQUIRE_INSNS_FLAGS2(ctx, ISA300);
1170 REQUIRE_VSX(ctx);
1172 xt = gen_vsr_ptr(a->xt);
1173 xa = gen_vsr_ptr(a->xa);
1174 xb = gen_vsr_ptr(a->xb);
1176 gen_helper_VPERM(xt, xa, xt, xb);
1178 tcg_temp_free_ptr(xt);
1179 tcg_temp_free_ptr(xa);
1180 tcg_temp_free_ptr(xb);
1182 return true;
1183 }
1185 static bool trans_XXPERMR(DisasContext *ctx, arg_XX3 *a)
1186 {
1187 TCGv_ptr xt, xa, xb;
1189 REQUIRE_INSNS_FLAGS2(ctx, ISA300);
1190 REQUIRE_VSX(ctx);
1192 xt = gen_vsr_ptr(a->xt);
1193 xa = gen_vsr_ptr(a->xa);
1194 xb = gen_vsr_ptr(a->xb);
1196 gen_helper_VPERMR(xt, xa, xt, xb);
1198 tcg_temp_free_ptr(xt);
1199 tcg_temp_free_ptr(xa);
1200 tcg_temp_free_ptr(xb);
1202 return true;
1203 }
1205 static bool trans_XXPERMDI(DisasContext *ctx, arg_XX3_dm *a)
1206 {
1207 TCGv_i64 t0, t1;
1209 REQUIRE_INSNS_FLAGS2(ctx, VSX);
1210 REQUIRE_VSX(ctx);
1212 t0 = tcg_temp_new_i64();
1214 if (unlikely(a->xt == a->xa || a->xt == a->xb)) {
1215 t1 = tcg_temp_new_i64();
1217 get_cpu_vsr(t0, a->xa, (a->dm & 2) == 0);
1218 get_cpu_vsr(t1, a->xb, (a->dm & 1) == 0);
1220 set_cpu_vsr(a->xt, t0, true);
1221 set_cpu_vsr(a->xt, t1, false);
1223 tcg_temp_free_i64(t1);
1224 } else {
1225 get_cpu_vsr(t0, a->xa, (a->dm & 2) == 0);
1226 set_cpu_vsr(a->xt, t0, true);
1228 get_cpu_vsr(t0, a->xb, (a->dm & 1) == 0);
1229 set_cpu_vsr(a->xt, t0, false);
1230 }
1232 tcg_temp_free_i64(t0);
1234 return true;
1235 }
1237 static bool trans_XXPERMX(DisasContext *ctx, arg_8RR_XX4_uim3 *a)
1238 {
1239 TCGv_ptr xt, xa, xb, xc;
1241 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
1242 REQUIRE_VSX(ctx);
1244 xt = gen_vsr_ptr(a->xt);
1245 xa = gen_vsr_ptr(a->xa);
1246 xb = gen_vsr_ptr(a->xb);
1247 xc = gen_vsr_ptr(a->xc);
1249 gen_helper_XXPERMX(xt, xa, xb, xc, tcg_constant_tl(a->uim3));
1251 tcg_temp_free_ptr(xt);
1252 tcg_temp_free_ptr(xa);
1253 tcg_temp_free_ptr(xb);
1254 tcg_temp_free_ptr(xc);
1256 return true;
1257 }
1259 #define XXGENPCV(NAME) \
1260 static bool trans_##NAME(DisasContext *ctx, arg_X_imm5 *a) \
1261 { \
1262 TCGv_ptr xt, vrb; \
1263 \
1264 REQUIRE_INSNS_FLAGS2(ctx, ISA310); \
1265 REQUIRE_VSX(ctx); \
1266 \
1267 if (a->imm & ~0x3) { \
1268 gen_invalid(ctx); \
1269 return true; \
1270 } \
1271 \
1272 xt = gen_vsr_ptr(a->xt); \
1273 vrb = gen_avr_ptr(a->vrb); \
1274 \
1275 switch (a->imm) { \
1276 case 0b00000: /* Big-Endian expansion */ \
1277 glue(gen_helper_, glue(NAME, _be_exp))(xt, vrb); \
1278 break; \
1279 case 0b00001: /* Big-Endian compression */ \
1280 glue(gen_helper_, glue(NAME, _be_comp))(xt, vrb); \
1281 break; \
1282 case 0b00010: /* Little-Endian expansion */ \
1283 glue(gen_helper_, glue(NAME, _le_exp))(xt, vrb); \
1284 break; \
1285 case 0b00011: /* Little-Endian compression */ \
1286 glue(gen_helper_, glue(NAME, _le_comp))(xt, vrb); \
1287 break; \
1288 } \
1289 \
1290 tcg_temp_free_ptr(xt); \
1291 tcg_temp_free_ptr(vrb); \
1292 \
1293 return true; \
1294 }
1296 XXGENPCV(XXGENPCVBM)
1297 XXGENPCV(XXGENPCVHM)
1298 XXGENPCV(XXGENPCVWM)
1299 XXGENPCV(XXGENPCVDM)
1300 #undef XXGENPCV
1302 #define GEN_VSX_HELPER_VSX_MADD(name, op1, aop, mop, inval, type) \
1303 static void gen_##name(DisasContext *ctx) \
1304 { \
1305 TCGv_ptr xt, xa, b, c; \
1306 if (unlikely(!ctx->vsx_enabled)) { \
1307 gen_exception(ctx, POWERPC_EXCP_VSXU); \
1308 return; \
1309 } \
1310 xt = gen_vsr_ptr(xT(ctx->opcode)); \
1311 xa = gen_vsr_ptr(xA(ctx->opcode)); \
1312 if (ctx->opcode & PPC_BIT32(25)) { \
1313 /* \
1314 * AxT + B \
1315 */ \
1316 b = gen_vsr_ptr(xT(ctx->opcode)); \
1317 c = gen_vsr_ptr(xB(ctx->opcode)); \
1318 } else { \
1319 /* \
1320 * AxB + T \
1321 */ \
1322 b = gen_vsr_ptr(xB(ctx->opcode)); \
1323 c = gen_vsr_ptr(xT(ctx->opcode)); \
1324 } \
1325 gen_helper_##name(cpu_env, xt, xa, b, c); \
1326 tcg_temp_free_ptr(xt); \
1327 tcg_temp_free_ptr(xa); \
1328 tcg_temp_free_ptr(b); \
1329 tcg_temp_free_ptr(c); \
1330 }
1332 GEN_VSX_HELPER_VSX_MADD(xsmadddp, 0x04, 0x04, 0x05, 0, PPC2_VSX)
1333 GEN_VSX_HELPER_VSX_MADD(xsmsubdp, 0x04, 0x06, 0x07, 0, PPC2_VSX)
1334 GEN_VSX_HELPER_VSX_MADD(xsnmadddp, 0x04, 0x14, 0x15, 0, PPC2_VSX)
1335 GEN_VSX_HELPER_VSX_MADD(xsnmsubdp, 0x04, 0x16, 0x17, 0, PPC2_VSX)
1336 GEN_VSX_HELPER_VSX_MADD(xsmaddsp, 0x04, 0x00, 0x01, 0, PPC2_VSX207)
1337 GEN_VSX_HELPER_VSX_MADD(xsmsubsp, 0x04, 0x02, 0x03, 0, PPC2_VSX207)
1338 GEN_VSX_HELPER_VSX_MADD(xsnmaddsp, 0x04, 0x10, 0x11, 0, PPC2_VSX207)
1339 GEN_VSX_HELPER_VSX_MADD(xsnmsubsp, 0x04, 0x12, 0x13, 0, PPC2_VSX207)
1340 GEN_VSX_HELPER_VSX_MADD(xvmadddp, 0x04, 0x0C, 0x0D, 0, PPC2_VSX)
1341 GEN_VSX_HELPER_VSX_MADD(xvmsubdp, 0x04, 0x0E, 0x0F, 0, PPC2_VSX)
1342 GEN_VSX_HELPER_VSX_MADD(xvnmadddp, 0x04, 0x1C, 0x1D, 0, PPC2_VSX)
1343 GEN_VSX_HELPER_VSX_MADD(xvnmsubdp, 0x04, 0x1E, 0x1F, 0, PPC2_VSX)
1344 GEN_VSX_HELPER_VSX_MADD(xvmaddsp, 0x04, 0x08, 0x09, 0, PPC2_VSX)
1345 GEN_VSX_HELPER_VSX_MADD(xvmsubsp, 0x04, 0x0A, 0x0B, 0, PPC2_VSX)
1346 GEN_VSX_HELPER_VSX_MADD(xvnmaddsp, 0x04, 0x18, 0x19, 0, PPC2_VSX)
1347 GEN_VSX_HELPER_VSX_MADD(xvnmsubsp, 0x04, 0x1A, 0x1B, 0, PPC2_VSX)
1349 static void gen_xxbrd(DisasContext *ctx)
1350 {
1351 TCGv_i64 xth;
1352 TCGv_i64 xtl;
1353 TCGv_i64 xbh;
1354 TCGv_i64 xbl;
1356 if (unlikely(!ctx->vsx_enabled)) {
1357 gen_exception(ctx, POWERPC_EXCP_VSXU);
1358 return;
1359 }
1360 xth = tcg_temp_new_i64();
1361 xtl = tcg_temp_new_i64();
1362 xbh = tcg_temp_new_i64();
1363 xbl = tcg_temp_new_i64();
1364 get_cpu_vsr(xbh, xB(ctx->opcode), true);
1365 get_cpu_vsr(xbl, xB(ctx->opcode), false);
1367 tcg_gen_bswap64_i64(xth, xbh);
1368 tcg_gen_bswap64_i64(xtl, xbl);
1369 set_cpu_vsr(xT(ctx->opcode), xth, true);
1370 set_cpu_vsr(xT(ctx->opcode), xtl, false);
1372 tcg_temp_free_i64(xth);
1373 tcg_temp_free_i64(xtl);
1374 tcg_temp_free_i64(xbh);
1375 tcg_temp_free_i64(xbl);
1376 }
1378 static void gen_xxbrh(DisasContext *ctx)
1379 {
1380 TCGv_i64 xth;
1381 TCGv_i64 xtl;
1382 TCGv_i64 xbh;
1383 TCGv_i64 xbl;
1385 if (unlikely(!ctx->vsx_enabled)) {
1386 gen_exception(ctx, POWERPC_EXCP_VSXU);
1387 return;
1388 }
1389 xth = tcg_temp_new_i64();
1390 xtl = tcg_temp_new_i64();
1391 xbh = tcg_temp_new_i64();
1392 xbl = tcg_temp_new_i64();
1393 get_cpu_vsr(xbh, xB(ctx->opcode), true);
1394 get_cpu_vsr(xbl, xB(ctx->opcode), false);
1396 gen_bswap16x8(xth, xtl, xbh, xbl);
1397 set_cpu_vsr(xT(ctx->opcode), xth, true);
1398 set_cpu_vsr(xT(ctx->opcode), xtl, false);
1400 tcg_temp_free_i64(xth);
1401 tcg_temp_free_i64(xtl);
1402 tcg_temp_free_i64(xbh);
1403 tcg_temp_free_i64(xbl);
1404 }
1406 static void gen_xxbrq(DisasContext *ctx)
1407 {
1408 TCGv_i64 xth;
1409 TCGv_i64 xtl;
1410 TCGv_i64 xbh;
1411 TCGv_i64 xbl;
1412 TCGv_i64 t0;
1414 if (unlikely(!ctx->vsx_enabled)) {
1415 gen_exception(ctx, POWERPC_EXCP_VSXU);
1416 return;
1417 }
1418 xth = tcg_temp_new_i64();
1419 xtl = tcg_temp_new_i64();
1420 xbh = tcg_temp_new_i64();
1421 xbl = tcg_temp_new_i64();
1422 get_cpu_vsr(xbh, xB(ctx->opcode), true);
1423 get_cpu_vsr(xbl, xB(ctx->opcode), false);
1424 t0 = tcg_temp_new_i64();
1426 tcg_gen_bswap64_i64(t0, xbl);
1427 tcg_gen_bswap64_i64(xtl, xbh);
1428 set_cpu_vsr(xT(ctx->opcode), xtl, false);
1429 tcg_gen_mov_i64(xth, t0);
1430 set_cpu_vsr(xT(ctx->opcode), xth, true);
1432 tcg_temp_free_i64(t0);
1433 tcg_temp_free_i64(xth);
1434 tcg_temp_free_i64(xtl);
1435 tcg_temp_free_i64(xbh);
1436 tcg_temp_free_i64(xbl);
1437 }
1439 static void gen_xxbrw(DisasContext *ctx)
1440 {
1441 TCGv_i64 xth;
1442 TCGv_i64 xtl;
1443 TCGv_i64 xbh;
1444 TCGv_i64 xbl;
1446 if (unlikely(!ctx->vsx_enabled)) {
1447 gen_exception(ctx, POWERPC_EXCP_VSXU);
1448 return;
1449 }
1450 xth = tcg_temp_new_i64();
1451 xtl = tcg_temp_new_i64();
1452 xbh = tcg_temp_new_i64();
1453 xbl = tcg_temp_new_i64();
1454 get_cpu_vsr(xbh, xB(ctx->opcode), true);
1455 get_cpu_vsr(xbl, xB(ctx->opcode), false);
1457 gen_bswap32x4(xth, xtl, xbh, xbl);
1458 set_cpu_vsr(xT(ctx->opcode), xth, true);
1459 set_cpu_vsr(xT(ctx->opcode), xtl, false);
1461 tcg_temp_free_i64(xth);
1462 tcg_temp_free_i64(xtl);
1463 tcg_temp_free_i64(xbh);
1464 tcg_temp_free_i64(xbl);
1465 }
1467 #define VSX_LOGICAL(name, vece, tcg_op) \
1468 static void glue(gen_, name)(DisasContext *ctx) \
1469 { \
1470 if (unlikely(!ctx->vsx_enabled)) { \
1471 gen_exception(ctx, POWERPC_EXCP_VSXU); \
1472 return; \
1473 } \
1474 tcg_op(vece, vsr_full_offset(xT(ctx->opcode)), \
1475 vsr_full_offset(xA(ctx->opcode)), \
1476 vsr_full_offset(xB(ctx->opcode)), 16, 16); \
1477 }
1479 VSX_LOGICAL(xxland, MO_64, tcg_gen_gvec_and)
1480 VSX_LOGICAL(xxlandc, MO_64, tcg_gen_gvec_andc)
1481 VSX_LOGICAL(xxlor, MO_64, tcg_gen_gvec_or)
1482 VSX_LOGICAL(xxlxor, MO_64, tcg_gen_gvec_xor)
1483 VSX_LOGICAL(xxlnor, MO_64, tcg_gen_gvec_nor)
1484 VSX_LOGICAL(xxleqv, MO_64, tcg_gen_gvec_eqv)
1485 VSX_LOGICAL(xxlnand, MO_64, tcg_gen_gvec_nand)
1486 VSX_LOGICAL(xxlorc, MO_64, tcg_gen_gvec_orc)
1488 #define VSX_XXMRG(name, high) \
1489 static void glue(gen_, name)(DisasContext *ctx) \
1490 { \
1491 TCGv_i64 a0, a1, b0, b1, tmp; \
1492 if (unlikely(!ctx->vsx_enabled)) { \
1493 gen_exception(ctx, POWERPC_EXCP_VSXU); \
1494 return; \
1495 } \
1496 a0 = tcg_temp_new_i64(); \
1497 a1 = tcg_temp_new_i64(); \
1498 b0 = tcg_temp_new_i64(); \
1499 b1 = tcg_temp_new_i64(); \
1500 tmp = tcg_temp_new_i64(); \
1501 get_cpu_vsr(a0, xA(ctx->opcode), high); \
1502 get_cpu_vsr(a1, xA(ctx->opcode), high); \
1503 get_cpu_vsr(b0, xB(ctx->opcode), high); \
1504 get_cpu_vsr(b1, xB(ctx->opcode), high); \
1505 tcg_gen_shri_i64(a0, a0, 32); \
1506 tcg_gen_shri_i64(b0, b0, 32); \
1507 tcg_gen_deposit_i64(tmp, b0, a0, 32, 32); \
1508 set_cpu_vsr(xT(ctx->opcode), tmp, true); \
1509 tcg_gen_deposit_i64(tmp, b1, a1, 32, 32); \
1510 set_cpu_vsr(xT(ctx->opcode), tmp, false); \
1511 tcg_temp_free_i64(a0); \
1512 tcg_temp_free_i64(a1); \
1513 tcg_temp_free_i64(b0); \
1514 tcg_temp_free_i64(b1); \
1515 tcg_temp_free_i64(tmp); \
1516 }
1518 VSX_XXMRG(xxmrghw, 1)
1519 VSX_XXMRG(xxmrglw, 0)
1521 static bool trans_XXSEL(DisasContext *ctx, arg_XX4 *a)
1522 {
1523 REQUIRE_INSNS_FLAGS2(ctx, VSX);
1524 REQUIRE_VSX(ctx);
1526 tcg_gen_gvec_bitsel(MO_64, vsr_full_offset(a->xt), vsr_full_offset(a->xc),
1527 vsr_full_offset(a->xb), vsr_full_offset(a->xa), 16, 16);
1529 return true;
1530 }
1532 static bool trans_XXSPLTW(DisasContext *ctx, arg_XX2 *a)
1533 {
1534 int tofs, bofs;
1536 REQUIRE_VSX(ctx);
1538 tofs = vsr_full_offset(a->xt);
1539 bofs = vsr_full_offset(a->xb);
1540 bofs += a->uim << MO_32;
1541 #ifndef HOST_WORDS_BIG_ENDIAN
1542 bofs ^= 8 | 4;
1543 #endif
1545 tcg_gen_gvec_dup_mem(MO_32, tofs, bofs, 16, 16);
1546 return true;
1547 }
1549 #define pattern(x) (((x) & 0xff) * (~(uint64_t)0 / 0xff))
1551 static bool trans_XXSPLTIB(DisasContext *ctx, arg_X_imm8 *a)
1552 {
1553 if (a->xt < 32) {
1554 REQUIRE_VSX(ctx);
1555 } else {
1556 REQUIRE_VECTOR(ctx);
1557 }
1558 tcg_gen_gvec_dup_imm(MO_8, vsr_full_offset(a->xt), 16, 16, a->imm);
1559 return true;
1560 }
1562 static bool trans_XXSPLTIW(DisasContext *ctx, arg_8RR_D *a)
1563 {
1564 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
1565 REQUIRE_VSX(ctx);
1567 tcg_gen_gvec_dup_imm(MO_32, vsr_full_offset(a->xt), 16, 16, a->si);
1569 return true;
1570 }
1572 static bool trans_XXSPLTIDP(DisasContext *ctx, arg_8RR_D *a)
1573 {
1574 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
1575 REQUIRE_VSX(ctx);
1577 tcg_gen_gvec_dup_imm(MO_64, vsr_full_offset(a->xt), 16, 16,
1578 helper_todouble(a->si));
1579 return true;
1580 }
1582 static bool trans_XXSPLTI32DX(DisasContext *ctx, arg_8RR_D_IX *a)
1583 {
1584 TCGv_i32 imm;
1586 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
1587 REQUIRE_VSX(ctx);
1589 imm = tcg_constant_i32(a->si);
1591 tcg_gen_st_i32(imm, cpu_env,
1592 offsetof(CPUPPCState, vsr[a->xt].VsrW(0 + a->ix)));
1593 tcg_gen_st_i32(imm, cpu_env,
1594 offsetof(CPUPPCState, vsr[a->xt].VsrW(2 + a->ix)));
1596 return true;
1597 }
1599 static bool trans_LXVKQ(DisasContext *ctx, arg_X_uim5 *a)
1600 {
1601 static const uint64_t values[32] = {
1602 0, /* Unspecified */
1603 0x3FFF000000000000llu, /* QP +1.0 */
1604 0x4000000000000000llu, /* QP +2.0 */
1605 0x4000800000000000llu, /* QP +3.0 */
1606 0x4001000000000000llu, /* QP +4.0 */
1607 0x4001400000000000llu, /* QP +5.0 */
1608 0x4001800000000000llu, /* QP +6.0 */
1609 0x4001C00000000000llu, /* QP +7.0 */
1610 0x7FFF000000000000llu, /* QP +Inf */
1611 0x7FFF800000000000llu, /* QP dQNaN */
1612 0, /* Unspecified */
1613 0, /* Unspecified */
1614 0, /* Unspecified */
1615 0, /* Unspecified */
1616 0, /* Unspecified */
1617 0, /* Unspecified */
1618 0x8000000000000000llu, /* QP -0.0 */
1619 0xBFFF000000000000llu, /* QP -1.0 */
1620 0xC000000000000000llu, /* QP -2.0 */
1621 0xC000800000000000llu, /* QP -3.0 */
1622 0xC001000000000000llu, /* QP -4.0 */
1623 0xC001400000000000llu, /* QP -5.0 */
1624 0xC001800000000000llu, /* QP -6.0 */
1625 0xC001C00000000000llu, /* QP -7.0 */
1626 0xFFFF000000000000llu, /* QP -Inf */
1627 };
1629 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
1630 REQUIRE_VSX(ctx);
1632 if (values[a->uim]) {
1633 set_cpu_vsr(a->xt, tcg_constant_i64(0x0), false);
1634 set_cpu_vsr(a->xt, tcg_constant_i64(values[a->uim]), true);
1635 } else {
1636 gen_invalid(ctx);
1637 }
1639 return true;
1640 }
1642 static void gen_xxsldwi(DisasContext *ctx)
1643 {
1644 TCGv_i64 xth, xtl;
1645 if (unlikely(!ctx->vsx_enabled)) {
1646 gen_exception(ctx, POWERPC_EXCP_VSXU);
1647 return;
1648 }
1649 xth = tcg_temp_new_i64();
1650 xtl = tcg_temp_new_i64();
1652 switch (SHW(ctx->opcode)) {
1653 case 0: {
1654 get_cpu_vsr(xth, xA(ctx->opcode), true);
1655 get_cpu_vsr(xtl, xA(ctx->opcode), false);
1656 break;
1657 }
1658 case 1: {
1659 TCGv_i64 t0 = tcg_temp_new_i64();
1660 get_cpu_vsr(xth, xA(ctx->opcode), true);
1661 tcg_gen_shli_i64(xth, xth, 32);
1662 get_cpu_vsr(t0, xA(ctx->opcode), false);
1663 tcg_gen_shri_i64(t0, t0, 32);
1664 tcg_gen_or_i64(xth, xth, t0);
1665 get_cpu_vsr(xtl, xA(ctx->opcode), false);
1666 tcg_gen_shli_i64(xtl, xtl, 32);
1667 get_cpu_vsr(t0, xB(ctx->opcode), true);
1668 tcg_gen_shri_i64(t0, t0, 32);
1669 tcg_gen_or_i64(xtl, xtl, t0);
1670 tcg_temp_free_i64(t0);
1671 break;
1672 }
1673 case 2: {
1674 get_cpu_vsr(xth, xA(ctx->opcode), false);
1675 get_cpu_vsr(xtl, xB(ctx->opcode), true);
1676 break;
1677 }
1678 case 3: {
1679 TCGv_i64 t0 = tcg_temp_new_i64();
1680 get_cpu_vsr(xth, xA(ctx->opcode), false);
1681 tcg_gen_shli_i64(xth, xth, 32);
1682 get_cpu_vsr(t0, xB(ctx->opcode), true);
1683 tcg_gen_shri_i64(t0, t0, 32);
1684 tcg_gen_or_i64(xth, xth, t0);
1685 get_cpu_vsr(xtl, xB(ctx->opcode), true);
1686 tcg_gen_shli_i64(xtl, xtl, 32);
1687 get_cpu_vsr(t0, xB(ctx->opcode), false);
1688 tcg_gen_shri_i64(t0, t0, 32);
1689 tcg_gen_or_i64(xtl, xtl, t0);
1690 tcg_temp_free_i64(t0);
1691 break;
1692 }
1693 }
1695 set_cpu_vsr(xT(ctx->opcode), xth, true);
1696 set_cpu_vsr(xT(ctx->opcode), xtl, false);
1698 tcg_temp_free_i64(xth);
1699 tcg_temp_free_i64(xtl);
1700 }
1702 #define VSX_EXTRACT_INSERT(name) \
1703 static void gen_##name(DisasContext *ctx) \
1704 { \
1705 TCGv_ptr xt, xb; \
1706 TCGv_i32 t0; \
1707 TCGv_i64 t1; \
1708 uint8_t uimm = UIMM4(ctx->opcode); \
1709 \
1710 if (unlikely(!ctx->vsx_enabled)) { \
1711 gen_exception(ctx, POWERPC_EXCP_VSXU); \
1712 return; \
1713 } \
1714 xt = gen_vsr_ptr(xT(ctx->opcode)); \
1715 xb = gen_vsr_ptr(xB(ctx->opcode)); \
1716 t0 = tcg_temp_new_i32(); \
1717 t1 = tcg_temp_new_i64(); \
1718 /* \
1719 * uimm > 15 out of bound and for \
1720 * uimm > 12 handle as per hardware in helper \
1721 */ \
1722 if (uimm > 15) { \
1723 tcg_gen_movi_i64(t1, 0); \
1724 set_cpu_vsr(xT(ctx->opcode), t1, true); \
1725 set_cpu_vsr(xT(ctx->opcode), t1, false); \
1726 return; \
1727 } \
1728 tcg_gen_movi_i32(t0, uimm); \
1729 gen_helper_##name(cpu_env, xt, xb, t0); \
1730 tcg_temp_free_ptr(xb); \
1731 tcg_temp_free_ptr(xt); \
1732 tcg_temp_free_i32(t0); \
1733 tcg_temp_free_i64(t1); \
1734 }
1736 VSX_EXTRACT_INSERT(xxextractuw)
1737 VSX_EXTRACT_INSERT(xxinsertw)
1739 #ifdef TARGET_PPC64
1740 static void gen_xsxexpdp(DisasContext *ctx)
1741 {
1742 TCGv rt = cpu_gpr[rD(ctx->opcode)];
1743 TCGv_i64 t0;
1744 if (unlikely(!ctx->vsx_enabled)) {
1745 gen_exception(ctx, POWERPC_EXCP_VSXU);
1746 return;
1747 }
1748 t0 = tcg_temp_new_i64();
1749 get_cpu_vsr(t0, xB(ctx->opcode), true);
1750 tcg_gen_extract_i64(rt, t0, 52, 11);
1751 tcg_temp_free_i64(t0);
1752 }
1754 static void gen_xsxexpqp(DisasContext *ctx)
1755 {
1756 TCGv_i64 xth;
1757 TCGv_i64 xtl;
1758 TCGv_i64 xbh;
1760 if (unlikely(!ctx->vsx_enabled)) {
1761 gen_exception(ctx, POWERPC_EXCP_VSXU);
1762 return;
1763 }
1764 xth = tcg_temp_new_i64();
1765 xtl = tcg_temp_new_i64();
1766 xbh = tcg_temp_new_i64();
1767 get_cpu_vsr(xbh, rB(ctx->opcode) + 32, true);
1769 tcg_gen_extract_i64(xth, xbh, 48, 15);
1770 set_cpu_vsr(rD(ctx->opcode) + 32, xth, true);
1771 tcg_gen_movi_i64(xtl, 0);
1772 set_cpu_vsr(rD(ctx->opcode) + 32, xtl, false);
1774 tcg_temp_free_i64(xbh);
1775 tcg_temp_free_i64(xth);
1776 tcg_temp_free_i64(xtl);
1777 }
1779 static void gen_xsiexpdp(DisasContext *ctx)
1780 {
1781 TCGv_i64 xth;
1782 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1783 TCGv rb = cpu_gpr[rB(ctx->opcode)];
1784 TCGv_i64 t0;
1786 if (unlikely(!ctx->vsx_enabled)) {
1787 gen_exception(ctx, POWERPC_EXCP_VSXU);
1788 return;
1789 }
1790 t0 = tcg_temp_new_i64();
1791 xth = tcg_temp_new_i64();
1792 tcg_gen_andi_i64(xth, ra, 0x800FFFFFFFFFFFFF);
1793 tcg_gen_andi_i64(t0, rb, 0x7FF);
1794 tcg_gen_shli_i64(t0, t0, 52);
1795 tcg_gen_or_i64(xth, xth, t0);
1796 set_cpu_vsr(xT(ctx->opcode), xth, true);
1797 set_cpu_vsr(xT(ctx->opcode), tcg_constant_i64(0), false);
1798 tcg_temp_free_i64(t0);
1799 tcg_temp_free_i64(xth);
1800 }
1802 static void gen_xsiexpqp(DisasContext *ctx)
1803 {
1804 TCGv_i64 xth;
1805 TCGv_i64 xtl;
1806 TCGv_i64 xah;
1807 TCGv_i64 xal;
1808 TCGv_i64 xbh;
1809 TCGv_i64 t0;
1811 if (unlikely(!ctx->vsx_enabled)) {
1812 gen_exception(ctx, POWERPC_EXCP_VSXU);
1813 return;
1814 }
1815 xth = tcg_temp_new_i64();
1816 xtl = tcg_temp_new_i64();
1817 xah = tcg_temp_new_i64();
1818 xal = tcg_temp_new_i64();
1819 get_cpu_vsr(xah, rA(ctx->opcode) + 32, true);
1820 get_cpu_vsr(xal, rA(ctx->opcode) + 32, false);
1821 xbh = tcg_temp_new_i64();
1822 get_cpu_vsr(xbh, rB(ctx->opcode) + 32, true);
1823 t0 = tcg_temp_new_i64();
1825 tcg_gen_andi_i64(xth, xah, 0x8000FFFFFFFFFFFF);
1826 tcg_gen_andi_i64(t0, xbh, 0x7FFF);
1827 tcg_gen_shli_i64(t0, t0, 48);
1828 tcg_gen_or_i64(xth, xth, t0);
1829 set_cpu_vsr(rD(ctx->opcode) + 32, xth, true);
1830 tcg_gen_mov_i64(xtl, xal);
1831 set_cpu_vsr(rD(ctx->opcode) + 32, xtl, false);
1833 tcg_temp_free_i64(t0);
1834 tcg_temp_free_i64(xth);
1835 tcg_temp_free_i64(xtl);
1836 tcg_temp_free_i64(xah);
1837 tcg_temp_free_i64(xal);
1838 tcg_temp_free_i64(xbh);
1839 }
1841 static void gen_xsxsigdp(DisasContext *ctx)
1842 {
1843 TCGv rt = cpu_gpr[rD(ctx->opcode)];
1844 TCGv_i64 t0, t1, zr, nan, exp;
1846 if (unlikely(!ctx->vsx_enabled)) {
1847 gen_exception(ctx, POWERPC_EXCP_VSXU);
1848 return;
1849 }
1850 exp = tcg_temp_new_i64();
1851 t0 = tcg_temp_new_i64();
1852 t1 = tcg_temp_new_i64();
1853 zr = tcg_const_i64(0);
1854 nan = tcg_const_i64(2047);
1856 get_cpu_vsr(t1, xB(ctx->opcode), true);
1857 tcg_gen_extract_i64(exp, t1, 52, 11);
1858 tcg_gen_movi_i64(t0, 0x0010000000000000);
1859 tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, zr, zr, t0);
1860 tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, nan, zr, t0);
1861 get_cpu_vsr(t1, xB(ctx->opcode), true);
1862 tcg_gen_deposit_i64(rt, t0, t1, 0, 52);
1864 tcg_temp_free_i64(t0);
1865 tcg_temp_free_i64(t1);
1866 tcg_temp_free_i64(exp);
1867 tcg_temp_free_i64(zr);
1868 tcg_temp_free_i64(nan);
1869 }
1871 static void gen_xsxsigqp(DisasContext *ctx)
1872 {
1873 TCGv_i64 t0, zr, nan, exp;
1874 TCGv_i64 xth;
1875 TCGv_i64 xtl;
1876 TCGv_i64 xbh;
1877 TCGv_i64 xbl;
1879 if (unlikely(!ctx->vsx_enabled)) {
1880 gen_exception(ctx, POWERPC_EXCP_VSXU);
1881 return;
1882 }
1883 xth = tcg_temp_new_i64();
1884 xtl = tcg_temp_new_i64();
1885 xbh = tcg_temp_new_i64();
1886 xbl = tcg_temp_new_i64();
1887 get_cpu_vsr(xbh, rB(ctx->opcode) + 32, true);
1888 get_cpu_vsr(xbl, rB(ctx->opcode) + 32, false);
1889 exp = tcg_temp_new_i64();
1890 t0 = tcg_temp_new_i64();
1891 zr = tcg_const_i64(0);
1892 nan = tcg_const_i64(32767);
1894 tcg_gen_extract_i64(exp, xbh, 48, 15);
1895 tcg_gen_movi_i64(t0, 0x0001000000000000);
1896 tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, zr, zr, t0);
1897 tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, nan, zr, t0);
1898 tcg_gen_deposit_i64(xth, t0, xbh, 0, 48);
1899 set_cpu_vsr(rD(ctx->opcode) + 32, xth, true);
1900 tcg_gen_mov_i64(xtl, xbl);
1901 set_cpu_vsr(rD(ctx->opcode) + 32, xtl, false);
1903 tcg_temp_free_i64(t0);
1904 tcg_temp_free_i64(exp);
1905 tcg_temp_free_i64(zr);
1906 tcg_temp_free_i64(nan);
1907 tcg_temp_free_i64(xth);
1908 tcg_temp_free_i64(xtl);
1909 tcg_temp_free_i64(xbh);
1910 tcg_temp_free_i64(xbl);
1911 }
1912 #endif
1914 static void gen_xviexpsp(DisasContext *ctx)
1915 {
1916 TCGv_i64 xth;
1917 TCGv_i64 xtl;
1918 TCGv_i64 xah;
1919 TCGv_i64 xal;
1920 TCGv_i64 xbh;
1921 TCGv_i64 xbl;
1922 TCGv_i64 t0;
1924 if (unlikely(!ctx->vsx_enabled)) {
1925 gen_exception(ctx, POWERPC_EXCP_VSXU);
1926 return;
1927 }
1928 xth = tcg_temp_new_i64();
1929 xtl = tcg_temp_new_i64();
1930 xah = tcg_temp_new_i64();
1931 xal = tcg_temp_new_i64();
1932 xbh = tcg_temp_new_i64();
1933 xbl = tcg_temp_new_i64();
1934 get_cpu_vsr(xah, xA(ctx->opcode), true);
1935 get_cpu_vsr(xal, xA(ctx->opcode), false);
1936 get_cpu_vsr(xbh, xB(ctx->opcode), true);
1937 get_cpu_vsr(xbl, xB(ctx->opcode), false);
1938 t0 = tcg_temp_new_i64();
1940 tcg_gen_andi_i64(xth, xah, 0x807FFFFF807FFFFF);
1941 tcg_gen_andi_i64(t0, xbh, 0xFF000000FF);
1942 tcg_gen_shli_i64(t0, t0, 23);
1943 tcg_gen_or_i64(xth, xth, t0);
1944 set_cpu_vsr(xT(ctx->opcode), xth, true);
1945 tcg_gen_andi_i64(xtl, xal, 0x807FFFFF807FFFFF);
1946 tcg_gen_andi_i64(t0, xbl, 0xFF000000FF);
1947 tcg_gen_shli_i64(t0, t0, 23);
1948 tcg_gen_or_i64(xtl, xtl, t0);
1949 set_cpu_vsr(xT(ctx->opcode), xtl, false);
1951 tcg_temp_free_i64(t0);
1952 tcg_temp_free_i64(xth);
1953 tcg_temp_free_i64(xtl);
1954 tcg_temp_free_i64(xah);
1955 tcg_temp_free_i64(xal);
1956 tcg_temp_free_i64(xbh);
1957 tcg_temp_free_i64(xbl);
1958 }
1960 static void gen_xviexpdp(DisasContext *ctx)
1961 {
1962 TCGv_i64 xth;
1963 TCGv_i64 xtl;
1964 TCGv_i64 xah;
1965 TCGv_i64 xal;
1966 TCGv_i64 xbh;
1967 TCGv_i64 xbl;
1969 if (unlikely(!ctx->vsx_enabled)) {
1970 gen_exception(ctx, POWERPC_EXCP_VSXU);
1971 return;
1972 }
1973 xth = tcg_temp_new_i64();
1974 xtl = tcg_temp_new_i64();
1975 xah = tcg_temp_new_i64();
1976 xal = tcg_temp_new_i64();
1977 xbh = tcg_temp_new_i64();
1978 xbl = tcg_temp_new_i64();
1979 get_cpu_vsr(xah, xA(ctx->opcode), true);
1980 get_cpu_vsr(xal, xA(ctx->opcode), false);
1981 get_cpu_vsr(xbh, xB(ctx->opcode), true);
1982 get_cpu_vsr(xbl, xB(ctx->opcode), false);
1984 tcg_gen_deposit_i64(xth, xah, xbh, 52, 11);
1985 set_cpu_vsr(xT(ctx->opcode), xth, true);
1987 tcg_gen_deposit_i64(xtl, xal, xbl, 52, 11);
1988 set_cpu_vsr(xT(ctx->opcode), xtl, false);
1990 tcg_temp_free_i64(xth);
1991 tcg_temp_free_i64(xtl);
1992 tcg_temp_free_i64(xah);
1993 tcg_temp_free_i64(xal);
1994 tcg_temp_free_i64(xbh);
1995 tcg_temp_free_i64(xbl);
1996 }
1998 static void gen_xvxexpsp(DisasContext *ctx)
1999 {
2000 TCGv_i64 xth;
2001 TCGv_i64 xtl;
2002 TCGv_i64 xbh;
2003 TCGv_i64 xbl;
2005 if (unlikely(!ctx->vsx_enabled)) {
2006 gen_exception(ctx, POWERPC_EXCP_VSXU);
2007 return;
2008 }
2009 xth = tcg_temp_new_i64();
2010 xtl = tcg_temp_new_i64();
2011 xbh = tcg_temp_new_i64();
2012 xbl = tcg_temp_new_i64();
2013 get_cpu_vsr(xbh, xB(ctx->opcode), true);
2014 get_cpu_vsr(xbl, xB(ctx->opcode), false);
2016 tcg_gen_shri_i64(xth, xbh, 23);
2017 tcg_gen_andi_i64(xth, xth, 0xFF000000FF);
2018 set_cpu_vsr(xT(ctx->opcode), xth, true);
2019 tcg_gen_shri_i64(xtl, xbl, 23);
2020 tcg_gen_andi_i64(xtl, xtl, 0xFF000000FF);
2021 set_cpu_vsr(xT(ctx->opcode), xtl, false);
2023 tcg_temp_free_i64(xth);
2024 tcg_temp_free_i64(xtl);
2025 tcg_temp_free_i64(xbh);
2026 tcg_temp_free_i64(xbl);
2027 }
2029 static void gen_xvxexpdp(DisasContext *ctx)
2030 {
2031 TCGv_i64 xth;
2032 TCGv_i64 xtl;
2033 TCGv_i64 xbh;
2034 TCGv_i64 xbl;
2036 if (unlikely(!ctx->vsx_enabled)) {
2037 gen_exception(ctx, POWERPC_EXCP_VSXU);
2038 return;
2039 }
2040 xth = tcg_temp_new_i64();
2041 xtl = tcg_temp_new_i64();
2042 xbh = tcg_temp_new_i64();
2043 xbl = tcg_temp_new_i64();
2044 get_cpu_vsr(xbh, xB(ctx->opcode), true);
2045 get_cpu_vsr(xbl, xB(ctx->opcode), false);
2047 tcg_gen_extract_i64(xth, xbh, 52, 11);
2048 set_cpu_vsr(xT(ctx->opcode), xth, true);
2049 tcg_gen_extract_i64(xtl, xbl, 52, 11);
2050 set_cpu_vsr(xT(ctx->opcode), xtl, false);
2052 tcg_temp_free_i64(xth);
2053 tcg_temp_free_i64(xtl);
2054 tcg_temp_free_i64(xbh);
2055 tcg_temp_free_i64(xbl);
2056 }
2058 GEN_VSX_HELPER_X2(xvxsigsp, 0x00, 0x04, 0, PPC2_ISA300)
2060 static void gen_xvxsigdp(DisasContext *ctx)
2061 {
2062 TCGv_i64 xth;
2063 TCGv_i64 xtl;
2064 TCGv_i64 xbh;
2065 TCGv_i64 xbl;
2066 TCGv_i64 t0, zr, nan, exp;
2068 if (unlikely(!ctx->vsx_enabled)) {
2069 gen_exception(ctx, POWERPC_EXCP_VSXU);
2070 return;
2071 }
2072 xth = tcg_temp_new_i64();
2073 xtl = tcg_temp_new_i64();
2074 xbh = tcg_temp_new_i64();
2075 xbl = tcg_temp_new_i64();
2076 get_cpu_vsr(xbh, xB(ctx->opcode), true);
2077 get_cpu_vsr(xbl, xB(ctx->opcode), false);
2078 exp = tcg_temp_new_i64();
2079 t0 = tcg_temp_new_i64();
2080 zr = tcg_const_i64(0);
2081 nan = tcg_const_i64(2047);
2083 tcg_gen_extract_i64(exp, xbh, 52, 11);
2084 tcg_gen_movi_i64(t0, 0x0010000000000000);
2085 tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, zr, zr, t0);
2086 tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, nan, zr, t0);
2087 tcg_gen_deposit_i64(xth, t0, xbh, 0, 52);
2088 set_cpu_vsr(xT(ctx->opcode), xth, true);
2090 tcg_gen_extract_i64(exp, xbl, 52, 11);
2091 tcg_gen_movi_i64(t0, 0x0010000000000000);
2092 tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, zr, zr, t0);
2093 tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, nan, zr, t0);
2094 tcg_gen_deposit_i64(xtl, t0, xbl, 0, 52);
2095 set_cpu_vsr(xT(ctx->opcode), xtl, false);
2097 tcg_temp_free_i64(t0);
2098 tcg_temp_free_i64(exp);
2099 tcg_temp_free_i64(zr);
2100 tcg_temp_free_i64(nan);
2101 tcg_temp_free_i64(xth);
2102 tcg_temp_free_i64(xtl);
2103 tcg_temp_free_i64(xbh);
2104 tcg_temp_free_i64(xbl);
2105 }
2107 static bool do_lstxv(DisasContext *ctx, int ra, TCGv displ,
2108 int rt, bool store, bool paired)
2109 {
2110 TCGv ea;
2111 TCGv_i64 xt;
2112 MemOp mop;
2113 int rt1, rt2;
2115 xt = tcg_temp_new_i64();
2117 mop = DEF_MEMOP(MO_UQ);
2119 gen_set_access_type(ctx, ACCESS_INT);
2120 ea = do_ea_calc(ctx, ra, displ);
2122 if (paired && ctx->le_mode) {
2123 rt1 = rt + 1;
2124 rt2 = rt;
2125 } else {
2126 rt1 = rt;
2127 rt2 = rt + 1;
2128 }
2130 if (store) {
2131 get_cpu_vsr(xt, rt1, !ctx->le_mode);
2132 tcg_gen_qemu_st_i64(xt, ea, ctx->mem_idx, mop);
2133 gen_addr_add(ctx, ea, ea, 8);
2134 get_cpu_vsr(xt, rt1, ctx->le_mode);
2135 tcg_gen_qemu_st_i64(xt, ea, ctx->mem_idx, mop);
2136 if (paired) {
2137 gen_addr_add(ctx, ea, ea, 8);
2138 get_cpu_vsr(xt, rt2, !ctx->le_mode);
2139 tcg_gen_qemu_st_i64(xt, ea, ctx->mem_idx, mop);
2140 gen_addr_add(ctx, ea, ea, 8);
2141 get_cpu_vsr(xt, rt2, ctx->le_mode);
2142 tcg_gen_qemu_st_i64(xt, ea, ctx->mem_idx, mop);
2143 }
2144 } else {
2145 tcg_gen_qemu_ld_i64(xt, ea, ctx->mem_idx, mop);
2146 set_cpu_vsr(rt1, xt, !ctx->le_mode);
2147 gen_addr_add(ctx, ea, ea, 8);
2148 tcg_gen_qemu_ld_i64(xt, ea, ctx->mem_idx, mop);
2149 set_cpu_vsr(rt1, xt, ctx->le_mode);
2150 if (paired) {
2151 gen_addr_add(ctx, ea, ea, 8);
2152 tcg_gen_qemu_ld_i64(xt, ea, ctx->mem_idx, mop);
2153 set_cpu_vsr(rt2, xt, !ctx->le_mode);
2154 gen_addr_add(ctx, ea, ea, 8);
2155 tcg_gen_qemu_ld_i64(xt, ea, ctx->mem_idx, mop);
2156 set_cpu_vsr(rt2, xt, ctx->le_mode);
2157 }
2158 }
2160 tcg_temp_free(ea);
2161 tcg_temp_free_i64(xt);
2162 return true;
2163 }
2165 static bool do_lstxv_D(DisasContext *ctx, arg_D *a, bool store, bool paired)
2166 {
2167 if (paired || a->rt >= 32) {
2168 REQUIRE_VSX(ctx);
2169 } else {
2170 REQUIRE_VECTOR(ctx);
2171 }
2173 return do_lstxv(ctx, a->ra, tcg_constant_tl(a->si), a->rt, store, paired);
2174 }
2176 static bool do_lstxv_PLS_D(DisasContext *ctx, arg_PLS_D *a,
2177 bool store, bool paired)
2178 {
2179 arg_D d;
2180 REQUIRE_VSX(ctx);
2182 if (!resolve_PLS_D(ctx, &d, a)) {
2183 return true;
2184 }
2186 return do_lstxv(ctx, d.ra, tcg_constant_tl(d.si), d.rt, store, paired);
2187 }
2189 static bool do_lstxv_X(DisasContext *ctx, arg_X *a, bool store, bool paired)
2190 {
2191 if (paired || a->rt >= 32) {
2192 REQUIRE_VSX(ctx);
2193 } else {
2194 REQUIRE_VECTOR(ctx);
2195 }
2197 return do_lstxv(ctx, a->ra, cpu_gpr[a->rb], a->rt, store, paired);
2198 }
2200 TRANS_FLAGS2(ISA300, STXV, do_lstxv_D, true, false)
2201 TRANS_FLAGS2(ISA300, LXV, do_lstxv_D, false, false)
2202 TRANS_FLAGS2(ISA310, STXVP, do_lstxv_D, true, true)
2203 TRANS_FLAGS2(ISA310, LXVP, do_lstxv_D, false, true)
2204 TRANS_FLAGS2(ISA300, STXVX, do_lstxv_X, true, false)
2205 TRANS_FLAGS2(ISA300, LXVX, do_lstxv_X, false, false)
2206 TRANS_FLAGS2(ISA310, STXVPX, do_lstxv_X, true, true)
2207 TRANS_FLAGS2(ISA310, LXVPX, do_lstxv_X, false, true)
2208 TRANS64_FLAGS2(ISA310, PSTXV, do_lstxv_PLS_D, true, false)
2209 TRANS64_FLAGS2(ISA310, PLXV, do_lstxv_PLS_D, false, false)
2210 TRANS64_FLAGS2(ISA310, PSTXVP, do_lstxv_PLS_D, true, true)
2211 TRANS64_FLAGS2(ISA310, PLXVP, do_lstxv_PLS_D, false, true)
2213 static void gen_xxeval_i64(TCGv_i64 t, TCGv_i64 a, TCGv_i64 b, TCGv_i64 c,
2214 int64_t imm)
2215 {
2216 /*
2217 * Instead of processing imm bit-by-bit, we'll skip the computation of
2218 * conjunctions whose corresponding bit is unset.
2219 */
2220 int bit;
2221 TCGv_i64 conj, disj;
2223 conj = tcg_temp_new_i64();
2224 disj = tcg_const_i64(0);
2226 /* Iterate over set bits from the least to the most significant bit */
2227 while (imm) {
2228 /*
2229 * Get the next bit to be processed with ctz64. Invert the result of
2230 * ctz64 to match the indexing used by PowerISA.
2231 */
2232 bit = 7 - ctz64(imm);
2233 if (bit & 0x4) {
2234 tcg_gen_mov_i64(conj, a);
2235 } else {
2236 tcg_gen_not_i64(conj, a);
2237 }
2238 if (bit & 0x2) {
2239 tcg_gen_and_i64(conj, conj, b);
2240 } else {
2241 tcg_gen_andc_i64(conj, conj, b);
2242 }
2243 if (bit & 0x1) {
2244 tcg_gen_and_i64(conj, conj, c);
2245 } else {
2246 tcg_gen_andc_i64(conj, conj, c);
2247 }
2248 tcg_gen_or_i64(disj, disj, conj);
2250 /* Unset the least significant bit that is set */
2251 imm &= imm - 1;
2252 }
2254 tcg_gen_mov_i64(t, disj);
2256 tcg_temp_free_i64(conj);
2257 tcg_temp_free_i64(disj);
2258 }
2260 static void gen_xxeval_vec(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b,
2261 TCGv_vec c, int64_t imm)
2262 {
2263 /*
2264 * Instead of processing imm bit-by-bit, we'll skip the computation of
2265 * conjunctions whose corresponding bit is unset.
2266 */
2267 int bit;
2268 TCGv_vec disj, conj;
2270 disj = tcg_const_zeros_vec_matching(t);
2271 conj = tcg_temp_new_vec_matching(t);
2273 /* Iterate over set bits from the least to the most significant bit */
2274 while (imm) {
2275 /*
2276 * Get the next bit to be processed with ctz64. Invert the result of
2277 * ctz64 to match the indexing used by PowerISA.
2278 */
2279 bit = 7 - ctz64(imm);
2280 if (bit & 0x4) {
2281 tcg_gen_mov_vec(conj, a);
2282 } else {
2283 tcg_gen_not_vec(vece, conj, a);
2284 }
2285 if (bit & 0x2) {
2286 tcg_gen_and_vec(vece, conj, conj, b);
2287 } else {
2288 tcg_gen_andc_vec(vece, conj, conj, b);
2289 }
2290 if (bit & 0x1) {
2291 tcg_gen_and_vec(vece, conj, conj, c);
2292 } else {
2293 tcg_gen_andc_vec(vece, conj, conj, c);
2294 }
2295 tcg_gen_or_vec(vece, disj, disj, conj);
2297 /* Unset the least significant bit that is set */
2298 imm &= imm - 1;
2299 }
2301 tcg_gen_mov_vec(t, disj);
2303 tcg_temp_free_vec(disj);
2304 tcg_temp_free_vec(conj);
2305 }
2307 static bool trans_XXEVAL(DisasContext *ctx, arg_8RR_XX4_imm *a)
2308 {
2309 static const TCGOpcode vecop_list[] = {
2310 INDEX_op_andc_vec, 0
2311 };
2312 static const GVecGen4i op = {
2313 .fniv = gen_xxeval_vec,
2314 .fno = gen_helper_XXEVAL,
2315 .fni8 = gen_xxeval_i64,
2316 .opt_opc = vecop_list,
2317 .vece = MO_64
2318 };
2319 int xt = vsr_full_offset(a->xt), xa = vsr_full_offset(a->xa),
2320 xb = vsr_full_offset(a->xb), xc = vsr_full_offset(a->xc);
2322 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
2323 REQUIRE_VSX(ctx);
2325 /* Equivalent functions that can be implemented with a single gen_gvec */
2326 switch (a->imm) {
2327 case 0b00000000: /* true */
2328 set_cpu_vsr(a->xt, tcg_constant_i64(0), true);
2329 set_cpu_vsr(a->xt, tcg_constant_i64(0), false);
2330 break;
2331 case 0b00000011: /* and(B,A) */
2332 tcg_gen_gvec_and(MO_64, xt, xb, xa, 16, 16);
2333 break;
2334 case 0b00000101: /* and(C,A) */
2335 tcg_gen_gvec_and(MO_64, xt, xc, xa, 16, 16);
2336 break;
2337 case 0b00001111: /* A */
2338 tcg_gen_gvec_mov(MO_64, xt, xa, 16, 16);
2339 break;
2340 case 0b00010001: /* and(C,B) */
2341 tcg_gen_gvec_and(MO_64, xt, xc, xb, 16, 16);
2342 break;
2343 case 0b00011011: /* C?B:A */
2344 tcg_gen_gvec_bitsel(MO_64, xt, xc, xb, xa, 16, 16);
2345 break;
2346 case 0b00011101: /* B?C:A */
2347 tcg_gen_gvec_bitsel(MO_64, xt, xb, xc, xa, 16, 16);
2348 break;
2349 case 0b00100111: /* C?A:B */
2350 tcg_gen_gvec_bitsel(MO_64, xt, xc, xa, xb, 16, 16);
2351 break;
2352 case 0b00110011: /* B */
2353 tcg_gen_gvec_mov(MO_64, xt, xb, 16, 16);
2354 break;
2355 case 0b00110101: /* A?C:B */
2356 tcg_gen_gvec_bitsel(MO_64, xt, xa, xc, xb, 16, 16);
2357 break;
2358 case 0b00111100: /* xor(B,A) */
2359 tcg_gen_gvec_xor(MO_64, xt, xb, xa, 16, 16);
2360 break;
2361 case 0b00111111: /* or(B,A) */
2362 tcg_gen_gvec_or(MO_64, xt, xb, xa, 16, 16);
2363 break;
2364 case 0b01000111: /* B?A:C */
2365 tcg_gen_gvec_bitsel(MO_64, xt, xb, xa, xc, 16, 16);
2366 break;
2367 case 0b01010011: /* A?B:C */
2368 tcg_gen_gvec_bitsel(MO_64, xt, xa, xb, xc, 16, 16);
2369 break;
2370 case 0b01010101: /* C */
2371 tcg_gen_gvec_mov(MO_64, xt, xc, 16, 16);
2372 break;
2373 case 0b01011010: /* xor(C,A) */
2374 tcg_gen_gvec_xor(MO_64, xt, xc, xa, 16, 16);
2375 break;
2376 case 0b01011111: /* or(C,A) */
2377 tcg_gen_gvec_or(MO_64, xt, xc, xa, 16, 16);
2378 break;
2379 case 0b01100110: /* xor(C,B) */
2380 tcg_gen_gvec_xor(MO_64, xt, xc, xb, 16, 16);
2381 break;
2382 case 0b01110111: /* or(C,B) */
2383 tcg_gen_gvec_or(MO_64, xt, xc, xb, 16, 16);
2384 break;
2385 case 0b10001000: /* nor(C,B) */
2386 tcg_gen_gvec_nor(MO_64, xt, xc, xb, 16, 16);
2387 break;
2388 case 0b10011001: /* eqv(C,B) */
2389 tcg_gen_gvec_eqv(MO_64, xt, xc, xb, 16, 16);
2390 break;
2391 case 0b10100000: /* nor(C,A) */
2392 tcg_gen_gvec_nor(MO_64, xt, xc, xa, 16, 16);
2393 break;
2394 case 0b10100101: /* eqv(C,A) */
2395 tcg_gen_gvec_eqv(MO_64, xt, xc, xa, 16, 16);
2396 break;
2397 case 0b10101010: /* not(C) */
2398 tcg_gen_gvec_not(MO_64, xt, xc, 16, 16);
2399 break;
2400 case 0b11000000: /* nor(B,A) */
2401 tcg_gen_gvec_nor(MO_64, xt, xb, xa, 16, 16);
2402 break;
2403 case 0b11000011: /* eqv(B,A) */
2404 tcg_gen_gvec_eqv(MO_64, xt, xb, xa, 16, 16);
2405 break;
2406 case 0b11001100: /* not(B) */
2407 tcg_gen_gvec_not(MO_64, xt, xb, 16, 16);
2408 break;
2409 case 0b11101110: /* nand(C,B) */
2410 tcg_gen_gvec_nand(MO_64, xt, xc, xb, 16, 16);
2411 break;
2412 case 0b11110000: /* not(A) */
2413 tcg_gen_gvec_not(MO_64, xt, xa, 16, 16);
2414 break;
2415 case 0b11111010: /* nand(C,A) */
2416 tcg_gen_gvec_nand(MO_64, xt, xc, xa, 16, 16);
2417 break;
2418 case 0b11111100: /* nand(B,A) */
2419 tcg_gen_gvec_nand(MO_64, xt, xb, xa, 16, 16);
2420 break;
2421 case 0b11111111: /* true */
2422 set_cpu_vsr(a->xt, tcg_constant_i64(-1), true);
2423 set_cpu_vsr(a->xt, tcg_constant_i64(-1), false);
2424 break;
2425 default:
2426 /* Fallback to compute all conjunctions/disjunctions */
2427 tcg_gen_gvec_4i(xt, xa, xb, xc, 16, 16, a->imm, &op);
2428 }
2430 return true;
2431 }
2433 static void gen_xxblendv_vec(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b,
2434 TCGv_vec c)
2435 {
2436 TCGv_vec tmp = tcg_temp_new_vec_matching(c);
2437 tcg_gen_sari_vec(vece, tmp, c, (8 << vece) - 1);
2438 tcg_gen_bitsel_vec(vece, t, tmp, b, a);
2439 tcg_temp_free_vec(tmp);
2440 }
2442 static bool do_xxblendv(DisasContext *ctx, arg_8RR_XX4 *a, unsigned vece)
2443 {
2444 static const TCGOpcode vecop_list[] = {
2445 INDEX_op_sari_vec, 0
2446 };
2447 static const GVecGen4 ops[4] = {
2448 {
2449 .fniv = gen_xxblendv_vec,
2450 .fno = gen_helper_XXBLENDVB,
2451 .opt_opc = vecop_list,
2452 .vece = MO_8
2453 },
2454 {
2455 .fniv = gen_xxblendv_vec,
2456 .fno = gen_helper_XXBLENDVH,
2457 .opt_opc = vecop_list,
2458 .vece = MO_16
2459 },
2460 {
2461 .fniv = gen_xxblendv_vec,
2462 .fno = gen_helper_XXBLENDVW,
2463 .opt_opc = vecop_list,
2464 .vece = MO_32
2465 },
2466 {
2467 .fniv = gen_xxblendv_vec,
2468 .fno = gen_helper_XXBLENDVD,
2469 .opt_opc = vecop_list,
2470 .vece = MO_64
2471 }
2472 };
2474 REQUIRE_VSX(ctx);
2476 tcg_gen_gvec_4(vsr_full_offset(a->xt), vsr_full_offset(a->xa),
2477 vsr_full_offset(a->xb), vsr_full_offset(a->xc),
2478 16, 16, &ops[vece]);
2480 return true;
2481 }
2483 TRANS(XXBLENDVB, do_xxblendv, MO_8)
2484 TRANS(XXBLENDVH, do_xxblendv, MO_16)
2485 TRANS(XXBLENDVW, do_xxblendv, MO_32)
2486 TRANS(XXBLENDVD, do_xxblendv, MO_64)
2488 static bool do_xsmaxmincjdp(DisasContext *ctx, arg_XX3 *a,
2489 void (*helper)(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr))
2490 {
2491 TCGv_ptr xt, xa, xb;
2493 REQUIRE_INSNS_FLAGS2(ctx, ISA300);
2494 REQUIRE_VSX(ctx);
2496 xt = gen_vsr_ptr(a->xt);
2497 xa = gen_vsr_ptr(a->xa);
2498 xb = gen_vsr_ptr(a->xb);
2500 helper(cpu_env, xt, xa, xb);
2502 tcg_temp_free_ptr(xt);
2503 tcg_temp_free_ptr(xa);
2504 tcg_temp_free_ptr(xb);
2506 return true;
2507 }
2509 TRANS(XSMAXCDP, do_xsmaxmincjdp, gen_helper_xsmaxcdp)
2510 TRANS(XSMINCDP, do_xsmaxmincjdp, gen_helper_xsmincdp)
2511 TRANS(XSMAXJDP, do_xsmaxmincjdp, gen_helper_xsmaxjdp)
2512 TRANS(XSMINJDP, do_xsmaxmincjdp, gen_helper_xsminjdp)
2514 #undef GEN_XX2FORM
2515 #undef GEN_XX3FORM
2516 #undef GEN_XX2IFORM
2517 #undef GEN_XX3_RC_FORM
2518 #undef GEN_XX3FORM_DM
2519 #undef VSX_LOGICAL