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target/ppc: Readability improvements in exception handlers
[qemu/armbru.git] / target / ppc / cpu.h
blob7c48b2eadb756f50e2209e4061ec15510631311b
1 /*
2 * PowerPC emulation cpu definitions for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #ifndef PPC_CPU_H
21 #define PPC_CPU_H
22
23 #include "qemu/int128.h"
24 #include "qemu/cpu-float.h"
25 #include "exec/cpu-defs.h"
26 #include "cpu-qom.h"
27 #include "qom/object.h"
28 #include "hw/registerfields.h"
29
30 #define CPU_RESOLVING_TYPE TYPE_POWERPC_CPU
31
32 #define TCG_GUEST_DEFAULT_MO 0
33
34 #define TARGET_PAGE_BITS_64K 16
35 #define TARGET_PAGE_BITS_16M 24
36
37 #if defined(TARGET_PPC64)
38 #define PPC_ELF_MACHINE EM_PPC64
39 #else
40 #define PPC_ELF_MACHINE EM_PPC
41 #endif
42
43 #define PPC_BIT_NR(bit) (63 - (bit))
44 #define PPC_BIT(bit) (0x8000000000000000ULL >> (bit))
45 #define PPC_BIT32(bit) (0x80000000 >> (bit))
46 #define PPC_BIT8(bit) (0x80 >> (bit))
47 #define PPC_BITMASK(bs, be) ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs))
48 #define PPC_BITMASK32(bs, be) ((PPC_BIT32(bs) - PPC_BIT32(be)) | \
49 PPC_BIT32(bs))
50 #define PPC_BITMASK8(bs, be) ((PPC_BIT8(bs) - PPC_BIT8(be)) | PPC_BIT8(bs))
51
52 /*
53 * QEMU version of the GETFIELD/SETFIELD macros from skiboot
54 *
55 * It might be better to use the existing extract64() and
56 * deposit64() but this means that all the register definitions will
57 * change and become incompatible with the ones found in skiboot.
58 */
59 #define MASK_TO_LSH(m) (__builtin_ffsll(m) - 1)
60 #define GETFIELD(m, v) (((v) & (m)) >> MASK_TO_LSH(m))
61 #define SETFIELD(m, v, val) \
62 (((v) & ~(m)) | ((((typeof(v))(val)) << MASK_TO_LSH(m)) & (m)))
63
64 /*****************************************************************************/
65 /* Exception vectors definitions */
66 enum {
67 POWERPC_EXCP_NONE = -1,
68 /* The 64 first entries are used by the PowerPC embedded specification */
69 POWERPC_EXCP_CRITICAL = 0, /* Critical input */
70 POWERPC_EXCP_MCHECK = 1, /* Machine check exception */
71 POWERPC_EXCP_DSI = 2, /* Data storage exception */
72 POWERPC_EXCP_ISI = 3, /* Instruction storage exception */
73 POWERPC_EXCP_EXTERNAL = 4, /* External input */
74 POWERPC_EXCP_ALIGN = 5, /* Alignment exception */
75 POWERPC_EXCP_PROGRAM = 6, /* Program exception */
76 POWERPC_EXCP_FPU = 7, /* Floating-point unavailable exception */
77 POWERPC_EXCP_SYSCALL = 8, /* System call exception */
78 POWERPC_EXCP_APU = 9, /* Auxiliary processor unavailable */
79 POWERPC_EXCP_DECR = 10, /* Decrementer exception */
80 POWERPC_EXCP_FIT = 11, /* Fixed-interval timer interrupt */
81 POWERPC_EXCP_WDT = 12, /* Watchdog timer interrupt */
82 POWERPC_EXCP_DTLB = 13, /* Data TLB miss */
83 POWERPC_EXCP_ITLB = 14, /* Instruction TLB miss */
84 POWERPC_EXCP_DEBUG = 15, /* Debug interrupt */
85 /* Vectors 16 to 31 are reserved */
86 POWERPC_EXCP_SPEU = 32, /* SPE/embedded floating-point unavailable */
87 POWERPC_EXCP_EFPDI = 33, /* Embedded floating-point data interrupt */
88 POWERPC_EXCP_EFPRI = 34, /* Embedded floating-point round interrupt */
89 POWERPC_EXCP_EPERFM = 35, /* Embedded performance monitor interrupt */
90 POWERPC_EXCP_DOORI = 36, /* Embedded doorbell interrupt */
91 POWERPC_EXCP_DOORCI = 37, /* Embedded doorbell critical interrupt */
92 POWERPC_EXCP_GDOORI = 38, /* Embedded guest doorbell interrupt */
93 POWERPC_EXCP_GDOORCI = 39, /* Embedded guest doorbell critical interrupt*/
94 POWERPC_EXCP_HYPPRIV = 41, /* Embedded hypervisor priv instruction */
95 /* Vectors 42 to 63 are reserved */
96 /* Exceptions defined in the PowerPC server specification */
97 POWERPC_EXCP_RESET = 64, /* System reset exception */
98 POWERPC_EXCP_DSEG = 65, /* Data segment exception */
99 POWERPC_EXCP_ISEG = 66, /* Instruction segment exception */
100 POWERPC_EXCP_HDECR = 67, /* Hypervisor decrementer exception */
101 POWERPC_EXCP_TRACE = 68, /* Trace exception */
102 POWERPC_EXCP_HDSI = 69, /* Hypervisor data storage exception */
103 POWERPC_EXCP_HISI = 70, /* Hypervisor instruction storage exception */
104 POWERPC_EXCP_HDSEG = 71, /* Hypervisor data segment exception */
105 POWERPC_EXCP_HISEG = 72, /* Hypervisor instruction segment exception */
106 POWERPC_EXCP_VPU = 73, /* Vector unavailable exception */
107 /* 40x specific exceptions */
108 POWERPC_EXCP_PIT = 74, /* Programmable interval timer interrupt */
109 /* Vectors 75-76 are 601 specific exceptions */
110 /* 602 specific exceptions */
111 POWERPC_EXCP_EMUL = 77, /* Emulation trap exception */
112 /* 602/603 specific exceptions */
113 POWERPC_EXCP_IFTLB = 78, /* Instruction fetch TLB miss */
114 POWERPC_EXCP_DLTLB = 79, /* Data load TLB miss */
115 POWERPC_EXCP_DSTLB = 80, /* Data store TLB miss */
116 /* Exceptions available on most PowerPC */
117 POWERPC_EXCP_FPA = 81, /* Floating-point assist exception */
118 POWERPC_EXCP_DABR = 82, /* Data address breakpoint */
119 POWERPC_EXCP_IABR = 83, /* Instruction address breakpoint */
120 POWERPC_EXCP_SMI = 84, /* System management interrupt */
121 POWERPC_EXCP_PERFM = 85, /* Embedded performance monitor interrupt */
122 /* 7xx/74xx specific exceptions */
123 POWERPC_EXCP_THERM = 86, /* Thermal interrupt */
124 /* 74xx specific exceptions */
125 POWERPC_EXCP_VPUA = 87, /* Vector assist exception */
126 /* 970FX specific exceptions */
127 POWERPC_EXCP_SOFTP = 88, /* Soft patch exception */
128 POWERPC_EXCP_MAINT = 89, /* Maintenance exception */
129 /* Freescale embedded cores specific exceptions */
130 POWERPC_EXCP_MEXTBR = 90, /* Maskable external breakpoint */
131 POWERPC_EXCP_NMEXTBR = 91, /* Non maskable external breakpoint */
132 POWERPC_EXCP_ITLBE = 92, /* Instruction TLB error */
133 POWERPC_EXCP_DTLBE = 93, /* Data TLB error */
134 /* VSX Unavailable (Power ISA 2.06 and later) */
135 POWERPC_EXCP_VSXU = 94, /* VSX Unavailable */
136 POWERPC_EXCP_FU = 95, /* Facility Unavailable */
137 /* Additional ISA 2.06 and later server exceptions */
138 POWERPC_EXCP_HV_EMU = 96, /* HV emulation assistance */
139 POWERPC_EXCP_HV_MAINT = 97, /* HMI */
140 POWERPC_EXCP_HV_FU = 98, /* Hypervisor Facility unavailable */
141 /* Server doorbell variants */
142 POWERPC_EXCP_SDOOR = 99,
143 POWERPC_EXCP_SDOOR_HV = 100,
144 /* ISA 3.00 additions */
145 POWERPC_EXCP_HVIRT = 101,
146 POWERPC_EXCP_SYSCALL_VECTORED = 102, /* scv exception */
147 POWERPC_EXCP_PERFM_EBB = 103, /* Performance Monitor EBB Exception */
148 POWERPC_EXCP_EXTERNAL_EBB = 104, /* External EBB Exception */
149 /* EOL */
150 POWERPC_EXCP_NB = 105,
151 /* QEMU exceptions: special cases we want to stop translation */
152 POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only */
153 };
154
155 /* Exceptions error codes */
156 enum {
157 /* Exception subtypes for POWERPC_EXCP_ALIGN */
158 POWERPC_EXCP_ALIGN_FP = 0x01, /* FP alignment exception */
159 POWERPC_EXCP_ALIGN_LST = 0x02, /* Unaligned mult/extern load/store */
160 POWERPC_EXCP_ALIGN_LE = 0x03, /* Multiple little-endian access */
161 POWERPC_EXCP_ALIGN_PROT = 0x04, /* Access cross protection boundary */
162 POWERPC_EXCP_ALIGN_BAT = 0x05, /* Access cross a BAT/seg boundary */
163 POWERPC_EXCP_ALIGN_CACHE = 0x06, /* Impossible dcbz access */
164 POWERPC_EXCP_ALIGN_INSN = 0x07, /* Pref. insn x-ing 64-byte boundary */
165 /* Exception subtypes for POWERPC_EXCP_PROGRAM */
166 /* FP exceptions */
167 POWERPC_EXCP_FP = 0x10,
168 POWERPC_EXCP_FP_OX = 0x01, /* FP overflow */
169 POWERPC_EXCP_FP_UX = 0x02, /* FP underflow */
170 POWERPC_EXCP_FP_ZX = 0x03, /* FP divide by zero */
171 POWERPC_EXCP_FP_XX = 0x04, /* FP inexact */
172 POWERPC_EXCP_FP_VXSNAN = 0x05, /* FP invalid SNaN op */
173 POWERPC_EXCP_FP_VXISI = 0x06, /* FP invalid infinite subtraction */
174 POWERPC_EXCP_FP_VXIDI = 0x07, /* FP invalid infinite divide */
175 POWERPC_EXCP_FP_VXZDZ = 0x08, /* FP invalid zero divide */
176 POWERPC_EXCP_FP_VXIMZ = 0x09, /* FP invalid infinite * zero */
177 POWERPC_EXCP_FP_VXVC = 0x0A, /* FP invalid compare */
178 POWERPC_EXCP_FP_VXSOFT = 0x0B, /* FP invalid operation */
179 POWERPC_EXCP_FP_VXSQRT = 0x0C, /* FP invalid square root */
180 POWERPC_EXCP_FP_VXCVI = 0x0D, /* FP invalid integer conversion */
181 /* Invalid instruction */
182 POWERPC_EXCP_INVAL = 0x20,
183 POWERPC_EXCP_INVAL_INVAL = 0x01, /* Invalid instruction */
184 POWERPC_EXCP_INVAL_LSWX = 0x02, /* Invalid lswx instruction */
185 POWERPC_EXCP_INVAL_SPR = 0x03, /* Invalid SPR access */
186 POWERPC_EXCP_INVAL_FP = 0x04, /* Unimplemented mandatory fp instr */
187 /* Privileged instruction */
188 POWERPC_EXCP_PRIV = 0x30,
189 POWERPC_EXCP_PRIV_OPC = 0x01, /* Privileged operation exception */
190 POWERPC_EXCP_PRIV_REG = 0x02, /* Privileged register exception */
191 /* Trap */
192 POWERPC_EXCP_TRAP = 0x40,
193 };
194
195 /* Exception model */
196 typedef enum powerpc_excp_t {
197 POWERPC_EXCP_UNKNOWN = 0,
198 /* Standard PowerPC exception model */
199 POWERPC_EXCP_STD,
200 /* PowerPC 40x exception model */
201 POWERPC_EXCP_40x,
202 /* PowerPC 603/604/G2 exception model */
203 POWERPC_EXCP_6xx,
204 /* PowerPC 7xx exception model */
205 POWERPC_EXCP_7xx,
206 /* PowerPC 74xx exception model */
207 POWERPC_EXCP_74xx,
208 /* BookE exception model */
209 POWERPC_EXCP_BOOKE,
210 /* PowerPC 970 exception model */
211 POWERPC_EXCP_970,
212 /* POWER7 exception model */
213 POWERPC_EXCP_POWER7,
214 /* POWER8 exception model */
215 POWERPC_EXCP_POWER8,
216 /* POWER9 exception model */
217 POWERPC_EXCP_POWER9,
218 /* POWER10 exception model */
219 POWERPC_EXCP_POWER10,
220 } powerpc_excp_t;
221
222 /*****************************************************************************/
223 /* MMU model */
224 typedef enum powerpc_mmu_t {
225 POWERPC_MMU_UNKNOWN = 0x00000000,
226 /* Standard 32 bits PowerPC MMU */
227 POWERPC_MMU_32B = 0x00000001,
228 /* PowerPC 6xx MMU with software TLB */
229 POWERPC_MMU_SOFT_6xx = 0x00000002,
230 /*
231 * PowerPC 74xx MMU with software TLB (this has been
232 * disabled, see git history for more information.
233 * keywords: tlbld tlbli TLBMISS PTEHI PTELO)
234 */
235 POWERPC_MMU_SOFT_74xx = 0x00000003,
236 /* PowerPC 4xx MMU with software TLB */
237 POWERPC_MMU_SOFT_4xx = 0x00000004,
238 /* PowerPC MMU in real mode only */
239 POWERPC_MMU_REAL = 0x00000006,
240 /* Freescale MPC8xx MMU model */
241 POWERPC_MMU_MPC8xx = 0x00000007,
242 /* BookE MMU model */
243 POWERPC_MMU_BOOKE = 0x00000008,
244 /* BookE 2.06 MMU model */
245 POWERPC_MMU_BOOKE206 = 0x00000009,
246 #define POWERPC_MMU_64 0x00010000
247 /* 64 bits PowerPC MMU */
248 POWERPC_MMU_64B = POWERPC_MMU_64 | 0x00000001,
249 /* Architecture 2.03 and later (has LPCR) */
250 POWERPC_MMU_2_03 = POWERPC_MMU_64 | 0x00000002,
251 /* Architecture 2.06 variant */
252 POWERPC_MMU_2_06 = POWERPC_MMU_64 | 0x00000003,
253 /* Architecture 2.07 variant */
254 POWERPC_MMU_2_07 = POWERPC_MMU_64 | 0x00000004,
255 /* Architecture 3.00 variant */
256 POWERPC_MMU_3_00 = POWERPC_MMU_64 | 0x00000005,
257 } powerpc_mmu_t;
258
259 static inline bool mmu_is_64bit(powerpc_mmu_t mmu_model)
260 {
261 return mmu_model & POWERPC_MMU_64;
262 }
263
264 /*****************************************************************************/
265 /* Input pins model */
266 typedef enum powerpc_input_t {
267 PPC_FLAGS_INPUT_UNKNOWN = 0,
268 /* PowerPC 6xx bus */
269 PPC_FLAGS_INPUT_6xx,
270 /* BookE bus */
271 PPC_FLAGS_INPUT_BookE,
272 /* PowerPC 405 bus */
273 PPC_FLAGS_INPUT_405,
274 /* PowerPC 970 bus */
275 PPC_FLAGS_INPUT_970,
276 /* PowerPC POWER7 bus */
277 PPC_FLAGS_INPUT_POWER7,
278 /* PowerPC POWER9 bus */
279 PPC_FLAGS_INPUT_POWER9,
280 /* Freescale RCPU bus */
281 PPC_FLAGS_INPUT_RCPU,
282 } powerpc_input_t;
283
284 #define PPC_INPUT(env) ((env)->bus_model)
285
286 /*****************************************************************************/
287 typedef struct opc_handler_t opc_handler_t;
288
289 /*****************************************************************************/
290 /* Types used to describe some PowerPC registers etc. */
291 typedef struct DisasContext DisasContext;
292 typedef struct ppc_dcr_t ppc_dcr_t;
293 typedef struct ppc_spr_t ppc_spr_t;
294 typedef struct ppc_tb_t ppc_tb_t;
295 typedef union ppc_tlb_t ppc_tlb_t;
296 typedef struct ppc_hash_pte64 ppc_hash_pte64_t;
297 typedef struct PPCHash64Options PPCHash64Options;
298
299 typedef struct CPUArchState CPUPPCState;
300
301 /* SPR access micro-ops generations callbacks */
302 struct ppc_spr_t {
303 const char *name;
304 target_ulong default_value;
305 #ifndef CONFIG_USER_ONLY
306 unsigned int gdb_id;
307 #endif
308 #ifdef CONFIG_TCG
309 void (*uea_read)(DisasContext *ctx, int gpr_num, int spr_num);
310 void (*uea_write)(DisasContext *ctx, int spr_num, int gpr_num);
311 # ifndef CONFIG_USER_ONLY
312 void (*oea_read)(DisasContext *ctx, int gpr_num, int spr_num);
313 void (*oea_write)(DisasContext *ctx, int spr_num, int gpr_num);
314 void (*hea_read)(DisasContext *ctx, int gpr_num, int spr_num);
315 void (*hea_write)(DisasContext *ctx, int spr_num, int gpr_num);
316 # endif
317 #endif
318 #ifdef CONFIG_KVM
319 /*
320 * We (ab)use the fact that all the SPRs will have ids for the
321 * ONE_REG interface will have KVM_REG_PPC to use 0 as meaning,
322 * don't sync this
323 */
324 uint64_t one_reg_id;
325 #endif
326 };
327
328 /* VSX/Altivec registers (128 bits) */
329 typedef union _ppc_vsr_t {
330 uint8_t u8[16];
331 uint16_t u16[8];
332 uint32_t u32[4];
333 uint64_t u64[2];
334 int8_t s8[16];
335 int16_t s16[8];
336 int32_t s32[4];
337 int64_t s64[2];
338 float16 f16[8];
339 float32 f32[4];
340 float64 f64[2];
341 float128 f128;
342 #ifdef CONFIG_INT128
343 __uint128_t u128;
344 #endif
345 Int128 s128;
346 } ppc_vsr_t;
347
348 typedef ppc_vsr_t ppc_avr_t;
349 typedef ppc_vsr_t ppc_fprp_t;
350 typedef ppc_vsr_t ppc_acc_t;
351
352 #if !defined(CONFIG_USER_ONLY)
353 /* Software TLB cache */
354 typedef struct ppc6xx_tlb_t ppc6xx_tlb_t;
355 struct ppc6xx_tlb_t {
356 target_ulong pte0;
357 target_ulong pte1;
358 target_ulong EPN;
359 };
360
361 typedef struct ppcemb_tlb_t ppcemb_tlb_t;
362 struct ppcemb_tlb_t {
363 uint64_t RPN;
364 target_ulong EPN;
365 target_ulong PID;
366 target_ulong size;
367 uint32_t prot;
368 uint32_t attr; /* Storage attributes */
369 };
370
371 typedef struct ppcmas_tlb_t {
372 uint32_t mas8;
373 uint32_t mas1;
374 uint64_t mas2;
375 uint64_t mas7_3;
376 } ppcmas_tlb_t;
377
378 union ppc_tlb_t {
379 ppc6xx_tlb_t *tlb6;
380 ppcemb_tlb_t *tlbe;
381 ppcmas_tlb_t *tlbm;
382 };
383
384 /* possible TLB variants */
385 #define TLB_NONE 0
386 #define TLB_6XX 1
387 #define TLB_EMB 2
388 #define TLB_MAS 3
389 #endif
390
391 typedef struct PPCHash64SegmentPageSizes PPCHash64SegmentPageSizes;
392
393 typedef struct ppc_slb_t ppc_slb_t;
394 struct ppc_slb_t {
395 uint64_t esid;
396 uint64_t vsid;
397 const PPCHash64SegmentPageSizes *sps;
398 };
399
400 #define MAX_SLB_ENTRIES 64
401 #define SEGMENT_SHIFT_256M 28
402 #define SEGMENT_MASK_256M (~((1ULL << SEGMENT_SHIFT_256M) - 1))
403
404 #define SEGMENT_SHIFT_1T 40
405 #define SEGMENT_MASK_1T (~((1ULL << SEGMENT_SHIFT_1T) - 1))
406
407 typedef struct ppc_v3_pate_t {
408 uint64_t dw0;
409 uint64_t dw1;
410 } ppc_v3_pate_t;
411
412 /* PMU related structs and defines */
413 #define PMU_COUNTERS_NUM 6
414 typedef enum {
415 PMU_EVENT_INVALID = 0,
416 PMU_EVENT_INACTIVE,
417 PMU_EVENT_CYCLES,
418 PMU_EVENT_INSTRUCTIONS,
419 PMU_EVENT_INSN_RUN_LATCH,
420 } PMUEventType;
421
422 /*****************************************************************************/
423 /* Machine state register bits definition */
424 #define MSR_SF PPC_BIT_NR(0) /* Sixty-four-bit mode hflags */
425 #define MSR_TAG PPC_BIT_NR(1) /* Tag-active mode (POWERx ?) */
426 #define MSR_ISF PPC_BIT_NR(2) /* Sixty-four-bit interrupt mode on 630 */
427 #define MSR_HV PPC_BIT_NR(3) /* hypervisor state hflags */
428 #define MSR_TS0 PPC_BIT_NR(29) /* Transactional state, 2 bits (Book3s) */
429 #define MSR_TS1 PPC_BIT_NR(30)
430 #define MSR_TM PPC_BIT_NR(31) /* Transactional Memory Available (Book3s) */
431 #define MSR_CM PPC_BIT_NR(32) /* Computation mode for BookE hflags */
432 #define MSR_ICM PPC_BIT_NR(33) /* Interrupt computation mode for BookE */
433 #define MSR_GS PPC_BIT_NR(35) /* guest state for BookE */
434 #define MSR_UCLE PPC_BIT_NR(37) /* User-mode cache lock enable for BookE */
435 #define MSR_VR PPC_BIT_NR(38) /* altivec available x hflags */
436 #define MSR_SPE PPC_BIT_NR(38) /* SPE enable for BookE x hflags */
437 #define MSR_VSX PPC_BIT_NR(40) /* Vector Scalar Extension (>= 2.06)x hflags */
438 #define MSR_S PPC_BIT_NR(41) /* Secure state */
439 #define MSR_KEY PPC_BIT_NR(44) /* key bit on 603e */
440 #define MSR_POW PPC_BIT_NR(45) /* Power management */
441 #define MSR_WE PPC_BIT_NR(45) /* Wait State Enable on 405 */
442 #define MSR_TGPR PPC_BIT_NR(46) /* TGPR usage on 602/603 x */
443 #define MSR_CE PPC_BIT_NR(46) /* Critical int. enable on embedded PPC x */
444 #define MSR_ILE PPC_BIT_NR(47) /* Interrupt little-endian mode */
445 #define MSR_EE PPC_BIT_NR(48) /* External interrupt enable */
446 #define MSR_PR PPC_BIT_NR(49) /* Problem state hflags */
447 #define MSR_FP PPC_BIT_NR(50) /* Floating point available hflags */
448 #define MSR_ME PPC_BIT_NR(51) /* Machine check interrupt enable */
449 #define MSR_FE0 PPC_BIT_NR(52) /* Floating point exception mode 0 */
450 #define MSR_SE PPC_BIT_NR(53) /* Single-step trace enable x hflags */
451 #define MSR_DWE PPC_BIT_NR(53) /* Debug wait enable on 405 x */
452 #define MSR_UBLE PPC_BIT_NR(53) /* User BTB lock enable on e500 x */
453 #define MSR_BE PPC_BIT_NR(54) /* Branch trace enable x hflags */
454 #define MSR_DE PPC_BIT_NR(54) /* Debug int. enable on embedded PPC x */
455 #define MSR_FE1 PPC_BIT_NR(55) /* Floating point exception mode 1 */
456 #define MSR_AL PPC_BIT_NR(56) /* AL bit on POWER */
457 #define MSR_EP PPC_BIT_NR(57) /* Exception prefix on 601 */
458 #define MSR_IR PPC_BIT_NR(58) /* Instruction relocate */
459 #define MSR_IS PPC_BIT_NR(58) /* Instruction address space (BookE) */
460 #define MSR_DR PPC_BIT_NR(59) /* Data relocate */
461 #define MSR_DS PPC_BIT_NR(59) /* Data address space (BookE) */
462 #define MSR_PE PPC_BIT_NR(60) /* Protection enable on 403 */
463 #define MSR_PX PPC_BIT_NR(61) /* Protection exclusive on 403 x */
464 #define MSR_PMM PPC_BIT_NR(61) /* Performance monitor mark on POWER x */
465 #define MSR_RI PPC_BIT_NR(62) /* Recoverable interrupt 1 */
466 #define MSR_LE PPC_BIT_NR(63) /* Little-endian mode 1 hflags */
467
468 FIELD(MSR, SF, MSR_SF, 1)
469 FIELD(MSR, TAG, MSR_TAG, 1)
470 FIELD(MSR, ISF, MSR_ISF, 1)
471 #if defined(TARGET_PPC64)
472 FIELD(MSR, HV, MSR_HV, 1)
473 #define FIELD_EX64_HV(storage) FIELD_EX64(storage, MSR, HV)
474 #else
475 #define FIELD_EX64_HV(storage) 0
476 #endif
477 FIELD(MSR, TS0, MSR_TS0, 1)
478 FIELD(MSR, TS1, MSR_TS1, 1)
479 FIELD(MSR, TS, MSR_TS0, 2)
480 FIELD(MSR, TM, MSR_TM, 1)
481 FIELD(MSR, CM, MSR_CM, 1)
482 FIELD(MSR, ICM, MSR_ICM, 1)
483 FIELD(MSR, GS, MSR_GS, 1)
484 FIELD(MSR, UCLE, MSR_UCLE, 1)
485 FIELD(MSR, VR, MSR_VR, 1)
486 FIELD(MSR, SPE, MSR_SPE, 1)
487 FIELD(MSR, VSX, MSR_VSX, 1)
488 FIELD(MSR, S, MSR_S, 1)
489 FIELD(MSR, KEY, MSR_KEY, 1)
490 FIELD(MSR, POW, MSR_POW, 1)
491 FIELD(MSR, WE, MSR_WE, 1)
492 FIELD(MSR, TGPR, MSR_TGPR, 1)
493 FIELD(MSR, CE, MSR_CE, 1)
494 FIELD(MSR, ILE, MSR_ILE, 1)
495 FIELD(MSR, EE, MSR_EE, 1)
496 FIELD(MSR, PR, MSR_PR, 1)
497 FIELD(MSR, FP, MSR_FP, 1)
498 FIELD(MSR, ME, MSR_ME, 1)
499 FIELD(MSR, FE0, MSR_FE0, 1)
500 FIELD(MSR, SE, MSR_SE, 1)
501 FIELD(MSR, DWE, MSR_DWE, 1)
502 FIELD(MSR, UBLE, MSR_UBLE, 1)
503 FIELD(MSR, BE, MSR_BE, 1)
504 FIELD(MSR, DE, MSR_DE, 1)
505 FIELD(MSR, FE1, MSR_FE1, 1)
506 FIELD(MSR, AL, MSR_AL, 1)
507 FIELD(MSR, EP, MSR_EP, 1)
508 FIELD(MSR, IR, MSR_IR, 1)
509 FIELD(MSR, DR, MSR_DR, 1)
510 FIELD(MSR, IS, MSR_IS, 1)
511 FIELD(MSR, DS, MSR_DS, 1)
512 FIELD(MSR, PE, MSR_PE, 1)
513 FIELD(MSR, PX, MSR_PX, 1)
514 FIELD(MSR, PMM, MSR_PMM, 1)
515 FIELD(MSR, RI, MSR_RI, 1)
516 FIELD(MSR, LE, MSR_LE, 1)
517
518 /*
519 * FE0 and FE1 bits are not side-by-side
520 * so we can't combine them using FIELD()
521 */
522 #define FIELD_EX64_FE(msr) \
523 ((FIELD_EX64(msr, MSR, FE0) << 1) | FIELD_EX64(msr, MSR, FE1))
524
525 /* PMU bits */
526 #define MMCR0_FC PPC_BIT(32) /* Freeze Counters */
527 #define MMCR0_PMAO PPC_BIT(56) /* Perf Monitor Alert Occurred */
528 #define MMCR0_PMAE PPC_BIT(37) /* Perf Monitor Alert Enable */
529 #define MMCR0_EBE PPC_BIT(43) /* Perf Monitor EBB Enable */
530 #define MMCR0_FCECE PPC_BIT(38) /* FC on Enabled Cond or Event */
531 #define MMCR0_PMCC0 PPC_BIT(44) /* PMC Control bit 0 */
532 #define MMCR0_PMCC1 PPC_BIT(45) /* PMC Control bit 1 */
533 #define MMCR0_PMCC PPC_BITMASK(44, 45) /* PMC Control */
534 #define MMCR0_FC14 PPC_BIT(58) /* PMC Freeze Counters 1-4 bit */
535 #define MMCR0_FC56 PPC_BIT(59) /* PMC Freeze Counters 5-6 bit */
536 #define MMCR0_PMC1CE PPC_BIT(48) /* MMCR0 PMC1 Condition Enabled */
537 #define MMCR0_PMCjCE PPC_BIT(49) /* MMCR0 PMCj Condition Enabled */
538 /* MMCR0 userspace r/w mask */
539 #define MMCR0_UREG_MASK (MMCR0_FC | MMCR0_PMAO | MMCR0_PMAE)
540 /* MMCR2 userspace r/w mask */
541 #define MMCR2_FC1P0 PPC_BIT(1) /* MMCR2 FCnP0 for PMC1 */
542 #define MMCR2_FC2P0 PPC_BIT(10) /* MMCR2 FCnP0 for PMC2 */
543 #define MMCR2_FC3P0 PPC_BIT(19) /* MMCR2 FCnP0 for PMC3 */
544 #define MMCR2_FC4P0 PPC_BIT(28) /* MMCR2 FCnP0 for PMC4 */
545 #define MMCR2_FC5P0 PPC_BIT(37) /* MMCR2 FCnP0 for PMC5 */
546 #define MMCR2_FC6P0 PPC_BIT(46) /* MMCR2 FCnP0 for PMC6 */
547 #define MMCR2_UREG_MASK (MMCR2_FC1P0 | MMCR2_FC2P0 | MMCR2_FC3P0 | \
548 MMCR2_FC4P0 | MMCR2_FC5P0 | MMCR2_FC6P0)
549
550 #define MMCR1_EVT_SIZE 8
551 /* extract64() does a right shift before extracting */
552 #define MMCR1_PMC1SEL_START 32
553 #define MMCR1_PMC1EVT_EXTR (64 - MMCR1_PMC1SEL_START - MMCR1_EVT_SIZE)
554 #define MMCR1_PMC2SEL_START 40
555 #define MMCR1_PMC2EVT_EXTR (64 - MMCR1_PMC2SEL_START - MMCR1_EVT_SIZE)
556 #define MMCR1_PMC3SEL_START 48
557 #define MMCR1_PMC3EVT_EXTR (64 - MMCR1_PMC3SEL_START - MMCR1_EVT_SIZE)
558 #define MMCR1_PMC4SEL_START 56
559 #define MMCR1_PMC4EVT_EXTR (64 - MMCR1_PMC4SEL_START - MMCR1_EVT_SIZE)
560
561 /* PMU uses CTRL_RUN to sample PM_RUN_INST_CMPL */
562 #define CTRL_RUN PPC_BIT(63)
563
564 /* EBB/BESCR bits */
565 /* Global Enable */
566 #define BESCR_GE PPC_BIT(0)
567 /* External Event-based Exception Enable */
568 #define BESCR_EE PPC_BIT(30)
569 /* Performance Monitor Event-based Exception Enable */
570 #define BESCR_PME PPC_BIT(31)
571 /* External Event-based Exception Occurred */
572 #define BESCR_EEO PPC_BIT(62)
573 /* Performance Monitor Event-based Exception Occurred */
574 #define BESCR_PMEO PPC_BIT(63)
575 #define BESCR_INVALID PPC_BITMASK(32, 33)
576
577 /* LPCR bits */
578 #define LPCR_VPM0 PPC_BIT(0)
579 #define LPCR_VPM1 PPC_BIT(1)
580 #define LPCR_ISL PPC_BIT(2)
581 #define LPCR_KBV PPC_BIT(3)
582 #define LPCR_DPFD_SHIFT (63 - 11)
583 #define LPCR_DPFD (0x7ull << LPCR_DPFD_SHIFT)
584 #define LPCR_VRMASD_SHIFT (63 - 16)
585 #define LPCR_VRMASD (0x1full << LPCR_VRMASD_SHIFT)
586 /* P9: Power-saving mode Exit Cause Enable (Upper Section) Mask */
587 #define LPCR_PECE_U_SHIFT (63 - 19)
588 #define LPCR_PECE_U_MASK (0x7ull << LPCR_PECE_U_SHIFT)
589 #define LPCR_HVEE PPC_BIT(17) /* Hypervisor Virt Exit Enable */
590 #define LPCR_RMLS_SHIFT (63 - 37) /* RMLS (removed in ISA v3.0) */
591 #define LPCR_RMLS (0xfull << LPCR_RMLS_SHIFT)
592 #define LPCR_HAIL PPC_BIT(37) /* ISA v3.1 HV AIL=3 equivalent */
593 #define LPCR_ILE PPC_BIT(38)
594 #define LPCR_AIL_SHIFT (63 - 40) /* Alternate interrupt location */
595 #define LPCR_AIL (3ull << LPCR_AIL_SHIFT)
596 #define LPCR_UPRT PPC_BIT(41) /* Use Process Table */
597 #define LPCR_EVIRT PPC_BIT(42) /* Enhanced Virtualisation */
598 #define LPCR_HR PPC_BIT(43) /* Host Radix */
599 #define LPCR_ONL PPC_BIT(45)
600 #define LPCR_LD PPC_BIT(46) /* Large Decrementer */
601 #define LPCR_P7_PECE0 PPC_BIT(49)
602 #define LPCR_P7_PECE1 PPC_BIT(50)
603 #define LPCR_P7_PECE2 PPC_BIT(51)
604 #define LPCR_P8_PECE0 PPC_BIT(47)
605 #define LPCR_P8_PECE1 PPC_BIT(48)
606 #define LPCR_P8_PECE2 PPC_BIT(49)
607 #define LPCR_P8_PECE3 PPC_BIT(50)
608 #define LPCR_P8_PECE4 PPC_BIT(51)
609 /* P9: Power-saving mode Exit Cause Enable (Lower Section) Mask */
610 #define LPCR_PECE_L_SHIFT (63 - 51)
611 #define LPCR_PECE_L_MASK (0x1full << LPCR_PECE_L_SHIFT)
612 #define LPCR_PDEE PPC_BIT(47) /* Privileged Doorbell Exit EN */
613 #define LPCR_HDEE PPC_BIT(48) /* Hyperv Doorbell Exit Enable */
614 #define LPCR_EEE PPC_BIT(49) /* External Exit Enable */
615 #define LPCR_DEE PPC_BIT(50) /* Decrementer Exit Enable */
616 #define LPCR_OEE PPC_BIT(51) /* Other Exit Enable */
617 #define LPCR_MER PPC_BIT(52)
618 #define LPCR_GTSE PPC_BIT(53) /* Guest Translation Shootdown */
619 #define LPCR_TC PPC_BIT(54)
620 #define LPCR_HEIC PPC_BIT(59) /* HV Extern Interrupt Control */
621 #define LPCR_LPES0 PPC_BIT(60)
622 #define LPCR_LPES1 PPC_BIT(61)
623 #define LPCR_RMI PPC_BIT(62)
624 #define LPCR_HVICE PPC_BIT(62) /* HV Virtualisation Int Enable */
625 #define LPCR_HDICE PPC_BIT(63)
626
627 /* PSSCR bits */
628 #define PSSCR_ESL PPC_BIT(42) /* Enable State Loss */
629 #define PSSCR_EC PPC_BIT(43) /* Exit Criterion */
630
631 /* HFSCR bits */
632 #define HFSCR_MSGP PPC_BIT(53) /* Privileged Message Send Facilities */
633 #define HFSCR_IC_MSGP 0xA
634
635 #define DBCR0_ICMP (1 << 27)
636 #define DBCR0_BRT (1 << 26)
637 #define DBSR_ICMP (1 << 27)
638 #define DBSR_BRT (1 << 26)
639
640 /* Hypervisor bit is more specific */
641 #if defined(TARGET_PPC64)
642 #define MSR_HVB (1ULL << MSR_HV)
643 #else
644 #define MSR_HVB (0ULL)
645 #endif
646
647 /* DSISR */
648 #define DSISR_NOPTE 0x40000000
649 /* Not permitted by access authority of encoded access authority */
650 #define DSISR_PROTFAULT 0x08000000
651 #define DSISR_ISSTORE 0x02000000
652 /* Not permitted by virtual page class key protection */
653 #define DSISR_AMR 0x00200000
654 /* Unsupported Radix Tree Configuration */
655 #define DSISR_R_BADCONFIG 0x00080000
656 #define DSISR_ATOMIC_RC 0x00040000
657 /* Unable to translate address of (guest) pde or process/page table entry */
658 #define DSISR_PRTABLE_FAULT 0x00020000
659
660 /* SRR1 error code fields */
661
662 #define SRR1_NOPTE DSISR_NOPTE
663 /* Not permitted due to no-execute or guard bit set */
664 #define SRR1_NOEXEC_GUARD 0x10000000
665 #define SRR1_PROTFAULT DSISR_PROTFAULT
666 #define SRR1_IAMR DSISR_AMR
667
668 /* SRR1[42:45] wakeup fields for System Reset Interrupt */
669
670 #define SRR1_WAKEMASK 0x003c0000 /* reason for wakeup */
671
672 #define SRR1_WAKEHMI 0x00280000 /* Hypervisor maintenance */
673 #define SRR1_WAKEHVI 0x00240000 /* Hypervisor Virt. Interrupt (P9) */
674 #define SRR1_WAKEEE 0x00200000 /* External interrupt */
675 #define SRR1_WAKEDEC 0x00180000 /* Decrementer interrupt */
676 #define SRR1_WAKEDBELL 0x00140000 /* Privileged doorbell */
677 #define SRR1_WAKERESET 0x00100000 /* System reset */
678 #define SRR1_WAKEHDBELL 0x000c0000 /* Hypervisor doorbell */
679 #define SRR1_WAKESCOM 0x00080000 /* SCOM not in power-saving mode */
680
681 /* SRR1[46:47] power-saving exit mode */
682
683 #define SRR1_WAKESTATE 0x00030000 /* Powersave exit mask */
684
685 #define SRR1_WS_HVLOSS 0x00030000 /* HV resources not maintained */
686 #define SRR1_WS_GPRLOSS 0x00020000 /* GPRs not maintained */
687 #define SRR1_WS_NOLOSS 0x00010000 /* All resources maintained */
688
689 /* Facility Status and Control (FSCR) bits */
690 #define FSCR_EBB (63 - 56) /* Event-Based Branch Facility */
691 #define FSCR_TAR (63 - 55) /* Target Address Register */
692 #define FSCR_SCV (63 - 51) /* System call vectored */
693 /* Interrupt cause mask and position in FSCR. HFSCR has the same format */
694 #define FSCR_IC_MASK (0xFFULL)
695 #define FSCR_IC_POS (63 - 7)
696 #define FSCR_IC_DSCR_SPR3 2
697 #define FSCR_IC_PMU 3
698 #define FSCR_IC_BHRB 4
699 #define FSCR_IC_TM 5
700 #define FSCR_IC_EBB 7
701 #define FSCR_IC_TAR 8
702 #define FSCR_IC_SCV 12
703
704 /* Exception state register bits definition */
705 #define ESR_PIL PPC_BIT(36) /* Illegal Instruction */
706 #define ESR_PPR PPC_BIT(37) /* Privileged Instruction */
707 #define ESR_PTR PPC_BIT(38) /* Trap */
708 #define ESR_FP PPC_BIT(39) /* Floating-Point Operation */
709 #define ESR_ST PPC_BIT(40) /* Store Operation */
710 #define ESR_AP PPC_BIT(44) /* Auxiliary Processor Operation */
711 #define ESR_PUO PPC_BIT(45) /* Unimplemented Operation */
712 #define ESR_BO PPC_BIT(46) /* Byte Ordering */
713 #define ESR_PIE PPC_BIT(47) /* Imprecise exception */
714 #define ESR_DATA PPC_BIT(53) /* Data Access (Embedded page table) */
715 #define ESR_TLBI PPC_BIT(54) /* TLB Ineligible (Embedded page table) */
716 #define ESR_PT PPC_BIT(55) /* Page Table (Embedded page table) */
717 #define ESR_SPV PPC_BIT(56) /* SPE/VMX operation */
718 #define ESR_EPID PPC_BIT(57) /* External Process ID operation */
719 #define ESR_VLEMI PPC_BIT(58) /* VLE operation */
720 #define ESR_MIF PPC_BIT(62) /* Misaligned instruction (VLE) */
721
722 /* Transaction EXception And Summary Register bits */
723 #define TEXASR_FAILURE_PERSISTENT (63 - 7)
724 #define TEXASR_DISALLOWED (63 - 8)
725 #define TEXASR_NESTING_OVERFLOW (63 - 9)
726 #define TEXASR_FOOTPRINT_OVERFLOW (63 - 10)
727 #define TEXASR_SELF_INDUCED_CONFLICT (63 - 11)
728 #define TEXASR_NON_TRANSACTIONAL_CONFLICT (63 - 12)
729 #define TEXASR_TRANSACTION_CONFLICT (63 - 13)
730 #define TEXASR_TRANSLATION_INVALIDATION_CONFLICT (63 - 14)
731 #define TEXASR_IMPLEMENTATION_SPECIFIC (63 - 15)
732 #define TEXASR_INSTRUCTION_FETCH_CONFLICT (63 - 16)
733 #define TEXASR_ABORT (63 - 31)
734 #define TEXASR_SUSPENDED (63 - 32)
735 #define TEXASR_PRIVILEGE_HV (63 - 34)
736 #define TEXASR_PRIVILEGE_PR (63 - 35)
737 #define TEXASR_FAILURE_SUMMARY (63 - 36)
738 #define TEXASR_TFIAR_EXACT (63 - 37)
739 #define TEXASR_ROT (63 - 38)
740 #define TEXASR_TRANSACTION_LEVEL (63 - 52) /* 12 bits */
741
742 enum {
743 POWERPC_FLAG_NONE = 0x00000000,
744 /* Flag for MSR bit 25 signification (VRE/SPE) */
745 POWERPC_FLAG_SPE = 0x00000001,
746 POWERPC_FLAG_VRE = 0x00000002,
747 /* Flag for MSR bit 17 signification (TGPR/CE) */
748 POWERPC_FLAG_TGPR = 0x00000004,
749 POWERPC_FLAG_CE = 0x00000008,
750 /* Flag for MSR bit 10 signification (SE/DWE/UBLE) */
751 POWERPC_FLAG_SE = 0x00000010,
752 POWERPC_FLAG_DWE = 0x00000020,
753 POWERPC_FLAG_UBLE = 0x00000040,
754 /* Flag for MSR bit 9 signification (BE/DE) */
755 POWERPC_FLAG_BE = 0x00000080,
756 POWERPC_FLAG_DE = 0x00000100,
757 /* Flag for MSR bit 2 signification (PX/PMM) */
758 POWERPC_FLAG_PX = 0x00000200,
759 POWERPC_FLAG_PMM = 0x00000400,
760 /* Flag for special features */
761 /* Decrementer clock */
762 POWERPC_FLAG_BUS_CLK = 0x00020000,
763 /* Has CFAR */
764 POWERPC_FLAG_CFAR = 0x00040000,
765 /* Has VSX */
766 POWERPC_FLAG_VSX = 0x00080000,
767 /* Has Transaction Memory (ISA 2.07) */
768 POWERPC_FLAG_TM = 0x00100000,
769 /* Has SCV (ISA 3.00) */
770 POWERPC_FLAG_SCV = 0x00200000,
771 /* Has >1 thread per core */
772 POWERPC_FLAG_SMT = 0x00400000,
773 /* Using "LPAR per core" mode (as opposed to per-thread) */
774 POWERPC_FLAG_SMT_1LPAR = 0x00800000,
775 };
776
777 /*
778 * Bits for env->hflags.
779 *
780 * Most of these bits overlap with corresponding bits in MSR,
781 * but some come from other sources. Those that do come from
782 * the MSR are validated in hreg_compute_hflags.
783 */
784 enum {
785 HFLAGS_LE = 0, /* MSR_LE */
786 HFLAGS_HV = 1, /* computed from MSR_HV and other state */
787 HFLAGS_64 = 2, /* computed from MSR_CE and MSR_SF */
788 HFLAGS_GTSE = 3, /* computed from SPR_LPCR[GTSE] */
789 HFLAGS_DR = 4, /* MSR_DR */
790 HFLAGS_HR = 5, /* computed from SPR_LPCR[HR] */
791 HFLAGS_SPE = 6, /* from MSR_SPE if cpu has SPE; avoid overlap w/ MSR_VR */
792 HFLAGS_TM = 8, /* computed from MSR_TM */
793 HFLAGS_BE = 9, /* MSR_BE -- from elsewhere on embedded ppc */
794 HFLAGS_SE = 10, /* MSR_SE -- from elsewhere on embedded ppc */
795 HFLAGS_FP = 13, /* MSR_FP */
796 HFLAGS_PR = 14, /* MSR_PR */
797 HFLAGS_PMCC0 = 15, /* MMCR0 PMCC bit 0 */
798 HFLAGS_PMCC1 = 16, /* MMCR0 PMCC bit 1 */
799 HFLAGS_PMCJCE = 17, /* MMCR0 PMCjCE bit */
800 HFLAGS_PMC_OTHER = 18, /* PMC other than PMC5-6 is enabled */
801 HFLAGS_INSN_CNT = 19, /* PMU instruction count enabled */
802 HFLAGS_VSX = 23, /* MSR_VSX if cpu has VSX */
803 HFLAGS_VR = 25, /* MSR_VR if cpu has VRE */
804
805 HFLAGS_IMMU_IDX = 26, /* 26..28 -- the composite immu_idx */
806 HFLAGS_DMMU_IDX = 29, /* 29..31 -- the composite dmmu_idx */
807 };
808
809 /*****************************************************************************/
810 /* Floating point status and control register */
811 #define FPSCR_DRN2 PPC_BIT_NR(29) /* Decimal Floating-Point rounding ctrl. */
812 #define FPSCR_DRN1 PPC_BIT_NR(30) /* Decimal Floating-Point rounding ctrl. */
813 #define FPSCR_DRN0 PPC_BIT_NR(31) /* Decimal Floating-Point rounding ctrl. */
814 #define FPSCR_FX PPC_BIT_NR(32) /* Floating-point exception summary */
815 #define FPSCR_FEX PPC_BIT_NR(33) /* Floating-point enabled exception summ.*/
816 #define FPSCR_VX PPC_BIT_NR(34) /* Floating-point invalid op. excp. summ.*/
817 #define FPSCR_OX PPC_BIT_NR(35) /* Floating-point overflow exception */
818 #define FPSCR_UX PPC_BIT_NR(36) /* Floating-point underflow exception */
819 #define FPSCR_ZX PPC_BIT_NR(37) /* Floating-point zero divide exception */
820 #define FPSCR_XX PPC_BIT_NR(38) /* Floating-point inexact exception */
821 #define FPSCR_VXSNAN PPC_BIT_NR(39) /* Floating-point invalid op. excp (sNan)*/
822 #define FPSCR_VXISI PPC_BIT_NR(40) /* Floating-point invalid op. excp (inf) */
823 #define FPSCR_VXIDI PPC_BIT_NR(41) /* Floating-point invalid op. excp (inf) */
824 #define FPSCR_VXZDZ PPC_BIT_NR(42) /* Floating-point invalid op. excp (zero)*/
825 #define FPSCR_VXIMZ PPC_BIT_NR(43) /* Floating-point invalid op. excp (inf) */
826 #define FPSCR_VXVC PPC_BIT_NR(44) /* Floating-point invalid op. excp (comp)*/
827 #define FPSCR_FR PPC_BIT_NR(45) /* Floating-point fraction rounded */
828 #define FPSCR_FI PPC_BIT_NR(46) /* Floating-point fraction inexact */
829 #define FPSCR_C PPC_BIT_NR(47) /* Floating-point result class descriptor*/
830 #define FPSCR_FL PPC_BIT_NR(48) /* Floating-point less than or negative */
831 #define FPSCR_FG PPC_BIT_NR(49) /* Floating-point greater than or neg. */
832 #define FPSCR_FE PPC_BIT_NR(50) /* Floating-point equal or zero */
833 #define FPSCR_FU PPC_BIT_NR(51) /* Floating-point unordered or NaN */
834 #define FPSCR_FPCC PPC_BIT_NR(51) /* Floating-point condition code */
835 #define FPSCR_FPRF PPC_BIT_NR(51) /* Floating-point result flags */
836 #define FPSCR_VXSOFT PPC_BIT_NR(53) /* Floating-point invalid op. excp (soft)*/
837 #define FPSCR_VXSQRT PPC_BIT_NR(54) /* Floating-point invalid op. excp (sqrt)*/
838 #define FPSCR_VXCVI PPC_BIT_NR(55) /* Floating-point invalid op. excp (int) */
839 #define FPSCR_VE PPC_BIT_NR(56) /* Floating-point invalid op. excp enable*/
840 #define FPSCR_OE PPC_BIT_NR(57) /* Floating-point overflow excp. enable */
841 #define FPSCR_UE PPC_BIT_NR(58) /* Floating-point underflow excp. enable */
842 #define FPSCR_ZE PPC_BIT_NR(59) /* Floating-point zero divide excp enable*/
843 #define FPSCR_XE PPC_BIT_NR(60) /* Floating-point inexact excp. enable */
844 #define FPSCR_NI PPC_BIT_NR(61) /* Floating-point non-IEEE mode */
845 #define FPSCR_RN1 PPC_BIT_NR(62)
846 #define FPSCR_RN0 PPC_BIT_NR(63) /* Floating-point rounding control */
847 /* Invalid operation exception summary */
848 #define FPSCR_IX ((1 << FPSCR_VXSNAN) | (1 << FPSCR_VXISI) | \
849 (1 << FPSCR_VXIDI) | (1 << FPSCR_VXZDZ) | \
850 (1 << FPSCR_VXIMZ) | (1 << FPSCR_VXVC) | \
851 (1 << FPSCR_VXSOFT) | (1 << FPSCR_VXSQRT) | \
852 (1 << FPSCR_VXCVI))
853
854 FIELD(FPSCR, FI, FPSCR_FI, 1)
855
856 #define FP_DRN2 (1ull << FPSCR_DRN2)
857 #define FP_DRN1 (1ull << FPSCR_DRN1)
858 #define FP_DRN0 (1ull << FPSCR_DRN0)
859 #define FP_DRN (FP_DRN2 | FP_DRN1 | FP_DRN0)
860 #define FP_FX (1ull << FPSCR_FX)
861 #define FP_FEX (1ull << FPSCR_FEX)
862 #define FP_VX (1ull << FPSCR_VX)
863 #define FP_OX (1ull << FPSCR_OX)
864 #define FP_UX (1ull << FPSCR_UX)
865 #define FP_ZX (1ull << FPSCR_ZX)
866 #define FP_XX (1ull << FPSCR_XX)
867 #define FP_VXSNAN (1ull << FPSCR_VXSNAN)
868 #define FP_VXISI (1ull << FPSCR_VXISI)
869 #define FP_VXIDI (1ull << FPSCR_VXIDI)
870 #define FP_VXZDZ (1ull << FPSCR_VXZDZ)
871 #define FP_VXIMZ (1ull << FPSCR_VXIMZ)
872 #define FP_VXVC (1ull << FPSCR_VXVC)
873 #define FP_FR (1ull << FPSCR_FR)
874 #define FP_FI (1ull << FPSCR_FI)
875 #define FP_C (1ull << FPSCR_C)
876 #define FP_FL (1ull << FPSCR_FL)
877 #define FP_FG (1ull << FPSCR_FG)
878 #define FP_FE (1ull << FPSCR_FE)
879 #define FP_FU (1ull << FPSCR_FU)
880 #define FP_FPCC (FP_FL | FP_FG | FP_FE | FP_FU)
881 #define FP_FPRF (FP_C | FP_FPCC)
882 #define FP_VXSOFT (1ull << FPSCR_VXSOFT)
883 #define FP_VXSQRT (1ull << FPSCR_VXSQRT)
884 #define FP_VXCVI (1ull << FPSCR_VXCVI)
885 #define FP_VE (1ull << FPSCR_VE)
886 #define FP_OE (1ull << FPSCR_OE)
887 #define FP_UE (1ull << FPSCR_UE)
888 #define FP_ZE (1ull << FPSCR_ZE)
889 #define FP_XE (1ull << FPSCR_XE)
890 #define FP_NI (1ull << FPSCR_NI)
891 #define FP_RN1 (1ull << FPSCR_RN1)
892 #define FP_RN0 (1ull << FPSCR_RN0)
893 #define FP_RN (FP_RN1 | FP_RN0)
894
895 #define FP_ENABLES (FP_VE | FP_OE | FP_UE | FP_ZE | FP_XE)
896 #define FP_STATUS (FP_FR | FP_FI | FP_FPRF)
897
898 /* the exception bits which can be cleared by mcrfs - includes FX */
899 #define FP_EX_CLEAR_BITS (FP_FX | FP_OX | FP_UX | FP_ZX | \
900 FP_XX | FP_VXSNAN | FP_VXISI | FP_VXIDI | \
901 FP_VXZDZ | FP_VXIMZ | FP_VXVC | FP_VXSOFT | \
902 FP_VXSQRT | FP_VXCVI)
903
904 /* FPSCR bits that can be set by mtfsf, mtfsfi and mtfsb1 */
905 #define FPSCR_MTFS_MASK (~(MAKE_64BIT_MASK(36, 28) | PPC_BIT(28) | \
906 FP_FEX | FP_VX | PPC_BIT(52)))
907
908 /*****************************************************************************/
909 /* Vector status and control register */
910 #define VSCR_NJ 16 /* Vector non-java */
911 #define VSCR_SAT 0 /* Vector saturation */
912
913 /*****************************************************************************/
914 /* BookE e500 MMU registers */
915
916 #define MAS0_NV_SHIFT 0
917 #define MAS0_NV_MASK (0xfff << MAS0_NV_SHIFT)
918
919 #define MAS0_WQ_SHIFT 12
920 #define MAS0_WQ_MASK (3 << MAS0_WQ_SHIFT)
921 /* Write TLB entry regardless of reservation */
922 #define MAS0_WQ_ALWAYS (0 << MAS0_WQ_SHIFT)
923 /* Write TLB entry only already in use */
924 #define MAS0_WQ_COND (1 << MAS0_WQ_SHIFT)
925 /* Clear TLB entry */
926 #define MAS0_WQ_CLR_RSRV (2 << MAS0_WQ_SHIFT)
927
928 #define MAS0_HES_SHIFT 14
929 #define MAS0_HES (1 << MAS0_HES_SHIFT)
930
931 #define MAS0_ESEL_SHIFT 16
932 #define MAS0_ESEL_MASK (0xfff << MAS0_ESEL_SHIFT)
933
934 #define MAS0_TLBSEL_SHIFT 28
935 #define MAS0_TLBSEL_MASK (3 << MAS0_TLBSEL_SHIFT)
936 #define MAS0_TLBSEL_TLB0 (0 << MAS0_TLBSEL_SHIFT)
937 #define MAS0_TLBSEL_TLB1 (1 << MAS0_TLBSEL_SHIFT)
938 #define MAS0_TLBSEL_TLB2 (2 << MAS0_TLBSEL_SHIFT)
939 #define MAS0_TLBSEL_TLB3 (3 << MAS0_TLBSEL_SHIFT)
940
941 #define MAS0_ATSEL_SHIFT 31
942 #define MAS0_ATSEL (1 << MAS0_ATSEL_SHIFT)
943 #define MAS0_ATSEL_TLB 0
944 #define MAS0_ATSEL_LRAT MAS0_ATSEL
945
946 #define MAS1_TSIZE_SHIFT 7
947 #define MAS1_TSIZE_MASK (0x1f << MAS1_TSIZE_SHIFT)
948
949 #define MAS1_TS_SHIFT 12
950 #define MAS1_TS (1 << MAS1_TS_SHIFT)
951
952 #define MAS1_IND_SHIFT 13
953 #define MAS1_IND (1 << MAS1_IND_SHIFT)
954
955 #define MAS1_TID_SHIFT 16
956 #define MAS1_TID_MASK (0x3fff << MAS1_TID_SHIFT)
957
958 #define MAS1_IPROT_SHIFT 30
959 #define MAS1_IPROT (1 << MAS1_IPROT_SHIFT)
960
961 #define MAS1_VALID_SHIFT 31
962 #define MAS1_VALID 0x80000000
963
964 #define MAS2_EPN_SHIFT 12
965 #define MAS2_EPN_MASK (~0ULL << MAS2_EPN_SHIFT)
966
967 #define MAS2_ACM_SHIFT 6
968 #define MAS2_ACM (1 << MAS2_ACM_SHIFT)
969
970 #define MAS2_VLE_SHIFT 5
971 #define MAS2_VLE (1 << MAS2_VLE_SHIFT)
972
973 #define MAS2_W_SHIFT 4
974 #define MAS2_W (1 << MAS2_W_SHIFT)
975
976 #define MAS2_I_SHIFT 3
977 #define MAS2_I (1 << MAS2_I_SHIFT)
978
979 #define MAS2_M_SHIFT 2
980 #define MAS2_M (1 << MAS2_M_SHIFT)
981
982 #define MAS2_G_SHIFT 1
983 #define MAS2_G (1 << MAS2_G_SHIFT)
984
985 #define MAS2_E_SHIFT 0
986 #define MAS2_E (1 << MAS2_E_SHIFT)
987
988 #define MAS3_RPN_SHIFT 12
989 #define MAS3_RPN_MASK (0xfffff << MAS3_RPN_SHIFT)
990
991 #define MAS3_U0 0x00000200
992 #define MAS3_U1 0x00000100
993 #define MAS3_U2 0x00000080
994 #define MAS3_U3 0x00000040
995 #define MAS3_UX 0x00000020
996 #define MAS3_SX 0x00000010
997 #define MAS3_UW 0x00000008
998 #define MAS3_SW 0x00000004
999 #define MAS3_UR 0x00000002
1000 #define MAS3_SR 0x00000001
1001 #define MAS3_SPSIZE_SHIFT 1
1002 #define MAS3_SPSIZE_MASK (0x3e << MAS3_SPSIZE_SHIFT)
1003
1004 #define MAS4_TLBSELD_SHIFT MAS0_TLBSEL_SHIFT
1005 #define MAS4_TLBSELD_MASK MAS0_TLBSEL_MASK
1006 #define MAS4_TIDSELD_MASK 0x00030000
1007 #define MAS4_TIDSELD_PID0 0x00000000
1008 #define MAS4_TIDSELD_PID1 0x00010000
1009 #define MAS4_TIDSELD_PID2 0x00020000
1010 #define MAS4_TIDSELD_PIDZ 0x00030000
1011 #define MAS4_INDD 0x00008000 /* Default IND */
1012 #define MAS4_TSIZED_SHIFT MAS1_TSIZE_SHIFT
1013 #define MAS4_TSIZED_MASK MAS1_TSIZE_MASK
1014 #define MAS4_ACMD 0x00000040
1015 #define MAS4_VLED 0x00000020
1016 #define MAS4_WD 0x00000010
1017 #define MAS4_ID 0x00000008
1018 #define MAS4_MD 0x00000004
1019 #define MAS4_GD 0x00000002
1020 #define MAS4_ED 0x00000001
1021 #define MAS4_WIMGED_MASK 0x0000001f /* Default WIMGE */
1022 #define MAS4_WIMGED_SHIFT 0
1023
1024 #define MAS5_SGS 0x80000000
1025 #define MAS5_SLPID_MASK 0x00000fff
1026
1027 #define MAS6_SPID0 0x3fff0000
1028 #define MAS6_SPID1 0x00007ffe
1029 #define MAS6_ISIZE(x) MAS1_TSIZE(x)
1030 #define MAS6_SAS 0x00000001
1031 #define MAS6_SPID MAS6_SPID0
1032 #define MAS6_SIND 0x00000002 /* Indirect page */
1033 #define MAS6_SIND_SHIFT 1
1034 #define MAS6_SPID_MASK 0x3fff0000
1035 #define MAS6_SPID_SHIFT 16
1036 #define MAS6_ISIZE_MASK 0x00000f80
1037 #define MAS6_ISIZE_SHIFT 7
1038
1039 #define MAS7_RPN 0xffffffff
1040
1041 #define MAS8_TGS 0x80000000
1042 #define MAS8_VF 0x40000000
1043 #define MAS8_TLBPID 0x00000fff
1044
1045 /* Bit definitions for MMUCFG */
1046 #define MMUCFG_MAVN 0x00000003 /* MMU Architecture Version Number */
1047 #define MMUCFG_MAVN_V1 0x00000000 /* v1.0 */
1048 #define MMUCFG_MAVN_V2 0x00000001 /* v2.0 */
1049 #define MMUCFG_NTLBS 0x0000000c /* Number of TLBs */
1050 #define MMUCFG_PIDSIZE 0x000007c0 /* PID Reg Size */
1051 #define MMUCFG_TWC 0x00008000 /* TLB Write Conditional (v2.0) */
1052 #define MMUCFG_LRAT 0x00010000 /* LRAT Supported (v2.0) */
1053 #define MMUCFG_RASIZE 0x00fe0000 /* Real Addr Size */
1054 #define MMUCFG_LPIDSIZE 0x0f000000 /* LPID Reg Size */
1055
1056 /* Bit definitions for MMUCSR0 */
1057 #define MMUCSR0_TLB1FI 0x00000002 /* TLB1 Flash invalidate */
1058 #define MMUCSR0_TLB0FI 0x00000004 /* TLB0 Flash invalidate */
1059 #define MMUCSR0_TLB2FI 0x00000040 /* TLB2 Flash invalidate */
1060 #define MMUCSR0_TLB3FI 0x00000020 /* TLB3 Flash invalidate */
1061 #define MMUCSR0_TLBFI (MMUCSR0_TLB0FI | MMUCSR0_TLB1FI | \
1062 MMUCSR0_TLB2FI | MMUCSR0_TLB3FI)
1063 #define MMUCSR0_TLB0PS 0x00000780 /* TLB0 Page Size */
1064 #define MMUCSR0_TLB1PS 0x00007800 /* TLB1 Page Size */
1065 #define MMUCSR0_TLB2PS 0x00078000 /* TLB2 Page Size */
1066 #define MMUCSR0_TLB3PS 0x00780000 /* TLB3 Page Size */
1067
1068 /* TLBnCFG encoding */
1069 #define TLBnCFG_N_ENTRY 0x00000fff /* number of entries */
1070 #define TLBnCFG_HES 0x00002000 /* HW select supported */
1071 #define TLBnCFG_AVAIL 0x00004000 /* variable page size */
1072 #define TLBnCFG_IPROT 0x00008000 /* IPROT supported */
1073 #define TLBnCFG_GTWE 0x00010000 /* Guest can write */
1074 #define TLBnCFG_IND 0x00020000 /* IND entries supported */
1075 #define TLBnCFG_PT 0x00040000 /* Can load from page table */
1076 #define TLBnCFG_MINSIZE 0x00f00000 /* Minimum Page Size (v1.0) */
1077 #define TLBnCFG_MINSIZE_SHIFT 20
1078 #define TLBnCFG_MAXSIZE 0x000f0000 /* Maximum Page Size (v1.0) */
1079 #define TLBnCFG_MAXSIZE_SHIFT 16
1080 #define TLBnCFG_ASSOC 0xff000000 /* Associativity */
1081 #define TLBnCFG_ASSOC_SHIFT 24
1082
1083 /* TLBnPS encoding */
1084 #define TLBnPS_4K 0x00000004
1085 #define TLBnPS_8K 0x00000008
1086 #define TLBnPS_16K 0x00000010
1087 #define TLBnPS_32K 0x00000020
1088 #define TLBnPS_64K 0x00000040
1089 #define TLBnPS_128K 0x00000080
1090 #define TLBnPS_256K 0x00000100
1091 #define TLBnPS_512K 0x00000200
1092 #define TLBnPS_1M 0x00000400
1093 #define TLBnPS_2M 0x00000800
1094 #define TLBnPS_4M 0x00001000
1095 #define TLBnPS_8M 0x00002000
1096 #define TLBnPS_16M 0x00004000
1097 #define TLBnPS_32M 0x00008000
1098 #define TLBnPS_64M 0x00010000
1099 #define TLBnPS_128M 0x00020000
1100 #define TLBnPS_256M 0x00040000
1101 #define TLBnPS_512M 0x00080000
1102 #define TLBnPS_1G 0x00100000
1103 #define TLBnPS_2G 0x00200000
1104 #define TLBnPS_4G 0x00400000
1105 #define TLBnPS_8G 0x00800000
1106 #define TLBnPS_16G 0x01000000
1107 #define TLBnPS_32G 0x02000000
1108 #define TLBnPS_64G 0x04000000
1109 #define TLBnPS_128G 0x08000000
1110 #define TLBnPS_256G 0x10000000
1111
1112 /* tlbilx action encoding */
1113 #define TLBILX_T_ALL 0
1114 #define TLBILX_T_TID 1
1115 #define TLBILX_T_FULLMATCH 3
1116 #define TLBILX_T_CLASS0 4
1117 #define TLBILX_T_CLASS1 5
1118 #define TLBILX_T_CLASS2 6
1119 #define TLBILX_T_CLASS3 7
1120
1121 /* BookE 2.06 helper defines */
1122
1123 #define BOOKE206_FLUSH_TLB0 (1 << 0)
1124 #define BOOKE206_FLUSH_TLB1 (1 << 1)
1125 #define BOOKE206_FLUSH_TLB2 (1 << 2)
1126 #define BOOKE206_FLUSH_TLB3 (1 << 3)
1127
1128 /* number of possible TLBs */
1129 #define BOOKE206_MAX_TLBN 4
1130
1131 #define EPID_EPID_SHIFT 0x0
1132 #define EPID_EPID 0xFF
1133 #define EPID_ELPID_SHIFT 0x10
1134 #define EPID_ELPID 0x3F0000
1135 #define EPID_EGS 0x20000000
1136 #define EPID_EGS_SHIFT 29
1137 #define EPID_EAS 0x40000000
1138 #define EPID_EAS_SHIFT 30
1139 #define EPID_EPR 0x80000000
1140 #define EPID_EPR_SHIFT 31
1141 /* We don't support EGS and ELPID */
1142 #define EPID_MASK (EPID_EPID | EPID_EAS | EPID_EPR)
1143
1144 /*****************************************************************************/
1145 /* Server and Embedded Processor Control */
1146
1147 #define DBELL_TYPE_SHIFT 27
1148 #define DBELL_TYPE_MASK (0x1f << DBELL_TYPE_SHIFT)
1149 #define DBELL_TYPE_DBELL (0x00 << DBELL_TYPE_SHIFT)
1150 #define DBELL_TYPE_DBELL_CRIT (0x01 << DBELL_TYPE_SHIFT)
1151 #define DBELL_TYPE_G_DBELL (0x02 << DBELL_TYPE_SHIFT)
1152 #define DBELL_TYPE_G_DBELL_CRIT (0x03 << DBELL_TYPE_SHIFT)
1153 #define DBELL_TYPE_G_DBELL_MC (0x04 << DBELL_TYPE_SHIFT)
1154
1155 #define DBELL_TYPE_DBELL_SERVER (0x05 << DBELL_TYPE_SHIFT)
1156
1157 #define DBELL_BRDCAST PPC_BIT(37)
1158 #define DBELL_LPIDTAG_SHIFT 14
1159 #define DBELL_LPIDTAG_MASK (0xfff << DBELL_LPIDTAG_SHIFT)
1160 #define DBELL_PIRTAG_MASK 0x3fff
1161
1162 #define DBELL_PROCIDTAG_MASK PPC_BITMASK(44, 63)
1163
1164 #define PPC_PAGE_SIZES_MAX_SZ 8
1165
1166 struct ppc_radix_page_info {
1167 uint32_t count;
1168 uint32_t entries[PPC_PAGE_SIZES_MAX_SZ];
1169 };
1170
1171 /*****************************************************************************/
1172 /* Dynamic Execution Control Register */
1173
1174 #define DEXCR_ASPECT(name, num) \
1175 FIELD(DEXCR, PNH_##name, PPC_BIT_NR(num), 1) \
1176 FIELD(DEXCR, PRO_##name, PPC_BIT_NR(num + 32), 1) \
1177 FIELD(HDEXCR, HNU_##name, PPC_BIT_NR(num), 1) \
1178 FIELD(HDEXCR, ENF_##name, PPC_BIT_NR(num + 32), 1) \
1179
1180 DEXCR_ASPECT(SBHE, 0)
1181 DEXCR_ASPECT(IBRTPD, 1)
1182 DEXCR_ASPECT(SRAPD, 4)
1183 DEXCR_ASPECT(NPHIE, 5)
1184 DEXCR_ASPECT(PHIE, 6)
1185
1186 /*****************************************************************************/
1187 /* PowerNV ChipTOD and TimeBase State Machine */
1188 struct pnv_tod_tbst {
1189 int tb_ready_for_tod; /* core TB ready to receive TOD from chiptod */
1190 int tod_sent_to_tb; /* chiptod sent TOD to the core TB */
1191
1192 /*
1193 * "Timers" for async TBST events are simulated by mfTFAC because TFAC
1194 * is polled for such events. These are just used to ensure firmware
1195 * performs the polling at least a few times.
1196 */
1197 int tb_state_timer;
1198 int tb_sync_pulse_timer;
1199 };
1200
1201 /*****************************************************************************/
1202 /* The whole PowerPC CPU context */
1203
1204 /*
1205 * PowerPC needs eight modes for different hypervisor/supervisor/guest
1206 * + real/paged mode combinations. The other two modes are for
1207 * external PID load/store.
1208 */
1209 #define PPC_TLB_EPID_LOAD 8
1210 #define PPC_TLB_EPID_STORE 9
1211
1212 #define PPC_CPU_OPCODES_LEN 0x40
1213 #define PPC_CPU_INDIRECT_OPCODES_LEN 0x20
1214
1215 struct CPUArchState {
1216 /* Most commonly used resources during translated code execution first */
1217 target_ulong gpr[32]; /* general purpose registers */
1218 target_ulong gprh[32]; /* storage for GPR MSB, used by the SPE extension */
1219 target_ulong lr;
1220 target_ulong ctr;
1221 uint32_t crf[8]; /* condition register */
1222 #if defined(TARGET_PPC64)
1223 target_ulong cfar;
1224 #endif
1225 target_ulong xer; /* XER (with SO, OV, CA split out) */
1226 target_ulong so;
1227 target_ulong ov;
1228 target_ulong ca;
1229 target_ulong ov32;
1230 target_ulong ca32;
1231
1232 target_ulong reserve_addr; /* Reservation address */
1233 target_ulong reserve_length; /* Reservation larx op size (bytes) */
1234 target_ulong reserve_val; /* Reservation value */
1235 #if defined(TARGET_PPC64)
1236 target_ulong reserve_val2;
1237 #endif
1238
1239 /* These are used in supervisor mode only */
1240 target_ulong msr; /* machine state register */
1241 target_ulong tgpr[4]; /* temporary general purpose registers, */
1242 /* used to speed-up TLB assist handlers */
1243
1244 target_ulong nip; /* next instruction pointer */
1245
1246 /* when a memory exception occurs, the access type is stored here */
1247 int access_type;
1248
1249 #if !defined(CONFIG_USER_ONLY)
1250 /* MMU context, only relevant for full system emulation */
1251 #if defined(TARGET_PPC64)
1252 ppc_slb_t slb[MAX_SLB_ENTRIES]; /* PowerPC 64 SLB area */
1253 struct CPUBreakpoint *ciabr_breakpoint;
1254 struct CPUWatchpoint *dawr0_watchpoint;
1255 #endif
1256 target_ulong sr[32]; /* segment registers */
1257 uint32_t nb_BATs; /* number of BATs */
1258 target_ulong DBAT[2][8];
1259 target_ulong IBAT[2][8];
1260 /* PowerPC TLB registers (for 4xx, e500 and 60x software driven TLBs) */
1261 int32_t nb_tlb; /* Total number of TLB */
1262 int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */
1263 int nb_ways; /* Number of ways in the TLB set */
1264 int last_way; /* Last used way used to allocate TLB in a LRU way */
1265 int id_tlbs; /* If 1, MMU has separated TLBs for instructions & data */
1266 int nb_pids; /* Number of available PID registers */
1267 int tlb_type; /* Type of TLB we're dealing with */
1268 ppc_tlb_t tlb; /* TLB is optional. Allocate them only if needed */
1269 #ifdef CONFIG_KVM
1270 bool tlb_dirty; /* Set to non-zero when modifying TLB */
1271 bool kvm_sw_tlb; /* non-zero if KVM SW TLB API is active */
1272 #endif /* CONFIG_KVM */
1273 uint32_t tlb_need_flush; /* Delayed flush needed */
1274 #define TLB_NEED_LOCAL_FLUSH 0x1
1275 #define TLB_NEED_GLOBAL_FLUSH 0x2
1276
1277 #if defined(TARGET_PPC64)
1278 /* PowerNV chiptod / timebase facility state. */
1279 /* Would be nice to put these into PnvCore */
1280 struct pnv_tod_tbst pnv_tod_tbst;
1281 #endif
1282 #endif
1283
1284 /* Other registers */
1285 target_ulong spr[1024]; /* special purpose registers */
1286 ppc_spr_t spr_cb[1024];
1287 /* Composite status for PMC[1-6] enabled and counting insns or cycles. */
1288 uint8_t pmc_ins_cnt;
1289 uint8_t pmc_cyc_cnt;
1290 /* Vector status and control register, minus VSCR_SAT */
1291 uint32_t vscr;
1292 /* VSX registers (including FP and AVR) */
1293 ppc_vsr_t vsr[64] QEMU_ALIGNED(16);
1294 /* Non-zero if and only if VSCR_SAT should be set */
1295 ppc_vsr_t vscr_sat QEMU_ALIGNED(16);
1296 /* SPE registers */
1297 uint64_t spe_acc;
1298 uint32_t spe_fscr;
1299 /* SPE and Altivec share status as they'll never be used simultaneously */
1300 float_status vec_status;
1301 float_status fp_status; /* Floating point execution context */
1302 target_ulong fpscr; /* Floating point status and control register */
1303
1304 /* Internal devices resources */
1305 ppc_tb_t *tb_env; /* Time base and decrementer */
1306 ppc_dcr_t *dcr_env; /* Device control registers */
1307
1308 int dcache_line_size;
1309 int icache_line_size;
1310
1311 /* These resources are used during exception processing */
1312 /* CPU model definition */
1313 target_ulong msr_mask;
1314 powerpc_mmu_t mmu_model;
1315 powerpc_excp_t excp_model;
1316 powerpc_input_t bus_model;
1317 int bfd_mach;
1318 uint32_t flags;
1319 uint64_t insns_flags;
1320 uint64_t insns_flags2;
1321
1322 int error_code;
1323 uint32_t pending_interrupts;
1324 #if !defined(CONFIG_USER_ONLY)
1325 uint64_t excp_stats[POWERPC_EXCP_NB];
1326 /*
1327 * This is the IRQ controller, which is implementation dependent and only
1328 * relevant when emulating a complete machine. Note that this isn't used
1329 * by recent Book3s compatible CPUs (POWER7 and newer).
1330 */
1331 uint32_t irq_input_state;
1332
1333 target_ulong excp_vectors[POWERPC_EXCP_NB]; /* Exception vectors */
1334 target_ulong excp_prefix;
1335 target_ulong ivor_mask;
1336 target_ulong ivpr_mask;
1337 target_ulong hreset_vector;
1338 hwaddr mpic_iack;
1339 bool mpic_proxy; /* true if the external proxy facility mode is enabled */
1340 bool has_hv_mode; /* set when the processor has an HV mode, thus HV priv */
1341 /* instructions and SPRs are diallowed if MSR:HV is 0 */
1342 /*
1343 * On P7/P8/P9, set when in PM state so we need to handle resume in a
1344 * special way (such as routing some resume causes to 0x100, i.e. sreset).
1345 */
1346 bool resume_as_sreset;
1347 #endif
1348
1349 /* These resources are used only in TCG */
1350 uint32_t hflags;
1351 target_ulong hflags_compat_nmsr; /* for migration compatibility */
1352
1353 /* Power management */
1354 int (*check_pow)(CPUPPCState *env);
1355
1356 #if !defined(CONFIG_USER_ONLY)
1357 void *load_info; /* holds boot loading state */
1358 #endif
1359
1360 /* booke timers */
1361
1362 /*
1363 * Specifies bit locations of the Time Base used to signal a fixed timer
1364 * exception on a transition from 0 to 1 (watchdog or fixed-interval timer)
1365 *
1366 * 0 selects the least significant bit, 63 selects the most significant bit
1367 */
1368 uint8_t fit_period[4];
1369 uint8_t wdt_period[4];
1370
1371 /* Transactional memory state */
1372 target_ulong tm_gpr[32];
1373 ppc_avr_t tm_vsr[64];
1374 uint64_t tm_cr;
1375 uint64_t tm_lr;
1376 uint64_t tm_ctr;
1377 uint64_t tm_fpscr;
1378 uint64_t tm_amr;
1379 uint64_t tm_ppr;
1380 uint64_t tm_vrsave;
1381 uint32_t tm_vscr;
1382 uint64_t tm_dscr;
1383 uint64_t tm_tar;
1384
1385 /*
1386 * Timers used to fire performance monitor alerts
1387 * when counting cycles.
1388 */
1389 QEMUTimer *pmu_cyc_overflow_timers[PMU_COUNTERS_NUM];
1390
1391 /*
1392 * PMU base time value used by the PMU to calculate
1393 * running cycles.
1394 */
1395 uint64_t pmu_base_time;
1396 };
1397
1398 #define _CORE_ID(cs) \
1399 (POWERPC_CPU(cs)->env.spr_cb[SPR_PIR].default_value & ~(cs->nr_threads - 1))
1400
1401 #define THREAD_SIBLING_FOREACH(cs, cs_sibling) \
1402 CPU_FOREACH(cs_sibling) \
1403 if (_CORE_ID(cs) == _CORE_ID(cs_sibling))
1404
1405 #define SET_FIT_PERIOD(a_, b_, c_, d_) \
1406 do { \
1407 env->fit_period[0] = (a_); \
1408 env->fit_period[1] = (b_); \
1409 env->fit_period[2] = (c_); \
1410 env->fit_period[3] = (d_); \
1411 } while (0)
1412
1413 #define SET_WDT_PERIOD(a_, b_, c_, d_) \
1414 do { \
1415 env->wdt_period[0] = (a_); \
1416 env->wdt_period[1] = (b_); \
1417 env->wdt_period[2] = (c_); \
1418 env->wdt_period[3] = (d_); \
1419 } while (0)
1420
1421 typedef struct PPCVirtualHypervisor PPCVirtualHypervisor;
1422 typedef struct PPCVirtualHypervisorClass PPCVirtualHypervisorClass;
1423
1424 /**
1425 * PowerPCCPU:
1426 * @env: #CPUPPCState
1427 * @vcpu_id: vCPU identifier given to KVM
1428 * @compat_pvr: Current logical PVR, zero if in "raw" mode
1429 *
1430 * A PowerPC CPU.
1431 */
1432 struct ArchCPU {
1433 CPUState parent_obj;
1434
1435 CPUPPCState env;
1436
1437 int vcpu_id;
1438 uint32_t compat_pvr;
1439 PPCVirtualHypervisor *vhyp;
1440 void *machine_data;
1441 int32_t node_id; /* NUMA node this CPU belongs to */
1442 PPCHash64Options *hash64_opts;
1443
1444 /* Those resources are used only during code translation */
1445 /* opcode handlers */
1446 opc_handler_t *opcodes[PPC_CPU_OPCODES_LEN];
1447
1448 /* Fields related to migration compatibility hacks */
1449 bool pre_2_8_migration;
1450 target_ulong mig_msr_mask;
1451 uint64_t mig_insns_flags;
1452 uint64_t mig_insns_flags2;
1453 uint32_t mig_nb_BATs;
1454 bool pre_2_10_migration;
1455 bool pre_3_0_migration;
1456 int32_t mig_slb_nr;
1457 };
1458
1459 /**
1460 * PowerPCCPUClass:
1461 * @parent_realize: The parent class' realize handler.
1462 * @parent_phases: The parent class' reset phase handlers.
1463 *
1464 * A PowerPC CPU model.
1465 */
1466 struct PowerPCCPUClass {
1467 CPUClass parent_class;
1468
1469 DeviceRealize parent_realize;
1470 DeviceUnrealize parent_unrealize;
1471 ResettablePhases parent_phases;
1472 void (*parent_parse_features)(const char *type, char *str, Error **errp);
1473
1474 uint32_t pvr;
1475 /*
1476 * If @best is false, match if pcc is in the family of pvr
1477 * Else match only if pcc is the best match for pvr in this family.
1478 */
1479 bool (*pvr_match)(struct PowerPCCPUClass *pcc, uint32_t pvr, bool best);
1480 uint64_t pcr_mask; /* Available bits in PCR register */
1481 uint64_t pcr_supported; /* Bits for supported PowerISA versions */
1482 uint32_t svr;
1483 uint64_t insns_flags;
1484 uint64_t insns_flags2;
1485 uint64_t msr_mask;
1486 uint64_t lpcr_mask; /* Available bits in the LPCR */
1487 uint64_t lpcr_pm; /* Power-saving mode Exit Cause Enable bits */
1488 powerpc_mmu_t mmu_model;
1489 powerpc_excp_t excp_model;
1490 powerpc_input_t bus_model;
1491 uint32_t flags;
1492 int bfd_mach;
1493 uint32_t l1_dcache_size, l1_icache_size;
1494 #ifndef CONFIG_USER_ONLY
1495 GDBFeature gdb_spr;
1496 #endif
1497 const PPCHash64Options *hash64_opts;
1498 struct ppc_radix_page_info *radix_page_info;
1499 uint32_t lrg_decr_bits;
1500 int n_host_threads;
1501 void (*init_proc)(CPUPPCState *env);
1502 int (*check_pow)(CPUPPCState *env);
1503 };
1504
1505 ObjectClass *ppc_cpu_class_by_name(const char *name);
1506 PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr);
1507 PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr);
1508 PowerPCCPUClass *ppc_cpu_get_family_class(PowerPCCPUClass *pcc);
1509
1510 #ifndef CONFIG_USER_ONLY
1511 struct PPCVirtualHypervisorClass {
1512 InterfaceClass parent;
1513 bool (*cpu_in_nested)(PowerPCCPU *cpu);
1514 void (*deliver_hv_excp)(PowerPCCPU *cpu, int excp);
1515 void (*hypercall)(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu);
1516 hwaddr (*hpt_mask)(PPCVirtualHypervisor *vhyp);
1517 const ppc_hash_pte64_t *(*map_hptes)(PPCVirtualHypervisor *vhyp,
1518 hwaddr ptex, int n);
1519 void (*unmap_hptes)(PPCVirtualHypervisor *vhyp,
1520 const ppc_hash_pte64_t *hptes,
1521 hwaddr ptex, int n);
1522 void (*hpte_set_c)(PPCVirtualHypervisor *vhyp, hwaddr ptex, uint64_t pte1);
1523 void (*hpte_set_r)(PPCVirtualHypervisor *vhyp, hwaddr ptex, uint64_t pte1);
1524 bool (*get_pate)(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu,
1525 target_ulong lpid, ppc_v3_pate_t *entry);
1526 target_ulong (*encode_hpt_for_kvm_pr)(PPCVirtualHypervisor *vhyp);
1527 void (*cpu_exec_enter)(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu);
1528 void (*cpu_exec_exit)(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu);
1529 };
1530
1531 #define TYPE_PPC_VIRTUAL_HYPERVISOR "ppc-virtual-hypervisor"
1532 DECLARE_OBJ_CHECKERS(PPCVirtualHypervisor, PPCVirtualHypervisorClass,
1533 PPC_VIRTUAL_HYPERVISOR, TYPE_PPC_VIRTUAL_HYPERVISOR)
1534
1535 static inline bool vhyp_cpu_in_nested(PowerPCCPU *cpu)
1536 {
1537 return PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp)->cpu_in_nested(cpu);
1538 }
1539 #endif /* CONFIG_USER_ONLY */
1540
1541 void ppc_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
1542 int ppc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
1543 int ppc_cpu_gdb_read_register_apple(CPUState *cpu, GByteArray *buf, int reg);
1544 int ppc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
1545 int ppc_cpu_gdb_write_register_apple(CPUState *cpu, uint8_t *buf, int reg);
1546 #ifndef CONFIG_USER_ONLY
1547 hwaddr ppc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
1548 #endif
1549 int ppc64_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
1550 int cpuid, DumpState *s);
1551 int ppc32_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
1552 int cpuid, DumpState *s);
1553 #ifndef CONFIG_USER_ONLY
1554 void ppc_maybe_interrupt(CPUPPCState *env);
1555 void ppc_cpu_do_interrupt(CPUState *cpu);
1556 bool ppc_cpu_exec_interrupt(CPUState *cpu, int int_req);
1557 void ppc_cpu_do_system_reset(CPUState *cs);
1558 void ppc_cpu_do_fwnmi_machine_check(CPUState *cs, target_ulong vector);
1559 extern const VMStateDescription vmstate_ppc_cpu;
1560 #endif
1561
1562 /*****************************************************************************/
1563 void ppc_translate_init(void);
1564
1565 #if !defined(CONFIG_USER_ONLY)
1566 void ppc_store_sdr1(CPUPPCState *env, target_ulong value);
1567 void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val);
1568 void ppc_update_ciabr(CPUPPCState *env);
1569 void ppc_store_ciabr(CPUPPCState *env, target_ulong value);
1570 void ppc_update_daw0(CPUPPCState *env);
1571 void ppc_store_dawr0(CPUPPCState *env, target_ulong value);
1572 void ppc_store_dawrx0(CPUPPCState *env, uint32_t value);
1573 #endif /* !defined(CONFIG_USER_ONLY) */
1574 void ppc_store_msr(CPUPPCState *env, target_ulong value);
1575
1576 void ppc_cpu_list(void);
1577
1578 /* Time-base and decrementer management */
1579 uint64_t cpu_ppc_load_tbl(CPUPPCState *env);
1580 uint32_t cpu_ppc_load_tbu(CPUPPCState *env);
1581 void cpu_ppc_store_tbu(CPUPPCState *env, uint32_t value);
1582 void cpu_ppc_store_tbl(CPUPPCState *env, uint32_t value);
1583 uint64_t cpu_ppc_load_atbl(CPUPPCState *env);
1584 uint32_t cpu_ppc_load_atbu(CPUPPCState *env);
1585 void cpu_ppc_store_atbl(CPUPPCState *env, uint32_t value);
1586 void cpu_ppc_store_atbu(CPUPPCState *env, uint32_t value);
1587 uint64_t cpu_ppc_load_vtb(CPUPPCState *env);
1588 void cpu_ppc_store_vtb(CPUPPCState *env, uint64_t value);
1589 bool ppc_decr_clear_on_delivery(CPUPPCState *env);
1590 target_ulong cpu_ppc_load_decr(CPUPPCState *env);
1591 void cpu_ppc_store_decr(CPUPPCState *env, target_ulong value);
1592 target_ulong cpu_ppc_load_hdecr(CPUPPCState *env);
1593 void cpu_ppc_store_hdecr(CPUPPCState *env, target_ulong value);
1594 void cpu_ppc_store_tbu40(CPUPPCState *env, uint64_t value);
1595 uint64_t cpu_ppc_load_purr(CPUPPCState *env);
1596 void cpu_ppc_store_purr(CPUPPCState *env, uint64_t value);
1597 #if !defined(CONFIG_USER_ONLY)
1598 target_ulong load_40x_pit(CPUPPCState *env);
1599 void store_40x_pit(CPUPPCState *env, target_ulong val);
1600 void store_40x_dbcr0(CPUPPCState *env, uint32_t val);
1601 void store_40x_sler(CPUPPCState *env, uint32_t val);
1602 void store_40x_tcr(CPUPPCState *env, target_ulong val);
1603 void store_40x_tsr(CPUPPCState *env, target_ulong val);
1604 void store_booke_tcr(CPUPPCState *env, target_ulong val);
1605 void store_booke_tsr(CPUPPCState *env, target_ulong val);
1606 void ppc_tlb_invalidate_all(CPUPPCState *env);
1607 void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr);
1608 void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp);
1609 void cpu_ppc_set_1lpar(PowerPCCPU *cpu);
1610 int ppcmas_tlb_check(CPUPPCState *env, ppcmas_tlb_t *tlb, hwaddr *raddrp,
1611 target_ulong address, uint32_t pid);
1612 int ppcemb_tlb_search(CPUPPCState *env, target_ulong address, uint32_t pid);
1613 hwaddr booke206_tlb_to_page_size(CPUPPCState *env, ppcmas_tlb_t *tlb);
1614 #endif
1615
1616 void ppc_store_fpscr(CPUPPCState *env, target_ulong val);
1617 void helper_hfscr_facility_check(CPUPPCState *env, uint32_t bit,
1618 const char *caller, uint32_t cause);
1619
1620 static inline uint64_t ppc_dump_gpr(CPUPPCState *env, int gprn)
1621 {
1622 uint64_t gprv;
1623
1624 gprv = env->gpr[gprn];
1625 if (env->flags & POWERPC_FLAG_SPE) {
1626 /*
1627 * If the CPU implements the SPE extension, we have to get the
1628 * high bits of the GPR from the gprh storage area
1629 */
1630 gprv &= 0xFFFFFFFFULL;
1631 gprv |= (uint64_t)env->gprh[gprn] << 32;
1632 }
1633
1634 return gprv;
1635 }
1636
1637 /* Device control registers */
1638 int ppc_dcr_read(ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp);
1639 int ppc_dcr_write(ppc_dcr_t *dcr_env, int dcrn, uint32_t val);
1640
1641 #define cpu_list ppc_cpu_list
1642
1643 /* MMU modes definitions */
1644 #define MMU_USER_IDX 0
1645 static inline int ppc_env_mmu_index(CPUPPCState *env, bool ifetch)
1646 {
1647 #ifdef CONFIG_USER_ONLY
1648 return MMU_USER_IDX;
1649 #else
1650 return (env->hflags >> (ifetch ? HFLAGS_IMMU_IDX : HFLAGS_DMMU_IDX)) & 7;
1651 #endif
1652 }
1653
1654 /* Compatibility modes */
1655 #if defined(TARGET_PPC64)
1656 bool ppc_check_compat(PowerPCCPU *cpu, uint32_t compat_pvr,
1657 uint32_t min_compat_pvr, uint32_t max_compat_pvr);
1658 bool ppc_type_check_compat(const char *cputype, uint32_t compat_pvr,
1659 uint32_t min_compat_pvr, uint32_t max_compat_pvr);
1660
1661 int ppc_set_compat(PowerPCCPU *cpu, uint32_t compat_pvr, Error **errp);
1662
1663 #if !defined(CONFIG_USER_ONLY)
1664 int ppc_set_compat_all(uint32_t compat_pvr, Error **errp);
1665 int ppc_init_compat_all(uint32_t compat_pvr, Error **errp);
1666 #endif
1667 int ppc_compat_max_vthreads(PowerPCCPU *cpu);
1668 void ppc_compat_add_property(Object *obj, const char *name,
1669 uint32_t *compat_pvr, const char *basedesc);
1670 #endif /* defined(TARGET_PPC64) */
1671
1672 #include "exec/cpu-all.h"
1673
1674 /*****************************************************************************/
1675 /* CRF definitions */
1676 #define CRF_LT_BIT 3
1677 #define CRF_GT_BIT 2
1678 #define CRF_EQ_BIT 1
1679 #define CRF_SO_BIT 0
1680 #define CRF_LT (1 << CRF_LT_BIT)
1681 #define CRF_GT (1 << CRF_GT_BIT)
1682 #define CRF_EQ (1 << CRF_EQ_BIT)
1683 #define CRF_SO (1 << CRF_SO_BIT)
1684 /* For SPE extensions */
1685 #define CRF_CH (1 << CRF_LT_BIT)
1686 #define CRF_CL (1 << CRF_GT_BIT)
1687 #define CRF_CH_OR_CL (1 << CRF_EQ_BIT)
1688 #define CRF_CH_AND_CL (1 << CRF_SO_BIT)
1689
1690 /* XER definitions */
1691 #define XER_SO 31
1692 #define XER_OV 30
1693 #define XER_CA 29
1694 #define XER_OV32 19
1695 #define XER_CA32 18
1696 #define XER_CMP 8
1697 #define XER_BC 0
1698 #define xer_so (env->so)
1699 #define xer_cmp ((env->xer >> XER_CMP) & 0xFF)
1700 #define xer_bc ((env->xer >> XER_BC) & 0x7F)
1701
1702 /* SPR definitions */
1703 #define SPR_MQ (0x000)
1704 #define SPR_XER (0x001)
1705 #define SPR_LR (0x008)
1706 #define SPR_CTR (0x009)
1707 #define SPR_UAMR (0x00D)
1708 #define SPR_DSCR (0x011)
1709 #define SPR_DSISR (0x012)
1710 #define SPR_DAR (0x013)
1711 #define SPR_DECR (0x016)
1712 #define SPR_SDR1 (0x019)
1713 #define SPR_SRR0 (0x01A)
1714 #define SPR_SRR1 (0x01B)
1715 #define SPR_CFAR (0x01C)
1716 #define SPR_AMR (0x01D)
1717 #define SPR_ACOP (0x01F)
1718 #define SPR_BOOKE_PID (0x030)
1719 #define SPR_BOOKS_PID (0x030)
1720 #define SPR_BOOKE_DECAR (0x036)
1721 #define SPR_BOOKE_CSRR0 (0x03A)
1722 #define SPR_BOOKE_CSRR1 (0x03B)
1723 #define SPR_BOOKE_DEAR (0x03D)
1724 #define SPR_IAMR (0x03D)
1725 #define SPR_BOOKE_ESR (0x03E)
1726 #define SPR_BOOKE_IVPR (0x03F)
1727 #define SPR_MPC_EIE (0x050)
1728 #define SPR_MPC_EID (0x051)
1729 #define SPR_MPC_NRI (0x052)
1730 #define SPR_TFHAR (0x080)
1731 #define SPR_TFIAR (0x081)
1732 #define SPR_TEXASR (0x082)
1733 #define SPR_TEXASRU (0x083)
1734 #define SPR_UCTRL (0x088)
1735 #define SPR_TIDR (0x090)
1736 #define SPR_MPC_CMPA (0x090)
1737 #define SPR_MPC_CMPB (0x091)
1738 #define SPR_MPC_CMPC (0x092)
1739 #define SPR_MPC_CMPD (0x093)
1740 #define SPR_MPC_ECR (0x094)
1741 #define SPR_MPC_DER (0x095)
1742 #define SPR_MPC_COUNTA (0x096)
1743 #define SPR_MPC_COUNTB (0x097)
1744 #define SPR_CTRL (0x098)
1745 #define SPR_MPC_CMPE (0x098)
1746 #define SPR_MPC_CMPF (0x099)
1747 #define SPR_FSCR (0x099)
1748 #define SPR_MPC_CMPG (0x09A)
1749 #define SPR_MPC_CMPH (0x09B)
1750 #define SPR_MPC_LCTRL1 (0x09C)
1751 #define SPR_MPC_LCTRL2 (0x09D)
1752 #define SPR_UAMOR (0x09D)
1753 #define SPR_MPC_ICTRL (0x09E)
1754 #define SPR_MPC_BAR (0x09F)
1755 #define SPR_PSPB (0x09F)
1756 #define SPR_DPDES (0x0B0)
1757 #define SPR_DAWR0 (0x0B4)
1758 #define SPR_RPR (0x0BA)
1759 #define SPR_CIABR (0x0BB)
1760 #define SPR_DAWRX0 (0x0BC)
1761 #define SPR_HFSCR (0x0BE)
1762 #define SPR_VRSAVE (0x100)
1763 #define SPR_USPRG0 (0x100)
1764 #define SPR_USPRG1 (0x101)
1765 #define SPR_USPRG2 (0x102)
1766 #define SPR_USPRG3 (0x103)
1767 #define SPR_USPRG4 (0x104)
1768 #define SPR_USPRG5 (0x105)
1769 #define SPR_USPRG6 (0x106)
1770 #define SPR_USPRG7 (0x107)
1771 #define SPR_TBL (0x10C)
1772 #define SPR_TBU (0x10D)
1773 #define SPR_SPRG0 (0x110)
1774 #define SPR_SPRG1 (0x111)
1775 #define SPR_SPRG2 (0x112)
1776 #define SPR_SPRG3 (0x113)
1777 #define SPR_SPRG4 (0x114)
1778 #define SPR_SCOMC (0x114)
1779 #define SPR_SPRG5 (0x115)
1780 #define SPR_SCOMD (0x115)
1781 #define SPR_SPRG6 (0x116)
1782 #define SPR_SPRG7 (0x117)
1783 #define SPR_ASR (0x118)
1784 #define SPR_EAR (0x11A)
1785 #define SPR_WR_TBL (0x11C)
1786 #define SPR_WR_TBU (0x11D)
1787 #define SPR_TBU40 (0x11E)
1788 #define SPR_SVR (0x11E)
1789 #define SPR_BOOKE_PIR (0x11E)
1790 #define SPR_PVR (0x11F)
1791 #define SPR_HSPRG0 (0x130)
1792 #define SPR_BOOKE_DBSR (0x130)
1793 #define SPR_HSPRG1 (0x131)
1794 #define SPR_HDSISR (0x132)
1795 #define SPR_HDAR (0x133)
1796 #define SPR_BOOKE_EPCR (0x133)
1797 #define SPR_SPURR (0x134)
1798 #define SPR_BOOKE_DBCR0 (0x134)
1799 #define SPR_IBCR (0x135)
1800 #define SPR_PURR (0x135)
1801 #define SPR_BOOKE_DBCR1 (0x135)
1802 #define SPR_DBCR (0x136)
1803 #define SPR_HDEC (0x136)
1804 #define SPR_BOOKE_DBCR2 (0x136)
1805 #define SPR_HIOR (0x137)
1806 #define SPR_MBAR (0x137)
1807 #define SPR_RMOR (0x138)
1808 #define SPR_BOOKE_IAC1 (0x138)
1809 #define SPR_HRMOR (0x139)
1810 #define SPR_BOOKE_IAC2 (0x139)
1811 #define SPR_HSRR0 (0x13A)
1812 #define SPR_BOOKE_IAC3 (0x13A)
1813 #define SPR_HSRR1 (0x13B)
1814 #define SPR_BOOKE_IAC4 (0x13B)
1815 #define SPR_BOOKE_DAC1 (0x13C)
1816 #define SPR_MMCRH (0x13C)
1817 #define SPR_DABR2 (0x13D)
1818 #define SPR_BOOKE_DAC2 (0x13D)
1819 #define SPR_TFMR (0x13D)
1820 #define SPR_BOOKE_DVC1 (0x13E)
1821 #define SPR_LPCR (0x13E)
1822 #define SPR_BOOKE_DVC2 (0x13F)
1823 #define SPR_LPIDR (0x13F)
1824 #define SPR_BOOKE_TSR (0x150)
1825 #define SPR_HMER (0x150)
1826 #define SPR_HMEER (0x151)
1827 #define SPR_PCR (0x152)
1828 #define SPR_HEIR (0x153)
1829 #define SPR_BOOKE_LPIDR (0x152)
1830 #define SPR_BOOKE_TCR (0x154)
1831 #define SPR_BOOKE_TLB0PS (0x158)
1832 #define SPR_BOOKE_TLB1PS (0x159)
1833 #define SPR_BOOKE_TLB2PS (0x15A)
1834 #define SPR_BOOKE_TLB3PS (0x15B)
1835 #define SPR_AMOR (0x15D)
1836 #define SPR_BOOKE_MAS7_MAS3 (0x174)
1837 #define SPR_BOOKE_IVOR0 (0x190)
1838 #define SPR_BOOKE_IVOR1 (0x191)
1839 #define SPR_BOOKE_IVOR2 (0x192)
1840 #define SPR_BOOKE_IVOR3 (0x193)
1841 #define SPR_BOOKE_IVOR4 (0x194)
1842 #define SPR_BOOKE_IVOR5 (0x195)
1843 #define SPR_BOOKE_IVOR6 (0x196)
1844 #define SPR_BOOKE_IVOR7 (0x197)
1845 #define SPR_BOOKE_IVOR8 (0x198)
1846 #define SPR_BOOKE_IVOR9 (0x199)
1847 #define SPR_BOOKE_IVOR10 (0x19A)
1848 #define SPR_BOOKE_IVOR11 (0x19B)
1849 #define SPR_BOOKE_IVOR12 (0x19C)
1850 #define SPR_BOOKE_IVOR13 (0x19D)
1851 #define SPR_BOOKE_IVOR14 (0x19E)
1852 #define SPR_BOOKE_IVOR15 (0x19F)
1853 #define SPR_BOOKE_IVOR38 (0x1B0)
1854 #define SPR_BOOKE_IVOR39 (0x1B1)
1855 #define SPR_BOOKE_IVOR40 (0x1B2)
1856 #define SPR_BOOKE_IVOR41 (0x1B3)
1857 #define SPR_BOOKE_IVOR42 (0x1B4)
1858 #define SPR_BOOKE_GIVOR2 (0x1B8)
1859 #define SPR_BOOKE_GIVOR3 (0x1B9)
1860 #define SPR_BOOKE_GIVOR4 (0x1BA)
1861 #define SPR_BOOKE_GIVOR8 (0x1BB)
1862 #define SPR_BOOKE_GIVOR13 (0x1BC)
1863 #define SPR_BOOKE_GIVOR14 (0x1BD)
1864 #define SPR_TIR (0x1BE)
1865 #define SPR_UHDEXCR (0x1C7)
1866 #define SPR_PTCR (0x1D0)
1867 #define SPR_HASHKEYR (0x1D4)
1868 #define SPR_HASHPKEYR (0x1D5)
1869 #define SPR_HDEXCR (0x1D7)
1870 #define SPR_BOOKE_SPEFSCR (0x200)
1871 #define SPR_Exxx_BBEAR (0x201)
1872 #define SPR_Exxx_BBTAR (0x202)
1873 #define SPR_Exxx_L1CFG0 (0x203)
1874 #define SPR_Exxx_L1CFG1 (0x204)
1875 #define SPR_Exxx_NPIDR (0x205)
1876 #define SPR_ATBL (0x20E)
1877 #define SPR_ATBU (0x20F)
1878 #define SPR_IBAT0U (0x210)
1879 #define SPR_BOOKE_IVOR32 (0x210)
1880 #define SPR_RCPU_MI_GRA (0x210)
1881 #define SPR_IBAT0L (0x211)
1882 #define SPR_BOOKE_IVOR33 (0x211)
1883 #define SPR_IBAT1U (0x212)
1884 #define SPR_BOOKE_IVOR34 (0x212)
1885 #define SPR_IBAT1L (0x213)
1886 #define SPR_BOOKE_IVOR35 (0x213)
1887 #define SPR_IBAT2U (0x214)
1888 #define SPR_BOOKE_IVOR36 (0x214)
1889 #define SPR_IBAT2L (0x215)
1890 #define SPR_BOOKE_IVOR37 (0x215)
1891 #define SPR_IBAT3U (0x216)
1892 #define SPR_IBAT3L (0x217)
1893 #define SPR_DBAT0U (0x218)
1894 #define SPR_RCPU_L2U_GRA (0x218)
1895 #define SPR_DBAT0L (0x219)
1896 #define SPR_DBAT1U (0x21A)
1897 #define SPR_DBAT1L (0x21B)
1898 #define SPR_DBAT2U (0x21C)
1899 #define SPR_DBAT2L (0x21D)
1900 #define SPR_DBAT3U (0x21E)
1901 #define SPR_DBAT3L (0x21F)
1902 #define SPR_IBAT4U (0x230)
1903 #define SPR_RPCU_BBCMCR (0x230)
1904 #define SPR_MPC_IC_CST (0x230)
1905 #define SPR_Exxx_CTXCR (0x230)
1906 #define SPR_IBAT4L (0x231)
1907 #define SPR_MPC_IC_ADR (0x231)
1908 #define SPR_Exxx_DBCR3 (0x231)
1909 #define SPR_IBAT5U (0x232)
1910 #define SPR_MPC_IC_DAT (0x232)
1911 #define SPR_Exxx_DBCNT (0x232)
1912 #define SPR_IBAT5L (0x233)
1913 #define SPR_IBAT6U (0x234)
1914 #define SPR_IBAT6L (0x235)
1915 #define SPR_IBAT7U (0x236)
1916 #define SPR_IBAT7L (0x237)
1917 #define SPR_DBAT4U (0x238)
1918 #define SPR_RCPU_L2U_MCR (0x238)
1919 #define SPR_MPC_DC_CST (0x238)
1920 #define SPR_Exxx_ALTCTXCR (0x238)
1921 #define SPR_DBAT4L (0x239)
1922 #define SPR_MPC_DC_ADR (0x239)
1923 #define SPR_DBAT5U (0x23A)
1924 #define SPR_BOOKE_MCSRR0 (0x23A)
1925 #define SPR_MPC_DC_DAT (0x23A)
1926 #define SPR_DBAT5L (0x23B)
1927 #define SPR_BOOKE_MCSRR1 (0x23B)
1928 #define SPR_DBAT6U (0x23C)
1929 #define SPR_BOOKE_MCSR (0x23C)
1930 #define SPR_DBAT6L (0x23D)
1931 #define SPR_Exxx_MCAR (0x23D)
1932 #define SPR_DBAT7U (0x23E)
1933 #define SPR_BOOKE_DSRR0 (0x23E)
1934 #define SPR_DBAT7L (0x23F)
1935 #define SPR_BOOKE_DSRR1 (0x23F)
1936 #define SPR_BOOKE_SPRG8 (0x25C)
1937 #define SPR_BOOKE_SPRG9 (0x25D)
1938 #define SPR_BOOKE_MAS0 (0x270)
1939 #define SPR_BOOKE_MAS1 (0x271)
1940 #define SPR_BOOKE_MAS2 (0x272)
1941 #define SPR_BOOKE_MAS3 (0x273)
1942 #define SPR_BOOKE_MAS4 (0x274)
1943 #define SPR_BOOKE_MAS5 (0x275)
1944 #define SPR_BOOKE_MAS6 (0x276)
1945 #define SPR_BOOKE_PID1 (0x279)
1946 #define SPR_BOOKE_PID2 (0x27A)
1947 #define SPR_MPC_DPDR (0x280)
1948 #define SPR_MPC_IMMR (0x288)
1949 #define SPR_BOOKE_TLB0CFG (0x2B0)
1950 #define SPR_BOOKE_TLB1CFG (0x2B1)
1951 #define SPR_BOOKE_TLB2CFG (0x2B2)
1952 #define SPR_BOOKE_TLB3CFG (0x2B3)
1953 #define SPR_BOOKE_EPR (0x2BE)
1954 #define SPR_POWER_USIER2 (0x2E0)
1955 #define SPR_POWER_USIER3 (0x2E1)
1956 #define SPR_POWER_UMMCR3 (0x2E2)
1957 #define SPR_POWER_SIER2 (0x2F0)
1958 #define SPR_POWER_SIER3 (0x2F1)
1959 #define SPR_POWER_MMCR3 (0x2F2)
1960 #define SPR_PERF0 (0x300)
1961 #define SPR_RCPU_MI_RBA0 (0x300)
1962 #define SPR_MPC_MI_CTR (0x300)
1963 #define SPR_POWER_USIER (0x300)
1964 #define SPR_PERF1 (0x301)
1965 #define SPR_RCPU_MI_RBA1 (0x301)
1966 #define SPR_POWER_UMMCR2 (0x301)
1967 #define SPR_PERF2 (0x302)
1968 #define SPR_RCPU_MI_RBA2 (0x302)
1969 #define SPR_MPC_MI_AP (0x302)
1970 #define SPR_POWER_UMMCRA (0x302)
1971 #define SPR_PERF3 (0x303)
1972 #define SPR_RCPU_MI_RBA3 (0x303)
1973 #define SPR_MPC_MI_EPN (0x303)
1974 #define SPR_POWER_UPMC1 (0x303)
1975 #define SPR_PERF4 (0x304)
1976 #define SPR_POWER_UPMC2 (0x304)
1977 #define SPR_PERF5 (0x305)
1978 #define SPR_MPC_MI_TWC (0x305)
1979 #define SPR_POWER_UPMC3 (0x305)
1980 #define SPR_PERF6 (0x306)
1981 #define SPR_MPC_MI_RPN (0x306)
1982 #define SPR_POWER_UPMC4 (0x306)
1983 #define SPR_PERF7 (0x307)
1984 #define SPR_POWER_UPMC5 (0x307)
1985 #define SPR_PERF8 (0x308)
1986 #define SPR_RCPU_L2U_RBA0 (0x308)
1987 #define SPR_MPC_MD_CTR (0x308)
1988 #define SPR_POWER_UPMC6 (0x308)
1989 #define SPR_PERF9 (0x309)
1990 #define SPR_RCPU_L2U_RBA1 (0x309)
1991 #define SPR_MPC_MD_CASID (0x309)
1992 #define SPR_970_UPMC7 (0X309)
1993 #define SPR_PERFA (0x30A)
1994 #define SPR_RCPU_L2U_RBA2 (0x30A)
1995 #define SPR_MPC_MD_AP (0x30A)
1996 #define SPR_970_UPMC8 (0X30A)
1997 #define SPR_PERFB (0x30B)
1998 #define SPR_RCPU_L2U_RBA3 (0x30B)
1999 #define SPR_MPC_MD_EPN (0x30B)
2000 #define SPR_POWER_UMMCR0 (0X30B)
2001 #define SPR_PERFC (0x30C)
2002 #define SPR_MPC_MD_TWB (0x30C)
2003 #define SPR_POWER_USIAR (0X30C)
2004 #define SPR_PERFD (0x30D)
2005 #define SPR_MPC_MD_TWC (0x30D)
2006 #define SPR_POWER_USDAR (0X30D)
2007 #define SPR_PERFE (0x30E)
2008 #define SPR_MPC_MD_RPN (0x30E)
2009 #define SPR_POWER_UMMCR1 (0X30E)
2010 #define SPR_PERFF (0x30F)
2011 #define SPR_MPC_MD_TW (0x30F)
2012 #define SPR_UPERF0 (0x310)
2013 #define SPR_POWER_SIER (0x310)
2014 #define SPR_UPERF1 (0x311)
2015 #define SPR_POWER_MMCR2 (0x311)
2016 #define SPR_UPERF2 (0x312)
2017 #define SPR_POWER_MMCRA (0X312)
2018 #define SPR_UPERF3 (0x313)
2019 #define SPR_POWER_PMC1 (0X313)
2020 #define SPR_UPERF4 (0x314)
2021 #define SPR_POWER_PMC2 (0X314)
2022 #define SPR_UPERF5 (0x315)
2023 #define SPR_POWER_PMC3 (0X315)
2024 #define SPR_UPERF6 (0x316)
2025 #define SPR_POWER_PMC4 (0X316)
2026 #define SPR_UPERF7 (0x317)
2027 #define SPR_POWER_PMC5 (0X317)
2028 #define SPR_UPERF8 (0x318)
2029 #define SPR_POWER_PMC6 (0X318)
2030 #define SPR_UPERF9 (0x319)
2031 #define SPR_970_PMC7 (0X319)
2032 #define SPR_UPERFA (0x31A)
2033 #define SPR_970_PMC8 (0X31A)
2034 #define SPR_UPERFB (0x31B)
2035 #define SPR_POWER_MMCR0 (0X31B)
2036 #define SPR_UPERFC (0x31C)
2037 #define SPR_POWER_SIAR (0X31C)
2038 #define SPR_UPERFD (0x31D)
2039 #define SPR_POWER_SDAR (0X31D)
2040 #define SPR_UPERFE (0x31E)
2041 #define SPR_POWER_MMCR1 (0X31E)
2042 #define SPR_UPERFF (0x31F)
2043 #define SPR_RCPU_MI_RA0 (0x320)
2044 #define SPR_MPC_MI_DBCAM (0x320)
2045 #define SPR_BESCRS (0x320)
2046 #define SPR_RCPU_MI_RA1 (0x321)
2047 #define SPR_MPC_MI_DBRAM0 (0x321)
2048 #define SPR_BESCRSU (0x321)
2049 #define SPR_RCPU_MI_RA2 (0x322)
2050 #define SPR_MPC_MI_DBRAM1 (0x322)
2051 #define SPR_BESCRR (0x322)
2052 #define SPR_RCPU_MI_RA3 (0x323)
2053 #define SPR_BESCRRU (0x323)
2054 #define SPR_EBBHR (0x324)
2055 #define SPR_EBBRR (0x325)
2056 #define SPR_BESCR (0x326)
2057 #define SPR_RCPU_L2U_RA0 (0x328)
2058 #define SPR_MPC_MD_DBCAM (0x328)
2059 #define SPR_RCPU_L2U_RA1 (0x329)
2060 #define SPR_MPC_MD_DBRAM0 (0x329)
2061 #define SPR_RCPU_L2U_RA2 (0x32A)
2062 #define SPR_MPC_MD_DBRAM1 (0x32A)
2063 #define SPR_RCPU_L2U_RA3 (0x32B)
2064 #define SPR_UDEXCR (0x32C)
2065 #define SPR_TAR (0x32F)
2066 #define SPR_ASDR (0x330)
2067 #define SPR_DEXCR (0x33C)
2068 #define SPR_IC (0x350)
2069 #define SPR_VTB (0x351)
2070 #define SPR_MMCRC (0x353)
2071 #define SPR_PSSCR (0x357)
2072 #define SPR_440_INV0 (0x370)
2073 #define SPR_440_INV1 (0x371)
2074 #define SPR_TRIG1 (0x371)
2075 #define SPR_440_INV2 (0x372)
2076 #define SPR_TRIG2 (0x372)
2077 #define SPR_440_INV3 (0x373)
2078 #define SPR_440_ITV0 (0x374)
2079 #define SPR_440_ITV1 (0x375)
2080 #define SPR_440_ITV2 (0x376)
2081 #define SPR_440_ITV3 (0x377)
2082 #define SPR_440_CCR1 (0x378)
2083 #define SPR_TACR (0x378)
2084 #define SPR_TCSCR (0x379)
2085 #define SPR_CSIGR (0x37a)
2086 #define SPR_DCRIPR (0x37B)
2087 #define SPR_POWER_SPMC1 (0x37C)
2088 #define SPR_POWER_SPMC2 (0x37D)
2089 #define SPR_POWER_MMCRS (0x37E)
2090 #define SPR_WORT (0x37F)
2091 #define SPR_PPR (0x380)
2092 #define SPR_750_GQR0 (0x390)
2093 #define SPR_440_DNV0 (0x390)
2094 #define SPR_750_GQR1 (0x391)
2095 #define SPR_440_DNV1 (0x391)
2096 #define SPR_750_GQR2 (0x392)
2097 #define SPR_440_DNV2 (0x392)
2098 #define SPR_750_GQR3 (0x393)
2099 #define SPR_440_DNV3 (0x393)
2100 #define SPR_750_GQR4 (0x394)
2101 #define SPR_440_DTV0 (0x394)
2102 #define SPR_750_GQR5 (0x395)
2103 #define SPR_440_DTV1 (0x395)
2104 #define SPR_750_GQR6 (0x396)
2105 #define SPR_440_DTV2 (0x396)
2106 #define SPR_750_GQR7 (0x397)
2107 #define SPR_440_DTV3 (0x397)
2108 #define SPR_750_THRM4 (0x398)
2109 #define SPR_750CL_HID2 (0x398)
2110 #define SPR_440_DVLIM (0x398)
2111 #define SPR_750_WPAR (0x399)
2112 #define SPR_440_IVLIM (0x399)
2113 #define SPR_TSCR (0x399)
2114 #define SPR_750_DMAU (0x39A)
2115 #define SPR_750_DMAL (0x39B)
2116 #define SPR_440_RSTCFG (0x39B)
2117 #define SPR_BOOKE_DCDBTRL (0x39C)
2118 #define SPR_BOOKE_DCDBTRH (0x39D)
2119 #define SPR_BOOKE_ICDBTRL (0x39E)
2120 #define SPR_BOOKE_ICDBTRH (0x39F)
2121 #define SPR_74XX_UMMCR2 (0x3A0)
2122 #define SPR_7XX_UPMC5 (0x3A1)
2123 #define SPR_7XX_UPMC6 (0x3A2)
2124 #define SPR_UBAMR (0x3A7)
2125 #define SPR_7XX_UMMCR0 (0x3A8)
2126 #define SPR_7XX_UPMC1 (0x3A9)
2127 #define SPR_7XX_UPMC2 (0x3AA)
2128 #define SPR_7XX_USIAR (0x3AB)
2129 #define SPR_7XX_UMMCR1 (0x3AC)
2130 #define SPR_7XX_UPMC3 (0x3AD)
2131 #define SPR_7XX_UPMC4 (0x3AE)
2132 #define SPR_USDA (0x3AF)
2133 #define SPR_40x_ZPR (0x3B0)
2134 #define SPR_BOOKE_MAS7 (0x3B0)
2135 #define SPR_74XX_MMCR2 (0x3B0)
2136 #define SPR_7XX_PMC5 (0x3B1)
2137 #define SPR_40x_PID (0x3B1)
2138 #define SPR_7XX_PMC6 (0x3B2)
2139 #define SPR_440_MMUCR (0x3B2)
2140 #define SPR_4xx_CCR0 (0x3B3)
2141 #define SPR_BOOKE_EPLC (0x3B3)
2142 #define SPR_405_IAC3 (0x3B4)
2143 #define SPR_BOOKE_EPSC (0x3B4)
2144 #define SPR_405_IAC4 (0x3B5)
2145 #define SPR_405_DVC1 (0x3B6)
2146 #define SPR_405_DVC2 (0x3B7)
2147 #define SPR_BAMR (0x3B7)
2148 #define SPR_7XX_MMCR0 (0x3B8)
2149 #define SPR_7XX_PMC1 (0x3B9)
2150 #define SPR_40x_SGR (0x3B9)
2151 #define SPR_7XX_PMC2 (0x3BA)
2152 #define SPR_40x_DCWR (0x3BA)
2153 #define SPR_7XX_SIAR (0x3BB)
2154 #define SPR_405_SLER (0x3BB)
2155 #define SPR_7XX_MMCR1 (0x3BC)
2156 #define SPR_405_SU0R (0x3BC)
2157 #define SPR_401_SKR (0x3BC)
2158 #define SPR_7XX_PMC3 (0x3BD)
2159 #define SPR_405_DBCR1 (0x3BD)
2160 #define SPR_7XX_PMC4 (0x3BE)
2161 #define SPR_SDA (0x3BF)
2162 #define SPR_403_VTBL (0x3CC)
2163 #define SPR_403_VTBU (0x3CD)
2164 #define SPR_DMISS (0x3D0)
2165 #define SPR_DCMP (0x3D1)
2166 #define SPR_HASH1 (0x3D2)
2167 #define SPR_HASH2 (0x3D3)
2168 #define SPR_BOOKE_ICDBDR (0x3D3)
2169 #define SPR_TLBMISS (0x3D4)
2170 #define SPR_IMISS (0x3D4)
2171 #define SPR_40x_ESR (0x3D4)
2172 #define SPR_PTEHI (0x3D5)
2173 #define SPR_ICMP (0x3D5)
2174 #define SPR_40x_DEAR (0x3D5)
2175 #define SPR_PTELO (0x3D6)
2176 #define SPR_RPA (0x3D6)
2177 #define SPR_40x_EVPR (0x3D6)
2178 #define SPR_L3PM (0x3D7)
2179 #define SPR_403_CDBCR (0x3D7)
2180 #define SPR_L3ITCR0 (0x3D8)
2181 #define SPR_TCR (0x3D8)
2182 #define SPR_40x_TSR (0x3D8)
2183 #define SPR_IBR (0x3DA)
2184 #define SPR_40x_TCR (0x3DA)
2185 #define SPR_ESASRR (0x3DB)
2186 #define SPR_40x_PIT (0x3DB)
2187 #define SPR_403_TBL (0x3DC)
2188 #define SPR_403_TBU (0x3DD)
2189 #define SPR_SEBR (0x3DE)
2190 #define SPR_40x_SRR2 (0x3DE)
2191 #define SPR_SER (0x3DF)
2192 #define SPR_40x_SRR3 (0x3DF)
2193 #define SPR_L3OHCR (0x3E8)
2194 #define SPR_L3ITCR1 (0x3E9)
2195 #define SPR_L3ITCR2 (0x3EA)
2196 #define SPR_L3ITCR3 (0x3EB)
2197 #define SPR_HID0 (0x3F0)
2198 #define SPR_40x_DBSR (0x3F0)
2199 #define SPR_HID1 (0x3F1)
2200 #define SPR_IABR (0x3F2)
2201 #define SPR_40x_DBCR0 (0x3F2)
2202 #define SPR_Exxx_L1CSR0 (0x3F2)
2203 #define SPR_ICTRL (0x3F3)
2204 #define SPR_HID2 (0x3F3)
2205 #define SPR_750CL_HID4 (0x3F3)
2206 #define SPR_Exxx_L1CSR1 (0x3F3)
2207 #define SPR_440_DBDR (0x3F3)
2208 #define SPR_LDSTDB (0x3F4)
2209 #define SPR_750_TDCL (0x3F4)
2210 #define SPR_40x_IAC1 (0x3F4)
2211 #define SPR_MMUCSR0 (0x3F4)
2212 #define SPR_970_HID4 (0x3F4)
2213 #define SPR_DABR (0x3F5)
2214 #define DABR_MASK (~(target_ulong)0x7)
2215 #define SPR_Exxx_BUCSR (0x3F5)
2216 #define SPR_40x_IAC2 (0x3F5)
2217 #define SPR_40x_DAC1 (0x3F6)
2218 #define SPR_MSSCR0 (0x3F6)
2219 #define SPR_970_HID5 (0x3F6)
2220 #define SPR_MSSSR0 (0x3F7)
2221 #define SPR_MSSCR1 (0x3F7)
2222 #define SPR_DABRX (0x3F7)
2223 #define SPR_40x_DAC2 (0x3F7)
2224 #define SPR_MMUCFG (0x3F7)
2225 #define SPR_LDSTCR (0x3F8)
2226 #define SPR_L2PMCR (0x3F8)
2227 #define SPR_750FX_HID2 (0x3F8)
2228 #define SPR_Exxx_L1FINV0 (0x3F8)
2229 #define SPR_L2CR (0x3F9)
2230 #define SPR_Exxx_L2CSR0 (0x3F9)
2231 #define SPR_L3CR (0x3FA)
2232 #define SPR_750_TDCH (0x3FA)
2233 #define SPR_IABR2 (0x3FA)
2234 #define SPR_40x_DCCR (0x3FA)
2235 #define SPR_ICTC (0x3FB)
2236 #define SPR_40x_ICCR (0x3FB)
2237 #define SPR_THRM1 (0x3FC)
2238 #define SPR_403_PBL1 (0x3FC)
2239 #define SPR_SP (0x3FD)
2240 #define SPR_THRM2 (0x3FD)
2241 #define SPR_403_PBU1 (0x3FD)
2242 #define SPR_604_HID13 (0x3FD)
2243 #define SPR_LT (0x3FE)
2244 #define SPR_THRM3 (0x3FE)
2245 #define SPR_RCPU_FPECR (0x3FE)
2246 #define SPR_403_PBL2 (0x3FE)
2247 #define SPR_PIR (0x3FF)
2248 #define SPR_403_PBU2 (0x3FF)
2249 #define SPR_604_HID15 (0x3FF)
2250 #define SPR_E500_SVR (0x3FF)
2251
2252 /* Disable MAS Interrupt Updates for Hypervisor */
2253 #define EPCR_DMIUH (1 << 22)
2254 /* Disable Guest TLB Management Instructions */
2255 #define EPCR_DGTMI (1 << 23)
2256 /* Guest Interrupt Computation Mode */
2257 #define EPCR_GICM (1 << 24)
2258 /* Interrupt Computation Mode */
2259 #define EPCR_ICM (1 << 25)
2260 /* Disable Embedded Hypervisor Debug */
2261 #define EPCR_DUVD (1 << 26)
2262 /* Instruction Storage Interrupt Directed to Guest State */
2263 #define EPCR_ISIGS (1 << 27)
2264 /* Data Storage Interrupt Directed to Guest State */
2265 #define EPCR_DSIGS (1 << 28)
2266 /* Instruction TLB Error Interrupt Directed to Guest State */
2267 #define EPCR_ITLBGS (1 << 29)
2268 /* Data TLB Error Interrupt Directed to Guest State */
2269 #define EPCR_DTLBGS (1 << 30)
2270 /* External Input Interrupt Directed to Guest State */
2271 #define EPCR_EXTGS (1 << 31)
2272
2273 #define L1CSR0_CPE 0x00010000 /* Data Cache Parity Enable */
2274 #define L1CSR0_CUL 0x00000400 /* (D-)Cache Unable to Lock */
2275 #define L1CSR0_DCLFR 0x00000100 /* D-Cache Lock Flash Reset */
2276 #define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */
2277 #define L1CSR0_DCE 0x00000001 /* Data Cache Enable */
2278
2279 #define L1CSR1_CPE 0x00010000 /* Instruction Cache Parity Enable */
2280 #define L1CSR1_ICUL 0x00000400 /* I-Cache Unable to Lock */
2281 #define L1CSR1_ICLFR 0x00000100 /* I-Cache Lock Flash Reset */
2282 #define L1CSR1_ICFI 0x00000002 /* Instruction Cache Flash Invalidate */
2283 #define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */
2284
2285 /* E500 L2CSR0 */
2286 #define E500_L2CSR0_L2FI (1 << 21) /* L2 cache flash invalidate */
2287 #define E500_L2CSR0_L2FL (1 << 11) /* L2 cache flush */
2288 #define E500_L2CSR0_L2LFC (1 << 10) /* L2 cache lock flash clear */
2289
2290 /* HID0 bits */
2291 #define HID0_DEEPNAP (1 << 24) /* pre-2.06 */
2292 #define HID0_DOZE (1 << 23) /* pre-2.06 */
2293 #define HID0_NAP (1 << 22) /* pre-2.06 */
2294 #define HID0_HILE PPC_BIT(19) /* POWER8 */
2295 #define HID0_POWER9_HILE PPC_BIT(4)
2296
2297 /*****************************************************************************/
2298 /* PowerPC Instructions types definitions */
2299 enum {
2300 PPC_NONE = 0x0000000000000000ULL,
2301 /* PowerPC base instructions set */
2302 PPC_INSNS_BASE = 0x0000000000000001ULL,
2303 /* integer operations instructions */
2304 #define PPC_INTEGER PPC_INSNS_BASE
2305 /* flow control instructions */
2306 #define PPC_FLOW PPC_INSNS_BASE
2307 /* virtual memory instructions */
2308 #define PPC_MEM PPC_INSNS_BASE
2309 /* ld/st with reservation instructions */
2310 #define PPC_RES PPC_INSNS_BASE
2311 /* spr/msr access instructions */
2312 #define PPC_MISC PPC_INSNS_BASE
2313 /* 64 bits PowerPC instruction set */
2314 PPC_64B = 0x0000000000000020ULL,
2315 /* New 64 bits extensions (PowerPC 2.0x) */
2316 PPC_64BX = 0x0000000000000040ULL,
2317 /* 64 bits hypervisor extensions */
2318 PPC_64H = 0x0000000000000080ULL,
2319 /* New wait instruction (PowerPC 2.0x) */
2320 PPC_WAIT = 0x0000000000000100ULL,
2321 /* Time base mftb instruction */
2322 PPC_MFTB = 0x0000000000000200ULL,
2323
2324 /* Fixed-point unit extensions */
2325 /* isel instruction */
2326 PPC_ISEL = 0x0000000000000800ULL,
2327 /* popcntb instruction */
2328 PPC_POPCNTB = 0x0000000000001000ULL,
2329 /* string load / store */
2330 PPC_STRING = 0x0000000000002000ULL,
2331 /* real mode cache inhibited load / store */
2332 PPC_CILDST = 0x0000000000004000ULL,
2333
2334 /* Floating-point unit extensions */
2335 /* Optional floating point instructions */
2336 PPC_FLOAT = 0x0000000000010000ULL,
2337 /* New floating-point extensions (PowerPC 2.0x) */
2338 PPC_FLOAT_EXT = 0x0000000000020000ULL,
2339 PPC_FLOAT_FSQRT = 0x0000000000040000ULL,
2340 PPC_FLOAT_FRES = 0x0000000000080000ULL,
2341 PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL,
2342 PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
2343 PPC_FLOAT_FSEL = 0x0000000000400000ULL,
2344 PPC_FLOAT_STFIWX = 0x0000000000800000ULL,
2345
2346 /* Vector/SIMD extensions */
2347 /* Altivec support */
2348 PPC_ALTIVEC = 0x0000000001000000ULL,
2349 /* PowerPC 2.03 SPE extension */
2350 PPC_SPE = 0x0000000002000000ULL,
2351 /* PowerPC 2.03 SPE single-precision floating-point extension */
2352 PPC_SPE_SINGLE = 0x0000000004000000ULL,
2353 /* PowerPC 2.03 SPE double-precision floating-point extension */
2354 PPC_SPE_DOUBLE = 0x0000000008000000ULL,
2355
2356 /* Optional memory control instructions */
2357 PPC_MEM_TLBIA = 0x0000000010000000ULL,
2358 PPC_MEM_TLBIE = 0x0000000020000000ULL,
2359 PPC_MEM_TLBSYNC = 0x0000000040000000ULL,
2360 /* sync instruction */
2361 PPC_MEM_SYNC = 0x0000000080000000ULL,
2362 /* eieio instruction */
2363 PPC_MEM_EIEIO = 0x0000000100000000ULL,
2364
2365 /* Cache control instructions */
2366 PPC_CACHE = 0x0000000200000000ULL,
2367 /* icbi instruction */
2368 PPC_CACHE_ICBI = 0x0000000400000000ULL,
2369 /* dcbz instruction */
2370 PPC_CACHE_DCBZ = 0x0000000800000000ULL,
2371 /* dcba instruction */
2372 PPC_CACHE_DCBA = 0x0000002000000000ULL,
2373 /* Freescale cache locking instructions */
2374 PPC_CACHE_LOCK = 0x0000004000000000ULL,
2375
2376 /* MMU related extensions */
2377 /* external control instructions */
2378 PPC_EXTERN = 0x0000010000000000ULL,
2379 /* segment register access instructions */
2380 PPC_SEGMENT = 0x0000020000000000ULL,
2381 /* PowerPC 6xx TLB management instructions */
2382 PPC_6xx_TLB = 0x0000040000000000ULL,
2383 /* PowerPC 40x TLB management instructions */
2384 PPC_40x_TLB = 0x0000100000000000ULL,
2385 /* segment register access instructions for PowerPC 64 "bridge" */
2386 PPC_SEGMENT_64B = 0x0000200000000000ULL,
2387 /* SLB management */
2388 PPC_SLBI = 0x0000400000000000ULL,
2389
2390 /* Embedded PowerPC dedicated instructions */
2391 PPC_WRTEE = 0x0001000000000000ULL,
2392 /* PowerPC 40x exception model */
2393 PPC_40x_EXCP = 0x0002000000000000ULL,
2394 /* PowerPC 405 Mac instructions */
2395 PPC_405_MAC = 0x0004000000000000ULL,
2396 /* PowerPC 440 specific instructions */
2397 PPC_440_SPEC = 0x0008000000000000ULL,
2398 /* BookE (embedded) PowerPC specification */
2399 PPC_BOOKE = 0x0010000000000000ULL,
2400 /* mfapidi instruction */
2401 PPC_MFAPIDI = 0x0020000000000000ULL,
2402 /* tlbiva instruction */
2403 PPC_TLBIVA = 0x0040000000000000ULL,
2404 /* tlbivax instruction */
2405 PPC_TLBIVAX = 0x0080000000000000ULL,
2406 /* PowerPC 4xx dedicated instructions */
2407 PPC_4xx_COMMON = 0x0100000000000000ULL,
2408 /* PowerPC 40x ibct instructions */
2409 PPC_40x_ICBT = 0x0200000000000000ULL,
2410 /* rfmci is not implemented in all BookE PowerPC */
2411 PPC_RFMCI = 0x0400000000000000ULL,
2412 /* rfdi instruction */
2413 PPC_RFDI = 0x0800000000000000ULL,
2414 /* DCR accesses */
2415 PPC_DCR = 0x1000000000000000ULL,
2416 /* DCR extended accesse */
2417 PPC_DCRX = 0x2000000000000000ULL,
2418 /* popcntw and popcntd instructions */
2419 PPC_POPCNTWD = 0x8000000000000000ULL,
2420
2421 #define PPC_TCG_INSNS (PPC_INSNS_BASE | PPC_64B \
2422 | PPC_64BX | PPC_64H | PPC_WAIT | PPC_MFTB \
2423 | PPC_ISEL | PPC_POPCNTB \
2424 | PPC_STRING | PPC_FLOAT | PPC_FLOAT_EXT \
2425 | PPC_FLOAT_FSQRT | PPC_FLOAT_FRES \
2426 | PPC_FLOAT_FRSQRTE | PPC_FLOAT_FRSQRTES \
2427 | PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX \
2428 | PPC_ALTIVEC | PPC_SPE | PPC_SPE_SINGLE \
2429 | PPC_SPE_DOUBLE | PPC_MEM_TLBIA \
2430 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC \
2431 | PPC_MEM_SYNC | PPC_MEM_EIEIO \
2432 | PPC_CACHE | PPC_CACHE_ICBI \
2433 | PPC_CACHE_DCBZ \
2434 | PPC_CACHE_DCBA | PPC_CACHE_LOCK \
2435 | PPC_EXTERN | PPC_SEGMENT | PPC_6xx_TLB \
2436 | PPC_40x_TLB | PPC_SEGMENT_64B \
2437 | PPC_SLBI | PPC_WRTEE | PPC_40x_EXCP \
2438 | PPC_405_MAC | PPC_440_SPEC | PPC_BOOKE \
2439 | PPC_MFAPIDI | PPC_TLBIVA | PPC_TLBIVAX \
2440 | PPC_4xx_COMMON | PPC_40x_ICBT | PPC_RFMCI \
2441 | PPC_RFDI | PPC_DCR | PPC_DCRX | PPC_POPCNTWD \
2442 | PPC_CILDST)
2443
2444 /* extended type values */
2445
2446 /* BookE 2.06 PowerPC specification */
2447 PPC2_BOOKE206 = 0x0000000000000001ULL,
2448 /* VSX (extensions to Altivec / VMX) */
2449 PPC2_VSX = 0x0000000000000002ULL,
2450 /* Decimal Floating Point (DFP) */
2451 PPC2_DFP = 0x0000000000000004ULL,
2452 /* Embedded.Processor Control */
2453 PPC2_PRCNTL = 0x0000000000000008ULL,
2454 /* Byte-reversed, indexed, double-word load and store */
2455 PPC2_DBRX = 0x0000000000000010ULL,
2456 /* Book I 2.05 PowerPC specification */
2457 PPC2_ISA205 = 0x0000000000000020ULL,
2458 /* VSX additions in ISA 2.07 */
2459 PPC2_VSX207 = 0x0000000000000040ULL,
2460 /* ISA 2.06B bpermd */
2461 PPC2_PERM_ISA206 = 0x0000000000000080ULL,
2462 /* ISA 2.06B divide extended variants */
2463 PPC2_DIVE_ISA206 = 0x0000000000000100ULL,
2464 /* ISA 2.06B larx/stcx. instructions */
2465 PPC2_ATOMIC_ISA206 = 0x0000000000000200ULL,
2466 /* ISA 2.06B floating point integer conversion */
2467 PPC2_FP_CVT_ISA206 = 0x0000000000000400ULL,
2468 /* ISA 2.06B floating point test instructions */
2469 PPC2_FP_TST_ISA206 = 0x0000000000000800ULL,
2470 /* ISA 2.07 bctar instruction */
2471 PPC2_BCTAR_ISA207 = 0x0000000000001000ULL,
2472 /* ISA 2.07 load/store quadword */
2473 PPC2_LSQ_ISA207 = 0x0000000000002000ULL,
2474 /* ISA 2.07 Altivec */
2475 PPC2_ALTIVEC_207 = 0x0000000000004000ULL,
2476 /* PowerISA 2.07 Book3s specification */
2477 PPC2_ISA207S = 0x0000000000008000ULL,
2478 /* Double precision floating point conversion for signed integer 64 */
2479 PPC2_FP_CVT_S64 = 0x0000000000010000ULL,
2480 /* Transactional Memory (ISA 2.07, Book II) */
2481 PPC2_TM = 0x0000000000020000ULL,
2482 /* Server PM instructgions (ISA 2.06, Book III) */
2483 PPC2_PM_ISA206 = 0x0000000000040000ULL,
2484 /* POWER ISA 3.0 */
2485 PPC2_ISA300 = 0x0000000000080000ULL,
2486 /* POWER ISA 3.1 */
2487 PPC2_ISA310 = 0x0000000000100000ULL,
2488 /* lwsync instruction */
2489 PPC2_MEM_LWSYNC = 0x0000000000200000ULL,
2490 /* ISA 2.06 BCD assist instructions */
2491 PPC2_BCDA_ISA206 = 0x0000000000400000ULL,
2492
2493 #define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \
2494 PPC2_ISA205 | PPC2_VSX207 | PPC2_PERM_ISA206 | \
2495 PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \
2496 PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | \
2497 PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | \
2498 PPC2_ALTIVEC_207 | PPC2_ISA207S | PPC2_DFP | \
2499 PPC2_FP_CVT_S64 | PPC2_TM | PPC2_PM_ISA206 | \
2500 PPC2_ISA300 | PPC2_ISA310 | PPC2_MEM_LWSYNC | \
2501 PPC2_BCDA_ISA206)
2502 };
2503
2504 /*****************************************************************************/
2505 /*
2506 * Memory access type :
2507 * may be needed for precise access rights control and precise exceptions.
2508 */
2509 enum {
2510 /* Type of instruction that generated the access */
2511 ACCESS_CODE = 0x10, /* Code fetch access */
2512 ACCESS_INT = 0x20, /* Integer load/store access */
2513 ACCESS_FLOAT = 0x30, /* floating point load/store access */
2514 ACCESS_RES = 0x40, /* load/store with reservation */
2515 ACCESS_EXT = 0x50, /* external access */
2516 ACCESS_CACHE = 0x60, /* Cache manipulation */
2517 };
2518
2519 /*
2520 * Hardware interrupt sources:
2521 * all those exception can be raised simulteaneously
2522 */
2523 /* Input pins definitions */
2524 enum {
2525 /* 6xx bus input pins */
2526 PPC6xx_INPUT_HRESET = 0,
2527 PPC6xx_INPUT_SRESET = 1,
2528 PPC6xx_INPUT_CKSTP_IN = 2,
2529 PPC6xx_INPUT_MCP = 3,
2530 PPC6xx_INPUT_SMI = 4,
2531 PPC6xx_INPUT_INT = 5,
2532 PPC6xx_INPUT_TBEN = 6,
2533 PPC6xx_INPUT_WAKEUP = 7,
2534 PPC6xx_INPUT_NB,
2535 };
2536
2537 enum {
2538 /* Embedded PowerPC input pins */
2539 PPCBookE_INPUT_HRESET = 0,
2540 PPCBookE_INPUT_SRESET = 1,
2541 PPCBookE_INPUT_CKSTP_IN = 2,
2542 PPCBookE_INPUT_MCP = 3,
2543 PPCBookE_INPUT_SMI = 4,
2544 PPCBookE_INPUT_INT = 5,
2545 PPCBookE_INPUT_CINT = 6,
2546 PPCBookE_INPUT_NB,
2547 };
2548
2549 enum {
2550 /* PowerPC E500 input pins */
2551 PPCE500_INPUT_RESET_CORE = 0,
2552 PPCE500_INPUT_MCK = 1,
2553 PPCE500_INPUT_CINT = 3,
2554 PPCE500_INPUT_INT = 4,
2555 PPCE500_INPUT_DEBUG = 6,
2556 PPCE500_INPUT_NB,
2557 };
2558
2559 enum {
2560 /* PowerPC 40x input pins */
2561 PPC40x_INPUT_RESET_CORE = 0,
2562 PPC40x_INPUT_RESET_CHIP = 1,
2563 PPC40x_INPUT_RESET_SYS = 2,
2564 PPC40x_INPUT_CINT = 3,
2565 PPC40x_INPUT_INT = 4,
2566 PPC40x_INPUT_HALT = 5,
2567 PPC40x_INPUT_DEBUG = 6,
2568 PPC40x_INPUT_NB,
2569 };
2570
2571 enum {
2572 /* RCPU input pins */
2573 PPCRCPU_INPUT_PORESET = 0,
2574 PPCRCPU_INPUT_HRESET = 1,
2575 PPCRCPU_INPUT_SRESET = 2,
2576 PPCRCPU_INPUT_IRQ0 = 3,
2577 PPCRCPU_INPUT_IRQ1 = 4,
2578 PPCRCPU_INPUT_IRQ2 = 5,
2579 PPCRCPU_INPUT_IRQ3 = 6,
2580 PPCRCPU_INPUT_IRQ4 = 7,
2581 PPCRCPU_INPUT_IRQ5 = 8,
2582 PPCRCPU_INPUT_IRQ6 = 9,
2583 PPCRCPU_INPUT_IRQ7 = 10,
2584 PPCRCPU_INPUT_NB,
2585 };
2586
2587 #if defined(TARGET_PPC64)
2588 enum {
2589 /* PowerPC 970 input pins */
2590 PPC970_INPUT_HRESET = 0,
2591 PPC970_INPUT_SRESET = 1,
2592 PPC970_INPUT_CKSTP = 2,
2593 PPC970_INPUT_TBEN = 3,
2594 PPC970_INPUT_MCP = 4,
2595 PPC970_INPUT_INT = 5,
2596 PPC970_INPUT_THINT = 6,
2597 PPC970_INPUT_NB,
2598 };
2599
2600 enum {
2601 /* POWER7 input pins */
2602 POWER7_INPUT_INT = 0,
2603 /*
2604 * POWER7 probably has other inputs, but we don't care about them
2605 * for any existing machine. We can wire these up when we need
2606 * them
2607 */
2608 POWER7_INPUT_NB,
2609 };
2610
2611 enum {
2612 /* POWER9 input pins */
2613 POWER9_INPUT_INT = 0,
2614 POWER9_INPUT_HINT = 1,
2615 POWER9_INPUT_NB,
2616 };
2617 #endif
2618
2619 /* Hardware exceptions definitions */
2620 enum {
2621 /* External hardware exception sources */
2622 PPC_INTERRUPT_RESET = 0x00001, /* Reset exception */
2623 PPC_INTERRUPT_WAKEUP = 0x00002, /* Wakeup exception */
2624 PPC_INTERRUPT_MCK = 0x00004, /* Machine check exception */
2625 PPC_INTERRUPT_EXT = 0x00008, /* External interrupt */
2626 PPC_INTERRUPT_SMI = 0x00010, /* System management interrupt */
2627 PPC_INTERRUPT_CEXT = 0x00020, /* Critical external interrupt */
2628 PPC_INTERRUPT_DEBUG = 0x00040, /* External debug exception */
2629 PPC_INTERRUPT_THERM = 0x00080, /* Thermal exception */
2630 /* Internal hardware exception sources */
2631 PPC_INTERRUPT_DECR = 0x00100, /* Decrementer exception */
2632 PPC_INTERRUPT_HDECR = 0x00200, /* Hypervisor decrementer exception */
2633 PPC_INTERRUPT_PIT = 0x00400, /* Programmable interval timer int. */
2634 PPC_INTERRUPT_FIT = 0x00800, /* Fixed interval timer interrupt */
2635 PPC_INTERRUPT_WDT = 0x01000, /* Watchdog timer interrupt */
2636 PPC_INTERRUPT_CDOORBELL = 0x02000, /* Critical doorbell interrupt */
2637 PPC_INTERRUPT_DOORBELL = 0x04000, /* Doorbell interrupt */
2638 PPC_INTERRUPT_PERFM = 0x08000, /* Performance monitor interrupt */
2639 PPC_INTERRUPT_HMI = 0x10000, /* Hypervisor Maintenance interrupt */
2640 PPC_INTERRUPT_HDOORBELL = 0x20000, /* Hypervisor Doorbell interrupt */
2641 PPC_INTERRUPT_HVIRT = 0x40000, /* Hypervisor virtualization interrupt */
2642 PPC_INTERRUPT_EBB = 0x80000, /* Event-based Branch exception */
2643 };
2644
2645 /* Processor Compatibility mask (PCR) */
2646 enum {
2647 PCR_COMPAT_2_05 = PPC_BIT(62),
2648 PCR_COMPAT_2_06 = PPC_BIT(61),
2649 PCR_COMPAT_2_07 = PPC_BIT(60),
2650 PCR_COMPAT_3_00 = PPC_BIT(59),
2651 PCR_COMPAT_3_10 = PPC_BIT(58),
2652 PCR_VEC_DIS = PPC_BIT(0), /* Vec. disable (bit NA since POWER8) */
2653 PCR_VSX_DIS = PPC_BIT(1), /* VSX disable (bit NA since POWER8) */
2654 PCR_TM_DIS = PPC_BIT(2), /* Trans. memory disable (POWER8) */
2655 };
2656
2657 /* HMER/HMEER */
2658 enum {
2659 HMER_MALFUNCTION_ALERT = PPC_BIT(0),
2660 HMER_PROC_RECV_DONE = PPC_BIT(2),
2661 HMER_PROC_RECV_ERROR_MASKED = PPC_BIT(3),
2662 HMER_TFAC_ERROR = PPC_BIT(4),
2663 HMER_TFMR_PARITY_ERROR = PPC_BIT(5),
2664 HMER_XSCOM_FAIL = PPC_BIT(8),
2665 HMER_XSCOM_DONE = PPC_BIT(9),
2666 HMER_PROC_RECV_AGAIN = PPC_BIT(11),
2667 HMER_WARN_RISE = PPC_BIT(14),
2668 HMER_WARN_FALL = PPC_BIT(15),
2669 HMER_SCOM_FIR_HMI = PPC_BIT(16),
2670 HMER_TRIG_FIR_HMI = PPC_BIT(17),
2671 HMER_HYP_RESOURCE_ERR = PPC_BIT(20),
2672 HMER_XSCOM_STATUS_MASK = PPC_BITMASK(21, 23),
2673 };
2674
2675 /* TFMR */
2676 enum {
2677 TFMR_CONTROL_MASK = PPC_BITMASK(0, 24),
2678 TFMR_MASK_HMI = PPC_BIT(10),
2679 TFMR_TB_ECLIPZ = PPC_BIT(14),
2680 TFMR_LOAD_TOD_MOD = PPC_BIT(16),
2681 TFMR_MOVE_CHIP_TOD_TO_TB = PPC_BIT(18),
2682 TFMR_CLEAR_TB_ERRORS = PPC_BIT(24),
2683 TFMR_STATUS_MASK = PPC_BITMASK(25, 63),
2684 TFMR_TBST_ENCODED = PPC_BITMASK(28, 31), /* TBST = TB State */
2685 TFMR_TBST_LAST = PPC_BITMASK(32, 35), /* Previous TBST */
2686 TFMR_TB_ENABLED = PPC_BIT(40),
2687 TFMR_TB_VALID = PPC_BIT(41),
2688 TFMR_TB_SYNC_OCCURED = PPC_BIT(42),
2689 TFMR_FIRMWARE_CONTROL_ERROR = PPC_BIT(46),
2690 };
2691
2692 /* TFMR TBST (Time Base State Machine). */
2693 enum {
2694 TBST_RESET = 0x0,
2695 TBST_SEND_TOD_MOD = 0x1,
2696 TBST_NOT_SET = 0x2,
2697 TBST_SYNC_WAIT = 0x6,
2698 TBST_GET_TOD = 0x7,
2699 TBST_TB_RUNNING = 0x8,
2700 TBST_TB_ERROR = 0x9,
2701 };
2702
2703 /*****************************************************************************/
2704
2705 #define is_isa300(ctx) (!!(ctx->insns_flags2 & PPC2_ISA300))
2706 target_ulong cpu_read_xer(const CPUPPCState *env);
2707 void cpu_write_xer(CPUPPCState *env, target_ulong xer);
2708
2709 /*
2710 * All 64-bit server processors compliant with arch 2.x, ie. 970 and newer,
2711 * have PPC_SEGMENT_64B.
2712 */
2713 #define is_book3s_arch2x(ctx) (!!((ctx)->insns_flags & PPC_SEGMENT_64B))
2714
2715 #ifdef CONFIG_DEBUG_TCG
2716 void cpu_get_tb_cpu_state(CPUPPCState *env, vaddr *pc,
2717 uint64_t *cs_base, uint32_t *flags);
2718 #else
2719 static inline void cpu_get_tb_cpu_state(CPUPPCState *env, vaddr *pc,
2720 uint64_t *cs_base, uint32_t *flags)
2721 {
2722 *pc = env->nip;
2723 *cs_base = 0;
2724 *flags = env->hflags;
2725 }
2726 #endif
2727
2728 G_NORETURN void raise_exception(CPUPPCState *env, uint32_t exception);
2729 G_NORETURN void raise_exception_ra(CPUPPCState *env, uint32_t exception,
2730 uintptr_t raddr);
2731 G_NORETURN void raise_exception_err(CPUPPCState *env, uint32_t exception,
2732 uint32_t error_code);
2733 G_NORETURN void raise_exception_err_ra(CPUPPCState *env, uint32_t exception,
2734 uint32_t error_code, uintptr_t raddr);
2735
2736 /* PERFM EBB helper*/
2737 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
2738 void raise_ebb_perfm_exception(CPUPPCState *env);
2739 #endif
2740
2741 #if !defined(CONFIG_USER_ONLY)
2742 static inline int booke206_tlbm_id(CPUPPCState *env, ppcmas_tlb_t *tlbm)
2743 {
2744 uintptr_t tlbml = (uintptr_t)tlbm;
2745 uintptr_t tlbl = (uintptr_t)env->tlb.tlbm;
2746
2747 return (tlbml - tlbl) / sizeof(env->tlb.tlbm[0]);
2748 }
2749
2750 static inline int booke206_tlb_size(CPUPPCState *env, int tlbn)
2751 {
2752 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2753 int r = tlbncfg & TLBnCFG_N_ENTRY;
2754 return r;
2755 }
2756
2757 static inline int booke206_tlb_ways(CPUPPCState *env, int tlbn)
2758 {
2759 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2760 int r = tlbncfg >> TLBnCFG_ASSOC_SHIFT;
2761 return r;
2762 }
2763
2764 static inline int booke206_tlbm_to_tlbn(CPUPPCState *env, ppcmas_tlb_t *tlbm)
2765 {
2766 int id = booke206_tlbm_id(env, tlbm);
2767 int end = 0;
2768 int i;
2769
2770 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
2771 end += booke206_tlb_size(env, i);
2772 if (id < end) {
2773 return i;
2774 }
2775 }
2776
2777 cpu_abort(env_cpu(env), "Unknown TLBe: %d\n", id);
2778 return 0;
2779 }
2780
2781 static inline int booke206_tlbm_to_way(CPUPPCState *env, ppcmas_tlb_t *tlb)
2782 {
2783 int tlbn = booke206_tlbm_to_tlbn(env, tlb);
2784 int tlbid = booke206_tlbm_id(env, tlb);
2785 return tlbid & (booke206_tlb_ways(env, tlbn) - 1);
2786 }
2787
2788 static inline ppcmas_tlb_t *booke206_get_tlbm(CPUPPCState *env, const int tlbn,
2789 target_ulong ea, int way)
2790 {
2791 int r;
2792 uint32_t ways = booke206_tlb_ways(env, tlbn);
2793 int ways_bits = ctz32(ways);
2794 int tlb_bits = ctz32(booke206_tlb_size(env, tlbn));
2795 int i;
2796
2797 way &= ways - 1;
2798 ea >>= MAS2_EPN_SHIFT;
2799 ea &= (1 << (tlb_bits - ways_bits)) - 1;
2800 r = (ea << ways_bits) | way;
2801
2802 if (r >= booke206_tlb_size(env, tlbn)) {
2803 return NULL;
2804 }
2805
2806 /* bump up to tlbn index */
2807 for (i = 0; i < tlbn; i++) {
2808 r += booke206_tlb_size(env, i);
2809 }
2810
2811 return &env->tlb.tlbm[r];
2812 }
2813
2814 /* returns bitmap of supported page sizes for a given TLB */
2815 static inline uint32_t booke206_tlbnps(CPUPPCState *env, const int tlbn)
2816 {
2817 uint32_t ret = 0;
2818
2819 if ((env->spr[SPR_MMUCFG] & MMUCFG_MAVN) == MMUCFG_MAVN_V2) {
2820 /* MAV2 */
2821 ret = env->spr[SPR_BOOKE_TLB0PS + tlbn];
2822 } else {
2823 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2824 uint32_t min = (tlbncfg & TLBnCFG_MINSIZE) >> TLBnCFG_MINSIZE_SHIFT;
2825 uint32_t max = (tlbncfg & TLBnCFG_MAXSIZE) >> TLBnCFG_MAXSIZE_SHIFT;
2826 int i;
2827 for (i = min; i <= max; i++) {
2828 ret |= (1 << (i << 1));
2829 }
2830 }
2831
2832 return ret;
2833 }
2834
2835 static inline void booke206_fixed_size_tlbn(CPUPPCState *env, const int tlbn,
2836 ppcmas_tlb_t *tlb)
2837 {
2838 uint8_t i;
2839 int32_t tsize = -1;
2840
2841 for (i = 0; i < 32; i++) {
2842 if ((env->spr[SPR_BOOKE_TLB0PS + tlbn]) & (1ULL << i)) {
2843 if (tsize == -1) {
2844 tsize = i;
2845 } else {
2846 return;
2847 }
2848 }
2849 }
2850
2851 /* TLBnPS unimplemented? Odd.. */
2852 assert(tsize != -1);
2853 tlb->mas1 &= ~MAS1_TSIZE_MASK;
2854 tlb->mas1 |= ((uint32_t)tsize) << MAS1_TSIZE_SHIFT;
2855 }
2856
2857 #endif
2858
2859 static inline bool msr_is_64bit(CPUPPCState *env, target_ulong msr)
2860 {
2861 if (env->mmu_model == POWERPC_MMU_BOOKE206) {
2862 return msr & (1ULL << MSR_CM);
2863 }
2864
2865 return msr & (1ULL << MSR_SF);
2866 }
2867
2868 /**
2869 * Check whether register rx is in the range between start and
2870 * start + nregs (as needed by the LSWX and LSWI instructions)
2871 */
2872 static inline bool lsw_reg_in_range(int start, int nregs, int rx)
2873 {
2874 return (start + nregs <= 32 && rx >= start && rx < start + nregs) ||
2875 (start + nregs > 32 && (rx >= start || rx < start + nregs - 32));
2876 }
2877
2878 /* Accessors for FP, VMX and VSX registers */
2879 #if HOST_BIG_ENDIAN
2880 #define VsrB(i) u8[i]
2881 #define VsrSB(i) s8[i]
2882 #define VsrH(i) u16[i]
2883 #define VsrSH(i) s16[i]
2884 #define VsrW(i) u32[i]
2885 #define VsrSW(i) s32[i]
2886 #define VsrD(i) u64[i]
2887 #define VsrSD(i) s64[i]
2888 #define VsrHF(i) f16[i]
2889 #define VsrSF(i) f32[i]
2890 #define VsrDF(i) f64[i]
2891 #else
2892 #define VsrB(i) u8[15 - (i)]
2893 #define VsrSB(i) s8[15 - (i)]
2894 #define VsrH(i) u16[7 - (i)]
2895 #define VsrSH(i) s16[7 - (i)]
2896 #define VsrW(i) u32[3 - (i)]
2897 #define VsrSW(i) s32[3 - (i)]
2898 #define VsrD(i) u64[1 - (i)]
2899 #define VsrSD(i) s64[1 - (i)]
2900 #define VsrHF(i) f16[7 - (i)]
2901 #define VsrSF(i) f32[3 - (i)]
2902 #define VsrDF(i) f64[1 - (i)]
2903 #endif
2904
2905 static inline int vsr64_offset(int i, bool high)
2906 {
2907 return offsetof(CPUPPCState, vsr[i].VsrD(high ? 0 : 1));
2908 }
2909
2910 static inline int vsr_full_offset(int i)
2911 {
2912 return offsetof(CPUPPCState, vsr[i].u64[0]);
2913 }
2914
2915 static inline int acc_full_offset(int i)
2916 {
2917 return vsr_full_offset(i * 4);
2918 }
2919
2920 static inline int fpr_offset(int i)
2921 {
2922 return vsr64_offset(i, true);
2923 }
2924
2925 static inline uint64_t *cpu_fpr_ptr(CPUPPCState *env, int i)
2926 {
2927 return (uint64_t *)((uintptr_t)env + fpr_offset(i));
2928 }
2929
2930 static inline uint64_t *cpu_vsrl_ptr(CPUPPCState *env, int i)
2931 {
2932 return (uint64_t *)((uintptr_t)env + vsr64_offset(i, false));
2933 }
2934
2935 static inline long avr64_offset(int i, bool high)
2936 {
2937 return vsr64_offset(i + 32, high);
2938 }
2939
2940 static inline int avr_full_offset(int i)
2941 {
2942 return vsr_full_offset(i + 32);
2943 }
2944
2945 static inline ppc_avr_t *cpu_avr_ptr(CPUPPCState *env, int i)
2946 {
2947 return (ppc_avr_t *)((uintptr_t)env + avr_full_offset(i));
2948 }
2949
2950 static inline bool ppc_has_spr(PowerPCCPU *cpu, int spr)
2951 {
2952 /* We can test whether the SPR is defined by checking for a valid name */
2953 return cpu->env.spr_cb[spr].name != NULL;
2954 }
2955
2956 #if !defined(CONFIG_USER_ONLY)
2957 /* Sort out endianness of interrupt. Depends on the CPU, HV mode, etc. */
2958 static inline bool ppc_interrupts_little_endian(PowerPCCPU *cpu, bool hv)
2959 {
2960 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
2961 CPUPPCState *env = &cpu->env;
2962 bool ile;
2963
2964 if (hv && env->has_hv_mode) {
2965 if (is_isa300(pcc)) {
2966 ile = !!(env->spr[SPR_HID0] & HID0_POWER9_HILE);
2967 } else {
2968 ile = !!(env->spr[SPR_HID0] & HID0_HILE);
2969 }
2970
2971 } else if (pcc->lpcr_mask & LPCR_ILE) {
2972 ile = !!(env->spr[SPR_LPCR] & LPCR_ILE);
2973 } else {
2974 ile = FIELD_EX64(env->msr, MSR, ILE);
2975 }
2976
2977 return ile;
2978 }
2979 #endif
2980
2981 void dump_mmu(CPUPPCState *env);
2982
2983 void ppc_maybe_bswap_register(CPUPPCState *env, uint8_t *mem_buf, int len);
2984 void ppc_store_vscr(CPUPPCState *env, uint32_t vscr);
2985 uint32_t ppc_get_vscr(CPUPPCState *env);
2986 void ppc_set_cr(CPUPPCState *env, uint64_t cr);
2987 uint64_t ppc_get_cr(const CPUPPCState *env);
2988
2989 /*****************************************************************************/
2990 /* Power management enable checks */
2991 static inline int check_pow_none(CPUPPCState *env)
2992 {
2993 return 0;
2994 }
2995
2996 static inline int check_pow_nocheck(CPUPPCState *env)
2997 {
2998 return 1;
2999 }
3000
3001 /*****************************************************************************/
3002 /* PowerPC implementations definitions */
3003
3004 #define POWERPC_FAMILY(_name) \
3005 static void \
3006 glue(glue(ppc_, _name), _cpu_family_class_init)(ObjectClass *, void *); \
3007 \
3008 static const TypeInfo \
3009 glue(glue(ppc_, _name), _cpu_family_type_info) = { \
3010 .name = stringify(_name) "-family-" TYPE_POWERPC_CPU, \
3011 .parent = TYPE_POWERPC_CPU, \
3012 .abstract = true, \
3013 .class_init = glue(glue(ppc_, _name), _cpu_family_class_init), \
3014 }; \
3015 \
3016 static void glue(glue(ppc_, _name), _cpu_family_register_types)(void) \
3017 { \
3018 type_register_static( \
3019 &glue(glue(ppc_, _name), _cpu_family_type_info)); \
3020 } \
3021 \
3022 type_init(glue(glue(ppc_, _name), _cpu_family_register_types)) \
3023 \
3024 static void glue(glue(ppc_, _name), _cpu_family_class_init)
3025
3026
3027 #endif /* PPC_CPU_H */
armbru's QEMU hackery