| blob | 19010af03bb06624a9cbcab21caa7bc20dcedca7 |
1 # AArch64 A64 allowed instruction decoding
2 #
3 # Copyright (c) 2023 Linaro, Ltd
4 #
5 # This library is free software; you can redistribute it and/or
6 # modify it under the terms of the GNU Lesser General Public
7 # License as published by the Free Software Foundation; either
8 # version 2.1 of the License, or (at your option) any later version.
9 #
10 # This library is distributed in the hope that it will be useful,
11 # but WITHOUT ANY WARRANTY; without even the implied warranty of
12 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 # Lesser General Public License for more details.
14 #
15 # You should have received a copy of the GNU Lesser General Public
16 # License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 #
19 # This file is processed by scripts/decodetree.py
20 #
22 %rd 0:5
23 %esz_sd 22:1 !function=plus_2
24 %esz_hsd 22:2 !function=xor_2
25 %hl 11:1 21:1
26 %hlm 11:1 20:2
28 &r rn
29 &ri rd imm
30 &rri_sf rd rn imm sf
31 &i imm
32 &rr_e rd rn esz
33 &rrr_e rd rn rm esz
34 &rrx_e rd rn rm idx esz
35 &qrr_e q rd rn esz
36 &qrrr_e q rd rn rm esz
37 &qrrx_e q rd rn rm idx esz
38 &qrrrr_e q rd rn rm ra esz
40 @rr_h ........ ... ..... ...... rn:5 rd:5 &rr_e esz=1
41 @rr_d ........ ... ..... ...... rn:5 rd:5 &rr_e esz=3
42 @rr_sd ........ ... ..... ...... rn:5 rd:5 &rr_e esz=%esz_sd
44 @rrr_h ........ ... rm:5 ...... rn:5 rd:5 &rrr_e esz=1
45 @rrr_sd ........ ... rm:5 ...... rn:5 rd:5 &rrr_e esz=%esz_sd
46 @rrr_hsd ........ ... rm:5 ...... rn:5 rd:5 &rrr_e esz=%esz_hsd
47 @rrr_e ........ esz:2 . rm:5 ...... rn:5 rd:5 &rrr_e
49 @rrx_h ........ .. .. rm:4 .... . . rn:5 rd:5 &rrx_e esz=1 idx=%hlm
50 @rrx_s ........ .. . rm:5 .... . . rn:5 rd:5 &rrx_e esz=2 idx=%hl
51 @rrx_d ........ .. . rm:5 .... idx:1 . rn:5 rd:5 &rrx_e esz=3
53 @rr_q1e0 ........ ........ ...... rn:5 rd:5 &qrr_e q=1 esz=0
54 @r2r_q1e0 ........ ........ ...... rm:5 rd:5 &qrrr_e rn=%rd q=1 esz=0
55 @rrr_q1e0 ........ ... rm:5 ...... rn:5 rd:5 &qrrr_e q=1 esz=0
56 @rrr_q1e3 ........ ... rm:5 ...... rn:5 rd:5 &qrrr_e q=1 esz=3
57 @rrrr_q1e3 ........ ... rm:5 . ra:5 rn:5 rd:5 &qrrrr_e q=1 esz=3
59 @qrrr_b . q:1 ...... ... rm:5 ...... rn:5 rd:5 &qrrr_e esz=0
60 @qrrr_h . q:1 ...... ... rm:5 ...... rn:5 rd:5 &qrrr_e esz=1
61 @qrrr_sd . q:1 ...... ... rm:5 ...... rn:5 rd:5 &qrrr_e esz=%esz_sd
62 @qrrr_e . q:1 ...... esz:2 . rm:5 ...... rn:5 rd:5 &qrrr_e
64 @qrrx_h . q:1 .. .... .. .. rm:4 .... . . rn:5 rd:5 \
65 &qrrx_e esz=1 idx=%hlm
66 @qrrx_s . q:1 .. .... .. . rm:5 .... . . rn:5 rd:5 \
67 &qrrx_e esz=2 idx=%hl
68 @qrrx_d . q:1 .. .... .. . rm:5 .... idx:1 . rn:5 rd:5 \
69 &qrrx_e esz=3
71 ### Data Processing - Immediate
73 # PC-rel addressing
75 %imm_pcrel 5:s19 29:2
76 @pcrel . .. ..... ................... rd:5 &ri imm=%imm_pcrel
78 ADR 0 .. 10000 ................... ..... @pcrel
79 ADRP 1 .. 10000 ................... ..... @pcrel
81 # Add/subtract (immediate)
83 %imm12_sh12 10:12 !function=shl_12
84 @addsub_imm sf:1 .. ...... . imm:12 rn:5 rd:5
85 @addsub_imm12 sf:1 .. ...... . ............ rn:5 rd:5 imm=%imm12_sh12
87 ADD_i . 00 100010 0 ............ ..... ..... @addsub_imm
88 ADD_i . 00 100010 1 ............ ..... ..... @addsub_imm12
89 ADDS_i . 01 100010 0 ............ ..... ..... @addsub_imm
90 ADDS_i . 01 100010 1 ............ ..... ..... @addsub_imm12
92 SUB_i . 10 100010 0 ............ ..... ..... @addsub_imm
93 SUB_i . 10 100010 1 ............ ..... ..... @addsub_imm12
94 SUBS_i . 11 100010 0 ............ ..... ..... @addsub_imm
95 SUBS_i . 11 100010 1 ............ ..... ..... @addsub_imm12
97 # Add/subtract (immediate with tags)
99 &rri_tag rd rn uimm6 uimm4
100 @addsub_imm_tag . .. ...... . uimm6:6 .. uimm4:4 rn:5 rd:5 &rri_tag
102 ADDG_i 1 00 100011 0 ...... 00 .... ..... ..... @addsub_imm_tag
103 SUBG_i 1 10 100011 0 ...... 00 .... ..... ..... @addsub_imm_tag
105 # Logical (immediate)
107 &rri_log rd rn sf dbm
108 @logic_imm_64 1 .. ...... dbm:13 rn:5 rd:5 &rri_log sf=1
109 @logic_imm_32 0 .. ...... 0 dbm:12 rn:5 rd:5 &rri_log sf=0
111 AND_i . 00 100100 . ...... ...... ..... ..... @logic_imm_64
112 AND_i . 00 100100 . ...... ...... ..... ..... @logic_imm_32
113 ORR_i . 01 100100 . ...... ...... ..... ..... @logic_imm_64
114 ORR_i . 01 100100 . ...... ...... ..... ..... @logic_imm_32
115 EOR_i . 10 100100 . ...... ...... ..... ..... @logic_imm_64
116 EOR_i . 10 100100 . ...... ...... ..... ..... @logic_imm_32
117 ANDS_i . 11 100100 . ...... ...... ..... ..... @logic_imm_64
118 ANDS_i . 11 100100 . ...... ...... ..... ..... @logic_imm_32
120 # Move wide (immediate)
122 &movw rd sf imm hw
123 @movw_64 1 .. ...... hw:2 imm:16 rd:5 &movw sf=1
124 @movw_32 0 .. ...... 0 hw:1 imm:16 rd:5 &movw sf=0
126 MOVN . 00 100101 .. ................ ..... @movw_64
127 MOVN . 00 100101 .. ................ ..... @movw_32
128 MOVZ . 10 100101 .. ................ ..... @movw_64
129 MOVZ . 10 100101 .. ................ ..... @movw_32
130 MOVK . 11 100101 .. ................ ..... @movw_64
131 MOVK . 11 100101 .. ................ ..... @movw_32
133 # Bitfield
135 &bitfield rd rn sf immr imms
136 @bitfield_64 1 .. ...... 1 immr:6 imms:6 rn:5 rd:5 &bitfield sf=1
137 @bitfield_32 0 .. ...... 0 0 immr:5 0 imms:5 rn:5 rd:5 &bitfield sf=0
139 SBFM . 00 100110 . ...... ...... ..... ..... @bitfield_64
140 SBFM . 00 100110 . ...... ...... ..... ..... @bitfield_32
141 BFM . 01 100110 . ...... ...... ..... ..... @bitfield_64
142 BFM . 01 100110 . ...... ...... ..... ..... @bitfield_32
143 UBFM . 10 100110 . ...... ...... ..... ..... @bitfield_64
144 UBFM . 10 100110 . ...... ...... ..... ..... @bitfield_32
146 # Extract
148 &extract rd rn rm imm sf
150 EXTR 1 00 100111 1 0 rm:5 imm:6 rn:5 rd:5 &extract sf=1
151 EXTR 0 00 100111 0 0 rm:5 0 imm:5 rn:5 rd:5 &extract sf=0
153 # Branches
155 %imm26 0:s26 !function=times_4
156 @branch . ..... .......................... &i imm=%imm26
158 B 0 00101 .......................... @branch
159 BL 1 00101 .......................... @branch
161 %imm19 5:s19 !function=times_4
162 &cbz rt imm sf nz
164 CBZ sf:1 011010 nz:1 ................... rt:5 &cbz imm=%imm19
166 %imm14 5:s14 !function=times_4
167 %imm31_19 31:1 19:5
168 &tbz rt imm nz bitpos
170 TBZ . 011011 nz:1 ..... .............. rt:5 &tbz imm=%imm14 bitpos=%imm31_19
172 # B.cond and BC.cond
173 B_cond 0101010 0 ................... c:1 cond:4 imm=%imm19
175 BR 1101011 0000 11111 000000 rn:5 00000 &r
176 BLR 1101011 0001 11111 000000 rn:5 00000 &r
177 RET 1101011 0010 11111 000000 rn:5 00000 &r
179 &braz rn m
180 BRAZ 1101011 0000 11111 00001 m:1 rn:5 11111 &braz # BRAAZ, BRABZ
181 BLRAZ 1101011 0001 11111 00001 m:1 rn:5 11111 &braz # BLRAAZ, BLRABZ
183 &reta m
184 RETA 1101011 0010 11111 00001 m:1 11111 11111 &reta # RETAA, RETAB
186 &bra rn rm m
187 BRA 1101011 1000 11111 00001 m:1 rn:5 rm:5 &bra # BRAA, BRAB
188 BLRA 1101011 1001 11111 00001 m:1 rn:5 rm:5 &bra # BLRAA, BLRAB
190 ERET 1101011 0100 11111 000000 11111 00000
191 ERETA 1101011 0100 11111 00001 m:1 11111 11111 &reta # ERETAA, ERETAB
193 # We don't need to decode DRPS because it always UNDEFs except when
194 # the processor is in halting debug state (which we don't implement).
195 # The pattern is listed here as documentation.
196 # DRPS 1101011 0101 11111 000000 11111 00000
198 # Hint instruction group
199 {
200 [
201 YIELD 1101 0101 0000 0011 0010 0000 001 11111
202 WFE 1101 0101 0000 0011 0010 0000 010 11111
203 WFI 1101 0101 0000 0011 0010 0000 011 11111
204 # We implement WFE to never block, so our SEV/SEVL are NOPs
205 # SEV 1101 0101 0000 0011 0010 0000 100 11111
206 # SEVL 1101 0101 0000 0011 0010 0000 101 11111
207 # Our DGL is a NOP because we don't merge memory accesses anyway.
208 # DGL 1101 0101 0000 0011 0010 0000 110 11111
209 XPACLRI 1101 0101 0000 0011 0010 0000 111 11111
210 PACIA1716 1101 0101 0000 0011 0010 0001 000 11111
211 PACIB1716 1101 0101 0000 0011 0010 0001 010 11111
212 AUTIA1716 1101 0101 0000 0011 0010 0001 100 11111
213 AUTIB1716 1101 0101 0000 0011 0010 0001 110 11111
214 ESB 1101 0101 0000 0011 0010 0010 000 11111
215 PACIAZ 1101 0101 0000 0011 0010 0011 000 11111
216 PACIASP 1101 0101 0000 0011 0010 0011 001 11111
217 PACIBZ 1101 0101 0000 0011 0010 0011 010 11111
218 PACIBSP 1101 0101 0000 0011 0010 0011 011 11111
219 AUTIAZ 1101 0101 0000 0011 0010 0011 100 11111
220 AUTIASP 1101 0101 0000 0011 0010 0011 101 11111
221 AUTIBZ 1101 0101 0000 0011 0010 0011 110 11111
222 AUTIBSP 1101 0101 0000 0011 0010 0011 111 11111
223 ]
224 # The canonical NOP has CRm == op2 == 0, but all of the space
225 # that isn't specifically allocated to an instruction must NOP
226 NOP 1101 0101 0000 0011 0010 ---- --- 11111
227 }
229 # Barriers
231 CLREX 1101 0101 0000 0011 0011 ---- 010 11111
232 DSB_DMB 1101 0101 0000 0011 0011 domain:2 types:2 10- 11111
233 ISB 1101 0101 0000 0011 0011 ---- 110 11111
234 SB 1101 0101 0000 0011 0011 0000 111 11111
236 # PSTATE
238 CFINV 1101 0101 0000 0 000 0100 0000 000 11111
239 XAFLAG 1101 0101 0000 0 000 0100 0000 001 11111
240 AXFLAG 1101 0101 0000 0 000 0100 0000 010 11111
242 # These are architecturally all "MSR (immediate)"; we decode the destination
243 # register too because there is no commonality in our implementation.
244 @msr_i .... .... .... . ... .... imm:4 ... .....
245 MSR_i_UAO 1101 0101 0000 0 000 0100 .... 011 11111 @msr_i
246 MSR_i_PAN 1101 0101 0000 0 000 0100 .... 100 11111 @msr_i
247 MSR_i_SPSEL 1101 0101 0000 0 000 0100 .... 101 11111 @msr_i
248 MSR_i_SBSS 1101 0101 0000 0 011 0100 .... 001 11111 @msr_i
249 MSR_i_DIT 1101 0101 0000 0 011 0100 .... 010 11111 @msr_i
250 MSR_i_TCO 1101 0101 0000 0 011 0100 .... 100 11111 @msr_i
251 MSR_i_DAIFSET 1101 0101 0000 0 011 0100 .... 110 11111 @msr_i
252 MSR_i_DAIFCLEAR 1101 0101 0000 0 011 0100 .... 111 11111 @msr_i
253 MSR_i_ALLINT 1101 0101 0000 0 001 0100 000 imm:1 000 11111
254 MSR_i_SVCR 1101 0101 0000 0 011 0100 0 mask:2 imm:1 011 11111
256 # MRS, MSR (register), SYS, SYSL. These are all essentially the
257 # same instruction as far as QEMU is concerned.
258 # NB: op0 is bits [20:19], but op0=0b00 is other insns, so we have
259 # to hand-decode it.
260 SYS 1101 0101 00 l:1 01 op1:3 crn:4 crm:4 op2:3 rt:5 op0=1
261 SYS 1101 0101 00 l:1 10 op1:3 crn:4 crm:4 op2:3 rt:5 op0=2
262 SYS 1101 0101 00 l:1 11 op1:3 crn:4 crm:4 op2:3 rt:5 op0=3
264 # Exception generation
266 @i16 .... .... ... imm:16 ... .. &i
267 SVC 1101 0100 000 ................ 000 01 @i16
268 HVC 1101 0100 000 ................ 000 10 @i16
269 SMC 1101 0100 000 ................ 000 11 @i16
270 BRK 1101 0100 001 ................ 000 00 @i16
271 HLT 1101 0100 010 ................ 000 00 @i16
272 # These insns always UNDEF unless in halting debug state, which
273 # we don't implement. So we don't need to decode them. The patterns
274 # are listed here as documentation.
275 # DCPS1 1101 0100 101 ................ 000 01 @i16
276 # DCPS2 1101 0100 101 ................ 000 10 @i16
277 # DCPS3 1101 0100 101 ................ 000 11 @i16
279 # Loads and stores
281 &stxr rn rt rt2 rs sz lasr
282 &stlr rn rt sz lasr
283 @stxr sz:2 ...... ... rs:5 lasr:1 rt2:5 rn:5 rt:5 &stxr
284 @stlr sz:2 ...... ... ..... lasr:1 ..... rn:5 rt:5 &stlr
285 %imm1_30_p2 30:1 !function=plus_2
286 @stxp .. ...... ... rs:5 lasr:1 rt2:5 rn:5 rt:5 &stxr sz=%imm1_30_p2
287 STXR .. 001000 000 ..... . ..... ..... ..... @stxr # inc STLXR
288 LDXR .. 001000 010 ..... . ..... ..... ..... @stxr # inc LDAXR
289 STLR .. 001000 100 11111 . 11111 ..... ..... @stlr # inc STLLR
290 LDAR .. 001000 110 11111 . 11111 ..... ..... @stlr # inc LDLAR
292 STXP 1 . 001000 001 ..... . ..... ..... ..... @stxp # inc STLXP
293 LDXP 1 . 001000 011 ..... . ..... ..... ..... @stxp # inc LDAXP
295 # CASP, CASPA, CASPAL, CASPL (we don't decode the bits that determine
296 # acquire/release semantics because QEMU's cmpxchg always has those)
297 CASP 0 . 001000 0 - 1 rs:5 - 11111 rn:5 rt:5 sz=%imm1_30_p2
298 # CAS, CASA, CASAL, CASL
299 CAS sz:2 001000 1 - 1 rs:5 - 11111 rn:5 rt:5
301 &ldlit rt imm sz sign
302 @ldlit .. ... . .. ................... rt:5 &ldlit imm=%imm19
304 LD_lit 00 011 0 00 ................... ..... @ldlit sz=2 sign=0
305 LD_lit 01 011 0 00 ................... ..... @ldlit sz=3 sign=0
306 LD_lit 10 011 0 00 ................... ..... @ldlit sz=2 sign=1
307 LD_lit_v 00 011 1 00 ................... ..... @ldlit sz=2 sign=0
308 LD_lit_v 01 011 1 00 ................... ..... @ldlit sz=3 sign=0
309 LD_lit_v 10 011 1 00 ................... ..... @ldlit sz=4 sign=0
311 # PRFM
312 NOP 11 011 0 00 ------------------- -----
314 &ldstpair rt2 rt rn imm sz sign w p
315 @ldstpair .. ... . ... . imm:s7 rt2:5 rn:5 rt:5 &ldstpair
317 # STNP, LDNP: Signed offset, non-temporal hint. We don't emulate caches
318 # so we ignore hints about data access patterns, and handle these like
319 # plain signed offset.
320 STP 00 101 0 000 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0
321 LDP 00 101 0 000 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0
322 STP 10 101 0 000 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0
323 LDP 10 101 0 000 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0
324 STP_v 00 101 1 000 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0
325 LDP_v 00 101 1 000 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0
326 STP_v 01 101 1 000 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0
327 LDP_v 01 101 1 000 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0
328 STP_v 10 101 1 000 0 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=0
329 LDP_v 10 101 1 000 1 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=0
331 # STP and LDP: post-indexed
332 STP 00 101 0 001 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=1 w=1
333 LDP 00 101 0 001 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=1 w=1
334 LDP 01 101 0 001 1 ....... ..... ..... ..... @ldstpair sz=2 sign=1 p=1 w=1
335 STP 10 101 0 001 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=1 w=1
336 LDP 10 101 0 001 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=1 w=1
337 STP_v 00 101 1 001 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=1 w=1
338 LDP_v 00 101 1 001 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=1 w=1
339 STP_v 01 101 1 001 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=1 w=1
340 LDP_v 01 101 1 001 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=1 w=1
341 STP_v 10 101 1 001 0 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=1 w=1
342 LDP_v 10 101 1 001 1 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=1 w=1
344 # STP and LDP: offset
345 STP 00 101 0 010 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0
346 LDP 00 101 0 010 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0
347 LDP 01 101 0 010 1 ....... ..... ..... ..... @ldstpair sz=2 sign=1 p=0 w=0
348 STP 10 101 0 010 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0
349 LDP 10 101 0 010 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0
350 STP_v 00 101 1 010 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0
351 LDP_v 00 101 1 010 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0
352 STP_v 01 101 1 010 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0
353 LDP_v 01 101 1 010 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0
354 STP_v 10 101 1 010 0 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=0
355 LDP_v 10 101 1 010 1 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=0
357 # STP and LDP: pre-indexed
358 STP 00 101 0 011 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=1
359 LDP 00 101 0 011 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=1
360 LDP 01 101 0 011 1 ....... ..... ..... ..... @ldstpair sz=2 sign=1 p=0 w=1
361 STP 10 101 0 011 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=1
362 LDP 10 101 0 011 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=1
363 STP_v 00 101 1 011 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=1
364 LDP_v 00 101 1 011 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=1
365 STP_v 01 101 1 011 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=1
366 LDP_v 01 101 1 011 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=1
367 STP_v 10 101 1 011 0 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=1
368 LDP_v 10 101 1 011 1 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=1
370 # STGP: store tag and pair
371 STGP 01 101 0 001 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=1 w=1
372 STGP 01 101 0 010 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0
373 STGP 01 101 0 011 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=1
375 # Load/store register (unscaled immediate)
376 &ldst_imm rt rn imm sz sign w p unpriv ext
377 @ldst_imm .. ... . .. .. . imm:s9 .. rn:5 rt:5 &ldst_imm unpriv=0 p=0 w=0
378 @ldst_imm_pre .. ... . .. .. . imm:s9 .. rn:5 rt:5 &ldst_imm unpriv=0 p=0 w=1
379 @ldst_imm_post .. ... . .. .. . imm:s9 .. rn:5 rt:5 &ldst_imm unpriv=0 p=1 w=1
380 @ldst_imm_user .. ... . .. .. . imm:s9 .. rn:5 rt:5 &ldst_imm unpriv=1 p=0 w=0
382 STR_i sz:2 111 0 00 00 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0
383 LDR_i 00 111 0 00 01 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=1 sz=0
384 LDR_i 01 111 0 00 01 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=1 sz=1
385 LDR_i 10 111 0 00 01 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=1 sz=2
386 LDR_i 11 111 0 00 01 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0 sz=3
387 LDR_i 00 111 0 00 10 0 ......... 00 ..... ..... @ldst_imm sign=1 ext=0 sz=0
388 LDR_i 01 111 0 00 10 0 ......... 00 ..... ..... @ldst_imm sign=1 ext=0 sz=1
389 LDR_i 10 111 0 00 10 0 ......... 00 ..... ..... @ldst_imm sign=1 ext=0 sz=2
390 LDR_i 00 111 0 00 11 0 ......... 00 ..... ..... @ldst_imm sign=1 ext=1 sz=0
391 LDR_i 01 111 0 00 11 0 ......... 00 ..... ..... @ldst_imm sign=1 ext=1 sz=1
393 STR_i sz:2 111 0 00 00 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0
394 LDR_i 00 111 0 00 01 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=1 sz=0
395 LDR_i 01 111 0 00 01 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=1 sz=1
396 LDR_i 10 111 0 00 01 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=1 sz=2
397 LDR_i 11 111 0 00 01 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0 sz=3
398 LDR_i 00 111 0 00 10 0 ......... 01 ..... ..... @ldst_imm_post sign=1 ext=0 sz=0
399 LDR_i 01 111 0 00 10 0 ......... 01 ..... ..... @ldst_imm_post sign=1 ext=0 sz=1
400 LDR_i 10 111 0 00 10 0 ......... 01 ..... ..... @ldst_imm_post sign=1 ext=0 sz=2
401 LDR_i 00 111 0 00 11 0 ......... 01 ..... ..... @ldst_imm_post sign=1 ext=1 sz=0
402 LDR_i 01 111 0 00 11 0 ......... 01 ..... ..... @ldst_imm_post sign=1 ext=1 sz=1
404 STR_i sz:2 111 0 00 00 0 ......... 10 ..... ..... @ldst_imm_user sign=0 ext=0
405 LDR_i 00 111 0 00 01 0 ......... 10 ..... ..... @ldst_imm_user sign=0 ext=1 sz=0
406 LDR_i 01 111 0 00 01 0 ......... 10 ..... ..... @ldst_imm_user sign=0 ext=1 sz=1
407 LDR_i 10 111 0 00 01 0 ......... 10 ..... ..... @ldst_imm_user sign=0 ext=1 sz=2
408 LDR_i 11 111 0 00 01 0 ......... 10 ..... ..... @ldst_imm_user sign=0 ext=0 sz=3
409 LDR_i 00 111 0 00 10 0 ......... 10 ..... ..... @ldst_imm_user sign=1 ext=0 sz=0
410 LDR_i 01 111 0 00 10 0 ......... 10 ..... ..... @ldst_imm_user sign=1 ext=0 sz=1
411 LDR_i 10 111 0 00 10 0 ......... 10 ..... ..... @ldst_imm_user sign=1 ext=0 sz=2
412 LDR_i 00 111 0 00 11 0 ......... 10 ..... ..... @ldst_imm_user sign=1 ext=1 sz=0
413 LDR_i 01 111 0 00 11 0 ......... 10 ..... ..... @ldst_imm_user sign=1 ext=1 sz=1
415 STR_i sz:2 111 0 00 00 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0
416 LDR_i 00 111 0 00 01 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=1 sz=0
417 LDR_i 01 111 0 00 01 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=1 sz=1
418 LDR_i 10 111 0 00 01 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=1 sz=2
419 LDR_i 11 111 0 00 01 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0 sz=3
420 LDR_i 00 111 0 00 10 0 ......... 11 ..... ..... @ldst_imm_pre sign=1 ext=0 sz=0
421 LDR_i 01 111 0 00 10 0 ......... 11 ..... ..... @ldst_imm_pre sign=1 ext=0 sz=1
422 LDR_i 10 111 0 00 10 0 ......... 11 ..... ..... @ldst_imm_pre sign=1 ext=0 sz=2
423 LDR_i 00 111 0 00 11 0 ......... 11 ..... ..... @ldst_imm_pre sign=1 ext=1 sz=0
424 LDR_i 01 111 0 00 11 0 ......... 11 ..... ..... @ldst_imm_pre sign=1 ext=1 sz=1
426 # PRFM : prefetch memory: a no-op for QEMU
427 NOP 11 111 0 00 10 0 --------- 00 ----- -----
429 STR_v_i sz:2 111 1 00 00 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0
430 STR_v_i 00 111 1 00 10 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0 sz=4
431 LDR_v_i sz:2 111 1 00 01 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0
432 LDR_v_i 00 111 1 00 11 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0 sz=4
434 STR_v_i sz:2 111 1 00 00 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0
435 STR_v_i 00 111 1 00 10 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0 sz=4
436 LDR_v_i sz:2 111 1 00 01 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0
437 LDR_v_i 00 111 1 00 11 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0 sz=4
439 STR_v_i sz:2 111 1 00 00 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0
440 STR_v_i 00 111 1 00 10 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0 sz=4
441 LDR_v_i sz:2 111 1 00 01 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0
442 LDR_v_i 00 111 1 00 11 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0 sz=4
444 # Load/store with an unsigned 12 bit immediate, which is scaled by the
445 # element size. The function gets the sz:imm and returns the scaled immediate.
446 %uimm_scaled 10:12 sz:3 !function=uimm_scaled
448 @ldst_uimm .. ... . .. .. ............ rn:5 rt:5 &ldst_imm unpriv=0 p=0 w=0 imm=%uimm_scaled
450 STR_i sz:2 111 0 01 00 ............ ..... ..... @ldst_uimm sign=0 ext=0
451 LDR_i 00 111 0 01 01 ............ ..... ..... @ldst_uimm sign=0 ext=1 sz=0
452 LDR_i 01 111 0 01 01 ............ ..... ..... @ldst_uimm sign=0 ext=1 sz=1
453 LDR_i 10 111 0 01 01 ............ ..... ..... @ldst_uimm sign=0 ext=1 sz=2
454 LDR_i 11 111 0 01 01 ............ ..... ..... @ldst_uimm sign=0 ext=0 sz=3
455 LDR_i 00 111 0 01 10 ............ ..... ..... @ldst_uimm sign=1 ext=0 sz=0
456 LDR_i 01 111 0 01 10 ............ ..... ..... @ldst_uimm sign=1 ext=0 sz=1
457 LDR_i 10 111 0 01 10 ............ ..... ..... @ldst_uimm sign=1 ext=0 sz=2
458 LDR_i 00 111 0 01 11 ............ ..... ..... @ldst_uimm sign=1 ext=1 sz=0
459 LDR_i 01 111 0 01 11 ............ ..... ..... @ldst_uimm sign=1 ext=1 sz=1
461 # PRFM
462 NOP 11 111 0 01 10 ------------ ----- -----
464 STR_v_i sz:2 111 1 01 00 ............ ..... ..... @ldst_uimm sign=0 ext=0
465 STR_v_i 00 111 1 01 10 ............ ..... ..... @ldst_uimm sign=0 ext=0 sz=4
466 LDR_v_i sz:2 111 1 01 01 ............ ..... ..... @ldst_uimm sign=0 ext=0
467 LDR_v_i 00 111 1 01 11 ............ ..... ..... @ldst_uimm sign=0 ext=0 sz=4
469 # Load/store with register offset
470 &ldst rm rn rt sign ext sz opt s
471 @ldst .. ... . .. .. . rm:5 opt:3 s:1 .. rn:5 rt:5 &ldst
472 STR sz:2 111 0 00 00 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0
473 LDR 00 111 0 00 01 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=1 sz=0
474 LDR 01 111 0 00 01 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=1 sz=1
475 LDR 10 111 0 00 01 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=1 sz=2
476 LDR 11 111 0 00 01 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 sz=3
477 LDR 00 111 0 00 10 1 ..... ... . 10 ..... ..... @ldst sign=1 ext=0 sz=0
478 LDR 01 111 0 00 10 1 ..... ... . 10 ..... ..... @ldst sign=1 ext=0 sz=1
479 LDR 10 111 0 00 10 1 ..... ... . 10 ..... ..... @ldst sign=1 ext=0 sz=2
480 LDR 00 111 0 00 11 1 ..... ... . 10 ..... ..... @ldst sign=1 ext=1 sz=0
481 LDR 01 111 0 00 11 1 ..... ... . 10 ..... ..... @ldst sign=1 ext=1 sz=1
483 # PRFM
484 NOP 11 111 0 00 10 1 ----- -1- - 10 ----- -----
486 STR_v sz:2 111 1 00 00 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0
487 STR_v 00 111 1 00 10 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 sz=4
488 LDR_v sz:2 111 1 00 01 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0
489 LDR_v 00 111 1 00 11 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 sz=4
491 # Atomic memory operations
492 &atomic rs rn rt a r sz
493 @atomic sz:2 ... . .. a:1 r:1 . rs:5 . ... .. rn:5 rt:5 &atomic
494 LDADD .. 111 0 00 . . 1 ..... 0000 00 ..... ..... @atomic
495 LDCLR .. 111 0 00 . . 1 ..... 0001 00 ..... ..... @atomic
496 LDEOR .. 111 0 00 . . 1 ..... 0010 00 ..... ..... @atomic
497 LDSET .. 111 0 00 . . 1 ..... 0011 00 ..... ..... @atomic
498 LDSMAX .. 111 0 00 . . 1 ..... 0100 00 ..... ..... @atomic
499 LDSMIN .. 111 0 00 . . 1 ..... 0101 00 ..... ..... @atomic
500 LDUMAX .. 111 0 00 . . 1 ..... 0110 00 ..... ..... @atomic
501 LDUMIN .. 111 0 00 . . 1 ..... 0111 00 ..... ..... @atomic
502 SWP .. 111 0 00 . . 1 ..... 1000 00 ..... ..... @atomic
504 LDAPR sz:2 111 0 00 1 0 1 11111 1100 00 rn:5 rt:5
506 # Load/store register (pointer authentication)
508 # LDRA immediate is 10 bits signed and scaled, but the bits aren't all contiguous
509 %ldra_imm 22:s1 12:9 !function=times_8
511 LDRA 11 111 0 00 m:1 . 1 ......... w:1 1 rn:5 rt:5 imm=%ldra_imm
513 &ldapr_stlr_i rn rt imm sz sign ext
514 @ldapr_stlr_i .. ...... .. . imm:9 .. rn:5 rt:5 &ldapr_stlr_i
515 STLR_i sz:2 011001 00 0 ......... 00 ..... ..... @ldapr_stlr_i sign=0 ext=0
516 LDAPR_i sz:2 011001 01 0 ......... 00 ..... ..... @ldapr_stlr_i sign=0 ext=0
517 LDAPR_i 00 011001 10 0 ......... 00 ..... ..... @ldapr_stlr_i sign=1 ext=0 sz=0
518 LDAPR_i 01 011001 10 0 ......... 00 ..... ..... @ldapr_stlr_i sign=1 ext=0 sz=1
519 LDAPR_i 10 011001 10 0 ......... 00 ..... ..... @ldapr_stlr_i sign=1 ext=0 sz=2
520 LDAPR_i 00 011001 11 0 ......... 00 ..... ..... @ldapr_stlr_i sign=1 ext=1 sz=0
521 LDAPR_i 01 011001 11 0 ......... 00 ..... ..... @ldapr_stlr_i sign=1 ext=1 sz=1
523 # Load/store multiple structures
524 # The 4-bit opcode in [15:12] encodes repeat count and structure elements
525 &ldst_mult rm rn rt sz q p rpt selem
526 @ldst_mult . q:1 ...... p:1 . . rm:5 .... sz:2 rn:5 rt:5 &ldst_mult
527 ST_mult 0 . 001100 . 0 0 ..... 0000 .. ..... ..... @ldst_mult rpt=1 selem=4
528 ST_mult 0 . 001100 . 0 0 ..... 0010 .. ..... ..... @ldst_mult rpt=4 selem=1
529 ST_mult 0 . 001100 . 0 0 ..... 0100 .. ..... ..... @ldst_mult rpt=1 selem=3
530 ST_mult 0 . 001100 . 0 0 ..... 0110 .. ..... ..... @ldst_mult rpt=3 selem=1
531 ST_mult 0 . 001100 . 0 0 ..... 0111 .. ..... ..... @ldst_mult rpt=1 selem=1
532 ST_mult 0 . 001100 . 0 0 ..... 1000 .. ..... ..... @ldst_mult rpt=1 selem=2
533 ST_mult 0 . 001100 . 0 0 ..... 1010 .. ..... ..... @ldst_mult rpt=2 selem=1
535 LD_mult 0 . 001100 . 1 0 ..... 0000 .. ..... ..... @ldst_mult rpt=1 selem=4
536 LD_mult 0 . 001100 . 1 0 ..... 0010 .. ..... ..... @ldst_mult rpt=4 selem=1
537 LD_mult 0 . 001100 . 1 0 ..... 0100 .. ..... ..... @ldst_mult rpt=1 selem=3
538 LD_mult 0 . 001100 . 1 0 ..... 0110 .. ..... ..... @ldst_mult rpt=3 selem=1
539 LD_mult 0 . 001100 . 1 0 ..... 0111 .. ..... ..... @ldst_mult rpt=1 selem=1
540 LD_mult 0 . 001100 . 1 0 ..... 1000 .. ..... ..... @ldst_mult rpt=1 selem=2
541 LD_mult 0 . 001100 . 1 0 ..... 1010 .. ..... ..... @ldst_mult rpt=2 selem=1
543 # Load/store single structure
544 &ldst_single rm rn rt p selem index scale
546 %ldst_single_selem 13:1 21:1 !function=plus_1
548 %ldst_single_index_b 30:1 10:3
549 %ldst_single_index_h 30:1 11:2
550 %ldst_single_index_s 30:1 12:1
552 @ldst_single_b .. ...... p:1 .. rm:5 ...... rn:5 rt:5 \
553 &ldst_single scale=0 selem=%ldst_single_selem \
554 index=%ldst_single_index_b
555 @ldst_single_h .. ...... p:1 .. rm:5 ...... rn:5 rt:5 \
556 &ldst_single scale=1 selem=%ldst_single_selem \
557 index=%ldst_single_index_h
558 @ldst_single_s .. ...... p:1 .. rm:5 ...... rn:5 rt:5 \
559 &ldst_single scale=2 selem=%ldst_single_selem \
560 index=%ldst_single_index_s
561 @ldst_single_d . index:1 ...... p:1 .. rm:5 ...... rn:5 rt:5 \
562 &ldst_single scale=3 selem=%ldst_single_selem
564 ST_single 0 . 001101 . 0 . ..... 00 . ... ..... ..... @ldst_single_b
565 ST_single 0 . 001101 . 0 . ..... 01 . ..0 ..... ..... @ldst_single_h
566 ST_single 0 . 001101 . 0 . ..... 10 . .00 ..... ..... @ldst_single_s
567 ST_single 0 . 001101 . 0 . ..... 10 . 001 ..... ..... @ldst_single_d
569 LD_single 0 . 001101 . 1 . ..... 00 . ... ..... ..... @ldst_single_b
570 LD_single 0 . 001101 . 1 . ..... 01 . ..0 ..... ..... @ldst_single_h
571 LD_single 0 . 001101 . 1 . ..... 10 . .00 ..... ..... @ldst_single_s
572 LD_single 0 . 001101 . 1 . ..... 10 . 001 ..... ..... @ldst_single_d
574 # Replicating load case
575 LD_single_repl 0 q:1 001101 p:1 1 . rm:5 11 . 0 scale:2 rn:5 rt:5 selem=%ldst_single_selem
577 %tag_offset 12:s9 !function=scale_by_log2_tag_granule
578 &ldst_tag rn rt imm p w
579 @ldst_tag ........ .. . ......... .. rn:5 rt:5 &ldst_tag imm=%tag_offset
580 @ldst_tag_mult ........ .. . 000000000 .. rn:5 rt:5 &ldst_tag imm=0
582 STZGM 11011001 00 1 ......... 00 ..... ..... @ldst_tag_mult p=0 w=0
583 STG 11011001 00 1 ......... 01 ..... ..... @ldst_tag p=1 w=1
584 STG 11011001 00 1 ......... 10 ..... ..... @ldst_tag p=0 w=0
585 STG 11011001 00 1 ......... 11 ..... ..... @ldst_tag p=0 w=1
587 LDG 11011001 01 1 ......... 00 ..... ..... @ldst_tag p=0 w=0
588 STZG 11011001 01 1 ......... 01 ..... ..... @ldst_tag p=1 w=1
589 STZG 11011001 01 1 ......... 10 ..... ..... @ldst_tag p=0 w=0
590 STZG 11011001 01 1 ......... 11 ..... ..... @ldst_tag p=0 w=1
592 STGM 11011001 10 1 ......... 00 ..... ..... @ldst_tag_mult p=0 w=0
593 ST2G 11011001 10 1 ......... 01 ..... ..... @ldst_tag p=1 w=1
594 ST2G 11011001 10 1 ......... 10 ..... ..... @ldst_tag p=0 w=0
595 ST2G 11011001 10 1 ......... 11 ..... ..... @ldst_tag p=0 w=1
597 LDGM 11011001 11 1 ......... 00 ..... ..... @ldst_tag_mult p=0 w=0
598 STZ2G 11011001 11 1 ......... 01 ..... ..... @ldst_tag p=1 w=1
599 STZ2G 11011001 11 1 ......... 10 ..... ..... @ldst_tag p=0 w=0
600 STZ2G 11011001 11 1 ......... 11 ..... ..... @ldst_tag p=0 w=1
602 # Memory operations (memset, memcpy, memmove)
603 # Each of these comes in a set of three, eg SETP (prologue), SETM (main),
604 # SETE (epilogue), and each of those has different flavours to
605 # indicate whether memory accesses should be unpriv or non-temporal.
606 # We don't distinguish temporal and non-temporal accesses, but we
607 # do need to report it in syndrome register values.
609 # Memset
610 &set rs rn rd unpriv nontemp
611 # op2 bit 1 is nontemporal bit
612 @set .. ......... rs:5 .. nontemp:1 unpriv:1 .. rn:5 rd:5 &set
614 SETP 00 011001110 ..... 00 . . 01 ..... ..... @set
615 SETM 00 011001110 ..... 01 . . 01 ..... ..... @set
616 SETE 00 011001110 ..... 10 . . 01 ..... ..... @set
618 # Like SET, but also setting MTE tags
619 SETGP 00 011101110 ..... 00 . . 01 ..... ..... @set
620 SETGM 00 011101110 ..... 01 . . 01 ..... ..... @set
621 SETGE 00 011101110 ..... 10 . . 01 ..... ..... @set
623 # Memmove/Memcopy: the CPY insns allow overlapping src/dest and
624 # copy in the correct direction; the CPYF insns always copy forwards.
625 #
626 # options has the nontemporal and unpriv bits for src and dest
627 &cpy rs rn rd options
628 @cpy .. ... . ..... rs:5 options:4 .. rn:5 rd:5 &cpy
630 CPYFP 00 011 0 01000 ..... .... 01 ..... ..... @cpy
631 CPYFM 00 011 0 01010 ..... .... 01 ..... ..... @cpy
632 CPYFE 00 011 0 01100 ..... .... 01 ..... ..... @cpy
633 CPYP 00 011 1 01000 ..... .... 01 ..... ..... @cpy
634 CPYM 00 011 1 01010 ..... .... 01 ..... ..... @cpy
635 CPYE 00 011 1 01100 ..... .... 01 ..... ..... @cpy
637 ### Cryptographic AES
639 AESE 01001110 00 10100 00100 10 ..... ..... @r2r_q1e0
640 AESD 01001110 00 10100 00101 10 ..... ..... @r2r_q1e0
641 AESMC 01001110 00 10100 00110 10 ..... ..... @rr_q1e0
642 AESIMC 01001110 00 10100 00111 10 ..... ..... @rr_q1e0
644 ### Cryptographic three-register SHA
646 SHA1C 0101 1110 000 ..... 000000 ..... ..... @rrr_q1e0
647 SHA1P 0101 1110 000 ..... 000100 ..... ..... @rrr_q1e0
648 SHA1M 0101 1110 000 ..... 001000 ..... ..... @rrr_q1e0
649 SHA1SU0 0101 1110 000 ..... 001100 ..... ..... @rrr_q1e0
650 SHA256H 0101 1110 000 ..... 010000 ..... ..... @rrr_q1e0
651 SHA256H2 0101 1110 000 ..... 010100 ..... ..... @rrr_q1e0
652 SHA256SU1 0101 1110 000 ..... 011000 ..... ..... @rrr_q1e0
654 ### Cryptographic two-register SHA
656 SHA1H 0101 1110 0010 1000 0000 10 ..... ..... @rr_q1e0
657 SHA1SU1 0101 1110 0010 1000 0001 10 ..... ..... @rr_q1e0
658 SHA256SU0 0101 1110 0010 1000 0010 10 ..... ..... @rr_q1e0
660 ### Cryptographic three-register SHA512
662 SHA512H 1100 1110 011 ..... 100000 ..... ..... @rrr_q1e0
663 SHA512H2 1100 1110 011 ..... 100001 ..... ..... @rrr_q1e0
664 SHA512SU1 1100 1110 011 ..... 100010 ..... ..... @rrr_q1e0
665 RAX1 1100 1110 011 ..... 100011 ..... ..... @rrr_q1e3
666 SM3PARTW1 1100 1110 011 ..... 110000 ..... ..... @rrr_q1e0
667 SM3PARTW2 1100 1110 011 ..... 110001 ..... ..... @rrr_q1e0
668 SM4EKEY 1100 1110 011 ..... 110010 ..... ..... @rrr_q1e0
670 ### Cryptographic two-register SHA512
672 SHA512SU0 1100 1110 110 00000 100000 ..... ..... @rr_q1e0
673 SM4E 1100 1110 110 00000 100001 ..... ..... @r2r_q1e0
675 ### Cryptographic four-register
677 EOR3 1100 1110 000 ..... 0 ..... ..... ..... @rrrr_q1e3
678 BCAX 1100 1110 001 ..... 0 ..... ..... ..... @rrrr_q1e3
679 SM3SS1 1100 1110 010 ..... 0 ..... ..... ..... @rrrr_q1e3
681 ### Cryptographic three-register, imm2
683 &crypto3i rd rn rm imm
684 @crypto3i ........ ... rm:5 .. imm:2 .. rn:5 rd:5 &crypto3i
686 SM3TT1A 11001110 010 ..... 10 .. 00 ..... ..... @crypto3i
687 SM3TT1B 11001110 010 ..... 10 .. 01 ..... ..... @crypto3i
688 SM3TT2A 11001110 010 ..... 10 .. 10 ..... ..... @crypto3i
689 SM3TT2B 11001110 010 ..... 10 .. 11 ..... ..... @crypto3i
691 ### Cryptographic XAR
693 XAR 1100 1110 100 rm:5 imm:6 rn:5 rd:5
695 ### Advanced SIMD scalar copy
697 DUP_element_s 0101 1110 000 imm:5 0 0000 1 rn:5 rd:5
699 ### Advanced SIMD copy
701 DUP_element_v 0 q:1 00 1110 000 imm:5 0 0000 1 rn:5 rd:5
702 DUP_general 0 q:1 00 1110 000 imm:5 0 0001 1 rn:5 rd:5
703 INS_general 0 1 00 1110 000 imm:5 0 0011 1 rn:5 rd:5
704 SMOV 0 q:1 00 1110 000 imm:5 0 0101 1 rn:5 rd:5
705 UMOV 0 q:1 00 1110 000 imm:5 0 0111 1 rn:5 rd:5
706 INS_element 0 1 10 1110 000 di:5 0 si:4 1 rn:5 rd:5
708 ### Advanced SIMD scalar three same
710 FADD_s 0001 1110 ..1 ..... 0010 10 ..... ..... @rrr_hsd
711 FSUB_s 0001 1110 ..1 ..... 0011 10 ..... ..... @rrr_hsd
712 FDIV_s 0001 1110 ..1 ..... 0001 10 ..... ..... @rrr_hsd
713 FMUL_s 0001 1110 ..1 ..... 0000 10 ..... ..... @rrr_hsd
714 FNMUL_s 0001 1110 ..1 ..... 1000 10 ..... ..... @rrr_hsd
716 FMAX_s 0001 1110 ..1 ..... 0100 10 ..... ..... @rrr_hsd
717 FMIN_s 0001 1110 ..1 ..... 0101 10 ..... ..... @rrr_hsd
718 FMAXNM_s 0001 1110 ..1 ..... 0110 10 ..... ..... @rrr_hsd
719 FMINNM_s 0001 1110 ..1 ..... 0111 10 ..... ..... @rrr_hsd
721 FMULX_s 0101 1110 010 ..... 00011 1 ..... ..... @rrr_h
722 FMULX_s 0101 1110 0.1 ..... 11011 1 ..... ..... @rrr_sd
724 FCMEQ_s 0101 1110 010 ..... 00100 1 ..... ..... @rrr_h
725 FCMEQ_s 0101 1110 0.1 ..... 11100 1 ..... ..... @rrr_sd
727 FCMGE_s 0111 1110 010 ..... 00100 1 ..... ..... @rrr_h
728 FCMGE_s 0111 1110 0.1 ..... 11100 1 ..... ..... @rrr_sd
730 FCMGT_s 0111 1110 110 ..... 00100 1 ..... ..... @rrr_h
731 FCMGT_s 0111 1110 1.1 ..... 11100 1 ..... ..... @rrr_sd
733 FACGE_s 0111 1110 010 ..... 00101 1 ..... ..... @rrr_h
734 FACGE_s 0111 1110 0.1 ..... 11101 1 ..... ..... @rrr_sd
736 FACGT_s 0111 1110 110 ..... 00101 1 ..... ..... @rrr_h
737 FACGT_s 0111 1110 1.1 ..... 11101 1 ..... ..... @rrr_sd
739 FABD_s 0111 1110 110 ..... 00010 1 ..... ..... @rrr_h
740 FABD_s 0111 1110 1.1 ..... 11010 1 ..... ..... @rrr_sd
742 FRECPS_s 0101 1110 010 ..... 00111 1 ..... ..... @rrr_h
743 FRECPS_s 0101 1110 0.1 ..... 11111 1 ..... ..... @rrr_sd
745 FRSQRTS_s 0101 1110 110 ..... 00111 1 ..... ..... @rrr_h
746 FRSQRTS_s 0101 1110 1.1 ..... 11111 1 ..... ..... @rrr_sd
748 SQADD_s 0101 1110 ..1 ..... 00001 1 ..... ..... @rrr_e
749 UQADD_s 0111 1110 ..1 ..... 00001 1 ..... ..... @rrr_e
750 SQSUB_s 0101 1110 ..1 ..... 00101 1 ..... ..... @rrr_e
751 UQSUB_s 0111 1110 ..1 ..... 00101 1 ..... ..... @rrr_e
753 ### Advanced SIMD scalar pairwise
755 FADDP_s 0101 1110 0011 0000 1101 10 ..... ..... @rr_h
756 FADDP_s 0111 1110 0.11 0000 1101 10 ..... ..... @rr_sd
758 FMAXP_s 0101 1110 0011 0000 1111 10 ..... ..... @rr_h
759 FMAXP_s 0111 1110 0.11 0000 1111 10 ..... ..... @rr_sd
761 FMINP_s 0101 1110 1011 0000 1111 10 ..... ..... @rr_h
762 FMINP_s 0111 1110 1.11 0000 1111 10 ..... ..... @rr_sd
764 FMAXNMP_s 0101 1110 0011 0000 1100 10 ..... ..... @rr_h
765 FMAXNMP_s 0111 1110 0.11 0000 1100 10 ..... ..... @rr_sd
767 FMINNMP_s 0101 1110 1011 0000 1100 10 ..... ..... @rr_h
768 FMINNMP_s 0111 1110 1.11 0000 1100 10 ..... ..... @rr_sd
770 ADDP_s 0101 1110 1111 0001 1011 10 ..... ..... @rr_d
772 ### Advanced SIMD three same
774 FADD_v 0.00 1110 010 ..... 00010 1 ..... ..... @qrrr_h
775 FADD_v 0.00 1110 0.1 ..... 11010 1 ..... ..... @qrrr_sd
777 FSUB_v 0.00 1110 110 ..... 00010 1 ..... ..... @qrrr_h
778 FSUB_v 0.00 1110 1.1 ..... 11010 1 ..... ..... @qrrr_sd
780 FDIV_v 0.10 1110 010 ..... 00111 1 ..... ..... @qrrr_h
781 FDIV_v 0.10 1110 0.1 ..... 11111 1 ..... ..... @qrrr_sd
783 FMUL_v 0.10 1110 010 ..... 00011 1 ..... ..... @qrrr_h
784 FMUL_v 0.10 1110 0.1 ..... 11011 1 ..... ..... @qrrr_sd
786 FMAX_v 0.00 1110 010 ..... 00110 1 ..... ..... @qrrr_h
787 FMAX_v 0.00 1110 0.1 ..... 11110 1 ..... ..... @qrrr_sd
789 FMIN_v 0.00 1110 110 ..... 00110 1 ..... ..... @qrrr_h
790 FMIN_v 0.00 1110 1.1 ..... 11110 1 ..... ..... @qrrr_sd
792 FMAXNM_v 0.00 1110 010 ..... 00000 1 ..... ..... @qrrr_h
793 FMAXNM_v 0.00 1110 0.1 ..... 11000 1 ..... ..... @qrrr_sd
795 FMINNM_v 0.00 1110 110 ..... 00000 1 ..... ..... @qrrr_h
796 FMINNM_v 0.00 1110 1.1 ..... 11000 1 ..... ..... @qrrr_sd
798 FMULX_v 0.00 1110 010 ..... 00011 1 ..... ..... @qrrr_h
799 FMULX_v 0.00 1110 0.1 ..... 11011 1 ..... ..... @qrrr_sd
801 FMLA_v 0.00 1110 010 ..... 00001 1 ..... ..... @qrrr_h
802 FMLA_v 0.00 1110 0.1 ..... 11001 1 ..... ..... @qrrr_sd
804 FMLS_v 0.00 1110 110 ..... 00001 1 ..... ..... @qrrr_h
805 FMLS_v 0.00 1110 1.1 ..... 11001 1 ..... ..... @qrrr_sd
807 FMLAL_v 0.00 1110 001 ..... 11101 1 ..... ..... @qrrr_h
808 FMLSL_v 0.00 1110 101 ..... 11101 1 ..... ..... @qrrr_h
809 FMLAL2_v 0.10 1110 001 ..... 11001 1 ..... ..... @qrrr_h
810 FMLSL2_v 0.10 1110 101 ..... 11001 1 ..... ..... @qrrr_h
812 FCMEQ_v 0.00 1110 010 ..... 00100 1 ..... ..... @qrrr_h
813 FCMEQ_v 0.00 1110 0.1 ..... 11100 1 ..... ..... @qrrr_sd
815 FCMGE_v 0.10 1110 010 ..... 00100 1 ..... ..... @qrrr_h
816 FCMGE_v 0.10 1110 0.1 ..... 11100 1 ..... ..... @qrrr_sd
818 FCMGT_v 0.10 1110 110 ..... 00100 1 ..... ..... @qrrr_h
819 FCMGT_v 0.10 1110 1.1 ..... 11100 1 ..... ..... @qrrr_sd
821 FACGE_v 0.10 1110 010 ..... 00101 1 ..... ..... @qrrr_h
822 FACGE_v 0.10 1110 0.1 ..... 11101 1 ..... ..... @qrrr_sd
824 FACGT_v 0.10 1110 110 ..... 00101 1 ..... ..... @qrrr_h
825 FACGT_v 0.10 1110 1.1 ..... 11101 1 ..... ..... @qrrr_sd
827 FABD_v 0.10 1110 110 ..... 00010 1 ..... ..... @qrrr_h
828 FABD_v 0.10 1110 1.1 ..... 11010 1 ..... ..... @qrrr_sd
830 FRECPS_v 0.00 1110 010 ..... 00111 1 ..... ..... @qrrr_h
831 FRECPS_v 0.00 1110 0.1 ..... 11111 1 ..... ..... @qrrr_sd
833 FRSQRTS_v 0.00 1110 110 ..... 00111 1 ..... ..... @qrrr_h
834 FRSQRTS_v 0.00 1110 1.1 ..... 11111 1 ..... ..... @qrrr_sd
836 FADDP_v 0.10 1110 010 ..... 00010 1 ..... ..... @qrrr_h
837 FADDP_v 0.10 1110 0.1 ..... 11010 1 ..... ..... @qrrr_sd
839 FMAXP_v 0.10 1110 010 ..... 00110 1 ..... ..... @qrrr_h
840 FMAXP_v 0.10 1110 0.1 ..... 11110 1 ..... ..... @qrrr_sd
842 FMINP_v 0.10 1110 110 ..... 00110 1 ..... ..... @qrrr_h
843 FMINP_v 0.10 1110 1.1 ..... 11110 1 ..... ..... @qrrr_sd
845 FMAXNMP_v 0.10 1110 010 ..... 00000 1 ..... ..... @qrrr_h
846 FMAXNMP_v 0.10 1110 0.1 ..... 11000 1 ..... ..... @qrrr_sd
848 FMINNMP_v 0.10 1110 110 ..... 00000 1 ..... ..... @qrrr_h
849 FMINNMP_v 0.10 1110 1.1 ..... 11000 1 ..... ..... @qrrr_sd
851 ADDP_v 0.00 1110 ..1 ..... 10111 1 ..... ..... @qrrr_e
852 SMAXP_v 0.00 1110 ..1 ..... 10100 1 ..... ..... @qrrr_e
853 SMINP_v 0.00 1110 ..1 ..... 10101 1 ..... ..... @qrrr_e
854 UMAXP_v 0.10 1110 ..1 ..... 10100 1 ..... ..... @qrrr_e
855 UMINP_v 0.10 1110 ..1 ..... 10101 1 ..... ..... @qrrr_e
857 AND_v 0.00 1110 001 ..... 00011 1 ..... ..... @qrrr_b
858 BIC_v 0.00 1110 011 ..... 00011 1 ..... ..... @qrrr_b
859 ORR_v 0.00 1110 101 ..... 00011 1 ..... ..... @qrrr_b
860 ORN_v 0.00 1110 111 ..... 00011 1 ..... ..... @qrrr_b
861 EOR_v 0.10 1110 001 ..... 00011 1 ..... ..... @qrrr_b
862 BSL_v 0.10 1110 011 ..... 00011 1 ..... ..... @qrrr_b
863 BIT_v 0.10 1110 101 ..... 00011 1 ..... ..... @qrrr_b
864 BIF_v 0.10 1110 111 ..... 00011 1 ..... ..... @qrrr_b
866 SQADD_v 0.00 1110 ..1 ..... 00001 1 ..... ..... @qrrr_e
867 UQADD_v 0.10 1110 ..1 ..... 00001 1 ..... ..... @qrrr_e
868 SQSUB_v 0.00 1110 ..1 ..... 00101 1 ..... ..... @qrrr_e
869 UQSUB_v 0.10 1110 ..1 ..... 00101 1 ..... ..... @qrrr_e
871 ### Advanced SIMD scalar x indexed element
873 FMUL_si 0101 1111 00 .. .... 1001 . 0 ..... ..... @rrx_h
874 FMUL_si 0101 1111 10 . ..... 1001 . 0 ..... ..... @rrx_s
875 FMUL_si 0101 1111 11 0 ..... 1001 . 0 ..... ..... @rrx_d
877 FMLA_si 0101 1111 00 .. .... 0001 . 0 ..... ..... @rrx_h
878 FMLA_si 0101 1111 10 .. .... 0001 . 0 ..... ..... @rrx_s
879 FMLA_si 0101 1111 11 0. .... 0001 . 0 ..... ..... @rrx_d
881 FMLS_si 0101 1111 00 .. .... 0101 . 0 ..... ..... @rrx_h
882 FMLS_si 0101 1111 10 .. .... 0101 . 0 ..... ..... @rrx_s
883 FMLS_si 0101 1111 11 0. .... 0101 . 0 ..... ..... @rrx_d
885 FMULX_si 0111 1111 00 .. .... 1001 . 0 ..... ..... @rrx_h
886 FMULX_si 0111 1111 10 . ..... 1001 . 0 ..... ..... @rrx_s
887 FMULX_si 0111 1111 11 0 ..... 1001 . 0 ..... ..... @rrx_d
889 ### Advanced SIMD vector x indexed element
891 FMUL_vi 0.00 1111 00 .. .... 1001 . 0 ..... ..... @qrrx_h
892 FMUL_vi 0.00 1111 10 . ..... 1001 . 0 ..... ..... @qrrx_s
893 FMUL_vi 0.00 1111 11 0 ..... 1001 . 0 ..... ..... @qrrx_d
895 FMLA_vi 0.00 1111 00 .. .... 0001 . 0 ..... ..... @qrrx_h
896 FMLA_vi 0.00 1111 10 . ..... 0001 . 0 ..... ..... @qrrx_s
897 FMLA_vi 0.00 1111 11 0 ..... 0001 . 0 ..... ..... @qrrx_d
899 FMLS_vi 0.00 1111 00 .. .... 0101 . 0 ..... ..... @qrrx_h
900 FMLS_vi 0.00 1111 10 . ..... 0101 . 0 ..... ..... @qrrx_s
901 FMLS_vi 0.00 1111 11 0 ..... 0101 . 0 ..... ..... @qrrx_d
903 FMULX_vi 0.10 1111 00 .. .... 1001 . 0 ..... ..... @qrrx_h
904 FMULX_vi 0.10 1111 10 . ..... 1001 . 0 ..... ..... @qrrx_s
905 FMULX_vi 0.10 1111 11 0 ..... 1001 . 0 ..... ..... @qrrx_d
907 FMLAL_vi 0.00 1111 10 .. .... 0000 . 0 ..... ..... @qrrx_h
908 FMLSL_vi 0.00 1111 10 .. .... 0100 . 0 ..... ..... @qrrx_h
909 FMLAL2_vi 0.10 1111 10 .. .... 1000 . 0 ..... ..... @qrrx_h
910 FMLSL2_vi 0.10 1111 10 .. .... 1100 . 0 ..... ..... @qrrx_h