| blob | d6dbcaf3cbbe93f2415943086564dafd9effce8e |
1 /*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2018 SiFive, Inc
5 * Copyright (c) 2008-2009 Arnaud Patard <arnaud.patard@rtp-net.org>
6 * Copyright (c) 2009 Aurelien Jarno <aurelien@aurel32.net>
7 * Copyright (c) 2008 Fabrice Bellard
8 *
9 * Based on i386/tcg-target.c and mips/tcg-target.c
10 *
11 * Permission is hereby granted, free of charge, to any person obtaining a copy
12 * of this software and associated documentation files (the "Software"), to deal
13 * in the Software without restriction, including without limitation the rights
14 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
15 * copies of the Software, and to permit persons to whom the Software is
16 * furnished to do so, subject to the following conditions:
17 *
18 * The above copyright notice and this permission notice shall be included in
19 * all copies or substantial portions of the Software.
20 *
21 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
22 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
23 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
24 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
25 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
26 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
27 * THE SOFTWARE.
28 */
30 #include "../tcg-ldst.c.inc"
31 #include "../tcg-pool.c.inc"
33 #ifdef CONFIG_DEBUG_TCG
34 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
35 "zero",
36 "ra",
37 "sp",
38 "gp",
39 "tp",
40 "t0",
41 "t1",
42 "t2",
43 "s0",
44 "s1",
45 "a0",
46 "a1",
47 "a2",
48 "a3",
49 "a4",
50 "a5",
51 "a6",
52 "a7",
53 "s2",
54 "s3",
55 "s4",
56 "s5",
57 "s6",
58 "s7",
59 "s8",
60 "s9",
61 "s10",
62 "s11",
63 "t3",
64 "t4",
65 "t5",
66 "t6"
67 };
68 #endif
70 static const int tcg_target_reg_alloc_order[] = {
71 /* Call saved registers */
72 /* TCG_REG_S0 reserved for TCG_AREG0 */
73 TCG_REG_S1,
74 TCG_REG_S2,
75 TCG_REG_S3,
76 TCG_REG_S4,
77 TCG_REG_S5,
78 TCG_REG_S6,
79 TCG_REG_S7,
80 TCG_REG_S8,
81 TCG_REG_S9,
82 TCG_REG_S10,
83 TCG_REG_S11,
85 /* Call clobbered registers */
86 TCG_REG_T0,
87 TCG_REG_T1,
88 TCG_REG_T2,
89 TCG_REG_T3,
90 TCG_REG_T4,
91 TCG_REG_T5,
92 TCG_REG_T6,
94 /* Argument registers */
95 TCG_REG_A0,
96 TCG_REG_A1,
97 TCG_REG_A2,
98 TCG_REG_A3,
99 TCG_REG_A4,
100 TCG_REG_A5,
101 TCG_REG_A6,
102 TCG_REG_A7,
103 };
105 static const int tcg_target_call_iarg_regs[] = {
106 TCG_REG_A0,
107 TCG_REG_A1,
108 TCG_REG_A2,
109 TCG_REG_A3,
110 TCG_REG_A4,
111 TCG_REG_A5,
112 TCG_REG_A6,
113 TCG_REG_A7,
114 };
116 #ifndef have_zbb
117 bool have_zbb;
118 #endif
119 #if defined(__riscv_arch_test) && defined(__riscv_zba)
120 # define have_zba true
121 #else
122 static bool have_zba;
123 #endif
124 #if defined(__riscv_arch_test) && defined(__riscv_zicond)
125 # define have_zicond true
126 #else
127 static bool have_zicond;
128 #endif
130 static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot)
131 {
132 tcg_debug_assert(kind == TCG_CALL_RET_NORMAL);
133 tcg_debug_assert(slot >= 0 && slot <= 1);
134 return TCG_REG_A0 + slot;
135 }
137 #define TCG_CT_CONST_ZERO 0x100
138 #define TCG_CT_CONST_S12 0x200
139 #define TCG_CT_CONST_N12 0x400
140 #define TCG_CT_CONST_M12 0x800
141 #define TCG_CT_CONST_J12 0x1000
143 #define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 32)
145 #define sextreg sextract64
147 /* test if a constant matches the constraint */
148 static bool tcg_target_const_match(int64_t val, TCGType type, int ct, int vece)
149 {
150 if (ct & TCG_CT_CONST) {
151 return 1;
152 }
153 if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
154 return 1;
155 }
156 /*
157 * Sign extended from 12 bits: [-0x800, 0x7ff].
158 * Used for most arithmetic, as this is the isa field.
159 */
160 if ((ct & TCG_CT_CONST_S12) && val >= -0x800 && val <= 0x7ff) {
161 return 1;
162 }
163 /*
164 * Sign extended from 12 bits, negated: [-0x7ff, 0x800].
165 * Used for subtraction, where a constant must be handled by ADDI.
166 */
167 if ((ct & TCG_CT_CONST_N12) && val >= -0x7ff && val <= 0x800) {
168 return 1;
169 }
170 /*
171 * Sign extended from 12 bits, +/- matching: [-0x7ff, 0x7ff].
172 * Used by addsub2 and movcond, which may need the negative value,
173 * and requires the modified constant to be representable.
174 */
175 if ((ct & TCG_CT_CONST_M12) && val >= -0x7ff && val <= 0x7ff) {
176 return 1;
177 }
178 /*
179 * Inverse of sign extended from 12 bits: ~[-0x800, 0x7ff].
180 * Used to map ANDN back to ANDI, etc.
181 */
182 if ((ct & TCG_CT_CONST_J12) && ~val >= -0x800 && ~val <= 0x7ff) {
183 return 1;
184 }
185 return 0;
186 }
188 /*
189 * RISC-V Base ISA opcodes (IM)
190 */
192 typedef enum {
193 OPC_ADD = 0x33,
194 OPC_ADDI = 0x13,
195 OPC_AND = 0x7033,
196 OPC_ANDI = 0x7013,
197 OPC_AUIPC = 0x17,
198 OPC_BEQ = 0x63,
199 OPC_BGE = 0x5063,
200 OPC_BGEU = 0x7063,
201 OPC_BLT = 0x4063,
202 OPC_BLTU = 0x6063,
203 OPC_BNE = 0x1063,
204 OPC_DIV = 0x2004033,
205 OPC_DIVU = 0x2005033,
206 OPC_JAL = 0x6f,
207 OPC_JALR = 0x67,
208 OPC_LB = 0x3,
209 OPC_LBU = 0x4003,
210 OPC_LD = 0x3003,
211 OPC_LH = 0x1003,
212 OPC_LHU = 0x5003,
213 OPC_LUI = 0x37,
214 OPC_LW = 0x2003,
215 OPC_LWU = 0x6003,
216 OPC_MUL = 0x2000033,
217 OPC_MULH = 0x2001033,
218 OPC_MULHSU = 0x2002033,
219 OPC_MULHU = 0x2003033,
220 OPC_OR = 0x6033,
221 OPC_ORI = 0x6013,
222 OPC_REM = 0x2006033,
223 OPC_REMU = 0x2007033,
224 OPC_SB = 0x23,
225 OPC_SD = 0x3023,
226 OPC_SH = 0x1023,
227 OPC_SLL = 0x1033,
228 OPC_SLLI = 0x1013,
229 OPC_SLT = 0x2033,
230 OPC_SLTI = 0x2013,
231 OPC_SLTIU = 0x3013,
232 OPC_SLTU = 0x3033,
233 OPC_SRA = 0x40005033,
234 OPC_SRAI = 0x40005013,
235 OPC_SRL = 0x5033,
236 OPC_SRLI = 0x5013,
237 OPC_SUB = 0x40000033,
238 OPC_SW = 0x2023,
239 OPC_XOR = 0x4033,
240 OPC_XORI = 0x4013,
242 OPC_ADDIW = 0x1b,
243 OPC_ADDW = 0x3b,
244 OPC_DIVUW = 0x200503b,
245 OPC_DIVW = 0x200403b,
246 OPC_MULW = 0x200003b,
247 OPC_REMUW = 0x200703b,
248 OPC_REMW = 0x200603b,
249 OPC_SLLIW = 0x101b,
250 OPC_SLLW = 0x103b,
251 OPC_SRAIW = 0x4000501b,
252 OPC_SRAW = 0x4000503b,
253 OPC_SRLIW = 0x501b,
254 OPC_SRLW = 0x503b,
255 OPC_SUBW = 0x4000003b,
257 OPC_FENCE = 0x0000000f,
258 OPC_NOP = OPC_ADDI, /* nop = addi r0,r0,0 */
260 /* Zba: Bit manipulation extension, address generation */
261 OPC_ADD_UW = 0x0800003b,
263 /* Zbb: Bit manipulation extension, basic bit manipulation */
264 OPC_ANDN = 0x40007033,
265 OPC_CLZ = 0x60001013,
266 OPC_CLZW = 0x6000101b,
267 OPC_CPOP = 0x60201013,
268 OPC_CPOPW = 0x6020101b,
269 OPC_CTZ = 0x60101013,
270 OPC_CTZW = 0x6010101b,
271 OPC_ORN = 0x40006033,
272 OPC_REV8 = 0x6b805013,
273 OPC_ROL = 0x60001033,
274 OPC_ROLW = 0x6000103b,
275 OPC_ROR = 0x60005033,
276 OPC_RORW = 0x6000503b,
277 OPC_RORI = 0x60005013,
278 OPC_RORIW = 0x6000501b,
279 OPC_SEXT_B = 0x60401013,
280 OPC_SEXT_H = 0x60501013,
281 OPC_XNOR = 0x40004033,
282 OPC_ZEXT_H = 0x0800403b,
284 /* Zicond: integer conditional operations */
285 OPC_CZERO_EQZ = 0x0e005033,
286 OPC_CZERO_NEZ = 0x0e007033,
287 } RISCVInsn;
289 /*
290 * RISC-V immediate and instruction encoders (excludes 16-bit RVC)
291 */
293 /* Type-R */
295 static int32_t encode_r(RISCVInsn opc, TCGReg rd, TCGReg rs1, TCGReg rs2)
296 {
297 return opc | (rd & 0x1f) << 7 | (rs1 & 0x1f) << 15 | (rs2 & 0x1f) << 20;
298 }
300 /* Type-I */
302 static int32_t encode_imm12(uint32_t imm)
303 {
304 return (imm & 0xfff) << 20;
305 }
307 static int32_t encode_i(RISCVInsn opc, TCGReg rd, TCGReg rs1, uint32_t imm)
308 {
309 return opc | (rd & 0x1f) << 7 | (rs1 & 0x1f) << 15 | encode_imm12(imm);
310 }
312 /* Type-S */
314 static int32_t encode_simm12(uint32_t imm)
315 {
316 int32_t ret = 0;
318 ret |= (imm & 0xFE0) << 20;
319 ret |= (imm & 0x1F) << 7;
321 return ret;
322 }
324 static int32_t encode_s(RISCVInsn opc, TCGReg rs1, TCGReg rs2, uint32_t imm)
325 {
326 return opc | (rs1 & 0x1f) << 15 | (rs2 & 0x1f) << 20 | encode_simm12(imm);
327 }
329 /* Type-SB */
331 static int32_t encode_sbimm12(uint32_t imm)
332 {
333 int32_t ret = 0;
335 ret |= (imm & 0x1000) << 19;
336 ret |= (imm & 0x7e0) << 20;
337 ret |= (imm & 0x1e) << 7;
338 ret |= (imm & 0x800) >> 4;
340 return ret;
341 }
343 static int32_t encode_sb(RISCVInsn opc, TCGReg rs1, TCGReg rs2, uint32_t imm)
344 {
345 return opc | (rs1 & 0x1f) << 15 | (rs2 & 0x1f) << 20 | encode_sbimm12(imm);
346 }
348 /* Type-U */
350 static int32_t encode_uimm20(uint32_t imm)
351 {
352 return imm & 0xfffff000;
353 }
355 static int32_t encode_u(RISCVInsn opc, TCGReg rd, uint32_t imm)
356 {
357 return opc | (rd & 0x1f) << 7 | encode_uimm20(imm);
358 }
360 /* Type-UJ */
362 static int32_t encode_ujimm20(uint32_t imm)
363 {
364 int32_t ret = 0;
366 ret |= (imm & 0x0007fe) << (21 - 1);
367 ret |= (imm & 0x000800) << (20 - 11);
368 ret |= (imm & 0x0ff000) << (12 - 12);
369 ret |= (imm & 0x100000) << (31 - 20);
371 return ret;
372 }
374 static int32_t encode_uj(RISCVInsn opc, TCGReg rd, uint32_t imm)
375 {
376 return opc | (rd & 0x1f) << 7 | encode_ujimm20(imm);
377 }
379 /*
380 * RISC-V instruction emitters
381 */
383 static void tcg_out_opc_reg(TCGContext *s, RISCVInsn opc,
384 TCGReg rd, TCGReg rs1, TCGReg rs2)
385 {
386 tcg_out32(s, encode_r(opc, rd, rs1, rs2));
387 }
389 static void tcg_out_opc_imm(TCGContext *s, RISCVInsn opc,
390 TCGReg rd, TCGReg rs1, TCGArg imm)
391 {
392 tcg_out32(s, encode_i(opc, rd, rs1, imm));
393 }
395 static void tcg_out_opc_store(TCGContext *s, RISCVInsn opc,
396 TCGReg rs1, TCGReg rs2, uint32_t imm)
397 {
398 tcg_out32(s, encode_s(opc, rs1, rs2, imm));
399 }
401 static void tcg_out_opc_branch(TCGContext *s, RISCVInsn opc,
402 TCGReg rs1, TCGReg rs2, uint32_t imm)
403 {
404 tcg_out32(s, encode_sb(opc, rs1, rs2, imm));
405 }
407 static void tcg_out_opc_upper(TCGContext *s, RISCVInsn opc,
408 TCGReg rd, uint32_t imm)
409 {
410 tcg_out32(s, encode_u(opc, rd, imm));
411 }
413 static void tcg_out_opc_jump(TCGContext *s, RISCVInsn opc,
414 TCGReg rd, uint32_t imm)
415 {
416 tcg_out32(s, encode_uj(opc, rd, imm));
417 }
419 static void tcg_out_nop_fill(tcg_insn_unit *p, int count)
420 {
421 int i;
422 for (i = 0; i < count; ++i) {
423 p[i] = OPC_NOP;
424 }
425 }
427 /*
428 * Relocations
429 */
431 static bool reloc_sbimm12(tcg_insn_unit *src_rw, const tcg_insn_unit *target)
432 {
433 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw);
434 intptr_t offset = (intptr_t)target - (intptr_t)src_rx;
436 tcg_debug_assert((offset & 1) == 0);
437 if (offset == sextreg(offset, 0, 12)) {
438 *src_rw |= encode_sbimm12(offset);
439 return true;
440 }
442 return false;
443 }
445 static bool reloc_jimm20(tcg_insn_unit *src_rw, const tcg_insn_unit *target)
446 {
447 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw);
448 intptr_t offset = (intptr_t)target - (intptr_t)src_rx;
450 tcg_debug_assert((offset & 1) == 0);
451 if (offset == sextreg(offset, 0, 20)) {
452 *src_rw |= encode_ujimm20(offset);
453 return true;
454 }
456 return false;
457 }
459 static bool reloc_call(tcg_insn_unit *src_rw, const tcg_insn_unit *target)
460 {
461 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw);
462 intptr_t offset = (intptr_t)target - (intptr_t)src_rx;
463 int32_t lo = sextreg(offset, 0, 12);
464 int32_t hi = offset - lo;
466 if (offset == hi + lo) {
467 src_rw[0] |= encode_uimm20(hi);
468 src_rw[1] |= encode_imm12(lo);
469 return true;
470 }
472 return false;
473 }
475 static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
476 intptr_t value, intptr_t addend)
477 {
478 tcg_debug_assert(addend == 0);
479 switch (type) {
480 case R_RISCV_BRANCH:
481 return reloc_sbimm12(code_ptr, (tcg_insn_unit *)value);
482 case R_RISCV_JAL:
483 return reloc_jimm20(code_ptr, (tcg_insn_unit *)value);
484 case R_RISCV_CALL:
485 return reloc_call(code_ptr, (tcg_insn_unit *)value);
486 default:
487 g_assert_not_reached();
488 }
489 }
491 /*
492 * TCG intrinsics
493 */
495 static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
496 {
497 if (ret == arg) {
498 return true;
499 }
500 switch (type) {
501 case TCG_TYPE_I32:
502 case TCG_TYPE_I64:
503 tcg_out_opc_imm(s, OPC_ADDI, ret, arg, 0);
504 break;
505 default:
506 g_assert_not_reached();
507 }
508 return true;
509 }
511 static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd,
512 tcg_target_long val)
513 {
514 tcg_target_long lo, hi, tmp;
515 int shift, ret;
517 if (type == TCG_TYPE_I32) {
518 val = (int32_t)val;
519 }
521 lo = sextreg(val, 0, 12);
522 if (val == lo) {
523 tcg_out_opc_imm(s, OPC_ADDI, rd, TCG_REG_ZERO, lo);
524 return;
525 }
527 hi = val - lo;
528 if (val == (int32_t)val) {
529 tcg_out_opc_upper(s, OPC_LUI, rd, hi);
530 if (lo != 0) {
531 tcg_out_opc_imm(s, OPC_ADDIW, rd, rd, lo);
532 }
533 return;
534 }
536 tmp = tcg_pcrel_diff(s, (void *)val);
537 if (tmp == (int32_t)tmp) {
538 tcg_out_opc_upper(s, OPC_AUIPC, rd, 0);
539 tcg_out_opc_imm(s, OPC_ADDI, rd, rd, 0);
540 ret = reloc_call(s->code_ptr - 2, (const tcg_insn_unit *)val);
541 tcg_debug_assert(ret == true);
542 return;
543 }
545 /* Look for a single 20-bit section. */
546 shift = ctz64(val);
547 tmp = val >> shift;
548 if (tmp == sextreg(tmp, 0, 20)) {
549 tcg_out_opc_upper(s, OPC_LUI, rd, tmp << 12);
550 if (shift > 12) {
551 tcg_out_opc_imm(s, OPC_SLLI, rd, rd, shift - 12);
552 } else {
553 tcg_out_opc_imm(s, OPC_SRAI, rd, rd, 12 - shift);
554 }
555 return;
556 }
558 /* Look for a few high zero bits, with lots of bits set in the middle. */
559 shift = clz64(val);
560 tmp = val << shift;
561 if (tmp == sextreg(tmp, 12, 20) << 12) {
562 tcg_out_opc_upper(s, OPC_LUI, rd, tmp);
563 tcg_out_opc_imm(s, OPC_SRLI, rd, rd, shift);
564 return;
565 } else if (tmp == sextreg(tmp, 0, 12)) {
566 tcg_out_opc_imm(s, OPC_ADDI, rd, TCG_REG_ZERO, tmp);
567 tcg_out_opc_imm(s, OPC_SRLI, rd, rd, shift);
568 return;
569 }
571 /* Drop into the constant pool. */
572 new_pool_label(s, val, R_RISCV_CALL, s->code_ptr, 0);
573 tcg_out_opc_upper(s, OPC_AUIPC, rd, 0);
574 tcg_out_opc_imm(s, OPC_LD, rd, rd, 0);
575 }
577 static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2)
578 {
579 return false;
580 }
582 static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs,
583 tcg_target_long imm)
584 {
585 /* This function is only used for passing structs by reference. */
586 g_assert_not_reached();
587 }
589 static void tcg_out_ext8u(TCGContext *s, TCGReg ret, TCGReg arg)
590 {
591 tcg_out_opc_imm(s, OPC_ANDI, ret, arg, 0xff);
592 }
594 static void tcg_out_ext16u(TCGContext *s, TCGReg ret, TCGReg arg)
595 {
596 if (have_zbb) {
597 tcg_out_opc_reg(s, OPC_ZEXT_H, ret, arg, TCG_REG_ZERO);
598 } else {
599 tcg_out_opc_imm(s, OPC_SLLIW, ret, arg, 16);
600 tcg_out_opc_imm(s, OPC_SRLIW, ret, ret, 16);
601 }
602 }
604 static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg)
605 {
606 if (have_zba) {
607 tcg_out_opc_reg(s, OPC_ADD_UW, ret, arg, TCG_REG_ZERO);
608 } else {
609 tcg_out_opc_imm(s, OPC_SLLI, ret, arg, 32);
610 tcg_out_opc_imm(s, OPC_SRLI, ret, ret, 32);
611 }
612 }
614 static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
615 {
616 if (have_zbb) {
617 tcg_out_opc_imm(s, OPC_SEXT_B, ret, arg, 0);
618 } else {
619 tcg_out_opc_imm(s, OPC_SLLIW, ret, arg, 24);
620 tcg_out_opc_imm(s, OPC_SRAIW, ret, ret, 24);
621 }
622 }
624 static void tcg_out_ext16s(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
625 {
626 if (have_zbb) {
627 tcg_out_opc_imm(s, OPC_SEXT_H, ret, arg, 0);
628 } else {
629 tcg_out_opc_imm(s, OPC_SLLIW, ret, arg, 16);
630 tcg_out_opc_imm(s, OPC_SRAIW, ret, ret, 16);
631 }
632 }
634 static void tcg_out_ext32s(TCGContext *s, TCGReg ret, TCGReg arg)
635 {
636 tcg_out_opc_imm(s, OPC_ADDIW, ret, arg, 0);
637 }
639 static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg ret, TCGReg arg)
640 {
641 if (ret != arg) {
642 tcg_out_ext32s(s, ret, arg);
643 }
644 }
646 static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg ret, TCGReg arg)
647 {
648 tcg_out_ext32u(s, ret, arg);
649 }
651 static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg ret, TCGReg arg)
652 {
653 tcg_out_ext32s(s, ret, arg);
654 }
656 static void tcg_out_ldst(TCGContext *s, RISCVInsn opc, TCGReg data,
657 TCGReg addr, intptr_t offset)
658 {
659 intptr_t imm12 = sextreg(offset, 0, 12);
661 if (offset != imm12) {
662 intptr_t diff = tcg_pcrel_diff(s, (void *)offset);
664 if (addr == TCG_REG_ZERO && diff == (int32_t)diff) {
665 imm12 = sextreg(diff, 0, 12);
666 tcg_out_opc_upper(s, OPC_AUIPC, TCG_REG_TMP2, diff - imm12);
667 } else {
668 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP2, offset - imm12);
669 if (addr != TCG_REG_ZERO) {
670 tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP2, TCG_REG_TMP2, addr);
671 }
672 }
673 addr = TCG_REG_TMP2;
674 }
676 switch (opc) {
677 case OPC_SB:
678 case OPC_SH:
679 case OPC_SW:
680 case OPC_SD:
681 tcg_out_opc_store(s, opc, addr, data, imm12);
682 break;
683 case OPC_LB:
684 case OPC_LBU:
685 case OPC_LH:
686 case OPC_LHU:
687 case OPC_LW:
688 case OPC_LWU:
689 case OPC_LD:
690 tcg_out_opc_imm(s, opc, data, addr, imm12);
691 break;
692 default:
693 g_assert_not_reached();
694 }
695 }
697 static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg,
698 TCGReg arg1, intptr_t arg2)
699 {
700 RISCVInsn insn = type == TCG_TYPE_I32 ? OPC_LW : OPC_LD;
701 tcg_out_ldst(s, insn, arg, arg1, arg2);
702 }
704 static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
705 TCGReg arg1, intptr_t arg2)
706 {
707 RISCVInsn insn = type == TCG_TYPE_I32 ? OPC_SW : OPC_SD;
708 tcg_out_ldst(s, insn, arg, arg1, arg2);
709 }
711 static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
712 TCGReg base, intptr_t ofs)
713 {
714 if (val == 0) {
715 tcg_out_st(s, type, TCG_REG_ZERO, base, ofs);
716 return true;
717 }
718 return false;
719 }
721 static void tcg_out_addsub2(TCGContext *s,
722 TCGReg rl, TCGReg rh,
723 TCGReg al, TCGReg ah,
724 TCGArg bl, TCGArg bh,
725 bool cbl, bool cbh, bool is_sub, bool is32bit)
726 {
727 const RISCVInsn opc_add = is32bit ? OPC_ADDW : OPC_ADD;
728 const RISCVInsn opc_addi = is32bit ? OPC_ADDIW : OPC_ADDI;
729 const RISCVInsn opc_sub = is32bit ? OPC_SUBW : OPC_SUB;
730 TCGReg th = TCG_REG_TMP1;
732 /* If we have a negative constant such that negating it would
733 make the high part zero, we can (usually) eliminate one insn. */
734 if (cbl && cbh && bh == -1 && bl != 0) {
735 bl = -bl;
736 bh = 0;
737 is_sub = !is_sub;
738 }
740 /* By operating on the high part first, we get to use the final
741 carry operation to move back from the temporary. */
742 if (!cbh) {
743 tcg_out_opc_reg(s, (is_sub ? opc_sub : opc_add), th, ah, bh);
744 } else if (bh != 0 || ah == rl) {
745 tcg_out_opc_imm(s, opc_addi, th, ah, (is_sub ? -bh : bh));
746 } else {
747 th = ah;
748 }
750 /* Note that tcg optimization should eliminate the bl == 0 case. */
751 if (is_sub) {
752 if (cbl) {
753 tcg_out_opc_imm(s, OPC_SLTIU, TCG_REG_TMP0, al, bl);
754 tcg_out_opc_imm(s, opc_addi, rl, al, -bl);
755 } else {
756 tcg_out_opc_reg(s, OPC_SLTU, TCG_REG_TMP0, al, bl);
757 tcg_out_opc_reg(s, opc_sub, rl, al, bl);
758 }
759 tcg_out_opc_reg(s, opc_sub, rh, th, TCG_REG_TMP0);
760 } else {
761 if (cbl) {
762 tcg_out_opc_imm(s, opc_addi, rl, al, bl);
763 tcg_out_opc_imm(s, OPC_SLTIU, TCG_REG_TMP0, rl, bl);
764 } else if (al == bl) {
765 /*
766 * If the input regs overlap, this is a simple doubling
767 * and carry-out is the input msb. This special case is
768 * required when the output reg overlaps the input,
769 * but we might as well use it always.
770 */
771 tcg_out_opc_imm(s, OPC_SLTI, TCG_REG_TMP0, al, 0);
772 tcg_out_opc_reg(s, opc_add, rl, al, al);
773 } else {
774 tcg_out_opc_reg(s, opc_add, rl, al, bl);
775 tcg_out_opc_reg(s, OPC_SLTU, TCG_REG_TMP0,
776 rl, (rl == bl ? al : bl));
777 }
778 tcg_out_opc_reg(s, opc_add, rh, th, TCG_REG_TMP0);
779 }
780 }
782 static const struct {
783 RISCVInsn op;
784 bool swap;
785 } tcg_brcond_to_riscv[] = {
786 [TCG_COND_EQ] = { OPC_BEQ, false },
787 [TCG_COND_NE] = { OPC_BNE, false },
788 [TCG_COND_LT] = { OPC_BLT, false },
789 [TCG_COND_GE] = { OPC_BGE, false },
790 [TCG_COND_LE] = { OPC_BGE, true },
791 [TCG_COND_GT] = { OPC_BLT, true },
792 [TCG_COND_LTU] = { OPC_BLTU, false },
793 [TCG_COND_GEU] = { OPC_BGEU, false },
794 [TCG_COND_LEU] = { OPC_BGEU, true },
795 [TCG_COND_GTU] = { OPC_BLTU, true }
796 };
798 static void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGReg arg1,
799 TCGReg arg2, TCGLabel *l)
800 {
801 RISCVInsn op = tcg_brcond_to_riscv[cond].op;
803 tcg_debug_assert(op != 0);
805 if (tcg_brcond_to_riscv[cond].swap) {
806 TCGReg t = arg1;
807 arg1 = arg2;
808 arg2 = t;
809 }
811 tcg_out_reloc(s, s->code_ptr, R_RISCV_BRANCH, l, 0);
812 tcg_out_opc_branch(s, op, arg1, arg2, 0);
813 }
815 #define SETCOND_INV TCG_TARGET_NB_REGS
816 #define SETCOND_NEZ (SETCOND_INV << 1)
817 #define SETCOND_FLAGS (SETCOND_INV | SETCOND_NEZ)
819 static int tcg_out_setcond_int(TCGContext *s, TCGCond cond, TCGReg ret,
820 TCGReg arg1, tcg_target_long arg2, bool c2)
821 {
822 int flags = 0;
824 switch (cond) {
825 case TCG_COND_EQ: /* -> NE */
826 case TCG_COND_GE: /* -> LT */
827 case TCG_COND_GEU: /* -> LTU */
828 case TCG_COND_GT: /* -> LE */
829 case TCG_COND_GTU: /* -> LEU */
830 cond = tcg_invert_cond(cond);
831 flags ^= SETCOND_INV;
832 break;
833 default:
834 break;
835 }
837 switch (cond) {
838 case TCG_COND_LE:
839 case TCG_COND_LEU:
840 /*
841 * If we have a constant input, the most efficient way to implement
842 * LE is by adding 1 and using LT. Watch out for wrap around for LEU.
843 * We don't need to care for this for LE because the constant input
844 * is constrained to signed 12-bit, and 0x800 is representable in the
845 * temporary register.
846 */
847 if (c2) {
848 if (cond == TCG_COND_LEU) {
849 /* unsigned <= -1 is true */
850 if (arg2 == -1) {
851 tcg_out_movi(s, TCG_TYPE_REG, ret, !(flags & SETCOND_INV));
852 return ret;
853 }
854 cond = TCG_COND_LTU;
855 } else {
856 cond = TCG_COND_LT;
857 }
858 tcg_debug_assert(arg2 <= 0x7ff);
859 if (++arg2 == 0x800) {
860 tcg_out_movi(s, TCG_TYPE_REG, TCG_REG_TMP0, arg2);
861 arg2 = TCG_REG_TMP0;
862 c2 = false;
863 }
864 } else {
865 TCGReg tmp = arg2;
866 arg2 = arg1;
867 arg1 = tmp;
868 cond = tcg_swap_cond(cond); /* LE -> GE */
869 cond = tcg_invert_cond(cond); /* GE -> LT */
870 flags ^= SETCOND_INV;
871 }
872 break;
873 default:
874 break;
875 }
877 switch (cond) {
878 case TCG_COND_NE:
879 flags |= SETCOND_NEZ;
880 if (!c2) {
881 tcg_out_opc_reg(s, OPC_XOR, ret, arg1, arg2);
882 } else if (arg2 == 0) {
883 ret = arg1;
884 } else {
885 tcg_out_opc_imm(s, OPC_XORI, ret, arg1, arg2);
886 }
887 break;
889 case TCG_COND_LT:
890 if (c2) {
891 tcg_out_opc_imm(s, OPC_SLTI, ret, arg1, arg2);
892 } else {
893 tcg_out_opc_reg(s, OPC_SLT, ret, arg1, arg2);
894 }
895 break;
897 case TCG_COND_LTU:
898 if (c2) {
899 tcg_out_opc_imm(s, OPC_SLTIU, ret, arg1, arg2);
900 } else {
901 tcg_out_opc_reg(s, OPC_SLTU, ret, arg1, arg2);
902 }
903 break;
905 default:
906 g_assert_not_reached();
907 }
909 return ret | flags;
910 }
912 static void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGReg ret,
913 TCGReg arg1, tcg_target_long arg2, bool c2)
914 {
915 int tmpflags = tcg_out_setcond_int(s, cond, ret, arg1, arg2, c2);
917 if (tmpflags != ret) {
918 TCGReg tmp = tmpflags & ~SETCOND_FLAGS;
920 switch (tmpflags & SETCOND_FLAGS) {
921 case SETCOND_INV:
922 /* Intermediate result is boolean: simply invert. */
923 tcg_out_opc_imm(s, OPC_XORI, ret, tmp, 1);
924 break;
925 case SETCOND_NEZ:
926 /* Intermediate result is zero/non-zero: test != 0. */
927 tcg_out_opc_reg(s, OPC_SLTU, ret, TCG_REG_ZERO, tmp);
928 break;
929 case SETCOND_NEZ | SETCOND_INV:
930 /* Intermediate result is zero/non-zero: test == 0. */
931 tcg_out_opc_imm(s, OPC_SLTIU, ret, tmp, 1);
932 break;
933 default:
934 g_assert_not_reached();
935 }
936 }
937 }
939 static void tcg_out_negsetcond(TCGContext *s, TCGCond cond, TCGReg ret,
940 TCGReg arg1, tcg_target_long arg2, bool c2)
941 {
942 int tmpflags;
943 TCGReg tmp;
945 /* For LT/GE comparison against 0, replicate the sign bit. */
946 if (c2 && arg2 == 0) {
947 switch (cond) {
948 case TCG_COND_GE:
949 tcg_out_opc_imm(s, OPC_XORI, ret, arg1, -1);
950 arg1 = ret;
951 /* fall through */
952 case TCG_COND_LT:
953 tcg_out_opc_imm(s, OPC_SRAI, ret, arg1, TCG_TARGET_REG_BITS - 1);
954 return;
955 default:
956 break;
957 }
958 }
960 tmpflags = tcg_out_setcond_int(s, cond, ret, arg1, arg2, c2);
961 tmp = tmpflags & ~SETCOND_FLAGS;
963 /* If intermediate result is zero/non-zero: test != 0. */
964 if (tmpflags & SETCOND_NEZ) {
965 tcg_out_opc_reg(s, OPC_SLTU, ret, TCG_REG_ZERO, tmp);
966 tmp = ret;
967 }
969 /* Produce the 0/-1 result. */
970 if (tmpflags & SETCOND_INV) {
971 tcg_out_opc_imm(s, OPC_ADDI, ret, tmp, -1);
972 } else {
973 tcg_out_opc_reg(s, OPC_SUB, ret, TCG_REG_ZERO, tmp);
974 }
975 }
977 static void tcg_out_movcond_zicond(TCGContext *s, TCGReg ret, TCGReg test_ne,
978 int val1, bool c_val1,
979 int val2, bool c_val2)
980 {
981 if (val1 == 0) {
982 if (c_val2) {
983 tcg_out_movi(s, TCG_TYPE_REG, TCG_REG_TMP1, val2);
984 val2 = TCG_REG_TMP1;
985 }
986 tcg_out_opc_reg(s, OPC_CZERO_NEZ, ret, val2, test_ne);
987 return;
988 }
990 if (val2 == 0) {
991 if (c_val1) {
992 tcg_out_movi(s, TCG_TYPE_REG, TCG_REG_TMP1, val1);
993 val1 = TCG_REG_TMP1;
994 }
995 tcg_out_opc_reg(s, OPC_CZERO_EQZ, ret, val1, test_ne);
996 return;
997 }
999 if (c_val2) {
1000 if (c_val1) {
1001 tcg_out_movi(s, TCG_TYPE_REG, TCG_REG_TMP1, val1 - val2);
1002 } else {
1003 tcg_out_opc_imm(s, OPC_ADDI, TCG_REG_TMP1, val1, -val2);
1004 }
1005 tcg_out_opc_reg(s, OPC_CZERO_EQZ, ret, TCG_REG_TMP1, test_ne);
1006 tcg_out_opc_imm(s, OPC_ADDI, ret, ret, val2);
1007 return;
1008 }
1010 if (c_val1) {
1011 tcg_out_opc_imm(s, OPC_ADDI, TCG_REG_TMP1, val2, -val1);
1012 tcg_out_opc_reg(s, OPC_CZERO_NEZ, ret, TCG_REG_TMP1, test_ne);
1013 tcg_out_opc_imm(s, OPC_ADDI, ret, ret, val1);
1014 return;
1015 }
1017 tcg_out_opc_reg(s, OPC_CZERO_NEZ, TCG_REG_TMP1, val2, test_ne);
1018 tcg_out_opc_reg(s, OPC_CZERO_EQZ, TCG_REG_TMP0, val1, test_ne);
1019 tcg_out_opc_reg(s, OPC_OR, ret, TCG_REG_TMP0, TCG_REG_TMP1);
1020 }
1022 static void tcg_out_movcond_br1(TCGContext *s, TCGCond cond, TCGReg ret,
1023 TCGReg cmp1, TCGReg cmp2,
1024 int val, bool c_val)
1025 {
1026 RISCVInsn op;
1027 int disp = 8;
1029 tcg_debug_assert((unsigned)cond < ARRAY_SIZE(tcg_brcond_to_riscv));
1030 op = tcg_brcond_to_riscv[cond].op;
1031 tcg_debug_assert(op != 0);
1033 if (tcg_brcond_to_riscv[cond].swap) {
1034 tcg_out_opc_branch(s, op, cmp2, cmp1, disp);
1035 } else {
1036 tcg_out_opc_branch(s, op, cmp1, cmp2, disp);
1037 }
1038 if (c_val) {
1039 tcg_out_opc_imm(s, OPC_ADDI, ret, TCG_REG_ZERO, val);
1040 } else {
1041 tcg_out_opc_imm(s, OPC_ADDI, ret, val, 0);
1042 }
1043 }
1045 static void tcg_out_movcond_br2(TCGContext *s, TCGCond cond, TCGReg ret,
1046 TCGReg cmp1, TCGReg cmp2,
1047 int val1, bool c_val1,
1048 int val2, bool c_val2)
1049 {
1050 TCGReg tmp;
1052 /* TCG optimizer reorders to prefer ret matching val2. */
1053 if (!c_val2 && ret == val2) {
1054 cond = tcg_invert_cond(cond);
1055 tcg_out_movcond_br1(s, cond, ret, cmp1, cmp2, val1, c_val1);
1056 return;
1057 }
1059 if (!c_val1 && ret == val1) {
1060 tcg_out_movcond_br1(s, cond, ret, cmp1, cmp2, val2, c_val2);
1061 return;
1062 }
1064 tmp = (ret == cmp1 || ret == cmp2 ? TCG_REG_TMP1 : ret);
1065 if (c_val1) {
1066 tcg_out_movi(s, TCG_TYPE_REG, tmp, val1);
1067 } else {
1068 tcg_out_mov(s, TCG_TYPE_REG, tmp, val1);
1069 }
1070 tcg_out_movcond_br1(s, cond, tmp, cmp1, cmp2, val2, c_val2);
1071 tcg_out_mov(s, TCG_TYPE_REG, ret, tmp);
1072 }
1074 static void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGReg ret,
1075 TCGReg cmp1, int cmp2, bool c_cmp2,
1076 TCGReg val1, bool c_val1,
1077 TCGReg val2, bool c_val2)
1078 {
1079 int tmpflags;
1080 TCGReg t;
1082 if (!have_zicond && (!c_cmp2 || cmp2 == 0)) {
1083 tcg_out_movcond_br2(s, cond, ret, cmp1, cmp2,
1084 val1, c_val1, val2, c_val2);
1085 return;
1086 }
1088 tmpflags = tcg_out_setcond_int(s, cond, TCG_REG_TMP0, cmp1, cmp2, c_cmp2);
1089 t = tmpflags & ~SETCOND_FLAGS;
1091 if (have_zicond) {
1092 if (tmpflags & SETCOND_INV) {
1093 tcg_out_movcond_zicond(s, ret, t, val2, c_val2, val1, c_val1);
1094 } else {
1095 tcg_out_movcond_zicond(s, ret, t, val1, c_val1, val2, c_val2);
1096 }
1097 } else {
1098 cond = tmpflags & SETCOND_INV ? TCG_COND_EQ : TCG_COND_NE;
1099 tcg_out_movcond_br2(s, cond, ret, t, TCG_REG_ZERO,
1100 val1, c_val1, val2, c_val2);
1101 }
1102 }
1104 static void tcg_out_cltz(TCGContext *s, TCGType type, RISCVInsn insn,
1105 TCGReg ret, TCGReg src1, int src2, bool c_src2)
1106 {
1107 tcg_out_opc_imm(s, insn, ret, src1, 0);
1109 if (!c_src2 || src2 != (type == TCG_TYPE_I32 ? 32 : 64)) {
1110 /*
1111 * The requested zero result does not match the insn, so adjust.
1112 * Note that constraints put 'ret' in a new register, so the
1113 * computation above did not clobber either 'src1' or 'src2'.
1114 */
1115 tcg_out_movcond(s, TCG_COND_EQ, ret, src1, 0, true,
1116 src2, c_src2, ret, false);
1117 }
1118 }
1120 static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *arg, bool tail)
1121 {
1122 TCGReg link = tail ? TCG_REG_ZERO : TCG_REG_RA;
1123 ptrdiff_t offset = tcg_pcrel_diff(s, arg);
1124 int ret;
1126 tcg_debug_assert((offset & 1) == 0);
1127 if (offset == sextreg(offset, 0, 20)) {
1128 /* short jump: -2097150 to 2097152 */
1129 tcg_out_opc_jump(s, OPC_JAL, link, offset);
1130 } else if (offset == (int32_t)offset) {
1131 /* long jump: -2147483646 to 2147483648 */
1132 tcg_out_opc_upper(s, OPC_AUIPC, TCG_REG_TMP0, 0);
1133 tcg_out_opc_imm(s, OPC_JALR, link, TCG_REG_TMP0, 0);
1134 ret = reloc_call(s->code_ptr - 2, arg);
1135 tcg_debug_assert(ret == true);
1136 } else {
1137 /* far jump: 64-bit */
1138 tcg_target_long imm = sextreg((tcg_target_long)arg, 0, 12);
1139 tcg_target_long base = (tcg_target_long)arg - imm;
1140 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP0, base);
1141 tcg_out_opc_imm(s, OPC_JALR, link, TCG_REG_TMP0, imm);
1142 }
1143 }
1145 static void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg,
1146 const TCGHelperInfo *info)
1147 {
1148 tcg_out_call_int(s, arg, false);
1149 }
1151 static void tcg_out_mb(TCGContext *s, TCGArg a0)
1152 {
1153 tcg_insn_unit insn = OPC_FENCE;
1155 if (a0 & TCG_MO_LD_LD) {
1156 insn |= 0x02200000;
1157 }
1158 if (a0 & TCG_MO_ST_LD) {
1159 insn |= 0x01200000;
1160 }
1161 if (a0 & TCG_MO_LD_ST) {
1162 insn |= 0x02100000;
1163 }
1164 if (a0 & TCG_MO_ST_ST) {
1165 insn |= 0x02200000;
1166 }
1167 tcg_out32(s, insn);
1168 }
1170 /*
1171 * Load/store and TLB
1172 */
1174 static void tcg_out_goto(TCGContext *s, const tcg_insn_unit *target)
1175 {
1176 tcg_out_opc_jump(s, OPC_JAL, TCG_REG_ZERO, 0);
1177 bool ok = reloc_jimm20(s->code_ptr - 1, target);
1178 tcg_debug_assert(ok);
1179 }
1181 bool tcg_target_has_memory_bswap(MemOp memop)
1182 {
1183 return false;
1184 }
1186 /* We have three temps, we might as well expose them. */
1187 static const TCGLdstHelperParam ldst_helper_param = {
1188 .ntmp = 3, .tmp = { TCG_REG_TMP0, TCG_REG_TMP1, TCG_REG_TMP2 }
1189 };
1191 static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
1192 {
1193 MemOp opc = get_memop(l->oi);
1195 /* resolve label address */
1196 if (!reloc_sbimm12(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) {
1197 return false;
1198 }
1200 /* call load helper */
1201 tcg_out_ld_helper_args(s, l, &ldst_helper_param);
1202 tcg_out_call_int(s, qemu_ld_helpers[opc & MO_SSIZE], false);
1203 tcg_out_ld_helper_ret(s, l, true, &ldst_helper_param);
1205 tcg_out_goto(s, l->raddr);
1206 return true;
1207 }
1209 static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
1210 {
1211 MemOp opc = get_memop(l->oi);
1213 /* resolve label address */
1214 if (!reloc_sbimm12(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) {
1215 return false;
1216 }
1218 /* call store helper */
1219 tcg_out_st_helper_args(s, l, &ldst_helper_param);
1220 tcg_out_call_int(s, qemu_st_helpers[opc & MO_SIZE], false);
1222 tcg_out_goto(s, l->raddr);
1223 return true;
1224 }
1226 /* We expect to use a 12-bit negative offset from ENV. */
1227 #define MIN_TLB_MASK_TABLE_OFS -(1 << 11)
1229 /*
1230 * For system-mode, perform the TLB load and compare.
1231 * For user-mode, perform any required alignment tests.
1232 * In both cases, return a TCGLabelQemuLdst structure if the slow path
1233 * is required and fill in @h with the host address for the fast path.
1234 */
1235 static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, TCGReg *pbase,
1236 TCGReg addr_reg, MemOpIdx oi,
1237 bool is_ld)
1238 {
1239 TCGType addr_type = s->addr_type;
1240 TCGLabelQemuLdst *ldst = NULL;
1241 MemOp opc = get_memop(oi);
1242 TCGAtomAlign aa;
1243 unsigned a_mask;
1245 aa = atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, false);
1246 a_mask = (1u << aa.align) - 1;
1248 #ifdef CONFIG_SOFTMMU
1249 unsigned s_bits = opc & MO_SIZE;
1250 unsigned s_mask = (1u << s_bits) - 1;
1251 int mem_index = get_mmuidx(oi);
1252 int fast_ofs = tlb_mask_table_ofs(s, mem_index);
1253 int mask_ofs = fast_ofs + offsetof(CPUTLBDescFast, mask);
1254 int table_ofs = fast_ofs + offsetof(CPUTLBDescFast, table);
1255 int compare_mask;
1256 TCGReg addr_adj;
1258 ldst = new_ldst_label(s);
1259 ldst->is_ld = is_ld;
1260 ldst->oi = oi;
1261 ldst->addrlo_reg = addr_reg;
1263 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, TCG_AREG0, mask_ofs);
1264 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_AREG0, table_ofs);
1266 tcg_out_opc_imm(s, OPC_SRLI, TCG_REG_TMP2, addr_reg,
1267 s->page_bits - CPU_TLB_ENTRY_BITS);
1268 tcg_out_opc_reg(s, OPC_AND, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP0);
1269 tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP1);
1271 /*
1272 * For aligned accesses, we check the first byte and include the alignment
1273 * bits within the address. For unaligned access, we check that we don't
1274 * cross pages using the address of the last byte of the access.
1275 */
1276 addr_adj = addr_reg;
1277 if (a_mask < s_mask) {
1278 addr_adj = TCG_REG_TMP0;
1279 tcg_out_opc_imm(s, addr_type == TCG_TYPE_I32 ? OPC_ADDIW : OPC_ADDI,
1280 addr_adj, addr_reg, s_mask - a_mask);
1281 }
1282 compare_mask = s->page_mask | a_mask;
1283 if (compare_mask == sextreg(compare_mask, 0, 12)) {
1284 tcg_out_opc_imm(s, OPC_ANDI, TCG_REG_TMP1, addr_adj, compare_mask);
1285 } else {
1286 tcg_out_movi(s, addr_type, TCG_REG_TMP1, compare_mask);
1287 tcg_out_opc_reg(s, OPC_AND, TCG_REG_TMP1, TCG_REG_TMP1, addr_adj);
1288 }
1290 /* Load the tlb comparator and the addend. */
1291 QEMU_BUILD_BUG_ON(HOST_BIG_ENDIAN);
1292 tcg_out_ld(s, addr_type, TCG_REG_TMP0, TCG_REG_TMP2,
1293 is_ld ? offsetof(CPUTLBEntry, addr_read)
1294 : offsetof(CPUTLBEntry, addr_write));
1295 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP2, TCG_REG_TMP2,
1296 offsetof(CPUTLBEntry, addend));
1298 /* Compare masked address with the TLB entry. */
1299 ldst->label_ptr[0] = s->code_ptr;
1300 tcg_out_opc_branch(s, OPC_BNE, TCG_REG_TMP0, TCG_REG_TMP1, 0);
1302 /* TLB Hit - translate address using addend. */
1303 if (addr_type != TCG_TYPE_I32) {
1304 tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, addr_reg, TCG_REG_TMP2);
1305 } else if (have_zba) {
1306 tcg_out_opc_reg(s, OPC_ADD_UW, TCG_REG_TMP0, addr_reg, TCG_REG_TMP2);
1307 } else {
1308 tcg_out_ext32u(s, TCG_REG_TMP0, addr_reg);
1309 tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_REG_TMP0, TCG_REG_TMP2);
1310 }
1311 *pbase = TCG_REG_TMP0;
1312 #else
1313 TCGReg base;
1315 if (a_mask) {
1316 ldst = new_ldst_label(s);
1317 ldst->is_ld = is_ld;
1318 ldst->oi = oi;
1319 ldst->addrlo_reg = addr_reg;
1321 /* We are expecting alignment max 7, so we can always use andi. */
1322 tcg_debug_assert(a_mask == sextreg(a_mask, 0, 12));
1323 tcg_out_opc_imm(s, OPC_ANDI, TCG_REG_TMP1, addr_reg, a_mask);
1325 ldst->label_ptr[0] = s->code_ptr;
1326 tcg_out_opc_branch(s, OPC_BNE, TCG_REG_TMP1, TCG_REG_ZERO, 0);
1327 }
1329 if (guest_base != 0) {
1330 base = TCG_REG_TMP0;
1331 if (addr_type != TCG_TYPE_I32) {
1332 tcg_out_opc_reg(s, OPC_ADD, base, addr_reg, TCG_GUEST_BASE_REG);
1333 } else if (have_zba) {
1334 tcg_out_opc_reg(s, OPC_ADD_UW, base, addr_reg, TCG_GUEST_BASE_REG);
1335 } else {
1336 tcg_out_ext32u(s, base, addr_reg);
1337 tcg_out_opc_reg(s, OPC_ADD, base, base, TCG_GUEST_BASE_REG);
1338 }
1339 } else if (addr_type != TCG_TYPE_I32) {
1340 base = addr_reg;
1341 } else {
1342 base = TCG_REG_TMP0;
1343 tcg_out_ext32u(s, base, addr_reg);
1344 }
1345 *pbase = base;
1346 #endif
1348 return ldst;
1349 }
1351 static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg val,
1352 TCGReg base, MemOp opc, TCGType type)
1353 {
1354 /* Byte swapping is left to middle-end expansion. */
1355 tcg_debug_assert((opc & MO_BSWAP) == 0);
1357 switch (opc & (MO_SSIZE)) {
1358 case MO_UB:
1359 tcg_out_opc_imm(s, OPC_LBU, val, base, 0);
1360 break;
1361 case MO_SB:
1362 tcg_out_opc_imm(s, OPC_LB, val, base, 0);
1363 break;
1364 case MO_UW:
1365 tcg_out_opc_imm(s, OPC_LHU, val, base, 0);
1366 break;
1367 case MO_SW:
1368 tcg_out_opc_imm(s, OPC_LH, val, base, 0);
1369 break;
1370 case MO_UL:
1371 if (type == TCG_TYPE_I64) {
1372 tcg_out_opc_imm(s, OPC_LWU, val, base, 0);
1373 break;
1374 }
1375 /* FALLTHRU */
1376 case MO_SL:
1377 tcg_out_opc_imm(s, OPC_LW, val, base, 0);
1378 break;
1379 case MO_UQ:
1380 tcg_out_opc_imm(s, OPC_LD, val, base, 0);
1381 break;
1382 default:
1383 g_assert_not_reached();
1384 }
1385 }
1387 static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
1388 MemOpIdx oi, TCGType data_type)
1389 {
1390 TCGLabelQemuLdst *ldst;
1391 TCGReg base;
1393 ldst = prepare_host_addr(s, &base, addr_reg, oi, true);
1394 tcg_out_qemu_ld_direct(s, data_reg, base, get_memop(oi), data_type);
1396 if (ldst) {
1397 ldst->type = data_type;
1398 ldst->datalo_reg = data_reg;
1399 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr);
1400 }
1401 }
1403 static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg val,
1404 TCGReg base, MemOp opc)
1405 {
1406 /* Byte swapping is left to middle-end expansion. */
1407 tcg_debug_assert((opc & MO_BSWAP) == 0);
1409 switch (opc & (MO_SSIZE)) {
1410 case MO_8:
1411 tcg_out_opc_store(s, OPC_SB, base, val, 0);
1412 break;
1413 case MO_16:
1414 tcg_out_opc_store(s, OPC_SH, base, val, 0);
1415 break;
1416 case MO_32:
1417 tcg_out_opc_store(s, OPC_SW, base, val, 0);
1418 break;
1419 case MO_64:
1420 tcg_out_opc_store(s, OPC_SD, base, val, 0);
1421 break;
1422 default:
1423 g_assert_not_reached();
1424 }
1425 }
1427 static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
1428 MemOpIdx oi, TCGType data_type)
1429 {
1430 TCGLabelQemuLdst *ldst;
1431 TCGReg base;
1433 ldst = prepare_host_addr(s, &base, addr_reg, oi, false);
1434 tcg_out_qemu_st_direct(s, data_reg, base, get_memop(oi));
1436 if (ldst) {
1437 ldst->type = data_type;
1438 ldst->datalo_reg = data_reg;
1439 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr);
1440 }
1441 }
1443 static const tcg_insn_unit *tb_ret_addr;
1445 static void tcg_out_exit_tb(TCGContext *s, uintptr_t a0)
1446 {
1447 /* Reuse the zeroing that exists for goto_ptr. */
1448 if (a0 == 0) {
1449 tcg_out_call_int(s, tcg_code_gen_epilogue, true);
1450 } else {
1451 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_A0, a0);
1452 tcg_out_call_int(s, tb_ret_addr, true);
1453 }
1454 }
1456 static void tcg_out_goto_tb(TCGContext *s, int which)
1457 {
1458 /* Direct branch will be patched by tb_target_set_jmp_target. */
1459 set_jmp_insn_offset(s, which);
1460 tcg_out32(s, OPC_JAL);
1462 /* When branch is out of range, fall through to indirect. */
1463 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, TCG_REG_ZERO,
1464 get_jmp_target_addr(s, which));
1465 tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, TCG_REG_TMP0, 0);
1466 set_jmp_reset_offset(s, which);
1467 }
1469 void tb_target_set_jmp_target(const TranslationBlock *tb, int n,
1470 uintptr_t jmp_rx, uintptr_t jmp_rw)
1471 {
1472 uintptr_t addr = tb->jmp_target_addr[n];
1473 ptrdiff_t offset = addr - jmp_rx;
1474 tcg_insn_unit insn;
1476 /* Either directly branch, or fall through to indirect branch. */
1477 if (offset == sextreg(offset, 0, 20)) {
1478 insn = encode_uj(OPC_JAL, TCG_REG_ZERO, offset);
1479 } else {
1480 insn = OPC_NOP;
1481 }
1482 qatomic_set((uint32_t *)jmp_rw, insn);
1483 flush_idcache_range(jmp_rx, jmp_rw, 4);
1484 }
1486 static void tcg_out_op(TCGContext *s, TCGOpcode opc,
1487 const TCGArg args[TCG_MAX_OP_ARGS],
1488 const int const_args[TCG_MAX_OP_ARGS])
1489 {
1490 TCGArg a0 = args[0];
1491 TCGArg a1 = args[1];
1492 TCGArg a2 = args[2];
1493 int c2 = const_args[2];
1495 switch (opc) {
1496 case INDEX_op_goto_ptr:
1497 tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, a0, 0);
1498 break;
1500 case INDEX_op_br:
1501 tcg_out_reloc(s, s->code_ptr, R_RISCV_JAL, arg_label(a0), 0);
1502 tcg_out_opc_jump(s, OPC_JAL, TCG_REG_ZERO, 0);
1503 break;
1505 case INDEX_op_ld8u_i32:
1506 case INDEX_op_ld8u_i64:
1507 tcg_out_ldst(s, OPC_LBU, a0, a1, a2);
1508 break;
1509 case INDEX_op_ld8s_i32:
1510 case INDEX_op_ld8s_i64:
1511 tcg_out_ldst(s, OPC_LB, a0, a1, a2);
1512 break;
1513 case INDEX_op_ld16u_i32:
1514 case INDEX_op_ld16u_i64:
1515 tcg_out_ldst(s, OPC_LHU, a0, a1, a2);
1516 break;
1517 case INDEX_op_ld16s_i32:
1518 case INDEX_op_ld16s_i64:
1519 tcg_out_ldst(s, OPC_LH, a0, a1, a2);
1520 break;
1521 case INDEX_op_ld32u_i64:
1522 tcg_out_ldst(s, OPC_LWU, a0, a1, a2);
1523 break;
1524 case INDEX_op_ld_i32:
1525 case INDEX_op_ld32s_i64:
1526 tcg_out_ldst(s, OPC_LW, a0, a1, a2);
1527 break;
1528 case INDEX_op_ld_i64:
1529 tcg_out_ldst(s, OPC_LD, a0, a1, a2);
1530 break;
1532 case INDEX_op_st8_i32:
1533 case INDEX_op_st8_i64:
1534 tcg_out_ldst(s, OPC_SB, a0, a1, a2);
1535 break;
1536 case INDEX_op_st16_i32:
1537 case INDEX_op_st16_i64:
1538 tcg_out_ldst(s, OPC_SH, a0, a1, a2);
1539 break;
1540 case INDEX_op_st_i32:
1541 case INDEX_op_st32_i64:
1542 tcg_out_ldst(s, OPC_SW, a0, a1, a2);
1543 break;
1544 case INDEX_op_st_i64:
1545 tcg_out_ldst(s, OPC_SD, a0, a1, a2);
1546 break;
1548 case INDEX_op_add_i32:
1549 if (c2) {
1550 tcg_out_opc_imm(s, OPC_ADDIW, a0, a1, a2);
1551 } else {
1552 tcg_out_opc_reg(s, OPC_ADDW, a0, a1, a2);
1553 }
1554 break;
1555 case INDEX_op_add_i64:
1556 if (c2) {
1557 tcg_out_opc_imm(s, OPC_ADDI, a0, a1, a2);
1558 } else {
1559 tcg_out_opc_reg(s, OPC_ADD, a0, a1, a2);
1560 }
1561 break;
1563 case INDEX_op_sub_i32:
1564 if (c2) {
1565 tcg_out_opc_imm(s, OPC_ADDIW, a0, a1, -a2);
1566 } else {
1567 tcg_out_opc_reg(s, OPC_SUBW, a0, a1, a2);
1568 }
1569 break;
1570 case INDEX_op_sub_i64:
1571 if (c2) {
1572 tcg_out_opc_imm(s, OPC_ADDI, a0, a1, -a2);
1573 } else {
1574 tcg_out_opc_reg(s, OPC_SUB, a0, a1, a2);
1575 }
1576 break;
1578 case INDEX_op_and_i32:
1579 case INDEX_op_and_i64:
1580 if (c2) {
1581 tcg_out_opc_imm(s, OPC_ANDI, a0, a1, a2);
1582 } else {
1583 tcg_out_opc_reg(s, OPC_AND, a0, a1, a2);
1584 }
1585 break;
1587 case INDEX_op_or_i32:
1588 case INDEX_op_or_i64:
1589 if (c2) {
1590 tcg_out_opc_imm(s, OPC_ORI, a0, a1, a2);
1591 } else {
1592 tcg_out_opc_reg(s, OPC_OR, a0, a1, a2);
1593 }
1594 break;
1596 case INDEX_op_xor_i32:
1597 case INDEX_op_xor_i64:
1598 if (c2) {
1599 tcg_out_opc_imm(s, OPC_XORI, a0, a1, a2);
1600 } else {
1601 tcg_out_opc_reg(s, OPC_XOR, a0, a1, a2);
1602 }
1603 break;
1605 case INDEX_op_andc_i32:
1606 case INDEX_op_andc_i64:
1607 if (c2) {
1608 tcg_out_opc_imm(s, OPC_ANDI, a0, a1, ~a2);
1609 } else {
1610 tcg_out_opc_reg(s, OPC_ANDN, a0, a1, a2);
1611 }
1612 break;
1613 case INDEX_op_orc_i32:
1614 case INDEX_op_orc_i64:
1615 if (c2) {
1616 tcg_out_opc_imm(s, OPC_ORI, a0, a1, ~a2);
1617 } else {
1618 tcg_out_opc_reg(s, OPC_ORN, a0, a1, a2);
1619 }
1620 break;
1621 case INDEX_op_eqv_i32:
1622 case INDEX_op_eqv_i64:
1623 if (c2) {
1624 tcg_out_opc_imm(s, OPC_XORI, a0, a1, ~a2);
1625 } else {
1626 tcg_out_opc_reg(s, OPC_XNOR, a0, a1, a2);
1627 }
1628 break;
1630 case INDEX_op_not_i32:
1631 case INDEX_op_not_i64:
1632 tcg_out_opc_imm(s, OPC_XORI, a0, a1, -1);
1633 break;
1635 case INDEX_op_neg_i32:
1636 tcg_out_opc_reg(s, OPC_SUBW, a0, TCG_REG_ZERO, a1);
1637 break;
1638 case INDEX_op_neg_i64:
1639 tcg_out_opc_reg(s, OPC_SUB, a0, TCG_REG_ZERO, a1);
1640 break;
1642 case INDEX_op_mul_i32:
1643 tcg_out_opc_reg(s, OPC_MULW, a0, a1, a2);
1644 break;
1645 case INDEX_op_mul_i64:
1646 tcg_out_opc_reg(s, OPC_MUL, a0, a1, a2);
1647 break;
1649 case INDEX_op_div_i32:
1650 tcg_out_opc_reg(s, OPC_DIVW, a0, a1, a2);
1651 break;
1652 case INDEX_op_div_i64:
1653 tcg_out_opc_reg(s, OPC_DIV, a0, a1, a2);
1654 break;
1656 case INDEX_op_divu_i32:
1657 tcg_out_opc_reg(s, OPC_DIVUW, a0, a1, a2);
1658 break;
1659 case INDEX_op_divu_i64:
1660 tcg_out_opc_reg(s, OPC_DIVU, a0, a1, a2);
1661 break;
1663 case INDEX_op_rem_i32:
1664 tcg_out_opc_reg(s, OPC_REMW, a0, a1, a2);
1665 break;
1666 case INDEX_op_rem_i64:
1667 tcg_out_opc_reg(s, OPC_REM, a0, a1, a2);
1668 break;
1670 case INDEX_op_remu_i32:
1671 tcg_out_opc_reg(s, OPC_REMUW, a0, a1, a2);
1672 break;
1673 case INDEX_op_remu_i64:
1674 tcg_out_opc_reg(s, OPC_REMU, a0, a1, a2);
1675 break;
1677 case INDEX_op_shl_i32:
1678 if (c2) {
1679 tcg_out_opc_imm(s, OPC_SLLIW, a0, a1, a2 & 0x1f);
1680 } else {
1681 tcg_out_opc_reg(s, OPC_SLLW, a0, a1, a2);
1682 }
1683 break;
1684 case INDEX_op_shl_i64:
1685 if (c2) {
1686 tcg_out_opc_imm(s, OPC_SLLI, a0, a1, a2 & 0x3f);
1687 } else {
1688 tcg_out_opc_reg(s, OPC_SLL, a0, a1, a2);
1689 }
1690 break;
1692 case INDEX_op_shr_i32:
1693 if (c2) {
1694 tcg_out_opc_imm(s, OPC_SRLIW, a0, a1, a2 & 0x1f);
1695 } else {
1696 tcg_out_opc_reg(s, OPC_SRLW, a0, a1, a2);
1697 }
1698 break;
1699 case INDEX_op_shr_i64:
1700 if (c2) {
1701 tcg_out_opc_imm(s, OPC_SRLI, a0, a1, a2 & 0x3f);
1702 } else {
1703 tcg_out_opc_reg(s, OPC_SRL, a0, a1, a2);
1704 }
1705 break;
1707 case INDEX_op_sar_i32:
1708 if (c2) {
1709 tcg_out_opc_imm(s, OPC_SRAIW, a0, a1, a2 & 0x1f);
1710 } else {
1711 tcg_out_opc_reg(s, OPC_SRAW, a0, a1, a2);
1712 }
1713 break;
1714 case INDEX_op_sar_i64:
1715 if (c2) {
1716 tcg_out_opc_imm(s, OPC_SRAI, a0, a1, a2 & 0x3f);
1717 } else {
1718 tcg_out_opc_reg(s, OPC_SRA, a0, a1, a2);
1719 }
1720 break;
1722 case INDEX_op_rotl_i32:
1723 if (c2) {
1724 tcg_out_opc_imm(s, OPC_RORIW, a0, a1, -a2 & 0x1f);
1725 } else {
1726 tcg_out_opc_reg(s, OPC_ROLW, a0, a1, a2);
1727 }
1728 break;
1729 case INDEX_op_rotl_i64:
1730 if (c2) {
1731 tcg_out_opc_imm(s, OPC_RORI, a0, a1, -a2 & 0x3f);
1732 } else {
1733 tcg_out_opc_reg(s, OPC_ROL, a0, a1, a2);
1734 }
1735 break;
1737 case INDEX_op_rotr_i32:
1738 if (c2) {
1739 tcg_out_opc_imm(s, OPC_RORIW, a0, a1, a2 & 0x1f);
1740 } else {
1741 tcg_out_opc_reg(s, OPC_RORW, a0, a1, a2);
1742 }
1743 break;
1744 case INDEX_op_rotr_i64:
1745 if (c2) {
1746 tcg_out_opc_imm(s, OPC_RORI, a0, a1, a2 & 0x3f);
1747 } else {
1748 tcg_out_opc_reg(s, OPC_ROR, a0, a1, a2);
1749 }
1750 break;
1752 case INDEX_op_bswap64_i64:
1753 tcg_out_opc_imm(s, OPC_REV8, a0, a1, 0);
1754 break;
1755 case INDEX_op_bswap32_i32:
1756 a2 = 0;
1757 /* fall through */
1758 case INDEX_op_bswap32_i64:
1759 tcg_out_opc_imm(s, OPC_REV8, a0, a1, 0);
1760 if (a2 & TCG_BSWAP_OZ) {
1761 tcg_out_opc_imm(s, OPC_SRLI, a0, a0, 32);
1762 } else {
1763 tcg_out_opc_imm(s, OPC_SRAI, a0, a0, 32);
1764 }
1765 break;
1766 case INDEX_op_bswap16_i64:
1767 case INDEX_op_bswap16_i32:
1768 tcg_out_opc_imm(s, OPC_REV8, a0, a1, 0);
1769 if (a2 & TCG_BSWAP_OZ) {
1770 tcg_out_opc_imm(s, OPC_SRLI, a0, a0, 48);
1771 } else {
1772 tcg_out_opc_imm(s, OPC_SRAI, a0, a0, 48);
1773 }
1774 break;
1776 case INDEX_op_ctpop_i32:
1777 tcg_out_opc_imm(s, OPC_CPOPW, a0, a1, 0);
1778 break;
1779 case INDEX_op_ctpop_i64:
1780 tcg_out_opc_imm(s, OPC_CPOP, a0, a1, 0);
1781 break;
1783 case INDEX_op_clz_i32:
1784 tcg_out_cltz(s, TCG_TYPE_I32, OPC_CLZW, a0, a1, a2, c2);
1785 break;
1786 case INDEX_op_clz_i64:
1787 tcg_out_cltz(s, TCG_TYPE_I64, OPC_CLZ, a0, a1, a2, c2);
1788 break;
1789 case INDEX_op_ctz_i32:
1790 tcg_out_cltz(s, TCG_TYPE_I32, OPC_CTZW, a0, a1, a2, c2);
1791 break;
1792 case INDEX_op_ctz_i64:
1793 tcg_out_cltz(s, TCG_TYPE_I64, OPC_CTZ, a0, a1, a2, c2);
1794 break;
1796 case INDEX_op_add2_i32:
1797 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5],
1798 const_args[4], const_args[5], false, true);
1799 break;
1800 case INDEX_op_add2_i64:
1801 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5],
1802 const_args[4], const_args[5], false, false);
1803 break;
1804 case INDEX_op_sub2_i32:
1805 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5],
1806 const_args[4], const_args[5], true, true);
1807 break;
1808 case INDEX_op_sub2_i64:
1809 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5],
1810 const_args[4], const_args[5], true, false);
1811 break;
1813 case INDEX_op_brcond_i32:
1814 case INDEX_op_brcond_i64:
1815 tcg_out_brcond(s, a2, a0, a1, arg_label(args[3]));
1816 break;
1818 case INDEX_op_setcond_i32:
1819 case INDEX_op_setcond_i64:
1820 tcg_out_setcond(s, args[3], a0, a1, a2, c2);
1821 break;
1823 case INDEX_op_negsetcond_i32:
1824 case INDEX_op_negsetcond_i64:
1825 tcg_out_negsetcond(s, args[3], a0, a1, a2, c2);
1826 break;
1828 case INDEX_op_movcond_i32:
1829 case INDEX_op_movcond_i64:
1830 tcg_out_movcond(s, args[5], a0, a1, a2, c2,
1831 args[3], const_args[3], args[4], const_args[4]);
1832 break;
1834 case INDEX_op_qemu_ld_a32_i32:
1835 case INDEX_op_qemu_ld_a64_i32:
1836 tcg_out_qemu_ld(s, a0, a1, a2, TCG_TYPE_I32);
1837 break;
1838 case INDEX_op_qemu_ld_a32_i64:
1839 case INDEX_op_qemu_ld_a64_i64:
1840 tcg_out_qemu_ld(s, a0, a1, a2, TCG_TYPE_I64);
1841 break;
1842 case INDEX_op_qemu_st_a32_i32:
1843 case INDEX_op_qemu_st_a64_i32:
1844 tcg_out_qemu_st(s, a0, a1, a2, TCG_TYPE_I32);
1845 break;
1846 case INDEX_op_qemu_st_a32_i64:
1847 case INDEX_op_qemu_st_a64_i64:
1848 tcg_out_qemu_st(s, a0, a1, a2, TCG_TYPE_I64);
1849 break;
1851 case INDEX_op_extrh_i64_i32:
1852 tcg_out_opc_imm(s, OPC_SRAI, a0, a1, 32);
1853 break;
1855 case INDEX_op_mulsh_i32:
1856 case INDEX_op_mulsh_i64:
1857 tcg_out_opc_reg(s, OPC_MULH, a0, a1, a2);
1858 break;
1860 case INDEX_op_muluh_i32:
1861 case INDEX_op_muluh_i64:
1862 tcg_out_opc_reg(s, OPC_MULHU, a0, a1, a2);
1863 break;
1865 case INDEX_op_mb:
1866 tcg_out_mb(s, a0);
1867 break;
1869 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
1870 case INDEX_op_mov_i64:
1871 case INDEX_op_call: /* Always emitted via tcg_out_call. */
1872 case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */
1873 case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */
1874 case INDEX_op_ext8s_i32: /* Always emitted via tcg_reg_alloc_op. */
1875 case INDEX_op_ext8s_i64:
1876 case INDEX_op_ext8u_i32:
1877 case INDEX_op_ext8u_i64:
1878 case INDEX_op_ext16s_i32:
1879 case INDEX_op_ext16s_i64:
1880 case INDEX_op_ext16u_i32:
1881 case INDEX_op_ext16u_i64:
1882 case INDEX_op_ext32s_i64:
1883 case INDEX_op_ext32u_i64:
1884 case INDEX_op_ext_i32_i64:
1885 case INDEX_op_extu_i32_i64:
1886 case INDEX_op_extrl_i64_i32:
1887 default:
1888 g_assert_not_reached();
1889 }
1890 }
1892 static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
1893 {
1894 switch (op) {
1895 case INDEX_op_goto_ptr:
1896 return C_O0_I1(r);
1898 case INDEX_op_ld8u_i32:
1899 case INDEX_op_ld8s_i32:
1900 case INDEX_op_ld16u_i32:
1901 case INDEX_op_ld16s_i32:
1902 case INDEX_op_ld_i32:
1903 case INDEX_op_not_i32:
1904 case INDEX_op_neg_i32:
1905 case INDEX_op_ld8u_i64:
1906 case INDEX_op_ld8s_i64:
1907 case INDEX_op_ld16u_i64:
1908 case INDEX_op_ld16s_i64:
1909 case INDEX_op_ld32s_i64:
1910 case INDEX_op_ld32u_i64:
1911 case INDEX_op_ld_i64:
1912 case INDEX_op_not_i64:
1913 case INDEX_op_neg_i64:
1914 case INDEX_op_ext8u_i32:
1915 case INDEX_op_ext8u_i64:
1916 case INDEX_op_ext16u_i32:
1917 case INDEX_op_ext16u_i64:
1918 case INDEX_op_ext32u_i64:
1919 case INDEX_op_extu_i32_i64:
1920 case INDEX_op_ext8s_i32:
1921 case INDEX_op_ext8s_i64:
1922 case INDEX_op_ext16s_i32:
1923 case INDEX_op_ext16s_i64:
1924 case INDEX_op_ext32s_i64:
1925 case INDEX_op_extrl_i64_i32:
1926 case INDEX_op_extrh_i64_i32:
1927 case INDEX_op_ext_i32_i64:
1928 case INDEX_op_bswap16_i32:
1929 case INDEX_op_bswap32_i32:
1930 case INDEX_op_bswap16_i64:
1931 case INDEX_op_bswap32_i64:
1932 case INDEX_op_bswap64_i64:
1933 case INDEX_op_ctpop_i32:
1934 case INDEX_op_ctpop_i64:
1935 return C_O1_I1(r, r);
1937 case INDEX_op_st8_i32:
1938 case INDEX_op_st16_i32:
1939 case INDEX_op_st_i32:
1940 case INDEX_op_st8_i64:
1941 case INDEX_op_st16_i64:
1942 case INDEX_op_st32_i64:
1943 case INDEX_op_st_i64:
1944 return C_O0_I2(rZ, r);
1946 case INDEX_op_add_i32:
1947 case INDEX_op_and_i32:
1948 case INDEX_op_or_i32:
1949 case INDEX_op_xor_i32:
1950 case INDEX_op_add_i64:
1951 case INDEX_op_and_i64:
1952 case INDEX_op_or_i64:
1953 case INDEX_op_xor_i64:
1954 case INDEX_op_setcond_i32:
1955 case INDEX_op_setcond_i64:
1956 case INDEX_op_negsetcond_i32:
1957 case INDEX_op_negsetcond_i64:
1958 return C_O1_I2(r, r, rI);
1960 case INDEX_op_andc_i32:
1961 case INDEX_op_andc_i64:
1962 case INDEX_op_orc_i32:
1963 case INDEX_op_orc_i64:
1964 case INDEX_op_eqv_i32:
1965 case INDEX_op_eqv_i64:
1966 return C_O1_I2(r, r, rJ);
1968 case INDEX_op_sub_i32:
1969 case INDEX_op_sub_i64:
1970 return C_O1_I2(r, rZ, rN);
1972 case INDEX_op_mul_i32:
1973 case INDEX_op_mulsh_i32:
1974 case INDEX_op_muluh_i32:
1975 case INDEX_op_div_i32:
1976 case INDEX_op_divu_i32:
1977 case INDEX_op_rem_i32:
1978 case INDEX_op_remu_i32:
1979 case INDEX_op_mul_i64:
1980 case INDEX_op_mulsh_i64:
1981 case INDEX_op_muluh_i64:
1982 case INDEX_op_div_i64:
1983 case INDEX_op_divu_i64:
1984 case INDEX_op_rem_i64:
1985 case INDEX_op_remu_i64:
1986 return C_O1_I2(r, rZ, rZ);
1988 case INDEX_op_shl_i32:
1989 case INDEX_op_shr_i32:
1990 case INDEX_op_sar_i32:
1991 case INDEX_op_rotl_i32:
1992 case INDEX_op_rotr_i32:
1993 case INDEX_op_shl_i64:
1994 case INDEX_op_shr_i64:
1995 case INDEX_op_sar_i64:
1996 case INDEX_op_rotl_i64:
1997 case INDEX_op_rotr_i64:
1998 return C_O1_I2(r, r, ri);
2000 case INDEX_op_clz_i32:
2001 case INDEX_op_clz_i64:
2002 case INDEX_op_ctz_i32:
2003 case INDEX_op_ctz_i64:
2004 return C_N1_I2(r, r, rM);
2006 case INDEX_op_brcond_i32:
2007 case INDEX_op_brcond_i64:
2008 return C_O0_I2(rZ, rZ);
2010 case INDEX_op_movcond_i32:
2011 case INDEX_op_movcond_i64:
2012 return C_O1_I4(r, r, rI, rM, rM);
2014 case INDEX_op_add2_i32:
2015 case INDEX_op_add2_i64:
2016 case INDEX_op_sub2_i32:
2017 case INDEX_op_sub2_i64:
2018 return C_O2_I4(r, r, rZ, rZ, rM, rM);
2020 case INDEX_op_qemu_ld_a32_i32:
2021 case INDEX_op_qemu_ld_a64_i32:
2022 case INDEX_op_qemu_ld_a32_i64:
2023 case INDEX_op_qemu_ld_a64_i64:
2024 return C_O1_I1(r, r);
2025 case INDEX_op_qemu_st_a32_i32:
2026 case INDEX_op_qemu_st_a64_i32:
2027 case INDEX_op_qemu_st_a32_i64:
2028 case INDEX_op_qemu_st_a64_i64:
2029 return C_O0_I2(rZ, r);
2031 default:
2032 g_assert_not_reached();
2033 }
2034 }
2036 static const int tcg_target_callee_save_regs[] = {
2037 TCG_REG_S0, /* used for the global env (TCG_AREG0) */
2038 TCG_REG_S1,
2039 TCG_REG_S2,
2040 TCG_REG_S3,
2041 TCG_REG_S4,
2042 TCG_REG_S5,
2043 TCG_REG_S6,
2044 TCG_REG_S7,
2045 TCG_REG_S8,
2046 TCG_REG_S9,
2047 TCG_REG_S10,
2048 TCG_REG_S11,
2049 TCG_REG_RA, /* should be last for ABI compliance */
2050 };
2052 /* Stack frame parameters. */
2053 #define REG_SIZE (TCG_TARGET_REG_BITS / 8)
2054 #define SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * REG_SIZE)
2055 #define TEMP_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long))
2056 #define FRAME_SIZE ((TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE + SAVE_SIZE \
2057 + TCG_TARGET_STACK_ALIGN - 1) \
2058 & -TCG_TARGET_STACK_ALIGN)
2059 #define SAVE_OFS (TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE)
2061 /* We're expecting to be able to use an immediate for frame allocation. */
2062 QEMU_BUILD_BUG_ON(FRAME_SIZE > 0x7ff);
2064 /* Generate global QEMU prologue and epilogue code */
2065 static void tcg_target_qemu_prologue(TCGContext *s)
2066 {
2067 int i;
2069 tcg_set_frame(s, TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE, TEMP_SIZE);
2071 /* TB prologue */
2072 tcg_out_opc_imm(s, OPC_ADDI, TCG_REG_SP, TCG_REG_SP, -FRAME_SIZE);
2073 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
2074 tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
2075 TCG_REG_SP, SAVE_OFS + i * REG_SIZE);
2076 }
2078 #if !defined(CONFIG_SOFTMMU)
2079 tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base);
2080 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
2081 #endif
2083 /* Call generated code */
2084 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
2085 tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, tcg_target_call_iarg_regs[1], 0);
2087 /* Return path for goto_ptr. Set return value to 0 */
2088 tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr);
2089 tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_A0, TCG_REG_ZERO);
2091 /* TB epilogue */
2092 tb_ret_addr = tcg_splitwx_to_rx(s->code_ptr);
2093 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
2094 tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
2095 TCG_REG_SP, SAVE_OFS + i * REG_SIZE);
2096 }
2098 tcg_out_opc_imm(s, OPC_ADDI, TCG_REG_SP, TCG_REG_SP, FRAME_SIZE);
2099 tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, TCG_REG_RA, 0);
2100 }
2102 static void tcg_out_tb_start(TCGContext *s)
2103 {
2104 /* nothing to do */
2105 }
2107 static volatile sig_atomic_t got_sigill;
2109 static void sigill_handler(int signo, siginfo_t *si, void *data)
2110 {
2111 /* Skip the faulty instruction */
2112 ucontext_t *uc = (ucontext_t *)data;
2113 uc->uc_mcontext.__gregs[REG_PC] += 4;
2115 got_sigill = 1;
2116 }
2118 static void tcg_target_detect_isa(void)
2119 {
2120 #if !defined(have_zba) || !defined(have_zbb) || !defined(have_zicond)
2121 /*
2122 * TODO: It is expected that this will be determinable via
2123 * linux riscv_hwprobe syscall, not yet merged.
2124 * In the meantime, test via sigill.
2125 */
2127 struct sigaction sa_old, sa_new;
2129 memset(&sa_new, 0, sizeof(sa_new));
2130 sa_new.sa_flags = SA_SIGINFO;
2131 sa_new.sa_sigaction = sigill_handler;
2132 sigaction(SIGILL, &sa_new, &sa_old);
2134 #ifndef have_zba
2135 /* Probe for Zba: add.uw zero,zero,zero. */
2136 got_sigill = 0;
2137 asm volatile(".insn r 0x3b, 0, 0x04, zero, zero, zero" : : : "memory");
2138 have_zba = !got_sigill;
2139 #endif
2141 #ifndef have_zbb
2142 /* Probe for Zba: andn zero,zero,zero. */
2143 got_sigill = 0;
2144 asm volatile(".insn r 0x33, 7, 0x20, zero, zero, zero" : : : "memory");
2145 have_zbb = !got_sigill;
2146 #endif
2148 #ifndef have_zicond
2149 /* Probe for Zicond: czero.eqz zero,zero,zero. */
2150 got_sigill = 0;
2151 asm volatile(".insn r 0x33, 5, 0x07, zero, zero, zero" : : : "memory");
2152 have_zicond = !got_sigill;
2153 #endif
2155 sigaction(SIGILL, &sa_old, NULL);
2156 #endif
2157 }
2159 static void tcg_target_init(TCGContext *s)
2160 {
2161 tcg_target_detect_isa();
2163 tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff;
2164 tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff;
2166 tcg_target_call_clobber_regs = -1u;
2167 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S0);
2168 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S1);
2169 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S2);
2170 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S3);
2171 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S4);
2172 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S5);
2173 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S6);
2174 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S7);
2175 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S8);
2176 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S9);
2177 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S10);
2178 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S11);
2180 s->reserved_regs = 0;
2181 tcg_regset_set_reg(s->reserved_regs, TCG_REG_ZERO);
2182 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP0);
2183 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP1);
2184 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP2);
2185 tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP);
2186 tcg_regset_set_reg(s->reserved_regs, TCG_REG_GP);
2187 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TP);
2188 }
2190 typedef struct {
2191 DebugFrameHeader h;
2192 uint8_t fde_def_cfa[4];
2193 uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2];
2194 } DebugFrame;
2196 #define ELF_HOST_MACHINE EM_RISCV
2198 static const DebugFrame debug_frame = {
2199 .h.cie.len = sizeof(DebugFrameCIE) - 4, /* length after .len member */
2200 .h.cie.id = -1,
2201 .h.cie.version = 1,
2202 .h.cie.code_align = 1,
2203 .h.cie.data_align = -(TCG_TARGET_REG_BITS / 8) & 0x7f, /* sleb128 */
2204 .h.cie.return_column = TCG_REG_RA,
2206 /* Total FDE size does not include the "len" member. */
2207 .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset),
2209 .fde_def_cfa = {
2210 12, TCG_REG_SP, /* DW_CFA_def_cfa sp, ... */
2211 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */
2212 (FRAME_SIZE >> 7)
2213 },
2214 .fde_reg_ofs = {
2215 0x80 + 9, 12, /* DW_CFA_offset, s1, -96 */
2216 0x80 + 18, 11, /* DW_CFA_offset, s2, -88 */
2217 0x80 + 19, 10, /* DW_CFA_offset, s3, -80 */
2218 0x80 + 20, 9, /* DW_CFA_offset, s4, -72 */
2219 0x80 + 21, 8, /* DW_CFA_offset, s5, -64 */
2220 0x80 + 22, 7, /* DW_CFA_offset, s6, -56 */
2221 0x80 + 23, 6, /* DW_CFA_offset, s7, -48 */
2222 0x80 + 24, 5, /* DW_CFA_offset, s8, -40 */
2223 0x80 + 25, 4, /* DW_CFA_offset, s9, -32 */
2224 0x80 + 26, 3, /* DW_CFA_offset, s10, -24 */
2225 0x80 + 27, 2, /* DW_CFA_offset, s11, -16 */
2226 0x80 + 1 , 1, /* DW_CFA_offset, ra, -8 */
2227 }
2228 };
2230 void tcg_register_jit(const void *buf, size_t buf_size)
2231 {
2232 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame));
2233 }