2 * QTests for Nuvoton NPCM7xx EMC Modules.
4 * Copyright 2020 Google LLC
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 #include "qemu/osdep.h"
18 #include "libqos/libqos.h"
19 #include "qapi/qmp/qdict.h"
20 #include "qapi/qmp/qnum.h"
21 #include "qemu/bitops.h"
24 /* Name of the emc device. */
25 #define TYPE_NPCM7XX_EMC "npcm7xx-emc"
27 /* Timeout for various operations, in seconds. */
28 #define TIMEOUT_SECONDS 10
30 /* Address in memory of the descriptor. */
31 #define DESC_ADDR (1 << 20) /* 1 MiB */
33 /* Address in memory of the data packet. */
34 #define DATA_ADDR (DESC_ADDR + 4096)
38 #define NUM_TX_DESCRIPTORS 3
39 #define NUM_RX_DESCRIPTORS 2
41 /* Size of tx,rx test buffers. */
42 #define TX_DATA_LEN 64
43 #define RX_DATA_LEN 64
45 #define TX_STEP_COUNT 10000
46 #define RX_STEP_COUNT 10000
48 /* 32-bit register indices. */
49 typedef enum NPCM7xxPWMRegister
{
50 /* Control registers. */
54 /* There are 16 CAMn[ML] registers. */
69 /* Status registers. */
85 enum { NUM_CAMML_REGS
= 16 };
87 /* REG_CAMCMR fields */
88 /* Enable CAM Compare */
89 #define REG_CAMCMR_ECMP (1 << 4)
90 /* Accept Unicast Packet */
91 #define REG_CAMCMR_AUP (1 << 0)
93 /* REG_MCMDR fields */
95 #define REG_MCMDR_SWR (1 << 24)
96 /* Frame Transmission On */
97 #define REG_MCMDR_TXON (1 << 8)
98 /* Accept Long Packet */
99 #define REG_MCMDR_ALP (1 << 1)
100 /* Frame Reception On */
101 #define REG_MCMDR_RXON (1 << 0)
103 /* REG_MIEN fields */
104 /* Enable Transmit Completion Interrupt */
105 #define REG_MIEN_ENTXCP (1 << 18)
106 /* Enable Transmit Interrupt */
107 #define REG_MIEN_ENTXINTR (1 << 16)
108 /* Enable Receive Good Interrupt */
109 #define REG_MIEN_ENRXGD (1 << 4)
110 /* ENable Receive Interrupt */
111 #define REG_MIEN_ENRXINTR (1 << 0)
113 /* REG_MISTA fields */
114 /* Transmit Bus Error Interrupt */
115 #define REG_MISTA_TXBERR (1 << 24)
116 /* Transmit Descriptor Unavailable Interrupt */
117 #define REG_MISTA_TDU (1 << 23)
118 /* Transmit Completion Interrupt */
119 #define REG_MISTA_TXCP (1 << 18)
120 /* Transmit Interrupt */
121 #define REG_MISTA_TXINTR (1 << 16)
122 /* Receive Bus Error Interrupt */
123 #define REG_MISTA_RXBERR (1 << 11)
124 /* Receive Descriptor Unavailable Interrupt */
125 #define REG_MISTA_RDU (1 << 10)
126 /* DMA Early Notification Interrupt */
127 #define REG_MISTA_DENI (1 << 9)
128 /* Maximum Frame Length Interrupt */
129 #define REG_MISTA_DFOI (1 << 8)
130 /* Receive Good Interrupt */
131 #define REG_MISTA_RXGD (1 << 4)
132 /* Packet Too Long Interrupt */
133 #define REG_MISTA_PTLE (1 << 3)
134 /* Receive Interrupt */
135 #define REG_MISTA_RXINTR (1 << 0)
137 typedef struct NPCM7xxEMCTxDesc NPCM7xxEMCTxDesc
;
138 typedef struct NPCM7xxEMCRxDesc NPCM7xxEMCRxDesc
;
140 struct NPCM7xxEMCTxDesc
{
143 uint32_t status_and_length
;
147 struct NPCM7xxEMCRxDesc
{
148 uint32_t status_and_length
;
154 /* NPCM7xxEMCTxDesc.flags values */
155 /* Owner: 0 = cpu, 1 = emc */
156 #define TX_DESC_FLAG_OWNER_MASK (1 << 31)
157 /* Transmit interrupt enable */
158 #define TX_DESC_FLAG_INTEN (1 << 2)
160 /* NPCM7xxEMCTxDesc.status_and_length values */
161 /* Transmission complete */
162 #define TX_DESC_STATUS_TXCP (1 << 19)
163 /* Transmit interrupt */
164 #define TX_DESC_STATUS_TXINTR (1 << 16)
166 /* NPCM7xxEMCRxDesc.status_and_length values */
167 /* Owner: 0b00 = cpu, 0b10 = emc */
168 #define RX_DESC_STATUS_OWNER_SHIFT 30
169 #define RX_DESC_STATUS_OWNER_MASK 0xc0000000
170 /* Frame Reception Complete */
171 #define RX_DESC_STATUS_RXGD (1 << 20)
172 /* Packet too long */
173 #define RX_DESC_STATUS_PTLE (1 << 19)
174 /* Receive Interrupt */
175 #define RX_DESC_STATUS_RXINTR (1 << 16)
177 #define RX_DESC_PKT_LEN(word) ((uint32_t) (word) & 0xffff)
179 typedef struct EMCModule
{
185 typedef struct TestData
{
186 const EMCModule
*module
;
189 static const EMCModule emc_module_list
[] = {
193 .base_addr
= 0xf0825000
198 .base_addr
= 0xf0826000
202 /* Returns the index of the EMC module. */
203 static int emc_module_index(const EMCModule
*mod
)
205 ptrdiff_t diff
= mod
- emc_module_list
;
207 g_assert_true(diff
>= 0 && diff
< ARRAY_SIZE(emc_module_list
));
213 static void packet_test_clear(void *sockets
)
215 int *test_sockets
= sockets
;
217 close(test_sockets
[0]);
218 g_free(test_sockets
);
221 static int *packet_test_init(int module_num
, GString
*cmd_line
)
223 int *test_sockets
= g_new(int, 2);
224 int ret
= socketpair(PF_UNIX
, SOCK_STREAM
, 0, test_sockets
);
225 g_assert_cmpint(ret
, != , -1);
228 * KISS and use -nic. The driver accepts 'emc0' and 'emc1' as aliases
229 * in the 'model' field to specify the device to match.
231 g_string_append_printf(cmd_line
, " -nic socket,fd=%d,model=emc%d ",
232 test_sockets
[1], module_num
);
234 g_test_queue_destroy(packet_test_clear
, test_sockets
);
239 static uint32_t emc_read(QTestState
*qts
, const EMCModule
*mod
,
240 NPCM7xxPWMRegister regno
)
242 return qtest_readl(qts
, mod
->base_addr
+ regno
* sizeof(uint32_t));
246 static void emc_write(QTestState
*qts
, const EMCModule
*mod
,
247 NPCM7xxPWMRegister regno
, uint32_t value
)
249 qtest_writel(qts
, mod
->base_addr
+ regno
* sizeof(uint32_t), value
);
252 static void emc_read_tx_desc(QTestState
*qts
, uint32_t addr
,
253 NPCM7xxEMCTxDesc
*desc
)
255 qtest_memread(qts
, addr
, desc
, sizeof(*desc
));
256 desc
->flags
= le32_to_cpu(desc
->flags
);
257 desc
->txbsa
= le32_to_cpu(desc
->txbsa
);
258 desc
->status_and_length
= le32_to_cpu(desc
->status_and_length
);
259 desc
->ntxdsa
= le32_to_cpu(desc
->ntxdsa
);
262 static void emc_write_tx_desc(QTestState
*qts
, const NPCM7xxEMCTxDesc
*desc
,
265 NPCM7xxEMCTxDesc le_desc
;
267 le_desc
.flags
= cpu_to_le32(desc
->flags
);
268 le_desc
.txbsa
= cpu_to_le32(desc
->txbsa
);
269 le_desc
.status_and_length
= cpu_to_le32(desc
->status_and_length
);
270 le_desc
.ntxdsa
= cpu_to_le32(desc
->ntxdsa
);
271 qtest_memwrite(qts
, addr
, &le_desc
, sizeof(le_desc
));
274 static void emc_read_rx_desc(QTestState
*qts
, uint32_t addr
,
275 NPCM7xxEMCRxDesc
*desc
)
277 qtest_memread(qts
, addr
, desc
, sizeof(*desc
));
278 desc
->status_and_length
= le32_to_cpu(desc
->status_and_length
);
279 desc
->rxbsa
= le32_to_cpu(desc
->rxbsa
);
280 desc
->reserved
= le32_to_cpu(desc
->reserved
);
281 desc
->nrxdsa
= le32_to_cpu(desc
->nrxdsa
);
284 static void emc_write_rx_desc(QTestState
*qts
, const NPCM7xxEMCRxDesc
*desc
,
287 NPCM7xxEMCRxDesc le_desc
;
289 le_desc
.status_and_length
= cpu_to_le32(desc
->status_and_length
);
290 le_desc
.rxbsa
= cpu_to_le32(desc
->rxbsa
);
291 le_desc
.reserved
= cpu_to_le32(desc
->reserved
);
292 le_desc
.nrxdsa
= cpu_to_le32(desc
->nrxdsa
);
293 qtest_memwrite(qts
, addr
, &le_desc
, sizeof(le_desc
));
297 * Reset the EMC module.
298 * The module must be reset before, e.g., TXDLSA,RXDLSA are changed.
300 static bool emc_soft_reset(QTestState
*qts
, const EMCModule
*mod
)
305 emc_write(qts
, mod
, REG_MCMDR
, REG_MCMDR_SWR
);
308 * Wait for device to reset as the linux driver does.
309 * During reset the AHB reads 0 for all registers. So first wait for
310 * something that resets to non-zero, and then wait for SWR becoming 0.
312 end_time
= g_get_monotonic_time() + TIMEOUT_SECONDS
* G_TIME_SPAN_SECOND
;
315 qtest_clock_step(qts
, 100);
316 val
= emc_read(qts
, mod
, REG_FFTCR
);
317 } while (val
== 0 && g_get_monotonic_time() < end_time
);
320 qtest_clock_step(qts
, 100);
321 val
= emc_read(qts
, mod
, REG_MCMDR
);
322 if ((val
& REG_MCMDR_SWR
) == 0) {
324 * N.B. The CAMs have been reset here, so macaddr matching of
325 * incoming packets will not work.
329 } while (g_get_monotonic_time() < end_time
);
332 g_message("%s: Timeout expired", __func__
);
337 /* Check emc registers are reset to default value. */
338 static void test_init(gconstpointer test_data
)
340 const TestData
*td
= test_data
;
341 const EMCModule
*mod
= td
->module
;
342 QTestState
*qts
= qtest_init("-machine quanta-gsj");
345 #define CHECK_REG(regno, value) \
347 g_assert_cmphex(emc_read(qts, mod, (regno)), ==, (value)); \
350 CHECK_REG(REG_CAMCMR
, 0);
351 CHECK_REG(REG_CAMEN
, 0);
352 CHECK_REG(REG_TXDLSA
, 0xfffffffc);
353 CHECK_REG(REG_RXDLSA
, 0xfffffffc);
354 CHECK_REG(REG_MCMDR
, 0);
355 CHECK_REG(REG_MIID
, 0);
356 CHECK_REG(REG_MIIDA
, 0x00900000);
357 CHECK_REG(REG_FFTCR
, 0x0101);
358 CHECK_REG(REG_DMARFC
, 0x0800);
359 CHECK_REG(REG_MIEN
, 0);
360 CHECK_REG(REG_MISTA
, 0);
361 CHECK_REG(REG_MGSTA
, 0);
362 CHECK_REG(REG_MPCNT
, 0x7fff);
363 CHECK_REG(REG_MRPC
, 0);
364 CHECK_REG(REG_MRPCC
, 0);
365 CHECK_REG(REG_MREPC
, 0);
366 CHECK_REG(REG_DMARFS
, 0);
367 CHECK_REG(REG_CTXDSA
, 0);
368 CHECK_REG(REG_CTXBSA
, 0);
369 CHECK_REG(REG_CRXDSA
, 0);
370 CHECK_REG(REG_CRXBSA
, 0);
374 /* Skip over the MAC address registers, which is BASE+0 */
375 for (i
= 1; i
< NUM_CAMML_REGS
; ++i
) {
376 g_assert_cmpuint(emc_read(qts
, mod
, REG_CAMM_BASE
+ i
* 2), ==,
378 g_assert_cmpuint(emc_read(qts
, mod
, REG_CAML_BASE
+ i
* 2), ==,
386 static bool emc_wait_irq(QTestState
*qts
, const EMCModule
*mod
, int step
,
390 g_get_monotonic_time() + TIMEOUT_SECONDS
* G_TIME_SPAN_SECOND
;
393 if (qtest_get_irq(qts
, is_tx
? mod
->tx_irq
: mod
->rx_irq
)) {
396 qtest_clock_step(qts
, step
);
397 } while (g_get_monotonic_time() < end_time
);
399 g_message("%s: Timeout expired", __func__
);
403 static bool emc_wait_mista(QTestState
*qts
, const EMCModule
*mod
, int step
,
407 g_get_monotonic_time() + TIMEOUT_SECONDS
* G_TIME_SPAN_SECOND
;
410 uint32_t mista
= emc_read(qts
, mod
, REG_MISTA
);
414 qtest_clock_step(qts
, step
);
415 } while (g_get_monotonic_time() < end_time
);
417 g_message("%s: Timeout expired", __func__
);
421 static bool wait_socket_readable(int fd
)
428 FD_SET(fd
, &read_fds
);
429 tv
.tv_sec
= TIMEOUT_SECONDS
;
431 rv
= select(fd
+ 1, &read_fds
, NULL
, NULL
, &tv
);
434 } else if (rv
== 0) {
435 g_message("%s: Timeout expired", __func__
);
440 /* Initialize *desc (in host endian format). */
441 static void init_tx_desc(NPCM7xxEMCTxDesc
*desc
, size_t count
,
444 g_assert(count
>= 2);
445 memset(&desc
[0], 0, sizeof(*desc
) * count
);
446 /* Leave the last one alone, owned by the cpu -> stops transmission. */
447 for (size_t i
= 0; i
< count
- 1; ++i
) {
449 (TX_DESC_FLAG_OWNER_MASK
| /* owner = 1: emc */
451 0 | /* crc append = 0 */
452 0 /* padding enable = 0 */);
453 desc
[i
].status_and_length
=
454 (0 | /* collision count = 0 */
465 0 /* length filled in later */);
466 desc
[i
].ntxdsa
= desc_addr
+ (i
+ 1) * sizeof(*desc
);
470 static void enable_tx(QTestState
*qts
, const EMCModule
*mod
,
471 const NPCM7xxEMCTxDesc
*desc
, size_t count
,
472 uint32_t desc_addr
, uint32_t mien_flags
)
474 /* Write the descriptors to guest memory. */
475 for (size_t i
= 0; i
< count
; ++i
) {
476 emc_write_tx_desc(qts
, desc
+ i
, desc_addr
+ i
* sizeof(*desc
));
479 /* Trigger sending the packet. */
480 /* The module must be reset before changing TXDLSA. */
481 g_assert(emc_soft_reset(qts
, mod
));
482 emc_write(qts
, mod
, REG_TXDLSA
, desc_addr
);
483 emc_write(qts
, mod
, REG_CTXDSA
, ~0);
484 emc_write(qts
, mod
, REG_MIEN
, REG_MIEN_ENTXCP
| mien_flags
);
486 uint32_t mcmdr
= emc_read(qts
, mod
, REG_MCMDR
);
487 mcmdr
|= REG_MCMDR_TXON
;
488 emc_write(qts
, mod
, REG_MCMDR
, mcmdr
);
492 static void emc_send_verify1(QTestState
*qts
, const EMCModule
*mod
, int fd
,
493 bool with_irq
, uint32_t desc_addr
,
494 uint32_t next_desc_addr
,
495 const char *test_data
, int test_size
)
497 NPCM7xxEMCTxDesc result_desc
;
498 uint32_t expected_mask
, expected_value
, recv_len
;
500 char buffer
[TX_DATA_LEN
];
502 g_assert(wait_socket_readable(fd
));
504 /* Read the descriptor back. */
505 emc_read_tx_desc(qts
, desc_addr
, &result_desc
);
506 /* Descriptor should be owned by cpu now. */
507 g_assert((result_desc
.flags
& TX_DESC_FLAG_OWNER_MASK
) == 0);
508 /* Test the status bits, ignoring the length field. */
509 expected_mask
= 0xffff << 16;
510 expected_value
= TX_DESC_STATUS_TXCP
;
512 expected_value
|= TX_DESC_STATUS_TXINTR
;
514 g_assert_cmphex((result_desc
.status_and_length
& expected_mask
), ==,
517 /* Check data sent to the backend. */
519 ret
= recv(fd
, &recv_len
, sizeof(recv_len
), MSG_DONTWAIT
);
520 g_assert_cmpint(ret
, == , sizeof(recv_len
));
522 g_assert(wait_socket_readable(fd
));
523 memset(buffer
, 0xff, sizeof(buffer
));
524 ret
= recv(fd
, buffer
, test_size
, MSG_DONTWAIT
);
525 g_assert_cmpmem(buffer
, ret
, test_data
, test_size
);
528 static void emc_send_verify(QTestState
*qts
, const EMCModule
*mod
, int fd
,
531 NPCM7xxEMCTxDesc desc
[NUM_TX_DESCRIPTORS
];
532 uint32_t desc_addr
= DESC_ADDR
;
533 static const char test1_data
[] = "TEST1";
534 static const char test2_data
[] = "Testing 1 2 3 ...";
535 uint32_t data1_addr
= DATA_ADDR
;
536 uint32_t data2_addr
= data1_addr
+ sizeof(test1_data
);
538 uint32_t end_desc_addr
;
540 /* Prepare test data buffer. */
541 qtest_memwrite(qts
, data1_addr
, test1_data
, sizeof(test1_data
));
542 qtest_memwrite(qts
, data2_addr
, test2_data
, sizeof(test2_data
));
544 init_tx_desc(&desc
[0], NUM_TX_DESCRIPTORS
, desc_addr
);
545 desc
[0].txbsa
= data1_addr
;
546 desc
[0].status_and_length
|= sizeof(test1_data
);
547 desc
[1].txbsa
= data2_addr
;
548 desc
[1].status_and_length
|= sizeof(test2_data
);
550 enable_tx(qts
, mod
, &desc
[0], NUM_TX_DESCRIPTORS
, desc_addr
,
551 with_irq
? REG_MIEN_ENTXINTR
: 0);
553 /* Prod the device to send the packet. */
554 emc_write(qts
, mod
, REG_TSDR
, 1);
557 * It's problematic to observe the interrupt for each packet.
558 * Instead just wait until all the packets go out.
563 g_assert_true(emc_wait_irq(qts
, mod
, TX_STEP_COUNT
,
566 g_assert_true(emc_wait_mista(qts
, mod
, TX_STEP_COUNT
,
569 got_tdu
= !!(emc_read(qts
, mod
, REG_MISTA
) & REG_MISTA_TDU
);
570 /* If we don't have TDU yet, reset the interrupt. */
572 emc_write(qts
, mod
, REG_MISTA
,
573 emc_read(qts
, mod
, REG_MISTA
) & 0xffff0000);
577 end_desc_addr
= desc_addr
+ 2 * sizeof(desc
[0]);
578 g_assert_cmphex(emc_read(qts
, mod
, REG_CTXDSA
), ==, end_desc_addr
);
579 g_assert_cmphex(emc_read(qts
, mod
, REG_MISTA
), ==,
580 REG_MISTA_TXCP
| REG_MISTA_TXINTR
| REG_MISTA_TDU
);
582 emc_send_verify1(qts
, mod
, fd
, with_irq
,
583 desc_addr
, end_desc_addr
,
584 test1_data
, sizeof(test1_data
));
585 emc_send_verify1(qts
, mod
, fd
, with_irq
,
586 desc_addr
+ sizeof(desc
[0]), end_desc_addr
,
587 test2_data
, sizeof(test2_data
));
590 /* Initialize *desc (in host endian format). */
591 static void init_rx_desc(NPCM7xxEMCRxDesc
*desc
, size_t count
,
592 uint32_t desc_addr
, uint32_t data_addr
)
594 g_assert_true(count
>= 2);
595 memset(desc
, 0, sizeof(*desc
) * count
);
596 desc
[0].rxbsa
= data_addr
;
597 desc
[0].status_and_length
=
598 (0b10 << RX_DESC_STATUS_OWNER_SHIFT
| /* owner = 10: emc */
605 0 /* length (filled in later) */);
606 /* Leave the last one alone, owned by the cpu -> stops transmission. */
607 desc
[0].nrxdsa
= desc_addr
+ sizeof(*desc
);
610 static void enable_rx(QTestState
*qts
, const EMCModule
*mod
,
611 const NPCM7xxEMCRxDesc
*desc
, size_t count
,
612 uint32_t desc_addr
, uint32_t mien_flags
,
613 uint32_t mcmdr_flags
)
616 * Write the descriptor to guest memory.
617 * FWIW, IWBN if the docs said the buffer needs to be at least DMARFC
620 for (size_t i
= 0; i
< count
; ++i
) {
621 emc_write_rx_desc(qts
, desc
+ i
, desc_addr
+ i
* sizeof(*desc
));
624 /* Trigger receiving the packet. */
625 /* The module must be reset before changing RXDLSA. */
626 g_assert(emc_soft_reset(qts
, mod
));
627 emc_write(qts
, mod
, REG_RXDLSA
, desc_addr
);
628 emc_write(qts
, mod
, REG_MIEN
, REG_MIEN_ENRXGD
| mien_flags
);
631 * We don't know what the device's macaddr is, so just accept all
632 * unicast packets (AUP).
634 emc_write(qts
, mod
, REG_CAMCMR
, REG_CAMCMR_AUP
);
635 emc_write(qts
, mod
, REG_CAMEN
, 1 << 0);
637 uint32_t mcmdr
= emc_read(qts
, mod
, REG_MCMDR
);
638 mcmdr
|= REG_MCMDR_RXON
| mcmdr_flags
;
639 emc_write(qts
, mod
, REG_MCMDR
, mcmdr
);
643 static void emc_recv_verify(QTestState
*qts
, const EMCModule
*mod
, int fd
,
644 bool with_irq
, bool pump_rsdr
)
646 NPCM7xxEMCRxDesc desc
[NUM_RX_DESCRIPTORS
];
647 uint32_t desc_addr
= DESC_ADDR
;
648 uint32_t data_addr
= DATA_ADDR
;
650 uint32_t expected_mask
, expected_value
;
651 NPCM7xxEMCRxDesc result_desc
;
653 /* Prepare test data buffer. */
654 const char test
[RX_DATA_LEN
] = "TEST";
655 int len
= htonl(sizeof(test
));
656 const struct iovec iov
[] = {
659 .iov_len
= sizeof(len
),
661 .iov_base
= (char *) test
,
662 .iov_len
= sizeof(test
),
667 * Reset the device BEFORE sending a test packet, otherwise the packet
668 * may get swallowed by an active device of an earlier test.
670 init_rx_desc(&desc
[0], NUM_RX_DESCRIPTORS
, desc_addr
, data_addr
);
671 enable_rx(qts
, mod
, &desc
[0], NUM_RX_DESCRIPTORS
, desc_addr
,
672 with_irq
? REG_MIEN_ENRXINTR
: 0, 0);
675 * If requested, prod the device to accept a packet.
676 * This isn't necessary, the linux driver doesn't do this.
677 * Test doing/not-doing this for robustness.
680 emc_write(qts
, mod
, REG_RSDR
, 1);
683 /* Send test packet to device's socket. */
684 ret
= iov_send(fd
, iov
, 2, 0, sizeof(len
) + sizeof(test
));
685 g_assert_cmpint(ret
, == , sizeof(test
) + sizeof(len
));
687 /* Wait for RX interrupt. */
689 g_assert_true(emc_wait_irq(qts
, mod
, RX_STEP_COUNT
, /*is_tx=*/false));
691 g_assert_true(emc_wait_mista(qts
, mod
, RX_STEP_COUNT
, REG_MISTA_RXGD
));
694 g_assert_cmphex(emc_read(qts
, mod
, REG_CRXDSA
), ==,
695 desc_addr
+ sizeof(desc
[0]));
697 expected_mask
= 0xffff;
698 expected_value
= (REG_MISTA_DENI
|
701 g_assert_cmphex((emc_read(qts
, mod
, REG_MISTA
) & expected_mask
),
704 /* Read the descriptor back. */
705 emc_read_rx_desc(qts
, desc_addr
, &result_desc
);
706 /* Descriptor should be owned by cpu now. */
707 g_assert((result_desc
.status_and_length
& RX_DESC_STATUS_OWNER_MASK
) == 0);
708 /* Test the status bits, ignoring the length field. */
709 expected_mask
= 0xffff << 16;
710 expected_value
= RX_DESC_STATUS_RXGD
;
712 expected_value
|= RX_DESC_STATUS_RXINTR
;
714 g_assert_cmphex((result_desc
.status_and_length
& expected_mask
), ==,
716 g_assert_cmpint(RX_DESC_PKT_LEN(result_desc
.status_and_length
), ==,
717 RX_DATA_LEN
+ CRC_LENGTH
);
720 char buffer
[RX_DATA_LEN
];
721 qtest_memread(qts
, data_addr
, buffer
, sizeof(buffer
));
722 g_assert_cmpstr(buffer
, == , "TEST");
726 static void emc_test_ptle(QTestState
*qts
, const EMCModule
*mod
, int fd
)
728 NPCM7xxEMCRxDesc desc
[NUM_RX_DESCRIPTORS
];
729 uint32_t desc_addr
= DESC_ADDR
;
730 uint32_t data_addr
= DATA_ADDR
;
732 NPCM7xxEMCRxDesc result_desc
;
733 uint32_t expected_mask
, expected_value
;
735 /* Prepare test data buffer. */
736 #define PTLE_DATA_LEN 1600
737 char test_data
[PTLE_DATA_LEN
];
738 int len
= htonl(sizeof(test_data
));
739 const struct iovec iov
[] = {
742 .iov_len
= sizeof(len
),
744 .iov_base
= (char *) test_data
,
745 .iov_len
= sizeof(test_data
),
748 memset(test_data
, 42, sizeof(test_data
));
751 * Reset the device BEFORE sending a test packet, otherwise the packet
752 * may get swallowed by an active device of an earlier test.
754 init_rx_desc(&desc
[0], NUM_RX_DESCRIPTORS
, desc_addr
, data_addr
);
755 enable_rx(qts
, mod
, &desc
[0], NUM_RX_DESCRIPTORS
, desc_addr
,
756 REG_MIEN_ENRXINTR
, REG_MCMDR_ALP
);
758 /* Send test packet to device's socket. */
759 ret
= iov_send(fd
, iov
, 2, 0, sizeof(len
) + sizeof(test_data
));
760 g_assert_cmpint(ret
, == , sizeof(test_data
) + sizeof(len
));
762 /* Wait for RX interrupt. */
763 g_assert_true(emc_wait_irq(qts
, mod
, RX_STEP_COUNT
, /*is_tx=*/false));
765 /* Read the descriptor back. */
766 emc_read_rx_desc(qts
, desc_addr
, &result_desc
);
767 /* Descriptor should be owned by cpu now. */
768 g_assert((result_desc
.status_and_length
& RX_DESC_STATUS_OWNER_MASK
) == 0);
769 /* Test the status bits, ignoring the length field. */
770 expected_mask
= 0xffff << 16;
771 expected_value
= (RX_DESC_STATUS_RXGD
|
772 RX_DESC_STATUS_PTLE
|
773 RX_DESC_STATUS_RXINTR
);
774 g_assert_cmphex((result_desc
.status_and_length
& expected_mask
), ==,
776 g_assert_cmpint(RX_DESC_PKT_LEN(result_desc
.status_and_length
), ==,
777 PTLE_DATA_LEN
+ CRC_LENGTH
);
780 char buffer
[PTLE_DATA_LEN
];
781 qtest_memread(qts
, data_addr
, buffer
, sizeof(buffer
));
782 g_assert(memcmp(buffer
, test_data
, PTLE_DATA_LEN
) == 0);
786 static void test_tx(gconstpointer test_data
)
788 const TestData
*td
= test_data
;
789 GString
*cmd_line
= g_string_new("-machine quanta-gsj");
790 int *test_sockets
= packet_test_init(emc_module_index(td
->module
),
792 QTestState
*qts
= qtest_init(cmd_line
->str
);
795 * TODO: For pedantic correctness test_sockets[0] should be closed after
796 * the fork and before the exec, but that will require some harness
799 close(test_sockets
[1]);
800 /* Defensive programming */
801 test_sockets
[1] = -1;
803 qtest_irq_intercept_in(qts
, "/machine/soc/a9mpcore/gic");
805 emc_send_verify(qts
, td
->module
, test_sockets
[0], /*with_irq=*/false);
806 emc_send_verify(qts
, td
->module
, test_sockets
[0], /*with_irq=*/true);
811 static void test_rx(gconstpointer test_data
)
813 const TestData
*td
= test_data
;
814 GString
*cmd_line
= g_string_new("-machine quanta-gsj");
815 int *test_sockets
= packet_test_init(emc_module_index(td
->module
),
817 QTestState
*qts
= qtest_init(cmd_line
->str
);
820 * TODO: For pedantic correctness test_sockets[0] should be closed after
821 * the fork and before the exec, but that will require some harness
824 close(test_sockets
[1]);
825 /* Defensive programming */
826 test_sockets
[1] = -1;
828 qtest_irq_intercept_in(qts
, "/machine/soc/a9mpcore/gic");
830 emc_recv_verify(qts
, td
->module
, test_sockets
[0], /*with_irq=*/false,
831 /*pump_rsdr=*/false);
832 emc_recv_verify(qts
, td
->module
, test_sockets
[0], /*with_irq=*/false,
834 emc_recv_verify(qts
, td
->module
, test_sockets
[0], /*with_irq=*/true,
835 /*pump_rsdr=*/false);
836 emc_recv_verify(qts
, td
->module
, test_sockets
[0], /*with_irq=*/true,
838 emc_test_ptle(qts
, td
->module
, test_sockets
[0]);
844 static void emc_add_test(const char *name
, const TestData
* td
,
847 g_autofree
char *full_name
= g_strdup_printf(
848 "npcm7xx_emc/emc[%d]/%s", emc_module_index(td
->module
), name
);
849 qtest_add_data_func(full_name
, td
, fn
);
851 #define add_test(name, td) emc_add_test(#name, td, test_##name)
853 int main(int argc
, char **argv
)
855 TestData test_data_list
[ARRAY_SIZE(emc_module_list
)];
857 g_test_init(&argc
, &argv
, NULL
);
859 for (int i
= 0; i
< ARRAY_SIZE(emc_module_list
); ++i
) {
860 TestData
*td
= &test_data_list
[i
];
862 td
->module
= &emc_module_list
[i
];