tcg/i386/tcg-target.h

   1 /*
   2  * Tiny Code Generator for QEMU
   3  *
   4  * Copyright (c) 2008 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #ifndef I386_TCG_TARGET_H
  26 #define I386_TCG_TARGET_H
  27
  28 #include "host/cpuinfo.h"
  29
  30 #define TCG_TARGET_INSN_UNIT_SIZE  1
  31
  32 #ifdef __x86_64__
  33 # define TCG_TARGET_NB_REGS   32
  34 # define MAX_CODE_GEN_BUFFER_SIZE  (2 * GiB)
  35 #else
  36 # define TCG_TARGET_NB_REGS   24
  37 # define MAX_CODE_GEN_BUFFER_SIZE  UINT32_MAX
  38 #endif
  39
  40 typedef enum {
  41     TCG_REG_EAX = 0,
  42     TCG_REG_ECX,
  43     TCG_REG_EDX,
  44     TCG_REG_EBX,
  45     TCG_REG_ESP,
  46     TCG_REG_EBP,
  47     TCG_REG_ESI,
  48     TCG_REG_EDI,
  49
  50     /* 64-bit registers; always define the symbols to avoid
  51        too much if-deffing.  */
  52     TCG_REG_R8,
  53     TCG_REG_R9,
  54     TCG_REG_R10,
  55     TCG_REG_R11,
  56     TCG_REG_R12,
  57     TCG_REG_R13,
  58     TCG_REG_R14,
  59     TCG_REG_R15,
  60
  61     TCG_REG_XMM0,
  62     TCG_REG_XMM1,
  63     TCG_REG_XMM2,
  64     TCG_REG_XMM3,
  65     TCG_REG_XMM4,
  66     TCG_REG_XMM5,
  67     TCG_REG_XMM6,
  68     TCG_REG_XMM7,
  69
  70     /* 64-bit registers; likewise always define.  */
  71     TCG_REG_XMM8,
  72     TCG_REG_XMM9,
  73     TCG_REG_XMM10,
  74     TCG_REG_XMM11,
  75     TCG_REG_XMM12,
  76     TCG_REG_XMM13,
  77     TCG_REG_XMM14,
  78     TCG_REG_XMM15,
  79
  80     TCG_REG_RAX = TCG_REG_EAX,
  81     TCG_REG_RCX = TCG_REG_ECX,
  82     TCG_REG_RDX = TCG_REG_EDX,
  83     TCG_REG_RBX = TCG_REG_EBX,
  84     TCG_REG_RSP = TCG_REG_ESP,
  85     TCG_REG_RBP = TCG_REG_EBP,
  86     TCG_REG_RSI = TCG_REG_ESI,
  87     TCG_REG_RDI = TCG_REG_EDI,
  88
  89     TCG_AREG0 = TCG_REG_EBP,
  90     TCG_REG_CALL_STACK = TCG_REG_ESP
  91 } TCGReg;
  92
  93 /* used for function call generation */
  94 #define TCG_TARGET_STACK_ALIGN 16
  95 #if defined(_WIN64)
  96 #define TCG_TARGET_CALL_STACK_OFFSET 32
  97 #else
  98 #define TCG_TARGET_CALL_STACK_OFFSET 0
  99 #endif
 100 #define TCG_TARGET_CALL_ARG_I32      TCG_CALL_ARG_NORMAL
 101 #define TCG_TARGET_CALL_ARG_I64      TCG_CALL_ARG_NORMAL
 102 #if defined(_WIN64)
 103 # define TCG_TARGET_CALL_ARG_I128    TCG_CALL_ARG_BY_REF
 104 # define TCG_TARGET_CALL_RET_I128    TCG_CALL_RET_BY_VEC
 105 #elif TCG_TARGET_REG_BITS == 64
 106 # define TCG_TARGET_CALL_ARG_I128    TCG_CALL_ARG_NORMAL
 107 # define TCG_TARGET_CALL_RET_I128    TCG_CALL_RET_NORMAL
 108 #else
 109 # define TCG_TARGET_CALL_ARG_I128    TCG_CALL_ARG_NORMAL
 110 # define TCG_TARGET_CALL_RET_I128    TCG_CALL_RET_BY_REF
 111 #endif
 112
 113 #define have_bmi1         (cpuinfo & CPUINFO_BMI1)
 114 #define have_popcnt       (cpuinfo & CPUINFO_POPCNT)
 115 #define have_avx1         (cpuinfo & CPUINFO_AVX1)
 116 #define have_avx2         (cpuinfo & CPUINFO_AVX2)
 117 #define have_movbe        (cpuinfo & CPUINFO_MOVBE)
 118
 119 /*
 120  * There are interesting instructions in AVX512, so long as we have AVX512VL,
 121  * which indicates support for EVEX on sizes smaller than 512 bits.
 122  */
 123 #define have_avx512vl     ((cpuinfo & CPUINFO_AVX512VL) && \
 124                            (cpuinfo & CPUINFO_AVX512F))
 125 #define have_avx512bw     ((cpuinfo & CPUINFO_AVX512BW) && have_avx512vl)
 126 #define have_avx512dq     ((cpuinfo & CPUINFO_AVX512DQ) && have_avx512vl)
 127 #define have_avx512vbmi2  ((cpuinfo & CPUINFO_AVX512VBMI2) && have_avx512vl)
 128
 129 /* optional instructions */
 130 #define TCG_TARGET_HAS_div2_i32         1
 131 #define TCG_TARGET_HAS_rot_i32          1
 132 #define TCG_TARGET_HAS_ext8s_i32        1
 133 #define TCG_TARGET_HAS_ext16s_i32       1
 134 #define TCG_TARGET_HAS_ext8u_i32        1
 135 #define TCG_TARGET_HAS_ext16u_i32       1
 136 #define TCG_TARGET_HAS_bswap16_i32      1
 137 #define TCG_TARGET_HAS_bswap32_i32      1
 138 #define TCG_TARGET_HAS_not_i32          1
 139 #define TCG_TARGET_HAS_andc_i32         have_bmi1
 140 #define TCG_TARGET_HAS_orc_i32          0
 141 #define TCG_TARGET_HAS_eqv_i32          0
 142 #define TCG_TARGET_HAS_nand_i32         0
 143 #define TCG_TARGET_HAS_nor_i32          0
 144 #define TCG_TARGET_HAS_clz_i32          1
 145 #define TCG_TARGET_HAS_ctz_i32          1
 146 #define TCG_TARGET_HAS_ctpop_i32        have_popcnt
 147 #define TCG_TARGET_HAS_deposit_i32      1
 148 #define TCG_TARGET_HAS_extract_i32      1
 149 #define TCG_TARGET_HAS_sextract_i32     1
 150 #define TCG_TARGET_HAS_extract2_i32     1
 151 #define TCG_TARGET_HAS_negsetcond_i32   1
 152 #define TCG_TARGET_HAS_add2_i32         1
 153 #define TCG_TARGET_HAS_sub2_i32         1
 154 #define TCG_TARGET_HAS_mulu2_i32        1
 155 #define TCG_TARGET_HAS_muls2_i32        1
 156 #define TCG_TARGET_HAS_muluh_i32        0
 157 #define TCG_TARGET_HAS_mulsh_i32        0
 158
 159 #if TCG_TARGET_REG_BITS == 64
 160 /* Keep 32-bit values zero-extended in a register.  */
 161 #define TCG_TARGET_HAS_extr_i64_i32     1
 162 #define TCG_TARGET_HAS_div2_i64         1
 163 #define TCG_TARGET_HAS_rot_i64          1
 164 #define TCG_TARGET_HAS_ext8s_i64        1
 165 #define TCG_TARGET_HAS_ext16s_i64       1
 166 #define TCG_TARGET_HAS_ext32s_i64       1
 167 #define TCG_TARGET_HAS_ext8u_i64        1
 168 #define TCG_TARGET_HAS_ext16u_i64       1
 169 #define TCG_TARGET_HAS_ext32u_i64       1
 170 #define TCG_TARGET_HAS_bswap16_i64      1
 171 #define TCG_TARGET_HAS_bswap32_i64      1
 172 #define TCG_TARGET_HAS_bswap64_i64      1
 173 #define TCG_TARGET_HAS_not_i64          1
 174 #define TCG_TARGET_HAS_andc_i64         have_bmi1
 175 #define TCG_TARGET_HAS_orc_i64          0
 176 #define TCG_TARGET_HAS_eqv_i64          0
 177 #define TCG_TARGET_HAS_nand_i64         0
 178 #define TCG_TARGET_HAS_nor_i64          0
 179 #define TCG_TARGET_HAS_clz_i64          1
 180 #define TCG_TARGET_HAS_ctz_i64          1
 181 #define TCG_TARGET_HAS_ctpop_i64        have_popcnt
 182 #define TCG_TARGET_HAS_deposit_i64      1
 183 #define TCG_TARGET_HAS_extract_i64      1
 184 #define TCG_TARGET_HAS_sextract_i64     0
 185 #define TCG_TARGET_HAS_extract2_i64     1
 186 #define TCG_TARGET_HAS_negsetcond_i64   1
 187 #define TCG_TARGET_HAS_add2_i64         1
 188 #define TCG_TARGET_HAS_sub2_i64         1
 189 #define TCG_TARGET_HAS_mulu2_i64        1
 190 #define TCG_TARGET_HAS_muls2_i64        1
 191 #define TCG_TARGET_HAS_muluh_i64        0
 192 #define TCG_TARGET_HAS_mulsh_i64        0
 193 #define TCG_TARGET_HAS_qemu_st8_i32     0
 194 #else
 195 #define TCG_TARGET_HAS_qemu_st8_i32     1
 196 #endif
 197
 198 #define TCG_TARGET_HAS_qemu_ldst_i128 \
 199     (TCG_TARGET_REG_BITS == 64 && (cpuinfo & CPUINFO_ATOMIC_VMOVDQA))
 200
 201 #define TCG_TARGET_HAS_tst              1
 202
 203 /* We do not support older SSE systems, only beginning with AVX1.  */
 204 #define TCG_TARGET_HAS_v64              have_avx1
 205 #define TCG_TARGET_HAS_v128             have_avx1
 206 #define TCG_TARGET_HAS_v256             have_avx2
 207
 208 #define TCG_TARGET_HAS_andc_vec         1
 209 #define TCG_TARGET_HAS_orc_vec          have_avx512vl
 210 #define TCG_TARGET_HAS_nand_vec         have_avx512vl
 211 #define TCG_TARGET_HAS_nor_vec          have_avx512vl
 212 #define TCG_TARGET_HAS_eqv_vec          have_avx512vl
 213 #define TCG_TARGET_HAS_not_vec          have_avx512vl
 214 #define TCG_TARGET_HAS_neg_vec          0
 215 #define TCG_TARGET_HAS_abs_vec          1
 216 #define TCG_TARGET_HAS_roti_vec         have_avx512vl
 217 #define TCG_TARGET_HAS_rots_vec         0
 218 #define TCG_TARGET_HAS_rotv_vec         have_avx512vl
 219 #define TCG_TARGET_HAS_shi_vec          1
 220 #define TCG_TARGET_HAS_shs_vec          1
 221 #define TCG_TARGET_HAS_shv_vec          have_avx2
 222 #define TCG_TARGET_HAS_mul_vec          1
 223 #define TCG_TARGET_HAS_sat_vec          1
 224 #define TCG_TARGET_HAS_minmax_vec       1
 225 #define TCG_TARGET_HAS_bitsel_vec       have_avx512vl
 226 #define TCG_TARGET_HAS_cmpsel_vec       -1
 227
 228 #define TCG_TARGET_deposit_i32_valid(ofs, len) \
 229     (((ofs) == 0 && ((len) == 8 || (len) == 16)) || \
 230      (TCG_TARGET_REG_BITS == 32 && (ofs) == 8 && (len) == 8))
 231 #define TCG_TARGET_deposit_i64_valid    TCG_TARGET_deposit_i32_valid
 232
 233 /* Check for the possibility of high-byte extraction and, for 64-bit,
 234    zero-extending 32-bit right-shift.  */
 235 #define TCG_TARGET_extract_i32_valid(ofs, len) ((ofs) == 8 && (len) == 8)
 236 #define TCG_TARGET_extract_i64_valid(ofs, len) \
 237     (((ofs) == 8 && (len) == 8) || ((ofs) + (len)) == 32)
 238
 239 /* This defines the natural memory order supported by this
 240  * architecture before guarantees made by various barrier
 241  * instructions.
 242  *
 243  * The x86 has a pretty strong memory ordering which only really
 244  * allows for some stores to be re-ordered after loads.
 245  */
 246 #include "tcg/tcg-mo.h"
 247
 248 #define TCG_TARGET_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD)
 249 #define TCG_TARGET_NEED_LDST_LABELS
 250 #define TCG_TARGET_NEED_POOL_LABELS
 251
 252 #endif