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hw/arm: Deprecate various old Arm machine types
[qemu/armbru.git] / target / sparc / ldst_helper.c
blob1ecd58e8ff5c8147efbb0eda0e520693730b403e
1 /*
2 * Helpers for loads and stores
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "qemu/log.h"
22 #include "cpu.h"
23 #include "tcg/tcg.h"
24 #include "exec/helper-proto.h"
25 #include "exec/exec-all.h"
26 #include "exec/cpu_ldst.h"
27 #include "asi.h"
28
29 //#define DEBUG_MMU
30 //#define DEBUG_MXCC
31 //#define DEBUG_UNASSIGNED
32 //#define DEBUG_ASI
33 //#define DEBUG_CACHE_CONTROL
34
35 #ifdef DEBUG_MMU
36 #define DPRINTF_MMU(fmt, ...) \
37 do { printf("MMU: " fmt , ## __VA_ARGS__); } while (0)
38 #else
39 #define DPRINTF_MMU(fmt, ...) do {} while (0)
40 #endif
41
42 #ifdef DEBUG_MXCC
43 #define DPRINTF_MXCC(fmt, ...) \
44 do { printf("MXCC: " fmt , ## __VA_ARGS__); } while (0)
45 #else
46 #define DPRINTF_MXCC(fmt, ...) do {} while (0)
47 #endif
48
49 #ifdef DEBUG_ASI
50 #define DPRINTF_ASI(fmt, ...) \
51 do { printf("ASI: " fmt , ## __VA_ARGS__); } while (0)
52 #endif
53
54 #ifdef DEBUG_CACHE_CONTROL
55 #define DPRINTF_CACHE_CONTROL(fmt, ...) \
56 do { printf("CACHE_CONTROL: " fmt , ## __VA_ARGS__); } while (0)
57 #else
58 #define DPRINTF_CACHE_CONTROL(fmt, ...) do {} while (0)
59 #endif
60
61 #ifdef TARGET_SPARC64
62 #ifndef TARGET_ABI32
63 #define AM_CHECK(env1) ((env1)->pstate & PS_AM)
64 #else
65 #define AM_CHECK(env1) (1)
66 #endif
67 #endif
68
69 #if defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
70 /* Calculates TSB pointer value for fault page size
71 * UltraSPARC IIi has fixed sizes (8k or 64k) for the page pointers
72 * UA2005 holds the page size configuration in mmu_ctx registers */
73 static uint64_t ultrasparc_tsb_pointer(CPUSPARCState *env,
74 const SparcV9MMU *mmu, const int idx)
75 {
76 uint64_t tsb_register;
77 int page_size;
78 if (cpu_has_hypervisor(env)) {
79 int tsb_index = 0;
80 int ctx = mmu->tag_access & 0x1fffULL;
81 uint64_t ctx_register = mmu->sun4v_ctx_config[ctx ? 1 : 0];
82 tsb_index = idx;
83 tsb_index |= ctx ? 2 : 0;
84 page_size = idx ? ctx_register >> 8 : ctx_register;
85 page_size &= 7;
86 tsb_register = mmu->sun4v_tsb_pointers[tsb_index];
87 } else {
88 page_size = idx;
89 tsb_register = mmu->tsb;
90 }
91 int tsb_split = (tsb_register & 0x1000ULL) ? 1 : 0;
92 int tsb_size = tsb_register & 0xf;
93
94 uint64_t tsb_base_mask = (~0x1fffULL) << tsb_size;
95
96 /* move va bits to correct position,
97 * the context bits will be masked out later */
98 uint64_t va = mmu->tag_access >> (3 * page_size + 9);
99
100 /* calculate tsb_base mask and adjust va if split is in use */
101 if (tsb_split) {
102 if (idx == 0) {
103 va &= ~(1ULL << (13 + tsb_size));
104 } else {
105 va |= (1ULL << (13 + tsb_size));
106 }
107 tsb_base_mask <<= 1;
108 }
109
110 return ((tsb_register & tsb_base_mask) | (va & ~tsb_base_mask)) & ~0xfULL;
111 }
112
113 /* Calculates tag target register value by reordering bits
114 in tag access register */
115 static uint64_t ultrasparc_tag_target(uint64_t tag_access_register)
116 {
117 return ((tag_access_register & 0x1fff) << 48) | (tag_access_register >> 22);
118 }
119
120 static void replace_tlb_entry(SparcTLBEntry *tlb,
121 uint64_t tlb_tag, uint64_t tlb_tte,
122 CPUSPARCState *env)
123 {
124 target_ulong mask, size, va, offset;
125
126 /* flush page range if translation is valid */
127 if (TTE_IS_VALID(tlb->tte)) {
128 CPUState *cs = env_cpu(env);
129
130 size = 8192ULL << 3 * TTE_PGSIZE(tlb->tte);
131 mask = 1ULL + ~size;
132
133 va = tlb->tag & mask;
134
135 for (offset = 0; offset < size; offset += TARGET_PAGE_SIZE) {
136 tlb_flush_page(cs, va + offset);
137 }
138 }
139
140 tlb->tag = tlb_tag;
141 tlb->tte = tlb_tte;
142 }
143
144 static void demap_tlb(SparcTLBEntry *tlb, target_ulong demap_addr,
145 const char *strmmu, CPUSPARCState *env1)
146 {
147 unsigned int i;
148 target_ulong mask;
149 uint64_t context;
150
151 int is_demap_context = (demap_addr >> 6) & 1;
152
153 /* demap context */
154 switch ((demap_addr >> 4) & 3) {
155 case 0: /* primary */
156 context = env1->dmmu.mmu_primary_context;
157 break;
158 case 1: /* secondary */
159 context = env1->dmmu.mmu_secondary_context;
160 break;
161 case 2: /* nucleus */
162 context = 0;
163 break;
164 case 3: /* reserved */
165 default:
166 return;
167 }
168
169 for (i = 0; i < 64; i++) {
170 if (TTE_IS_VALID(tlb[i].tte)) {
171
172 if (is_demap_context) {
173 /* will remove non-global entries matching context value */
174 if (TTE_IS_GLOBAL(tlb[i].tte) ||
175 !tlb_compare_context(&tlb[i], context)) {
176 continue;
177 }
178 } else {
179 /* demap page
180 will remove any entry matching VA */
181 mask = 0xffffffffffffe000ULL;
182 mask <<= 3 * ((tlb[i].tte >> 61) & 3);
183
184 if (!compare_masked(demap_addr, tlb[i].tag, mask)) {
185 continue;
186 }
187
188 /* entry should be global or matching context value */
189 if (!TTE_IS_GLOBAL(tlb[i].tte) &&
190 !tlb_compare_context(&tlb[i], context)) {
191 continue;
192 }
193 }
194
195 replace_tlb_entry(&tlb[i], 0, 0, env1);
196 #ifdef DEBUG_MMU
197 DPRINTF_MMU("%s demap invalidated entry [%02u]\n", strmmu, i);
198 dump_mmu(env1);
199 #endif
200 }
201 }
202 }
203
204 static uint64_t sun4v_tte_to_sun4u(CPUSPARCState *env, uint64_t tag,
205 uint64_t sun4v_tte)
206 {
207 uint64_t sun4u_tte;
208 if (!(cpu_has_hypervisor(env) && (tag & TLB_UST1_IS_SUN4V_BIT))) {
209 /* is already in the sun4u format */
210 return sun4v_tte;
211 }
212 sun4u_tte = TTE_PA(sun4v_tte) | (sun4v_tte & TTE_VALID_BIT);
213 sun4u_tte |= (sun4v_tte & 3ULL) << 61; /* TTE_PGSIZE */
214 sun4u_tte |= CONVERT_BIT(sun4v_tte, TTE_NFO_BIT_UA2005, TTE_NFO_BIT);
215 sun4u_tte |= CONVERT_BIT(sun4v_tte, TTE_USED_BIT_UA2005, TTE_USED_BIT);
216 sun4u_tte |= CONVERT_BIT(sun4v_tte, TTE_W_OK_BIT_UA2005, TTE_W_OK_BIT);
217 sun4u_tte |= CONVERT_BIT(sun4v_tte, TTE_SIDEEFFECT_BIT_UA2005,
218 TTE_SIDEEFFECT_BIT);
219 sun4u_tte |= CONVERT_BIT(sun4v_tte, TTE_PRIV_BIT_UA2005, TTE_PRIV_BIT);
220 sun4u_tte |= CONVERT_BIT(sun4v_tte, TTE_LOCKED_BIT_UA2005, TTE_LOCKED_BIT);
221 return sun4u_tte;
222 }
223
224 static void replace_tlb_1bit_lru(SparcTLBEntry *tlb,
225 uint64_t tlb_tag, uint64_t tlb_tte,
226 const char *strmmu, CPUSPARCState *env1,
227 uint64_t addr)
228 {
229 unsigned int i, replace_used;
230
231 tlb_tte = sun4v_tte_to_sun4u(env1, addr, tlb_tte);
232 if (cpu_has_hypervisor(env1)) {
233 uint64_t new_vaddr = tlb_tag & ~0x1fffULL;
234 uint64_t new_size = 8192ULL << 3 * TTE_PGSIZE(tlb_tte);
235 uint32_t new_ctx = tlb_tag & 0x1fffU;
236 for (i = 0; i < 64; i++) {
237 uint32_t ctx = tlb[i].tag & 0x1fffU;
238 /* check if new mapping overlaps an existing one */
239 if (new_ctx == ctx) {
240 uint64_t vaddr = tlb[i].tag & ~0x1fffULL;
241 uint64_t size = 8192ULL << 3 * TTE_PGSIZE(tlb[i].tte);
242 if (new_vaddr == vaddr
243 || (new_vaddr < vaddr + size
244 && vaddr < new_vaddr + new_size)) {
245 DPRINTF_MMU("auto demap entry [%d] %lx->%lx\n", i, vaddr,
246 new_vaddr);
247 replace_tlb_entry(&tlb[i], tlb_tag, tlb_tte, env1);
248 return;
249 }
250 }
251
252 }
253 }
254 /* Try replacing invalid entry */
255 for (i = 0; i < 64; i++) {
256 if (!TTE_IS_VALID(tlb[i].tte)) {
257 replace_tlb_entry(&tlb[i], tlb_tag, tlb_tte, env1);
258 #ifdef DEBUG_MMU
259 DPRINTF_MMU("%s lru replaced invalid entry [%i]\n", strmmu, i);
260 dump_mmu(env1);
261 #endif
262 return;
263 }
264 }
265
266 /* All entries are valid, try replacing unlocked entry */
267
268 for (replace_used = 0; replace_used < 2; ++replace_used) {
269
270 /* Used entries are not replaced on first pass */
271
272 for (i = 0; i < 64; i++) {
273 if (!TTE_IS_LOCKED(tlb[i].tte) && !TTE_IS_USED(tlb[i].tte)) {
274
275 replace_tlb_entry(&tlb[i], tlb_tag, tlb_tte, env1);
276 #ifdef DEBUG_MMU
277 DPRINTF_MMU("%s lru replaced unlocked %s entry [%i]\n",
278 strmmu, (replace_used ? "used" : "unused"), i);
279 dump_mmu(env1);
280 #endif
281 return;
282 }
283 }
284
285 /* Now reset used bit and search for unused entries again */
286
287 for (i = 0; i < 64; i++) {
288 TTE_SET_UNUSED(tlb[i].tte);
289 }
290 }
291
292 #ifdef DEBUG_MMU
293 DPRINTF_MMU("%s lru replacement: no free entries available, "
294 "replacing the last one\n", strmmu);
295 #endif
296 /* corner case: the last entry is replaced anyway */
297 replace_tlb_entry(&tlb[63], tlb_tag, tlb_tte, env1);
298 }
299
300 #endif
301
302 #ifdef TARGET_SPARC64
303 /* returns true if access using this ASI is to have address translated by MMU
304 otherwise access is to raw physical address */
305 /* TODO: check sparc32 bits */
306 static inline int is_translating_asi(int asi)
307 {
308 /* Ultrasparc IIi translating asi
309 - note this list is defined by cpu implementation
310 */
311 switch (asi) {
312 case 0x04 ... 0x11:
313 case 0x16 ... 0x19:
314 case 0x1E ... 0x1F:
315 case 0x24 ... 0x2C:
316 case 0x70 ... 0x73:
317 case 0x78 ... 0x79:
318 case 0x80 ... 0xFF:
319 return 1;
320
321 default:
322 return 0;
323 }
324 }
325
326 static inline target_ulong address_mask(CPUSPARCState *env1, target_ulong addr)
327 {
328 if (AM_CHECK(env1)) {
329 addr &= 0xffffffffULL;
330 }
331 return addr;
332 }
333
334 static inline target_ulong asi_address_mask(CPUSPARCState *env,
335 int asi, target_ulong addr)
336 {
337 if (is_translating_asi(asi)) {
338 addr = address_mask(env, addr);
339 }
340 return addr;
341 }
342
343 #ifndef CONFIG_USER_ONLY
344 static inline void do_check_asi(CPUSPARCState *env, int asi, uintptr_t ra)
345 {
346 /* ASIs >= 0x80 are user mode.
347 * ASIs >= 0x30 are hyper mode (or super if hyper is not available).
348 * ASIs <= 0x2f are super mode.
349 */
350 if (asi < 0x80
351 && !cpu_hypervisor_mode(env)
352 && (!cpu_supervisor_mode(env)
353 || (asi >= 0x30 && cpu_has_hypervisor(env)))) {
354 cpu_raise_exception_ra(env, TT_PRIV_ACT, ra);
355 }
356 }
357 #endif /* !CONFIG_USER_ONLY */
358 #endif
359
360 #if defined(TARGET_SPARC64) || !defined(CONFIG_USER_ONLY)
361 static void do_check_align(CPUSPARCState *env, target_ulong addr,
362 uint32_t align, uintptr_t ra)
363 {
364 if (addr & align) {
365 cpu_raise_exception_ra(env, TT_UNALIGNED, ra);
366 }
367 }
368 #endif
369
370 #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) && \
371 defined(DEBUG_MXCC)
372 static void dump_mxcc(CPUSPARCState *env)
373 {
374 printf("mxccdata: %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64
375 "\n",
376 env->mxccdata[0], env->mxccdata[1],
377 env->mxccdata[2], env->mxccdata[3]);
378 printf("mxccregs: %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64
379 "\n"
380 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64
381 "\n",
382 env->mxccregs[0], env->mxccregs[1],
383 env->mxccregs[2], env->mxccregs[3],
384 env->mxccregs[4], env->mxccregs[5],
385 env->mxccregs[6], env->mxccregs[7]);
386 }
387 #endif
388
389 #if (defined(TARGET_SPARC64) || !defined(CONFIG_USER_ONLY)) \
390 && defined(DEBUG_ASI)
391 static void dump_asi(const char *txt, target_ulong addr, int asi, int size,
392 uint64_t r1)
393 {
394 switch (size) {
395 case 1:
396 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %02" PRIx64 "\n", txt,
397 addr, asi, r1 & 0xff);
398 break;
399 case 2:
400 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %04" PRIx64 "\n", txt,
401 addr, asi, r1 & 0xffff);
402 break;
403 case 4:
404 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %08" PRIx64 "\n", txt,
405 addr, asi, r1 & 0xffffffff);
406 break;
407 case 8:
408 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %016" PRIx64 "\n", txt,
409 addr, asi, r1);
410 break;
411 }
412 }
413 #endif
414
415 #ifndef CONFIG_USER_ONLY
416 #ifndef TARGET_SPARC64
417 static void sparc_raise_mmu_fault(CPUState *cs, hwaddr addr,
418 bool is_write, bool is_exec, int is_asi,
419 unsigned size, uintptr_t retaddr)
420 {
421 SPARCCPU *cpu = SPARC_CPU(cs);
422 CPUSPARCState *env = &cpu->env;
423 int fault_type;
424
425 #ifdef DEBUG_UNASSIGNED
426 if (is_asi) {
427 printf("Unassigned mem %s access of %d byte%s to " HWADDR_FMT_plx
428 " asi 0x%02x from " TARGET_FMT_lx "\n",
429 is_exec ? "exec" : is_write ? "write" : "read", size,
430 size == 1 ? "" : "s", addr, is_asi, env->pc);
431 } else {
432 printf("Unassigned mem %s access of %d byte%s to " HWADDR_FMT_plx
433 " from " TARGET_FMT_lx "\n",
434 is_exec ? "exec" : is_write ? "write" : "read", size,
435 size == 1 ? "" : "s", addr, env->pc);
436 }
437 #endif
438 /* Don't overwrite translation and access faults */
439 fault_type = (env->mmuregs[3] & 0x1c) >> 2;
440 if ((fault_type > 4) || (fault_type == 0)) {
441 env->mmuregs[3] = 0; /* Fault status register */
442 if (is_asi) {
443 env->mmuregs[3] |= 1 << 16;
444 }
445 if (env->psrs) {
446 env->mmuregs[3] |= 1 << 5;
447 }
448 if (is_exec) {
449 env->mmuregs[3] |= 1 << 6;
450 }
451 if (is_write) {
452 env->mmuregs[3] |= 1 << 7;
453 }
454 env->mmuregs[3] |= (5 << 2) | 2;
455 /* SuperSPARC will never place instruction fault addresses in the FAR */
456 if (!is_exec) {
457 env->mmuregs[4] = addr; /* Fault address register */
458 }
459 }
460 /* overflow (same type fault was not read before another fault) */
461 if (fault_type == ((env->mmuregs[3] & 0x1c)) >> 2) {
462 env->mmuregs[3] |= 1;
463 }
464
465 if ((env->mmuregs[0] & MMU_E) && !(env->mmuregs[0] & MMU_NF)) {
466 int tt = is_exec ? TT_CODE_ACCESS : TT_DATA_ACCESS;
467 cpu_raise_exception_ra(env, tt, retaddr);
468 }
469
470 /*
471 * flush neverland mappings created during no-fault mode,
472 * so the sequential MMU faults report proper fault types
473 */
474 if (env->mmuregs[0] & MMU_NF) {
475 tlb_flush(cs);
476 }
477 }
478 #else
479 static void sparc_raise_mmu_fault(CPUState *cs, hwaddr addr,
480 bool is_write, bool is_exec, int is_asi,
481 unsigned size, uintptr_t retaddr)
482 {
483 SPARCCPU *cpu = SPARC_CPU(cs);
484 CPUSPARCState *env = &cpu->env;
485
486 #ifdef DEBUG_UNASSIGNED
487 printf("Unassigned mem access to " HWADDR_FMT_plx " from " TARGET_FMT_lx
488 "\n", addr, env->pc);
489 #endif
490
491 if (is_exec) { /* XXX has_hypervisor */
492 if (env->lsu & (IMMU_E)) {
493 cpu_raise_exception_ra(env, TT_CODE_ACCESS, retaddr);
494 } else if (cpu_has_hypervisor(env) && !(env->hpstate & HS_PRIV)) {
495 cpu_raise_exception_ra(env, TT_INSN_REAL_TRANSLATION_MISS, retaddr);
496 }
497 } else {
498 if (env->lsu & (DMMU_E)) {
499 cpu_raise_exception_ra(env, TT_DATA_ACCESS, retaddr);
500 } else if (cpu_has_hypervisor(env) && !(env->hpstate & HS_PRIV)) {
501 cpu_raise_exception_ra(env, TT_DATA_REAL_TRANSLATION_MISS, retaddr);
502 }
503 }
504 }
505 #endif
506 #endif
507
508 #ifndef TARGET_SPARC64
509 #ifndef CONFIG_USER_ONLY
510
511
512 /* Leon3 cache control */
513
514 static void leon3_cache_control_st(CPUSPARCState *env, target_ulong addr,
515 uint64_t val, int size)
516 {
517 DPRINTF_CACHE_CONTROL("st addr:%08x, val:%" PRIx64 ", size:%d\n",
518 addr, val, size);
519
520 if (size != 4) {
521 DPRINTF_CACHE_CONTROL("32bits only\n");
522 return;
523 }
524
525 switch (addr) {
526 case 0x00: /* Cache control */
527
528 /* These values must always be read as zeros */
529 val &= ~CACHE_CTRL_FD;
530 val &= ~CACHE_CTRL_FI;
531 val &= ~CACHE_CTRL_IB;
532 val &= ~CACHE_CTRL_IP;
533 val &= ~CACHE_CTRL_DP;
534
535 env->cache_control = val;
536 break;
537 case 0x04: /* Instruction cache configuration */
538 case 0x08: /* Data cache configuration */
539 /* Read Only */
540 break;
541 default:
542 DPRINTF_CACHE_CONTROL("write unknown register %08x\n", addr);
543 break;
544 };
545 }
546
547 static uint64_t leon3_cache_control_ld(CPUSPARCState *env, target_ulong addr,
548 int size)
549 {
550 uint64_t ret = 0;
551
552 if (size != 4) {
553 DPRINTF_CACHE_CONTROL("32bits only\n");
554 return 0;
555 }
556
557 switch (addr) {
558 case 0x00: /* Cache control */
559 ret = env->cache_control;
560 break;
561
562 /* Configuration registers are read and only always keep those
563 predefined values */
564
565 case 0x04: /* Instruction cache configuration */
566 ret = 0x10220000;
567 break;
568 case 0x08: /* Data cache configuration */
569 ret = 0x18220000;
570 break;
571 default:
572 DPRINTF_CACHE_CONTROL("read unknown register %08x\n", addr);
573 break;
574 };
575 DPRINTF_CACHE_CONTROL("ld addr:%08x, ret:0x%" PRIx64 ", size:%d\n",
576 addr, ret, size);
577 return ret;
578 }
579
580 uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr,
581 int asi, uint32_t memop)
582 {
583 int size = 1 << (memop & MO_SIZE);
584 int sign = memop & MO_SIGN;
585 CPUState *cs = env_cpu(env);
586 uint64_t ret = 0;
587 #if defined(DEBUG_MXCC) || defined(DEBUG_ASI)
588 uint32_t last_addr = addr;
589 #endif
590 MemOpIdx oi;
591
592 do_check_align(env, addr, size - 1, GETPC());
593 switch (asi) {
594 case ASI_M_MXCC: /* SuperSparc MXCC registers, or... */
595 /* case ASI_LEON_CACHEREGS: Leon3 cache control */
596 switch (addr) {
597 case 0x00: /* Leon3 Cache Control */
598 case 0x08: /* Leon3 Instruction Cache config */
599 case 0x0C: /* Leon3 Date Cache config */
600 if (env->def.features & CPU_FEATURE_CACHE_CTRL) {
601 ret = leon3_cache_control_ld(env, addr, size);
602 }
603 break;
604 case 0x01c00a00: /* MXCC control register */
605 if (size == 8) {
606 ret = env->mxccregs[3];
607 } else {
608 qemu_log_mask(LOG_UNIMP,
609 "%08x: unimplemented access size: %d\n", addr,
610 size);
611 }
612 break;
613 case 0x01c00a04: /* MXCC control register */
614 if (size == 4) {
615 ret = env->mxccregs[3];
616 } else {
617 qemu_log_mask(LOG_UNIMP,
618 "%08x: unimplemented access size: %d\n", addr,
619 size);
620 }
621 break;
622 case 0x01c00c00: /* Module reset register */
623 if (size == 8) {
624 ret = env->mxccregs[5];
625 /* should we do something here? */
626 } else {
627 qemu_log_mask(LOG_UNIMP,
628 "%08x: unimplemented access size: %d\n", addr,
629 size);
630 }
631 break;
632 case 0x01c00f00: /* MBus port address register */
633 if (size == 8) {
634 ret = env->mxccregs[7];
635 } else {
636 qemu_log_mask(LOG_UNIMP,
637 "%08x: unimplemented access size: %d\n", addr,
638 size);
639 }
640 break;
641 default:
642 qemu_log_mask(LOG_UNIMP,
643 "%08x: unimplemented address, size: %d\n", addr,
644 size);
645 break;
646 }
647 DPRINTF_MXCC("asi = %d, size = %d, sign = %d, "
648 "addr = %08x -> ret = %" PRIx64 ","
649 "addr = %08x\n", asi, size, sign, last_addr, ret, addr);
650 #ifdef DEBUG_MXCC
651 dump_mxcc(env);
652 #endif
653 break;
654 case ASI_M_FLUSH_PROBE: /* SuperSparc MMU probe */
655 case ASI_LEON_MMUFLUSH: /* LEON3 MMU probe */
656 {
657 int mmulev;
658
659 mmulev = (addr >> 8) & 15;
660 if (mmulev > 4) {
661 ret = 0;
662 } else {
663 ret = mmu_probe(env, addr, mmulev);
664 }
665 DPRINTF_MMU("mmu_probe: 0x%08x (lev %d) -> 0x%08" PRIx64 "\n",
666 addr, mmulev, ret);
667 }
668 break;
669 case ASI_M_MMUREGS: /* SuperSparc MMU regs */
670 case ASI_LEON_MMUREGS: /* LEON3 MMU regs */
671 {
672 int reg = (addr >> 8) & 0x1f;
673
674 ret = env->mmuregs[reg];
675 if (reg == 3) { /* Fault status cleared on read */
676 env->mmuregs[3] = 0;
677 } else if (reg == 0x13) { /* Fault status read */
678 ret = env->mmuregs[3];
679 } else if (reg == 0x14) { /* Fault address read */
680 ret = env->mmuregs[4];
681 }
682 DPRINTF_MMU("mmu_read: reg[%d] = 0x%08" PRIx64 "\n", reg, ret);
683 }
684 break;
685 case ASI_M_TLBDIAG: /* Turbosparc ITLB Diagnostic */
686 case ASI_M_DIAGS: /* Turbosparc DTLB Diagnostic */
687 case ASI_M_IODIAG: /* Turbosparc IOTLB Diagnostic */
688 break;
689 case ASI_KERNELTXT: /* Supervisor code access */
690 oi = make_memop_idx(memop, cpu_mmu_index(env_cpu(env), true));
691 switch (size) {
692 case 1:
693 ret = cpu_ldb_code_mmu(env, addr, oi, GETPC());
694 break;
695 case 2:
696 ret = cpu_ldw_code_mmu(env, addr, oi, GETPC());
697 break;
698 default:
699 case 4:
700 ret = cpu_ldl_code_mmu(env, addr, oi, GETPC());
701 break;
702 case 8:
703 ret = cpu_ldq_code_mmu(env, addr, oi, GETPC());
704 break;
705 }
706 break;
707 case ASI_M_TXTC_TAG: /* SparcStation 5 I-cache tag */
708 case ASI_M_TXTC_DATA: /* SparcStation 5 I-cache data */
709 case ASI_M_DATAC_TAG: /* SparcStation 5 D-cache tag */
710 case ASI_M_DATAC_DATA: /* SparcStation 5 D-cache data */
711 break;
712 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
713 {
714 MemTxResult result;
715 hwaddr access_addr = (hwaddr)addr | ((hwaddr)(asi & 0xf) << 32);
716
717 switch (size) {
718 case 1:
719 ret = address_space_ldub(cs->as, access_addr,
720 MEMTXATTRS_UNSPECIFIED, &result);
721 break;
722 case 2:
723 ret = address_space_lduw(cs->as, access_addr,
724 MEMTXATTRS_UNSPECIFIED, &result);
725 break;
726 default:
727 case 4:
728 ret = address_space_ldl(cs->as, access_addr,
729 MEMTXATTRS_UNSPECIFIED, &result);
730 break;
731 case 8:
732 ret = address_space_ldq(cs->as, access_addr,
733 MEMTXATTRS_UNSPECIFIED, &result);
734 break;
735 }
736
737 if (result != MEMTX_OK) {
738 sparc_raise_mmu_fault(cs, access_addr, false, false, false,
739 size, GETPC());
740 }
741 break;
742 }
743 case 0x30: /* Turbosparc secondary cache diagnostic */
744 case 0x31: /* Turbosparc RAM snoop */
745 case 0x32: /* Turbosparc page table descriptor diagnostic */
746 case 0x39: /* data cache diagnostic register */
747 ret = 0;
748 break;
749 case 0x38: /* SuperSPARC MMU Breakpoint Control Registers */
750 {
751 int reg = (addr >> 8) & 3;
752
753 switch (reg) {
754 case 0: /* Breakpoint Value (Addr) */
755 ret = env->mmubpregs[reg];
756 break;
757 case 1: /* Breakpoint Mask */
758 ret = env->mmubpregs[reg];
759 break;
760 case 2: /* Breakpoint Control */
761 ret = env->mmubpregs[reg];
762 break;
763 case 3: /* Breakpoint Status */
764 ret = env->mmubpregs[reg];
765 env->mmubpregs[reg] = 0ULL;
766 break;
767 }
768 DPRINTF_MMU("read breakpoint reg[%d] 0x%016" PRIx64 "\n", reg,
769 ret);
770 }
771 break;
772 case 0x49: /* SuperSPARC MMU Counter Breakpoint Value */
773 ret = env->mmubpctrv;
774 break;
775 case 0x4a: /* SuperSPARC MMU Counter Breakpoint Control */
776 ret = env->mmubpctrc;
777 break;
778 case 0x4b: /* SuperSPARC MMU Counter Breakpoint Status */
779 ret = env->mmubpctrs;
780 break;
781 case 0x4c: /* SuperSPARC MMU Breakpoint Action */
782 ret = env->mmubpaction;
783 break;
784 case ASI_USERTXT: /* User code access, XXX */
785 default:
786 sparc_raise_mmu_fault(cs, addr, false, false, asi, size, GETPC());
787 ret = 0;
788 break;
789
790 case ASI_USERDATA: /* User data access */
791 case ASI_KERNELDATA: /* Supervisor data access */
792 case ASI_P: /* Implicit primary context data access (v9 only?) */
793 case ASI_M_BYPASS: /* MMU passthrough */
794 case ASI_LEON_BYPASS: /* LEON MMU passthrough */
795 /* These are always handled inline. */
796 g_assert_not_reached();
797 }
798 if (sign) {
799 switch (size) {
800 case 1:
801 ret = (int8_t) ret;
802 break;
803 case 2:
804 ret = (int16_t) ret;
805 break;
806 case 4:
807 ret = (int32_t) ret;
808 break;
809 default:
810 break;
811 }
812 }
813 #ifdef DEBUG_ASI
814 dump_asi("read ", last_addr, asi, size, ret);
815 #endif
816 return ret;
817 }
818
819 void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val,
820 int asi, uint32_t memop)
821 {
822 int size = 1 << (memop & MO_SIZE);
823 CPUState *cs = env_cpu(env);
824
825 do_check_align(env, addr, size - 1, GETPC());
826 switch (asi) {
827 case ASI_M_MXCC: /* SuperSparc MXCC registers, or... */
828 /* case ASI_LEON_CACHEREGS: Leon3 cache control */
829 switch (addr) {
830 case 0x00: /* Leon3 Cache Control */
831 case 0x08: /* Leon3 Instruction Cache config */
832 case 0x0C: /* Leon3 Date Cache config */
833 if (env->def.features & CPU_FEATURE_CACHE_CTRL) {
834 leon3_cache_control_st(env, addr, val, size);
835 }
836 break;
837
838 case 0x01c00000: /* MXCC stream data register 0 */
839 if (size == 8) {
840 env->mxccdata[0] = val;
841 } else {
842 qemu_log_mask(LOG_UNIMP,
843 "%08x: unimplemented access size: %d\n", addr,
844 size);
845 }
846 break;
847 case 0x01c00008: /* MXCC stream data register 1 */
848 if (size == 8) {
849 env->mxccdata[1] = val;
850 } else {
851 qemu_log_mask(LOG_UNIMP,
852 "%08x: unimplemented access size: %d\n", addr,
853 size);
854 }
855 break;
856 case 0x01c00010: /* MXCC stream data register 2 */
857 if (size == 8) {
858 env->mxccdata[2] = val;
859 } else {
860 qemu_log_mask(LOG_UNIMP,
861 "%08x: unimplemented access size: %d\n", addr,
862 size);
863 }
864 break;
865 case 0x01c00018: /* MXCC stream data register 3 */
866 if (size == 8) {
867 env->mxccdata[3] = val;
868 } else {
869 qemu_log_mask(LOG_UNIMP,
870 "%08x: unimplemented access size: %d\n", addr,
871 size);
872 }
873 break;
874 case 0x01c00100: /* MXCC stream source */
875 {
876 int i;
877
878 if (size == 8) {
879 env->mxccregs[0] = val;
880 } else {
881 qemu_log_mask(LOG_UNIMP,
882 "%08x: unimplemented access size: %d\n", addr,
883 size);
884 }
885
886 for (i = 0; i < 4; i++) {
887 MemTxResult result;
888 hwaddr access_addr = (env->mxccregs[0] & 0xffffffffULL) + 8 * i;
889
890 env->mxccdata[i] = address_space_ldq(cs->as,
891 access_addr,
892 MEMTXATTRS_UNSPECIFIED,
893 &result);
894 if (result != MEMTX_OK) {
895 /* TODO: investigate whether this is the right behaviour */
896 sparc_raise_mmu_fault(cs, access_addr, false, false,
897 false, size, GETPC());
898 }
899 }
900 break;
901 }
902 case 0x01c00200: /* MXCC stream destination */
903 {
904 int i;
905
906 if (size == 8) {
907 env->mxccregs[1] = val;
908 } else {
909 qemu_log_mask(LOG_UNIMP,
910 "%08x: unimplemented access size: %d\n", addr,
911 size);
912 }
913
914 for (i = 0; i < 4; i++) {
915 MemTxResult result;
916 hwaddr access_addr = (env->mxccregs[1] & 0xffffffffULL) + 8 * i;
917
918 address_space_stq(cs->as, access_addr, env->mxccdata[i],
919 MEMTXATTRS_UNSPECIFIED, &result);
920
921 if (result != MEMTX_OK) {
922 /* TODO: investigate whether this is the right behaviour */
923 sparc_raise_mmu_fault(cs, access_addr, true, false,
924 false, size, GETPC());
925 }
926 }
927 break;
928 }
929 case 0x01c00a00: /* MXCC control register */
930 if (size == 8) {
931 env->mxccregs[3] = val;
932 } else {
933 qemu_log_mask(LOG_UNIMP,
934 "%08x: unimplemented access size: %d\n", addr,
935 size);
936 }
937 break;
938 case 0x01c00a04: /* MXCC control register */
939 if (size == 4) {
940 env->mxccregs[3] = (env->mxccregs[3] & 0xffffffff00000000ULL)
941 | val;
942 } else {
943 qemu_log_mask(LOG_UNIMP,
944 "%08x: unimplemented access size: %d\n", addr,
945 size);
946 }
947 break;
948 case 0x01c00e00: /* MXCC error register */
949 /* writing a 1 bit clears the error */
950 if (size == 8) {
951 env->mxccregs[6] &= ~val;
952 } else {
953 qemu_log_mask(LOG_UNIMP,
954 "%08x: unimplemented access size: %d\n", addr,
955 size);
956 }
957 break;
958 case 0x01c00f00: /* MBus port address register */
959 if (size == 8) {
960 env->mxccregs[7] = val;
961 } else {
962 qemu_log_mask(LOG_UNIMP,
963 "%08x: unimplemented access size: %d\n", addr,
964 size);
965 }
966 break;
967 default:
968 qemu_log_mask(LOG_UNIMP,
969 "%08x: unimplemented address, size: %d\n", addr,
970 size);
971 break;
972 }
973 DPRINTF_MXCC("asi = %d, size = %d, addr = %08x, val = %" PRIx64 "\n",
974 asi, size, addr, val);
975 #ifdef DEBUG_MXCC
976 dump_mxcc(env);
977 #endif
978 break;
979 case ASI_M_FLUSH_PROBE: /* SuperSparc MMU flush */
980 case ASI_LEON_MMUFLUSH: /* LEON3 MMU flush */
981 {
982 int mmulev;
983
984 mmulev = (addr >> 8) & 15;
985 DPRINTF_MMU("mmu flush level %d\n", mmulev);
986 switch (mmulev) {
987 case 0: /* flush page */
988 tlb_flush_page(cs, addr & 0xfffff000);
989 break;
990 case 1: /* flush segment (256k) */
991 case 2: /* flush region (16M) */
992 case 3: /* flush context (4G) */
993 case 4: /* flush entire */
994 tlb_flush(cs);
995 break;
996 default:
997 break;
998 }
999 #ifdef DEBUG_MMU
1000 dump_mmu(env);
1001 #endif
1002 }
1003 break;
1004 case ASI_M_MMUREGS: /* write MMU regs */
1005 case ASI_LEON_MMUREGS: /* LEON3 write MMU regs */
1006 {
1007 int reg = (addr >> 8) & 0x1f;
1008 uint32_t oldreg;
1009
1010 oldreg = env->mmuregs[reg];
1011 switch (reg) {
1012 case 0: /* Control Register */
1013 env->mmuregs[reg] = (env->mmuregs[reg] & 0xff000000) |
1014 (val & 0x00ffffff);
1015 /* Mappings generated during no-fault mode
1016 are invalid in normal mode. */
1017 if ((oldreg ^ env->mmuregs[reg])
1018 & (MMU_NF | env->def.mmu_bm)) {
1019 tlb_flush(cs);
1020 }
1021 break;
1022 case 1: /* Context Table Pointer Register */
1023 env->mmuregs[reg] = val & env->def.mmu_ctpr_mask;
1024 break;
1025 case 2: /* Context Register */
1026 env->mmuregs[reg] = val & env->def.mmu_cxr_mask;
1027 if (oldreg != env->mmuregs[reg]) {
1028 /* we flush when the MMU context changes because
1029 QEMU has no MMU context support */
1030 tlb_flush(cs);
1031 }
1032 break;
1033 case 3: /* Synchronous Fault Status Register with Clear */
1034 case 4: /* Synchronous Fault Address Register */
1035 break;
1036 case 0x10: /* TLB Replacement Control Register */
1037 env->mmuregs[reg] = val & env->def.mmu_trcr_mask;
1038 break;
1039 case 0x13: /* Synchronous Fault Status Register with Read
1040 and Clear */
1041 env->mmuregs[3] = val & env->def.mmu_sfsr_mask;
1042 break;
1043 case 0x14: /* Synchronous Fault Address Register */
1044 env->mmuregs[4] = val;
1045 break;
1046 default:
1047 env->mmuregs[reg] = val;
1048 break;
1049 }
1050 if (oldreg != env->mmuregs[reg]) {
1051 DPRINTF_MMU("mmu change reg[%d]: 0x%08x -> 0x%08x\n",
1052 reg, oldreg, env->mmuregs[reg]);
1053 }
1054 #ifdef DEBUG_MMU
1055 dump_mmu(env);
1056 #endif
1057 }
1058 break;
1059 case ASI_M_TLBDIAG: /* Turbosparc ITLB Diagnostic */
1060 case ASI_M_DIAGS: /* Turbosparc DTLB Diagnostic */
1061 case ASI_M_IODIAG: /* Turbosparc IOTLB Diagnostic */
1062 break;
1063 case ASI_M_TXTC_TAG: /* I-cache tag */
1064 case ASI_M_TXTC_DATA: /* I-cache data */
1065 case ASI_M_DATAC_TAG: /* D-cache tag */
1066 case ASI_M_DATAC_DATA: /* D-cache data */
1067 case ASI_M_FLUSH_PAGE: /* I/D-cache flush page */
1068 case ASI_M_FLUSH_SEG: /* I/D-cache flush segment */
1069 case ASI_M_FLUSH_REGION: /* I/D-cache flush region */
1070 case ASI_M_FLUSH_CTX: /* I/D-cache flush context */
1071 case ASI_M_FLUSH_USER: /* I/D-cache flush user */
1072 break;
1073 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
1074 {
1075 MemTxResult result;
1076 hwaddr access_addr = (hwaddr)addr | ((hwaddr)(asi & 0xf) << 32);
1077
1078 switch (size) {
1079 case 1:
1080 address_space_stb(cs->as, access_addr, val,
1081 MEMTXATTRS_UNSPECIFIED, &result);
1082 break;
1083 case 2:
1084 address_space_stw(cs->as, access_addr, val,
1085 MEMTXATTRS_UNSPECIFIED, &result);
1086 break;
1087 case 4:
1088 default:
1089 address_space_stl(cs->as, access_addr, val,
1090 MEMTXATTRS_UNSPECIFIED, &result);
1091 break;
1092 case 8:
1093 address_space_stq(cs->as, access_addr, val,
1094 MEMTXATTRS_UNSPECIFIED, &result);
1095 break;
1096 }
1097 if (result != MEMTX_OK) {
1098 sparc_raise_mmu_fault(cs, access_addr, true, false, false,
1099 size, GETPC());
1100 }
1101 }
1102 break;
1103 case 0x30: /* store buffer tags or Turbosparc secondary cache diagnostic */
1104 case 0x31: /* store buffer data, Ross RT620 I-cache flush or
1105 Turbosparc snoop RAM */
1106 case 0x32: /* store buffer control or Turbosparc page table
1107 descriptor diagnostic */
1108 case 0x36: /* I-cache flash clear */
1109 case 0x37: /* D-cache flash clear */
1110 break;
1111 case 0x38: /* SuperSPARC MMU Breakpoint Control Registers*/
1112 {
1113 int reg = (addr >> 8) & 3;
1114
1115 switch (reg) {
1116 case 0: /* Breakpoint Value (Addr) */
1117 env->mmubpregs[reg] = (val & 0xfffffffffULL);
1118 break;
1119 case 1: /* Breakpoint Mask */
1120 env->mmubpregs[reg] = (val & 0xfffffffffULL);
1121 break;
1122 case 2: /* Breakpoint Control */
1123 env->mmubpregs[reg] = (val & 0x7fULL);
1124 break;
1125 case 3: /* Breakpoint Status */
1126 env->mmubpregs[reg] = (val & 0xfULL);
1127 break;
1128 }
1129 DPRINTF_MMU("write breakpoint reg[%d] 0x%016x\n", reg,
1130 env->mmuregs[reg]);
1131 }
1132 break;
1133 case 0x49: /* SuperSPARC MMU Counter Breakpoint Value */
1134 env->mmubpctrv = val & 0xffffffff;
1135 break;
1136 case 0x4a: /* SuperSPARC MMU Counter Breakpoint Control */
1137 env->mmubpctrc = val & 0x3;
1138 break;
1139 case 0x4b: /* SuperSPARC MMU Counter Breakpoint Status */
1140 env->mmubpctrs = val & 0x3;
1141 break;
1142 case 0x4c: /* SuperSPARC MMU Breakpoint Action */
1143 env->mmubpaction = val & 0x1fff;
1144 break;
1145 case ASI_USERTXT: /* User code access, XXX */
1146 case ASI_KERNELTXT: /* Supervisor code access, XXX */
1147 default:
1148 sparc_raise_mmu_fault(cs, addr, true, false, asi, size, GETPC());
1149 break;
1150
1151 case ASI_USERDATA: /* User data access */
1152 case ASI_KERNELDATA: /* Supervisor data access */
1153 case ASI_P:
1154 case ASI_M_BYPASS: /* MMU passthrough */
1155 case ASI_LEON_BYPASS: /* LEON MMU passthrough */
1156 case ASI_M_BCOPY: /* Block copy, sta access */
1157 case ASI_M_BFILL: /* Block fill, stda access */
1158 /* These are always handled inline. */
1159 g_assert_not_reached();
1160 }
1161 #ifdef DEBUG_ASI
1162 dump_asi("write", addr, asi, size, val);
1163 #endif
1164 }
1165
1166 #endif /* CONFIG_USER_ONLY */
1167 #else /* TARGET_SPARC64 */
1168
1169 #ifdef CONFIG_USER_ONLY
1170 uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr,
1171 int asi, uint32_t memop)
1172 {
1173 int size = 1 << (memop & MO_SIZE);
1174 int sign = memop & MO_SIGN;
1175 uint64_t ret = 0;
1176
1177 if (asi < 0x80) {
1178 cpu_raise_exception_ra(env, TT_PRIV_ACT, GETPC());
1179 }
1180 do_check_align(env, addr, size - 1, GETPC());
1181 addr = asi_address_mask(env, asi, addr);
1182
1183 switch (asi) {
1184 case ASI_PNF: /* Primary no-fault */
1185 case ASI_PNFL: /* Primary no-fault LE */
1186 case ASI_SNF: /* Secondary no-fault */
1187 case ASI_SNFL: /* Secondary no-fault LE */
1188 if (!page_check_range(addr, size, PAGE_READ)) {
1189 ret = 0;
1190 break;
1191 }
1192 switch (size) {
1193 case 1:
1194 ret = cpu_ldub_data(env, addr);
1195 break;
1196 case 2:
1197 ret = cpu_lduw_data(env, addr);
1198 break;
1199 case 4:
1200 ret = cpu_ldl_data(env, addr);
1201 break;
1202 case 8:
1203 ret = cpu_ldq_data(env, addr);
1204 break;
1205 default:
1206 g_assert_not_reached();
1207 }
1208 break;
1209 break;
1210
1211 case ASI_P: /* Primary */
1212 case ASI_PL: /* Primary LE */
1213 case ASI_S: /* Secondary */
1214 case ASI_SL: /* Secondary LE */
1215 /* These are always handled inline. */
1216 g_assert_not_reached();
1217
1218 default:
1219 cpu_raise_exception_ra(env, TT_DATA_ACCESS, GETPC());
1220 }
1221
1222 /* Convert from little endian */
1223 switch (asi) {
1224 case ASI_PNFL: /* Primary no-fault LE */
1225 case ASI_SNFL: /* Secondary no-fault LE */
1226 switch (size) {
1227 case 2:
1228 ret = bswap16(ret);
1229 break;
1230 case 4:
1231 ret = bswap32(ret);
1232 break;
1233 case 8:
1234 ret = bswap64(ret);
1235 break;
1236 }
1237 }
1238
1239 /* Convert to signed number */
1240 if (sign) {
1241 switch (size) {
1242 case 1:
1243 ret = (int8_t) ret;
1244 break;
1245 case 2:
1246 ret = (int16_t) ret;
1247 break;
1248 case 4:
1249 ret = (int32_t) ret;
1250 break;
1251 }
1252 }
1253 #ifdef DEBUG_ASI
1254 dump_asi("read", addr, asi, size, ret);
1255 #endif
1256 return ret;
1257 }
1258
1259 void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val,
1260 int asi, uint32_t memop)
1261 {
1262 int size = 1 << (memop & MO_SIZE);
1263 #ifdef DEBUG_ASI
1264 dump_asi("write", addr, asi, size, val);
1265 #endif
1266 if (asi < 0x80) {
1267 cpu_raise_exception_ra(env, TT_PRIV_ACT, GETPC());
1268 }
1269 do_check_align(env, addr, size - 1, GETPC());
1270
1271 switch (asi) {
1272 case ASI_P: /* Primary */
1273 case ASI_PL: /* Primary LE */
1274 case ASI_S: /* Secondary */
1275 case ASI_SL: /* Secondary LE */
1276 /* These are always handled inline. */
1277 g_assert_not_reached();
1278
1279 case ASI_PNF: /* Primary no-fault, RO */
1280 case ASI_SNF: /* Secondary no-fault, RO */
1281 case ASI_PNFL: /* Primary no-fault LE, RO */
1282 case ASI_SNFL: /* Secondary no-fault LE, RO */
1283 default:
1284 cpu_raise_exception_ra(env, TT_DATA_ACCESS, GETPC());
1285 }
1286 }
1287
1288 #else /* CONFIG_USER_ONLY */
1289
1290 uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr,
1291 int asi, uint32_t memop)
1292 {
1293 int size = 1 << (memop & MO_SIZE);
1294 int sign = memop & MO_SIGN;
1295 CPUState *cs = env_cpu(env);
1296 uint64_t ret = 0;
1297 #if defined(DEBUG_ASI)
1298 target_ulong last_addr = addr;
1299 #endif
1300
1301 asi &= 0xff;
1302
1303 do_check_asi(env, asi, GETPC());
1304 do_check_align(env, addr, size - 1, GETPC());
1305 addr = asi_address_mask(env, asi, addr);
1306
1307 switch (asi) {
1308 case ASI_PNF:
1309 case ASI_PNFL:
1310 case ASI_SNF:
1311 case ASI_SNFL:
1312 {
1313 MemOpIdx oi;
1314 int idx = (env->pstate & PS_PRIV
1315 ? (asi & 1 ? MMU_KERNEL_SECONDARY_IDX : MMU_KERNEL_IDX)
1316 : (asi & 1 ? MMU_USER_SECONDARY_IDX : MMU_USER_IDX));
1317
1318 if (cpu_get_phys_page_nofault(env, addr, idx) == -1ULL) {
1319 #ifdef DEBUG_ASI
1320 dump_asi("read ", last_addr, asi, size, ret);
1321 #endif
1322 /* exception_index is set in get_physical_address_data. */
1323 cpu_raise_exception_ra(env, cs->exception_index, GETPC());
1324 }
1325 oi = make_memop_idx(memop, idx);
1326 switch (size) {
1327 case 1:
1328 ret = cpu_ldb_mmu(env, addr, oi, GETPC());
1329 break;
1330 case 2:
1331 ret = cpu_ldw_mmu(env, addr, oi, GETPC());
1332 break;
1333 case 4:
1334 ret = cpu_ldl_mmu(env, addr, oi, GETPC());
1335 break;
1336 case 8:
1337 ret = cpu_ldq_mmu(env, addr, oi, GETPC());
1338 break;
1339 default:
1340 g_assert_not_reached();
1341 }
1342 }
1343 break;
1344
1345 case ASI_AIUP: /* As if user primary */
1346 case ASI_AIUS: /* As if user secondary */
1347 case ASI_AIUPL: /* As if user primary LE */
1348 case ASI_AIUSL: /* As if user secondary LE */
1349 case ASI_P: /* Primary */
1350 case ASI_S: /* Secondary */
1351 case ASI_PL: /* Primary LE */
1352 case ASI_SL: /* Secondary LE */
1353 case ASI_REAL: /* Bypass */
1354 case ASI_REAL_IO: /* Bypass, non-cacheable */
1355 case ASI_REAL_L: /* Bypass LE */
1356 case ASI_REAL_IO_L: /* Bypass, non-cacheable LE */
1357 case ASI_N: /* Nucleus */
1358 case ASI_NL: /* Nucleus Little Endian (LE) */
1359 case ASI_NUCLEUS_QUAD_LDD: /* Nucleus quad LDD 128 bit atomic */
1360 case ASI_NUCLEUS_QUAD_LDD_L: /* Nucleus quad LDD 128 bit atomic LE */
1361 case ASI_TWINX_AIUP: /* As if user primary, twinx */
1362 case ASI_TWINX_AIUS: /* As if user secondary, twinx */
1363 case ASI_TWINX_REAL: /* Real address, twinx */
1364 case ASI_TWINX_AIUP_L: /* As if user primary, twinx, LE */
1365 case ASI_TWINX_AIUS_L: /* As if user secondary, twinx, LE */
1366 case ASI_TWINX_REAL_L: /* Real address, twinx, LE */
1367 case ASI_TWINX_N: /* Nucleus, twinx */
1368 case ASI_TWINX_NL: /* Nucleus, twinx, LE */
1369 /* ??? From the UA2011 document; overlaps BLK_INIT_QUAD_LDD_* */
1370 case ASI_TWINX_P: /* Primary, twinx */
1371 case ASI_TWINX_PL: /* Primary, twinx, LE */
1372 case ASI_TWINX_S: /* Secondary, twinx */
1373 case ASI_TWINX_SL: /* Secondary, twinx, LE */
1374 /* These are always handled inline. */
1375 g_assert_not_reached();
1376
1377 case ASI_UPA_CONFIG: /* UPA config */
1378 /* XXX */
1379 break;
1380 case ASI_LSU_CONTROL: /* LSU */
1381 ret = env->lsu;
1382 break;
1383 case ASI_IMMU: /* I-MMU regs */
1384 {
1385 int reg = (addr >> 3) & 0xf;
1386 switch (reg) {
1387 case 0:
1388 /* 0x00 I-TSB Tag Target register */
1389 ret = ultrasparc_tag_target(env->immu.tag_access);
1390 break;
1391 case 3: /* SFSR */
1392 ret = env->immu.sfsr;
1393 break;
1394 case 5: /* TSB access */
1395 ret = env->immu.tsb;
1396 break;
1397 case 6:
1398 /* 0x30 I-TSB Tag Access register */
1399 ret = env->immu.tag_access;
1400 break;
1401 default:
1402 sparc_raise_mmu_fault(cs, addr, false, false, 1, size, GETPC());
1403 ret = 0;
1404 }
1405 break;
1406 }
1407 case ASI_IMMU_TSB_8KB_PTR: /* I-MMU 8k TSB pointer */
1408 {
1409 /* env->immuregs[5] holds I-MMU TSB register value
1410 env->immuregs[6] holds I-MMU Tag Access register value */
1411 ret = ultrasparc_tsb_pointer(env, &env->immu, 0);
1412 break;
1413 }
1414 case ASI_IMMU_TSB_64KB_PTR: /* I-MMU 64k TSB pointer */
1415 {
1416 /* env->immuregs[5] holds I-MMU TSB register value
1417 env->immuregs[6] holds I-MMU Tag Access register value */
1418 ret = ultrasparc_tsb_pointer(env, &env->immu, 1);
1419 break;
1420 }
1421 case ASI_ITLB_DATA_ACCESS: /* I-MMU data access */
1422 {
1423 int reg = (addr >> 3) & 0x3f;
1424
1425 ret = env->itlb[reg].tte;
1426 break;
1427 }
1428 case ASI_ITLB_TAG_READ: /* I-MMU tag read */
1429 {
1430 int reg = (addr >> 3) & 0x3f;
1431
1432 ret = env->itlb[reg].tag;
1433 break;
1434 }
1435 case ASI_DMMU: /* D-MMU regs */
1436 {
1437 int reg = (addr >> 3) & 0xf;
1438 switch (reg) {
1439 case 0:
1440 /* 0x00 D-TSB Tag Target register */
1441 ret = ultrasparc_tag_target(env->dmmu.tag_access);
1442 break;
1443 case 1: /* 0x08 Primary Context */
1444 ret = env->dmmu.mmu_primary_context;
1445 break;
1446 case 2: /* 0x10 Secondary Context */
1447 ret = env->dmmu.mmu_secondary_context;
1448 break;
1449 case 3: /* SFSR */
1450 ret = env->dmmu.sfsr;
1451 break;
1452 case 4: /* 0x20 SFAR */
1453 ret = env->dmmu.sfar;
1454 break;
1455 case 5: /* 0x28 TSB access */
1456 ret = env->dmmu.tsb;
1457 break;
1458 case 6: /* 0x30 D-TSB Tag Access register */
1459 ret = env->dmmu.tag_access;
1460 break;
1461 case 7:
1462 ret = env->dmmu.virtual_watchpoint;
1463 break;
1464 case 8:
1465 ret = env->dmmu.physical_watchpoint;
1466 break;
1467 default:
1468 sparc_raise_mmu_fault(cs, addr, false, false, 1, size, GETPC());
1469 ret = 0;
1470 }
1471 break;
1472 }
1473 case ASI_DMMU_TSB_8KB_PTR: /* D-MMU 8k TSB pointer */
1474 {
1475 /* env->dmmuregs[5] holds D-MMU TSB register value
1476 env->dmmuregs[6] holds D-MMU Tag Access register value */
1477 ret = ultrasparc_tsb_pointer(env, &env->dmmu, 0);
1478 break;
1479 }
1480 case ASI_DMMU_TSB_64KB_PTR: /* D-MMU 64k TSB pointer */
1481 {
1482 /* env->dmmuregs[5] holds D-MMU TSB register value
1483 env->dmmuregs[6] holds D-MMU Tag Access register value */
1484 ret = ultrasparc_tsb_pointer(env, &env->dmmu, 1);
1485 break;
1486 }
1487 case ASI_DTLB_DATA_ACCESS: /* D-MMU data access */
1488 {
1489 int reg = (addr >> 3) & 0x3f;
1490
1491 ret = env->dtlb[reg].tte;
1492 break;
1493 }
1494 case ASI_DTLB_TAG_READ: /* D-MMU tag read */
1495 {
1496 int reg = (addr >> 3) & 0x3f;
1497
1498 ret = env->dtlb[reg].tag;
1499 break;
1500 }
1501 case ASI_INTR_DISPATCH_STAT: /* Interrupt dispatch, RO */
1502 break;
1503 case ASI_INTR_RECEIVE: /* Interrupt data receive */
1504 ret = env->ivec_status;
1505 break;
1506 case ASI_INTR_R: /* Incoming interrupt vector, RO */
1507 {
1508 int reg = (addr >> 4) & 0x3;
1509 if (reg < 3) {
1510 ret = env->ivec_data[reg];
1511 }
1512 break;
1513 }
1514 case ASI_SCRATCHPAD: /* UA2005 privileged scratchpad */
1515 if (unlikely((addr >= 0x20) && (addr < 0x30))) {
1516 /* Hyperprivileged access only */
1517 sparc_raise_mmu_fault(cs, addr, false, false, 1, size, GETPC());
1518 }
1519 /* fall through */
1520 case ASI_HYP_SCRATCHPAD: /* UA2005 hyperprivileged scratchpad */
1521 {
1522 unsigned int i = (addr >> 3) & 0x7;
1523 ret = env->scratch[i];
1524 break;
1525 }
1526 case ASI_MMU: /* UA2005 Context ID registers */
1527 switch ((addr >> 3) & 0x3) {
1528 case 1:
1529 ret = env->dmmu.mmu_primary_context;
1530 break;
1531 case 2:
1532 ret = env->dmmu.mmu_secondary_context;
1533 break;
1534 default:
1535 sparc_raise_mmu_fault(cs, addr, true, false, 1, size, GETPC());
1536 }
1537 break;
1538 case ASI_DCACHE_DATA: /* D-cache data */
1539 case ASI_DCACHE_TAG: /* D-cache tag access */
1540 case ASI_ESTATE_ERROR_EN: /* E-cache error enable */
1541 case ASI_AFSR: /* E-cache asynchronous fault status */
1542 case ASI_AFAR: /* E-cache asynchronous fault address */
1543 case ASI_EC_TAG_DATA: /* E-cache tag data */
1544 case ASI_IC_INSTR: /* I-cache instruction access */
1545 case ASI_IC_TAG: /* I-cache tag access */
1546 case ASI_IC_PRE_DECODE: /* I-cache predecode */
1547 case ASI_IC_NEXT_FIELD: /* I-cache LRU etc. */
1548 case ASI_EC_W: /* E-cache tag */
1549 case ASI_EC_R: /* E-cache tag */
1550 break;
1551 case ASI_DMMU_TSB_DIRECT_PTR: /* D-MMU data pointer */
1552 case ASI_ITLB_DATA_IN: /* I-MMU data in, WO */
1553 case ASI_IMMU_DEMAP: /* I-MMU demap, WO */
1554 case ASI_DTLB_DATA_IN: /* D-MMU data in, WO */
1555 case ASI_DMMU_DEMAP: /* D-MMU demap, WO */
1556 case ASI_INTR_W: /* Interrupt vector, WO */
1557 default:
1558 sparc_raise_mmu_fault(cs, addr, false, false, 1, size, GETPC());
1559 ret = 0;
1560 break;
1561 }
1562
1563 /* Convert to signed number */
1564 if (sign) {
1565 switch (size) {
1566 case 1:
1567 ret = (int8_t) ret;
1568 break;
1569 case 2:
1570 ret = (int16_t) ret;
1571 break;
1572 case 4:
1573 ret = (int32_t) ret;
1574 break;
1575 default:
1576 break;
1577 }
1578 }
1579 #ifdef DEBUG_ASI
1580 dump_asi("read ", last_addr, asi, size, ret);
1581 #endif
1582 return ret;
1583 }
1584
1585 void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val,
1586 int asi, uint32_t memop)
1587 {
1588 int size = 1 << (memop & MO_SIZE);
1589 CPUState *cs = env_cpu(env);
1590
1591 #ifdef DEBUG_ASI
1592 dump_asi("write", addr, asi, size, val);
1593 #endif
1594
1595 asi &= 0xff;
1596
1597 do_check_asi(env, asi, GETPC());
1598 do_check_align(env, addr, size - 1, GETPC());
1599 addr = asi_address_mask(env, asi, addr);
1600
1601 switch (asi) {
1602 case ASI_AIUP: /* As if user primary */
1603 case ASI_AIUS: /* As if user secondary */
1604 case ASI_AIUPL: /* As if user primary LE */
1605 case ASI_AIUSL: /* As if user secondary LE */
1606 case ASI_P: /* Primary */
1607 case ASI_S: /* Secondary */
1608 case ASI_PL: /* Primary LE */
1609 case ASI_SL: /* Secondary LE */
1610 case ASI_REAL: /* Bypass */
1611 case ASI_REAL_IO: /* Bypass, non-cacheable */
1612 case ASI_REAL_L: /* Bypass LE */
1613 case ASI_REAL_IO_L: /* Bypass, non-cacheable LE */
1614 case ASI_N: /* Nucleus */
1615 case ASI_NL: /* Nucleus Little Endian (LE) */
1616 case ASI_NUCLEUS_QUAD_LDD: /* Nucleus quad LDD 128 bit atomic */
1617 case ASI_NUCLEUS_QUAD_LDD_L: /* Nucleus quad LDD 128 bit atomic LE */
1618 case ASI_TWINX_AIUP: /* As if user primary, twinx */
1619 case ASI_TWINX_AIUS: /* As if user secondary, twinx */
1620 case ASI_TWINX_REAL: /* Real address, twinx */
1621 case ASI_TWINX_AIUP_L: /* As if user primary, twinx, LE */
1622 case ASI_TWINX_AIUS_L: /* As if user secondary, twinx, LE */
1623 case ASI_TWINX_REAL_L: /* Real address, twinx, LE */
1624 case ASI_TWINX_N: /* Nucleus, twinx */
1625 case ASI_TWINX_NL: /* Nucleus, twinx, LE */
1626 /* ??? From the UA2011 document; overlaps BLK_INIT_QUAD_LDD_* */
1627 case ASI_TWINX_P: /* Primary, twinx */
1628 case ASI_TWINX_PL: /* Primary, twinx, LE */
1629 case ASI_TWINX_S: /* Secondary, twinx */
1630 case ASI_TWINX_SL: /* Secondary, twinx, LE */
1631 /* These are always handled inline. */
1632 g_assert_not_reached();
1633 /* these ASIs have different functions on UltraSPARC-IIIi
1634 * and UA2005 CPUs. Use the explicit numbers to avoid confusion
1635 */
1636 case 0x31:
1637 case 0x32:
1638 case 0x39:
1639 case 0x3a:
1640 if (cpu_has_hypervisor(env)) {
1641 /* UA2005
1642 * ASI_DMMU_CTX_ZERO_TSB_BASE_PS0
1643 * ASI_DMMU_CTX_ZERO_TSB_BASE_PS1
1644 * ASI_DMMU_CTX_NONZERO_TSB_BASE_PS0
1645 * ASI_DMMU_CTX_NONZERO_TSB_BASE_PS1
1646 */
1647 int idx = ((asi & 2) >> 1) | ((asi & 8) >> 2);
1648 env->dmmu.sun4v_tsb_pointers[idx] = val;
1649 } else {
1650 goto illegal_insn;
1651 }
1652 break;
1653 case 0x33:
1654 case 0x3b:
1655 if (cpu_has_hypervisor(env)) {
1656 /* UA2005
1657 * ASI_DMMU_CTX_ZERO_CONFIG
1658 * ASI_DMMU_CTX_NONZERO_CONFIG
1659 */
1660 env->dmmu.sun4v_ctx_config[(asi & 8) >> 3] = val;
1661 } else {
1662 goto illegal_insn;
1663 }
1664 break;
1665 case 0x35:
1666 case 0x36:
1667 case 0x3d:
1668 case 0x3e:
1669 if (cpu_has_hypervisor(env)) {
1670 /* UA2005
1671 * ASI_IMMU_CTX_ZERO_TSB_BASE_PS0
1672 * ASI_IMMU_CTX_ZERO_TSB_BASE_PS1
1673 * ASI_IMMU_CTX_NONZERO_TSB_BASE_PS0
1674 * ASI_IMMU_CTX_NONZERO_TSB_BASE_PS1
1675 */
1676 int idx = ((asi & 2) >> 1) | ((asi & 8) >> 2);
1677 env->immu.sun4v_tsb_pointers[idx] = val;
1678 } else {
1679 goto illegal_insn;
1680 }
1681 break;
1682 case 0x37:
1683 case 0x3f:
1684 if (cpu_has_hypervisor(env)) {
1685 /* UA2005
1686 * ASI_IMMU_CTX_ZERO_CONFIG
1687 * ASI_IMMU_CTX_NONZERO_CONFIG
1688 */
1689 env->immu.sun4v_ctx_config[(asi & 8) >> 3] = val;
1690 } else {
1691 goto illegal_insn;
1692 }
1693 break;
1694 case ASI_UPA_CONFIG: /* UPA config */
1695 /* XXX */
1696 return;
1697 case ASI_LSU_CONTROL: /* LSU */
1698 env->lsu = val & (DMMU_E | IMMU_E);
1699 return;
1700 case ASI_IMMU: /* I-MMU regs */
1701 {
1702 int reg = (addr >> 3) & 0xf;
1703 uint64_t oldreg;
1704
1705 oldreg = env->immu.mmuregs[reg];
1706 switch (reg) {
1707 case 0: /* RO */
1708 return;
1709 case 1: /* Not in I-MMU */
1710 case 2:
1711 return;
1712 case 3: /* SFSR */
1713 if ((val & 1) == 0) {
1714 val = 0; /* Clear SFSR */
1715 }
1716 env->immu.sfsr = val;
1717 break;
1718 case 4: /* RO */
1719 return;
1720 case 5: /* TSB access */
1721 DPRINTF_MMU("immu TSB write: 0x%016" PRIx64 " -> 0x%016"
1722 PRIx64 "\n", env->immu.tsb, val);
1723 env->immu.tsb = val;
1724 break;
1725 case 6: /* Tag access */
1726 env->immu.tag_access = val;
1727 break;
1728 case 7:
1729 case 8:
1730 return;
1731 default:
1732 sparc_raise_mmu_fault(cs, addr, true, false, 1, size, GETPC());
1733 break;
1734 }
1735
1736 if (oldreg != env->immu.mmuregs[reg]) {
1737 DPRINTF_MMU("immu change reg[%d]: 0x%016" PRIx64 " -> 0x%016"
1738 PRIx64 "\n", reg, oldreg, env->immuregs[reg]);
1739 }
1740 #ifdef DEBUG_MMU
1741 dump_mmu(env);
1742 #endif
1743 return;
1744 }
1745 case ASI_ITLB_DATA_IN: /* I-MMU data in */
1746 /* ignore real translation entries */
1747 if (!(addr & TLB_UST1_IS_REAL_BIT)) {
1748 replace_tlb_1bit_lru(env->itlb, env->immu.tag_access,
1749 val, "immu", env, addr);
1750 }
1751 return;
1752 case ASI_ITLB_DATA_ACCESS: /* I-MMU data access */
1753 {
1754 /* TODO: auto demap */
1755
1756 unsigned int i = (addr >> 3) & 0x3f;
1757
1758 /* ignore real translation entries */
1759 if (!(addr & TLB_UST1_IS_REAL_BIT)) {
1760 replace_tlb_entry(&env->itlb[i], env->immu.tag_access,
1761 sun4v_tte_to_sun4u(env, addr, val), env);
1762 }
1763 #ifdef DEBUG_MMU
1764 DPRINTF_MMU("immu data access replaced entry [%i]\n", i);
1765 dump_mmu(env);
1766 #endif
1767 return;
1768 }
1769 case ASI_IMMU_DEMAP: /* I-MMU demap */
1770 demap_tlb(env->itlb, addr, "immu", env);
1771 return;
1772 case ASI_DMMU: /* D-MMU regs */
1773 {
1774 int reg = (addr >> 3) & 0xf;
1775 uint64_t oldreg;
1776
1777 oldreg = env->dmmu.mmuregs[reg];
1778 switch (reg) {
1779 case 0: /* RO */
1780 case 4:
1781 return;
1782 case 3: /* SFSR */
1783 if ((val & 1) == 0) {
1784 val = 0; /* Clear SFSR, Fault address */
1785 env->dmmu.sfar = 0;
1786 }
1787 env->dmmu.sfsr = val;
1788 break;
1789 case 1: /* Primary context */
1790 env->dmmu.mmu_primary_context = val;
1791 /* can be optimized to only flush MMU_USER_IDX
1792 and MMU_KERNEL_IDX entries */
1793 tlb_flush(cs);
1794 break;
1795 case 2: /* Secondary context */
1796 env->dmmu.mmu_secondary_context = val;
1797 /* can be optimized to only flush MMU_USER_SECONDARY_IDX
1798 and MMU_KERNEL_SECONDARY_IDX entries */
1799 tlb_flush(cs);
1800 break;
1801 case 5: /* TSB access */
1802 DPRINTF_MMU("dmmu TSB write: 0x%016" PRIx64 " -> 0x%016"
1803 PRIx64 "\n", env->dmmu.tsb, val);
1804 env->dmmu.tsb = val;
1805 break;
1806 case 6: /* Tag access */
1807 env->dmmu.tag_access = val;
1808 break;
1809 case 7: /* Virtual Watchpoint */
1810 env->dmmu.virtual_watchpoint = val;
1811 break;
1812 case 8: /* Physical Watchpoint */
1813 env->dmmu.physical_watchpoint = val;
1814 break;
1815 default:
1816 sparc_raise_mmu_fault(cs, addr, true, false, 1, size, GETPC());
1817 break;
1818 }
1819
1820 if (oldreg != env->dmmu.mmuregs[reg]) {
1821 DPRINTF_MMU("dmmu change reg[%d]: 0x%016" PRIx64 " -> 0x%016"
1822 PRIx64 "\n", reg, oldreg, env->dmmuregs[reg]);
1823 }
1824 #ifdef DEBUG_MMU
1825 dump_mmu(env);
1826 #endif
1827 return;
1828 }
1829 case ASI_DTLB_DATA_IN: /* D-MMU data in */
1830 /* ignore real translation entries */
1831 if (!(addr & TLB_UST1_IS_REAL_BIT)) {
1832 replace_tlb_1bit_lru(env->dtlb, env->dmmu.tag_access,
1833 val, "dmmu", env, addr);
1834 }
1835 return;
1836 case ASI_DTLB_DATA_ACCESS: /* D-MMU data access */
1837 {
1838 unsigned int i = (addr >> 3) & 0x3f;
1839
1840 /* ignore real translation entries */
1841 if (!(addr & TLB_UST1_IS_REAL_BIT)) {
1842 replace_tlb_entry(&env->dtlb[i], env->dmmu.tag_access,
1843 sun4v_tte_to_sun4u(env, addr, val), env);
1844 }
1845 #ifdef DEBUG_MMU
1846 DPRINTF_MMU("dmmu data access replaced entry [%i]\n", i);
1847 dump_mmu(env);
1848 #endif
1849 return;
1850 }
1851 case ASI_DMMU_DEMAP: /* D-MMU demap */
1852 demap_tlb(env->dtlb, addr, "dmmu", env);
1853 return;
1854 case ASI_INTR_RECEIVE: /* Interrupt data receive */
1855 env->ivec_status = val & 0x20;
1856 return;
1857 case ASI_SCRATCHPAD: /* UA2005 privileged scratchpad */
1858 if (unlikely((addr >= 0x20) && (addr < 0x30))) {
1859 /* Hyperprivileged access only */
1860 sparc_raise_mmu_fault(cs, addr, true, false, 1, size, GETPC());
1861 }
1862 /* fall through */
1863 case ASI_HYP_SCRATCHPAD: /* UA2005 hyperprivileged scratchpad */
1864 {
1865 unsigned int i = (addr >> 3) & 0x7;
1866 env->scratch[i] = val;
1867 return;
1868 }
1869 case ASI_MMU: /* UA2005 Context ID registers */
1870 {
1871 switch ((addr >> 3) & 0x3) {
1872 case 1:
1873 env->dmmu.mmu_primary_context = val;
1874 env->immu.mmu_primary_context = val;
1875 tlb_flush_by_mmuidx(cs,
1876 (1 << MMU_USER_IDX) | (1 << MMU_KERNEL_IDX));
1877 break;
1878 case 2:
1879 env->dmmu.mmu_secondary_context = val;
1880 env->immu.mmu_secondary_context = val;
1881 tlb_flush_by_mmuidx(cs,
1882 (1 << MMU_USER_SECONDARY_IDX) |
1883 (1 << MMU_KERNEL_SECONDARY_IDX));
1884 break;
1885 default:
1886 sparc_raise_mmu_fault(cs, addr, true, false, 1, size, GETPC());
1887 }
1888 }
1889 return;
1890 case ASI_QUEUE: /* UA2005 CPU mondo queue */
1891 case ASI_DCACHE_DATA: /* D-cache data */
1892 case ASI_DCACHE_TAG: /* D-cache tag access */
1893 case ASI_ESTATE_ERROR_EN: /* E-cache error enable */
1894 case ASI_AFSR: /* E-cache asynchronous fault status */
1895 case ASI_AFAR: /* E-cache asynchronous fault address */
1896 case ASI_EC_TAG_DATA: /* E-cache tag data */
1897 case ASI_IC_INSTR: /* I-cache instruction access */
1898 case ASI_IC_TAG: /* I-cache tag access */
1899 case ASI_IC_PRE_DECODE: /* I-cache predecode */
1900 case ASI_IC_NEXT_FIELD: /* I-cache LRU etc. */
1901 case ASI_EC_W: /* E-cache tag */
1902 case ASI_EC_R: /* E-cache tag */
1903 return;
1904 case ASI_IMMU_TSB_8KB_PTR: /* I-MMU 8k TSB pointer, RO */
1905 case ASI_IMMU_TSB_64KB_PTR: /* I-MMU 64k TSB pointer, RO */
1906 case ASI_ITLB_TAG_READ: /* I-MMU tag read, RO */
1907 case ASI_DMMU_TSB_8KB_PTR: /* D-MMU 8k TSB pointer, RO */
1908 case ASI_DMMU_TSB_64KB_PTR: /* D-MMU 64k TSB pointer, RO */
1909 case ASI_DMMU_TSB_DIRECT_PTR: /* D-MMU data pointer, RO */
1910 case ASI_DTLB_TAG_READ: /* D-MMU tag read, RO */
1911 case ASI_INTR_DISPATCH_STAT: /* Interrupt dispatch, RO */
1912 case ASI_INTR_R: /* Incoming interrupt vector, RO */
1913 case ASI_PNF: /* Primary no-fault, RO */
1914 case ASI_SNF: /* Secondary no-fault, RO */
1915 case ASI_PNFL: /* Primary no-fault LE, RO */
1916 case ASI_SNFL: /* Secondary no-fault LE, RO */
1917 default:
1918 sparc_raise_mmu_fault(cs, addr, true, false, 1, size, GETPC());
1919 return;
1920 illegal_insn:
1921 cpu_raise_exception_ra(env, TT_ILL_INSN, GETPC());
1922 }
1923 }
1924 #endif /* CONFIG_USER_ONLY */
1925 #endif /* TARGET_SPARC64 */
1926
1927 #if !defined(CONFIG_USER_ONLY)
1928
1929 void sparc_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
1930 vaddr addr, unsigned size,
1931 MMUAccessType access_type,
1932 int mmu_idx, MemTxAttrs attrs,
1933 MemTxResult response, uintptr_t retaddr)
1934 {
1935 bool is_write = access_type == MMU_DATA_STORE;
1936 bool is_exec = access_type == MMU_INST_FETCH;
1937 bool is_asi = false;
1938
1939 sparc_raise_mmu_fault(cs, physaddr, is_write, is_exec,
1940 is_asi, size, retaddr);
1941 }
1942 #endif
armbru's QEMU hackery