target/sparc/cpu.c

   1 /*
   2  * Sparc CPU init helpers
   3  *
   4  *  Copyright (c) 2003-2005 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "qapi/error.h"
  22 #include "cpu.h"
  23 #include "qemu/module.h"
  24 #include "qemu/qemu-print.h"
  25 #include "exec/exec-all.h"
  26 #include "hw/qdev-properties.h"
  27 #include "qapi/visitor.h"
  28 #include "tcg/tcg.h"
  29
  30 //#define DEBUG_FEATURES
  31
  32 static void sparc_cpu_reset_hold(Object *obj)
  33 {
  34     CPUState *s = CPU(obj);
  35     SPARCCPU *cpu = SPARC_CPU(s);
  36     SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(cpu);
  37     CPUSPARCState *env = &cpu->env;
  38
  39     if (scc->parent_phases.hold) {
  40         scc->parent_phases.hold(obj);
  41     }
  42
  43     memset(env, 0, offsetof(CPUSPARCState, end_reset_fields));
  44     env->cwp = 0;
  45 #ifndef TARGET_SPARC64
  46     env->wim = 1;
  47 #endif
  48     env->regwptr = env->regbase + (env->cwp * 16);
  49 #if defined(CONFIG_USER_ONLY)
  50 #ifdef TARGET_SPARC64
  51     env->cleanwin = env->nwindows - 2;
  52     env->cansave = env->nwindows - 2;
  53     env->pstate = PS_RMO | PS_PEF | PS_IE;
  54     env->asi = 0x82; /* Primary no-fault */
  55 #endif
  56 #else
  57 #if !defined(TARGET_SPARC64)
  58     env->psret = 0;
  59     env->psrs = 1;
  60     env->psrps = 1;
  61 #endif
  62 #ifdef TARGET_SPARC64
  63     env->pstate = PS_PRIV | PS_RED | PS_PEF;
  64     if (!cpu_has_hypervisor(env)) {
  65         env->pstate |= PS_AG;
  66     }
  67     env->hpstate = cpu_has_hypervisor(env) ? HS_PRIV : 0;
  68     env->tl = env->maxtl;
  69     env->gl = 2;
  70     cpu_tsptr(env)->tt = TT_POWER_ON_RESET;
  71     env->lsu = 0;
  72 #else
  73     env->mmuregs[0] &= ~(MMU_E | MMU_NF);
  74     env->mmuregs[0] |= env->def.mmu_bm;
  75 #endif
  76     env->pc = 0;
  77     env->npc = env->pc + 4;
  78 #endif
  79     env->cache_control = 0;
  80 }
  81
  82 #ifndef CONFIG_USER_ONLY
  83 static bool sparc_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
  84 {
  85     if (interrupt_request & CPU_INTERRUPT_HARD) {
  86         SPARCCPU *cpu = SPARC_CPU(cs);
  87         CPUSPARCState *env = &cpu->env;
  88
  89         if (cpu_interrupts_enabled(env) && env->interrupt_index > 0) {
  90             int pil = env->interrupt_index & 0xf;
  91             int type = env->interrupt_index & 0xf0;
  92
  93             if (type != TT_EXTINT || cpu_pil_allowed(env, pil)) {
  94                 cs->exception_index = env->interrupt_index;
  95                 sparc_cpu_do_interrupt(cs);
  96                 return true;
  97             }
  98         }
  99     }
 100     return false;
 101 }
 102 #endif /* !CONFIG_USER_ONLY */
 103
 104 static void cpu_sparc_disas_set_info(CPUState *cpu, disassemble_info *info)
 105 {
 106     info->print_insn = print_insn_sparc;
 107 #ifdef TARGET_SPARC64
 108     info->mach = bfd_mach_sparc_v9b;
 109 #endif
 110 }
 111
 112 static void
 113 cpu_add_feat_as_prop(const char *typename, const char *name, const char *val)
 114 {
 115     GlobalProperty *prop = g_new0(typeof(*prop), 1);
 116     prop->driver = typename;
 117     prop->property = g_strdup(name);
 118     prop->value = g_strdup(val);
 119     qdev_prop_register_global(prop);
 120 }
 121
 122 /* Parse "+feature,-feature,feature=foo" CPU feature string */
 123 static void sparc_cpu_parse_features(const char *typename, char *features,
 124                                      Error **errp)
 125 {
 126     GList *l, *plus_features = NULL, *minus_features = NULL;
 127     char *featurestr; /* Single 'key=value" string being parsed */
 128     static bool cpu_globals_initialized;
 129
 130     if (cpu_globals_initialized) {
 131         return;
 132     }
 133     cpu_globals_initialized = true;
 134
 135     if (!features) {
 136         return;
 137     }
 138
 139     for (featurestr = strtok(features, ",");
 140          featurestr;
 141          featurestr = strtok(NULL, ",")) {
 142         const char *name;
 143         const char *val = NULL;
 144         char *eq = NULL;
 145
 146         /* Compatibility syntax: */
 147         if (featurestr[0] == '+') {
 148             plus_features = g_list_append(plus_features,
 149                                           g_strdup(featurestr + 1));
 150             continue;
 151         } else if (featurestr[0] == '-') {
 152             minus_features = g_list_append(minus_features,
 153                                            g_strdup(featurestr + 1));
 154             continue;
 155         }
 156
 157         eq = strchr(featurestr, '=');
 158         name = featurestr;
 159         if (eq) {
 160             *eq++ = 0;
 161             val = eq;
 162
 163             /*
 164              * Temporarily, only +feat/-feat will be supported
 165              * for boolean properties until we remove the
 166              * minus-overrides-plus semantics and just follow
 167              * the order options appear on the command-line.
 168              *
 169              * TODO: warn if user is relying on minus-override-plus semantics
 170              * TODO: remove minus-override-plus semantics after
 171              *       warning for a few releases
 172              */
 173             if (!strcasecmp(val, "on") ||
 174                 !strcasecmp(val, "off") ||
 175                 !strcasecmp(val, "true") ||
 176                 !strcasecmp(val, "false")) {
 177                 error_setg(errp, "Boolean properties in format %s=%s"
 178                                  " are not supported", name, val);
 179                 return;
 180             }
 181         } else {
 182             error_setg(errp, "Unsupported property format: %s", name);
 183             return;
 184         }
 185         cpu_add_feat_as_prop(typename, name, val);
 186     }
 187
 188     for (l = plus_features; l; l = l->next) {
 189         const char *name = l->data;
 190         cpu_add_feat_as_prop(typename, name, "on");
 191     }
 192     g_list_free_full(plus_features, g_free);
 193
 194     for (l = minus_features; l; l = l->next) {
 195         const char *name = l->data;
 196         cpu_add_feat_as_prop(typename, name, "off");
 197     }
 198     g_list_free_full(minus_features, g_free);
 199 }
 200
 201 void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu)
 202 {
 203 #if !defined(TARGET_SPARC64)
 204     env->mxccregs[7] = ((cpu + 8) & 0xf) << 24;
 205 #endif
 206 }
 207
 208 static const sparc_def_t sparc_defs[] = {
 209 #ifdef TARGET_SPARC64
 210     {
 211         .name = "Fujitsu Sparc64",
 212         .iu_version = ((0x04ULL << 48) | (0x02ULL << 32) | (0ULL << 24)),
 213         .fpu_version = 0x00000000,
 214         .mmu_version = mmu_us_12,
 215         .nwindows = 4,
 216         .maxtl = 4,
 217         .features = CPU_DEFAULT_FEATURES,
 218     },
 219     {
 220         .name = "Fujitsu Sparc64 III",
 221         .iu_version = ((0x04ULL << 48) | (0x03ULL << 32) | (0ULL << 24)),
 222         .fpu_version = 0x00000000,
 223         .mmu_version = mmu_us_12,
 224         .nwindows = 5,
 225         .maxtl = 4,
 226         .features = CPU_DEFAULT_FEATURES,
 227     },
 228     {
 229         .name = "Fujitsu Sparc64 IV",
 230         .iu_version = ((0x04ULL << 48) | (0x04ULL << 32) | (0ULL << 24)),
 231         .fpu_version = 0x00000000,
 232         .mmu_version = mmu_us_12,
 233         .nwindows = 8,
 234         .maxtl = 5,
 235         .features = CPU_DEFAULT_FEATURES,
 236     },
 237     {
 238         .name = "Fujitsu Sparc64 V",
 239         .iu_version = ((0x04ULL << 48) | (0x05ULL << 32) | (0x51ULL << 24)),
 240         .fpu_version = 0x00000000,
 241         .mmu_version = mmu_us_12,
 242         .nwindows = 8,
 243         .maxtl = 5,
 244         .features = CPU_DEFAULT_FEATURES,
 245     },
 246     {
 247         .name = "TI UltraSparc I",
 248         .iu_version = ((0x17ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)),
 249         .fpu_version = 0x00000000,
 250         .mmu_version = mmu_us_12,
 251         .nwindows = 8,
 252         .maxtl = 5,
 253         .features = CPU_DEFAULT_FEATURES,
 254     },
 255     {
 256         .name = "TI UltraSparc II",
 257         .iu_version = ((0x17ULL << 48) | (0x11ULL << 32) | (0x20ULL << 24)),
 258         .fpu_version = 0x00000000,
 259         .mmu_version = mmu_us_12,
 260         .nwindows = 8,
 261         .maxtl = 5,
 262         .features = CPU_DEFAULT_FEATURES,
 263     },
 264     {
 265         .name = "TI UltraSparc IIi",
 266         .iu_version = ((0x17ULL << 48) | (0x12ULL << 32) | (0x91ULL << 24)),
 267         .fpu_version = 0x00000000,
 268         .mmu_version = mmu_us_12,
 269         .nwindows = 8,
 270         .maxtl = 5,
 271         .features = CPU_DEFAULT_FEATURES,
 272     },
 273     {
 274         .name = "TI UltraSparc IIe",
 275         .iu_version = ((0x17ULL << 48) | (0x13ULL << 32) | (0x14ULL << 24)),
 276         .fpu_version = 0x00000000,
 277         .mmu_version = mmu_us_12,
 278         .nwindows = 8,
 279         .maxtl = 5,
 280         .features = CPU_DEFAULT_FEATURES,
 281     },
 282     {
 283         .name = "Sun UltraSparc III",
 284         .iu_version = ((0x3eULL << 48) | (0x14ULL << 32) | (0x34ULL << 24)),
 285         .fpu_version = 0x00000000,
 286         .mmu_version = mmu_us_12,
 287         .nwindows = 8,
 288         .maxtl = 5,
 289         .features = CPU_DEFAULT_FEATURES,
 290     },
 291     {
 292         .name = "Sun UltraSparc III Cu",
 293         .iu_version = ((0x3eULL << 48) | (0x15ULL << 32) | (0x41ULL << 24)),
 294         .fpu_version = 0x00000000,
 295         .mmu_version = mmu_us_3,
 296         .nwindows = 8,
 297         .maxtl = 5,
 298         .features = CPU_DEFAULT_FEATURES,
 299     },
 300     {
 301         .name = "Sun UltraSparc IIIi",
 302         .iu_version = ((0x3eULL << 48) | (0x16ULL << 32) | (0x34ULL << 24)),
 303         .fpu_version = 0x00000000,
 304         .mmu_version = mmu_us_12,
 305         .nwindows = 8,
 306         .maxtl = 5,
 307         .features = CPU_DEFAULT_FEATURES,
 308     },
 309     {
 310         .name = "Sun UltraSparc IV",
 311         .iu_version = ((0x3eULL << 48) | (0x18ULL << 32) | (0x31ULL << 24)),
 312         .fpu_version = 0x00000000,
 313         .mmu_version = mmu_us_4,
 314         .nwindows = 8,
 315         .maxtl = 5,
 316         .features = CPU_DEFAULT_FEATURES,
 317     },
 318     {
 319         .name = "Sun UltraSparc IV+",
 320         .iu_version = ((0x3eULL << 48) | (0x19ULL << 32) | (0x22ULL << 24)),
 321         .fpu_version = 0x00000000,
 322         .mmu_version = mmu_us_12,
 323         .nwindows = 8,
 324         .maxtl = 5,
 325         .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_CMT,
 326     },
 327     {
 328         .name = "Sun UltraSparc IIIi+",
 329         .iu_version = ((0x3eULL << 48) | (0x22ULL << 32) | (0ULL << 24)),
 330         .fpu_version = 0x00000000,
 331         .mmu_version = mmu_us_3,
 332         .nwindows = 8,
 333         .maxtl = 5,
 334         .features = CPU_DEFAULT_FEATURES,
 335     },
 336     {
 337         .name = "Sun UltraSparc T1",
 338         /* defined in sparc_ifu_fdp.v and ctu.h */
 339         .iu_version = ((0x3eULL << 48) | (0x23ULL << 32) | (0x02ULL << 24)),
 340         .fpu_version = 0x00000000,
 341         .mmu_version = mmu_sun4v,
 342         .nwindows = 8,
 343         .maxtl = 6,
 344         .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_HYPV | CPU_FEATURE_CMT
 345         | CPU_FEATURE_GL,
 346     },
 347     {
 348         .name = "Sun UltraSparc T2",
 349         /* defined in tlu_asi_ctl.v and n2_revid_cust.v */
 350         .iu_version = ((0x3eULL << 48) | (0x24ULL << 32) | (0x02ULL << 24)),
 351         .fpu_version = 0x00000000,
 352         .mmu_version = mmu_sun4v,
 353         .nwindows = 8,
 354         .maxtl = 6,
 355         .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_HYPV | CPU_FEATURE_CMT
 356         | CPU_FEATURE_GL,
 357     },
 358     {
 359         .name = "NEC UltraSparc I",
 360         .iu_version = ((0x22ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)),
 361         .fpu_version = 0x00000000,
 362         .mmu_version = mmu_us_12,
 363         .nwindows = 8,
 364         .maxtl = 5,
 365         .features = CPU_DEFAULT_FEATURES,
 366     },
 367 #else
 368     {
 369         .name = "Fujitsu MB86904",
 370         .iu_version = 0x04 << 24, /* Impl 0, ver 4 */
 371         .fpu_version = 4 << FSR_VER_SHIFT, /* FPU version 4 (Meiko) */
 372         .mmu_version = 0x04 << 24, /* Impl 0, ver 4 */
 373         .mmu_bm = 0x00004000,
 374         .mmu_ctpr_mask = 0x00ffffc0,
 375         .mmu_cxr_mask = 0x000000ff,
 376         .mmu_sfsr_mask = 0x00016fff,
 377         .mmu_trcr_mask = 0x00ffffff,
 378         .nwindows = 8,
 379         .features = CPU_DEFAULT_FEATURES,
 380     },
 381     {
 382         .name = "Fujitsu MB86907",
 383         .iu_version = 0x05 << 24, /* Impl 0, ver 5 */
 384         .fpu_version = 4 << FSR_VER_SHIFT, /* FPU version 4 (Meiko) */
 385         .mmu_version = 0x05 << 24, /* Impl 0, ver 5 */
 386         .mmu_bm = 0x00004000,
 387         .mmu_ctpr_mask = 0xffffffc0,
 388         .mmu_cxr_mask = 0x000000ff,
 389         .mmu_sfsr_mask = 0x00016fff,
 390         .mmu_trcr_mask = 0xffffffff,
 391         .nwindows = 8,
 392         .features = CPU_DEFAULT_FEATURES,
 393     },
 394     {
 395         .name = "TI MicroSparc I",
 396         .iu_version = 0x41000000,
 397         .fpu_version = 4 << FSR_VER_SHIFT,
 398         .mmu_version = 0x41000000,
 399         .mmu_bm = 0x00004000,
 400         .mmu_ctpr_mask = 0x007ffff0,
 401         .mmu_cxr_mask = 0x0000003f,
 402         .mmu_sfsr_mask = 0x00016fff,
 403         .mmu_trcr_mask = 0x0000003f,
 404         .nwindows = 7,
 405         .features = CPU_FEATURE_MUL | CPU_FEATURE_DIV,
 406     },
 407     {
 408         .name = "TI MicroSparc II",
 409         .iu_version = 0x42000000,
 410         .fpu_version = 4 << FSR_VER_SHIFT,
 411         .mmu_version = 0x02000000,
 412         .mmu_bm = 0x00004000,
 413         .mmu_ctpr_mask = 0x00ffffc0,
 414         .mmu_cxr_mask = 0x000000ff,
 415         .mmu_sfsr_mask = 0x00016fff,
 416         .mmu_trcr_mask = 0x00ffffff,
 417         .nwindows = 8,
 418         .features = CPU_DEFAULT_FEATURES,
 419     },
 420     {
 421         .name = "TI MicroSparc IIep",
 422         .iu_version = 0x42000000,
 423         .fpu_version = 4 << FSR_VER_SHIFT,
 424         .mmu_version = 0x04000000,
 425         .mmu_bm = 0x00004000,
 426         .mmu_ctpr_mask = 0x00ffffc0,
 427         .mmu_cxr_mask = 0x000000ff,
 428         .mmu_sfsr_mask = 0x00016bff,
 429         .mmu_trcr_mask = 0x00ffffff,
 430         .nwindows = 8,
 431         .features = CPU_DEFAULT_FEATURES,
 432     },
 433     {
 434         .name = "TI SuperSparc 40", /* STP1020NPGA */
 435         .iu_version = 0x41000000, /* SuperSPARC 2.x */
 436         .fpu_version = 0 << FSR_VER_SHIFT,
 437         .mmu_version = 0x00000800, /* SuperSPARC 2.x, no MXCC */
 438         .mmu_bm = 0x00002000,
 439         .mmu_ctpr_mask = 0xffffffc0,
 440         .mmu_cxr_mask = 0x0000ffff,
 441         .mmu_sfsr_mask = 0xffffffff,
 442         .mmu_trcr_mask = 0xffffffff,
 443         .nwindows = 8,
 444         .features = CPU_DEFAULT_FEATURES,
 445     },
 446     {
 447         .name = "TI SuperSparc 50", /* STP1020PGA */
 448         .iu_version = 0x40000000, /* SuperSPARC 3.x */
 449         .fpu_version = 0 << FSR_VER_SHIFT,
 450         .mmu_version = 0x01000800, /* SuperSPARC 3.x, no MXCC */
 451         .mmu_bm = 0x00002000,
 452         .mmu_ctpr_mask = 0xffffffc0,
 453         .mmu_cxr_mask = 0x0000ffff,
 454         .mmu_sfsr_mask = 0xffffffff,
 455         .mmu_trcr_mask = 0xffffffff,
 456         .nwindows = 8,
 457         .features = CPU_DEFAULT_FEATURES,
 458     },
 459     {
 460         .name = "TI SuperSparc 51",
 461         .iu_version = 0x40000000, /* SuperSPARC 3.x */
 462         .fpu_version = 0 << FSR_VER_SHIFT,
 463         .mmu_version = 0x01000000, /* SuperSPARC 3.x, MXCC */
 464         .mmu_bm = 0x00002000,
 465         .mmu_ctpr_mask = 0xffffffc0,
 466         .mmu_cxr_mask = 0x0000ffff,
 467         .mmu_sfsr_mask = 0xffffffff,
 468         .mmu_trcr_mask = 0xffffffff,
 469         .mxcc_version = 0x00000104,
 470         .nwindows = 8,
 471         .features = CPU_DEFAULT_FEATURES,
 472     },
 473     {
 474         .name = "TI SuperSparc 60", /* STP1020APGA */
 475         .iu_version = 0x40000000, /* SuperSPARC 3.x */
 476         .fpu_version = 0 << FSR_VER_SHIFT,
 477         .mmu_version = 0x01000800, /* SuperSPARC 3.x, no MXCC */
 478         .mmu_bm = 0x00002000,
 479         .mmu_ctpr_mask = 0xffffffc0,
 480         .mmu_cxr_mask = 0x0000ffff,
 481         .mmu_sfsr_mask = 0xffffffff,
 482         .mmu_trcr_mask = 0xffffffff,
 483         .nwindows = 8,
 484         .features = CPU_DEFAULT_FEATURES,
 485     },
 486     {
 487         .name = "TI SuperSparc 61",
 488         .iu_version = 0x44000000, /* SuperSPARC 3.x */
 489         .fpu_version = 0 << FSR_VER_SHIFT,
 490         .mmu_version = 0x01000000, /* SuperSPARC 3.x, MXCC */
 491         .mmu_bm = 0x00002000,
 492         .mmu_ctpr_mask = 0xffffffc0,
 493         .mmu_cxr_mask = 0x0000ffff,
 494         .mmu_sfsr_mask = 0xffffffff,
 495         .mmu_trcr_mask = 0xffffffff,
 496         .mxcc_version = 0x00000104,
 497         .nwindows = 8,
 498         .features = CPU_DEFAULT_FEATURES,
 499     },
 500     {
 501         .name = "TI SuperSparc II",
 502         .iu_version = 0x40000000, /* SuperSPARC II 1.x */
 503         .fpu_version = 0 << FSR_VER_SHIFT,
 504         .mmu_version = 0x08000000, /* SuperSPARC II 1.x, MXCC */
 505         .mmu_bm = 0x00002000,
 506         .mmu_ctpr_mask = 0xffffffc0,
 507         .mmu_cxr_mask = 0x0000ffff,
 508         .mmu_sfsr_mask = 0xffffffff,
 509         .mmu_trcr_mask = 0xffffffff,
 510         .mxcc_version = 0x00000104,
 511         .nwindows = 8,
 512         .features = CPU_DEFAULT_FEATURES,
 513     },
 514     {
 515         .name = "LEON2",
 516         .iu_version = 0xf2000000,
 517         .fpu_version = 4 << FSR_VER_SHIFT, /* FPU version 4 (Meiko) */
 518         .mmu_version = 0xf2000000,
 519         .mmu_bm = 0x00004000,
 520         .mmu_ctpr_mask = 0x007ffff0,
 521         .mmu_cxr_mask = 0x0000003f,
 522         .mmu_sfsr_mask = 0xffffffff,
 523         .mmu_trcr_mask = 0xffffffff,
 524         .nwindows = 8,
 525         .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_TA0_SHUTDOWN,
 526     },
 527     {
 528         .name = "LEON3",
 529         .iu_version = 0xf3000000,
 530         .fpu_version = 4 << FSR_VER_SHIFT, /* FPU version 4 (Meiko) */
 531         .mmu_version = 0xf3000000,
 532         .mmu_bm = 0x00000000,
 533         .mmu_ctpr_mask = 0xfffffffc,
 534         .mmu_cxr_mask = 0x000000ff,
 535         .mmu_sfsr_mask = 0xffffffff,
 536         .mmu_trcr_mask = 0xffffffff,
 537         .nwindows = 8,
 538         .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_TA0_SHUTDOWN |
 539         CPU_FEATURE_ASR17 | CPU_FEATURE_CACHE_CTRL | CPU_FEATURE_POWERDOWN |
 540         CPU_FEATURE_CASA,
 541     },
 542 #endif
 543 };
 544
 545 /* This must match sparc_cpu_properties[]. */
 546 static const char * const feature_name[] = {
 547     [CPU_FEATURE_BIT_FLOAT128] = "float128",
 548 #ifdef TARGET_SPARC64
 549     [CPU_FEATURE_BIT_CMT] = "cmt",
 550     [CPU_FEATURE_BIT_GL] = "gl",
 551     [CPU_FEATURE_BIT_HYPV] = "hypv",
 552     [CPU_FEATURE_BIT_VIS1] = "vis1",
 553     [CPU_FEATURE_BIT_VIS2] = "vis2",
 554 #else
 555     [CPU_FEATURE_BIT_MUL] = "mul",
 556     [CPU_FEATURE_BIT_DIV] = "div",
 557     [CPU_FEATURE_BIT_FSMULD] = "fsmuld",
 558 #endif
 559 };
 560
 561 static void print_features(uint32_t features, const char *prefix)
 562 {
 563     unsigned int i;
 564
 565     for (i = 0; i < ARRAY_SIZE(feature_name); i++) {
 566         if (feature_name[i] && (features & (1 << i))) {
 567             if (prefix) {
 568                 qemu_printf("%s", prefix);
 569             }
 570             qemu_printf("%s ", feature_name[i]);
 571         }
 572     }
 573 }
 574
 575 void sparc_cpu_list(void)
 576 {
 577     unsigned int i;
 578
 579     for (i = 0; i < ARRAY_SIZE(sparc_defs); i++) {
 580         qemu_printf("Sparc %16s IU " TARGET_FMT_lx
 581                     " FPU %08x MMU %08x NWINS %d ",
 582                     sparc_defs[i].name,
 583                     sparc_defs[i].iu_version,
 584                     sparc_defs[i].fpu_version,
 585                     sparc_defs[i].mmu_version,
 586                     sparc_defs[i].nwindows);
 587         print_features(CPU_DEFAULT_FEATURES & ~sparc_defs[i].features, "-");
 588         print_features(~CPU_DEFAULT_FEATURES & sparc_defs[i].features, "+");
 589         qemu_printf("\n");
 590     }
 591     qemu_printf("Default CPU feature flags (use '-' to remove): ");
 592     print_features(CPU_DEFAULT_FEATURES, NULL);
 593     qemu_printf("\n");
 594     qemu_printf("Available CPU feature flags (use '+' to add): ");
 595     print_features(~CPU_DEFAULT_FEATURES, NULL);
 596     qemu_printf("\n");
 597     qemu_printf("Numerical features (use '=' to set): iu_version "
 598                 "fpu_version mmu_version nwindows\n");
 599 }
 600
 601 static void cpu_print_cc(FILE *f, uint32_t cc)
 602 {
 603     qemu_fprintf(f, "%c%c%c%c", cc & PSR_NEG ? 'N' : '-',
 604                  cc & PSR_ZERO ? 'Z' : '-', cc & PSR_OVF ? 'V' : '-',
 605                  cc & PSR_CARRY ? 'C' : '-');
 606 }
 607
 608 #ifdef TARGET_SPARC64
 609 #define REGS_PER_LINE 4
 610 #else
 611 #define REGS_PER_LINE 8
 612 #endif
 613
 614 static void sparc_cpu_dump_state(CPUState *cs, FILE *f, int flags)
 615 {
 616     SPARCCPU *cpu = SPARC_CPU(cs);
 617     CPUSPARCState *env = &cpu->env;
 618     int i, x;
 619
 620     qemu_fprintf(f, "pc: " TARGET_FMT_lx "  npc: " TARGET_FMT_lx "\n", env->pc,
 621                  env->npc);
 622
 623     for (i = 0; i < 8; i++) {
 624         if (i % REGS_PER_LINE == 0) {
 625             qemu_fprintf(f, "%%g%d-%d:", i, i + REGS_PER_LINE - 1);
 626         }
 627         qemu_fprintf(f, " " TARGET_FMT_lx, env->gregs[i]);
 628         if (i % REGS_PER_LINE == REGS_PER_LINE - 1) {
 629             qemu_fprintf(f, "\n");
 630         }
 631     }
 632     for (x = 0; x < 3; x++) {
 633         for (i = 0; i < 8; i++) {
 634             if (i % REGS_PER_LINE == 0) {
 635                 qemu_fprintf(f, "%%%c%d-%d: ",
 636                              x == 0 ? 'o' : (x == 1 ? 'l' : 'i'),
 637                              i, i + REGS_PER_LINE - 1);
 638             }
 639             qemu_fprintf(f, TARGET_FMT_lx " ", env->regwptr[i + x * 8]);
 640             if (i % REGS_PER_LINE == REGS_PER_LINE - 1) {
 641                 qemu_fprintf(f, "\n");
 642             }
 643         }
 644     }
 645
 646     if (flags & CPU_DUMP_FPU) {
 647         for (i = 0; i < TARGET_DPREGS; i++) {
 648             if ((i & 3) == 0) {
 649                 qemu_fprintf(f, "%%f%02d: ", i * 2);
 650             }
 651             qemu_fprintf(f, " %016" PRIx64, env->fpr[i].ll);
 652             if ((i & 3) == 3) {
 653                 qemu_fprintf(f, "\n");
 654             }
 655         }
 656     }
 657
 658 #ifdef TARGET_SPARC64
 659     qemu_fprintf(f, "pstate: %08x ccr: %02x (icc: ", env->pstate,
 660                  (unsigned)cpu_get_ccr(env));
 661     cpu_print_cc(f, cpu_get_ccr(env) << PSR_CARRY_SHIFT);
 662     qemu_fprintf(f, " xcc: ");
 663     cpu_print_cc(f, cpu_get_ccr(env) << (PSR_CARRY_SHIFT - 4));
 664     qemu_fprintf(f, ") asi: %02x tl: %d pil: %x gl: %d\n", env->asi, env->tl,
 665                  env->psrpil, env->gl);
 666     qemu_fprintf(f, "tbr: " TARGET_FMT_lx " hpstate: " TARGET_FMT_lx " htba: "
 667                  TARGET_FMT_lx "\n", env->tbr, env->hpstate, env->htba);
 668     qemu_fprintf(f, "cansave: %d canrestore: %d otherwin: %d wstate: %d "
 669                  "cleanwin: %d cwp: %d\n",
 670                  env->cansave, env->canrestore, env->otherwin, env->wstate,
 671                  env->cleanwin, env->nwindows - 1 - env->cwp);
 672     qemu_fprintf(f, "fsr: " TARGET_FMT_lx " y: " TARGET_FMT_lx " fprs: %016x\n",
 673                  cpu_get_fsr(env), env->y, env->fprs);
 674
 675 #else
 676     qemu_fprintf(f, "psr: %08x (icc: ", cpu_get_psr(env));
 677     cpu_print_cc(f, cpu_get_psr(env));
 678     qemu_fprintf(f, " SPE: %c%c%c) wim: %08x\n", env->psrs ? 'S' : '-',
 679                  env->psrps ? 'P' : '-', env->psret ? 'E' : '-',
 680                  env->wim);
 681     qemu_fprintf(f, "fsr: " TARGET_FMT_lx " y: " TARGET_FMT_lx "\n",
 682                  cpu_get_fsr(env), env->y);
 683 #endif
 684     qemu_fprintf(f, "\n");
 685 }
 686
 687 static void sparc_cpu_set_pc(CPUState *cs, vaddr value)
 688 {
 689     SPARCCPU *cpu = SPARC_CPU(cs);
 690
 691     cpu->env.pc = value;
 692     cpu->env.npc = value + 4;
 693 }
 694
 695 static vaddr sparc_cpu_get_pc(CPUState *cs)
 696 {
 697     SPARCCPU *cpu = SPARC_CPU(cs);
 698
 699     return cpu->env.pc;
 700 }
 701
 702 static void sparc_cpu_synchronize_from_tb(CPUState *cs,
 703                                           const TranslationBlock *tb)
 704 {
 705     SPARCCPU *cpu = SPARC_CPU(cs);
 706
 707     tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));
 708     cpu->env.pc = tb->pc;
 709     cpu->env.npc = tb->cs_base;
 710 }
 711
 712 static bool sparc_cpu_has_work(CPUState *cs)
 713 {
 714     SPARCCPU *cpu = SPARC_CPU(cs);
 715     CPUSPARCState *env = &cpu->env;
 716
 717     return (cs->interrupt_request & CPU_INTERRUPT_HARD) &&
 718            cpu_interrupts_enabled(env);
 719 }
 720
 721 static int sparc_cpu_mmu_index(CPUState *cs, bool ifetch)
 722 {
 723     CPUSPARCState *env = cpu_env(cs);
 724
 725 #ifndef TARGET_SPARC64
 726     if ((env->mmuregs[0] & MMU_E) == 0) { /* MMU disabled */
 727         return MMU_PHYS_IDX;
 728     } else {
 729         return env->psrs;
 730     }
 731 #else
 732     /* IMMU or DMMU disabled.  */
 733     if (ifetch
 734         ? (env->lsu & IMMU_E) == 0 || (env->pstate & PS_RED) != 0
 735         : (env->lsu & DMMU_E) == 0) {
 736         return MMU_PHYS_IDX;
 737     } else if (cpu_hypervisor_mode(env)) {
 738         return MMU_PHYS_IDX;
 739     } else if (env->tl > 0) {
 740         return MMU_NUCLEUS_IDX;
 741     } else if (cpu_supervisor_mode(env)) {
 742         return MMU_KERNEL_IDX;
 743     } else {
 744         return MMU_USER_IDX;
 745     }
 746 #endif
 747 }
 748
 749 static char *sparc_cpu_type_name(const char *cpu_model)
 750 {
 751     char *name = g_strdup_printf(SPARC_CPU_TYPE_NAME("%s"), cpu_model);
 752     char *s = name;
 753
 754     /* SPARC cpu model names happen to have whitespaces,
 755      * as type names shouldn't have spaces replace them with '-'
 756      */
 757     while ((s = strchr(s, ' '))) {
 758         *s = '-';
 759     }
 760
 761     return name;
 762 }
 763
 764 static ObjectClass *sparc_cpu_class_by_name(const char *cpu_model)
 765 {
 766     ObjectClass *oc;
 767     char *typename;
 768
 769     typename = sparc_cpu_type_name(cpu_model);
 770     oc = object_class_by_name(typename);
 771     g_free(typename);
 772     return oc;
 773 }
 774
 775 static void sparc_cpu_realizefn(DeviceState *dev, Error **errp)
 776 {
 777     CPUState *cs = CPU(dev);
 778     SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(dev);
 779     Error *local_err = NULL;
 780     SPARCCPU *cpu = SPARC_CPU(dev);
 781     CPUSPARCState *env = &cpu->env;
 782
 783 #if defined(CONFIG_USER_ONLY)
 784     /* We are emulating the kernel, which will trap and emulate float128. */
 785     env->def.features |= CPU_FEATURE_FLOAT128;
 786 #endif
 787
 788     env->version = env->def.iu_version;
 789     env->nwindows = env->def.nwindows;
 790 #if !defined(TARGET_SPARC64)
 791     env->mmuregs[0] |= env->def.mmu_version;
 792     cpu_sparc_set_id(env, 0);
 793     env->mxccregs[7] |= env->def.mxcc_version;
 794 #else
 795     env->mmu_version = env->def.mmu_version;
 796     env->maxtl = env->def.maxtl;
 797     env->version |= env->def.maxtl << 8;
 798     env->version |= env->def.nwindows - 1;
 799 #endif
 800     cpu_put_fsr(env, 0);
 801
 802     cpu_exec_realizefn(cs, &local_err);
 803     if (local_err != NULL) {
 804         error_propagate(errp, local_err);
 805         return;
 806     }
 807
 808     qemu_init_vcpu(cs);
 809
 810     scc->parent_realize(dev, errp);
 811 }
 812
 813 static void sparc_cpu_initfn(Object *obj)
 814 {
 815     SPARCCPU *cpu = SPARC_CPU(obj);
 816     SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(obj);
 817     CPUSPARCState *env = &cpu->env;
 818
 819     if (scc->cpu_def) {
 820         env->def = *scc->cpu_def;
 821     }
 822 }
 823
 824 static void sparc_get_nwindows(Object *obj, Visitor *v, const char *name,
 825                                void *opaque, Error **errp)
 826 {
 827     SPARCCPU *cpu = SPARC_CPU(obj);
 828     int64_t value = cpu->env.def.nwindows;
 829
 830     visit_type_int(v, name, &value, errp);
 831 }
 832
 833 static void sparc_set_nwindows(Object *obj, Visitor *v, const char *name,
 834                                void *opaque, Error **errp)
 835 {
 836     const int64_t min = MIN_NWINDOWS;
 837     const int64_t max = MAX_NWINDOWS;
 838     SPARCCPU *cpu = SPARC_CPU(obj);
 839     int64_t value;
 840
 841     if (!visit_type_int(v, name, &value, errp)) {
 842         return;
 843     }
 844
 845     if (value < min || value > max) {
 846         error_setg(errp, "Property %s.%s doesn't take value %" PRId64
 847                    " (minimum: %" PRId64 ", maximum: %" PRId64 ")",
 848                    object_get_typename(obj), name ? name : "null",
 849                    value, min, max);
 850         return;
 851     }
 852     cpu->env.def.nwindows = value;
 853 }
 854
 855 static PropertyInfo qdev_prop_nwindows = {
 856     .name  = "int",
 857     .get   = sparc_get_nwindows,
 858     .set   = sparc_set_nwindows,
 859 };
 860
 861 /* This must match feature_name[]. */
 862 static Property sparc_cpu_properties[] = {
 863     DEFINE_PROP_BIT("float128", SPARCCPU, env.def.features,
 864                     CPU_FEATURE_BIT_FLOAT128, false),
 865 #ifdef TARGET_SPARC64
 866     DEFINE_PROP_BIT("cmt",      SPARCCPU, env.def.features,
 867                     CPU_FEATURE_BIT_CMT, false),
 868     DEFINE_PROP_BIT("gl",       SPARCCPU, env.def.features,
 869                     CPU_FEATURE_BIT_GL, false),
 870     DEFINE_PROP_BIT("hypv",     SPARCCPU, env.def.features,
 871                     CPU_FEATURE_BIT_HYPV, false),
 872     DEFINE_PROP_BIT("vis1",     SPARCCPU, env.def.features,
 873                     CPU_FEATURE_BIT_VIS1, false),
 874     DEFINE_PROP_BIT("vis2",     SPARCCPU, env.def.features,
 875                     CPU_FEATURE_BIT_VIS2, false),
 876 #else
 877     DEFINE_PROP_BIT("mul",      SPARCCPU, env.def.features,
 878                     CPU_FEATURE_BIT_MUL, false),
 879     DEFINE_PROP_BIT("div",      SPARCCPU, env.def.features,
 880                     CPU_FEATURE_BIT_DIV, false),
 881     DEFINE_PROP_BIT("fsmuld",   SPARCCPU, env.def.features,
 882                     CPU_FEATURE_BIT_FSMULD, false),
 883 #endif
 884     DEFINE_PROP_UNSIGNED("iu-version", SPARCCPU, env.def.iu_version, 0,
 885                          qdev_prop_uint64, target_ulong),
 886     DEFINE_PROP_UINT32("fpu-version", SPARCCPU, env.def.fpu_version, 0),
 887     DEFINE_PROP_UINT32("mmu-version", SPARCCPU, env.def.mmu_version, 0),
 888     DEFINE_PROP("nwindows", SPARCCPU, env.def.nwindows,
 889                 qdev_prop_nwindows, uint32_t),
 890     DEFINE_PROP_END_OF_LIST()
 891 };
 892
 893 #ifndef CONFIG_USER_ONLY
 894 #include "hw/core/sysemu-cpu-ops.h"
 895
 896 static const struct SysemuCPUOps sparc_sysemu_ops = {
 897     .get_phys_page_debug = sparc_cpu_get_phys_page_debug,
 898     .legacy_vmsd = &vmstate_sparc_cpu,
 899 };
 900 #endif
 901
 902 #ifdef CONFIG_TCG
 903 #include "hw/core/tcg-cpu-ops.h"
 904
 905 static const TCGCPUOps sparc_tcg_ops = {
 906     .initialize = sparc_tcg_init,
 907     .synchronize_from_tb = sparc_cpu_synchronize_from_tb,
 908     .restore_state_to_opc = sparc_restore_state_to_opc,
 909
 910 #ifndef CONFIG_USER_ONLY
 911     .tlb_fill = sparc_cpu_tlb_fill,
 912     .cpu_exec_interrupt = sparc_cpu_exec_interrupt,
 913     .do_interrupt = sparc_cpu_do_interrupt,
 914     .do_transaction_failed = sparc_cpu_do_transaction_failed,
 915     .do_unaligned_access = sparc_cpu_do_unaligned_access,
 916 #endif /* !CONFIG_USER_ONLY */
 917 };
 918 #endif /* CONFIG_TCG */
 919
 920 static void sparc_cpu_class_init(ObjectClass *oc, void *data)
 921 {
 922     SPARCCPUClass *scc = SPARC_CPU_CLASS(oc);
 923     CPUClass *cc = CPU_CLASS(oc);
 924     DeviceClass *dc = DEVICE_CLASS(oc);
 925     ResettableClass *rc = RESETTABLE_CLASS(oc);
 926
 927     device_class_set_parent_realize(dc, sparc_cpu_realizefn,
 928                                     &scc->parent_realize);
 929     device_class_set_props(dc, sparc_cpu_properties);
 930
 931     resettable_class_set_parent_phases(rc, NULL, sparc_cpu_reset_hold, NULL,
 932                                        &scc->parent_phases);
 933
 934     cc->class_by_name = sparc_cpu_class_by_name;
 935     cc->parse_features = sparc_cpu_parse_features;
 936     cc->has_work = sparc_cpu_has_work;
 937     cc->mmu_index = sparc_cpu_mmu_index;
 938     cc->dump_state = sparc_cpu_dump_state;
 939 #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
 940     cc->memory_rw_debug = sparc_cpu_memory_rw_debug;
 941 #endif
 942     cc->set_pc = sparc_cpu_set_pc;
 943     cc->get_pc = sparc_cpu_get_pc;
 944     cc->gdb_read_register = sparc_cpu_gdb_read_register;
 945     cc->gdb_write_register = sparc_cpu_gdb_write_register;
 946 #ifndef CONFIG_USER_ONLY
 947     cc->sysemu_ops = &sparc_sysemu_ops;
 948 #endif
 949     cc->disas_set_info = cpu_sparc_disas_set_info;
 950
 951 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
 952     cc->gdb_num_core_regs = 86;
 953 #else
 954     cc->gdb_num_core_regs = 72;
 955 #endif
 956     cc->tcg_ops = &sparc_tcg_ops;
 957 }
 958
 959 static const TypeInfo sparc_cpu_type_info = {
 960     .name = TYPE_SPARC_CPU,
 961     .parent = TYPE_CPU,
 962     .instance_size = sizeof(SPARCCPU),
 963     .instance_align = __alignof(SPARCCPU),
 964     .instance_init = sparc_cpu_initfn,
 965     .abstract = true,
 966     .class_size = sizeof(SPARCCPUClass),
 967     .class_init = sparc_cpu_class_init,
 968 };
 969
 970 static void sparc_cpu_cpudef_class_init(ObjectClass *oc, void *data)
 971 {
 972     SPARCCPUClass *scc = SPARC_CPU_CLASS(oc);
 973     scc->cpu_def = data;
 974 }
 975
 976 static void sparc_register_cpudef_type(const struct sparc_def_t *def)
 977 {
 978     char *typename = sparc_cpu_type_name(def->name);
 979     TypeInfo ti = {
 980         .name = typename,
 981         .parent = TYPE_SPARC_CPU,
 982         .class_init = sparc_cpu_cpudef_class_init,
 983         .class_data = (void *)def,
 984     };
 985
 986     type_register(&ti);
 987     g_free(typename);
 988 }
 989
 990 static void sparc_cpu_register_types(void)
 991 {
 992     int i;
 993
 994     type_register_static(&sparc_cpu_type_info);
 995     for (i = 0; i < ARRAY_SIZE(sparc_defs); i++) {
 996         sparc_register_cpudef_type(&sparc_defs[i]);
 997     }
 998 }
 999
1000 type_init(sparc_cpu_register_types)