target/avr/cpu.c

   1 /*
   2  * QEMU AVR CPU
   3  *
   4  * Copyright (c) 2019-2020 Michael Rolnik
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see
  18  * <http://www.gnu.org/licenses/lgpl-2.1.html>
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "qapi/error.h"
  23 #include "qemu/qemu-print.h"
  24 #include "exec/exec-all.h"
  25 #include "cpu.h"
  26 #include "disas/dis-asm.h"
  27 #include "tcg/debug-assert.h"
  28 #include "hw/qdev-properties.h"
  29
  30 static void avr_cpu_set_pc(CPUState *cs, vaddr value)
  31 {
  32     AVRCPU *cpu = AVR_CPU(cs);
  33
  34     cpu->env.pc_w = value / 2; /* internally PC points to words */
  35 }
  36
  37 static vaddr avr_cpu_get_pc(CPUState *cs)
  38 {
  39     AVRCPU *cpu = AVR_CPU(cs);
  40
  41     return cpu->env.pc_w * 2;
  42 }
  43
  44 static bool avr_cpu_has_work(CPUState *cs)
  45 {
  46     AVRCPU *cpu = AVR_CPU(cs);
  47     CPUAVRState *env = &cpu->env;
  48
  49     return (cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_RESET))
  50             && cpu_interrupts_enabled(env);
  51 }
  52
  53 static int avr_cpu_mmu_index(CPUState *cs, bool ifetch)
  54 {
  55     return ifetch ? MMU_CODE_IDX : MMU_DATA_IDX;
  56 }
  57
  58 static void avr_cpu_synchronize_from_tb(CPUState *cs,
  59                                         const TranslationBlock *tb)
  60 {
  61     AVRCPU *cpu = AVR_CPU(cs);
  62     CPUAVRState *env = &cpu->env;
  63
  64     tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));
  65     env->pc_w = tb->pc / 2; /* internally PC points to words */
  66 }
  67
  68 static void avr_restore_state_to_opc(CPUState *cs,
  69                                      const TranslationBlock *tb,
  70                                      const uint64_t *data)
  71 {
  72     AVRCPU *cpu = AVR_CPU(cs);
  73     CPUAVRState *env = &cpu->env;
  74
  75     env->pc_w = data[0];
  76 }
  77
  78 static void avr_cpu_reset_hold(Object *obj)
  79 {
  80     CPUState *cs = CPU(obj);
  81     AVRCPU *cpu = AVR_CPU(cs);
  82     AVRCPUClass *mcc = AVR_CPU_GET_CLASS(cpu);
  83     CPUAVRState *env = &cpu->env;
  84
  85     if (mcc->parent_phases.hold) {
  86         mcc->parent_phases.hold(obj);
  87     }
  88
  89     env->pc_w = 0;
  90     env->sregI = 1;
  91     env->sregC = 0;
  92     env->sregZ = 0;
  93     env->sregN = 0;
  94     env->sregV = 0;
  95     env->sregS = 0;
  96     env->sregH = 0;
  97     env->sregT = 0;
  98
  99     env->rampD = 0;
 100     env->rampX = 0;
 101     env->rampY = 0;
 102     env->rampZ = 0;
 103     env->eind = 0;
 104     env->sp = cpu->init_sp;
 105
 106     env->skip = 0;
 107
 108     memset(env->r, 0, sizeof(env->r));
 109 }
 110
 111 static void avr_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
 112 {
 113     info->mach = bfd_arch_avr;
 114     info->print_insn = avr_print_insn;
 115 }
 116
 117 static void avr_cpu_realizefn(DeviceState *dev, Error **errp)
 118 {
 119     CPUState *cs = CPU(dev);
 120     AVRCPUClass *mcc = AVR_CPU_GET_CLASS(dev);
 121     Error *local_err = NULL;
 122
 123     cpu_exec_realizefn(cs, &local_err);
 124     if (local_err != NULL) {
 125         error_propagate(errp, local_err);
 126         return;
 127     }
 128     qemu_init_vcpu(cs);
 129     cpu_reset(cs);
 130
 131     mcc->parent_realize(dev, errp);
 132 }
 133
 134 static void avr_cpu_set_int(void *opaque, int irq, int level)
 135 {
 136     AVRCPU *cpu = opaque;
 137     CPUAVRState *env = &cpu->env;
 138     CPUState *cs = CPU(cpu);
 139     uint64_t mask = (1ull << irq);
 140
 141     if (level) {
 142         env->intsrc |= mask;
 143         cpu_interrupt(cs, CPU_INTERRUPT_HARD);
 144     } else {
 145         env->intsrc &= ~mask;
 146         if (env->intsrc == 0) {
 147             cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
 148         }
 149     }
 150 }
 151
 152 static void avr_cpu_initfn(Object *obj)
 153 {
 154     AVRCPU *cpu = AVR_CPU(obj);
 155
 156     /* Set the number of interrupts supported by the CPU. */
 157     qdev_init_gpio_in(DEVICE(cpu), avr_cpu_set_int,
 158                       sizeof(cpu->env.intsrc) * 8);
 159 }
 160
 161 static Property avr_cpu_properties[] = {
 162     DEFINE_PROP_UINT32("init-sp", AVRCPU, init_sp, 0),
 163     DEFINE_PROP_END_OF_LIST()
 164 };
 165
 166 static ObjectClass *avr_cpu_class_by_name(const char *cpu_model)
 167 {
 168     return object_class_by_name(cpu_model);
 169 }
 170
 171 static void avr_cpu_dump_state(CPUState *cs, FILE *f, int flags)
 172 {
 173     AVRCPU *cpu = AVR_CPU(cs);
 174     CPUAVRState *env = &cpu->env;
 175     int i;
 176
 177     qemu_fprintf(f, "\n");
 178     qemu_fprintf(f, "PC:    %06x\n", env->pc_w * 2); /* PC points to words */
 179     qemu_fprintf(f, "SP:      %04x\n", env->sp);
 180     qemu_fprintf(f, "rampD:     %02x\n", env->rampD >> 16);
 181     qemu_fprintf(f, "rampX:     %02x\n", env->rampX >> 16);
 182     qemu_fprintf(f, "rampY:     %02x\n", env->rampY >> 16);
 183     qemu_fprintf(f, "rampZ:     %02x\n", env->rampZ >> 16);
 184     qemu_fprintf(f, "EIND:      %02x\n", env->eind >> 16);
 185     qemu_fprintf(f, "X:       %02x%02x\n", env->r[27], env->r[26]);
 186     qemu_fprintf(f, "Y:       %02x%02x\n", env->r[29], env->r[28]);
 187     qemu_fprintf(f, "Z:       %02x%02x\n", env->r[31], env->r[30]);
 188     qemu_fprintf(f, "SREG:    [ %c %c %c %c %c %c %c %c ]\n",
 189                  env->sregI ? 'I' : '-',
 190                  env->sregT ? 'T' : '-',
 191                  env->sregH ? 'H' : '-',
 192                  env->sregS ? 'S' : '-',
 193                  env->sregV ? 'V' : '-',
 194                  env->sregN ? '-' : 'N', /* Zf has negative logic */
 195                  env->sregZ ? 'Z' : '-',
 196                  env->sregC ? 'I' : '-');
 197     qemu_fprintf(f, "SKIP:    %02x\n", env->skip);
 198
 199     qemu_fprintf(f, "\n");
 200     for (i = 0; i < ARRAY_SIZE(env->r); i++) {
 201         qemu_fprintf(f, "R[%02d]:  %02x   ", i, env->r[i]);
 202
 203         if ((i % 8) == 7) {
 204             qemu_fprintf(f, "\n");
 205         }
 206     }
 207     qemu_fprintf(f, "\n");
 208 }
 209
 210 #include "hw/core/sysemu-cpu-ops.h"
 211
 212 static const struct SysemuCPUOps avr_sysemu_ops = {
 213     .get_phys_page_debug = avr_cpu_get_phys_page_debug,
 214 };
 215
 216 #include "hw/core/tcg-cpu-ops.h"
 217
 218 static const TCGCPUOps avr_tcg_ops = {
 219     .initialize = avr_cpu_tcg_init,
 220     .synchronize_from_tb = avr_cpu_synchronize_from_tb,
 221     .restore_state_to_opc = avr_restore_state_to_opc,
 222     .cpu_exec_interrupt = avr_cpu_exec_interrupt,
 223     .tlb_fill = avr_cpu_tlb_fill,
 224     .do_interrupt = avr_cpu_do_interrupt,
 225 };
 226
 227 static void avr_cpu_class_init(ObjectClass *oc, void *data)
 228 {
 229     DeviceClass *dc = DEVICE_CLASS(oc);
 230     CPUClass *cc = CPU_CLASS(oc);
 231     AVRCPUClass *mcc = AVR_CPU_CLASS(oc);
 232     ResettableClass *rc = RESETTABLE_CLASS(oc);
 233
 234     device_class_set_parent_realize(dc, avr_cpu_realizefn, &mcc->parent_realize);
 235
 236     device_class_set_props(dc, avr_cpu_properties);
 237
 238     resettable_class_set_parent_phases(rc, NULL, avr_cpu_reset_hold, NULL,
 239                                        &mcc->parent_phases);
 240
 241     cc->class_by_name = avr_cpu_class_by_name;
 242
 243     cc->has_work = avr_cpu_has_work;
 244     cc->mmu_index = avr_cpu_mmu_index;
 245     cc->dump_state = avr_cpu_dump_state;
 246     cc->set_pc = avr_cpu_set_pc;
 247     cc->get_pc = avr_cpu_get_pc;
 248     dc->vmsd = &vms_avr_cpu;
 249     cc->sysemu_ops = &avr_sysemu_ops;
 250     cc->disas_set_info = avr_cpu_disas_set_info;
 251     cc->gdb_read_register = avr_cpu_gdb_read_register;
 252     cc->gdb_write_register = avr_cpu_gdb_write_register;
 253     cc->gdb_adjust_breakpoint = avr_cpu_gdb_adjust_breakpoint;
 254     cc->gdb_core_xml_file = "avr-cpu.xml";
 255     cc->tcg_ops = &avr_tcg_ops;
 256 }
 257
 258 /*
 259  * Setting features of AVR core type avr5
 260  * --------------------------------------
 261  *
 262  * This type of AVR core is present in the following AVR MCUs:
 263  *
 264  * ata5702m322, ata5782, ata5790, ata5790n, ata5791, ata5795, ata5831, ata6613c,
 265  * ata6614q, ata8210, ata8510, atmega16, atmega16a, atmega161, atmega162,
 266  * atmega163, atmega164a, atmega164p, atmega164pa, atmega165, atmega165a,
 267  * atmega165p, atmega165pa, atmega168, atmega168a, atmega168p, atmega168pa,
 268  * atmega168pb, atmega169, atmega169a, atmega169p, atmega169pa, atmega16hvb,
 269  * atmega16hvbrevb, atmega16m1, atmega16u4, atmega32a, atmega32, atmega323,
 270  * atmega324a, atmega324p, atmega324pa, atmega325, atmega325a, atmega325p,
 271  * atmega325pa, atmega3250, atmega3250a, atmega3250p, atmega3250pa, atmega328,
 272  * atmega328p, atmega328pb, atmega329, atmega329a, atmega329p, atmega329pa,
 273  * atmega3290, atmega3290a, atmega3290p, atmega3290pa, atmega32c1, atmega32m1,
 274  * atmega32u4, atmega32u6, atmega406, atmega64, atmega64a, atmega640, atmega644,
 275  * atmega644a, atmega644p, atmega644pa, atmega645, atmega645a, atmega645p,
 276  * atmega6450, atmega6450a, atmega6450p, atmega649, atmega649a, atmega649p,
 277  * atmega6490, atmega16hva, atmega16hva2, atmega32hvb, atmega6490a, atmega6490p,
 278  * atmega64c1, atmega64m1, atmega64hve, atmega64hve2, atmega64rfr2,
 279  * atmega644rfr2, atmega32hvbrevb, at90can32, at90can64, at90pwm161, at90pwm216,
 280  * at90pwm316, at90scr100, at90usb646, at90usb647, at94k, m3000
 281  */
 282 static void avr_avr5_initfn(Object *obj)
 283 {
 284     AVRCPU *cpu = AVR_CPU(obj);
 285     CPUAVRState *env = &cpu->env;
 286
 287     set_avr_feature(env, AVR_FEATURE_LPM);
 288     set_avr_feature(env, AVR_FEATURE_IJMP_ICALL);
 289     set_avr_feature(env, AVR_FEATURE_ADIW_SBIW);
 290     set_avr_feature(env, AVR_FEATURE_SRAM);
 291     set_avr_feature(env, AVR_FEATURE_BREAK);
 292
 293     set_avr_feature(env, AVR_FEATURE_2_BYTE_PC);
 294     set_avr_feature(env, AVR_FEATURE_2_BYTE_SP);
 295     set_avr_feature(env, AVR_FEATURE_JMP_CALL);
 296     set_avr_feature(env, AVR_FEATURE_LPMX);
 297     set_avr_feature(env, AVR_FEATURE_MOVW);
 298     set_avr_feature(env, AVR_FEATURE_MUL);
 299 }
 300
 301 /*
 302  * Setting features of AVR core type avr51
 303  * --------------------------------------
 304  *
 305  * This type of AVR core is present in the following AVR MCUs:
 306  *
 307  * atmega128, atmega128a, atmega1280, atmega1281, atmega1284, atmega1284p,
 308  * atmega128rfa1, atmega128rfr2, atmega1284rfr2, at90can128, at90usb1286,
 309  * at90usb1287
 310  */
 311 static void avr_avr51_initfn(Object *obj)
 312 {
 313     AVRCPU *cpu = AVR_CPU(obj);
 314     CPUAVRState *env = &cpu->env;
 315
 316     set_avr_feature(env, AVR_FEATURE_LPM);
 317     set_avr_feature(env, AVR_FEATURE_IJMP_ICALL);
 318     set_avr_feature(env, AVR_FEATURE_ADIW_SBIW);
 319     set_avr_feature(env, AVR_FEATURE_SRAM);
 320     set_avr_feature(env, AVR_FEATURE_BREAK);
 321
 322     set_avr_feature(env, AVR_FEATURE_2_BYTE_PC);
 323     set_avr_feature(env, AVR_FEATURE_2_BYTE_SP);
 324     set_avr_feature(env, AVR_FEATURE_RAMPZ);
 325     set_avr_feature(env, AVR_FEATURE_ELPMX);
 326     set_avr_feature(env, AVR_FEATURE_ELPM);
 327     set_avr_feature(env, AVR_FEATURE_JMP_CALL);
 328     set_avr_feature(env, AVR_FEATURE_LPMX);
 329     set_avr_feature(env, AVR_FEATURE_MOVW);
 330     set_avr_feature(env, AVR_FEATURE_MUL);
 331 }
 332
 333 /*
 334  * Setting features of AVR core type avr6
 335  * --------------------------------------
 336  *
 337  * This type of AVR core is present in the following AVR MCUs:
 338  *
 339  * atmega2560, atmega2561, atmega256rfr2, atmega2564rfr2
 340  */
 341 static void avr_avr6_initfn(Object *obj)
 342 {
 343     AVRCPU *cpu = AVR_CPU(obj);
 344     CPUAVRState *env = &cpu->env;
 345
 346     set_avr_feature(env, AVR_FEATURE_LPM);
 347     set_avr_feature(env, AVR_FEATURE_IJMP_ICALL);
 348     set_avr_feature(env, AVR_FEATURE_ADIW_SBIW);
 349     set_avr_feature(env, AVR_FEATURE_SRAM);
 350     set_avr_feature(env, AVR_FEATURE_BREAK);
 351
 352     set_avr_feature(env, AVR_FEATURE_3_BYTE_PC);
 353     set_avr_feature(env, AVR_FEATURE_2_BYTE_SP);
 354     set_avr_feature(env, AVR_FEATURE_RAMPZ);
 355     set_avr_feature(env, AVR_FEATURE_EIJMP_EICALL);
 356     set_avr_feature(env, AVR_FEATURE_ELPMX);
 357     set_avr_feature(env, AVR_FEATURE_ELPM);
 358     set_avr_feature(env, AVR_FEATURE_JMP_CALL);
 359     set_avr_feature(env, AVR_FEATURE_LPMX);
 360     set_avr_feature(env, AVR_FEATURE_MOVW);
 361     set_avr_feature(env, AVR_FEATURE_MUL);
 362 }
 363
 364 typedef struct AVRCPUInfo {
 365     const char *name;
 366     void (*initfn)(Object *obj);
 367 } AVRCPUInfo;
 368
 369
 370 #define DEFINE_AVR_CPU_TYPE(model, initfn) \
 371     { \
 372         .parent = TYPE_AVR_CPU, \
 373         .instance_init = initfn, \
 374         .name = AVR_CPU_TYPE_NAME(model), \
 375     }
 376
 377 static const TypeInfo avr_cpu_type_info[] = {
 378     {
 379         .name = TYPE_AVR_CPU,
 380         .parent = TYPE_CPU,
 381         .instance_size = sizeof(AVRCPU),
 382         .instance_align = __alignof(AVRCPU),
 383         .instance_init = avr_cpu_initfn,
 384         .class_size = sizeof(AVRCPUClass),
 385         .class_init = avr_cpu_class_init,
 386         .abstract = true,
 387     },
 388     DEFINE_AVR_CPU_TYPE("avr5", avr_avr5_initfn),
 389     DEFINE_AVR_CPU_TYPE("avr51", avr_avr51_initfn),
 390     DEFINE_AVR_CPU_TYPE("avr6", avr_avr6_initfn),
 391 };
 392
 393 DEFINE_TYPES(avr_cpu_type_info)