4 * Copyright (c) 2013 Alexander Graf <agraf@suse.de>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
22 #include "exec/exec-all.h"
23 #include "tcg/tcg-op.h"
24 #include "tcg/tcg-op-gvec.h"
27 #include "translate.h"
28 #include "internals.h"
29 #include "qemu/host-utils.h"
31 #include "hw/semihosting/semihost.h"
32 #include "exec/gen-icount.h"
34 #include "exec/helper-proto.h"
35 #include "exec/helper-gen.h"
38 #include "trace-tcg.h"
39 #include "translate-a64.h"
40 #include "qemu/atomic128.h"
42 static TCGv_i64 cpu_X
[32];
43 static TCGv_i64 cpu_pc
;
45 /* Load/store exclusive handling */
46 static TCGv_i64 cpu_exclusive_high
;
48 static const char *regnames
[] = {
49 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
50 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
51 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
52 "x24", "x25", "x26", "x27", "x28", "x29", "lr", "sp"
56 A64_SHIFT_TYPE_LSL
= 0,
57 A64_SHIFT_TYPE_LSR
= 1,
58 A64_SHIFT_TYPE_ASR
= 2,
59 A64_SHIFT_TYPE_ROR
= 3
62 /* Table based decoder typedefs - used when the relevant bits for decode
63 * are too awkwardly scattered across the instruction (eg SIMD).
65 typedef void AArch64DecodeFn(DisasContext
*s
, uint32_t insn
);
67 typedef struct AArch64DecodeTable
{
70 AArch64DecodeFn
*disas_fn
;
73 /* Function prototype for gen_ functions for calling Neon helpers */
74 typedef void NeonGenOneOpEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i32
);
75 typedef void NeonGenTwoOpFn(TCGv_i32
, TCGv_i32
, TCGv_i32
);
76 typedef void NeonGenTwoOpEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i32
, TCGv_i32
);
77 typedef void NeonGenTwo64OpFn(TCGv_i64
, TCGv_i64
, TCGv_i64
);
78 typedef void NeonGenTwo64OpEnvFn(TCGv_i64
, TCGv_ptr
, TCGv_i64
, TCGv_i64
);
79 typedef void NeonGenNarrowFn(TCGv_i32
, TCGv_i64
);
80 typedef void NeonGenNarrowEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i64
);
81 typedef void NeonGenWidenFn(TCGv_i64
, TCGv_i32
);
82 typedef void NeonGenTwoSingleOPFn(TCGv_i32
, TCGv_i32
, TCGv_i32
, TCGv_ptr
);
83 typedef void NeonGenTwoDoubleOPFn(TCGv_i64
, TCGv_i64
, TCGv_i64
, TCGv_ptr
);
84 typedef void NeonGenOneOpFn(TCGv_i64
, TCGv_i64
);
85 typedef void CryptoTwoOpFn(TCGv_ptr
, TCGv_ptr
);
86 typedef void CryptoThreeOpIntFn(TCGv_ptr
, TCGv_ptr
, TCGv_i32
);
87 typedef void CryptoThreeOpFn(TCGv_ptr
, TCGv_ptr
, TCGv_ptr
);
88 typedef void AtomicThreeOpFn(TCGv_i64
, TCGv_i64
, TCGv_i64
, TCGArg
, MemOp
);
90 /* initialize TCG globals. */
91 void a64_translate_init(void)
95 cpu_pc
= tcg_global_mem_new_i64(cpu_env
,
96 offsetof(CPUARMState
, pc
),
98 for (i
= 0; i
< 32; i
++) {
99 cpu_X
[i
] = tcg_global_mem_new_i64(cpu_env
,
100 offsetof(CPUARMState
, xregs
[i
]),
104 cpu_exclusive_high
= tcg_global_mem_new_i64(cpu_env
,
105 offsetof(CPUARMState
, exclusive_high
), "exclusive_high");
109 * Return the core mmu_idx to use for A64 "unprivileged load/store" insns
111 static int get_a64_user_mem_index(DisasContext
*s
)
114 * If AccType_UNPRIV is not used, the insn uses AccType_NORMAL,
115 * which is the usual mmu_idx for this cpu state.
117 ARMMMUIdx useridx
= s
->mmu_idx
;
121 * We have pre-computed the condition for AccType_UNPRIV.
122 * Therefore we should never get here with a mmu_idx for
123 * which we do not know the corresponding user mmu_idx.
126 case ARMMMUIdx_E10_1
:
127 case ARMMMUIdx_E10_1_PAN
:
128 useridx
= ARMMMUIdx_E10_0
;
130 case ARMMMUIdx_E20_2
:
131 case ARMMMUIdx_E20_2_PAN
:
132 useridx
= ARMMMUIdx_E20_0
;
134 case ARMMMUIdx_SE10_1
:
135 case ARMMMUIdx_SE10_1_PAN
:
136 useridx
= ARMMMUIdx_SE10_0
;
139 g_assert_not_reached();
142 return arm_to_core_mmu_idx(useridx
);
145 static void reset_btype(DisasContext
*s
)
148 TCGv_i32 zero
= tcg_const_i32(0);
149 tcg_gen_st_i32(zero
, cpu_env
, offsetof(CPUARMState
, btype
));
150 tcg_temp_free_i32(zero
);
155 static void set_btype(DisasContext
*s
, int val
)
159 /* BTYPE is a 2-bit field, and 0 should be done with reset_btype. */
160 tcg_debug_assert(val
>= 1 && val
<= 3);
162 tcg_val
= tcg_const_i32(val
);
163 tcg_gen_st_i32(tcg_val
, cpu_env
, offsetof(CPUARMState
, btype
));
164 tcg_temp_free_i32(tcg_val
);
168 void gen_a64_set_pc_im(uint64_t val
)
170 tcg_gen_movi_i64(cpu_pc
, val
);
174 * Handle Top Byte Ignore (TBI) bits.
176 * If address tagging is enabled via the TCR TBI bits:
177 * + for EL2 and EL3 there is only one TBI bit, and if it is set
178 * then the address is zero-extended, clearing bits [63:56]
179 * + for EL0 and EL1, TBI0 controls addresses with bit 55 == 0
180 * and TBI1 controls addressses with bit 55 == 1.
181 * If the appropriate TBI bit is set for the address then
182 * the address is sign-extended from bit 55 into bits [63:56]
184 * Here We have concatenated TBI{1,0} into tbi.
186 static void gen_top_byte_ignore(DisasContext
*s
, TCGv_i64 dst
,
187 TCGv_i64 src
, int tbi
)
190 /* Load unmodified address */
191 tcg_gen_mov_i64(dst
, src
);
192 } else if (!regime_has_2_ranges(s
->mmu_idx
)) {
193 /* Force tag byte to all zero */
194 tcg_gen_extract_i64(dst
, src
, 0, 56);
196 /* Sign-extend from bit 55. */
197 tcg_gen_sextract_i64(dst
, src
, 0, 56);
200 TCGv_i64 tcg_zero
= tcg_const_i64(0);
203 * The two TBI bits differ.
204 * If tbi0, then !tbi1: only use the extension if positive.
205 * if !tbi0, then tbi1: only use the extension if negative.
207 tcg_gen_movcond_i64(tbi
== 1 ? TCG_COND_GE
: TCG_COND_LT
,
208 dst
, dst
, tcg_zero
, dst
, src
);
209 tcg_temp_free_i64(tcg_zero
);
214 static void gen_a64_set_pc(DisasContext
*s
, TCGv_i64 src
)
217 * If address tagging is enabled for instructions via the TCR TBI bits,
218 * then loading an address into the PC will clear out any tag.
220 gen_top_byte_ignore(s
, cpu_pc
, src
, s
->tbii
);
224 * Return a "clean" address for ADDR according to TBID.
225 * This is always a fresh temporary, as we need to be able to
226 * increment this independently of a dirty write-back address.
228 static TCGv_i64
clean_data_tbi(DisasContext
*s
, TCGv_i64 addr
)
230 TCGv_i64 clean
= new_tmp_a64(s
);
232 * In order to get the correct value in the FAR_ELx register,
233 * we must present the memory subsystem with the "dirty" address
234 * including the TBI. In system mode we can make this work via
235 * the TLB, dropping the TBI during translation. But for user-only
236 * mode we don't have that option, and must remove the top byte now.
238 #ifdef CONFIG_USER_ONLY
239 gen_top_byte_ignore(s
, clean
, addr
, s
->tbid
);
241 tcg_gen_mov_i64(clean
, addr
);
246 typedef struct DisasCompare64
{
251 static void a64_test_cc(DisasCompare64
*c64
, int cc
)
255 arm_test_cc(&c32
, cc
);
257 /* Sign-extend the 32-bit value so that the GE/LT comparisons work
258 * properly. The NE/EQ comparisons are also fine with this choice. */
259 c64
->cond
= c32
.cond
;
260 c64
->value
= tcg_temp_new_i64();
261 tcg_gen_ext_i32_i64(c64
->value
, c32
.value
);
266 static void a64_free_cc(DisasCompare64
*c64
)
268 tcg_temp_free_i64(c64
->value
);
271 static void gen_exception_internal(int excp
)
273 TCGv_i32 tcg_excp
= tcg_const_i32(excp
);
275 assert(excp_is_internal(excp
));
276 gen_helper_exception_internal(cpu_env
, tcg_excp
);
277 tcg_temp_free_i32(tcg_excp
);
280 static void gen_exception_internal_insn(DisasContext
*s
, uint64_t pc
, int excp
)
282 gen_a64_set_pc_im(pc
);
283 gen_exception_internal(excp
);
284 s
->base
.is_jmp
= DISAS_NORETURN
;
287 static void gen_exception_insn(DisasContext
*s
, uint64_t pc
, int excp
,
288 uint32_t syndrome
, uint32_t target_el
)
290 gen_a64_set_pc_im(pc
);
291 gen_exception(excp
, syndrome
, target_el
);
292 s
->base
.is_jmp
= DISAS_NORETURN
;
295 static void gen_exception_bkpt_insn(DisasContext
*s
, uint32_t syndrome
)
299 gen_a64_set_pc_im(s
->pc_curr
);
300 tcg_syn
= tcg_const_i32(syndrome
);
301 gen_helper_exception_bkpt_insn(cpu_env
, tcg_syn
);
302 tcg_temp_free_i32(tcg_syn
);
303 s
->base
.is_jmp
= DISAS_NORETURN
;
306 static void gen_step_complete_exception(DisasContext
*s
)
308 /* We just completed step of an insn. Move from Active-not-pending
309 * to Active-pending, and then also take the swstep exception.
310 * This corresponds to making the (IMPDEF) choice to prioritize
311 * swstep exceptions over asynchronous exceptions taken to an exception
312 * level where debug is disabled. This choice has the advantage that
313 * we do not need to maintain internal state corresponding to the
314 * ISV/EX syndrome bits between completion of the step and generation
315 * of the exception, and our syndrome information is always correct.
318 gen_swstep_exception(s
, 1, s
->is_ldex
);
319 s
->base
.is_jmp
= DISAS_NORETURN
;
322 static inline bool use_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
324 /* No direct tb linking with singlestep (either QEMU's or the ARM
325 * debug architecture kind) or deterministic io
327 if (s
->base
.singlestep_enabled
|| s
->ss_active
||
328 (tb_cflags(s
->base
.tb
) & CF_LAST_IO
)) {
332 #ifndef CONFIG_USER_ONLY
333 /* Only link tbs from inside the same guest page */
334 if ((s
->base
.tb
->pc
& TARGET_PAGE_MASK
) != (dest
& TARGET_PAGE_MASK
)) {
342 static inline void gen_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
344 TranslationBlock
*tb
;
347 if (use_goto_tb(s
, n
, dest
)) {
349 gen_a64_set_pc_im(dest
);
350 tcg_gen_exit_tb(tb
, n
);
351 s
->base
.is_jmp
= DISAS_NORETURN
;
353 gen_a64_set_pc_im(dest
);
355 gen_step_complete_exception(s
);
356 } else if (s
->base
.singlestep_enabled
) {
357 gen_exception_internal(EXCP_DEBUG
);
359 tcg_gen_lookup_and_goto_ptr();
360 s
->base
.is_jmp
= DISAS_NORETURN
;
365 void unallocated_encoding(DisasContext
*s
)
367 /* Unallocated and reserved encodings are uncategorized */
368 gen_exception_insn(s
, s
->pc_curr
, EXCP_UDEF
, syn_uncategorized(),
369 default_exception_el(s
));
372 static void init_tmp_a64_array(DisasContext
*s
)
374 #ifdef CONFIG_DEBUG_TCG
375 memset(s
->tmp_a64
, 0, sizeof(s
->tmp_a64
));
377 s
->tmp_a64_count
= 0;
380 static void free_tmp_a64(DisasContext
*s
)
383 for (i
= 0; i
< s
->tmp_a64_count
; i
++) {
384 tcg_temp_free_i64(s
->tmp_a64
[i
]);
386 init_tmp_a64_array(s
);
389 TCGv_i64
new_tmp_a64(DisasContext
*s
)
391 assert(s
->tmp_a64_count
< TMP_A64_MAX
);
392 return s
->tmp_a64
[s
->tmp_a64_count
++] = tcg_temp_new_i64();
395 TCGv_i64
new_tmp_a64_zero(DisasContext
*s
)
397 TCGv_i64 t
= new_tmp_a64(s
);
398 tcg_gen_movi_i64(t
, 0);
403 * Register access functions
405 * These functions are used for directly accessing a register in where
406 * changes to the final register value are likely to be made. If you
407 * need to use a register for temporary calculation (e.g. index type
408 * operations) use the read_* form.
410 * B1.2.1 Register mappings
412 * In instruction register encoding 31 can refer to ZR (zero register) or
413 * the SP (stack pointer) depending on context. In QEMU's case we map SP
414 * to cpu_X[31] and ZR accesses to a temporary which can be discarded.
415 * This is the point of the _sp forms.
417 TCGv_i64
cpu_reg(DisasContext
*s
, int reg
)
420 return new_tmp_a64_zero(s
);
426 /* register access for when 31 == SP */
427 TCGv_i64
cpu_reg_sp(DisasContext
*s
, int reg
)
432 /* read a cpu register in 32bit/64bit mode. Returns a TCGv_i64
433 * representing the register contents. This TCGv is an auto-freed
434 * temporary so it need not be explicitly freed, and may be modified.
436 TCGv_i64
read_cpu_reg(DisasContext
*s
, int reg
, int sf
)
438 TCGv_i64 v
= new_tmp_a64(s
);
441 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
443 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
446 tcg_gen_movi_i64(v
, 0);
451 TCGv_i64
read_cpu_reg_sp(DisasContext
*s
, int reg
, int sf
)
453 TCGv_i64 v
= new_tmp_a64(s
);
455 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
457 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
462 /* Return the offset into CPUARMState of a slice (from
463 * the least significant end) of FP register Qn (ie
465 * (Note that this is not the same mapping as for A32; see cpu.h)
467 static inline int fp_reg_offset(DisasContext
*s
, int regno
, MemOp size
)
469 return vec_reg_offset(s
, regno
, 0, size
);
472 /* Offset of the high half of the 128 bit vector Qn */
473 static inline int fp_reg_hi_offset(DisasContext
*s
, int regno
)
475 return vec_reg_offset(s
, regno
, 1, MO_64
);
478 /* Convenience accessors for reading and writing single and double
479 * FP registers. Writing clears the upper parts of the associated
480 * 128 bit vector register, as required by the architecture.
481 * Note that unlike the GP register accessors, the values returned
482 * by the read functions must be manually freed.
484 static TCGv_i64
read_fp_dreg(DisasContext
*s
, int reg
)
486 TCGv_i64 v
= tcg_temp_new_i64();
488 tcg_gen_ld_i64(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_64
));
492 static TCGv_i32
read_fp_sreg(DisasContext
*s
, int reg
)
494 TCGv_i32 v
= tcg_temp_new_i32();
496 tcg_gen_ld_i32(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_32
));
500 static TCGv_i32
read_fp_hreg(DisasContext
*s
, int reg
)
502 TCGv_i32 v
= tcg_temp_new_i32();
504 tcg_gen_ld16u_i32(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_16
));
508 /* Clear the bits above an N-bit vector, for N = (is_q ? 128 : 64).
509 * If SVE is not enabled, then there are only 128 bits in the vector.
511 static void clear_vec_high(DisasContext
*s
, bool is_q
, int rd
)
513 unsigned ofs
= fp_reg_offset(s
, rd
, MO_64
);
514 unsigned vsz
= vec_full_reg_size(s
);
517 TCGv_i64 tcg_zero
= tcg_const_i64(0);
518 tcg_gen_st_i64(tcg_zero
, cpu_env
, ofs
+ 8);
519 tcg_temp_free_i64(tcg_zero
);
522 tcg_gen_gvec_dup8i(ofs
+ 16, vsz
- 16, vsz
- 16, 0);
526 void write_fp_dreg(DisasContext
*s
, int reg
, TCGv_i64 v
)
528 unsigned ofs
= fp_reg_offset(s
, reg
, MO_64
);
530 tcg_gen_st_i64(v
, cpu_env
, ofs
);
531 clear_vec_high(s
, false, reg
);
534 static void write_fp_sreg(DisasContext
*s
, int reg
, TCGv_i32 v
)
536 TCGv_i64 tmp
= tcg_temp_new_i64();
538 tcg_gen_extu_i32_i64(tmp
, v
);
539 write_fp_dreg(s
, reg
, tmp
);
540 tcg_temp_free_i64(tmp
);
543 TCGv_ptr
get_fpstatus_ptr(bool is_f16
)
545 TCGv_ptr statusptr
= tcg_temp_new_ptr();
548 /* In A64 all instructions (both FP and Neon) use the FPCR; there
549 * is no equivalent of the A32 Neon "standard FPSCR value".
550 * However half-precision operations operate under a different
551 * FZ16 flag and use vfp.fp_status_f16 instead of vfp.fp_status.
554 offset
= offsetof(CPUARMState
, vfp
.fp_status_f16
);
556 offset
= offsetof(CPUARMState
, vfp
.fp_status
);
558 tcg_gen_addi_ptr(statusptr
, cpu_env
, offset
);
562 /* Expand a 2-operand AdvSIMD vector operation using an expander function. */
563 static void gen_gvec_fn2(DisasContext
*s
, bool is_q
, int rd
, int rn
,
564 GVecGen2Fn
*gvec_fn
, int vece
)
566 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
567 is_q
? 16 : 8, vec_full_reg_size(s
));
570 /* Expand a 2-operand + immediate AdvSIMD vector operation using
571 * an expander function.
573 static void gen_gvec_fn2i(DisasContext
*s
, bool is_q
, int rd
, int rn
,
574 int64_t imm
, GVecGen2iFn
*gvec_fn
, int vece
)
576 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
577 imm
, is_q
? 16 : 8, vec_full_reg_size(s
));
580 /* Expand a 3-operand AdvSIMD vector operation using an expander function. */
581 static void gen_gvec_fn3(DisasContext
*s
, bool is_q
, int rd
, int rn
, int rm
,
582 GVecGen3Fn
*gvec_fn
, int vece
)
584 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
585 vec_full_reg_offset(s
, rm
), is_q
? 16 : 8, vec_full_reg_size(s
));
588 /* Expand a 4-operand AdvSIMD vector operation using an expander function. */
589 static void gen_gvec_fn4(DisasContext
*s
, bool is_q
, int rd
, int rn
, int rm
,
590 int rx
, GVecGen4Fn
*gvec_fn
, int vece
)
592 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
593 vec_full_reg_offset(s
, rm
), vec_full_reg_offset(s
, rx
),
594 is_q
? 16 : 8, vec_full_reg_size(s
));
597 /* Expand a 2-operand + immediate AdvSIMD vector operation using
600 static void gen_gvec_op2i(DisasContext
*s
, bool is_q
, int rd
,
601 int rn
, int64_t imm
, const GVecGen2i
*gvec_op
)
603 tcg_gen_gvec_2i(vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
604 is_q
? 16 : 8, vec_full_reg_size(s
), imm
, gvec_op
);
607 /* Expand a 3-operand AdvSIMD vector operation using an op descriptor. */
608 static void gen_gvec_op3(DisasContext
*s
, bool is_q
, int rd
,
609 int rn
, int rm
, const GVecGen3
*gvec_op
)
611 tcg_gen_gvec_3(vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
612 vec_full_reg_offset(s
, rm
), is_q
? 16 : 8,
613 vec_full_reg_size(s
), gvec_op
);
616 /* Expand a 3-operand operation using an out-of-line helper. */
617 static void gen_gvec_op3_ool(DisasContext
*s
, bool is_q
, int rd
,
618 int rn
, int rm
, int data
, gen_helper_gvec_3
*fn
)
620 tcg_gen_gvec_3_ool(vec_full_reg_offset(s
, rd
),
621 vec_full_reg_offset(s
, rn
),
622 vec_full_reg_offset(s
, rm
),
623 is_q
? 16 : 8, vec_full_reg_size(s
), data
, fn
);
626 /* Expand a 3-operand + env pointer operation using
627 * an out-of-line helper.
629 static void gen_gvec_op3_env(DisasContext
*s
, bool is_q
, int rd
,
630 int rn
, int rm
, gen_helper_gvec_3_ptr
*fn
)
632 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
633 vec_full_reg_offset(s
, rn
),
634 vec_full_reg_offset(s
, rm
), cpu_env
,
635 is_q
? 16 : 8, vec_full_reg_size(s
), 0, fn
);
638 /* Expand a 3-operand + fpstatus pointer + simd data value operation using
639 * an out-of-line helper.
641 static void gen_gvec_op3_fpst(DisasContext
*s
, bool is_q
, int rd
, int rn
,
642 int rm
, bool is_fp16
, int data
,
643 gen_helper_gvec_3_ptr
*fn
)
645 TCGv_ptr fpst
= get_fpstatus_ptr(is_fp16
);
646 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
647 vec_full_reg_offset(s
, rn
),
648 vec_full_reg_offset(s
, rm
), fpst
,
649 is_q
? 16 : 8, vec_full_reg_size(s
), data
, fn
);
650 tcg_temp_free_ptr(fpst
);
653 /* Set ZF and NF based on a 64 bit result. This is alas fiddlier
654 * than the 32 bit equivalent.
656 static inline void gen_set_NZ64(TCGv_i64 result
)
658 tcg_gen_extr_i64_i32(cpu_ZF
, cpu_NF
, result
);
659 tcg_gen_or_i32(cpu_ZF
, cpu_ZF
, cpu_NF
);
662 /* Set NZCV as for a logical operation: NZ as per result, CV cleared. */
663 static inline void gen_logic_CC(int sf
, TCGv_i64 result
)
666 gen_set_NZ64(result
);
668 tcg_gen_extrl_i64_i32(cpu_ZF
, result
);
669 tcg_gen_mov_i32(cpu_NF
, cpu_ZF
);
671 tcg_gen_movi_i32(cpu_CF
, 0);
672 tcg_gen_movi_i32(cpu_VF
, 0);
675 /* dest = T0 + T1; compute C, N, V and Z flags */
676 static void gen_add_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
679 TCGv_i64 result
, flag
, tmp
;
680 result
= tcg_temp_new_i64();
681 flag
= tcg_temp_new_i64();
682 tmp
= tcg_temp_new_i64();
684 tcg_gen_movi_i64(tmp
, 0);
685 tcg_gen_add2_i64(result
, flag
, t0
, tmp
, t1
, tmp
);
687 tcg_gen_extrl_i64_i32(cpu_CF
, flag
);
689 gen_set_NZ64(result
);
691 tcg_gen_xor_i64(flag
, result
, t0
);
692 tcg_gen_xor_i64(tmp
, t0
, t1
);
693 tcg_gen_andc_i64(flag
, flag
, tmp
);
694 tcg_temp_free_i64(tmp
);
695 tcg_gen_extrh_i64_i32(cpu_VF
, flag
);
697 tcg_gen_mov_i64(dest
, result
);
698 tcg_temp_free_i64(result
);
699 tcg_temp_free_i64(flag
);
701 /* 32 bit arithmetic */
702 TCGv_i32 t0_32
= tcg_temp_new_i32();
703 TCGv_i32 t1_32
= tcg_temp_new_i32();
704 TCGv_i32 tmp
= tcg_temp_new_i32();
706 tcg_gen_movi_i32(tmp
, 0);
707 tcg_gen_extrl_i64_i32(t0_32
, t0
);
708 tcg_gen_extrl_i64_i32(t1_32
, t1
);
709 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, t1_32
, tmp
);
710 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
711 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
712 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
713 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
714 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
716 tcg_temp_free_i32(tmp
);
717 tcg_temp_free_i32(t0_32
);
718 tcg_temp_free_i32(t1_32
);
722 /* dest = T0 - T1; compute C, N, V and Z flags */
723 static void gen_sub_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
726 /* 64 bit arithmetic */
727 TCGv_i64 result
, flag
, tmp
;
729 result
= tcg_temp_new_i64();
730 flag
= tcg_temp_new_i64();
731 tcg_gen_sub_i64(result
, t0
, t1
);
733 gen_set_NZ64(result
);
735 tcg_gen_setcond_i64(TCG_COND_GEU
, flag
, t0
, t1
);
736 tcg_gen_extrl_i64_i32(cpu_CF
, flag
);
738 tcg_gen_xor_i64(flag
, result
, t0
);
739 tmp
= tcg_temp_new_i64();
740 tcg_gen_xor_i64(tmp
, t0
, t1
);
741 tcg_gen_and_i64(flag
, flag
, tmp
);
742 tcg_temp_free_i64(tmp
);
743 tcg_gen_extrh_i64_i32(cpu_VF
, flag
);
744 tcg_gen_mov_i64(dest
, result
);
745 tcg_temp_free_i64(flag
);
746 tcg_temp_free_i64(result
);
748 /* 32 bit arithmetic */
749 TCGv_i32 t0_32
= tcg_temp_new_i32();
750 TCGv_i32 t1_32
= tcg_temp_new_i32();
753 tcg_gen_extrl_i64_i32(t0_32
, t0
);
754 tcg_gen_extrl_i64_i32(t1_32
, t1
);
755 tcg_gen_sub_i32(cpu_NF
, t0_32
, t1_32
);
756 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
757 tcg_gen_setcond_i32(TCG_COND_GEU
, cpu_CF
, t0_32
, t1_32
);
758 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
759 tmp
= tcg_temp_new_i32();
760 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
761 tcg_temp_free_i32(t0_32
);
762 tcg_temp_free_i32(t1_32
);
763 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tmp
);
764 tcg_temp_free_i32(tmp
);
765 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
769 /* dest = T0 + T1 + CF; do not compute flags. */
770 static void gen_adc(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
772 TCGv_i64 flag
= tcg_temp_new_i64();
773 tcg_gen_extu_i32_i64(flag
, cpu_CF
);
774 tcg_gen_add_i64(dest
, t0
, t1
);
775 tcg_gen_add_i64(dest
, dest
, flag
);
776 tcg_temp_free_i64(flag
);
779 tcg_gen_ext32u_i64(dest
, dest
);
783 /* dest = T0 + T1 + CF; compute C, N, V and Z flags. */
784 static void gen_adc_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
787 TCGv_i64 result
, cf_64
, vf_64
, tmp
;
788 result
= tcg_temp_new_i64();
789 cf_64
= tcg_temp_new_i64();
790 vf_64
= tcg_temp_new_i64();
791 tmp
= tcg_const_i64(0);
793 tcg_gen_extu_i32_i64(cf_64
, cpu_CF
);
794 tcg_gen_add2_i64(result
, cf_64
, t0
, tmp
, cf_64
, tmp
);
795 tcg_gen_add2_i64(result
, cf_64
, result
, cf_64
, t1
, tmp
);
796 tcg_gen_extrl_i64_i32(cpu_CF
, cf_64
);
797 gen_set_NZ64(result
);
799 tcg_gen_xor_i64(vf_64
, result
, t0
);
800 tcg_gen_xor_i64(tmp
, t0
, t1
);
801 tcg_gen_andc_i64(vf_64
, vf_64
, tmp
);
802 tcg_gen_extrh_i64_i32(cpu_VF
, vf_64
);
804 tcg_gen_mov_i64(dest
, result
);
806 tcg_temp_free_i64(tmp
);
807 tcg_temp_free_i64(vf_64
);
808 tcg_temp_free_i64(cf_64
);
809 tcg_temp_free_i64(result
);
811 TCGv_i32 t0_32
, t1_32
, tmp
;
812 t0_32
= tcg_temp_new_i32();
813 t1_32
= tcg_temp_new_i32();
814 tmp
= tcg_const_i32(0);
816 tcg_gen_extrl_i64_i32(t0_32
, t0
);
817 tcg_gen_extrl_i64_i32(t1_32
, t1
);
818 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, cpu_CF
, tmp
);
819 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, cpu_NF
, cpu_CF
, t1_32
, tmp
);
821 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
822 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
823 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
824 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
825 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
827 tcg_temp_free_i32(tmp
);
828 tcg_temp_free_i32(t1_32
);
829 tcg_temp_free_i32(t0_32
);
834 * Load/Store generators
838 * Store from GPR register to memory.
840 static void do_gpr_st_memidx(DisasContext
*s
, TCGv_i64 source
,
841 TCGv_i64 tcg_addr
, int size
, int memidx
,
843 unsigned int iss_srt
,
844 bool iss_sf
, bool iss_ar
)
847 tcg_gen_qemu_st_i64(source
, tcg_addr
, memidx
, s
->be_data
+ size
);
852 syn
= syn_data_abort_with_iss(0,
858 0, 0, 0, 0, 0, false);
859 disas_set_insn_syndrome(s
, syn
);
863 static void do_gpr_st(DisasContext
*s
, TCGv_i64 source
,
864 TCGv_i64 tcg_addr
, int size
,
866 unsigned int iss_srt
,
867 bool iss_sf
, bool iss_ar
)
869 do_gpr_st_memidx(s
, source
, tcg_addr
, size
, get_mem_index(s
),
870 iss_valid
, iss_srt
, iss_sf
, iss_ar
);
874 * Load from memory to GPR register
876 static void do_gpr_ld_memidx(DisasContext
*s
,
877 TCGv_i64 dest
, TCGv_i64 tcg_addr
,
878 int size
, bool is_signed
,
879 bool extend
, int memidx
,
880 bool iss_valid
, unsigned int iss_srt
,
881 bool iss_sf
, bool iss_ar
)
883 MemOp memop
= s
->be_data
+ size
;
891 tcg_gen_qemu_ld_i64(dest
, tcg_addr
, memidx
, memop
);
893 if (extend
&& is_signed
) {
895 tcg_gen_ext32u_i64(dest
, dest
);
901 syn
= syn_data_abort_with_iss(0,
907 0, 0, 0, 0, 0, false);
908 disas_set_insn_syndrome(s
, syn
);
912 static void do_gpr_ld(DisasContext
*s
,
913 TCGv_i64 dest
, TCGv_i64 tcg_addr
,
914 int size
, bool is_signed
, bool extend
,
915 bool iss_valid
, unsigned int iss_srt
,
916 bool iss_sf
, bool iss_ar
)
918 do_gpr_ld_memidx(s
, dest
, tcg_addr
, size
, is_signed
, extend
,
920 iss_valid
, iss_srt
, iss_sf
, iss_ar
);
924 * Store from FP register to memory
926 static void do_fp_st(DisasContext
*s
, int srcidx
, TCGv_i64 tcg_addr
, int size
)
928 /* This writes the bottom N bits of a 128 bit wide vector to memory */
929 TCGv_i64 tmp
= tcg_temp_new_i64();
930 tcg_gen_ld_i64(tmp
, cpu_env
, fp_reg_offset(s
, srcidx
, MO_64
));
932 tcg_gen_qemu_st_i64(tmp
, tcg_addr
, get_mem_index(s
),
935 bool be
= s
->be_data
== MO_BE
;
936 TCGv_i64 tcg_hiaddr
= tcg_temp_new_i64();
938 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
939 tcg_gen_qemu_st_i64(tmp
, be
? tcg_hiaddr
: tcg_addr
, get_mem_index(s
),
941 tcg_gen_ld_i64(tmp
, cpu_env
, fp_reg_hi_offset(s
, srcidx
));
942 tcg_gen_qemu_st_i64(tmp
, be
? tcg_addr
: tcg_hiaddr
, get_mem_index(s
),
944 tcg_temp_free_i64(tcg_hiaddr
);
947 tcg_temp_free_i64(tmp
);
951 * Load from memory to FP register
953 static void do_fp_ld(DisasContext
*s
, int destidx
, TCGv_i64 tcg_addr
, int size
)
955 /* This always zero-extends and writes to a full 128 bit wide vector */
956 TCGv_i64 tmplo
= tcg_temp_new_i64();
960 MemOp memop
= s
->be_data
+ size
;
961 tmphi
= tcg_const_i64(0);
962 tcg_gen_qemu_ld_i64(tmplo
, tcg_addr
, get_mem_index(s
), memop
);
964 bool be
= s
->be_data
== MO_BE
;
967 tmphi
= tcg_temp_new_i64();
968 tcg_hiaddr
= tcg_temp_new_i64();
970 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
971 tcg_gen_qemu_ld_i64(tmplo
, be
? tcg_hiaddr
: tcg_addr
, get_mem_index(s
),
973 tcg_gen_qemu_ld_i64(tmphi
, be
? tcg_addr
: tcg_hiaddr
, get_mem_index(s
),
975 tcg_temp_free_i64(tcg_hiaddr
);
978 tcg_gen_st_i64(tmplo
, cpu_env
, fp_reg_offset(s
, destidx
, MO_64
));
979 tcg_gen_st_i64(tmphi
, cpu_env
, fp_reg_hi_offset(s
, destidx
));
981 tcg_temp_free_i64(tmplo
);
982 tcg_temp_free_i64(tmphi
);
984 clear_vec_high(s
, true, destidx
);
988 * Vector load/store helpers.
990 * The principal difference between this and a FP load is that we don't
991 * zero extend as we are filling a partial chunk of the vector register.
992 * These functions don't support 128 bit loads/stores, which would be
993 * normal load/store operations.
995 * The _i32 versions are useful when operating on 32 bit quantities
996 * (eg for floating point single or using Neon helper functions).
999 /* Get value of an element within a vector register */
1000 static void read_vec_element(DisasContext
*s
, TCGv_i64 tcg_dest
, int srcidx
,
1001 int element
, MemOp memop
)
1003 int vect_off
= vec_reg_offset(s
, srcidx
, element
, memop
& MO_SIZE
);
1006 tcg_gen_ld8u_i64(tcg_dest
, cpu_env
, vect_off
);
1009 tcg_gen_ld16u_i64(tcg_dest
, cpu_env
, vect_off
);
1012 tcg_gen_ld32u_i64(tcg_dest
, cpu_env
, vect_off
);
1015 tcg_gen_ld8s_i64(tcg_dest
, cpu_env
, vect_off
);
1018 tcg_gen_ld16s_i64(tcg_dest
, cpu_env
, vect_off
);
1021 tcg_gen_ld32s_i64(tcg_dest
, cpu_env
, vect_off
);
1025 tcg_gen_ld_i64(tcg_dest
, cpu_env
, vect_off
);
1028 g_assert_not_reached();
1032 static void read_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_dest
, int srcidx
,
1033 int element
, MemOp memop
)
1035 int vect_off
= vec_reg_offset(s
, srcidx
, element
, memop
& MO_SIZE
);
1038 tcg_gen_ld8u_i32(tcg_dest
, cpu_env
, vect_off
);
1041 tcg_gen_ld16u_i32(tcg_dest
, cpu_env
, vect_off
);
1044 tcg_gen_ld8s_i32(tcg_dest
, cpu_env
, vect_off
);
1047 tcg_gen_ld16s_i32(tcg_dest
, cpu_env
, vect_off
);
1051 tcg_gen_ld_i32(tcg_dest
, cpu_env
, vect_off
);
1054 g_assert_not_reached();
1058 /* Set value of an element within a vector register */
1059 static void write_vec_element(DisasContext
*s
, TCGv_i64 tcg_src
, int destidx
,
1060 int element
, MemOp memop
)
1062 int vect_off
= vec_reg_offset(s
, destidx
, element
, memop
& MO_SIZE
);
1065 tcg_gen_st8_i64(tcg_src
, cpu_env
, vect_off
);
1068 tcg_gen_st16_i64(tcg_src
, cpu_env
, vect_off
);
1071 tcg_gen_st32_i64(tcg_src
, cpu_env
, vect_off
);
1074 tcg_gen_st_i64(tcg_src
, cpu_env
, vect_off
);
1077 g_assert_not_reached();
1081 static void write_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_src
,
1082 int destidx
, int element
, MemOp memop
)
1084 int vect_off
= vec_reg_offset(s
, destidx
, element
, memop
& MO_SIZE
);
1087 tcg_gen_st8_i32(tcg_src
, cpu_env
, vect_off
);
1090 tcg_gen_st16_i32(tcg_src
, cpu_env
, vect_off
);
1093 tcg_gen_st_i32(tcg_src
, cpu_env
, vect_off
);
1096 g_assert_not_reached();
1100 /* Store from vector register to memory */
1101 static void do_vec_st(DisasContext
*s
, int srcidx
, int element
,
1102 TCGv_i64 tcg_addr
, int size
, MemOp endian
)
1104 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
1106 read_vec_element(s
, tcg_tmp
, srcidx
, element
, size
);
1107 tcg_gen_qemu_st_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), endian
| size
);
1109 tcg_temp_free_i64(tcg_tmp
);
1112 /* Load from memory to vector register */
1113 static void do_vec_ld(DisasContext
*s
, int destidx
, int element
,
1114 TCGv_i64 tcg_addr
, int size
, MemOp endian
)
1116 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
1118 tcg_gen_qemu_ld_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), endian
| size
);
1119 write_vec_element(s
, tcg_tmp
, destidx
, element
, size
);
1121 tcg_temp_free_i64(tcg_tmp
);
1124 /* Check that FP/Neon access is enabled. If it is, return
1125 * true. If not, emit code to generate an appropriate exception,
1126 * and return false; the caller should not emit any code for
1127 * the instruction. Note that this check must happen after all
1128 * unallocated-encoding checks (otherwise the syndrome information
1129 * for the resulting exception will be incorrect).
1131 static inline bool fp_access_check(DisasContext
*s
)
1133 assert(!s
->fp_access_checked
);
1134 s
->fp_access_checked
= true;
1136 if (!s
->fp_excp_el
) {
1140 gen_exception_insn(s
, s
->pc_curr
, EXCP_UDEF
,
1141 syn_fp_access_trap(1, 0xe, false), s
->fp_excp_el
);
1145 /* Check that SVE access is enabled. If it is, return true.
1146 * If not, emit code to generate an appropriate exception and return false.
1148 bool sve_access_check(DisasContext
*s
)
1150 if (s
->sve_excp_el
) {
1151 gen_exception_insn(s
, s
->pc_curr
, EXCP_UDEF
, syn_sve_access_trap(),
1155 return fp_access_check(s
);
1159 * This utility function is for doing register extension with an
1160 * optional shift. You will likely want to pass a temporary for the
1161 * destination register. See DecodeRegExtend() in the ARM ARM.
1163 static void ext_and_shift_reg(TCGv_i64 tcg_out
, TCGv_i64 tcg_in
,
1164 int option
, unsigned int shift
)
1166 int extsize
= extract32(option
, 0, 2);
1167 bool is_signed
= extract32(option
, 2, 1);
1172 tcg_gen_ext8s_i64(tcg_out
, tcg_in
);
1175 tcg_gen_ext16s_i64(tcg_out
, tcg_in
);
1178 tcg_gen_ext32s_i64(tcg_out
, tcg_in
);
1181 tcg_gen_mov_i64(tcg_out
, tcg_in
);
1187 tcg_gen_ext8u_i64(tcg_out
, tcg_in
);
1190 tcg_gen_ext16u_i64(tcg_out
, tcg_in
);
1193 tcg_gen_ext32u_i64(tcg_out
, tcg_in
);
1196 tcg_gen_mov_i64(tcg_out
, tcg_in
);
1202 tcg_gen_shli_i64(tcg_out
, tcg_out
, shift
);
1206 static inline void gen_check_sp_alignment(DisasContext
*s
)
1208 /* The AArch64 architecture mandates that (if enabled via PSTATE
1209 * or SCTLR bits) there is a check that SP is 16-aligned on every
1210 * SP-relative load or store (with an exception generated if it is not).
1211 * In line with general QEMU practice regarding misaligned accesses,
1212 * we omit these checks for the sake of guest program performance.
1213 * This function is provided as a hook so we can more easily add these
1214 * checks in future (possibly as a "favour catching guest program bugs
1215 * over speed" user selectable option).
1220 * This provides a simple table based table lookup decoder. It is
1221 * intended to be used when the relevant bits for decode are too
1222 * awkwardly placed and switch/if based logic would be confusing and
1223 * deeply nested. Since it's a linear search through the table, tables
1224 * should be kept small.
1226 * It returns the first handler where insn & mask == pattern, or
1227 * NULL if there is no match.
1228 * The table is terminated by an empty mask (i.e. 0)
1230 static inline AArch64DecodeFn
*lookup_disas_fn(const AArch64DecodeTable
*table
,
1233 const AArch64DecodeTable
*tptr
= table
;
1235 while (tptr
->mask
) {
1236 if ((insn
& tptr
->mask
) == tptr
->pattern
) {
1237 return tptr
->disas_fn
;
1245 * The instruction disassembly implemented here matches
1246 * the instruction encoding classifications in chapter C4
1247 * of the ARM Architecture Reference Manual (DDI0487B_a);
1248 * classification names and decode diagrams here should generally
1249 * match up with those in the manual.
1252 /* Unconditional branch (immediate)
1254 * +----+-----------+-------------------------------------+
1255 * | op | 0 0 1 0 1 | imm26 |
1256 * +----+-----------+-------------------------------------+
1258 static void disas_uncond_b_imm(DisasContext
*s
, uint32_t insn
)
1260 uint64_t addr
= s
->pc_curr
+ sextract32(insn
, 0, 26) * 4;
1262 if (insn
& (1U << 31)) {
1263 /* BL Branch with link */
1264 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->base
.pc_next
);
1267 /* B Branch / BL Branch with link */
1269 gen_goto_tb(s
, 0, addr
);
1272 /* Compare and branch (immediate)
1273 * 31 30 25 24 23 5 4 0
1274 * +----+-------------+----+---------------------+--------+
1275 * | sf | 0 1 1 0 1 0 | op | imm19 | Rt |
1276 * +----+-------------+----+---------------------+--------+
1278 static void disas_comp_b_imm(DisasContext
*s
, uint32_t insn
)
1280 unsigned int sf
, op
, rt
;
1282 TCGLabel
*label_match
;
1285 sf
= extract32(insn
, 31, 1);
1286 op
= extract32(insn
, 24, 1); /* 0: CBZ; 1: CBNZ */
1287 rt
= extract32(insn
, 0, 5);
1288 addr
= s
->pc_curr
+ sextract32(insn
, 5, 19) * 4;
1290 tcg_cmp
= read_cpu_reg(s
, rt
, sf
);
1291 label_match
= gen_new_label();
1294 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1295 tcg_cmp
, 0, label_match
);
1297 gen_goto_tb(s
, 0, s
->base
.pc_next
);
1298 gen_set_label(label_match
);
1299 gen_goto_tb(s
, 1, addr
);
1302 /* Test and branch (immediate)
1303 * 31 30 25 24 23 19 18 5 4 0
1304 * +----+-------------+----+-------+-------------+------+
1305 * | b5 | 0 1 1 0 1 1 | op | b40 | imm14 | Rt |
1306 * +----+-------------+----+-------+-------------+------+
1308 static void disas_test_b_imm(DisasContext
*s
, uint32_t insn
)
1310 unsigned int bit_pos
, op
, rt
;
1312 TCGLabel
*label_match
;
1315 bit_pos
= (extract32(insn
, 31, 1) << 5) | extract32(insn
, 19, 5);
1316 op
= extract32(insn
, 24, 1); /* 0: TBZ; 1: TBNZ */
1317 addr
= s
->pc_curr
+ sextract32(insn
, 5, 14) * 4;
1318 rt
= extract32(insn
, 0, 5);
1320 tcg_cmp
= tcg_temp_new_i64();
1321 tcg_gen_andi_i64(tcg_cmp
, cpu_reg(s
, rt
), (1ULL << bit_pos
));
1322 label_match
= gen_new_label();
1325 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1326 tcg_cmp
, 0, label_match
);
1327 tcg_temp_free_i64(tcg_cmp
);
1328 gen_goto_tb(s
, 0, s
->base
.pc_next
);
1329 gen_set_label(label_match
);
1330 gen_goto_tb(s
, 1, addr
);
1333 /* Conditional branch (immediate)
1334 * 31 25 24 23 5 4 3 0
1335 * +---------------+----+---------------------+----+------+
1336 * | 0 1 0 1 0 1 0 | o1 | imm19 | o0 | cond |
1337 * +---------------+----+---------------------+----+------+
1339 static void disas_cond_b_imm(DisasContext
*s
, uint32_t insn
)
1344 if ((insn
& (1 << 4)) || (insn
& (1 << 24))) {
1345 unallocated_encoding(s
);
1348 addr
= s
->pc_curr
+ sextract32(insn
, 5, 19) * 4;
1349 cond
= extract32(insn
, 0, 4);
1353 /* genuinely conditional branches */
1354 TCGLabel
*label_match
= gen_new_label();
1355 arm_gen_test_cc(cond
, label_match
);
1356 gen_goto_tb(s
, 0, s
->base
.pc_next
);
1357 gen_set_label(label_match
);
1358 gen_goto_tb(s
, 1, addr
);
1360 /* 0xe and 0xf are both "always" conditions */
1361 gen_goto_tb(s
, 0, addr
);
1365 /* HINT instruction group, including various allocated HINTs */
1366 static void handle_hint(DisasContext
*s
, uint32_t insn
,
1367 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1369 unsigned int selector
= crm
<< 3 | op2
;
1372 unallocated_encoding(s
);
1377 case 0b00000: /* NOP */
1379 case 0b00011: /* WFI */
1380 s
->base
.is_jmp
= DISAS_WFI
;
1382 case 0b00001: /* YIELD */
1383 /* When running in MTTCG we don't generate jumps to the yield and
1384 * WFE helpers as it won't affect the scheduling of other vCPUs.
1385 * If we wanted to more completely model WFE/SEV so we don't busy
1386 * spin unnecessarily we would need to do something more involved.
1388 if (!(tb_cflags(s
->base
.tb
) & CF_PARALLEL
)) {
1389 s
->base
.is_jmp
= DISAS_YIELD
;
1392 case 0b00010: /* WFE */
1393 if (!(tb_cflags(s
->base
.tb
) & CF_PARALLEL
)) {
1394 s
->base
.is_jmp
= DISAS_WFE
;
1397 case 0b00100: /* SEV */
1398 case 0b00101: /* SEVL */
1399 /* we treat all as NOP at least for now */
1401 case 0b00111: /* XPACLRI */
1402 if (s
->pauth_active
) {
1403 gen_helper_xpaci(cpu_X
[30], cpu_env
, cpu_X
[30]);
1406 case 0b01000: /* PACIA1716 */
1407 if (s
->pauth_active
) {
1408 gen_helper_pacia(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1411 case 0b01010: /* PACIB1716 */
1412 if (s
->pauth_active
) {
1413 gen_helper_pacib(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1416 case 0b01100: /* AUTIA1716 */
1417 if (s
->pauth_active
) {
1418 gen_helper_autia(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1421 case 0b01110: /* AUTIB1716 */
1422 if (s
->pauth_active
) {
1423 gen_helper_autib(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1426 case 0b11000: /* PACIAZ */
1427 if (s
->pauth_active
) {
1428 gen_helper_pacia(cpu_X
[30], cpu_env
, cpu_X
[30],
1429 new_tmp_a64_zero(s
));
1432 case 0b11001: /* PACIASP */
1433 if (s
->pauth_active
) {
1434 gen_helper_pacia(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1437 case 0b11010: /* PACIBZ */
1438 if (s
->pauth_active
) {
1439 gen_helper_pacib(cpu_X
[30], cpu_env
, cpu_X
[30],
1440 new_tmp_a64_zero(s
));
1443 case 0b11011: /* PACIBSP */
1444 if (s
->pauth_active
) {
1445 gen_helper_pacib(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1448 case 0b11100: /* AUTIAZ */
1449 if (s
->pauth_active
) {
1450 gen_helper_autia(cpu_X
[30], cpu_env
, cpu_X
[30],
1451 new_tmp_a64_zero(s
));
1454 case 0b11101: /* AUTIASP */
1455 if (s
->pauth_active
) {
1456 gen_helper_autia(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1459 case 0b11110: /* AUTIBZ */
1460 if (s
->pauth_active
) {
1461 gen_helper_autib(cpu_X
[30], cpu_env
, cpu_X
[30],
1462 new_tmp_a64_zero(s
));
1465 case 0b11111: /* AUTIBSP */
1466 if (s
->pauth_active
) {
1467 gen_helper_autib(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1471 /* default specified as NOP equivalent */
1476 static void gen_clrex(DisasContext
*s
, uint32_t insn
)
1478 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
1481 /* CLREX, DSB, DMB, ISB */
1482 static void handle_sync(DisasContext
*s
, uint32_t insn
,
1483 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1488 unallocated_encoding(s
);
1499 case 1: /* MBReqTypes_Reads */
1500 bar
= TCG_BAR_SC
| TCG_MO_LD_LD
| TCG_MO_LD_ST
;
1502 case 2: /* MBReqTypes_Writes */
1503 bar
= TCG_BAR_SC
| TCG_MO_ST_ST
;
1505 default: /* MBReqTypes_All */
1506 bar
= TCG_BAR_SC
| TCG_MO_ALL
;
1512 /* We need to break the TB after this insn to execute
1513 * a self-modified code correctly and also to take
1514 * any pending interrupts immediately.
1517 gen_goto_tb(s
, 0, s
->base
.pc_next
);
1521 if (crm
!= 0 || !dc_isar_feature(aa64_sb
, s
)) {
1522 goto do_unallocated
;
1525 * TODO: There is no speculation barrier opcode for TCG;
1526 * MB and end the TB instead.
1528 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_SC
);
1529 gen_goto_tb(s
, 0, s
->base
.pc_next
);
1534 unallocated_encoding(s
);
1539 static void gen_xaflag(void)
1541 TCGv_i32 z
= tcg_temp_new_i32();
1543 tcg_gen_setcondi_i32(TCG_COND_EQ
, z
, cpu_ZF
, 0);
1552 tcg_gen_or_i32(cpu_NF
, cpu_CF
, z
);
1553 tcg_gen_subi_i32(cpu_NF
, cpu_NF
, 1);
1556 tcg_gen_and_i32(cpu_ZF
, z
, cpu_CF
);
1557 tcg_gen_xori_i32(cpu_ZF
, cpu_ZF
, 1);
1559 /* (!C & Z) << 31 -> -(Z & ~C) */
1560 tcg_gen_andc_i32(cpu_VF
, z
, cpu_CF
);
1561 tcg_gen_neg_i32(cpu_VF
, cpu_VF
);
1564 tcg_gen_or_i32(cpu_CF
, cpu_CF
, z
);
1566 tcg_temp_free_i32(z
);
1569 static void gen_axflag(void)
1571 tcg_gen_sari_i32(cpu_VF
, cpu_VF
, 31); /* V ? -1 : 0 */
1572 tcg_gen_andc_i32(cpu_CF
, cpu_CF
, cpu_VF
); /* C & !V */
1574 /* !(Z | V) -> !(!ZF | V) -> ZF & !V -> ZF & ~VF */
1575 tcg_gen_andc_i32(cpu_ZF
, cpu_ZF
, cpu_VF
);
1577 tcg_gen_movi_i32(cpu_NF
, 0);
1578 tcg_gen_movi_i32(cpu_VF
, 0);
1581 /* MSR (immediate) - move immediate to processor state field */
1582 static void handle_msr_i(DisasContext
*s
, uint32_t insn
,
1583 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1586 int op
= op1
<< 3 | op2
;
1588 /* End the TB by default, chaining is ok. */
1589 s
->base
.is_jmp
= DISAS_TOO_MANY
;
1592 case 0x00: /* CFINV */
1593 if (crm
!= 0 || !dc_isar_feature(aa64_condm_4
, s
)) {
1594 goto do_unallocated
;
1596 tcg_gen_xori_i32(cpu_CF
, cpu_CF
, 1);
1597 s
->base
.is_jmp
= DISAS_NEXT
;
1600 case 0x01: /* XAFlag */
1601 if (crm
!= 0 || !dc_isar_feature(aa64_condm_5
, s
)) {
1602 goto do_unallocated
;
1605 s
->base
.is_jmp
= DISAS_NEXT
;
1608 case 0x02: /* AXFlag */
1609 if (crm
!= 0 || !dc_isar_feature(aa64_condm_5
, s
)) {
1610 goto do_unallocated
;
1613 s
->base
.is_jmp
= DISAS_NEXT
;
1616 case 0x03: /* UAO */
1617 if (!dc_isar_feature(aa64_uao
, s
) || s
->current_el
== 0) {
1618 goto do_unallocated
;
1621 set_pstate_bits(PSTATE_UAO
);
1623 clear_pstate_bits(PSTATE_UAO
);
1625 t1
= tcg_const_i32(s
->current_el
);
1626 gen_helper_rebuild_hflags_a64(cpu_env
, t1
);
1627 tcg_temp_free_i32(t1
);
1630 case 0x04: /* PAN */
1631 if (!dc_isar_feature(aa64_pan
, s
) || s
->current_el
== 0) {
1632 goto do_unallocated
;
1635 set_pstate_bits(PSTATE_PAN
);
1637 clear_pstate_bits(PSTATE_PAN
);
1639 t1
= tcg_const_i32(s
->current_el
);
1640 gen_helper_rebuild_hflags_a64(cpu_env
, t1
);
1641 tcg_temp_free_i32(t1
);
1644 case 0x05: /* SPSel */
1645 if (s
->current_el
== 0) {
1646 goto do_unallocated
;
1648 t1
= tcg_const_i32(crm
& PSTATE_SP
);
1649 gen_helper_msr_i_spsel(cpu_env
, t1
);
1650 tcg_temp_free_i32(t1
);
1653 case 0x1e: /* DAIFSet */
1654 t1
= tcg_const_i32(crm
);
1655 gen_helper_msr_i_daifset(cpu_env
, t1
);
1656 tcg_temp_free_i32(t1
);
1659 case 0x1f: /* DAIFClear */
1660 t1
= tcg_const_i32(crm
);
1661 gen_helper_msr_i_daifclear(cpu_env
, t1
);
1662 tcg_temp_free_i32(t1
);
1663 /* For DAIFClear, exit the cpu loop to re-evaluate pending IRQs. */
1664 s
->base
.is_jmp
= DISAS_UPDATE
;
1669 unallocated_encoding(s
);
1674 static void gen_get_nzcv(TCGv_i64 tcg_rt
)
1676 TCGv_i32 tmp
= tcg_temp_new_i32();
1677 TCGv_i32 nzcv
= tcg_temp_new_i32();
1679 /* build bit 31, N */
1680 tcg_gen_andi_i32(nzcv
, cpu_NF
, (1U << 31));
1681 /* build bit 30, Z */
1682 tcg_gen_setcondi_i32(TCG_COND_EQ
, tmp
, cpu_ZF
, 0);
1683 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 30, 1);
1684 /* build bit 29, C */
1685 tcg_gen_deposit_i32(nzcv
, nzcv
, cpu_CF
, 29, 1);
1686 /* build bit 28, V */
1687 tcg_gen_shri_i32(tmp
, cpu_VF
, 31);
1688 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 28, 1);
1689 /* generate result */
1690 tcg_gen_extu_i32_i64(tcg_rt
, nzcv
);
1692 tcg_temp_free_i32(nzcv
);
1693 tcg_temp_free_i32(tmp
);
1696 static void gen_set_nzcv(TCGv_i64 tcg_rt
)
1698 TCGv_i32 nzcv
= tcg_temp_new_i32();
1700 /* take NZCV from R[t] */
1701 tcg_gen_extrl_i64_i32(nzcv
, tcg_rt
);
1704 tcg_gen_andi_i32(cpu_NF
, nzcv
, (1U << 31));
1706 tcg_gen_andi_i32(cpu_ZF
, nzcv
, (1 << 30));
1707 tcg_gen_setcondi_i32(TCG_COND_EQ
, cpu_ZF
, cpu_ZF
, 0);
1709 tcg_gen_andi_i32(cpu_CF
, nzcv
, (1 << 29));
1710 tcg_gen_shri_i32(cpu_CF
, cpu_CF
, 29);
1712 tcg_gen_andi_i32(cpu_VF
, nzcv
, (1 << 28));
1713 tcg_gen_shli_i32(cpu_VF
, cpu_VF
, 3);
1714 tcg_temp_free_i32(nzcv
);
1717 /* MRS - move from system register
1718 * MSR (register) - move to system register
1721 * These are all essentially the same insn in 'read' and 'write'
1722 * versions, with varying op0 fields.
1724 static void handle_sys(DisasContext
*s
, uint32_t insn
, bool isread
,
1725 unsigned int op0
, unsigned int op1
, unsigned int op2
,
1726 unsigned int crn
, unsigned int crm
, unsigned int rt
)
1728 const ARMCPRegInfo
*ri
;
1731 ri
= get_arm_cp_reginfo(s
->cp_regs
,
1732 ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP
,
1733 crn
, crm
, op0
, op1
, op2
));
1736 /* Unknown register; this might be a guest error or a QEMU
1737 * unimplemented feature.
1739 qemu_log_mask(LOG_UNIMP
, "%s access to unsupported AArch64 "
1740 "system register op0:%d op1:%d crn:%d crm:%d op2:%d\n",
1741 isread
? "read" : "write", op0
, op1
, crn
, crm
, op2
);
1742 unallocated_encoding(s
);
1746 /* Check access permissions */
1747 if (!cp_access_ok(s
->current_el
, ri
, isread
)) {
1748 unallocated_encoding(s
);
1753 /* Emit code to perform further access permissions checks at
1754 * runtime; this may result in an exception.
1757 TCGv_i32 tcg_syn
, tcg_isread
;
1760 gen_a64_set_pc_im(s
->pc_curr
);
1761 tmpptr
= tcg_const_ptr(ri
);
1762 syndrome
= syn_aa64_sysregtrap(op0
, op1
, op2
, crn
, crm
, rt
, isread
);
1763 tcg_syn
= tcg_const_i32(syndrome
);
1764 tcg_isread
= tcg_const_i32(isread
);
1765 gen_helper_access_check_cp_reg(cpu_env
, tmpptr
, tcg_syn
, tcg_isread
);
1766 tcg_temp_free_ptr(tmpptr
);
1767 tcg_temp_free_i32(tcg_syn
);
1768 tcg_temp_free_i32(tcg_isread
);
1769 } else if (ri
->type
& ARM_CP_RAISES_EXC
) {
1771 * The readfn or writefn might raise an exception;
1772 * synchronize the CPU state in case it does.
1774 gen_a64_set_pc_im(s
->pc_curr
);
1777 /* Handle special cases first */
1778 switch (ri
->type
& ~(ARM_CP_FLAG_MASK
& ~ARM_CP_SPECIAL
)) {
1782 tcg_rt
= cpu_reg(s
, rt
);
1784 gen_get_nzcv(tcg_rt
);
1786 gen_set_nzcv(tcg_rt
);
1789 case ARM_CP_CURRENTEL
:
1790 /* Reads as current EL value from pstate, which is
1791 * guaranteed to be constant by the tb flags.
1793 tcg_rt
= cpu_reg(s
, rt
);
1794 tcg_gen_movi_i64(tcg_rt
, s
->current_el
<< 2);
1797 /* Writes clear the aligned block of memory which rt points into. */
1798 tcg_rt
= clean_data_tbi(s
, cpu_reg(s
, rt
));
1799 gen_helper_dc_zva(cpu_env
, tcg_rt
);
1804 if ((ri
->type
& ARM_CP_FPU
) && !fp_access_check(s
)) {
1806 } else if ((ri
->type
& ARM_CP_SVE
) && !sve_access_check(s
)) {
1810 if ((tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) && (ri
->type
& ARM_CP_IO
)) {
1814 tcg_rt
= cpu_reg(s
, rt
);
1817 if (ri
->type
& ARM_CP_CONST
) {
1818 tcg_gen_movi_i64(tcg_rt
, ri
->resetvalue
);
1819 } else if (ri
->readfn
) {
1821 tmpptr
= tcg_const_ptr(ri
);
1822 gen_helper_get_cp_reg64(tcg_rt
, cpu_env
, tmpptr
);
1823 tcg_temp_free_ptr(tmpptr
);
1825 tcg_gen_ld_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
1828 if (ri
->type
& ARM_CP_CONST
) {
1829 /* If not forbidden by access permissions, treat as WI */
1831 } else if (ri
->writefn
) {
1833 tmpptr
= tcg_const_ptr(ri
);
1834 gen_helper_set_cp_reg64(cpu_env
, tmpptr
, tcg_rt
);
1835 tcg_temp_free_ptr(tmpptr
);
1837 tcg_gen_st_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
1841 if ((tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) && (ri
->type
& ARM_CP_IO
)) {
1842 /* I/O operations must end the TB here (whether read or write) */
1843 s
->base
.is_jmp
= DISAS_UPDATE
;
1845 if (!isread
&& !(ri
->type
& ARM_CP_SUPPRESS_TB_END
)) {
1847 * A write to any coprocessor regiser that ends a TB
1848 * must rebuild the hflags for the next TB.
1850 TCGv_i32 tcg_el
= tcg_const_i32(s
->current_el
);
1851 gen_helper_rebuild_hflags_a64(cpu_env
, tcg_el
);
1852 tcg_temp_free_i32(tcg_el
);
1854 * We default to ending the TB on a coprocessor register write,
1855 * but allow this to be suppressed by the register definition
1856 * (usually only necessary to work around guest bugs).
1858 s
->base
.is_jmp
= DISAS_UPDATE
;
1863 * 31 22 21 20 19 18 16 15 12 11 8 7 5 4 0
1864 * +---------------------+---+-----+-----+-------+-------+-----+------+
1865 * | 1 1 0 1 0 1 0 1 0 0 | L | op0 | op1 | CRn | CRm | op2 | Rt |
1866 * +---------------------+---+-----+-----+-------+-------+-----+------+
1868 static void disas_system(DisasContext
*s
, uint32_t insn
)
1870 unsigned int l
, op0
, op1
, crn
, crm
, op2
, rt
;
1871 l
= extract32(insn
, 21, 1);
1872 op0
= extract32(insn
, 19, 2);
1873 op1
= extract32(insn
, 16, 3);
1874 crn
= extract32(insn
, 12, 4);
1875 crm
= extract32(insn
, 8, 4);
1876 op2
= extract32(insn
, 5, 3);
1877 rt
= extract32(insn
, 0, 5);
1880 if (l
|| rt
!= 31) {
1881 unallocated_encoding(s
);
1885 case 2: /* HINT (including allocated hints like NOP, YIELD, etc) */
1886 handle_hint(s
, insn
, op1
, op2
, crm
);
1888 case 3: /* CLREX, DSB, DMB, ISB */
1889 handle_sync(s
, insn
, op1
, op2
, crm
);
1891 case 4: /* MSR (immediate) */
1892 handle_msr_i(s
, insn
, op1
, op2
, crm
);
1895 unallocated_encoding(s
);
1900 handle_sys(s
, insn
, l
, op0
, op1
, op2
, crn
, crm
, rt
);
1903 /* Exception generation
1905 * 31 24 23 21 20 5 4 2 1 0
1906 * +-----------------+-----+------------------------+-----+----+
1907 * | 1 1 0 1 0 1 0 0 | opc | imm16 | op2 | LL |
1908 * +-----------------------+------------------------+----------+
1910 static void disas_exc(DisasContext
*s
, uint32_t insn
)
1912 int opc
= extract32(insn
, 21, 3);
1913 int op2_ll
= extract32(insn
, 0, 5);
1914 int imm16
= extract32(insn
, 5, 16);
1919 /* For SVC, HVC and SMC we advance the single-step state
1920 * machine before taking the exception. This is architecturally
1921 * mandated, to ensure that single-stepping a system call
1922 * instruction works properly.
1927 gen_exception_insn(s
, s
->base
.pc_next
, EXCP_SWI
,
1928 syn_aa64_svc(imm16
), default_exception_el(s
));
1931 if (s
->current_el
== 0) {
1932 unallocated_encoding(s
);
1935 /* The pre HVC helper handles cases when HVC gets trapped
1936 * as an undefined insn by runtime configuration.
1938 gen_a64_set_pc_im(s
->pc_curr
);
1939 gen_helper_pre_hvc(cpu_env
);
1941 gen_exception_insn(s
, s
->base
.pc_next
, EXCP_HVC
,
1942 syn_aa64_hvc(imm16
), 2);
1945 if (s
->current_el
== 0) {
1946 unallocated_encoding(s
);
1949 gen_a64_set_pc_im(s
->pc_curr
);
1950 tmp
= tcg_const_i32(syn_aa64_smc(imm16
));
1951 gen_helper_pre_smc(cpu_env
, tmp
);
1952 tcg_temp_free_i32(tmp
);
1954 gen_exception_insn(s
, s
->base
.pc_next
, EXCP_SMC
,
1955 syn_aa64_smc(imm16
), 3);
1958 unallocated_encoding(s
);
1964 unallocated_encoding(s
);
1968 gen_exception_bkpt_insn(s
, syn_aa64_bkpt(imm16
));
1972 unallocated_encoding(s
);
1975 /* HLT. This has two purposes.
1976 * Architecturally, it is an external halting debug instruction.
1977 * Since QEMU doesn't implement external debug, we treat this as
1978 * it is required for halting debug disabled: it will UNDEF.
1979 * Secondly, "HLT 0xf000" is the A64 semihosting syscall instruction.
1981 if (semihosting_enabled() && imm16
== 0xf000) {
1982 #ifndef CONFIG_USER_ONLY
1983 /* In system mode, don't allow userspace access to semihosting,
1984 * to provide some semblance of security (and for consistency
1985 * with our 32-bit semihosting).
1987 if (s
->current_el
== 0) {
1988 unsupported_encoding(s
, insn
);
1992 gen_exception_internal_insn(s
, s
->pc_curr
, EXCP_SEMIHOST
);
1994 unsupported_encoding(s
, insn
);
1998 if (op2_ll
< 1 || op2_ll
> 3) {
1999 unallocated_encoding(s
);
2002 /* DCPS1, DCPS2, DCPS3 */
2003 unsupported_encoding(s
, insn
);
2006 unallocated_encoding(s
);
2011 /* Unconditional branch (register)
2012 * 31 25 24 21 20 16 15 10 9 5 4 0
2013 * +---------------+-------+-------+-------+------+-------+
2014 * | 1 1 0 1 0 1 1 | opc | op2 | op3 | Rn | op4 |
2015 * +---------------+-------+-------+-------+------+-------+
2017 static void disas_uncond_b_reg(DisasContext
*s
, uint32_t insn
)
2019 unsigned int opc
, op2
, op3
, rn
, op4
;
2020 unsigned btype_mod
= 2; /* 0: BR, 1: BLR, 2: other */
2024 opc
= extract32(insn
, 21, 4);
2025 op2
= extract32(insn
, 16, 5);
2026 op3
= extract32(insn
, 10, 6);
2027 rn
= extract32(insn
, 5, 5);
2028 op4
= extract32(insn
, 0, 5);
2031 goto do_unallocated
;
2043 goto do_unallocated
;
2045 dst
= cpu_reg(s
, rn
);
2050 if (!dc_isar_feature(aa64_pauth
, s
)) {
2051 goto do_unallocated
;
2055 if (rn
!= 0x1f || op4
!= 0x1f) {
2056 goto do_unallocated
;
2059 modifier
= cpu_X
[31];
2061 /* BRAAZ, BRABZ, BLRAAZ, BLRABZ */
2063 goto do_unallocated
;
2065 modifier
= new_tmp_a64_zero(s
);
2067 if (s
->pauth_active
) {
2068 dst
= new_tmp_a64(s
);
2070 gen_helper_autia(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2072 gen_helper_autib(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2075 dst
= cpu_reg(s
, rn
);
2080 goto do_unallocated
;
2082 gen_a64_set_pc(s
, dst
);
2083 /* BLR also needs to load return address */
2085 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->base
.pc_next
);
2091 if (!dc_isar_feature(aa64_pauth
, s
)) {
2092 goto do_unallocated
;
2094 if ((op3
& ~1) != 2) {
2095 goto do_unallocated
;
2097 btype_mod
= opc
& 1;
2098 if (s
->pauth_active
) {
2099 dst
= new_tmp_a64(s
);
2100 modifier
= cpu_reg_sp(s
, op4
);
2102 gen_helper_autia(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2104 gen_helper_autib(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2107 dst
= cpu_reg(s
, rn
);
2109 gen_a64_set_pc(s
, dst
);
2110 /* BLRAA also needs to load return address */
2112 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->base
.pc_next
);
2117 if (s
->current_el
== 0) {
2118 goto do_unallocated
;
2123 goto do_unallocated
;
2125 dst
= tcg_temp_new_i64();
2126 tcg_gen_ld_i64(dst
, cpu_env
,
2127 offsetof(CPUARMState
, elr_el
[s
->current_el
]));
2130 case 2: /* ERETAA */
2131 case 3: /* ERETAB */
2132 if (!dc_isar_feature(aa64_pauth
, s
)) {
2133 goto do_unallocated
;
2135 if (rn
!= 0x1f || op4
!= 0x1f) {
2136 goto do_unallocated
;
2138 dst
= tcg_temp_new_i64();
2139 tcg_gen_ld_i64(dst
, cpu_env
,
2140 offsetof(CPUARMState
, elr_el
[s
->current_el
]));
2141 if (s
->pauth_active
) {
2142 modifier
= cpu_X
[31];
2144 gen_helper_autia(dst
, cpu_env
, dst
, modifier
);
2146 gen_helper_autib(dst
, cpu_env
, dst
, modifier
);
2152 goto do_unallocated
;
2154 if (tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) {
2158 gen_helper_exception_return(cpu_env
, dst
);
2159 tcg_temp_free_i64(dst
);
2160 /* Must exit loop to check un-masked IRQs */
2161 s
->base
.is_jmp
= DISAS_EXIT
;
2165 if (op3
!= 0 || op4
!= 0 || rn
!= 0x1f) {
2166 goto do_unallocated
;
2168 unsupported_encoding(s
, insn
);
2174 unallocated_encoding(s
);
2178 switch (btype_mod
) {
2180 if (dc_isar_feature(aa64_bti
, s
)) {
2181 /* BR to {x16,x17} or !guard -> 1, else 3. */
2182 set_btype(s
, rn
== 16 || rn
== 17 || !s
->guarded_page
? 1 : 3);
2187 if (dc_isar_feature(aa64_bti
, s
)) {
2188 /* BLR sets BTYPE to 2, regardless of source guarded page. */
2193 default: /* RET or none of the above. */
2194 /* BTYPE will be set to 0 by normal end-of-insn processing. */
2198 s
->base
.is_jmp
= DISAS_JUMP
;
2201 /* Branches, exception generating and system instructions */
2202 static void disas_b_exc_sys(DisasContext
*s
, uint32_t insn
)
2204 switch (extract32(insn
, 25, 7)) {
2205 case 0x0a: case 0x0b:
2206 case 0x4a: case 0x4b: /* Unconditional branch (immediate) */
2207 disas_uncond_b_imm(s
, insn
);
2209 case 0x1a: case 0x5a: /* Compare & branch (immediate) */
2210 disas_comp_b_imm(s
, insn
);
2212 case 0x1b: case 0x5b: /* Test & branch (immediate) */
2213 disas_test_b_imm(s
, insn
);
2215 case 0x2a: /* Conditional branch (immediate) */
2216 disas_cond_b_imm(s
, insn
);
2218 case 0x6a: /* Exception generation / System */
2219 if (insn
& (1 << 24)) {
2220 if (extract32(insn
, 22, 2) == 0) {
2221 disas_system(s
, insn
);
2223 unallocated_encoding(s
);
2229 case 0x6b: /* Unconditional branch (register) */
2230 disas_uncond_b_reg(s
, insn
);
2233 unallocated_encoding(s
);
2239 * Load/Store exclusive instructions are implemented by remembering
2240 * the value/address loaded, and seeing if these are the same
2241 * when the store is performed. This is not actually the architecturally
2242 * mandated semantics, but it works for typical guest code sequences
2243 * and avoids having to monitor regular stores.
2245 * The store exclusive uses the atomic cmpxchg primitives to avoid
2246 * races in multi-threaded linux-user and when MTTCG softmmu is
2249 static void gen_load_exclusive(DisasContext
*s
, int rt
, int rt2
,
2250 TCGv_i64 addr
, int size
, bool is_pair
)
2252 int idx
= get_mem_index(s
);
2253 MemOp memop
= s
->be_data
;
2255 g_assert(size
<= 3);
2257 g_assert(size
>= 2);
2259 /* The pair must be single-copy atomic for the doubleword. */
2260 memop
|= MO_64
| MO_ALIGN
;
2261 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
, memop
);
2262 if (s
->be_data
== MO_LE
) {
2263 tcg_gen_extract_i64(cpu_reg(s
, rt
), cpu_exclusive_val
, 0, 32);
2264 tcg_gen_extract_i64(cpu_reg(s
, rt2
), cpu_exclusive_val
, 32, 32);
2266 tcg_gen_extract_i64(cpu_reg(s
, rt
), cpu_exclusive_val
, 32, 32);
2267 tcg_gen_extract_i64(cpu_reg(s
, rt2
), cpu_exclusive_val
, 0, 32);
2270 /* The pair must be single-copy atomic for *each* doubleword, not
2271 the entire quadword, however it must be quadword aligned. */
2273 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
,
2274 memop
| MO_ALIGN_16
);
2276 TCGv_i64 addr2
= tcg_temp_new_i64();
2277 tcg_gen_addi_i64(addr2
, addr
, 8);
2278 tcg_gen_qemu_ld_i64(cpu_exclusive_high
, addr2
, idx
, memop
);
2279 tcg_temp_free_i64(addr2
);
2281 tcg_gen_mov_i64(cpu_reg(s
, rt
), cpu_exclusive_val
);
2282 tcg_gen_mov_i64(cpu_reg(s
, rt2
), cpu_exclusive_high
);
2285 memop
|= size
| MO_ALIGN
;
2286 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
, memop
);
2287 tcg_gen_mov_i64(cpu_reg(s
, rt
), cpu_exclusive_val
);
2289 tcg_gen_mov_i64(cpu_exclusive_addr
, addr
);
2292 static void gen_store_exclusive(DisasContext
*s
, int rd
, int rt
, int rt2
,
2293 TCGv_i64 addr
, int size
, int is_pair
)
2295 /* if (env->exclusive_addr == addr && env->exclusive_val == [addr]
2296 * && (!is_pair || env->exclusive_high == [addr + datasize])) {
2299 * [addr + datasize] = {Rt2};
2305 * env->exclusive_addr = -1;
2307 TCGLabel
*fail_label
= gen_new_label();
2308 TCGLabel
*done_label
= gen_new_label();
2311 tcg_gen_brcond_i64(TCG_COND_NE
, addr
, cpu_exclusive_addr
, fail_label
);
2313 tmp
= tcg_temp_new_i64();
2316 if (s
->be_data
== MO_LE
) {
2317 tcg_gen_concat32_i64(tmp
, cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
2319 tcg_gen_concat32_i64(tmp
, cpu_reg(s
, rt2
), cpu_reg(s
, rt
));
2321 tcg_gen_atomic_cmpxchg_i64(tmp
, cpu_exclusive_addr
,
2322 cpu_exclusive_val
, tmp
,
2324 MO_64
| MO_ALIGN
| s
->be_data
);
2325 tcg_gen_setcond_i64(TCG_COND_NE
, tmp
, tmp
, cpu_exclusive_val
);
2326 } else if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
2327 if (!HAVE_CMPXCHG128
) {
2328 gen_helper_exit_atomic(cpu_env
);
2329 s
->base
.is_jmp
= DISAS_NORETURN
;
2330 } else if (s
->be_data
== MO_LE
) {
2331 gen_helper_paired_cmpxchg64_le_parallel(tmp
, cpu_env
,
2336 gen_helper_paired_cmpxchg64_be_parallel(tmp
, cpu_env
,
2341 } else if (s
->be_data
== MO_LE
) {
2342 gen_helper_paired_cmpxchg64_le(tmp
, cpu_env
, cpu_exclusive_addr
,
2343 cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
2345 gen_helper_paired_cmpxchg64_be(tmp
, cpu_env
, cpu_exclusive_addr
,
2346 cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
2349 tcg_gen_atomic_cmpxchg_i64(tmp
, cpu_exclusive_addr
, cpu_exclusive_val
,
2350 cpu_reg(s
, rt
), get_mem_index(s
),
2351 size
| MO_ALIGN
| s
->be_data
);
2352 tcg_gen_setcond_i64(TCG_COND_NE
, tmp
, tmp
, cpu_exclusive_val
);
2354 tcg_gen_mov_i64(cpu_reg(s
, rd
), tmp
);
2355 tcg_temp_free_i64(tmp
);
2356 tcg_gen_br(done_label
);
2358 gen_set_label(fail_label
);
2359 tcg_gen_movi_i64(cpu_reg(s
, rd
), 1);
2360 gen_set_label(done_label
);
2361 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
2364 static void gen_compare_and_swap(DisasContext
*s
, int rs
, int rt
,
2367 TCGv_i64 tcg_rs
= cpu_reg(s
, rs
);
2368 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2369 int memidx
= get_mem_index(s
);
2370 TCGv_i64 clean_addr
;
2373 gen_check_sp_alignment(s
);
2375 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2376 tcg_gen_atomic_cmpxchg_i64(tcg_rs
, clean_addr
, tcg_rs
, tcg_rt
, memidx
,
2377 size
| MO_ALIGN
| s
->be_data
);
2380 static void gen_compare_and_swap_pair(DisasContext
*s
, int rs
, int rt
,
2383 TCGv_i64 s1
= cpu_reg(s
, rs
);
2384 TCGv_i64 s2
= cpu_reg(s
, rs
+ 1);
2385 TCGv_i64 t1
= cpu_reg(s
, rt
);
2386 TCGv_i64 t2
= cpu_reg(s
, rt
+ 1);
2387 TCGv_i64 clean_addr
;
2388 int memidx
= get_mem_index(s
);
2391 gen_check_sp_alignment(s
);
2393 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2396 TCGv_i64 cmp
= tcg_temp_new_i64();
2397 TCGv_i64 val
= tcg_temp_new_i64();
2399 if (s
->be_data
== MO_LE
) {
2400 tcg_gen_concat32_i64(val
, t1
, t2
);
2401 tcg_gen_concat32_i64(cmp
, s1
, s2
);
2403 tcg_gen_concat32_i64(val
, t2
, t1
);
2404 tcg_gen_concat32_i64(cmp
, s2
, s1
);
2407 tcg_gen_atomic_cmpxchg_i64(cmp
, clean_addr
, cmp
, val
, memidx
,
2408 MO_64
| MO_ALIGN
| s
->be_data
);
2409 tcg_temp_free_i64(val
);
2411 if (s
->be_data
== MO_LE
) {
2412 tcg_gen_extr32_i64(s1
, s2
, cmp
);
2414 tcg_gen_extr32_i64(s2
, s1
, cmp
);
2416 tcg_temp_free_i64(cmp
);
2417 } else if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
2418 if (HAVE_CMPXCHG128
) {
2419 TCGv_i32 tcg_rs
= tcg_const_i32(rs
);
2420 if (s
->be_data
== MO_LE
) {
2421 gen_helper_casp_le_parallel(cpu_env
, tcg_rs
,
2422 clean_addr
, t1
, t2
);
2424 gen_helper_casp_be_parallel(cpu_env
, tcg_rs
,
2425 clean_addr
, t1
, t2
);
2427 tcg_temp_free_i32(tcg_rs
);
2429 gen_helper_exit_atomic(cpu_env
);
2430 s
->base
.is_jmp
= DISAS_NORETURN
;
2433 TCGv_i64 d1
= tcg_temp_new_i64();
2434 TCGv_i64 d2
= tcg_temp_new_i64();
2435 TCGv_i64 a2
= tcg_temp_new_i64();
2436 TCGv_i64 c1
= tcg_temp_new_i64();
2437 TCGv_i64 c2
= tcg_temp_new_i64();
2438 TCGv_i64 zero
= tcg_const_i64(0);
2440 /* Load the two words, in memory order. */
2441 tcg_gen_qemu_ld_i64(d1
, clean_addr
, memidx
,
2442 MO_64
| MO_ALIGN_16
| s
->be_data
);
2443 tcg_gen_addi_i64(a2
, clean_addr
, 8);
2444 tcg_gen_qemu_ld_i64(d2
, a2
, memidx
, MO_64
| s
->be_data
);
2446 /* Compare the two words, also in memory order. */
2447 tcg_gen_setcond_i64(TCG_COND_EQ
, c1
, d1
, s1
);
2448 tcg_gen_setcond_i64(TCG_COND_EQ
, c2
, d2
, s2
);
2449 tcg_gen_and_i64(c2
, c2
, c1
);
2451 /* If compare equal, write back new data, else write back old data. */
2452 tcg_gen_movcond_i64(TCG_COND_NE
, c1
, c2
, zero
, t1
, d1
);
2453 tcg_gen_movcond_i64(TCG_COND_NE
, c2
, c2
, zero
, t2
, d2
);
2454 tcg_gen_qemu_st_i64(c1
, clean_addr
, memidx
, MO_64
| s
->be_data
);
2455 tcg_gen_qemu_st_i64(c2
, a2
, memidx
, MO_64
| s
->be_data
);
2456 tcg_temp_free_i64(a2
);
2457 tcg_temp_free_i64(c1
);
2458 tcg_temp_free_i64(c2
);
2459 tcg_temp_free_i64(zero
);
2461 /* Write back the data from memory to Rs. */
2462 tcg_gen_mov_i64(s1
, d1
);
2463 tcg_gen_mov_i64(s2
, d2
);
2464 tcg_temp_free_i64(d1
);
2465 tcg_temp_free_i64(d2
);
2469 /* Update the Sixty-Four bit (SF) registersize. This logic is derived
2470 * from the ARMv8 specs for LDR (Shared decode for all encodings).
2472 static bool disas_ldst_compute_iss_sf(int size
, bool is_signed
, int opc
)
2474 int opc0
= extract32(opc
, 0, 1);
2478 regsize
= opc0
? 32 : 64;
2480 regsize
= size
== 3 ? 64 : 32;
2482 return regsize
== 64;
2485 /* Load/store exclusive
2487 * 31 30 29 24 23 22 21 20 16 15 14 10 9 5 4 0
2488 * +-----+-------------+----+---+----+------+----+-------+------+------+
2489 * | sz | 0 0 1 0 0 0 | o2 | L | o1 | Rs | o0 | Rt2 | Rn | Rt |
2490 * +-----+-------------+----+---+----+------+----+-------+------+------+
2492 * sz: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64 bit
2493 * L: 0 -> store, 1 -> load
2494 * o2: 0 -> exclusive, 1 -> not
2495 * o1: 0 -> single register, 1 -> register pair
2496 * o0: 1 -> load-acquire/store-release, 0 -> not
2498 static void disas_ldst_excl(DisasContext
*s
, uint32_t insn
)
2500 int rt
= extract32(insn
, 0, 5);
2501 int rn
= extract32(insn
, 5, 5);
2502 int rt2
= extract32(insn
, 10, 5);
2503 int rs
= extract32(insn
, 16, 5);
2504 int is_lasr
= extract32(insn
, 15, 1);
2505 int o2_L_o1_o0
= extract32(insn
, 21, 3) * 2 | is_lasr
;
2506 int size
= extract32(insn
, 30, 2);
2507 TCGv_i64 clean_addr
;
2509 switch (o2_L_o1_o0
) {
2510 case 0x0: /* STXR */
2511 case 0x1: /* STLXR */
2513 gen_check_sp_alignment(s
);
2516 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2518 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2519 gen_store_exclusive(s
, rs
, rt
, rt2
, clean_addr
, size
, false);
2522 case 0x4: /* LDXR */
2523 case 0x5: /* LDAXR */
2525 gen_check_sp_alignment(s
);
2527 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2529 gen_load_exclusive(s
, rt
, rt2
, clean_addr
, size
, false);
2531 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2535 case 0x8: /* STLLR */
2536 if (!dc_isar_feature(aa64_lor
, s
)) {
2539 /* StoreLORelease is the same as Store-Release for QEMU. */
2541 case 0x9: /* STLR */
2542 /* Generate ISS for non-exclusive accesses including LASR. */
2544 gen_check_sp_alignment(s
);
2546 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2547 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2548 do_gpr_st(s
, cpu_reg(s
, rt
), clean_addr
, size
, true, rt
,
2549 disas_ldst_compute_iss_sf(size
, false, 0), is_lasr
);
2552 case 0xc: /* LDLAR */
2553 if (!dc_isar_feature(aa64_lor
, s
)) {
2556 /* LoadLOAcquire is the same as Load-Acquire for QEMU. */
2558 case 0xd: /* LDAR */
2559 /* Generate ISS for non-exclusive accesses including LASR. */
2561 gen_check_sp_alignment(s
);
2563 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2564 do_gpr_ld(s
, cpu_reg(s
, rt
), clean_addr
, size
, false, false, true, rt
,
2565 disas_ldst_compute_iss_sf(size
, false, 0), is_lasr
);
2566 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2569 case 0x2: case 0x3: /* CASP / STXP */
2570 if (size
& 2) { /* STXP / STLXP */
2572 gen_check_sp_alignment(s
);
2575 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2577 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2578 gen_store_exclusive(s
, rs
, rt
, rt2
, clean_addr
, size
, true);
2582 && ((rt
| rs
) & 1) == 0
2583 && dc_isar_feature(aa64_atomics
, s
)) {
2585 gen_compare_and_swap_pair(s
, rs
, rt
, rn
, size
| 2);
2590 case 0x6: case 0x7: /* CASPA / LDXP */
2591 if (size
& 2) { /* LDXP / LDAXP */
2593 gen_check_sp_alignment(s
);
2595 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2597 gen_load_exclusive(s
, rt
, rt2
, clean_addr
, size
, true);
2599 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2604 && ((rt
| rs
) & 1) == 0
2605 && dc_isar_feature(aa64_atomics
, s
)) {
2606 /* CASPA / CASPAL */
2607 gen_compare_and_swap_pair(s
, rs
, rt
, rn
, size
| 2);
2613 case 0xb: /* CASL */
2614 case 0xe: /* CASA */
2615 case 0xf: /* CASAL */
2616 if (rt2
== 31 && dc_isar_feature(aa64_atomics
, s
)) {
2617 gen_compare_and_swap(s
, rs
, rt
, rn
, size
);
2622 unallocated_encoding(s
);
2626 * Load register (literal)
2628 * 31 30 29 27 26 25 24 23 5 4 0
2629 * +-----+-------+---+-----+-------------------+-------+
2630 * | opc | 0 1 1 | V | 0 0 | imm19 | Rt |
2631 * +-----+-------+---+-----+-------------------+-------+
2633 * V: 1 -> vector (simd/fp)
2634 * opc (non-vector): 00 -> 32 bit, 01 -> 64 bit,
2635 * 10-> 32 bit signed, 11 -> prefetch
2636 * opc (vector): 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit (11 unallocated)
2638 static void disas_ld_lit(DisasContext
*s
, uint32_t insn
)
2640 int rt
= extract32(insn
, 0, 5);
2641 int64_t imm
= sextract32(insn
, 5, 19) << 2;
2642 bool is_vector
= extract32(insn
, 26, 1);
2643 int opc
= extract32(insn
, 30, 2);
2644 bool is_signed
= false;
2646 TCGv_i64 tcg_rt
, clean_addr
;
2650 unallocated_encoding(s
);
2654 if (!fp_access_check(s
)) {
2659 /* PRFM (literal) : prefetch */
2662 size
= 2 + extract32(opc
, 0, 1);
2663 is_signed
= extract32(opc
, 1, 1);
2666 tcg_rt
= cpu_reg(s
, rt
);
2668 clean_addr
= tcg_const_i64(s
->pc_curr
+ imm
);
2670 do_fp_ld(s
, rt
, clean_addr
, size
);
2672 /* Only unsigned 32bit loads target 32bit registers. */
2673 bool iss_sf
= opc
!= 0;
2675 do_gpr_ld(s
, tcg_rt
, clean_addr
, size
, is_signed
, false,
2676 true, rt
, iss_sf
, false);
2678 tcg_temp_free_i64(clean_addr
);
2682 * LDNP (Load Pair - non-temporal hint)
2683 * LDP (Load Pair - non vector)
2684 * LDPSW (Load Pair Signed Word - non vector)
2685 * STNP (Store Pair - non-temporal hint)
2686 * STP (Store Pair - non vector)
2687 * LDNP (Load Pair of SIMD&FP - non-temporal hint)
2688 * LDP (Load Pair of SIMD&FP)
2689 * STNP (Store Pair of SIMD&FP - non-temporal hint)
2690 * STP (Store Pair of SIMD&FP)
2692 * 31 30 29 27 26 25 24 23 22 21 15 14 10 9 5 4 0
2693 * +-----+-------+---+---+-------+---+-----------------------------+
2694 * | opc | 1 0 1 | V | 0 | index | L | imm7 | Rt2 | Rn | Rt |
2695 * +-----+-------+---+---+-------+---+-------+-------+------+------+
2697 * opc: LDP/STP/LDNP/STNP 00 -> 32 bit, 10 -> 64 bit
2699 * LDP/STP/LDNP/STNP (SIMD) 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit
2700 * V: 0 -> GPR, 1 -> Vector
2701 * idx: 00 -> signed offset with non-temporal hint, 01 -> post-index,
2702 * 10 -> signed offset, 11 -> pre-index
2703 * L: 0 -> Store 1 -> Load
2705 * Rt, Rt2 = GPR or SIMD registers to be stored
2706 * Rn = general purpose register containing address
2707 * imm7 = signed offset (multiple of 4 or 8 depending on size)
2709 static void disas_ldst_pair(DisasContext
*s
, uint32_t insn
)
2711 int rt
= extract32(insn
, 0, 5);
2712 int rn
= extract32(insn
, 5, 5);
2713 int rt2
= extract32(insn
, 10, 5);
2714 uint64_t offset
= sextract64(insn
, 15, 7);
2715 int index
= extract32(insn
, 23, 2);
2716 bool is_vector
= extract32(insn
, 26, 1);
2717 bool is_load
= extract32(insn
, 22, 1);
2718 int opc
= extract32(insn
, 30, 2);
2720 bool is_signed
= false;
2721 bool postindex
= false;
2724 TCGv_i64 clean_addr
, dirty_addr
;
2729 unallocated_encoding(s
);
2736 size
= 2 + extract32(opc
, 1, 1);
2737 is_signed
= extract32(opc
, 0, 1);
2738 if (!is_load
&& is_signed
) {
2739 unallocated_encoding(s
);
2745 case 1: /* post-index */
2750 /* signed offset with "non-temporal" hint. Since we don't emulate
2751 * caches we don't care about hints to the cache system about
2752 * data access patterns, and handle this identically to plain
2756 /* There is no non-temporal-hint version of LDPSW */
2757 unallocated_encoding(s
);
2762 case 2: /* signed offset, rn not updated */
2765 case 3: /* pre-index */
2771 if (is_vector
&& !fp_access_check(s
)) {
2778 gen_check_sp_alignment(s
);
2781 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
2783 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
2785 clean_addr
= clean_data_tbi(s
, dirty_addr
);
2789 do_fp_ld(s
, rt
, clean_addr
, size
);
2791 do_fp_st(s
, rt
, clean_addr
, size
);
2793 tcg_gen_addi_i64(clean_addr
, clean_addr
, 1 << size
);
2795 do_fp_ld(s
, rt2
, clean_addr
, size
);
2797 do_fp_st(s
, rt2
, clean_addr
, size
);
2800 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2801 TCGv_i64 tcg_rt2
= cpu_reg(s
, rt2
);
2804 TCGv_i64 tmp
= tcg_temp_new_i64();
2806 /* Do not modify tcg_rt before recognizing any exception
2807 * from the second load.
2809 do_gpr_ld(s
, tmp
, clean_addr
, size
, is_signed
, false,
2810 false, 0, false, false);
2811 tcg_gen_addi_i64(clean_addr
, clean_addr
, 1 << size
);
2812 do_gpr_ld(s
, tcg_rt2
, clean_addr
, size
, is_signed
, false,
2813 false, 0, false, false);
2815 tcg_gen_mov_i64(tcg_rt
, tmp
);
2816 tcg_temp_free_i64(tmp
);
2818 do_gpr_st(s
, tcg_rt
, clean_addr
, size
,
2819 false, 0, false, false);
2820 tcg_gen_addi_i64(clean_addr
, clean_addr
, 1 << size
);
2821 do_gpr_st(s
, tcg_rt2
, clean_addr
, size
,
2822 false, 0, false, false);
2828 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
2830 tcg_gen_mov_i64(cpu_reg_sp(s
, rn
), dirty_addr
);
2835 * Load/store (immediate post-indexed)
2836 * Load/store (immediate pre-indexed)
2837 * Load/store (unscaled immediate)
2839 * 31 30 29 27 26 25 24 23 22 21 20 12 11 10 9 5 4 0
2840 * +----+-------+---+-----+-----+---+--------+-----+------+------+
2841 * |size| 1 1 1 | V | 0 0 | opc | 0 | imm9 | idx | Rn | Rt |
2842 * +----+-------+---+-----+-----+---+--------+-----+------+------+
2844 * idx = 01 -> post-indexed, 11 pre-indexed, 00 unscaled imm. (no writeback)
2846 * V = 0 -> non-vector
2847 * size: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64bit
2848 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2850 static void disas_ldst_reg_imm9(DisasContext
*s
, uint32_t insn
,
2856 int rn
= extract32(insn
, 5, 5);
2857 int imm9
= sextract32(insn
, 12, 9);
2858 int idx
= extract32(insn
, 10, 2);
2859 bool is_signed
= false;
2860 bool is_store
= false;
2861 bool is_extended
= false;
2862 bool is_unpriv
= (idx
== 2);
2863 bool iss_valid
= !is_vector
;
2867 TCGv_i64 clean_addr
, dirty_addr
;
2870 size
|= (opc
& 2) << 1;
2871 if (size
> 4 || is_unpriv
) {
2872 unallocated_encoding(s
);
2875 is_store
= ((opc
& 1) == 0);
2876 if (!fp_access_check(s
)) {
2880 if (size
== 3 && opc
== 2) {
2881 /* PRFM - prefetch */
2883 unallocated_encoding(s
);
2888 if (opc
== 3 && size
> 1) {
2889 unallocated_encoding(s
);
2892 is_store
= (opc
== 0);
2893 is_signed
= extract32(opc
, 1, 1);
2894 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
2912 g_assert_not_reached();
2916 gen_check_sp_alignment(s
);
2919 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
2921 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, imm9
);
2923 clean_addr
= clean_data_tbi(s
, dirty_addr
);
2927 do_fp_st(s
, rt
, clean_addr
, size
);
2929 do_fp_ld(s
, rt
, clean_addr
, size
);
2932 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2933 int memidx
= is_unpriv
? get_a64_user_mem_index(s
) : get_mem_index(s
);
2934 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
2937 do_gpr_st_memidx(s
, tcg_rt
, clean_addr
, size
, memidx
,
2938 iss_valid
, rt
, iss_sf
, false);
2940 do_gpr_ld_memidx(s
, tcg_rt
, clean_addr
, size
,
2941 is_signed
, is_extended
, memidx
,
2942 iss_valid
, rt
, iss_sf
, false);
2947 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
2949 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, imm9
);
2951 tcg_gen_mov_i64(tcg_rn
, dirty_addr
);
2956 * Load/store (register offset)
2958 * 31 30 29 27 26 25 24 23 22 21 20 16 15 13 12 11 10 9 5 4 0
2959 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
2960 * |size| 1 1 1 | V | 0 0 | opc | 1 | Rm | opt | S| 1 0 | Rn | Rt |
2961 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
2964 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
2965 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2967 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
2968 * opc<0>: 0 -> store, 1 -> load
2969 * V: 1 -> vector/simd
2970 * opt: extend encoding (see DecodeRegExtend)
2971 * S: if S=1 then scale (essentially index by sizeof(size))
2972 * Rt: register to transfer into/out of
2973 * Rn: address register or SP for base
2974 * Rm: offset register or ZR for offset
2976 static void disas_ldst_reg_roffset(DisasContext
*s
, uint32_t insn
,
2982 int rn
= extract32(insn
, 5, 5);
2983 int shift
= extract32(insn
, 12, 1);
2984 int rm
= extract32(insn
, 16, 5);
2985 int opt
= extract32(insn
, 13, 3);
2986 bool is_signed
= false;
2987 bool is_store
= false;
2988 bool is_extended
= false;
2990 TCGv_i64 tcg_rm
, clean_addr
, dirty_addr
;
2992 if (extract32(opt
, 1, 1) == 0) {
2993 unallocated_encoding(s
);
2998 size
|= (opc
& 2) << 1;
3000 unallocated_encoding(s
);
3003 is_store
= !extract32(opc
, 0, 1);
3004 if (!fp_access_check(s
)) {
3008 if (size
== 3 && opc
== 2) {
3009 /* PRFM - prefetch */
3012 if (opc
== 3 && size
> 1) {
3013 unallocated_encoding(s
);
3016 is_store
= (opc
== 0);
3017 is_signed
= extract32(opc
, 1, 1);
3018 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
3022 gen_check_sp_alignment(s
);
3024 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
3026 tcg_rm
= read_cpu_reg(s
, rm
, 1);
3027 ext_and_shift_reg(tcg_rm
, tcg_rm
, opt
, shift
? size
: 0);
3029 tcg_gen_add_i64(dirty_addr
, dirty_addr
, tcg_rm
);
3030 clean_addr
= clean_data_tbi(s
, dirty_addr
);
3034 do_fp_st(s
, rt
, clean_addr
, size
);
3036 do_fp_ld(s
, rt
, clean_addr
, size
);
3039 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
3040 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
3042 do_gpr_st(s
, tcg_rt
, clean_addr
, size
,
3043 true, rt
, iss_sf
, false);
3045 do_gpr_ld(s
, tcg_rt
, clean_addr
, size
,
3046 is_signed
, is_extended
,
3047 true, rt
, iss_sf
, false);
3053 * Load/store (unsigned immediate)
3055 * 31 30 29 27 26 25 24 23 22 21 10 9 5
3056 * +----+-------+---+-----+-----+------------+-------+------+
3057 * |size| 1 1 1 | V | 0 1 | opc | imm12 | Rn | Rt |
3058 * +----+-------+---+-----+-----+------------+-------+------+
3061 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
3062 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
3064 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
3065 * opc<0>: 0 -> store, 1 -> load
3066 * Rn: base address register (inc SP)
3067 * Rt: target register
3069 static void disas_ldst_reg_unsigned_imm(DisasContext
*s
, uint32_t insn
,
3075 int rn
= extract32(insn
, 5, 5);
3076 unsigned int imm12
= extract32(insn
, 10, 12);
3077 unsigned int offset
;
3079 TCGv_i64 clean_addr
, dirty_addr
;
3082 bool is_signed
= false;
3083 bool is_extended
= false;
3086 size
|= (opc
& 2) << 1;
3088 unallocated_encoding(s
);
3091 is_store
= !extract32(opc
, 0, 1);
3092 if (!fp_access_check(s
)) {
3096 if (size
== 3 && opc
== 2) {
3097 /* PRFM - prefetch */
3100 if (opc
== 3 && size
> 1) {
3101 unallocated_encoding(s
);
3104 is_store
= (opc
== 0);
3105 is_signed
= extract32(opc
, 1, 1);
3106 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
3110 gen_check_sp_alignment(s
);
3112 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
3113 offset
= imm12
<< size
;
3114 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
3115 clean_addr
= clean_data_tbi(s
, dirty_addr
);
3119 do_fp_st(s
, rt
, clean_addr
, size
);
3121 do_fp_ld(s
, rt
, clean_addr
, size
);
3124 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
3125 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
3127 do_gpr_st(s
, tcg_rt
, clean_addr
, size
,
3128 true, rt
, iss_sf
, false);
3130 do_gpr_ld(s
, tcg_rt
, clean_addr
, size
, is_signed
, is_extended
,
3131 true, rt
, iss_sf
, false);
3136 /* Atomic memory operations
3138 * 31 30 27 26 24 22 21 16 15 12 10 5 0
3139 * +------+-------+---+-----+-----+---+----+----+-----+-----+----+-----+
3140 * | size | 1 1 1 | V | 0 0 | A R | 1 | Rs | o3 | opc | 0 0 | Rn | Rt |
3141 * +------+-------+---+-----+-----+--------+----+-----+-----+----+-----+
3143 * Rt: the result register
3144 * Rn: base address or SP
3145 * Rs: the source register for the operation
3146 * V: vector flag (always 0 as of v8.3)
3150 static void disas_ldst_atomic(DisasContext
*s
, uint32_t insn
,
3151 int size
, int rt
, bool is_vector
)
3153 int rs
= extract32(insn
, 16, 5);
3154 int rn
= extract32(insn
, 5, 5);
3155 int o3_opc
= extract32(insn
, 12, 4);
3156 bool r
= extract32(insn
, 22, 1);
3157 bool a
= extract32(insn
, 23, 1);
3158 TCGv_i64 tcg_rs
, clean_addr
;
3159 AtomicThreeOpFn
*fn
;
3161 if (is_vector
|| !dc_isar_feature(aa64_atomics
, s
)) {
3162 unallocated_encoding(s
);
3166 case 000: /* LDADD */
3167 fn
= tcg_gen_atomic_fetch_add_i64
;
3169 case 001: /* LDCLR */
3170 fn
= tcg_gen_atomic_fetch_and_i64
;
3172 case 002: /* LDEOR */
3173 fn
= tcg_gen_atomic_fetch_xor_i64
;
3175 case 003: /* LDSET */
3176 fn
= tcg_gen_atomic_fetch_or_i64
;
3178 case 004: /* LDSMAX */
3179 fn
= tcg_gen_atomic_fetch_smax_i64
;
3181 case 005: /* LDSMIN */
3182 fn
= tcg_gen_atomic_fetch_smin_i64
;
3184 case 006: /* LDUMAX */
3185 fn
= tcg_gen_atomic_fetch_umax_i64
;
3187 case 007: /* LDUMIN */
3188 fn
= tcg_gen_atomic_fetch_umin_i64
;
3191 fn
= tcg_gen_atomic_xchg_i64
;
3193 case 014: /* LDAPR, LDAPRH, LDAPRB */
3194 if (!dc_isar_feature(aa64_rcpc_8_3
, s
) ||
3195 rs
!= 31 || a
!= 1 || r
!= 0) {
3196 unallocated_encoding(s
);
3201 unallocated_encoding(s
);
3206 gen_check_sp_alignment(s
);
3208 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
3210 if (o3_opc
== 014) {
3212 * LDAPR* are a special case because they are a simple load, not a
3213 * fetch-and-do-something op.
3214 * The architectural consistency requirements here are weaker than
3215 * full load-acquire (we only need "load-acquire processor consistent"),
3216 * but we choose to implement them as full LDAQ.
3218 do_gpr_ld(s
, cpu_reg(s
, rt
), clean_addr
, size
, false, false,
3219 true, rt
, disas_ldst_compute_iss_sf(size
, false, 0), true);
3220 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
3224 tcg_rs
= read_cpu_reg(s
, rs
, true);
3226 if (o3_opc
== 1) { /* LDCLR */
3227 tcg_gen_not_i64(tcg_rs
, tcg_rs
);
3230 /* The tcg atomic primitives are all full barriers. Therefore we
3231 * can ignore the Acquire and Release bits of this instruction.
3233 fn(cpu_reg(s
, rt
), clean_addr
, tcg_rs
, get_mem_index(s
),
3234 s
->be_data
| size
| MO_ALIGN
);
3238 * PAC memory operations
3240 * 31 30 27 26 24 22 21 12 11 10 5 0
3241 * +------+-------+---+-----+-----+---+--------+---+---+----+-----+
3242 * | size | 1 1 1 | V | 0 0 | M S | 1 | imm9 | W | 1 | Rn | Rt |
3243 * +------+-------+---+-----+-----+---+--------+---+---+----+-----+
3245 * Rt: the result register
3246 * Rn: base address or SP
3247 * V: vector flag (always 0 as of v8.3)
3248 * M: clear for key DA, set for key DB
3249 * W: pre-indexing flag
3252 static void disas_ldst_pac(DisasContext
*s
, uint32_t insn
,
3253 int size
, int rt
, bool is_vector
)
3255 int rn
= extract32(insn
, 5, 5);
3256 bool is_wback
= extract32(insn
, 11, 1);
3257 bool use_key_a
= !extract32(insn
, 23, 1);
3259 TCGv_i64 clean_addr
, dirty_addr
, tcg_rt
;
3261 if (size
!= 3 || is_vector
|| !dc_isar_feature(aa64_pauth
, s
)) {
3262 unallocated_encoding(s
);
3267 gen_check_sp_alignment(s
);
3269 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
3271 if (s
->pauth_active
) {
3273 gen_helper_autda(dirty_addr
, cpu_env
, dirty_addr
, cpu_X
[31]);
3275 gen_helper_autdb(dirty_addr
, cpu_env
, dirty_addr
, cpu_X
[31]);
3279 /* Form the 10-bit signed, scaled offset. */
3280 offset
= (extract32(insn
, 22, 1) << 9) | extract32(insn
, 12, 9);
3281 offset
= sextract32(offset
<< size
, 0, 10 + size
);
3282 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
3284 /* Note that "clean" and "dirty" here refer to TBI not PAC. */
3285 clean_addr
= clean_data_tbi(s
, dirty_addr
);
3287 tcg_rt
= cpu_reg(s
, rt
);
3288 do_gpr_ld(s
, tcg_rt
, clean_addr
, size
, /* is_signed */ false,
3289 /* extend */ false, /* iss_valid */ !is_wback
,
3290 /* iss_srt */ rt
, /* iss_sf */ true, /* iss_ar */ false);
3293 tcg_gen_mov_i64(cpu_reg_sp(s
, rn
), dirty_addr
);
3298 * LDAPR/STLR (unscaled immediate)
3300 * 31 30 24 22 21 12 10 5 0
3301 * +------+-------------+-----+---+--------+-----+----+-----+
3302 * | size | 0 1 1 0 0 1 | opc | 0 | imm9 | 0 0 | Rn | Rt |
3303 * +------+-------------+-----+---+--------+-----+----+-----+
3305 * Rt: source or destination register
3307 * imm9: unscaled immediate offset
3308 * opc: 00: STLUR*, 01/10/11: various LDAPUR*
3309 * size: size of load/store
3311 static void disas_ldst_ldapr_stlr(DisasContext
*s
, uint32_t insn
)
3313 int rt
= extract32(insn
, 0, 5);
3314 int rn
= extract32(insn
, 5, 5);
3315 int offset
= sextract32(insn
, 12, 9);
3316 int opc
= extract32(insn
, 22, 2);
3317 int size
= extract32(insn
, 30, 2);
3318 TCGv_i64 clean_addr
, dirty_addr
;
3319 bool is_store
= false;
3320 bool is_signed
= false;
3321 bool extend
= false;
3324 if (!dc_isar_feature(aa64_rcpc_8_4
, s
)) {
3325 unallocated_encoding(s
);
3330 case 0: /* STLURB */
3333 case 1: /* LDAPUR* */
3335 case 2: /* LDAPURS* 64-bit variant */
3337 unallocated_encoding(s
);
3342 case 3: /* LDAPURS* 32-bit variant */
3344 unallocated_encoding(s
);
3348 extend
= true; /* zero-extend 32->64 after signed load */
3351 g_assert_not_reached();
3354 iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
3357 gen_check_sp_alignment(s
);
3360 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
3361 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
3362 clean_addr
= clean_data_tbi(s
, dirty_addr
);
3365 /* Store-Release semantics */
3366 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
3367 do_gpr_st(s
, cpu_reg(s
, rt
), clean_addr
, size
, true, rt
, iss_sf
, true);
3370 * Load-AcquirePC semantics; we implement as the slightly more
3371 * restrictive Load-Acquire.
3373 do_gpr_ld(s
, cpu_reg(s
, rt
), clean_addr
, size
, is_signed
, extend
,
3374 true, rt
, iss_sf
, true);
3375 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
3379 /* Load/store register (all forms) */
3380 static void disas_ldst_reg(DisasContext
*s
, uint32_t insn
)
3382 int rt
= extract32(insn
, 0, 5);
3383 int opc
= extract32(insn
, 22, 2);
3384 bool is_vector
= extract32(insn
, 26, 1);
3385 int size
= extract32(insn
, 30, 2);
3387 switch (extract32(insn
, 24, 2)) {
3389 if (extract32(insn
, 21, 1) == 0) {
3390 /* Load/store register (unscaled immediate)
3391 * Load/store immediate pre/post-indexed
3392 * Load/store register unprivileged
3394 disas_ldst_reg_imm9(s
, insn
, opc
, size
, rt
, is_vector
);
3397 switch (extract32(insn
, 10, 2)) {
3399 disas_ldst_atomic(s
, insn
, size
, rt
, is_vector
);
3402 disas_ldst_reg_roffset(s
, insn
, opc
, size
, rt
, is_vector
);
3405 disas_ldst_pac(s
, insn
, size
, rt
, is_vector
);
3410 disas_ldst_reg_unsigned_imm(s
, insn
, opc
, size
, rt
, is_vector
);
3413 unallocated_encoding(s
);
3416 /* AdvSIMD load/store multiple structures
3418 * 31 30 29 23 22 21 16 15 12 11 10 9 5 4 0
3419 * +---+---+---------------+---+-------------+--------+------+------+------+
3420 * | 0 | Q | 0 0 1 1 0 0 0 | L | 0 0 0 0 0 0 | opcode | size | Rn | Rt |
3421 * +---+---+---------------+---+-------------+--------+------+------+------+
3423 * AdvSIMD load/store multiple structures (post-indexed)
3425 * 31 30 29 23 22 21 20 16 15 12 11 10 9 5 4 0
3426 * +---+---+---------------+---+---+---------+--------+------+------+------+
3427 * | 0 | Q | 0 0 1 1 0 0 1 | L | 0 | Rm | opcode | size | Rn | Rt |
3428 * +---+---+---------------+---+---+---------+--------+------+------+------+
3430 * Rt: first (or only) SIMD&FP register to be transferred
3431 * Rn: base address or SP
3432 * Rm (post-index only): post-index register (when !31) or size dependent #imm
3434 static void disas_ldst_multiple_struct(DisasContext
*s
, uint32_t insn
)
3436 int rt
= extract32(insn
, 0, 5);
3437 int rn
= extract32(insn
, 5, 5);
3438 int rm
= extract32(insn
, 16, 5);
3439 int size
= extract32(insn
, 10, 2);
3440 int opcode
= extract32(insn
, 12, 4);
3441 bool is_store
= !extract32(insn
, 22, 1);
3442 bool is_postidx
= extract32(insn
, 23, 1);
3443 bool is_q
= extract32(insn
, 30, 1);
3444 TCGv_i64 clean_addr
, tcg_rn
, tcg_ebytes
;
3445 MemOp endian
= s
->be_data
;
3447 int ebytes
; /* bytes per element */
3448 int elements
; /* elements per vector */
3449 int rpt
; /* num iterations */
3450 int selem
; /* structure elements */
3453 if (extract32(insn
, 31, 1) || extract32(insn
, 21, 1)) {
3454 unallocated_encoding(s
);
3458 if (!is_postidx
&& rm
!= 0) {
3459 unallocated_encoding(s
);
3463 /* From the shared decode logic */
3494 unallocated_encoding(s
);
3498 if (size
== 3 && !is_q
&& selem
!= 1) {
3500 unallocated_encoding(s
);
3504 if (!fp_access_check(s
)) {
3509 gen_check_sp_alignment(s
);
3512 /* For our purposes, bytes are always little-endian. */
3517 /* Consecutive little-endian elements from a single register
3518 * can be promoted to a larger little-endian operation.
3520 if (selem
== 1 && endian
== MO_LE
) {
3524 elements
= (is_q
? 16 : 8) / ebytes
;
3526 tcg_rn
= cpu_reg_sp(s
, rn
);
3527 clean_addr
= clean_data_tbi(s
, tcg_rn
);
3528 tcg_ebytes
= tcg_const_i64(ebytes
);
3530 for (r
= 0; r
< rpt
; r
++) {
3532 for (e
= 0; e
< elements
; e
++) {
3534 for (xs
= 0; xs
< selem
; xs
++) {
3535 int tt
= (rt
+ r
+ xs
) % 32;
3537 do_vec_st(s
, tt
, e
, clean_addr
, size
, endian
);
3539 do_vec_ld(s
, tt
, e
, clean_addr
, size
, endian
);
3541 tcg_gen_add_i64(clean_addr
, clean_addr
, tcg_ebytes
);
3545 tcg_temp_free_i64(tcg_ebytes
);
3548 /* For non-quad operations, setting a slice of the low
3549 * 64 bits of the register clears the high 64 bits (in
3550 * the ARM ARM pseudocode this is implicit in the fact
3551 * that 'rval' is a 64 bit wide variable).
3552 * For quad operations, we might still need to zero the
3555 for (r
= 0; r
< rpt
* selem
; r
++) {
3556 int tt
= (rt
+ r
) % 32;
3557 clear_vec_high(s
, is_q
, tt
);
3563 tcg_gen_addi_i64(tcg_rn
, tcg_rn
, rpt
* elements
* selem
* ebytes
);
3565 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
3570 /* AdvSIMD load/store single structure
3572 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
3573 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3574 * | 0 | Q | 0 0 1 1 0 1 0 | L R | 0 0 0 0 0 | opc | S | size | Rn | Rt |
3575 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3577 * AdvSIMD load/store single structure (post-indexed)
3579 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
3580 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3581 * | 0 | Q | 0 0 1 1 0 1 1 | L R | Rm | opc | S | size | Rn | Rt |
3582 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3584 * Rt: first (or only) SIMD&FP register to be transferred
3585 * Rn: base address or SP
3586 * Rm (post-index only): post-index register (when !31) or size dependent #imm
3587 * index = encoded in Q:S:size dependent on size
3589 * lane_size = encoded in R, opc
3590 * transfer width = encoded in opc, S, size
3592 static void disas_ldst_single_struct(DisasContext
*s
, uint32_t insn
)
3594 int rt
= extract32(insn
, 0, 5);
3595 int rn
= extract32(insn
, 5, 5);
3596 int rm
= extract32(insn
, 16, 5);
3597 int size
= extract32(insn
, 10, 2);
3598 int S
= extract32(insn
, 12, 1);
3599 int opc
= extract32(insn
, 13, 3);
3600 int R
= extract32(insn
, 21, 1);
3601 int is_load
= extract32(insn
, 22, 1);
3602 int is_postidx
= extract32(insn
, 23, 1);
3603 int is_q
= extract32(insn
, 30, 1);
3605 int scale
= extract32(opc
, 1, 2);
3606 int selem
= (extract32(opc
, 0, 1) << 1 | R
) + 1;
3607 bool replicate
= false;
3608 int index
= is_q
<< 3 | S
<< 2 | size
;
3610 TCGv_i64 clean_addr
, tcg_rn
, tcg_ebytes
;
3612 if (extract32(insn
, 31, 1)) {
3613 unallocated_encoding(s
);
3616 if (!is_postidx
&& rm
!= 0) {
3617 unallocated_encoding(s
);
3623 if (!is_load
|| S
) {
3624 unallocated_encoding(s
);
3633 if (extract32(size
, 0, 1)) {
3634 unallocated_encoding(s
);
3640 if (extract32(size
, 1, 1)) {
3641 unallocated_encoding(s
);
3644 if (!extract32(size
, 0, 1)) {
3648 unallocated_encoding(s
);
3656 g_assert_not_reached();
3659 if (!fp_access_check(s
)) {
3663 ebytes
= 1 << scale
;
3666 gen_check_sp_alignment(s
);
3669 tcg_rn
= cpu_reg_sp(s
, rn
);
3670 clean_addr
= clean_data_tbi(s
, tcg_rn
);
3671 tcg_ebytes
= tcg_const_i64(ebytes
);
3673 for (xs
= 0; xs
< selem
; xs
++) {
3675 /* Load and replicate to all elements */
3676 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
3678 tcg_gen_qemu_ld_i64(tcg_tmp
, clean_addr
,
3679 get_mem_index(s
), s
->be_data
+ scale
);
3680 tcg_gen_gvec_dup_i64(scale
, vec_full_reg_offset(s
, rt
),
3681 (is_q
+ 1) * 8, vec_full_reg_size(s
),
3683 tcg_temp_free_i64(tcg_tmp
);
3685 /* Load/store one element per register */
3687 do_vec_ld(s
, rt
, index
, clean_addr
, scale
, s
->be_data
);
3689 do_vec_st(s
, rt
, index
, clean_addr
, scale
, s
->be_data
);
3692 tcg_gen_add_i64(clean_addr
, clean_addr
, tcg_ebytes
);
3695 tcg_temp_free_i64(tcg_ebytes
);
3699 tcg_gen_addi_i64(tcg_rn
, tcg_rn
, selem
* ebytes
);
3701 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
3706 /* Loads and stores */
3707 static void disas_ldst(DisasContext
*s
, uint32_t insn
)
3709 switch (extract32(insn
, 24, 6)) {
3710 case 0x08: /* Load/store exclusive */
3711 disas_ldst_excl(s
, insn
);
3713 case 0x18: case 0x1c: /* Load register (literal) */
3714 disas_ld_lit(s
, insn
);
3716 case 0x28: case 0x29:
3717 case 0x2c: case 0x2d: /* Load/store pair (all forms) */
3718 disas_ldst_pair(s
, insn
);
3720 case 0x38: case 0x39:
3721 case 0x3c: case 0x3d: /* Load/store register (all forms) */
3722 disas_ldst_reg(s
, insn
);
3724 case 0x0c: /* AdvSIMD load/store multiple structures */
3725 disas_ldst_multiple_struct(s
, insn
);
3727 case 0x0d: /* AdvSIMD load/store single structure */
3728 disas_ldst_single_struct(s
, insn
);
3730 case 0x19: /* LDAPR/STLR (unscaled immediate) */
3731 if (extract32(insn
, 10, 2) != 0 ||
3732 extract32(insn
, 21, 1) != 0) {
3733 unallocated_encoding(s
);
3736 disas_ldst_ldapr_stlr(s
, insn
);
3739 unallocated_encoding(s
);
3744 /* PC-rel. addressing
3745 * 31 30 29 28 24 23 5 4 0
3746 * +----+-------+-----------+-------------------+------+
3747 * | op | immlo | 1 0 0 0 0 | immhi | Rd |
3748 * +----+-------+-----------+-------------------+------+
3750 static void disas_pc_rel_adr(DisasContext
*s
, uint32_t insn
)
3752 unsigned int page
, rd
;
3756 page
= extract32(insn
, 31, 1);
3757 /* SignExtend(immhi:immlo) -> offset */
3758 offset
= sextract64(insn
, 5, 19);
3759 offset
= offset
<< 2 | extract32(insn
, 29, 2);
3760 rd
= extract32(insn
, 0, 5);
3764 /* ADRP (page based) */
3769 tcg_gen_movi_i64(cpu_reg(s
, rd
), base
+ offset
);
3773 * Add/subtract (immediate)
3775 * 31 30 29 28 24 23 22 21 10 9 5 4 0
3776 * +--+--+--+-----------+-----+-------------+-----+-----+
3777 * |sf|op| S| 1 0 0 0 1 |shift| imm12 | Rn | Rd |
3778 * +--+--+--+-----------+-----+-------------+-----+-----+
3780 * sf: 0 -> 32bit, 1 -> 64bit
3781 * op: 0 -> add , 1 -> sub
3783 * shift: 00 -> LSL imm by 0, 01 -> LSL imm by 12
3785 static void disas_add_sub_imm(DisasContext
*s
, uint32_t insn
)
3787 int rd
= extract32(insn
, 0, 5);
3788 int rn
= extract32(insn
, 5, 5);
3789 uint64_t imm
= extract32(insn
, 10, 12);
3790 int shift
= extract32(insn
, 22, 2);
3791 bool setflags
= extract32(insn
, 29, 1);
3792 bool sub_op
= extract32(insn
, 30, 1);
3793 bool is_64bit
= extract32(insn
, 31, 1);
3795 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
3796 TCGv_i64 tcg_rd
= setflags
? cpu_reg(s
, rd
) : cpu_reg_sp(s
, rd
);
3797 TCGv_i64 tcg_result
;
3806 unallocated_encoding(s
);
3810 tcg_result
= tcg_temp_new_i64();
3813 tcg_gen_subi_i64(tcg_result
, tcg_rn
, imm
);
3815 tcg_gen_addi_i64(tcg_result
, tcg_rn
, imm
);
3818 TCGv_i64 tcg_imm
= tcg_const_i64(imm
);
3820 gen_sub_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
3822 gen_add_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
3824 tcg_temp_free_i64(tcg_imm
);
3828 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
3830 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
3833 tcg_temp_free_i64(tcg_result
);
3836 /* The input should be a value in the bottom e bits (with higher
3837 * bits zero); returns that value replicated into every element
3838 * of size e in a 64 bit integer.
3840 static uint64_t bitfield_replicate(uint64_t mask
, unsigned int e
)
3850 /* Return a value with the bottom len bits set (where 0 < len <= 64) */
3851 static inline uint64_t bitmask64(unsigned int length
)
3853 assert(length
> 0 && length
<= 64);
3854 return ~0ULL >> (64 - length
);
3857 /* Simplified variant of pseudocode DecodeBitMasks() for the case where we
3858 * only require the wmask. Returns false if the imms/immr/immn are a reserved
3859 * value (ie should cause a guest UNDEF exception), and true if they are
3860 * valid, in which case the decoded bit pattern is written to result.
3862 bool logic_imm_decode_wmask(uint64_t *result
, unsigned int immn
,
3863 unsigned int imms
, unsigned int immr
)
3866 unsigned e
, levels
, s
, r
;
3869 assert(immn
< 2 && imms
< 64 && immr
< 64);
3871 /* The bit patterns we create here are 64 bit patterns which
3872 * are vectors of identical elements of size e = 2, 4, 8, 16, 32 or
3873 * 64 bits each. Each element contains the same value: a run
3874 * of between 1 and e-1 non-zero bits, rotated within the
3875 * element by between 0 and e-1 bits.
3877 * The element size and run length are encoded into immn (1 bit)
3878 * and imms (6 bits) as follows:
3879 * 64 bit elements: immn = 1, imms = <length of run - 1>
3880 * 32 bit elements: immn = 0, imms = 0 : <length of run - 1>
3881 * 16 bit elements: immn = 0, imms = 10 : <length of run - 1>
3882 * 8 bit elements: immn = 0, imms = 110 : <length of run - 1>
3883 * 4 bit elements: immn = 0, imms = 1110 : <length of run - 1>
3884 * 2 bit elements: immn = 0, imms = 11110 : <length of run - 1>
3885 * Notice that immn = 0, imms = 11111x is the only combination
3886 * not covered by one of the above options; this is reserved.
3887 * Further, <length of run - 1> all-ones is a reserved pattern.
3889 * In all cases the rotation is by immr % e (and immr is 6 bits).
3892 /* First determine the element size */
3893 len
= 31 - clz32((immn
<< 6) | (~imms
& 0x3f));
3895 /* This is the immn == 0, imms == 0x11111x case */
3905 /* <length of run - 1> mustn't be all-ones. */
3909 /* Create the value of one element: s+1 set bits rotated
3910 * by r within the element (which is e bits wide)...
3912 mask
= bitmask64(s
+ 1);
3914 mask
= (mask
>> r
) | (mask
<< (e
- r
));
3915 mask
&= bitmask64(e
);
3917 /* ...then replicate the element over the whole 64 bit value */
3918 mask
= bitfield_replicate(mask
, e
);
3923 /* Logical (immediate)
3924 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
3925 * +----+-----+-------------+---+------+------+------+------+
3926 * | sf | opc | 1 0 0 1 0 0 | N | immr | imms | Rn | Rd |
3927 * +----+-----+-------------+---+------+------+------+------+
3929 static void disas_logic_imm(DisasContext
*s
, uint32_t insn
)
3931 unsigned int sf
, opc
, is_n
, immr
, imms
, rn
, rd
;
3932 TCGv_i64 tcg_rd
, tcg_rn
;
3934 bool is_and
= false;
3936 sf
= extract32(insn
, 31, 1);
3937 opc
= extract32(insn
, 29, 2);
3938 is_n
= extract32(insn
, 22, 1);
3939 immr
= extract32(insn
, 16, 6);
3940 imms
= extract32(insn
, 10, 6);
3941 rn
= extract32(insn
, 5, 5);
3942 rd
= extract32(insn
, 0, 5);
3945 unallocated_encoding(s
);
3949 if (opc
== 0x3) { /* ANDS */
3950 tcg_rd
= cpu_reg(s
, rd
);
3952 tcg_rd
= cpu_reg_sp(s
, rd
);
3954 tcg_rn
= cpu_reg(s
, rn
);
3956 if (!logic_imm_decode_wmask(&wmask
, is_n
, imms
, immr
)) {
3957 /* some immediate field values are reserved */
3958 unallocated_encoding(s
);
3963 wmask
&= 0xffffffff;
3967 case 0x3: /* ANDS */
3969 tcg_gen_andi_i64(tcg_rd
, tcg_rn
, wmask
);
3973 tcg_gen_ori_i64(tcg_rd
, tcg_rn
, wmask
);
3976 tcg_gen_xori_i64(tcg_rd
, tcg_rn
, wmask
);
3979 assert(FALSE
); /* must handle all above */
3983 if (!sf
&& !is_and
) {
3984 /* zero extend final result; we know we can skip this for AND
3985 * since the immediate had the high 32 bits clear.
3987 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3990 if (opc
== 3) { /* ANDS */
3991 gen_logic_CC(sf
, tcg_rd
);
3996 * Move wide (immediate)
3998 * 31 30 29 28 23 22 21 20 5 4 0
3999 * +--+-----+-------------+-----+----------------+------+
4000 * |sf| opc | 1 0 0 1 0 1 | hw | imm16 | Rd |
4001 * +--+-----+-------------+-----+----------------+------+
4003 * sf: 0 -> 32 bit, 1 -> 64 bit
4004 * opc: 00 -> N, 10 -> Z, 11 -> K
4005 * hw: shift/16 (0,16, and sf only 32, 48)
4007 static void disas_movw_imm(DisasContext
*s
, uint32_t insn
)
4009 int rd
= extract32(insn
, 0, 5);
4010 uint64_t imm
= extract32(insn
, 5, 16);
4011 int sf
= extract32(insn
, 31, 1);
4012 int opc
= extract32(insn
, 29, 2);
4013 int pos
= extract32(insn
, 21, 2) << 4;
4014 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4017 if (!sf
&& (pos
>= 32)) {
4018 unallocated_encoding(s
);
4032 tcg_gen_movi_i64(tcg_rd
, imm
);
4035 tcg_imm
= tcg_const_i64(imm
);
4036 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_imm
, pos
, 16);
4037 tcg_temp_free_i64(tcg_imm
);
4039 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4043 unallocated_encoding(s
);
4049 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
4050 * +----+-----+-------------+---+------+------+------+------+
4051 * | sf | opc | 1 0 0 1 1 0 | N | immr | imms | Rn | Rd |
4052 * +----+-----+-------------+---+------+------+------+------+
4054 static void disas_bitfield(DisasContext
*s
, uint32_t insn
)
4056 unsigned int sf
, n
, opc
, ri
, si
, rn
, rd
, bitsize
, pos
, len
;
4057 TCGv_i64 tcg_rd
, tcg_tmp
;
4059 sf
= extract32(insn
, 31, 1);
4060 opc
= extract32(insn
, 29, 2);
4061 n
= extract32(insn
, 22, 1);
4062 ri
= extract32(insn
, 16, 6);
4063 si
= extract32(insn
, 10, 6);
4064 rn
= extract32(insn
, 5, 5);
4065 rd
= extract32(insn
, 0, 5);
4066 bitsize
= sf
? 64 : 32;
4068 if (sf
!= n
|| ri
>= bitsize
|| si
>= bitsize
|| opc
> 2) {
4069 unallocated_encoding(s
);
4073 tcg_rd
= cpu_reg(s
, rd
);
4075 /* Suppress the zero-extend for !sf. Since RI and SI are constrained
4076 to be smaller than bitsize, we'll never reference data outside the
4077 low 32-bits anyway. */
4078 tcg_tmp
= read_cpu_reg(s
, rn
, 1);
4080 /* Recognize simple(r) extractions. */
4082 /* Wd<s-r:0> = Wn<s:r> */
4083 len
= (si
- ri
) + 1;
4084 if (opc
== 0) { /* SBFM: ASR, SBFX, SXTB, SXTH, SXTW */
4085 tcg_gen_sextract_i64(tcg_rd
, tcg_tmp
, ri
, len
);
4087 } else if (opc
== 2) { /* UBFM: UBFX, LSR, UXTB, UXTH */
4088 tcg_gen_extract_i64(tcg_rd
, tcg_tmp
, ri
, len
);
4091 /* opc == 1, BFXIL fall through to deposit */
4092 tcg_gen_shri_i64(tcg_tmp
, tcg_tmp
, ri
);
4095 /* Handle the ri > si case with a deposit
4096 * Wd<32+s-r,32-r> = Wn<s:0>
4099 pos
= (bitsize
- ri
) & (bitsize
- 1);
4102 if (opc
== 0 && len
< ri
) {
4103 /* SBFM: sign extend the destination field from len to fill
4104 the balance of the word. Let the deposit below insert all
4105 of those sign bits. */
4106 tcg_gen_sextract_i64(tcg_tmp
, tcg_tmp
, 0, len
);
4110 if (opc
== 1) { /* BFM, BFXIL */
4111 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, pos
, len
);
4113 /* SBFM or UBFM: We start with zero, and we haven't modified
4114 any bits outside bitsize, therefore the zero-extension
4115 below is unneeded. */
4116 tcg_gen_deposit_z_i64(tcg_rd
, tcg_tmp
, pos
, len
);
4121 if (!sf
) { /* zero extend final result */
4122 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4127 * 31 30 29 28 23 22 21 20 16 15 10 9 5 4 0
4128 * +----+------+-------------+---+----+------+--------+------+------+
4129 * | sf | op21 | 1 0 0 1 1 1 | N | o0 | Rm | imms | Rn | Rd |
4130 * +----+------+-------------+---+----+------+--------+------+------+
4132 static void disas_extract(DisasContext
*s
, uint32_t insn
)
4134 unsigned int sf
, n
, rm
, imm
, rn
, rd
, bitsize
, op21
, op0
;
4136 sf
= extract32(insn
, 31, 1);
4137 n
= extract32(insn
, 22, 1);
4138 rm
= extract32(insn
, 16, 5);
4139 imm
= extract32(insn
, 10, 6);
4140 rn
= extract32(insn
, 5, 5);
4141 rd
= extract32(insn
, 0, 5);
4142 op21
= extract32(insn
, 29, 2);
4143 op0
= extract32(insn
, 21, 1);
4144 bitsize
= sf
? 64 : 32;
4146 if (sf
!= n
|| op21
|| op0
|| imm
>= bitsize
) {
4147 unallocated_encoding(s
);
4149 TCGv_i64 tcg_rd
, tcg_rm
, tcg_rn
;
4151 tcg_rd
= cpu_reg(s
, rd
);
4153 if (unlikely(imm
== 0)) {
4154 /* tcg shl_i32/shl_i64 is undefined for 32/64 bit shifts,
4155 * so an extract from bit 0 is a special case.
4158 tcg_gen_mov_i64(tcg_rd
, cpu_reg(s
, rm
));
4160 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rm
));
4163 tcg_rm
= cpu_reg(s
, rm
);
4164 tcg_rn
= cpu_reg(s
, rn
);
4167 /* Specialization to ROR happens in EXTRACT2. */
4168 tcg_gen_extract2_i64(tcg_rd
, tcg_rm
, tcg_rn
, imm
);
4170 TCGv_i32 t0
= tcg_temp_new_i32();
4172 tcg_gen_extrl_i64_i32(t0
, tcg_rm
);
4174 tcg_gen_rotri_i32(t0
, t0
, imm
);
4176 TCGv_i32 t1
= tcg_temp_new_i32();
4177 tcg_gen_extrl_i64_i32(t1
, tcg_rn
);
4178 tcg_gen_extract2_i32(t0
, t0
, t1
, imm
);
4179 tcg_temp_free_i32(t1
);
4181 tcg_gen_extu_i32_i64(tcg_rd
, t0
);
4182 tcg_temp_free_i32(t0
);
4188 /* Data processing - immediate */
4189 static void disas_data_proc_imm(DisasContext
*s
, uint32_t insn
)
4191 switch (extract32(insn
, 23, 6)) {
4192 case 0x20: case 0x21: /* PC-rel. addressing */
4193 disas_pc_rel_adr(s
, insn
);
4195 case 0x22: case 0x23: /* Add/subtract (immediate) */
4196 disas_add_sub_imm(s
, insn
);
4198 case 0x24: /* Logical (immediate) */
4199 disas_logic_imm(s
, insn
);
4201 case 0x25: /* Move wide (immediate) */
4202 disas_movw_imm(s
, insn
);
4204 case 0x26: /* Bitfield */
4205 disas_bitfield(s
, insn
);
4207 case 0x27: /* Extract */
4208 disas_extract(s
, insn
);
4211 unallocated_encoding(s
);
4216 /* Shift a TCGv src by TCGv shift_amount, put result in dst.
4217 * Note that it is the caller's responsibility to ensure that the
4218 * shift amount is in range (ie 0..31 or 0..63) and provide the ARM
4219 * mandated semantics for out of range shifts.
4221 static void shift_reg(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
4222 enum a64_shift_type shift_type
, TCGv_i64 shift_amount
)
4224 switch (shift_type
) {
4225 case A64_SHIFT_TYPE_LSL
:
4226 tcg_gen_shl_i64(dst
, src
, shift_amount
);
4228 case A64_SHIFT_TYPE_LSR
:
4229 tcg_gen_shr_i64(dst
, src
, shift_amount
);
4231 case A64_SHIFT_TYPE_ASR
:
4233 tcg_gen_ext32s_i64(dst
, src
);
4235 tcg_gen_sar_i64(dst
, sf
? src
: dst
, shift_amount
);
4237 case A64_SHIFT_TYPE_ROR
:
4239 tcg_gen_rotr_i64(dst
, src
, shift_amount
);
4242 t0
= tcg_temp_new_i32();
4243 t1
= tcg_temp_new_i32();
4244 tcg_gen_extrl_i64_i32(t0
, src
);
4245 tcg_gen_extrl_i64_i32(t1
, shift_amount
);
4246 tcg_gen_rotr_i32(t0
, t0
, t1
);
4247 tcg_gen_extu_i32_i64(dst
, t0
);
4248 tcg_temp_free_i32(t0
);
4249 tcg_temp_free_i32(t1
);
4253 assert(FALSE
); /* all shift types should be handled */
4257 if (!sf
) { /* zero extend final result */
4258 tcg_gen_ext32u_i64(dst
, dst
);
4262 /* Shift a TCGv src by immediate, put result in dst.
4263 * The shift amount must be in range (this should always be true as the
4264 * relevant instructions will UNDEF on bad shift immediates).
4266 static void shift_reg_imm(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
4267 enum a64_shift_type shift_type
, unsigned int shift_i
)
4269 assert(shift_i
< (sf
? 64 : 32));
4272 tcg_gen_mov_i64(dst
, src
);
4274 TCGv_i64 shift_const
;
4276 shift_const
= tcg_const_i64(shift_i
);
4277 shift_reg(dst
, src
, sf
, shift_type
, shift_const
);
4278 tcg_temp_free_i64(shift_const
);
4282 /* Logical (shifted register)
4283 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
4284 * +----+-----+-----------+-------+---+------+--------+------+------+
4285 * | sf | opc | 0 1 0 1 0 | shift | N | Rm | imm6 | Rn | Rd |
4286 * +----+-----+-----------+-------+---+------+--------+------+------+
4288 static void disas_logic_reg(DisasContext
*s
, uint32_t insn
)
4290 TCGv_i64 tcg_rd
, tcg_rn
, tcg_rm
;
4291 unsigned int sf
, opc
, shift_type
, invert
, rm
, shift_amount
, rn
, rd
;
4293 sf
= extract32(insn
, 31, 1);
4294 opc
= extract32(insn
, 29, 2);
4295 shift_type
= extract32(insn
, 22, 2);
4296 invert
= extract32(insn
, 21, 1);
4297 rm
= extract32(insn
, 16, 5);
4298 shift_amount
= extract32(insn
, 10, 6);
4299 rn
= extract32(insn
, 5, 5);
4300 rd
= extract32(insn
, 0, 5);
4302 if (!sf
&& (shift_amount
& (1 << 5))) {
4303 unallocated_encoding(s
);
4307 tcg_rd
= cpu_reg(s
, rd
);
4309 if (opc
== 1 && shift_amount
== 0 && shift_type
== 0 && rn
== 31) {
4310 /* Unshifted ORR and ORN with WZR/XZR is the standard encoding for
4311 * register-register MOV and MVN, so it is worth special casing.
4313 tcg_rm
= cpu_reg(s
, rm
);
4315 tcg_gen_not_i64(tcg_rd
, tcg_rm
);
4317 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4321 tcg_gen_mov_i64(tcg_rd
, tcg_rm
);
4323 tcg_gen_ext32u_i64(tcg_rd
, tcg_rm
);
4329 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
4332 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, shift_amount
);
4335 tcg_rn
= cpu_reg(s
, rn
);
4337 switch (opc
| (invert
<< 2)) {
4340 tcg_gen_and_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4343 tcg_gen_or_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4346 tcg_gen_xor_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4350 tcg_gen_andc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4353 tcg_gen_orc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4356 tcg_gen_eqv_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4364 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4368 gen_logic_CC(sf
, tcg_rd
);
4373 * Add/subtract (extended register)
4375 * 31|30|29|28 24|23 22|21|20 16|15 13|12 10|9 5|4 0|
4376 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
4377 * |sf|op| S| 0 1 0 1 1 | opt | 1| Rm |option| imm3 | Rn | Rd |
4378 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
4380 * sf: 0 -> 32bit, 1 -> 64bit
4381 * op: 0 -> add , 1 -> sub
4384 * option: extension type (see DecodeRegExtend)
4385 * imm3: optional shift to Rm
4387 * Rd = Rn + LSL(extend(Rm), amount)
4389 static void disas_add_sub_ext_reg(DisasContext
*s
, uint32_t insn
)
4391 int rd
= extract32(insn
, 0, 5);
4392 int rn
= extract32(insn
, 5, 5);
4393 int imm3
= extract32(insn
, 10, 3);
4394 int option
= extract32(insn
, 13, 3);
4395 int rm
= extract32(insn
, 16, 5);
4396 int opt
= extract32(insn
, 22, 2);
4397 bool setflags
= extract32(insn
, 29, 1);
4398 bool sub_op
= extract32(insn
, 30, 1);
4399 bool sf
= extract32(insn
, 31, 1);
4401 TCGv_i64 tcg_rm
, tcg_rn
; /* temps */
4403 TCGv_i64 tcg_result
;
4405 if (imm3
> 4 || opt
!= 0) {
4406 unallocated_encoding(s
);
4410 /* non-flag setting ops may use SP */
4412 tcg_rd
= cpu_reg_sp(s
, rd
);
4414 tcg_rd
= cpu_reg(s
, rd
);
4416 tcg_rn
= read_cpu_reg_sp(s
, rn
, sf
);
4418 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
4419 ext_and_shift_reg(tcg_rm
, tcg_rm
, option
, imm3
);
4421 tcg_result
= tcg_temp_new_i64();
4425 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
4427 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
4431 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4433 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4438 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
4440 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
4443 tcg_temp_free_i64(tcg_result
);
4447 * Add/subtract (shifted register)
4449 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
4450 * +--+--+--+-----------+-----+--+-------+---------+------+------+
4451 * |sf|op| S| 0 1 0 1 1 |shift| 0| Rm | imm6 | Rn | Rd |
4452 * +--+--+--+-----------+-----+--+-------+---------+------+------+
4454 * sf: 0 -> 32bit, 1 -> 64bit
4455 * op: 0 -> add , 1 -> sub
4457 * shift: 00 -> LSL, 01 -> LSR, 10 -> ASR, 11 -> RESERVED
4458 * imm6: Shift amount to apply to Rm before the add/sub
4460 static void disas_add_sub_reg(DisasContext
*s
, uint32_t insn
)
4462 int rd
= extract32(insn
, 0, 5);
4463 int rn
= extract32(insn
, 5, 5);
4464 int imm6
= extract32(insn
, 10, 6);
4465 int rm
= extract32(insn
, 16, 5);
4466 int shift_type
= extract32(insn
, 22, 2);
4467 bool setflags
= extract32(insn
, 29, 1);
4468 bool sub_op
= extract32(insn
, 30, 1);
4469 bool sf
= extract32(insn
, 31, 1);
4471 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4472 TCGv_i64 tcg_rn
, tcg_rm
;
4473 TCGv_i64 tcg_result
;
4475 if ((shift_type
== 3) || (!sf
&& (imm6
> 31))) {
4476 unallocated_encoding(s
);
4480 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4481 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
4483 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, imm6
);
4485 tcg_result
= tcg_temp_new_i64();
4489 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
4491 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
4495 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4497 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4502 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
4504 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
4507 tcg_temp_free_i64(tcg_result
);
4510 /* Data-processing (3 source)
4512 * 31 30 29 28 24 23 21 20 16 15 14 10 9 5 4 0
4513 * +--+------+-----------+------+------+----+------+------+------+
4514 * |sf| op54 | 1 1 0 1 1 | op31 | Rm | o0 | Ra | Rn | Rd |
4515 * +--+------+-----------+------+------+----+------+------+------+
4517 static void disas_data_proc_3src(DisasContext
*s
, uint32_t insn
)
4519 int rd
= extract32(insn
, 0, 5);
4520 int rn
= extract32(insn
, 5, 5);
4521 int ra
= extract32(insn
, 10, 5);
4522 int rm
= extract32(insn
, 16, 5);
4523 int op_id
= (extract32(insn
, 29, 3) << 4) |
4524 (extract32(insn
, 21, 3) << 1) |
4525 extract32(insn
, 15, 1);
4526 bool sf
= extract32(insn
, 31, 1);
4527 bool is_sub
= extract32(op_id
, 0, 1);
4528 bool is_high
= extract32(op_id
, 2, 1);
4529 bool is_signed
= false;
4534 /* Note that op_id is sf:op54:op31:o0 so it includes the 32/64 size flag */
4536 case 0x42: /* SMADDL */
4537 case 0x43: /* SMSUBL */
4538 case 0x44: /* SMULH */
4541 case 0x0: /* MADD (32bit) */
4542 case 0x1: /* MSUB (32bit) */
4543 case 0x40: /* MADD (64bit) */
4544 case 0x41: /* MSUB (64bit) */
4545 case 0x4a: /* UMADDL */
4546 case 0x4b: /* UMSUBL */
4547 case 0x4c: /* UMULH */
4550 unallocated_encoding(s
);
4555 TCGv_i64 low_bits
= tcg_temp_new_i64(); /* low bits discarded */
4556 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4557 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
4558 TCGv_i64 tcg_rm
= cpu_reg(s
, rm
);
4561 tcg_gen_muls2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
4563 tcg_gen_mulu2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
4566 tcg_temp_free_i64(low_bits
);
4570 tcg_op1
= tcg_temp_new_i64();
4571 tcg_op2
= tcg_temp_new_i64();
4572 tcg_tmp
= tcg_temp_new_i64();
4575 tcg_gen_mov_i64(tcg_op1
, cpu_reg(s
, rn
));
4576 tcg_gen_mov_i64(tcg_op2
, cpu_reg(s
, rm
));
4579 tcg_gen_ext32s_i64(tcg_op1
, cpu_reg(s
, rn
));
4580 tcg_gen_ext32s_i64(tcg_op2
, cpu_reg(s
, rm
));
4582 tcg_gen_ext32u_i64(tcg_op1
, cpu_reg(s
, rn
));
4583 tcg_gen_ext32u_i64(tcg_op2
, cpu_reg(s
, rm
));
4587 if (ra
== 31 && !is_sub
) {
4588 /* Special-case MADD with rA == XZR; it is the standard MUL alias */
4589 tcg_gen_mul_i64(cpu_reg(s
, rd
), tcg_op1
, tcg_op2
);
4591 tcg_gen_mul_i64(tcg_tmp
, tcg_op1
, tcg_op2
);
4593 tcg_gen_sub_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
4595 tcg_gen_add_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
4600 tcg_gen_ext32u_i64(cpu_reg(s
, rd
), cpu_reg(s
, rd
));
4603 tcg_temp_free_i64(tcg_op1
);
4604 tcg_temp_free_i64(tcg_op2
);
4605 tcg_temp_free_i64(tcg_tmp
);
4608 /* Add/subtract (with carry)
4609 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 10 9 5 4 0
4610 * +--+--+--+------------------------+------+-------------+------+-----+
4611 * |sf|op| S| 1 1 0 1 0 0 0 0 | rm | 0 0 0 0 0 0 | Rn | Rd |
4612 * +--+--+--+------------------------+------+-------------+------+-----+
4615 static void disas_adc_sbc(DisasContext
*s
, uint32_t insn
)
4617 unsigned int sf
, op
, setflags
, rm
, rn
, rd
;
4618 TCGv_i64 tcg_y
, tcg_rn
, tcg_rd
;
4620 sf
= extract32(insn
, 31, 1);
4621 op
= extract32(insn
, 30, 1);
4622 setflags
= extract32(insn
, 29, 1);
4623 rm
= extract32(insn
, 16, 5);
4624 rn
= extract32(insn
, 5, 5);
4625 rd
= extract32(insn
, 0, 5);
4627 tcg_rd
= cpu_reg(s
, rd
);
4628 tcg_rn
= cpu_reg(s
, rn
);
4631 tcg_y
= new_tmp_a64(s
);
4632 tcg_gen_not_i64(tcg_y
, cpu_reg(s
, rm
));
4634 tcg_y
= cpu_reg(s
, rm
);
4638 gen_adc_CC(sf
, tcg_rd
, tcg_rn
, tcg_y
);
4640 gen_adc(sf
, tcg_rd
, tcg_rn
, tcg_y
);
4645 * Rotate right into flags
4646 * 31 30 29 21 15 10 5 4 0
4647 * +--+--+--+-----------------+--------+-----------+------+--+------+
4648 * |sf|op| S| 1 1 0 1 0 0 0 0 | imm6 | 0 0 0 0 1 | Rn |o2| mask |
4649 * +--+--+--+-----------------+--------+-----------+------+--+------+
4651 static void disas_rotate_right_into_flags(DisasContext
*s
, uint32_t insn
)
4653 int mask
= extract32(insn
, 0, 4);
4654 int o2
= extract32(insn
, 4, 1);
4655 int rn
= extract32(insn
, 5, 5);
4656 int imm6
= extract32(insn
, 15, 6);
4657 int sf_op_s
= extract32(insn
, 29, 3);
4661 if (sf_op_s
!= 5 || o2
!= 0 || !dc_isar_feature(aa64_condm_4
, s
)) {
4662 unallocated_encoding(s
);
4666 tcg_rn
= read_cpu_reg(s
, rn
, 1);
4667 tcg_gen_rotri_i64(tcg_rn
, tcg_rn
, imm6
);
4669 nzcv
= tcg_temp_new_i32();
4670 tcg_gen_extrl_i64_i32(nzcv
, tcg_rn
);
4672 if (mask
& 8) { /* N */
4673 tcg_gen_shli_i32(cpu_NF
, nzcv
, 31 - 3);
4675 if (mask
& 4) { /* Z */
4676 tcg_gen_not_i32(cpu_ZF
, nzcv
);
4677 tcg_gen_andi_i32(cpu_ZF
, cpu_ZF
, 4);
4679 if (mask
& 2) { /* C */
4680 tcg_gen_extract_i32(cpu_CF
, nzcv
, 1, 1);
4682 if (mask
& 1) { /* V */
4683 tcg_gen_shli_i32(cpu_VF
, nzcv
, 31 - 0);
4686 tcg_temp_free_i32(nzcv
);
4690 * Evaluate into flags
4691 * 31 30 29 21 15 14 10 5 4 0
4692 * +--+--+--+-----------------+---------+----+---------+------+--+------+
4693 * |sf|op| S| 1 1 0 1 0 0 0 0 | opcode2 | sz | 0 0 1 0 | Rn |o3| mask |
4694 * +--+--+--+-----------------+---------+----+---------+------+--+------+
4696 static void disas_evaluate_into_flags(DisasContext
*s
, uint32_t insn
)
4698 int o3_mask
= extract32(insn
, 0, 5);
4699 int rn
= extract32(insn
, 5, 5);
4700 int o2
= extract32(insn
, 15, 6);
4701 int sz
= extract32(insn
, 14, 1);
4702 int sf_op_s
= extract32(insn
, 29, 3);
4706 if (sf_op_s
!= 1 || o2
!= 0 || o3_mask
!= 0xd ||
4707 !dc_isar_feature(aa64_condm_4
, s
)) {
4708 unallocated_encoding(s
);
4711 shift
= sz
? 16 : 24; /* SETF16 or SETF8 */
4713 tmp
= tcg_temp_new_i32();
4714 tcg_gen_extrl_i64_i32(tmp
, cpu_reg(s
, rn
));
4715 tcg_gen_shli_i32(cpu_NF
, tmp
, shift
);
4716 tcg_gen_shli_i32(cpu_VF
, tmp
, shift
- 1);
4717 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
4718 tcg_gen_xor_i32(cpu_VF
, cpu_VF
, cpu_NF
);
4719 tcg_temp_free_i32(tmp
);
4722 /* Conditional compare (immediate / register)
4723 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
4724 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
4725 * |sf|op| S| 1 1 0 1 0 0 1 0 |imm5/rm | cond |i/r |o2| Rn |o3|nzcv |
4726 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
4729 static void disas_cc(DisasContext
*s
, uint32_t insn
)
4731 unsigned int sf
, op
, y
, cond
, rn
, nzcv
, is_imm
;
4732 TCGv_i32 tcg_t0
, tcg_t1
, tcg_t2
;
4733 TCGv_i64 tcg_tmp
, tcg_y
, tcg_rn
;
4736 if (!extract32(insn
, 29, 1)) {
4737 unallocated_encoding(s
);
4740 if (insn
& (1 << 10 | 1 << 4)) {
4741 unallocated_encoding(s
);
4744 sf
= extract32(insn
, 31, 1);
4745 op
= extract32(insn
, 30, 1);
4746 is_imm
= extract32(insn
, 11, 1);
4747 y
= extract32(insn
, 16, 5); /* y = rm (reg) or imm5 (imm) */
4748 cond
= extract32(insn
, 12, 4);
4749 rn
= extract32(insn
, 5, 5);
4750 nzcv
= extract32(insn
, 0, 4);
4752 /* Set T0 = !COND. */
4753 tcg_t0
= tcg_temp_new_i32();
4754 arm_test_cc(&c
, cond
);
4755 tcg_gen_setcondi_i32(tcg_invert_cond(c
.cond
), tcg_t0
, c
.value
, 0);
4758 /* Load the arguments for the new comparison. */
4760 tcg_y
= new_tmp_a64(s
);
4761 tcg_gen_movi_i64(tcg_y
, y
);
4763 tcg_y
= cpu_reg(s
, y
);
4765 tcg_rn
= cpu_reg(s
, rn
);
4767 /* Set the flags for the new comparison. */
4768 tcg_tmp
= tcg_temp_new_i64();
4770 gen_sub_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
4772 gen_add_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
4774 tcg_temp_free_i64(tcg_tmp
);
4776 /* If COND was false, force the flags to #nzcv. Compute two masks
4777 * to help with this: T1 = (COND ? 0 : -1), T2 = (COND ? -1 : 0).
4778 * For tcg hosts that support ANDC, we can make do with just T1.
4779 * In either case, allow the tcg optimizer to delete any unused mask.
4781 tcg_t1
= tcg_temp_new_i32();
4782 tcg_t2
= tcg_temp_new_i32();
4783 tcg_gen_neg_i32(tcg_t1
, tcg_t0
);
4784 tcg_gen_subi_i32(tcg_t2
, tcg_t0
, 1);
4786 if (nzcv
& 8) { /* N */
4787 tcg_gen_or_i32(cpu_NF
, cpu_NF
, tcg_t1
);
4789 if (TCG_TARGET_HAS_andc_i32
) {
4790 tcg_gen_andc_i32(cpu_NF
, cpu_NF
, tcg_t1
);
4792 tcg_gen_and_i32(cpu_NF
, cpu_NF
, tcg_t2
);
4795 if (nzcv
& 4) { /* Z */
4796 if (TCG_TARGET_HAS_andc_i32
) {
4797 tcg_gen_andc_i32(cpu_ZF
, cpu_ZF
, tcg_t1
);
4799 tcg_gen_and_i32(cpu_ZF
, cpu_ZF
, tcg_t2
);
4802 tcg_gen_or_i32(cpu_ZF
, cpu_ZF
, tcg_t0
);
4804 if (nzcv
& 2) { /* C */
4805 tcg_gen_or_i32(cpu_CF
, cpu_CF
, tcg_t0
);
4807 if (TCG_TARGET_HAS_andc_i32
) {
4808 tcg_gen_andc_i32(cpu_CF
, cpu_CF
, tcg_t1
);
4810 tcg_gen_and_i32(cpu_CF
, cpu_CF
, tcg_t2
);
4813 if (nzcv
& 1) { /* V */
4814 tcg_gen_or_i32(cpu_VF
, cpu_VF
, tcg_t1
);
4816 if (TCG_TARGET_HAS_andc_i32
) {
4817 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tcg_t1
);
4819 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tcg_t2
);
4822 tcg_temp_free_i32(tcg_t0
);
4823 tcg_temp_free_i32(tcg_t1
);
4824 tcg_temp_free_i32(tcg_t2
);
4827 /* Conditional select
4828 * 31 30 29 28 21 20 16 15 12 11 10 9 5 4 0
4829 * +----+----+---+-----------------+------+------+-----+------+------+
4830 * | sf | op | S | 1 1 0 1 0 1 0 0 | Rm | cond | op2 | Rn | Rd |
4831 * +----+----+---+-----------------+------+------+-----+------+------+
4833 static void disas_cond_select(DisasContext
*s
, uint32_t insn
)
4835 unsigned int sf
, else_inv
, rm
, cond
, else_inc
, rn
, rd
;
4836 TCGv_i64 tcg_rd
, zero
;
4839 if (extract32(insn
, 29, 1) || extract32(insn
, 11, 1)) {
4840 /* S == 1 or op2<1> == 1 */
4841 unallocated_encoding(s
);
4844 sf
= extract32(insn
, 31, 1);
4845 else_inv
= extract32(insn
, 30, 1);
4846 rm
= extract32(insn
, 16, 5);
4847 cond
= extract32(insn
, 12, 4);
4848 else_inc
= extract32(insn
, 10, 1);
4849 rn
= extract32(insn
, 5, 5);
4850 rd
= extract32(insn
, 0, 5);
4852 tcg_rd
= cpu_reg(s
, rd
);
4854 a64_test_cc(&c
, cond
);
4855 zero
= tcg_const_i64(0);
4857 if (rn
== 31 && rm
== 31 && (else_inc
^ else_inv
)) {
4859 tcg_gen_setcond_i64(tcg_invert_cond(c
.cond
), tcg_rd
, c
.value
, zero
);
4861 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
4864 TCGv_i64 t_true
= cpu_reg(s
, rn
);
4865 TCGv_i64 t_false
= read_cpu_reg(s
, rm
, 1);
4866 if (else_inv
&& else_inc
) {
4867 tcg_gen_neg_i64(t_false
, t_false
);
4868 } else if (else_inv
) {
4869 tcg_gen_not_i64(t_false
, t_false
);
4870 } else if (else_inc
) {
4871 tcg_gen_addi_i64(t_false
, t_false
, 1);
4873 tcg_gen_movcond_i64(c
.cond
, tcg_rd
, c
.value
, zero
, t_true
, t_false
);
4876 tcg_temp_free_i64(zero
);
4880 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4884 static void handle_clz(DisasContext
*s
, unsigned int sf
,
4885 unsigned int rn
, unsigned int rd
)
4887 TCGv_i64 tcg_rd
, tcg_rn
;
4888 tcg_rd
= cpu_reg(s
, rd
);
4889 tcg_rn
= cpu_reg(s
, rn
);
4892 tcg_gen_clzi_i64(tcg_rd
, tcg_rn
, 64);
4894 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
4895 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
4896 tcg_gen_clzi_i32(tcg_tmp32
, tcg_tmp32
, 32);
4897 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
4898 tcg_temp_free_i32(tcg_tmp32
);
4902 static void handle_cls(DisasContext
*s
, unsigned int sf
,
4903 unsigned int rn
, unsigned int rd
)
4905 TCGv_i64 tcg_rd
, tcg_rn
;
4906 tcg_rd
= cpu_reg(s
, rd
);
4907 tcg_rn
= cpu_reg(s
, rn
);
4910 tcg_gen_clrsb_i64(tcg_rd
, tcg_rn
);
4912 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
4913 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
4914 tcg_gen_clrsb_i32(tcg_tmp32
, tcg_tmp32
);
4915 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
4916 tcg_temp_free_i32(tcg_tmp32
);
4920 static void handle_rbit(DisasContext
*s
, unsigned int sf
,
4921 unsigned int rn
, unsigned int rd
)
4923 TCGv_i64 tcg_rd
, tcg_rn
;
4924 tcg_rd
= cpu_reg(s
, rd
);
4925 tcg_rn
= cpu_reg(s
, rn
);
4928 gen_helper_rbit64(tcg_rd
, tcg_rn
);
4930 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
4931 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
4932 gen_helper_rbit(tcg_tmp32
, tcg_tmp32
);
4933 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
4934 tcg_temp_free_i32(tcg_tmp32
);
4938 /* REV with sf==1, opcode==3 ("REV64") */
4939 static void handle_rev64(DisasContext
*s
, unsigned int sf
,
4940 unsigned int rn
, unsigned int rd
)
4943 unallocated_encoding(s
);
4946 tcg_gen_bswap64_i64(cpu_reg(s
, rd
), cpu_reg(s
, rn
));
4949 /* REV with sf==0, opcode==2
4950 * REV32 (sf==1, opcode==2)
4952 static void handle_rev32(DisasContext
*s
, unsigned int sf
,
4953 unsigned int rn
, unsigned int rd
)
4955 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4958 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
4959 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4961 /* bswap32_i64 requires zero high word */
4962 tcg_gen_ext32u_i64(tcg_tmp
, tcg_rn
);
4963 tcg_gen_bswap32_i64(tcg_rd
, tcg_tmp
);
4964 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 32);
4965 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
);
4966 tcg_gen_concat32_i64(tcg_rd
, tcg_rd
, tcg_tmp
);
4968 tcg_temp_free_i64(tcg_tmp
);
4970 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rn
));
4971 tcg_gen_bswap32_i64(tcg_rd
, tcg_rd
);
4975 /* REV16 (opcode==1) */
4976 static void handle_rev16(DisasContext
*s
, unsigned int sf
,
4977 unsigned int rn
, unsigned int rd
)
4979 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4980 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
4981 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4982 TCGv_i64 mask
= tcg_const_i64(sf
? 0x00ff00ff00ff00ffull
: 0x00ff00ff);
4984 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 8);
4985 tcg_gen_and_i64(tcg_rd
, tcg_rn
, mask
);
4986 tcg_gen_and_i64(tcg_tmp
, tcg_tmp
, mask
);
4987 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, 8);
4988 tcg_gen_or_i64(tcg_rd
, tcg_rd
, tcg_tmp
);
4990 tcg_temp_free_i64(mask
);
4991 tcg_temp_free_i64(tcg_tmp
);
4994 /* Data-processing (1 source)
4995 * 31 30 29 28 21 20 16 15 10 9 5 4 0
4996 * +----+---+---+-----------------+---------+--------+------+------+
4997 * | sf | 1 | S | 1 1 0 1 0 1 1 0 | opcode2 | opcode | Rn | Rd |
4998 * +----+---+---+-----------------+---------+--------+------+------+
5000 static void disas_data_proc_1src(DisasContext
*s
, uint32_t insn
)
5002 unsigned int sf
, opcode
, opcode2
, rn
, rd
;
5005 if (extract32(insn
, 29, 1)) {
5006 unallocated_encoding(s
);
5010 sf
= extract32(insn
, 31, 1);
5011 opcode
= extract32(insn
, 10, 6);
5012 opcode2
= extract32(insn
, 16, 5);
5013 rn
= extract32(insn
, 5, 5);
5014 rd
= extract32(insn
, 0, 5);
5016 #define MAP(SF, O2, O1) ((SF) | (O1 << 1) | (O2 << 7))
5018 switch (MAP(sf
, opcode2
, opcode
)) {
5019 case MAP(0, 0x00, 0x00): /* RBIT */
5020 case MAP(1, 0x00, 0x00):
5021 handle_rbit(s
, sf
, rn
, rd
);
5023 case MAP(0, 0x00, 0x01): /* REV16 */
5024 case MAP(1, 0x00, 0x01):
5025 handle_rev16(s
, sf
, rn
, rd
);
5027 case MAP(0, 0x00, 0x02): /* REV/REV32 */
5028 case MAP(1, 0x00, 0x02):
5029 handle_rev32(s
, sf
, rn
, rd
);
5031 case MAP(1, 0x00, 0x03): /* REV64 */
5032 handle_rev64(s
, sf
, rn
, rd
);
5034 case MAP(0, 0x00, 0x04): /* CLZ */
5035 case MAP(1, 0x00, 0x04):
5036 handle_clz(s
, sf
, rn
, rd
);
5038 case MAP(0, 0x00, 0x05): /* CLS */
5039 case MAP(1, 0x00, 0x05):
5040 handle_cls(s
, sf
, rn
, rd
);
5042 case MAP(1, 0x01, 0x00): /* PACIA */
5043 if (s
->pauth_active
) {
5044 tcg_rd
= cpu_reg(s
, rd
);
5045 gen_helper_pacia(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5046 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5047 goto do_unallocated
;
5050 case MAP(1, 0x01, 0x01): /* PACIB */
5051 if (s
->pauth_active
) {
5052 tcg_rd
= cpu_reg(s
, rd
);
5053 gen_helper_pacib(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5054 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5055 goto do_unallocated
;
5058 case MAP(1, 0x01, 0x02): /* PACDA */
5059 if (s
->pauth_active
) {
5060 tcg_rd
= cpu_reg(s
, rd
);
5061 gen_helper_pacda(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5062 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5063 goto do_unallocated
;
5066 case MAP(1, 0x01, 0x03): /* PACDB */
5067 if (s
->pauth_active
) {
5068 tcg_rd
= cpu_reg(s
, rd
);
5069 gen_helper_pacdb(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5070 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5071 goto do_unallocated
;
5074 case MAP(1, 0x01, 0x04): /* AUTIA */
5075 if (s
->pauth_active
) {
5076 tcg_rd
= cpu_reg(s
, rd
);
5077 gen_helper_autia(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5078 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5079 goto do_unallocated
;
5082 case MAP(1, 0x01, 0x05): /* AUTIB */
5083 if (s
->pauth_active
) {
5084 tcg_rd
= cpu_reg(s
, rd
);
5085 gen_helper_autib(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5086 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5087 goto do_unallocated
;
5090 case MAP(1, 0x01, 0x06): /* AUTDA */
5091 if (s
->pauth_active
) {
5092 tcg_rd
= cpu_reg(s
, rd
);
5093 gen_helper_autda(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5094 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5095 goto do_unallocated
;
5098 case MAP(1, 0x01, 0x07): /* AUTDB */
5099 if (s
->pauth_active
) {
5100 tcg_rd
= cpu_reg(s
, rd
);
5101 gen_helper_autdb(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5102 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5103 goto do_unallocated
;
5106 case MAP(1, 0x01, 0x08): /* PACIZA */
5107 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5108 goto do_unallocated
;
5109 } else if (s
->pauth_active
) {
5110 tcg_rd
= cpu_reg(s
, rd
);
5111 gen_helper_pacia(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5114 case MAP(1, 0x01, 0x09): /* PACIZB */
5115 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5116 goto do_unallocated
;
5117 } else if (s
->pauth_active
) {
5118 tcg_rd
= cpu_reg(s
, rd
);
5119 gen_helper_pacib(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5122 case MAP(1, 0x01, 0x0a): /* PACDZA */
5123 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5124 goto do_unallocated
;
5125 } else if (s
->pauth_active
) {
5126 tcg_rd
= cpu_reg(s
, rd
);
5127 gen_helper_pacda(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5130 case MAP(1, 0x01, 0x0b): /* PACDZB */
5131 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5132 goto do_unallocated
;
5133 } else if (s
->pauth_active
) {
5134 tcg_rd
= cpu_reg(s
, rd
);
5135 gen_helper_pacdb(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5138 case MAP(1, 0x01, 0x0c): /* AUTIZA */
5139 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5140 goto do_unallocated
;
5141 } else if (s
->pauth_active
) {
5142 tcg_rd
= cpu_reg(s
, rd
);
5143 gen_helper_autia(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5146 case MAP(1, 0x01, 0x0d): /* AUTIZB */
5147 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5148 goto do_unallocated
;
5149 } else if (s
->pauth_active
) {
5150 tcg_rd
= cpu_reg(s
, rd
);
5151 gen_helper_autib(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5154 case MAP(1, 0x01, 0x0e): /* AUTDZA */
5155 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5156 goto do_unallocated
;
5157 } else if (s
->pauth_active
) {
5158 tcg_rd
= cpu_reg(s
, rd
);
5159 gen_helper_autda(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5162 case MAP(1, 0x01, 0x0f): /* AUTDZB */
5163 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5164 goto do_unallocated
;
5165 } else if (s
->pauth_active
) {
5166 tcg_rd
= cpu_reg(s
, rd
);
5167 gen_helper_autdb(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5170 case MAP(1, 0x01, 0x10): /* XPACI */
5171 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5172 goto do_unallocated
;
5173 } else if (s
->pauth_active
) {
5174 tcg_rd
= cpu_reg(s
, rd
);
5175 gen_helper_xpaci(tcg_rd
, cpu_env
, tcg_rd
);
5178 case MAP(1, 0x01, 0x11): /* XPACD */
5179 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5180 goto do_unallocated
;
5181 } else if (s
->pauth_active
) {
5182 tcg_rd
= cpu_reg(s
, rd
);
5183 gen_helper_xpacd(tcg_rd
, cpu_env
, tcg_rd
);
5188 unallocated_encoding(s
);
5195 static void handle_div(DisasContext
*s
, bool is_signed
, unsigned int sf
,
5196 unsigned int rm
, unsigned int rn
, unsigned int rd
)
5198 TCGv_i64 tcg_n
, tcg_m
, tcg_rd
;
5199 tcg_rd
= cpu_reg(s
, rd
);
5201 if (!sf
&& is_signed
) {
5202 tcg_n
= new_tmp_a64(s
);
5203 tcg_m
= new_tmp_a64(s
);
5204 tcg_gen_ext32s_i64(tcg_n
, cpu_reg(s
, rn
));
5205 tcg_gen_ext32s_i64(tcg_m
, cpu_reg(s
, rm
));
5207 tcg_n
= read_cpu_reg(s
, rn
, sf
);
5208 tcg_m
= read_cpu_reg(s
, rm
, sf
);
5212 gen_helper_sdiv64(tcg_rd
, tcg_n
, tcg_m
);
5214 gen_helper_udiv64(tcg_rd
, tcg_n
, tcg_m
);
5217 if (!sf
) { /* zero extend final result */
5218 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
5222 /* LSLV, LSRV, ASRV, RORV */
5223 static void handle_shift_reg(DisasContext
*s
,
5224 enum a64_shift_type shift_type
, unsigned int sf
,
5225 unsigned int rm
, unsigned int rn
, unsigned int rd
)
5227 TCGv_i64 tcg_shift
= tcg_temp_new_i64();
5228 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
5229 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
5231 tcg_gen_andi_i64(tcg_shift
, cpu_reg(s
, rm
), sf
? 63 : 31);
5232 shift_reg(tcg_rd
, tcg_rn
, sf
, shift_type
, tcg_shift
);
5233 tcg_temp_free_i64(tcg_shift
);
5236 /* CRC32[BHWX], CRC32C[BHWX] */
5237 static void handle_crc32(DisasContext
*s
,
5238 unsigned int sf
, unsigned int sz
, bool crc32c
,
5239 unsigned int rm
, unsigned int rn
, unsigned int rd
)
5241 TCGv_i64 tcg_acc
, tcg_val
;
5244 if (!dc_isar_feature(aa64_crc32
, s
)
5245 || (sf
== 1 && sz
!= 3)
5246 || (sf
== 0 && sz
== 3)) {
5247 unallocated_encoding(s
);
5252 tcg_val
= cpu_reg(s
, rm
);
5266 g_assert_not_reached();
5268 tcg_val
= new_tmp_a64(s
);
5269 tcg_gen_andi_i64(tcg_val
, cpu_reg(s
, rm
), mask
);
5272 tcg_acc
= cpu_reg(s
, rn
);
5273 tcg_bytes
= tcg_const_i32(1 << sz
);
5276 gen_helper_crc32c_64(cpu_reg(s
, rd
), tcg_acc
, tcg_val
, tcg_bytes
);
5278 gen_helper_crc32_64(cpu_reg(s
, rd
), tcg_acc
, tcg_val
, tcg_bytes
);
5281 tcg_temp_free_i32(tcg_bytes
);
5284 /* Data-processing (2 source)
5285 * 31 30 29 28 21 20 16 15 10 9 5 4 0
5286 * +----+---+---+-----------------+------+--------+------+------+
5287 * | sf | 0 | S | 1 1 0 1 0 1 1 0 | Rm | opcode | Rn | Rd |
5288 * +----+---+---+-----------------+------+--------+------+------+
5290 static void disas_data_proc_2src(DisasContext
*s
, uint32_t insn
)
5292 unsigned int sf
, rm
, opcode
, rn
, rd
;
5293 sf
= extract32(insn
, 31, 1);
5294 rm
= extract32(insn
, 16, 5);
5295 opcode
= extract32(insn
, 10, 6);
5296 rn
= extract32(insn
, 5, 5);
5297 rd
= extract32(insn
, 0, 5);
5299 if (extract32(insn
, 29, 1)) {
5300 unallocated_encoding(s
);
5306 handle_div(s
, false, sf
, rm
, rn
, rd
);
5309 handle_div(s
, true, sf
, rm
, rn
, rd
);
5312 handle_shift_reg(s
, A64_SHIFT_TYPE_LSL
, sf
, rm
, rn
, rd
);
5315 handle_shift_reg(s
, A64_SHIFT_TYPE_LSR
, sf
, rm
, rn
, rd
);
5318 handle_shift_reg(s
, A64_SHIFT_TYPE_ASR
, sf
, rm
, rn
, rd
);
5321 handle_shift_reg(s
, A64_SHIFT_TYPE_ROR
, sf
, rm
, rn
, rd
);
5323 case 12: /* PACGA */
5324 if (sf
== 0 || !dc_isar_feature(aa64_pauth
, s
)) {
5325 goto do_unallocated
;
5327 gen_helper_pacga(cpu_reg(s
, rd
), cpu_env
,
5328 cpu_reg(s
, rn
), cpu_reg_sp(s
, rm
));
5337 case 23: /* CRC32 */
5339 int sz
= extract32(opcode
, 0, 2);
5340 bool crc32c
= extract32(opcode
, 2, 1);
5341 handle_crc32(s
, sf
, sz
, crc32c
, rm
, rn
, rd
);
5346 unallocated_encoding(s
);
5352 * Data processing - register
5353 * 31 30 29 28 25 21 20 16 10 0
5354 * +--+---+--+---+-------+-----+-------+-------+---------+
5355 * | |op0| |op1| 1 0 1 | op2 | | op3 | |
5356 * +--+---+--+---+-------+-----+-------+-------+---------+
5358 static void disas_data_proc_reg(DisasContext
*s
, uint32_t insn
)
5360 int op0
= extract32(insn
, 30, 1);
5361 int op1
= extract32(insn
, 28, 1);
5362 int op2
= extract32(insn
, 21, 4);
5363 int op3
= extract32(insn
, 10, 6);
5368 /* Add/sub (extended register) */
5369 disas_add_sub_ext_reg(s
, insn
);
5371 /* Add/sub (shifted register) */
5372 disas_add_sub_reg(s
, insn
);
5375 /* Logical (shifted register) */
5376 disas_logic_reg(s
, insn
);
5384 case 0x00: /* Add/subtract (with carry) */
5385 disas_adc_sbc(s
, insn
);
5388 case 0x01: /* Rotate right into flags */
5390 disas_rotate_right_into_flags(s
, insn
);
5393 case 0x02: /* Evaluate into flags */
5397 disas_evaluate_into_flags(s
, insn
);
5401 goto do_unallocated
;
5405 case 0x2: /* Conditional compare */
5406 disas_cc(s
, insn
); /* both imm and reg forms */
5409 case 0x4: /* Conditional select */
5410 disas_cond_select(s
, insn
);
5413 case 0x6: /* Data-processing */
5414 if (op0
) { /* (1 source) */
5415 disas_data_proc_1src(s
, insn
);
5416 } else { /* (2 source) */
5417 disas_data_proc_2src(s
, insn
);
5420 case 0x8 ... 0xf: /* (3 source) */
5421 disas_data_proc_3src(s
, insn
);
5426 unallocated_encoding(s
);
5431 static void handle_fp_compare(DisasContext
*s
, int size
,
5432 unsigned int rn
, unsigned int rm
,
5433 bool cmp_with_zero
, bool signal_all_nans
)
5435 TCGv_i64 tcg_flags
= tcg_temp_new_i64();
5436 TCGv_ptr fpst
= get_fpstatus_ptr(size
== MO_16
);
5438 if (size
== MO_64
) {
5439 TCGv_i64 tcg_vn
, tcg_vm
;
5441 tcg_vn
= read_fp_dreg(s
, rn
);
5442 if (cmp_with_zero
) {
5443 tcg_vm
= tcg_const_i64(0);
5445 tcg_vm
= read_fp_dreg(s
, rm
);
5447 if (signal_all_nans
) {
5448 gen_helper_vfp_cmped_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5450 gen_helper_vfp_cmpd_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5452 tcg_temp_free_i64(tcg_vn
);
5453 tcg_temp_free_i64(tcg_vm
);
5455 TCGv_i32 tcg_vn
= tcg_temp_new_i32();
5456 TCGv_i32 tcg_vm
= tcg_temp_new_i32();
5458 read_vec_element_i32(s
, tcg_vn
, rn
, 0, size
);
5459 if (cmp_with_zero
) {
5460 tcg_gen_movi_i32(tcg_vm
, 0);
5462 read_vec_element_i32(s
, tcg_vm
, rm
, 0, size
);
5467 if (signal_all_nans
) {
5468 gen_helper_vfp_cmpes_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5470 gen_helper_vfp_cmps_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5474 if (signal_all_nans
) {
5475 gen_helper_vfp_cmpeh_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5477 gen_helper_vfp_cmph_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5481 g_assert_not_reached();
5484 tcg_temp_free_i32(tcg_vn
);
5485 tcg_temp_free_i32(tcg_vm
);
5488 tcg_temp_free_ptr(fpst
);
5490 gen_set_nzcv(tcg_flags
);
5492 tcg_temp_free_i64(tcg_flags
);
5495 /* Floating point compare
5496 * 31 30 29 28 24 23 22 21 20 16 15 14 13 10 9 5 4 0
5497 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
5498 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | op | 1 0 0 0 | Rn | op2 |
5499 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
5501 static void disas_fp_compare(DisasContext
*s
, uint32_t insn
)
5503 unsigned int mos
, type
, rm
, op
, rn
, opc
, op2r
;
5506 mos
= extract32(insn
, 29, 3);
5507 type
= extract32(insn
, 22, 2);
5508 rm
= extract32(insn
, 16, 5);
5509 op
= extract32(insn
, 14, 2);
5510 rn
= extract32(insn
, 5, 5);
5511 opc
= extract32(insn
, 3, 2);
5512 op2r
= extract32(insn
, 0, 3);
5514 if (mos
|| op
|| op2r
) {
5515 unallocated_encoding(s
);
5528 if (dc_isar_feature(aa64_fp16
, s
)) {
5533 unallocated_encoding(s
);
5537 if (!fp_access_check(s
)) {
5541 handle_fp_compare(s
, size
, rn
, rm
, opc
& 1, opc
& 2);
5544 /* Floating point conditional compare
5545 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
5546 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
5547 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 0 1 | Rn | op | nzcv |
5548 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
5550 static void disas_fp_ccomp(DisasContext
*s
, uint32_t insn
)
5552 unsigned int mos
, type
, rm
, cond
, rn
, op
, nzcv
;
5554 TCGLabel
*label_continue
= NULL
;
5557 mos
= extract32(insn
, 29, 3);
5558 type
= extract32(insn
, 22, 2);
5559 rm
= extract32(insn
, 16, 5);
5560 cond
= extract32(insn
, 12, 4);
5561 rn
= extract32(insn
, 5, 5);
5562 op
= extract32(insn
, 4, 1);
5563 nzcv
= extract32(insn
, 0, 4);
5566 unallocated_encoding(s
);
5579 if (dc_isar_feature(aa64_fp16
, s
)) {
5584 unallocated_encoding(s
);
5588 if (!fp_access_check(s
)) {
5592 if (cond
< 0x0e) { /* not always */
5593 TCGLabel
*label_match
= gen_new_label();
5594 label_continue
= gen_new_label();
5595 arm_gen_test_cc(cond
, label_match
);
5597 tcg_flags
= tcg_const_i64(nzcv
<< 28);
5598 gen_set_nzcv(tcg_flags
);
5599 tcg_temp_free_i64(tcg_flags
);
5600 tcg_gen_br(label_continue
);
5601 gen_set_label(label_match
);
5604 handle_fp_compare(s
, size
, rn
, rm
, false, op
);
5607 gen_set_label(label_continue
);
5611 /* Floating point conditional select
5612 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
5613 * +---+---+---+-----------+------+---+------+------+-----+------+------+
5614 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 1 1 | Rn | Rd |
5615 * +---+---+---+-----------+------+---+------+------+-----+------+------+
5617 static void disas_fp_csel(DisasContext
*s
, uint32_t insn
)
5619 unsigned int mos
, type
, rm
, cond
, rn
, rd
;
5620 TCGv_i64 t_true
, t_false
, t_zero
;
5624 mos
= extract32(insn
, 29, 3);
5625 type
= extract32(insn
, 22, 2);
5626 rm
= extract32(insn
, 16, 5);
5627 cond
= extract32(insn
, 12, 4);
5628 rn
= extract32(insn
, 5, 5);
5629 rd
= extract32(insn
, 0, 5);
5632 unallocated_encoding(s
);
5645 if (dc_isar_feature(aa64_fp16
, s
)) {
5650 unallocated_encoding(s
);
5654 if (!fp_access_check(s
)) {
5658 /* Zero extend sreg & hreg inputs to 64 bits now. */
5659 t_true
= tcg_temp_new_i64();
5660 t_false
= tcg_temp_new_i64();
5661 read_vec_element(s
, t_true
, rn
, 0, sz
);
5662 read_vec_element(s
, t_false
, rm
, 0, sz
);
5664 a64_test_cc(&c
, cond
);
5665 t_zero
= tcg_const_i64(0);
5666 tcg_gen_movcond_i64(c
.cond
, t_true
, c
.value
, t_zero
, t_true
, t_false
);
5667 tcg_temp_free_i64(t_zero
);
5668 tcg_temp_free_i64(t_false
);
5671 /* Note that sregs & hregs write back zeros to the high bits,
5672 and we've already done the zero-extension. */
5673 write_fp_dreg(s
, rd
, t_true
);
5674 tcg_temp_free_i64(t_true
);
5677 /* Floating-point data-processing (1 source) - half precision */
5678 static void handle_fp_1src_half(DisasContext
*s
, int opcode
, int rd
, int rn
)
5680 TCGv_ptr fpst
= NULL
;
5681 TCGv_i32 tcg_op
= read_fp_hreg(s
, rn
);
5682 TCGv_i32 tcg_res
= tcg_temp_new_i32();
5685 case 0x0: /* FMOV */
5686 tcg_gen_mov_i32(tcg_res
, tcg_op
);
5688 case 0x1: /* FABS */
5689 tcg_gen_andi_i32(tcg_res
, tcg_op
, 0x7fff);
5691 case 0x2: /* FNEG */
5692 tcg_gen_xori_i32(tcg_res
, tcg_op
, 0x8000);
5694 case 0x3: /* FSQRT */
5695 fpst
= get_fpstatus_ptr(true);
5696 gen_helper_sqrt_f16(tcg_res
, tcg_op
, fpst
);
5698 case 0x8: /* FRINTN */
5699 case 0x9: /* FRINTP */
5700 case 0xa: /* FRINTM */
5701 case 0xb: /* FRINTZ */
5702 case 0xc: /* FRINTA */
5704 TCGv_i32 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(opcode
& 7));
5705 fpst
= get_fpstatus_ptr(true);
5707 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5708 gen_helper_advsimd_rinth(tcg_res
, tcg_op
, fpst
);
5710 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5711 tcg_temp_free_i32(tcg_rmode
);
5714 case 0xe: /* FRINTX */
5715 fpst
= get_fpstatus_ptr(true);
5716 gen_helper_advsimd_rinth_exact(tcg_res
, tcg_op
, fpst
);
5718 case 0xf: /* FRINTI */
5719 fpst
= get_fpstatus_ptr(true);
5720 gen_helper_advsimd_rinth(tcg_res
, tcg_op
, fpst
);
5726 write_fp_sreg(s
, rd
, tcg_res
);
5729 tcg_temp_free_ptr(fpst
);
5731 tcg_temp_free_i32(tcg_op
);
5732 tcg_temp_free_i32(tcg_res
);
5735 /* Floating-point data-processing (1 source) - single precision */
5736 static void handle_fp_1src_single(DisasContext
*s
, int opcode
, int rd
, int rn
)
5738 void (*gen_fpst
)(TCGv_i32
, TCGv_i32
, TCGv_ptr
);
5739 TCGv_i32 tcg_op
, tcg_res
;
5743 tcg_op
= read_fp_sreg(s
, rn
);
5744 tcg_res
= tcg_temp_new_i32();
5747 case 0x0: /* FMOV */
5748 tcg_gen_mov_i32(tcg_res
, tcg_op
);
5750 case 0x1: /* FABS */
5751 gen_helper_vfp_abss(tcg_res
, tcg_op
);
5753 case 0x2: /* FNEG */
5754 gen_helper_vfp_negs(tcg_res
, tcg_op
);
5756 case 0x3: /* FSQRT */
5757 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
5759 case 0x8: /* FRINTN */
5760 case 0x9: /* FRINTP */
5761 case 0xa: /* FRINTM */
5762 case 0xb: /* FRINTZ */
5763 case 0xc: /* FRINTA */
5764 rmode
= arm_rmode_to_sf(opcode
& 7);
5765 gen_fpst
= gen_helper_rints
;
5767 case 0xe: /* FRINTX */
5768 gen_fpst
= gen_helper_rints_exact
;
5770 case 0xf: /* FRINTI */
5771 gen_fpst
= gen_helper_rints
;
5773 case 0x10: /* FRINT32Z */
5774 rmode
= float_round_to_zero
;
5775 gen_fpst
= gen_helper_frint32_s
;
5777 case 0x11: /* FRINT32X */
5778 gen_fpst
= gen_helper_frint32_s
;
5780 case 0x12: /* FRINT64Z */
5781 rmode
= float_round_to_zero
;
5782 gen_fpst
= gen_helper_frint64_s
;
5784 case 0x13: /* FRINT64X */
5785 gen_fpst
= gen_helper_frint64_s
;
5788 g_assert_not_reached();
5791 fpst
= get_fpstatus_ptr(false);
5793 TCGv_i32 tcg_rmode
= tcg_const_i32(rmode
);
5794 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5795 gen_fpst(tcg_res
, tcg_op
, fpst
);
5796 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5797 tcg_temp_free_i32(tcg_rmode
);
5799 gen_fpst(tcg_res
, tcg_op
, fpst
);
5801 tcg_temp_free_ptr(fpst
);
5804 write_fp_sreg(s
, rd
, tcg_res
);
5805 tcg_temp_free_i32(tcg_op
);
5806 tcg_temp_free_i32(tcg_res
);
5809 /* Floating-point data-processing (1 source) - double precision */
5810 static void handle_fp_1src_double(DisasContext
*s
, int opcode
, int rd
, int rn
)
5812 void (*gen_fpst
)(TCGv_i64
, TCGv_i64
, TCGv_ptr
);
5813 TCGv_i64 tcg_op
, tcg_res
;
5818 case 0x0: /* FMOV */
5819 gen_gvec_fn2(s
, false, rd
, rn
, tcg_gen_gvec_mov
, 0);
5823 tcg_op
= read_fp_dreg(s
, rn
);
5824 tcg_res
= tcg_temp_new_i64();
5827 case 0x1: /* FABS */
5828 gen_helper_vfp_absd(tcg_res
, tcg_op
);
5830 case 0x2: /* FNEG */
5831 gen_helper_vfp_negd(tcg_res
, tcg_op
);
5833 case 0x3: /* FSQRT */
5834 gen_helper_vfp_sqrtd(tcg_res
, tcg_op
, cpu_env
);
5836 case 0x8: /* FRINTN */
5837 case 0x9: /* FRINTP */
5838 case 0xa: /* FRINTM */
5839 case 0xb: /* FRINTZ */
5840 case 0xc: /* FRINTA */
5841 rmode
= arm_rmode_to_sf(opcode
& 7);
5842 gen_fpst
= gen_helper_rintd
;
5844 case 0xe: /* FRINTX */
5845 gen_fpst
= gen_helper_rintd_exact
;
5847 case 0xf: /* FRINTI */
5848 gen_fpst
= gen_helper_rintd
;
5850 case 0x10: /* FRINT32Z */
5851 rmode
= float_round_to_zero
;
5852 gen_fpst
= gen_helper_frint32_d
;
5854 case 0x11: /* FRINT32X */
5855 gen_fpst
= gen_helper_frint32_d
;
5857 case 0x12: /* FRINT64Z */
5858 rmode
= float_round_to_zero
;
5859 gen_fpst
= gen_helper_frint64_d
;
5861 case 0x13: /* FRINT64X */
5862 gen_fpst
= gen_helper_frint64_d
;
5865 g_assert_not_reached();
5868 fpst
= get_fpstatus_ptr(false);
5870 TCGv_i32 tcg_rmode
= tcg_const_i32(rmode
);
5871 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5872 gen_fpst(tcg_res
, tcg_op
, fpst
);
5873 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5874 tcg_temp_free_i32(tcg_rmode
);
5876 gen_fpst(tcg_res
, tcg_op
, fpst
);
5878 tcg_temp_free_ptr(fpst
);
5881 write_fp_dreg(s
, rd
, tcg_res
);
5882 tcg_temp_free_i64(tcg_op
);
5883 tcg_temp_free_i64(tcg_res
);
5886 static void handle_fp_fcvt(DisasContext
*s
, int opcode
,
5887 int rd
, int rn
, int dtype
, int ntype
)
5892 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
5894 /* Single to double */
5895 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
5896 gen_helper_vfp_fcvtds(tcg_rd
, tcg_rn
, cpu_env
);
5897 write_fp_dreg(s
, rd
, tcg_rd
);
5898 tcg_temp_free_i64(tcg_rd
);
5900 /* Single to half */
5901 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
5902 TCGv_i32 ahp
= get_ahp_flag();
5903 TCGv_ptr fpst
= get_fpstatus_ptr(false);
5905 gen_helper_vfp_fcvt_f32_to_f16(tcg_rd
, tcg_rn
, fpst
, ahp
);
5906 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
5907 write_fp_sreg(s
, rd
, tcg_rd
);
5908 tcg_temp_free_i32(tcg_rd
);
5909 tcg_temp_free_i32(ahp
);
5910 tcg_temp_free_ptr(fpst
);
5912 tcg_temp_free_i32(tcg_rn
);
5917 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
5918 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
5920 /* Double to single */
5921 gen_helper_vfp_fcvtsd(tcg_rd
, tcg_rn
, cpu_env
);
5923 TCGv_ptr fpst
= get_fpstatus_ptr(false);
5924 TCGv_i32 ahp
= get_ahp_flag();
5925 /* Double to half */
5926 gen_helper_vfp_fcvt_f64_to_f16(tcg_rd
, tcg_rn
, fpst
, ahp
);
5927 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
5928 tcg_temp_free_ptr(fpst
);
5929 tcg_temp_free_i32(ahp
);
5931 write_fp_sreg(s
, rd
, tcg_rd
);
5932 tcg_temp_free_i32(tcg_rd
);
5933 tcg_temp_free_i64(tcg_rn
);
5938 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
5939 TCGv_ptr tcg_fpst
= get_fpstatus_ptr(false);
5940 TCGv_i32 tcg_ahp
= get_ahp_flag();
5941 tcg_gen_ext16u_i32(tcg_rn
, tcg_rn
);
5943 /* Half to single */
5944 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
5945 gen_helper_vfp_fcvt_f16_to_f32(tcg_rd
, tcg_rn
, tcg_fpst
, tcg_ahp
);
5946 write_fp_sreg(s
, rd
, tcg_rd
);
5947 tcg_temp_free_i32(tcg_rd
);
5949 /* Half to double */
5950 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
5951 gen_helper_vfp_fcvt_f16_to_f64(tcg_rd
, tcg_rn
, tcg_fpst
, tcg_ahp
);
5952 write_fp_dreg(s
, rd
, tcg_rd
);
5953 tcg_temp_free_i64(tcg_rd
);
5955 tcg_temp_free_i32(tcg_rn
);
5956 tcg_temp_free_ptr(tcg_fpst
);
5957 tcg_temp_free_i32(tcg_ahp
);
5965 /* Floating point data-processing (1 source)
5966 * 31 30 29 28 24 23 22 21 20 15 14 10 9 5 4 0
5967 * +---+---+---+-----------+------+---+--------+-----------+------+------+
5968 * | M | 0 | S | 1 1 1 1 0 | type | 1 | opcode | 1 0 0 0 0 | Rn | Rd |
5969 * +---+---+---+-----------+------+---+--------+-----------+------+------+
5971 static void disas_fp_1src(DisasContext
*s
, uint32_t insn
)
5973 int mos
= extract32(insn
, 29, 3);
5974 int type
= extract32(insn
, 22, 2);
5975 int opcode
= extract32(insn
, 15, 6);
5976 int rn
= extract32(insn
, 5, 5);
5977 int rd
= extract32(insn
, 0, 5);
5980 unallocated_encoding(s
);
5985 case 0x4: case 0x5: case 0x7:
5987 /* FCVT between half, single and double precision */
5988 int dtype
= extract32(opcode
, 0, 2);
5989 if (type
== 2 || dtype
== type
) {
5990 unallocated_encoding(s
);
5993 if (!fp_access_check(s
)) {
5997 handle_fp_fcvt(s
, opcode
, rd
, rn
, dtype
, type
);
6001 case 0x10 ... 0x13: /* FRINT{32,64}{X,Z} */
6002 if (type
> 1 || !dc_isar_feature(aa64_frint
, s
)) {
6003 unallocated_encoding(s
);
6010 /* 32-to-32 and 64-to-64 ops */
6013 if (!fp_access_check(s
)) {
6016 handle_fp_1src_single(s
, opcode
, rd
, rn
);
6019 if (!fp_access_check(s
)) {
6022 handle_fp_1src_double(s
, opcode
, rd
, rn
);
6025 if (!dc_isar_feature(aa64_fp16
, s
)) {
6026 unallocated_encoding(s
);
6030 if (!fp_access_check(s
)) {
6033 handle_fp_1src_half(s
, opcode
, rd
, rn
);
6036 unallocated_encoding(s
);
6041 unallocated_encoding(s
);
6046 /* Floating-point data-processing (2 source) - single precision */
6047 static void handle_fp_2src_single(DisasContext
*s
, int opcode
,
6048 int rd
, int rn
, int rm
)
6055 tcg_res
= tcg_temp_new_i32();
6056 fpst
= get_fpstatus_ptr(false);
6057 tcg_op1
= read_fp_sreg(s
, rn
);
6058 tcg_op2
= read_fp_sreg(s
, rm
);
6061 case 0x0: /* FMUL */
6062 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6064 case 0x1: /* FDIV */
6065 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6067 case 0x2: /* FADD */
6068 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6070 case 0x3: /* FSUB */
6071 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6073 case 0x4: /* FMAX */
6074 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6076 case 0x5: /* FMIN */
6077 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6079 case 0x6: /* FMAXNM */
6080 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6082 case 0x7: /* FMINNM */
6083 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6085 case 0x8: /* FNMUL */
6086 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6087 gen_helper_vfp_negs(tcg_res
, tcg_res
);
6091 write_fp_sreg(s
, rd
, tcg_res
);
6093 tcg_temp_free_ptr(fpst
);
6094 tcg_temp_free_i32(tcg_op1
);
6095 tcg_temp_free_i32(tcg_op2
);
6096 tcg_temp_free_i32(tcg_res
);
6099 /* Floating-point data-processing (2 source) - double precision */
6100 static void handle_fp_2src_double(DisasContext
*s
, int opcode
,
6101 int rd
, int rn
, int rm
)
6108 tcg_res
= tcg_temp_new_i64();
6109 fpst
= get_fpstatus_ptr(false);
6110 tcg_op1
= read_fp_dreg(s
, rn
);
6111 tcg_op2
= read_fp_dreg(s
, rm
);
6114 case 0x0: /* FMUL */
6115 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6117 case 0x1: /* FDIV */
6118 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6120 case 0x2: /* FADD */
6121 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6123 case 0x3: /* FSUB */
6124 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6126 case 0x4: /* FMAX */
6127 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6129 case 0x5: /* FMIN */
6130 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6132 case 0x6: /* FMAXNM */
6133 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6135 case 0x7: /* FMINNM */
6136 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6138 case 0x8: /* FNMUL */
6139 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6140 gen_helper_vfp_negd(tcg_res
, tcg_res
);
6144 write_fp_dreg(s
, rd
, tcg_res
);
6146 tcg_temp_free_ptr(fpst
);
6147 tcg_temp_free_i64(tcg_op1
);
6148 tcg_temp_free_i64(tcg_op2
);
6149 tcg_temp_free_i64(tcg_res
);
6152 /* Floating-point data-processing (2 source) - half precision */
6153 static void handle_fp_2src_half(DisasContext
*s
, int opcode
,
6154 int rd
, int rn
, int rm
)
6161 tcg_res
= tcg_temp_new_i32();
6162 fpst
= get_fpstatus_ptr(true);
6163 tcg_op1
= read_fp_hreg(s
, rn
);
6164 tcg_op2
= read_fp_hreg(s
, rm
);
6167 case 0x0: /* FMUL */
6168 gen_helper_advsimd_mulh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6170 case 0x1: /* FDIV */
6171 gen_helper_advsimd_divh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6173 case 0x2: /* FADD */
6174 gen_helper_advsimd_addh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6176 case 0x3: /* FSUB */
6177 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6179 case 0x4: /* FMAX */
6180 gen_helper_advsimd_maxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6182 case 0x5: /* FMIN */
6183 gen_helper_advsimd_minh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6185 case 0x6: /* FMAXNM */
6186 gen_helper_advsimd_maxnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6188 case 0x7: /* FMINNM */
6189 gen_helper_advsimd_minnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6191 case 0x8: /* FNMUL */
6192 gen_helper_advsimd_mulh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6193 tcg_gen_xori_i32(tcg_res
, tcg_res
, 0x8000);
6196 g_assert_not_reached();
6199 write_fp_sreg(s
, rd
, tcg_res
);
6201 tcg_temp_free_ptr(fpst
);
6202 tcg_temp_free_i32(tcg_op1
);
6203 tcg_temp_free_i32(tcg_op2
);
6204 tcg_temp_free_i32(tcg_res
);
6207 /* Floating point data-processing (2 source)
6208 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
6209 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
6210 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | opcode | 1 0 | Rn | Rd |
6211 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
6213 static void disas_fp_2src(DisasContext
*s
, uint32_t insn
)
6215 int mos
= extract32(insn
, 29, 3);
6216 int type
= extract32(insn
, 22, 2);
6217 int rd
= extract32(insn
, 0, 5);
6218 int rn
= extract32(insn
, 5, 5);
6219 int rm
= extract32(insn
, 16, 5);
6220 int opcode
= extract32(insn
, 12, 4);
6222 if (opcode
> 8 || mos
) {
6223 unallocated_encoding(s
);
6229 if (!fp_access_check(s
)) {
6232 handle_fp_2src_single(s
, opcode
, rd
, rn
, rm
);
6235 if (!fp_access_check(s
)) {
6238 handle_fp_2src_double(s
, opcode
, rd
, rn
, rm
);
6241 if (!dc_isar_feature(aa64_fp16
, s
)) {
6242 unallocated_encoding(s
);
6245 if (!fp_access_check(s
)) {
6248 handle_fp_2src_half(s
, opcode
, rd
, rn
, rm
);
6251 unallocated_encoding(s
);
6255 /* Floating-point data-processing (3 source) - single precision */
6256 static void handle_fp_3src_single(DisasContext
*s
, bool o0
, bool o1
,
6257 int rd
, int rn
, int rm
, int ra
)
6259 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
;
6260 TCGv_i32 tcg_res
= tcg_temp_new_i32();
6261 TCGv_ptr fpst
= get_fpstatus_ptr(false);
6263 tcg_op1
= read_fp_sreg(s
, rn
);
6264 tcg_op2
= read_fp_sreg(s
, rm
);
6265 tcg_op3
= read_fp_sreg(s
, ra
);
6267 /* These are fused multiply-add, and must be done as one
6268 * floating point operation with no rounding between the
6269 * multiplication and addition steps.
6270 * NB that doing the negations here as separate steps is
6271 * correct : an input NaN should come out with its sign bit
6272 * flipped if it is a negated-input.
6275 gen_helper_vfp_negs(tcg_op3
, tcg_op3
);
6279 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
6282 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
6284 write_fp_sreg(s
, rd
, tcg_res
);
6286 tcg_temp_free_ptr(fpst
);
6287 tcg_temp_free_i32(tcg_op1
);
6288 tcg_temp_free_i32(tcg_op2
);
6289 tcg_temp_free_i32(tcg_op3
);
6290 tcg_temp_free_i32(tcg_res
);
6293 /* Floating-point data-processing (3 source) - double precision */
6294 static void handle_fp_3src_double(DisasContext
*s
, bool o0
, bool o1
,
6295 int rd
, int rn
, int rm
, int ra
)
6297 TCGv_i64 tcg_op1
, tcg_op2
, tcg_op3
;
6298 TCGv_i64 tcg_res
= tcg_temp_new_i64();
6299 TCGv_ptr fpst
= get_fpstatus_ptr(false);
6301 tcg_op1
= read_fp_dreg(s
, rn
);
6302 tcg_op2
= read_fp_dreg(s
, rm
);
6303 tcg_op3
= read_fp_dreg(s
, ra
);
6305 /* These are fused multiply-add, and must be done as one
6306 * floating point operation with no rounding between the
6307 * multiplication and addition steps.
6308 * NB that doing the negations here as separate steps is
6309 * correct : an input NaN should come out with its sign bit
6310 * flipped if it is a negated-input.
6313 gen_helper_vfp_negd(tcg_op3
, tcg_op3
);
6317 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
6320 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
6322 write_fp_dreg(s
, rd
, tcg_res
);
6324 tcg_temp_free_ptr(fpst
);
6325 tcg_temp_free_i64(tcg_op1
);
6326 tcg_temp_free_i64(tcg_op2
);
6327 tcg_temp_free_i64(tcg_op3
);
6328 tcg_temp_free_i64(tcg_res
);
6331 /* Floating-point data-processing (3 source) - half precision */
6332 static void handle_fp_3src_half(DisasContext
*s
, bool o0
, bool o1
,
6333 int rd
, int rn
, int rm
, int ra
)
6335 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
;
6336 TCGv_i32 tcg_res
= tcg_temp_new_i32();
6337 TCGv_ptr fpst
= get_fpstatus_ptr(true);
6339 tcg_op1
= read_fp_hreg(s
, rn
);
6340 tcg_op2
= read_fp_hreg(s
, rm
);
6341 tcg_op3
= read_fp_hreg(s
, ra
);
6343 /* These are fused multiply-add, and must be done as one
6344 * floating point operation with no rounding between the
6345 * multiplication and addition steps.
6346 * NB that doing the negations here as separate steps is
6347 * correct : an input NaN should come out with its sign bit
6348 * flipped if it is a negated-input.
6351 tcg_gen_xori_i32(tcg_op3
, tcg_op3
, 0x8000);
6355 tcg_gen_xori_i32(tcg_op1
, tcg_op1
, 0x8000);
6358 gen_helper_advsimd_muladdh(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
6360 write_fp_sreg(s
, rd
, tcg_res
);
6362 tcg_temp_free_ptr(fpst
);
6363 tcg_temp_free_i32(tcg_op1
);
6364 tcg_temp_free_i32(tcg_op2
);
6365 tcg_temp_free_i32(tcg_op3
);
6366 tcg_temp_free_i32(tcg_res
);
6369 /* Floating point data-processing (3 source)
6370 * 31 30 29 28 24 23 22 21 20 16 15 14 10 9 5 4 0
6371 * +---+---+---+-----------+------+----+------+----+------+------+------+
6372 * | M | 0 | S | 1 1 1 1 1 | type | o1 | Rm | o0 | Ra | Rn | Rd |
6373 * +---+---+---+-----------+------+----+------+----+------+------+------+
6375 static void disas_fp_3src(DisasContext
*s
, uint32_t insn
)
6377 int mos
= extract32(insn
, 29, 3);
6378 int type
= extract32(insn
, 22, 2);
6379 int rd
= extract32(insn
, 0, 5);
6380 int rn
= extract32(insn
, 5, 5);
6381 int ra
= extract32(insn
, 10, 5);
6382 int rm
= extract32(insn
, 16, 5);
6383 bool o0
= extract32(insn
, 15, 1);
6384 bool o1
= extract32(insn
, 21, 1);
6387 unallocated_encoding(s
);
6393 if (!fp_access_check(s
)) {
6396 handle_fp_3src_single(s
, o0
, o1
, rd
, rn
, rm
, ra
);
6399 if (!fp_access_check(s
)) {
6402 handle_fp_3src_double(s
, o0
, o1
, rd
, rn
, rm
, ra
);
6405 if (!dc_isar_feature(aa64_fp16
, s
)) {
6406 unallocated_encoding(s
);
6409 if (!fp_access_check(s
)) {
6412 handle_fp_3src_half(s
, o0
, o1
, rd
, rn
, rm
, ra
);
6415 unallocated_encoding(s
);
6419 /* Floating point immediate
6420 * 31 30 29 28 24 23 22 21 20 13 12 10 9 5 4 0
6421 * +---+---+---+-----------+------+---+------------+-------+------+------+
6422 * | M | 0 | S | 1 1 1 1 0 | type | 1 | imm8 | 1 0 0 | imm5 | Rd |
6423 * +---+---+---+-----------+------+---+------------+-------+------+------+
6425 static void disas_fp_imm(DisasContext
*s
, uint32_t insn
)
6427 int rd
= extract32(insn
, 0, 5);
6428 int imm5
= extract32(insn
, 5, 5);
6429 int imm8
= extract32(insn
, 13, 8);
6430 int type
= extract32(insn
, 22, 2);
6431 int mos
= extract32(insn
, 29, 3);
6437 unallocated_encoding(s
);
6450 if (dc_isar_feature(aa64_fp16
, s
)) {
6455 unallocated_encoding(s
);
6459 if (!fp_access_check(s
)) {
6463 imm
= vfp_expand_imm(sz
, imm8
);
6465 tcg_res
= tcg_const_i64(imm
);
6466 write_fp_dreg(s
, rd
, tcg_res
);
6467 tcg_temp_free_i64(tcg_res
);
6470 /* Handle floating point <=> fixed point conversions. Note that we can
6471 * also deal with fp <=> integer conversions as a special case (scale == 64)
6472 * OPTME: consider handling that special case specially or at least skipping
6473 * the call to scalbn in the helpers for zero shifts.
6475 static void handle_fpfpcvt(DisasContext
*s
, int rd
, int rn
, int opcode
,
6476 bool itof
, int rmode
, int scale
, int sf
, int type
)
6478 bool is_signed
= !(opcode
& 1);
6479 TCGv_ptr tcg_fpstatus
;
6480 TCGv_i32 tcg_shift
, tcg_single
;
6481 TCGv_i64 tcg_double
;
6483 tcg_fpstatus
= get_fpstatus_ptr(type
== 3);
6485 tcg_shift
= tcg_const_i32(64 - scale
);
6488 TCGv_i64 tcg_int
= cpu_reg(s
, rn
);
6490 TCGv_i64 tcg_extend
= new_tmp_a64(s
);
6493 tcg_gen_ext32s_i64(tcg_extend
, tcg_int
);
6495 tcg_gen_ext32u_i64(tcg_extend
, tcg_int
);
6498 tcg_int
= tcg_extend
;
6502 case 1: /* float64 */
6503 tcg_double
= tcg_temp_new_i64();
6505 gen_helper_vfp_sqtod(tcg_double
, tcg_int
,
6506 tcg_shift
, tcg_fpstatus
);
6508 gen_helper_vfp_uqtod(tcg_double
, tcg_int
,
6509 tcg_shift
, tcg_fpstatus
);
6511 write_fp_dreg(s
, rd
, tcg_double
);
6512 tcg_temp_free_i64(tcg_double
);
6515 case 0: /* float32 */
6516 tcg_single
= tcg_temp_new_i32();
6518 gen_helper_vfp_sqtos(tcg_single
, tcg_int
,
6519 tcg_shift
, tcg_fpstatus
);
6521 gen_helper_vfp_uqtos(tcg_single
, tcg_int
,
6522 tcg_shift
, tcg_fpstatus
);
6524 write_fp_sreg(s
, rd
, tcg_single
);
6525 tcg_temp_free_i32(tcg_single
);
6528 case 3: /* float16 */
6529 tcg_single
= tcg_temp_new_i32();
6531 gen_helper_vfp_sqtoh(tcg_single
, tcg_int
,
6532 tcg_shift
, tcg_fpstatus
);
6534 gen_helper_vfp_uqtoh(tcg_single
, tcg_int
,
6535 tcg_shift
, tcg_fpstatus
);
6537 write_fp_sreg(s
, rd
, tcg_single
);
6538 tcg_temp_free_i32(tcg_single
);
6542 g_assert_not_reached();
6545 TCGv_i64 tcg_int
= cpu_reg(s
, rd
);
6548 if (extract32(opcode
, 2, 1)) {
6549 /* There are too many rounding modes to all fit into rmode,
6550 * so FCVTA[US] is a special case.
6552 rmode
= FPROUNDING_TIEAWAY
;
6555 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
6557 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
6560 case 1: /* float64 */
6561 tcg_double
= read_fp_dreg(s
, rn
);
6564 gen_helper_vfp_tosld(tcg_int
, tcg_double
,
6565 tcg_shift
, tcg_fpstatus
);
6567 gen_helper_vfp_tosqd(tcg_int
, tcg_double
,
6568 tcg_shift
, tcg_fpstatus
);
6572 gen_helper_vfp_tould(tcg_int
, tcg_double
,
6573 tcg_shift
, tcg_fpstatus
);
6575 gen_helper_vfp_touqd(tcg_int
, tcg_double
,
6576 tcg_shift
, tcg_fpstatus
);
6580 tcg_gen_ext32u_i64(tcg_int
, tcg_int
);
6582 tcg_temp_free_i64(tcg_double
);
6585 case 0: /* float32 */
6586 tcg_single
= read_fp_sreg(s
, rn
);
6589 gen_helper_vfp_tosqs(tcg_int
, tcg_single
,
6590 tcg_shift
, tcg_fpstatus
);
6592 gen_helper_vfp_touqs(tcg_int
, tcg_single
,
6593 tcg_shift
, tcg_fpstatus
);
6596 TCGv_i32 tcg_dest
= tcg_temp_new_i32();
6598 gen_helper_vfp_tosls(tcg_dest
, tcg_single
,
6599 tcg_shift
, tcg_fpstatus
);
6601 gen_helper_vfp_touls(tcg_dest
, tcg_single
,
6602 tcg_shift
, tcg_fpstatus
);
6604 tcg_gen_extu_i32_i64(tcg_int
, tcg_dest
);
6605 tcg_temp_free_i32(tcg_dest
);
6607 tcg_temp_free_i32(tcg_single
);
6610 case 3: /* float16 */
6611 tcg_single
= read_fp_sreg(s
, rn
);
6614 gen_helper_vfp_tosqh(tcg_int
, tcg_single
,
6615 tcg_shift
, tcg_fpstatus
);
6617 gen_helper_vfp_touqh(tcg_int
, tcg_single
,
6618 tcg_shift
, tcg_fpstatus
);
6621 TCGv_i32 tcg_dest
= tcg_temp_new_i32();
6623 gen_helper_vfp_toslh(tcg_dest
, tcg_single
,
6624 tcg_shift
, tcg_fpstatus
);
6626 gen_helper_vfp_toulh(tcg_dest
, tcg_single
,
6627 tcg_shift
, tcg_fpstatus
);
6629 tcg_gen_extu_i32_i64(tcg_int
, tcg_dest
);
6630 tcg_temp_free_i32(tcg_dest
);
6632 tcg_temp_free_i32(tcg_single
);
6636 g_assert_not_reached();
6639 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
6640 tcg_temp_free_i32(tcg_rmode
);
6643 tcg_temp_free_ptr(tcg_fpstatus
);
6644 tcg_temp_free_i32(tcg_shift
);
6647 /* Floating point <-> fixed point conversions
6648 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
6649 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
6650 * | sf | 0 | S | 1 1 1 1 0 | type | 0 | rmode | opcode | scale | Rn | Rd |
6651 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
6653 static void disas_fp_fixed_conv(DisasContext
*s
, uint32_t insn
)
6655 int rd
= extract32(insn
, 0, 5);
6656 int rn
= extract32(insn
, 5, 5);
6657 int scale
= extract32(insn
, 10, 6);
6658 int opcode
= extract32(insn
, 16, 3);
6659 int rmode
= extract32(insn
, 19, 2);
6660 int type
= extract32(insn
, 22, 2);
6661 bool sbit
= extract32(insn
, 29, 1);
6662 bool sf
= extract32(insn
, 31, 1);
6665 if (sbit
|| (!sf
&& scale
< 32)) {
6666 unallocated_encoding(s
);
6671 case 0: /* float32 */
6672 case 1: /* float64 */
6674 case 3: /* float16 */
6675 if (dc_isar_feature(aa64_fp16
, s
)) {
6680 unallocated_encoding(s
);
6684 switch ((rmode
<< 3) | opcode
) {
6685 case 0x2: /* SCVTF */
6686 case 0x3: /* UCVTF */
6689 case 0x18: /* FCVTZS */
6690 case 0x19: /* FCVTZU */
6694 unallocated_encoding(s
);
6698 if (!fp_access_check(s
)) {
6702 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, FPROUNDING_ZERO
, scale
, sf
, type
);
6705 static void handle_fmov(DisasContext
*s
, int rd
, int rn
, int type
, bool itof
)
6707 /* FMOV: gpr to or from float, double, or top half of quad fp reg,
6708 * without conversion.
6712 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
6718 tmp
= tcg_temp_new_i64();
6719 tcg_gen_ext32u_i64(tmp
, tcg_rn
);
6720 write_fp_dreg(s
, rd
, tmp
);
6721 tcg_temp_free_i64(tmp
);
6725 write_fp_dreg(s
, rd
, tcg_rn
);
6728 /* 64 bit to top half. */
6729 tcg_gen_st_i64(tcg_rn
, cpu_env
, fp_reg_hi_offset(s
, rd
));
6730 clear_vec_high(s
, true, rd
);
6734 tmp
= tcg_temp_new_i64();
6735 tcg_gen_ext16u_i64(tmp
, tcg_rn
);
6736 write_fp_dreg(s
, rd
, tmp
);
6737 tcg_temp_free_i64(tmp
);
6740 g_assert_not_reached();
6743 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
6748 tcg_gen_ld32u_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_32
));
6752 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_64
));
6755 /* 64 bits from top half */
6756 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_hi_offset(s
, rn
));
6760 tcg_gen_ld16u_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_16
));
6763 g_assert_not_reached();
6768 static void handle_fjcvtzs(DisasContext
*s
, int rd
, int rn
)
6770 TCGv_i64 t
= read_fp_dreg(s
, rn
);
6771 TCGv_ptr fpstatus
= get_fpstatus_ptr(false);
6773 gen_helper_fjcvtzs(t
, t
, fpstatus
);
6775 tcg_temp_free_ptr(fpstatus
);
6777 tcg_gen_ext32u_i64(cpu_reg(s
, rd
), t
);
6778 tcg_gen_extrh_i64_i32(cpu_ZF
, t
);
6779 tcg_gen_movi_i32(cpu_CF
, 0);
6780 tcg_gen_movi_i32(cpu_NF
, 0);
6781 tcg_gen_movi_i32(cpu_VF
, 0);
6783 tcg_temp_free_i64(t
);
6786 /* Floating point <-> integer conversions
6787 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
6788 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
6789 * | sf | 0 | S | 1 1 1 1 0 | type | 1 | rmode | opc | 0 0 0 0 0 0 | Rn | Rd |
6790 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
6792 static void disas_fp_int_conv(DisasContext
*s
, uint32_t insn
)
6794 int rd
= extract32(insn
, 0, 5);
6795 int rn
= extract32(insn
, 5, 5);
6796 int opcode
= extract32(insn
, 16, 3);
6797 int rmode
= extract32(insn
, 19, 2);
6798 int type
= extract32(insn
, 22, 2);
6799 bool sbit
= extract32(insn
, 29, 1);
6800 bool sf
= extract32(insn
, 31, 1);
6804 goto do_unallocated
;
6812 case 4: /* FCVTAS */
6813 case 5: /* FCVTAU */
6815 goto do_unallocated
;
6818 case 0: /* FCVT[NPMZ]S */
6819 case 1: /* FCVT[NPMZ]U */
6821 case 0: /* float32 */
6822 case 1: /* float64 */
6824 case 3: /* float16 */
6825 if (!dc_isar_feature(aa64_fp16
, s
)) {
6826 goto do_unallocated
;
6830 goto do_unallocated
;
6832 if (!fp_access_check(s
)) {
6835 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, rmode
, 64, sf
, type
);
6839 switch (sf
<< 7 | type
<< 5 | rmode
<< 3 | opcode
) {
6840 case 0b01100110: /* FMOV half <-> 32-bit int */
6842 case 0b11100110: /* FMOV half <-> 64-bit int */
6844 if (!dc_isar_feature(aa64_fp16
, s
)) {
6845 goto do_unallocated
;
6848 case 0b00000110: /* FMOV 32-bit */
6850 case 0b10100110: /* FMOV 64-bit */
6852 case 0b11001110: /* FMOV top half of 128-bit */
6854 if (!fp_access_check(s
)) {
6858 handle_fmov(s
, rd
, rn
, type
, itof
);
6861 case 0b00111110: /* FJCVTZS */
6862 if (!dc_isar_feature(aa64_jscvt
, s
)) {
6863 goto do_unallocated
;
6864 } else if (fp_access_check(s
)) {
6865 handle_fjcvtzs(s
, rd
, rn
);
6871 unallocated_encoding(s
);
6878 /* FP-specific subcases of table C3-6 (SIMD and FP data processing)
6879 * 31 30 29 28 25 24 0
6880 * +---+---+---+---------+-----------------------------+
6881 * | | 0 | | 1 1 1 1 | |
6882 * +---+---+---+---------+-----------------------------+
6884 static void disas_data_proc_fp(DisasContext
*s
, uint32_t insn
)
6886 if (extract32(insn
, 24, 1)) {
6887 /* Floating point data-processing (3 source) */
6888 disas_fp_3src(s
, insn
);
6889 } else if (extract32(insn
, 21, 1) == 0) {
6890 /* Floating point to fixed point conversions */
6891 disas_fp_fixed_conv(s
, insn
);
6893 switch (extract32(insn
, 10, 2)) {
6895 /* Floating point conditional compare */
6896 disas_fp_ccomp(s
, insn
);
6899 /* Floating point data-processing (2 source) */
6900 disas_fp_2src(s
, insn
);
6903 /* Floating point conditional select */
6904 disas_fp_csel(s
, insn
);
6907 switch (ctz32(extract32(insn
, 12, 4))) {
6908 case 0: /* [15:12] == xxx1 */
6909 /* Floating point immediate */
6910 disas_fp_imm(s
, insn
);
6912 case 1: /* [15:12] == xx10 */
6913 /* Floating point compare */
6914 disas_fp_compare(s
, insn
);
6916 case 2: /* [15:12] == x100 */
6917 /* Floating point data-processing (1 source) */
6918 disas_fp_1src(s
, insn
);
6920 case 3: /* [15:12] == 1000 */
6921 unallocated_encoding(s
);
6923 default: /* [15:12] == 0000 */
6924 /* Floating point <-> integer conversions */
6925 disas_fp_int_conv(s
, insn
);
6933 static void do_ext64(DisasContext
*s
, TCGv_i64 tcg_left
, TCGv_i64 tcg_right
,
6936 /* Extract 64 bits from the middle of two concatenated 64 bit
6937 * vector register slices left:right. The extracted bits start
6938 * at 'pos' bits into the right (least significant) side.
6939 * We return the result in tcg_right, and guarantee not to
6942 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
6943 assert(pos
> 0 && pos
< 64);
6945 tcg_gen_shri_i64(tcg_right
, tcg_right
, pos
);
6946 tcg_gen_shli_i64(tcg_tmp
, tcg_left
, 64 - pos
);
6947 tcg_gen_or_i64(tcg_right
, tcg_right
, tcg_tmp
);
6949 tcg_temp_free_i64(tcg_tmp
);
6953 * 31 30 29 24 23 22 21 20 16 15 14 11 10 9 5 4 0
6954 * +---+---+-------------+-----+---+------+---+------+---+------+------+
6955 * | 0 | Q | 1 0 1 1 1 0 | op2 | 0 | Rm | 0 | imm4 | 0 | Rn | Rd |
6956 * +---+---+-------------+-----+---+------+---+------+---+------+------+
6958 static void disas_simd_ext(DisasContext
*s
, uint32_t insn
)
6960 int is_q
= extract32(insn
, 30, 1);
6961 int op2
= extract32(insn
, 22, 2);
6962 int imm4
= extract32(insn
, 11, 4);
6963 int rm
= extract32(insn
, 16, 5);
6964 int rn
= extract32(insn
, 5, 5);
6965 int rd
= extract32(insn
, 0, 5);
6966 int pos
= imm4
<< 3;
6967 TCGv_i64 tcg_resl
, tcg_resh
;
6969 if (op2
!= 0 || (!is_q
&& extract32(imm4
, 3, 1))) {
6970 unallocated_encoding(s
);
6974 if (!fp_access_check(s
)) {
6978 tcg_resh
= tcg_temp_new_i64();
6979 tcg_resl
= tcg_temp_new_i64();
6981 /* Vd gets bits starting at pos bits into Vm:Vn. This is
6982 * either extracting 128 bits from a 128:128 concatenation, or
6983 * extracting 64 bits from a 64:64 concatenation.
6986 read_vec_element(s
, tcg_resl
, rn
, 0, MO_64
);
6988 read_vec_element(s
, tcg_resh
, rm
, 0, MO_64
);
6989 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
6991 tcg_gen_movi_i64(tcg_resh
, 0);
6998 EltPosns eltposns
[] = { {rn
, 0}, {rn
, 1}, {rm
, 0}, {rm
, 1} };
6999 EltPosns
*elt
= eltposns
;
7006 read_vec_element(s
, tcg_resl
, elt
->reg
, elt
->elt
, MO_64
);
7008 read_vec_element(s
, tcg_resh
, elt
->reg
, elt
->elt
, MO_64
);
7011 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
7012 tcg_hh
= tcg_temp_new_i64();
7013 read_vec_element(s
, tcg_hh
, elt
->reg
, elt
->elt
, MO_64
);
7014 do_ext64(s
, tcg_hh
, tcg_resh
, pos
);
7015 tcg_temp_free_i64(tcg_hh
);
7019 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
7020 tcg_temp_free_i64(tcg_resl
);
7021 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
7022 tcg_temp_free_i64(tcg_resh
);
7023 clear_vec_high(s
, true, rd
);
7027 * 31 30 29 24 23 22 21 20 16 15 14 13 12 11 10 9 5 4 0
7028 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
7029 * | 0 | Q | 0 0 1 1 1 0 | op2 | 0 | Rm | 0 | len | op | 0 0 | Rn | Rd |
7030 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
7032 static void disas_simd_tb(DisasContext
*s
, uint32_t insn
)
7034 int op2
= extract32(insn
, 22, 2);
7035 int is_q
= extract32(insn
, 30, 1);
7036 int rm
= extract32(insn
, 16, 5);
7037 int rn
= extract32(insn
, 5, 5);
7038 int rd
= extract32(insn
, 0, 5);
7039 int is_tblx
= extract32(insn
, 12, 1);
7040 int len
= extract32(insn
, 13, 2);
7041 TCGv_i64 tcg_resl
, tcg_resh
, tcg_idx
;
7042 TCGv_i32 tcg_regno
, tcg_numregs
;
7045 unallocated_encoding(s
);
7049 if (!fp_access_check(s
)) {
7053 /* This does a table lookup: for every byte element in the input
7054 * we index into a table formed from up to four vector registers,
7055 * and then the output is the result of the lookups. Our helper
7056 * function does the lookup operation for a single 64 bit part of
7059 tcg_resl
= tcg_temp_new_i64();
7060 tcg_resh
= tcg_temp_new_i64();
7063 read_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
7065 tcg_gen_movi_i64(tcg_resl
, 0);
7067 if (is_tblx
&& is_q
) {
7068 read_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
7070 tcg_gen_movi_i64(tcg_resh
, 0);
7073 tcg_idx
= tcg_temp_new_i64();
7074 tcg_regno
= tcg_const_i32(rn
);
7075 tcg_numregs
= tcg_const_i32(len
+ 1);
7076 read_vec_element(s
, tcg_idx
, rm
, 0, MO_64
);
7077 gen_helper_simd_tbl(tcg_resl
, cpu_env
, tcg_resl
, tcg_idx
,
7078 tcg_regno
, tcg_numregs
);
7080 read_vec_element(s
, tcg_idx
, rm
, 1, MO_64
);
7081 gen_helper_simd_tbl(tcg_resh
, cpu_env
, tcg_resh
, tcg_idx
,
7082 tcg_regno
, tcg_numregs
);
7084 tcg_temp_free_i64(tcg_idx
);
7085 tcg_temp_free_i32(tcg_regno
);
7086 tcg_temp_free_i32(tcg_numregs
);
7088 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
7089 tcg_temp_free_i64(tcg_resl
);
7090 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
7091 tcg_temp_free_i64(tcg_resh
);
7092 clear_vec_high(s
, true, rd
);
7096 * 31 30 29 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
7097 * +---+---+-------------+------+---+------+---+------------------+------+
7098 * | 0 | Q | 0 0 1 1 1 0 | size | 0 | Rm | 0 | opc | 1 0 | Rn | Rd |
7099 * +---+---+-------------+------+---+------+---+------------------+------+
7101 static void disas_simd_zip_trn(DisasContext
*s
, uint32_t insn
)
7103 int rd
= extract32(insn
, 0, 5);
7104 int rn
= extract32(insn
, 5, 5);
7105 int rm
= extract32(insn
, 16, 5);
7106 int size
= extract32(insn
, 22, 2);
7107 /* opc field bits [1:0] indicate ZIP/UZP/TRN;
7108 * bit 2 indicates 1 vs 2 variant of the insn.
7110 int opcode
= extract32(insn
, 12, 2);
7111 bool part
= extract32(insn
, 14, 1);
7112 bool is_q
= extract32(insn
, 30, 1);
7113 int esize
= 8 << size
;
7115 int datasize
= is_q
? 128 : 64;
7116 int elements
= datasize
/ esize
;
7117 TCGv_i64 tcg_res
, tcg_resl
, tcg_resh
;
7119 if (opcode
== 0 || (size
== 3 && !is_q
)) {
7120 unallocated_encoding(s
);
7124 if (!fp_access_check(s
)) {
7128 tcg_resl
= tcg_const_i64(0);
7129 tcg_resh
= tcg_const_i64(0);
7130 tcg_res
= tcg_temp_new_i64();
7132 for (i
= 0; i
< elements
; i
++) {
7134 case 1: /* UZP1/2 */
7136 int midpoint
= elements
/ 2;
7138 read_vec_element(s
, tcg_res
, rn
, 2 * i
+ part
, size
);
7140 read_vec_element(s
, tcg_res
, rm
,
7141 2 * (i
- midpoint
) + part
, size
);
7145 case 2: /* TRN1/2 */
7147 read_vec_element(s
, tcg_res
, rm
, (i
& ~1) + part
, size
);
7149 read_vec_element(s
, tcg_res
, rn
, (i
& ~1) + part
, size
);
7152 case 3: /* ZIP1/2 */
7154 int base
= part
* elements
/ 2;
7156 read_vec_element(s
, tcg_res
, rm
, base
+ (i
>> 1), size
);
7158 read_vec_element(s
, tcg_res
, rn
, base
+ (i
>> 1), size
);
7163 g_assert_not_reached();
7168 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
);
7169 tcg_gen_or_i64(tcg_resl
, tcg_resl
, tcg_res
);
7171 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
- 64);
7172 tcg_gen_or_i64(tcg_resh
, tcg_resh
, tcg_res
);
7176 tcg_temp_free_i64(tcg_res
);
7178 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
7179 tcg_temp_free_i64(tcg_resl
);
7180 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
7181 tcg_temp_free_i64(tcg_resh
);
7182 clear_vec_high(s
, true, rd
);
7186 * do_reduction_op helper
7188 * This mirrors the Reduce() pseudocode in the ARM ARM. It is
7189 * important for correct NaN propagation that we do these
7190 * operations in exactly the order specified by the pseudocode.
7192 * This is a recursive function, TCG temps should be freed by the
7193 * calling function once it is done with the values.
7195 static TCGv_i32
do_reduction_op(DisasContext
*s
, int fpopcode
, int rn
,
7196 int esize
, int size
, int vmap
, TCGv_ptr fpst
)
7198 if (esize
== size
) {
7200 MemOp msize
= esize
== 16 ? MO_16
: MO_32
;
7203 /* We should have one register left here */
7204 assert(ctpop8(vmap
) == 1);
7205 element
= ctz32(vmap
);
7206 assert(element
< 8);
7208 tcg_elem
= tcg_temp_new_i32();
7209 read_vec_element_i32(s
, tcg_elem
, rn
, element
, msize
);
7212 int bits
= size
/ 2;
7213 int shift
= ctpop8(vmap
) / 2;
7214 int vmap_lo
= (vmap
>> shift
) & vmap
;
7215 int vmap_hi
= (vmap
& ~vmap_lo
);
7216 TCGv_i32 tcg_hi
, tcg_lo
, tcg_res
;
7218 tcg_hi
= do_reduction_op(s
, fpopcode
, rn
, esize
, bits
, vmap_hi
, fpst
);
7219 tcg_lo
= do_reduction_op(s
, fpopcode
, rn
, esize
, bits
, vmap_lo
, fpst
);
7220 tcg_res
= tcg_temp_new_i32();
7223 case 0x0c: /* fmaxnmv half-precision */
7224 gen_helper_advsimd_maxnumh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7226 case 0x0f: /* fmaxv half-precision */
7227 gen_helper_advsimd_maxh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7229 case 0x1c: /* fminnmv half-precision */
7230 gen_helper_advsimd_minnumh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7232 case 0x1f: /* fminv half-precision */
7233 gen_helper_advsimd_minh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7235 case 0x2c: /* fmaxnmv */
7236 gen_helper_vfp_maxnums(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7238 case 0x2f: /* fmaxv */
7239 gen_helper_vfp_maxs(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7241 case 0x3c: /* fminnmv */
7242 gen_helper_vfp_minnums(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7244 case 0x3f: /* fminv */
7245 gen_helper_vfp_mins(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7248 g_assert_not_reached();
7251 tcg_temp_free_i32(tcg_hi
);
7252 tcg_temp_free_i32(tcg_lo
);
7257 /* AdvSIMD across lanes
7258 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
7259 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
7260 * | 0 | Q | U | 0 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
7261 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
7263 static void disas_simd_across_lanes(DisasContext
*s
, uint32_t insn
)
7265 int rd
= extract32(insn
, 0, 5);
7266 int rn
= extract32(insn
, 5, 5);
7267 int size
= extract32(insn
, 22, 2);
7268 int opcode
= extract32(insn
, 12, 5);
7269 bool is_q
= extract32(insn
, 30, 1);
7270 bool is_u
= extract32(insn
, 29, 1);
7272 bool is_min
= false;
7276 TCGv_i64 tcg_res
, tcg_elt
;
7279 case 0x1b: /* ADDV */
7281 unallocated_encoding(s
);
7285 case 0x3: /* SADDLV, UADDLV */
7286 case 0xa: /* SMAXV, UMAXV */
7287 case 0x1a: /* SMINV, UMINV */
7288 if (size
== 3 || (size
== 2 && !is_q
)) {
7289 unallocated_encoding(s
);
7293 case 0xc: /* FMAXNMV, FMINNMV */
7294 case 0xf: /* FMAXV, FMINV */
7295 /* Bit 1 of size field encodes min vs max and the actual size
7296 * depends on the encoding of the U bit. If not set (and FP16
7297 * enabled) then we do half-precision float instead of single
7300 is_min
= extract32(size
, 1, 1);
7302 if (!is_u
&& dc_isar_feature(aa64_fp16
, s
)) {
7304 } else if (!is_u
|| !is_q
|| extract32(size
, 0, 1)) {
7305 unallocated_encoding(s
);
7312 unallocated_encoding(s
);
7316 if (!fp_access_check(s
)) {
7321 elements
= (is_q
? 128 : 64) / esize
;
7323 tcg_res
= tcg_temp_new_i64();
7324 tcg_elt
= tcg_temp_new_i64();
7326 /* These instructions operate across all lanes of a vector
7327 * to produce a single result. We can guarantee that a 64
7328 * bit intermediate is sufficient:
7329 * + for [US]ADDLV the maximum element size is 32 bits, and
7330 * the result type is 64 bits
7331 * + for FMAX*V, FMIN*V, ADDV the intermediate type is the
7332 * same as the element size, which is 32 bits at most
7333 * For the integer operations we can choose to work at 64
7334 * or 32 bits and truncate at the end; for simplicity
7335 * we use 64 bits always. The floating point
7336 * ops do require 32 bit intermediates, though.
7339 read_vec_element(s
, tcg_res
, rn
, 0, size
| (is_u
? 0 : MO_SIGN
));
7341 for (i
= 1; i
< elements
; i
++) {
7342 read_vec_element(s
, tcg_elt
, rn
, i
, size
| (is_u
? 0 : MO_SIGN
));
7345 case 0x03: /* SADDLV / UADDLV */
7346 case 0x1b: /* ADDV */
7347 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_elt
);
7349 case 0x0a: /* SMAXV / UMAXV */
7351 tcg_gen_umax_i64(tcg_res
, tcg_res
, tcg_elt
);
7353 tcg_gen_smax_i64(tcg_res
, tcg_res
, tcg_elt
);
7356 case 0x1a: /* SMINV / UMINV */
7358 tcg_gen_umin_i64(tcg_res
, tcg_res
, tcg_elt
);
7360 tcg_gen_smin_i64(tcg_res
, tcg_res
, tcg_elt
);
7364 g_assert_not_reached();
7369 /* Floating point vector reduction ops which work across 32
7370 * bit (single) or 16 bit (half-precision) intermediates.
7371 * Note that correct NaN propagation requires that we do these
7372 * operations in exactly the order specified by the pseudocode.
7374 TCGv_ptr fpst
= get_fpstatus_ptr(size
== MO_16
);
7375 int fpopcode
= opcode
| is_min
<< 4 | is_u
<< 5;
7376 int vmap
= (1 << elements
) - 1;
7377 TCGv_i32 tcg_res32
= do_reduction_op(s
, fpopcode
, rn
, esize
,
7378 (is_q
? 128 : 64), vmap
, fpst
);
7379 tcg_gen_extu_i32_i64(tcg_res
, tcg_res32
);
7380 tcg_temp_free_i32(tcg_res32
);
7381 tcg_temp_free_ptr(fpst
);
7384 tcg_temp_free_i64(tcg_elt
);
7386 /* Now truncate the result to the width required for the final output */
7387 if (opcode
== 0x03) {
7388 /* SADDLV, UADDLV: result is 2*esize */
7394 tcg_gen_ext8u_i64(tcg_res
, tcg_res
);
7397 tcg_gen_ext16u_i64(tcg_res
, tcg_res
);
7400 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
7405 g_assert_not_reached();
7408 write_fp_dreg(s
, rd
, tcg_res
);
7409 tcg_temp_free_i64(tcg_res
);
7412 /* DUP (Element, Vector)
7414 * 31 30 29 21 20 16 15 10 9 5 4 0
7415 * +---+---+-------------------+--------+-------------+------+------+
7416 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
7417 * +---+---+-------------------+--------+-------------+------+------+
7419 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7421 static void handle_simd_dupe(DisasContext
*s
, int is_q
, int rd
, int rn
,
7424 int size
= ctz32(imm5
);
7427 if (size
> 3 || (size
== 3 && !is_q
)) {
7428 unallocated_encoding(s
);
7432 if (!fp_access_check(s
)) {
7436 index
= imm5
>> (size
+ 1);
7437 tcg_gen_gvec_dup_mem(size
, vec_full_reg_offset(s
, rd
),
7438 vec_reg_offset(s
, rn
, index
, size
),
7439 is_q
? 16 : 8, vec_full_reg_size(s
));
7442 /* DUP (element, scalar)
7443 * 31 21 20 16 15 10 9 5 4 0
7444 * +-----------------------+--------+-------------+------+------+
7445 * | 0 1 0 1 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
7446 * +-----------------------+--------+-------------+------+------+
7448 static void handle_simd_dupes(DisasContext
*s
, int rd
, int rn
,
7451 int size
= ctz32(imm5
);
7456 unallocated_encoding(s
);
7460 if (!fp_access_check(s
)) {
7464 index
= imm5
>> (size
+ 1);
7466 /* This instruction just extracts the specified element and
7467 * zero-extends it into the bottom of the destination register.
7469 tmp
= tcg_temp_new_i64();
7470 read_vec_element(s
, tmp
, rn
, index
, size
);
7471 write_fp_dreg(s
, rd
, tmp
);
7472 tcg_temp_free_i64(tmp
);
7477 * 31 30 29 21 20 16 15 10 9 5 4 0
7478 * +---+---+-------------------+--------+-------------+------+------+
7479 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 1 1 | Rn | Rd |
7480 * +---+---+-------------------+--------+-------------+------+------+
7482 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7484 static void handle_simd_dupg(DisasContext
*s
, int is_q
, int rd
, int rn
,
7487 int size
= ctz32(imm5
);
7488 uint32_t dofs
, oprsz
, maxsz
;
7490 if (size
> 3 || ((size
== 3) && !is_q
)) {
7491 unallocated_encoding(s
);
7495 if (!fp_access_check(s
)) {
7499 dofs
= vec_full_reg_offset(s
, rd
);
7500 oprsz
= is_q
? 16 : 8;
7501 maxsz
= vec_full_reg_size(s
);
7503 tcg_gen_gvec_dup_i64(size
, dofs
, oprsz
, maxsz
, cpu_reg(s
, rn
));
7508 * 31 21 20 16 15 14 11 10 9 5 4 0
7509 * +-----------------------+--------+------------+---+------+------+
7510 * | 0 1 1 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
7511 * +-----------------------+--------+------------+---+------+------+
7513 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7514 * index: encoded in imm5<4:size+1>
7516 static void handle_simd_inse(DisasContext
*s
, int rd
, int rn
,
7519 int size
= ctz32(imm5
);
7520 int src_index
, dst_index
;
7524 unallocated_encoding(s
);
7528 if (!fp_access_check(s
)) {
7532 dst_index
= extract32(imm5
, 1+size
, 5);
7533 src_index
= extract32(imm4
, size
, 4);
7535 tmp
= tcg_temp_new_i64();
7537 read_vec_element(s
, tmp
, rn
, src_index
, size
);
7538 write_vec_element(s
, tmp
, rd
, dst_index
, size
);
7540 tcg_temp_free_i64(tmp
);
7542 /* INS is considered a 128-bit write for SVE. */
7543 clear_vec_high(s
, true, rd
);
7549 * 31 21 20 16 15 10 9 5 4 0
7550 * +-----------------------+--------+-------------+------+------+
7551 * | 0 1 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 1 1 1 | Rn | Rd |
7552 * +-----------------------+--------+-------------+------+------+
7554 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7555 * index: encoded in imm5<4:size+1>
7557 static void handle_simd_insg(DisasContext
*s
, int rd
, int rn
, int imm5
)
7559 int size
= ctz32(imm5
);
7563 unallocated_encoding(s
);
7567 if (!fp_access_check(s
)) {
7571 idx
= extract32(imm5
, 1 + size
, 4 - size
);
7572 write_vec_element(s
, cpu_reg(s
, rn
), rd
, idx
, size
);
7574 /* INS is considered a 128-bit write for SVE. */
7575 clear_vec_high(s
, true, rd
);
7582 * 31 30 29 21 20 16 15 12 10 9 5 4 0
7583 * +---+---+-------------------+--------+-------------+------+------+
7584 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 1 U 1 1 | Rn | Rd |
7585 * +---+---+-------------------+--------+-------------+------+------+
7587 * U: unsigned when set
7588 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7590 static void handle_simd_umov_smov(DisasContext
*s
, int is_q
, int is_signed
,
7591 int rn
, int rd
, int imm5
)
7593 int size
= ctz32(imm5
);
7597 /* Check for UnallocatedEncodings */
7599 if (size
> 2 || (size
== 2 && !is_q
)) {
7600 unallocated_encoding(s
);
7605 || (size
< 3 && is_q
)
7606 || (size
== 3 && !is_q
)) {
7607 unallocated_encoding(s
);
7612 if (!fp_access_check(s
)) {
7616 element
= extract32(imm5
, 1+size
, 4);
7618 tcg_rd
= cpu_reg(s
, rd
);
7619 read_vec_element(s
, tcg_rd
, rn
, element
, size
| (is_signed
? MO_SIGN
: 0));
7620 if (is_signed
&& !is_q
) {
7621 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
7626 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
7627 * +---+---+----+-----------------+------+---+------+---+------+------+
7628 * | 0 | Q | op | 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
7629 * +---+---+----+-----------------+------+---+------+---+------+------+
7631 static void disas_simd_copy(DisasContext
*s
, uint32_t insn
)
7633 int rd
= extract32(insn
, 0, 5);
7634 int rn
= extract32(insn
, 5, 5);
7635 int imm4
= extract32(insn
, 11, 4);
7636 int op
= extract32(insn
, 29, 1);
7637 int is_q
= extract32(insn
, 30, 1);
7638 int imm5
= extract32(insn
, 16, 5);
7643 handle_simd_inse(s
, rd
, rn
, imm4
, imm5
);
7645 unallocated_encoding(s
);
7650 /* DUP (element - vector) */
7651 handle_simd_dupe(s
, is_q
, rd
, rn
, imm5
);
7655 handle_simd_dupg(s
, is_q
, rd
, rn
, imm5
);
7660 handle_simd_insg(s
, rd
, rn
, imm5
);
7662 unallocated_encoding(s
);
7667 /* UMOV/SMOV (is_q indicates 32/64; imm4 indicates signedness) */
7668 handle_simd_umov_smov(s
, is_q
, (imm4
== 5), rn
, rd
, imm5
);
7671 unallocated_encoding(s
);
7677 /* AdvSIMD modified immediate
7678 * 31 30 29 28 19 18 16 15 12 11 10 9 5 4 0
7679 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
7680 * | 0 | Q | op | 0 1 1 1 1 0 0 0 0 0 | abc | cmode | o2 | 1 | defgh | Rd |
7681 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
7683 * There are a number of operations that can be carried out here:
7684 * MOVI - move (shifted) imm into register
7685 * MVNI - move inverted (shifted) imm into register
7686 * ORR - bitwise OR of (shifted) imm with register
7687 * BIC - bitwise clear of (shifted) imm with register
7688 * With ARMv8.2 we also have:
7689 * FMOV half-precision
7691 static void disas_simd_mod_imm(DisasContext
*s
, uint32_t insn
)
7693 int rd
= extract32(insn
, 0, 5);
7694 int cmode
= extract32(insn
, 12, 4);
7695 int cmode_3_1
= extract32(cmode
, 1, 3);
7696 int cmode_0
= extract32(cmode
, 0, 1);
7697 int o2
= extract32(insn
, 11, 1);
7698 uint64_t abcdefgh
= extract32(insn
, 5, 5) | (extract32(insn
, 16, 3) << 5);
7699 bool is_neg
= extract32(insn
, 29, 1);
7700 bool is_q
= extract32(insn
, 30, 1);
7703 if (o2
!= 0 || ((cmode
== 0xf) && is_neg
&& !is_q
)) {
7704 /* Check for FMOV (vector, immediate) - half-precision */
7705 if (!(dc_isar_feature(aa64_fp16
, s
) && o2
&& cmode
== 0xf)) {
7706 unallocated_encoding(s
);
7711 if (!fp_access_check(s
)) {
7715 /* See AdvSIMDExpandImm() in ARM ARM */
7716 switch (cmode_3_1
) {
7717 case 0: /* Replicate(Zeros(24):imm8, 2) */
7718 case 1: /* Replicate(Zeros(16):imm8:Zeros(8), 2) */
7719 case 2: /* Replicate(Zeros(8):imm8:Zeros(16), 2) */
7720 case 3: /* Replicate(imm8:Zeros(24), 2) */
7722 int shift
= cmode_3_1
* 8;
7723 imm
= bitfield_replicate(abcdefgh
<< shift
, 32);
7726 case 4: /* Replicate(Zeros(8):imm8, 4) */
7727 case 5: /* Replicate(imm8:Zeros(8), 4) */
7729 int shift
= (cmode_3_1
& 0x1) * 8;
7730 imm
= bitfield_replicate(abcdefgh
<< shift
, 16);
7735 /* Replicate(Zeros(8):imm8:Ones(16), 2) */
7736 imm
= (abcdefgh
<< 16) | 0xffff;
7738 /* Replicate(Zeros(16):imm8:Ones(8), 2) */
7739 imm
= (abcdefgh
<< 8) | 0xff;
7741 imm
= bitfield_replicate(imm
, 32);
7744 if (!cmode_0
&& !is_neg
) {
7745 imm
= bitfield_replicate(abcdefgh
, 8);
7746 } else if (!cmode_0
&& is_neg
) {
7749 for (i
= 0; i
< 8; i
++) {
7750 if ((abcdefgh
) & (1 << i
)) {
7751 imm
|= 0xffULL
<< (i
* 8);
7754 } else if (cmode_0
) {
7756 imm
= (abcdefgh
& 0x3f) << 48;
7757 if (abcdefgh
& 0x80) {
7758 imm
|= 0x8000000000000000ULL
;
7760 if (abcdefgh
& 0x40) {
7761 imm
|= 0x3fc0000000000000ULL
;
7763 imm
|= 0x4000000000000000ULL
;
7767 /* FMOV (vector, immediate) - half-precision */
7768 imm
= vfp_expand_imm(MO_16
, abcdefgh
);
7769 /* now duplicate across the lanes */
7770 imm
= bitfield_replicate(imm
, 16);
7772 imm
= (abcdefgh
& 0x3f) << 19;
7773 if (abcdefgh
& 0x80) {
7776 if (abcdefgh
& 0x40) {
7787 fprintf(stderr
, "%s: cmode_3_1: %x\n", __func__
, cmode_3_1
);
7788 g_assert_not_reached();
7791 if (cmode_3_1
!= 7 && is_neg
) {
7795 if (!((cmode
& 0x9) == 0x1 || (cmode
& 0xd) == 0x9)) {
7796 /* MOVI or MVNI, with MVNI negation handled above. */
7797 tcg_gen_gvec_dup64i(vec_full_reg_offset(s
, rd
), is_q
? 16 : 8,
7798 vec_full_reg_size(s
), imm
);
7800 /* ORR or BIC, with BIC negation to AND handled above. */
7802 gen_gvec_fn2i(s
, is_q
, rd
, rd
, imm
, tcg_gen_gvec_andi
, MO_64
);
7804 gen_gvec_fn2i(s
, is_q
, rd
, rd
, imm
, tcg_gen_gvec_ori
, MO_64
);
7809 /* AdvSIMD scalar copy
7810 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
7811 * +-----+----+-----------------+------+---+------+---+------+------+
7812 * | 0 1 | op | 1 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
7813 * +-----+----+-----------------+------+---+------+---+------+------+
7815 static void disas_simd_scalar_copy(DisasContext
*s
, uint32_t insn
)
7817 int rd
= extract32(insn
, 0, 5);
7818 int rn
= extract32(insn
, 5, 5);
7819 int imm4
= extract32(insn
, 11, 4);
7820 int imm5
= extract32(insn
, 16, 5);
7821 int op
= extract32(insn
, 29, 1);
7823 if (op
!= 0 || imm4
!= 0) {
7824 unallocated_encoding(s
);
7828 /* DUP (element, scalar) */
7829 handle_simd_dupes(s
, rd
, rn
, imm5
);
7832 /* AdvSIMD scalar pairwise
7833 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
7834 * +-----+---+-----------+------+-----------+--------+-----+------+------+
7835 * | 0 1 | U | 1 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
7836 * +-----+---+-----------+------+-----------+--------+-----+------+------+
7838 static void disas_simd_scalar_pairwise(DisasContext
*s
, uint32_t insn
)
7840 int u
= extract32(insn
, 29, 1);
7841 int size
= extract32(insn
, 22, 2);
7842 int opcode
= extract32(insn
, 12, 5);
7843 int rn
= extract32(insn
, 5, 5);
7844 int rd
= extract32(insn
, 0, 5);
7847 /* For some ops (the FP ones), size[1] is part of the encoding.
7848 * For ADDP strictly it is not but size[1] is always 1 for valid
7851 opcode
|= (extract32(size
, 1, 1) << 5);
7854 case 0x3b: /* ADDP */
7855 if (u
|| size
!= 3) {
7856 unallocated_encoding(s
);
7859 if (!fp_access_check(s
)) {
7865 case 0xc: /* FMAXNMP */
7866 case 0xd: /* FADDP */
7867 case 0xf: /* FMAXP */
7868 case 0x2c: /* FMINNMP */
7869 case 0x2f: /* FMINP */
7870 /* FP op, size[0] is 32 or 64 bit*/
7872 if (!dc_isar_feature(aa64_fp16
, s
)) {
7873 unallocated_encoding(s
);
7879 size
= extract32(size
, 0, 1) ? MO_64
: MO_32
;
7882 if (!fp_access_check(s
)) {
7886 fpst
= get_fpstatus_ptr(size
== MO_16
);
7889 unallocated_encoding(s
);
7893 if (size
== MO_64
) {
7894 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
7895 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
7896 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7898 read_vec_element(s
, tcg_op1
, rn
, 0, MO_64
);
7899 read_vec_element(s
, tcg_op2
, rn
, 1, MO_64
);
7902 case 0x3b: /* ADDP */
7903 tcg_gen_add_i64(tcg_res
, tcg_op1
, tcg_op2
);
7905 case 0xc: /* FMAXNMP */
7906 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7908 case 0xd: /* FADDP */
7909 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7911 case 0xf: /* FMAXP */
7912 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7914 case 0x2c: /* FMINNMP */
7915 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7917 case 0x2f: /* FMINP */
7918 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7921 g_assert_not_reached();
7924 write_fp_dreg(s
, rd
, tcg_res
);
7926 tcg_temp_free_i64(tcg_op1
);
7927 tcg_temp_free_i64(tcg_op2
);
7928 tcg_temp_free_i64(tcg_res
);
7930 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
7931 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
7932 TCGv_i32 tcg_res
= tcg_temp_new_i32();
7934 read_vec_element_i32(s
, tcg_op1
, rn
, 0, size
);
7935 read_vec_element_i32(s
, tcg_op2
, rn
, 1, size
);
7937 if (size
== MO_16
) {
7939 case 0xc: /* FMAXNMP */
7940 gen_helper_advsimd_maxnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7942 case 0xd: /* FADDP */
7943 gen_helper_advsimd_addh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7945 case 0xf: /* FMAXP */
7946 gen_helper_advsimd_maxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7948 case 0x2c: /* FMINNMP */
7949 gen_helper_advsimd_minnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7951 case 0x2f: /* FMINP */
7952 gen_helper_advsimd_minh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7955 g_assert_not_reached();
7959 case 0xc: /* FMAXNMP */
7960 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7962 case 0xd: /* FADDP */
7963 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7965 case 0xf: /* FMAXP */
7966 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7968 case 0x2c: /* FMINNMP */
7969 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7971 case 0x2f: /* FMINP */
7972 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7975 g_assert_not_reached();
7979 write_fp_sreg(s
, rd
, tcg_res
);
7981 tcg_temp_free_i32(tcg_op1
);
7982 tcg_temp_free_i32(tcg_op2
);
7983 tcg_temp_free_i32(tcg_res
);
7987 tcg_temp_free_ptr(fpst
);
7992 * Common SSHR[RA]/USHR[RA] - Shift right (optional rounding/accumulate)
7994 * This code is handles the common shifting code and is used by both
7995 * the vector and scalar code.
7997 static void handle_shri_with_rndacc(TCGv_i64 tcg_res
, TCGv_i64 tcg_src
,
7998 TCGv_i64 tcg_rnd
, bool accumulate
,
7999 bool is_u
, int size
, int shift
)
8001 bool extended_result
= false;
8002 bool round
= tcg_rnd
!= NULL
;
8004 TCGv_i64 tcg_src_hi
;
8006 if (round
&& size
== 3) {
8007 extended_result
= true;
8008 ext_lshift
= 64 - shift
;
8009 tcg_src_hi
= tcg_temp_new_i64();
8010 } else if (shift
== 64) {
8011 if (!accumulate
&& is_u
) {
8012 /* result is zero */
8013 tcg_gen_movi_i64(tcg_res
, 0);
8018 /* Deal with the rounding step */
8020 if (extended_result
) {
8021 TCGv_i64 tcg_zero
= tcg_const_i64(0);
8023 /* take care of sign extending tcg_res */
8024 tcg_gen_sari_i64(tcg_src_hi
, tcg_src
, 63);
8025 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
8026 tcg_src
, tcg_src_hi
,
8029 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
8033 tcg_temp_free_i64(tcg_zero
);
8035 tcg_gen_add_i64(tcg_src
, tcg_src
, tcg_rnd
);
8039 /* Now do the shift right */
8040 if (round
&& extended_result
) {
8041 /* extended case, >64 bit precision required */
8042 if (ext_lshift
== 0) {
8043 /* special case, only high bits matter */
8044 tcg_gen_mov_i64(tcg_src
, tcg_src_hi
);
8046 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
8047 tcg_gen_shli_i64(tcg_src_hi
, tcg_src_hi
, ext_lshift
);
8048 tcg_gen_or_i64(tcg_src
, tcg_src
, tcg_src_hi
);
8053 /* essentially shifting in 64 zeros */
8054 tcg_gen_movi_i64(tcg_src
, 0);
8056 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
8060 /* effectively extending the sign-bit */
8061 tcg_gen_sari_i64(tcg_src
, tcg_src
, 63);
8063 tcg_gen_sari_i64(tcg_src
, tcg_src
, shift
);
8069 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_src
);
8071 tcg_gen_mov_i64(tcg_res
, tcg_src
);
8074 if (extended_result
) {
8075 tcg_temp_free_i64(tcg_src_hi
);
8079 /* SSHR[RA]/USHR[RA] - Scalar shift right (optional rounding/accumulate) */
8080 static void handle_scalar_simd_shri(DisasContext
*s
,
8081 bool is_u
, int immh
, int immb
,
8082 int opcode
, int rn
, int rd
)
8085 int immhb
= immh
<< 3 | immb
;
8086 int shift
= 2 * (8 << size
) - immhb
;
8087 bool accumulate
= false;
8089 bool insert
= false;
8094 if (!extract32(immh
, 3, 1)) {
8095 unallocated_encoding(s
);
8099 if (!fp_access_check(s
)) {
8104 case 0x02: /* SSRA / USRA (accumulate) */
8107 case 0x04: /* SRSHR / URSHR (rounding) */
8110 case 0x06: /* SRSRA / URSRA (accum + rounding) */
8111 accumulate
= round
= true;
8113 case 0x08: /* SRI */
8119 uint64_t round_const
= 1ULL << (shift
- 1);
8120 tcg_round
= tcg_const_i64(round_const
);
8125 tcg_rn
= read_fp_dreg(s
, rn
);
8126 tcg_rd
= (accumulate
|| insert
) ? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
8129 /* shift count same as element size is valid but does nothing;
8130 * special case to avoid potential shift by 64.
8132 int esize
= 8 << size
;
8133 if (shift
!= esize
) {
8134 tcg_gen_shri_i64(tcg_rn
, tcg_rn
, shift
);
8135 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, 0, esize
- shift
);
8138 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
8139 accumulate
, is_u
, size
, shift
);
8142 write_fp_dreg(s
, rd
, tcg_rd
);
8144 tcg_temp_free_i64(tcg_rn
);
8145 tcg_temp_free_i64(tcg_rd
);
8147 tcg_temp_free_i64(tcg_round
);
8151 /* SHL/SLI - Scalar shift left */
8152 static void handle_scalar_simd_shli(DisasContext
*s
, bool insert
,
8153 int immh
, int immb
, int opcode
,
8156 int size
= 32 - clz32(immh
) - 1;
8157 int immhb
= immh
<< 3 | immb
;
8158 int shift
= immhb
- (8 << size
);
8159 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
8160 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
8162 if (!extract32(immh
, 3, 1)) {
8163 unallocated_encoding(s
);
8167 if (!fp_access_check(s
)) {
8171 tcg_rn
= read_fp_dreg(s
, rn
);
8172 tcg_rd
= insert
? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
8175 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, shift
, 64 - shift
);
8177 tcg_gen_shli_i64(tcg_rd
, tcg_rn
, shift
);
8180 write_fp_dreg(s
, rd
, tcg_rd
);
8182 tcg_temp_free_i64(tcg_rn
);
8183 tcg_temp_free_i64(tcg_rd
);
8186 /* SQSHRN/SQSHRUN - Saturating (signed/unsigned) shift right with
8187 * (signed/unsigned) narrowing */
8188 static void handle_vec_simd_sqshrn(DisasContext
*s
, bool is_scalar
, bool is_q
,
8189 bool is_u_shift
, bool is_u_narrow
,
8190 int immh
, int immb
, int opcode
,
8193 int immhb
= immh
<< 3 | immb
;
8194 int size
= 32 - clz32(immh
) - 1;
8195 int esize
= 8 << size
;
8196 int shift
= (2 * esize
) - immhb
;
8197 int elements
= is_scalar
? 1 : (64 / esize
);
8198 bool round
= extract32(opcode
, 0, 1);
8199 MemOp ldop
= (size
+ 1) | (is_u_shift
? 0 : MO_SIGN
);
8200 TCGv_i64 tcg_rn
, tcg_rd
, tcg_round
;
8201 TCGv_i32 tcg_rd_narrowed
;
8204 static NeonGenNarrowEnvFn
* const signed_narrow_fns
[4][2] = {
8205 { gen_helper_neon_narrow_sat_s8
,
8206 gen_helper_neon_unarrow_sat8
},
8207 { gen_helper_neon_narrow_sat_s16
,
8208 gen_helper_neon_unarrow_sat16
},
8209 { gen_helper_neon_narrow_sat_s32
,
8210 gen_helper_neon_unarrow_sat32
},
8213 static NeonGenNarrowEnvFn
* const unsigned_narrow_fns
[4] = {
8214 gen_helper_neon_narrow_sat_u8
,
8215 gen_helper_neon_narrow_sat_u16
,
8216 gen_helper_neon_narrow_sat_u32
,
8219 NeonGenNarrowEnvFn
*narrowfn
;
8225 if (extract32(immh
, 3, 1)) {
8226 unallocated_encoding(s
);
8230 if (!fp_access_check(s
)) {
8235 narrowfn
= unsigned_narrow_fns
[size
];
8237 narrowfn
= signed_narrow_fns
[size
][is_u_narrow
? 1 : 0];
8240 tcg_rn
= tcg_temp_new_i64();
8241 tcg_rd
= tcg_temp_new_i64();
8242 tcg_rd_narrowed
= tcg_temp_new_i32();
8243 tcg_final
= tcg_const_i64(0);
8246 uint64_t round_const
= 1ULL << (shift
- 1);
8247 tcg_round
= tcg_const_i64(round_const
);
8252 for (i
= 0; i
< elements
; i
++) {
8253 read_vec_element(s
, tcg_rn
, rn
, i
, ldop
);
8254 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
8255 false, is_u_shift
, size
+1, shift
);
8256 narrowfn(tcg_rd_narrowed
, cpu_env
, tcg_rd
);
8257 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd_narrowed
);
8258 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
8262 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
8264 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
8268 tcg_temp_free_i64(tcg_round
);
8270 tcg_temp_free_i64(tcg_rn
);
8271 tcg_temp_free_i64(tcg_rd
);
8272 tcg_temp_free_i32(tcg_rd_narrowed
);
8273 tcg_temp_free_i64(tcg_final
);
8275 clear_vec_high(s
, is_q
, rd
);
8278 /* SQSHLU, UQSHL, SQSHL: saturating left shifts */
8279 static void handle_simd_qshl(DisasContext
*s
, bool scalar
, bool is_q
,
8280 bool src_unsigned
, bool dst_unsigned
,
8281 int immh
, int immb
, int rn
, int rd
)
8283 int immhb
= immh
<< 3 | immb
;
8284 int size
= 32 - clz32(immh
) - 1;
8285 int shift
= immhb
- (8 << size
);
8289 assert(!(scalar
&& is_q
));
8292 if (!is_q
&& extract32(immh
, 3, 1)) {
8293 unallocated_encoding(s
);
8297 /* Since we use the variable-shift helpers we must
8298 * replicate the shift count into each element of
8299 * the tcg_shift value.
8303 shift
|= shift
<< 8;
8306 shift
|= shift
<< 16;
8312 g_assert_not_reached();
8316 if (!fp_access_check(s
)) {
8321 TCGv_i64 tcg_shift
= tcg_const_i64(shift
);
8322 static NeonGenTwo64OpEnvFn
* const fns
[2][2] = {
8323 { gen_helper_neon_qshl_s64
, gen_helper_neon_qshlu_s64
},
8324 { NULL
, gen_helper_neon_qshl_u64
},
8326 NeonGenTwo64OpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
];
8327 int maxpass
= is_q
? 2 : 1;
8329 for (pass
= 0; pass
< maxpass
; pass
++) {
8330 TCGv_i64 tcg_op
= tcg_temp_new_i64();
8332 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
8333 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
8334 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
8336 tcg_temp_free_i64(tcg_op
);
8338 tcg_temp_free_i64(tcg_shift
);
8339 clear_vec_high(s
, is_q
, rd
);
8341 TCGv_i32 tcg_shift
= tcg_const_i32(shift
);
8342 static NeonGenTwoOpEnvFn
* const fns
[2][2][3] = {
8344 { gen_helper_neon_qshl_s8
,
8345 gen_helper_neon_qshl_s16
,
8346 gen_helper_neon_qshl_s32
},
8347 { gen_helper_neon_qshlu_s8
,
8348 gen_helper_neon_qshlu_s16
,
8349 gen_helper_neon_qshlu_s32
}
8351 { NULL
, NULL
, NULL
},
8352 { gen_helper_neon_qshl_u8
,
8353 gen_helper_neon_qshl_u16
,
8354 gen_helper_neon_qshl_u32
}
8357 NeonGenTwoOpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
][size
];
8358 MemOp memop
= scalar
? size
: MO_32
;
8359 int maxpass
= scalar
? 1 : is_q
? 4 : 2;
8361 for (pass
= 0; pass
< maxpass
; pass
++) {
8362 TCGv_i32 tcg_op
= tcg_temp_new_i32();
8364 read_vec_element_i32(s
, tcg_op
, rn
, pass
, memop
);
8365 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
8369 tcg_gen_ext8u_i32(tcg_op
, tcg_op
);
8372 tcg_gen_ext16u_i32(tcg_op
, tcg_op
);
8377 g_assert_not_reached();
8379 write_fp_sreg(s
, rd
, tcg_op
);
8381 write_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
8384 tcg_temp_free_i32(tcg_op
);
8386 tcg_temp_free_i32(tcg_shift
);
8389 clear_vec_high(s
, is_q
, rd
);
8394 /* Common vector code for handling integer to FP conversion */
8395 static void handle_simd_intfp_conv(DisasContext
*s
, int rd
, int rn
,
8396 int elements
, int is_signed
,
8397 int fracbits
, int size
)
8399 TCGv_ptr tcg_fpst
= get_fpstatus_ptr(size
== MO_16
);
8400 TCGv_i32 tcg_shift
= NULL
;
8402 MemOp mop
= size
| (is_signed
? MO_SIGN
: 0);
8405 if (fracbits
|| size
== MO_64
) {
8406 tcg_shift
= tcg_const_i32(fracbits
);
8409 if (size
== MO_64
) {
8410 TCGv_i64 tcg_int64
= tcg_temp_new_i64();
8411 TCGv_i64 tcg_double
= tcg_temp_new_i64();
8413 for (pass
= 0; pass
< elements
; pass
++) {
8414 read_vec_element(s
, tcg_int64
, rn
, pass
, mop
);
8417 gen_helper_vfp_sqtod(tcg_double
, tcg_int64
,
8418 tcg_shift
, tcg_fpst
);
8420 gen_helper_vfp_uqtod(tcg_double
, tcg_int64
,
8421 tcg_shift
, tcg_fpst
);
8423 if (elements
== 1) {
8424 write_fp_dreg(s
, rd
, tcg_double
);
8426 write_vec_element(s
, tcg_double
, rd
, pass
, MO_64
);
8430 tcg_temp_free_i64(tcg_int64
);
8431 tcg_temp_free_i64(tcg_double
);
8434 TCGv_i32 tcg_int32
= tcg_temp_new_i32();
8435 TCGv_i32 tcg_float
= tcg_temp_new_i32();
8437 for (pass
= 0; pass
< elements
; pass
++) {
8438 read_vec_element_i32(s
, tcg_int32
, rn
, pass
, mop
);
8444 gen_helper_vfp_sltos(tcg_float
, tcg_int32
,
8445 tcg_shift
, tcg_fpst
);
8447 gen_helper_vfp_ultos(tcg_float
, tcg_int32
,
8448 tcg_shift
, tcg_fpst
);
8452 gen_helper_vfp_sitos(tcg_float
, tcg_int32
, tcg_fpst
);
8454 gen_helper_vfp_uitos(tcg_float
, tcg_int32
, tcg_fpst
);
8461 gen_helper_vfp_sltoh(tcg_float
, tcg_int32
,
8462 tcg_shift
, tcg_fpst
);
8464 gen_helper_vfp_ultoh(tcg_float
, tcg_int32
,
8465 tcg_shift
, tcg_fpst
);
8469 gen_helper_vfp_sitoh(tcg_float
, tcg_int32
, tcg_fpst
);
8471 gen_helper_vfp_uitoh(tcg_float
, tcg_int32
, tcg_fpst
);
8476 g_assert_not_reached();
8479 if (elements
== 1) {
8480 write_fp_sreg(s
, rd
, tcg_float
);
8482 write_vec_element_i32(s
, tcg_float
, rd
, pass
, size
);
8486 tcg_temp_free_i32(tcg_int32
);
8487 tcg_temp_free_i32(tcg_float
);
8490 tcg_temp_free_ptr(tcg_fpst
);
8492 tcg_temp_free_i32(tcg_shift
);
8495 clear_vec_high(s
, elements
<< size
== 16, rd
);
8498 /* UCVTF/SCVTF - Integer to FP conversion */
8499 static void handle_simd_shift_intfp_conv(DisasContext
*s
, bool is_scalar
,
8500 bool is_q
, bool is_u
,
8501 int immh
, int immb
, int opcode
,
8504 int size
, elements
, fracbits
;
8505 int immhb
= immh
<< 3 | immb
;
8509 if (!is_scalar
&& !is_q
) {
8510 unallocated_encoding(s
);
8513 } else if (immh
& 4) {
8515 } else if (immh
& 2) {
8517 if (!dc_isar_feature(aa64_fp16
, s
)) {
8518 unallocated_encoding(s
);
8522 /* immh == 0 would be a failure of the decode logic */
8523 g_assert(immh
== 1);
8524 unallocated_encoding(s
);
8531 elements
= (8 << is_q
) >> size
;
8533 fracbits
= (16 << size
) - immhb
;
8535 if (!fp_access_check(s
)) {
8539 handle_simd_intfp_conv(s
, rd
, rn
, elements
, !is_u
, fracbits
, size
);
8542 /* FCVTZS, FVCVTZU - FP to fixedpoint conversion */
8543 static void handle_simd_shift_fpint_conv(DisasContext
*s
, bool is_scalar
,
8544 bool is_q
, bool is_u
,
8545 int immh
, int immb
, int rn
, int rd
)
8547 int immhb
= immh
<< 3 | immb
;
8548 int pass
, size
, fracbits
;
8549 TCGv_ptr tcg_fpstatus
;
8550 TCGv_i32 tcg_rmode
, tcg_shift
;
8554 if (!is_scalar
&& !is_q
) {
8555 unallocated_encoding(s
);
8558 } else if (immh
& 0x4) {
8560 } else if (immh
& 0x2) {
8562 if (!dc_isar_feature(aa64_fp16
, s
)) {
8563 unallocated_encoding(s
);
8567 /* Should have split out AdvSIMD modified immediate earlier. */
8569 unallocated_encoding(s
);
8573 if (!fp_access_check(s
)) {
8577 assert(!(is_scalar
&& is_q
));
8579 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO
));
8580 tcg_fpstatus
= get_fpstatus_ptr(size
== MO_16
);
8581 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
8582 fracbits
= (16 << size
) - immhb
;
8583 tcg_shift
= tcg_const_i32(fracbits
);
8585 if (size
== MO_64
) {
8586 int maxpass
= is_scalar
? 1 : 2;
8588 for (pass
= 0; pass
< maxpass
; pass
++) {
8589 TCGv_i64 tcg_op
= tcg_temp_new_i64();
8591 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
8593 gen_helper_vfp_touqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
8595 gen_helper_vfp_tosqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
8597 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
8598 tcg_temp_free_i64(tcg_op
);
8600 clear_vec_high(s
, is_q
, rd
);
8602 void (*fn
)(TCGv_i32
, TCGv_i32
, TCGv_i32
, TCGv_ptr
);
8603 int maxpass
= is_scalar
? 1 : ((8 << is_q
) >> size
);
8608 fn
= gen_helper_vfp_touhh
;
8610 fn
= gen_helper_vfp_toshh
;
8615 fn
= gen_helper_vfp_touls
;
8617 fn
= gen_helper_vfp_tosls
;
8621 g_assert_not_reached();
8624 for (pass
= 0; pass
< maxpass
; pass
++) {
8625 TCGv_i32 tcg_op
= tcg_temp_new_i32();
8627 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
8628 fn(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
8630 write_fp_sreg(s
, rd
, tcg_op
);
8632 write_vec_element_i32(s
, tcg_op
, rd
, pass
, size
);
8634 tcg_temp_free_i32(tcg_op
);
8637 clear_vec_high(s
, is_q
, rd
);
8641 tcg_temp_free_ptr(tcg_fpstatus
);
8642 tcg_temp_free_i32(tcg_shift
);
8643 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
8644 tcg_temp_free_i32(tcg_rmode
);
8647 /* AdvSIMD scalar shift by immediate
8648 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
8649 * +-----+---+-------------+------+------+--------+---+------+------+
8650 * | 0 1 | U | 1 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
8651 * +-----+---+-------------+------+------+--------+---+------+------+
8653 * This is the scalar version so it works on a fixed sized registers
8655 static void disas_simd_scalar_shift_imm(DisasContext
*s
, uint32_t insn
)
8657 int rd
= extract32(insn
, 0, 5);
8658 int rn
= extract32(insn
, 5, 5);
8659 int opcode
= extract32(insn
, 11, 5);
8660 int immb
= extract32(insn
, 16, 3);
8661 int immh
= extract32(insn
, 19, 4);
8662 bool is_u
= extract32(insn
, 29, 1);
8665 unallocated_encoding(s
);
8670 case 0x08: /* SRI */
8672 unallocated_encoding(s
);
8676 case 0x00: /* SSHR / USHR */
8677 case 0x02: /* SSRA / USRA */
8678 case 0x04: /* SRSHR / URSHR */
8679 case 0x06: /* SRSRA / URSRA */
8680 handle_scalar_simd_shri(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
8682 case 0x0a: /* SHL / SLI */
8683 handle_scalar_simd_shli(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
8685 case 0x1c: /* SCVTF, UCVTF */
8686 handle_simd_shift_intfp_conv(s
, true, false, is_u
, immh
, immb
,
8689 case 0x10: /* SQSHRUN, SQSHRUN2 */
8690 case 0x11: /* SQRSHRUN, SQRSHRUN2 */
8692 unallocated_encoding(s
);
8695 handle_vec_simd_sqshrn(s
, true, false, false, true,
8696 immh
, immb
, opcode
, rn
, rd
);
8698 case 0x12: /* SQSHRN, SQSHRN2, UQSHRN */
8699 case 0x13: /* SQRSHRN, SQRSHRN2, UQRSHRN, UQRSHRN2 */
8700 handle_vec_simd_sqshrn(s
, true, false, is_u
, is_u
,
8701 immh
, immb
, opcode
, rn
, rd
);
8703 case 0xc: /* SQSHLU */
8705 unallocated_encoding(s
);
8708 handle_simd_qshl(s
, true, false, false, true, immh
, immb
, rn
, rd
);
8710 case 0xe: /* SQSHL, UQSHL */
8711 handle_simd_qshl(s
, true, false, is_u
, is_u
, immh
, immb
, rn
, rd
);
8713 case 0x1f: /* FCVTZS, FCVTZU */
8714 handle_simd_shift_fpint_conv(s
, true, false, is_u
, immh
, immb
, rn
, rd
);
8717 unallocated_encoding(s
);
8722 /* AdvSIMD scalar three different
8723 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
8724 * +-----+---+-----------+------+---+------+--------+-----+------+------+
8725 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
8726 * +-----+---+-----------+------+---+------+--------+-----+------+------+
8728 static void disas_simd_scalar_three_reg_diff(DisasContext
*s
, uint32_t insn
)
8730 bool is_u
= extract32(insn
, 29, 1);
8731 int size
= extract32(insn
, 22, 2);
8732 int opcode
= extract32(insn
, 12, 4);
8733 int rm
= extract32(insn
, 16, 5);
8734 int rn
= extract32(insn
, 5, 5);
8735 int rd
= extract32(insn
, 0, 5);
8738 unallocated_encoding(s
);
8743 case 0x9: /* SQDMLAL, SQDMLAL2 */
8744 case 0xb: /* SQDMLSL, SQDMLSL2 */
8745 case 0xd: /* SQDMULL, SQDMULL2 */
8746 if (size
== 0 || size
== 3) {
8747 unallocated_encoding(s
);
8752 unallocated_encoding(s
);
8756 if (!fp_access_check(s
)) {
8761 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8762 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8763 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8765 read_vec_element(s
, tcg_op1
, rn
, 0, MO_32
| MO_SIGN
);
8766 read_vec_element(s
, tcg_op2
, rm
, 0, MO_32
| MO_SIGN
);
8768 tcg_gen_mul_i64(tcg_res
, tcg_op1
, tcg_op2
);
8769 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
8772 case 0xd: /* SQDMULL, SQDMULL2 */
8774 case 0xb: /* SQDMLSL, SQDMLSL2 */
8775 tcg_gen_neg_i64(tcg_res
, tcg_res
);
8777 case 0x9: /* SQDMLAL, SQDMLAL2 */
8778 read_vec_element(s
, tcg_op1
, rd
, 0, MO_64
);
8779 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
,
8783 g_assert_not_reached();
8786 write_fp_dreg(s
, rd
, tcg_res
);
8788 tcg_temp_free_i64(tcg_op1
);
8789 tcg_temp_free_i64(tcg_op2
);
8790 tcg_temp_free_i64(tcg_res
);
8792 TCGv_i32 tcg_op1
= read_fp_hreg(s
, rn
);
8793 TCGv_i32 tcg_op2
= read_fp_hreg(s
, rm
);
8794 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8796 gen_helper_neon_mull_s16(tcg_res
, tcg_op1
, tcg_op2
);
8797 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
8800 case 0xd: /* SQDMULL, SQDMULL2 */
8802 case 0xb: /* SQDMLSL, SQDMLSL2 */
8803 gen_helper_neon_negl_u32(tcg_res
, tcg_res
);
8805 case 0x9: /* SQDMLAL, SQDMLAL2 */
8807 TCGv_i64 tcg_op3
= tcg_temp_new_i64();
8808 read_vec_element(s
, tcg_op3
, rd
, 0, MO_32
);
8809 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
,
8811 tcg_temp_free_i64(tcg_op3
);
8815 g_assert_not_reached();
8818 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
8819 write_fp_dreg(s
, rd
, tcg_res
);
8821 tcg_temp_free_i32(tcg_op1
);
8822 tcg_temp_free_i32(tcg_op2
);
8823 tcg_temp_free_i64(tcg_res
);
8827 static void handle_3same_64(DisasContext
*s
, int opcode
, bool u
,
8828 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
, TCGv_i64 tcg_rm
)
8830 /* Handle 64x64->64 opcodes which are shared between the scalar
8831 * and vector 3-same groups. We cover every opcode where size == 3
8832 * is valid in either the three-reg-same (integer, not pairwise)
8833 * or scalar-three-reg-same groups.
8838 case 0x1: /* SQADD */
8840 gen_helper_neon_qadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8842 gen_helper_neon_qadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8845 case 0x5: /* SQSUB */
8847 gen_helper_neon_qsub_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8849 gen_helper_neon_qsub_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8852 case 0x6: /* CMGT, CMHI */
8853 /* 64 bit integer comparison, result = test ? (2^64 - 1) : 0.
8854 * We implement this using setcond (test) and then negating.
8856 cond
= u
? TCG_COND_GTU
: TCG_COND_GT
;
8858 tcg_gen_setcond_i64(cond
, tcg_rd
, tcg_rn
, tcg_rm
);
8859 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
8861 case 0x7: /* CMGE, CMHS */
8862 cond
= u
? TCG_COND_GEU
: TCG_COND_GE
;
8864 case 0x11: /* CMTST, CMEQ */
8869 gen_cmtst_i64(tcg_rd
, tcg_rn
, tcg_rm
);
8871 case 0x8: /* SSHL, USHL */
8873 gen_ushl_i64(tcg_rd
, tcg_rn
, tcg_rm
);
8875 gen_sshl_i64(tcg_rd
, tcg_rn
, tcg_rm
);
8878 case 0x9: /* SQSHL, UQSHL */
8880 gen_helper_neon_qshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8882 gen_helper_neon_qshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8885 case 0xa: /* SRSHL, URSHL */
8887 gen_helper_neon_rshl_u64(tcg_rd
, tcg_rn
, tcg_rm
);
8889 gen_helper_neon_rshl_s64(tcg_rd
, tcg_rn
, tcg_rm
);
8892 case 0xb: /* SQRSHL, UQRSHL */
8894 gen_helper_neon_qrshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8896 gen_helper_neon_qrshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8899 case 0x10: /* ADD, SUB */
8901 tcg_gen_sub_i64(tcg_rd
, tcg_rn
, tcg_rm
);
8903 tcg_gen_add_i64(tcg_rd
, tcg_rn
, tcg_rm
);
8907 g_assert_not_reached();
8911 /* Handle the 3-same-operands float operations; shared by the scalar
8912 * and vector encodings. The caller must filter out any encodings
8913 * not allocated for the encoding it is dealing with.
8915 static void handle_3same_float(DisasContext
*s
, int size
, int elements
,
8916 int fpopcode
, int rd
, int rn
, int rm
)
8919 TCGv_ptr fpst
= get_fpstatus_ptr(false);
8921 for (pass
= 0; pass
< elements
; pass
++) {
8924 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8925 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8926 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8928 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
8929 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
8932 case 0x39: /* FMLS */
8933 /* As usual for ARM, separate negation for fused multiply-add */
8934 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
8936 case 0x19: /* FMLA */
8937 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
8938 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
,
8941 case 0x18: /* FMAXNM */
8942 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8944 case 0x1a: /* FADD */
8945 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8947 case 0x1b: /* FMULX */
8948 gen_helper_vfp_mulxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8950 case 0x1c: /* FCMEQ */
8951 gen_helper_neon_ceq_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8953 case 0x1e: /* FMAX */
8954 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8956 case 0x1f: /* FRECPS */
8957 gen_helper_recpsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8959 case 0x38: /* FMINNM */
8960 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8962 case 0x3a: /* FSUB */
8963 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8965 case 0x3e: /* FMIN */
8966 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8968 case 0x3f: /* FRSQRTS */
8969 gen_helper_rsqrtsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8971 case 0x5b: /* FMUL */
8972 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8974 case 0x5c: /* FCMGE */
8975 gen_helper_neon_cge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8977 case 0x5d: /* FACGE */
8978 gen_helper_neon_acge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8980 case 0x5f: /* FDIV */
8981 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8983 case 0x7a: /* FABD */
8984 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8985 gen_helper_vfp_absd(tcg_res
, tcg_res
);
8987 case 0x7c: /* FCMGT */
8988 gen_helper_neon_cgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8990 case 0x7d: /* FACGT */
8991 gen_helper_neon_acgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8994 g_assert_not_reached();
8997 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
8999 tcg_temp_free_i64(tcg_res
);
9000 tcg_temp_free_i64(tcg_op1
);
9001 tcg_temp_free_i64(tcg_op2
);
9004 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
9005 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
9006 TCGv_i32 tcg_res
= tcg_temp_new_i32();
9008 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
9009 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
9012 case 0x39: /* FMLS */
9013 /* As usual for ARM, separate negation for fused multiply-add */
9014 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
9016 case 0x19: /* FMLA */
9017 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
9018 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
,
9021 case 0x1a: /* FADD */
9022 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9024 case 0x1b: /* FMULX */
9025 gen_helper_vfp_mulxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9027 case 0x1c: /* FCMEQ */
9028 gen_helper_neon_ceq_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9030 case 0x1e: /* FMAX */
9031 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9033 case 0x1f: /* FRECPS */
9034 gen_helper_recpsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9036 case 0x18: /* FMAXNM */
9037 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9039 case 0x38: /* FMINNM */
9040 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9042 case 0x3a: /* FSUB */
9043 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9045 case 0x3e: /* FMIN */
9046 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9048 case 0x3f: /* FRSQRTS */
9049 gen_helper_rsqrtsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9051 case 0x5b: /* FMUL */
9052 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9054 case 0x5c: /* FCMGE */
9055 gen_helper_neon_cge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9057 case 0x5d: /* FACGE */
9058 gen_helper_neon_acge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9060 case 0x5f: /* FDIV */
9061 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9063 case 0x7a: /* FABD */
9064 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9065 gen_helper_vfp_abss(tcg_res
, tcg_res
);
9067 case 0x7c: /* FCMGT */
9068 gen_helper_neon_cgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9070 case 0x7d: /* FACGT */
9071 gen_helper_neon_acgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9074 g_assert_not_reached();
9077 if (elements
== 1) {
9078 /* scalar single so clear high part */
9079 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
9081 tcg_gen_extu_i32_i64(tcg_tmp
, tcg_res
);
9082 write_vec_element(s
, tcg_tmp
, rd
, pass
, MO_64
);
9083 tcg_temp_free_i64(tcg_tmp
);
9085 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
9088 tcg_temp_free_i32(tcg_res
);
9089 tcg_temp_free_i32(tcg_op1
);
9090 tcg_temp_free_i32(tcg_op2
);
9094 tcg_temp_free_ptr(fpst
);
9096 clear_vec_high(s
, elements
* (size
? 8 : 4) > 8, rd
);
9099 /* AdvSIMD scalar three same
9100 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
9101 * +-----+---+-----------+------+---+------+--------+---+------+------+
9102 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
9103 * +-----+---+-----------+------+---+------+--------+---+------+------+
9105 static void disas_simd_scalar_three_reg_same(DisasContext
*s
, uint32_t insn
)
9107 int rd
= extract32(insn
, 0, 5);
9108 int rn
= extract32(insn
, 5, 5);
9109 int opcode
= extract32(insn
, 11, 5);
9110 int rm
= extract32(insn
, 16, 5);
9111 int size
= extract32(insn
, 22, 2);
9112 bool u
= extract32(insn
, 29, 1);
9115 if (opcode
>= 0x18) {
9116 /* Floating point: U, size[1] and opcode indicate operation */
9117 int fpopcode
= opcode
| (extract32(size
, 1, 1) << 5) | (u
<< 6);
9119 case 0x1b: /* FMULX */
9120 case 0x1f: /* FRECPS */
9121 case 0x3f: /* FRSQRTS */
9122 case 0x5d: /* FACGE */
9123 case 0x7d: /* FACGT */
9124 case 0x1c: /* FCMEQ */
9125 case 0x5c: /* FCMGE */
9126 case 0x7c: /* FCMGT */
9127 case 0x7a: /* FABD */
9130 unallocated_encoding(s
);
9134 if (!fp_access_check(s
)) {
9138 handle_3same_float(s
, extract32(size
, 0, 1), 1, fpopcode
, rd
, rn
, rm
);
9143 case 0x1: /* SQADD, UQADD */
9144 case 0x5: /* SQSUB, UQSUB */
9145 case 0x9: /* SQSHL, UQSHL */
9146 case 0xb: /* SQRSHL, UQRSHL */
9148 case 0x8: /* SSHL, USHL */
9149 case 0xa: /* SRSHL, URSHL */
9150 case 0x6: /* CMGT, CMHI */
9151 case 0x7: /* CMGE, CMHS */
9152 case 0x11: /* CMTST, CMEQ */
9153 case 0x10: /* ADD, SUB (vector) */
9155 unallocated_encoding(s
);
9159 case 0x16: /* SQDMULH, SQRDMULH (vector) */
9160 if (size
!= 1 && size
!= 2) {
9161 unallocated_encoding(s
);
9166 unallocated_encoding(s
);
9170 if (!fp_access_check(s
)) {
9174 tcg_rd
= tcg_temp_new_i64();
9177 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
9178 TCGv_i64 tcg_rm
= read_fp_dreg(s
, rm
);
9180 handle_3same_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rm
);
9181 tcg_temp_free_i64(tcg_rn
);
9182 tcg_temp_free_i64(tcg_rm
);
9184 /* Do a single operation on the lowest element in the vector.
9185 * We use the standard Neon helpers and rely on 0 OP 0 == 0 with
9186 * no side effects for all these operations.
9187 * OPTME: special-purpose helpers would avoid doing some
9188 * unnecessary work in the helper for the 8 and 16 bit cases.
9190 NeonGenTwoOpEnvFn
*genenvfn
;
9191 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
9192 TCGv_i32 tcg_rm
= tcg_temp_new_i32();
9193 TCGv_i32 tcg_rd32
= tcg_temp_new_i32();
9195 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
9196 read_vec_element_i32(s
, tcg_rm
, rm
, 0, size
);
9199 case 0x1: /* SQADD, UQADD */
9201 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9202 { gen_helper_neon_qadd_s8
, gen_helper_neon_qadd_u8
},
9203 { gen_helper_neon_qadd_s16
, gen_helper_neon_qadd_u16
},
9204 { gen_helper_neon_qadd_s32
, gen_helper_neon_qadd_u32
},
9206 genenvfn
= fns
[size
][u
];
9209 case 0x5: /* SQSUB, UQSUB */
9211 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9212 { gen_helper_neon_qsub_s8
, gen_helper_neon_qsub_u8
},
9213 { gen_helper_neon_qsub_s16
, gen_helper_neon_qsub_u16
},
9214 { gen_helper_neon_qsub_s32
, gen_helper_neon_qsub_u32
},
9216 genenvfn
= fns
[size
][u
];
9219 case 0x9: /* SQSHL, UQSHL */
9221 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9222 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
9223 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
9224 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
9226 genenvfn
= fns
[size
][u
];
9229 case 0xb: /* SQRSHL, UQRSHL */
9231 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9232 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
9233 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
9234 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
9236 genenvfn
= fns
[size
][u
];
9239 case 0x16: /* SQDMULH, SQRDMULH */
9241 static NeonGenTwoOpEnvFn
* const fns
[2][2] = {
9242 { gen_helper_neon_qdmulh_s16
, gen_helper_neon_qrdmulh_s16
},
9243 { gen_helper_neon_qdmulh_s32
, gen_helper_neon_qrdmulh_s32
},
9245 assert(size
== 1 || size
== 2);
9246 genenvfn
= fns
[size
- 1][u
];
9250 g_assert_not_reached();
9253 genenvfn(tcg_rd32
, cpu_env
, tcg_rn
, tcg_rm
);
9254 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd32
);
9255 tcg_temp_free_i32(tcg_rd32
);
9256 tcg_temp_free_i32(tcg_rn
);
9257 tcg_temp_free_i32(tcg_rm
);
9260 write_fp_dreg(s
, rd
, tcg_rd
);
9262 tcg_temp_free_i64(tcg_rd
);
9265 /* AdvSIMD scalar three same FP16
9266 * 31 30 29 28 24 23 22 21 20 16 15 14 13 11 10 9 5 4 0
9267 * +-----+---+-----------+---+-----+------+-----+--------+---+----+----+
9268 * | 0 1 | U | 1 1 1 1 0 | a | 1 0 | Rm | 0 0 | opcode | 1 | Rn | Rd |
9269 * +-----+---+-----------+---+-----+------+-----+--------+---+----+----+
9270 * v: 0101 1110 0100 0000 0000 0100 0000 0000 => 5e400400
9271 * m: 1101 1111 0110 0000 1100 0100 0000 0000 => df60c400
9273 static void disas_simd_scalar_three_reg_same_fp16(DisasContext
*s
,
9276 int rd
= extract32(insn
, 0, 5);
9277 int rn
= extract32(insn
, 5, 5);
9278 int opcode
= extract32(insn
, 11, 3);
9279 int rm
= extract32(insn
, 16, 5);
9280 bool u
= extract32(insn
, 29, 1);
9281 bool a
= extract32(insn
, 23, 1);
9282 int fpopcode
= opcode
| (a
<< 3) | (u
<< 4);
9289 case 0x03: /* FMULX */
9290 case 0x04: /* FCMEQ (reg) */
9291 case 0x07: /* FRECPS */
9292 case 0x0f: /* FRSQRTS */
9293 case 0x14: /* FCMGE (reg) */
9294 case 0x15: /* FACGE */
9295 case 0x1a: /* FABD */
9296 case 0x1c: /* FCMGT (reg) */
9297 case 0x1d: /* FACGT */
9300 unallocated_encoding(s
);
9304 if (!dc_isar_feature(aa64_fp16
, s
)) {
9305 unallocated_encoding(s
);
9308 if (!fp_access_check(s
)) {
9312 fpst
= get_fpstatus_ptr(true);
9314 tcg_op1
= read_fp_hreg(s
, rn
);
9315 tcg_op2
= read_fp_hreg(s
, rm
);
9316 tcg_res
= tcg_temp_new_i32();
9319 case 0x03: /* FMULX */
9320 gen_helper_advsimd_mulxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9322 case 0x04: /* FCMEQ (reg) */
9323 gen_helper_advsimd_ceq_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9325 case 0x07: /* FRECPS */
9326 gen_helper_recpsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9328 case 0x0f: /* FRSQRTS */
9329 gen_helper_rsqrtsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9331 case 0x14: /* FCMGE (reg) */
9332 gen_helper_advsimd_cge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9334 case 0x15: /* FACGE */
9335 gen_helper_advsimd_acge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9337 case 0x1a: /* FABD */
9338 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9339 tcg_gen_andi_i32(tcg_res
, tcg_res
, 0x7fff);
9341 case 0x1c: /* FCMGT (reg) */
9342 gen_helper_advsimd_cgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9344 case 0x1d: /* FACGT */
9345 gen_helper_advsimd_acgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9348 g_assert_not_reached();
9351 write_fp_sreg(s
, rd
, tcg_res
);
9354 tcg_temp_free_i32(tcg_res
);
9355 tcg_temp_free_i32(tcg_op1
);
9356 tcg_temp_free_i32(tcg_op2
);
9357 tcg_temp_free_ptr(fpst
);
9360 /* AdvSIMD scalar three same extra
9361 * 31 30 29 28 24 23 22 21 20 16 15 14 11 10 9 5 4 0
9362 * +-----+---+-----------+------+---+------+---+--------+---+----+----+
9363 * | 0 1 | U | 1 1 1 1 0 | size | 0 | Rm | 1 | opcode | 1 | Rn | Rd |
9364 * +-----+---+-----------+------+---+------+---+--------+---+----+----+
9366 static void disas_simd_scalar_three_reg_same_extra(DisasContext
*s
,
9369 int rd
= extract32(insn
, 0, 5);
9370 int rn
= extract32(insn
, 5, 5);
9371 int opcode
= extract32(insn
, 11, 4);
9372 int rm
= extract32(insn
, 16, 5);
9373 int size
= extract32(insn
, 22, 2);
9374 bool u
= extract32(insn
, 29, 1);
9375 TCGv_i32 ele1
, ele2
, ele3
;
9379 switch (u
* 16 + opcode
) {
9380 case 0x10: /* SQRDMLAH (vector) */
9381 case 0x11: /* SQRDMLSH (vector) */
9382 if (size
!= 1 && size
!= 2) {
9383 unallocated_encoding(s
);
9386 feature
= dc_isar_feature(aa64_rdm
, s
);
9389 unallocated_encoding(s
);
9393 unallocated_encoding(s
);
9396 if (!fp_access_check(s
)) {
9400 /* Do a single operation on the lowest element in the vector.
9401 * We use the standard Neon helpers and rely on 0 OP 0 == 0
9402 * with no side effects for all these operations.
9403 * OPTME: special-purpose helpers would avoid doing some
9404 * unnecessary work in the helper for the 16 bit cases.
9406 ele1
= tcg_temp_new_i32();
9407 ele2
= tcg_temp_new_i32();
9408 ele3
= tcg_temp_new_i32();
9410 read_vec_element_i32(s
, ele1
, rn
, 0, size
);
9411 read_vec_element_i32(s
, ele2
, rm
, 0, size
);
9412 read_vec_element_i32(s
, ele3
, rd
, 0, size
);
9415 case 0x0: /* SQRDMLAH */
9417 gen_helper_neon_qrdmlah_s16(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9419 gen_helper_neon_qrdmlah_s32(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9422 case 0x1: /* SQRDMLSH */
9424 gen_helper_neon_qrdmlsh_s16(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9426 gen_helper_neon_qrdmlsh_s32(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9430 g_assert_not_reached();
9432 tcg_temp_free_i32(ele1
);
9433 tcg_temp_free_i32(ele2
);
9435 res
= tcg_temp_new_i64();
9436 tcg_gen_extu_i32_i64(res
, ele3
);
9437 tcg_temp_free_i32(ele3
);
9439 write_fp_dreg(s
, rd
, res
);
9440 tcg_temp_free_i64(res
);
9443 static void handle_2misc_64(DisasContext
*s
, int opcode
, bool u
,
9444 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
,
9445 TCGv_i32 tcg_rmode
, TCGv_ptr tcg_fpstatus
)
9447 /* Handle 64->64 opcodes which are shared between the scalar and
9448 * vector 2-reg-misc groups. We cover every integer opcode where size == 3
9449 * is valid in either group and also the double-precision fp ops.
9450 * The caller only need provide tcg_rmode and tcg_fpstatus if the op
9456 case 0x4: /* CLS, CLZ */
9458 tcg_gen_clzi_i64(tcg_rd
, tcg_rn
, 64);
9460 tcg_gen_clrsb_i64(tcg_rd
, tcg_rn
);
9464 /* This opcode is shared with CNT and RBIT but we have earlier
9465 * enforced that size == 3 if and only if this is the NOT insn.
9467 tcg_gen_not_i64(tcg_rd
, tcg_rn
);
9469 case 0x7: /* SQABS, SQNEG */
9471 gen_helper_neon_qneg_s64(tcg_rd
, cpu_env
, tcg_rn
);
9473 gen_helper_neon_qabs_s64(tcg_rd
, cpu_env
, tcg_rn
);
9476 case 0xa: /* CMLT */
9477 /* 64 bit integer comparison against zero, result is
9478 * test ? (2^64 - 1) : 0. We implement via setcond(!test) and
9483 tcg_gen_setcondi_i64(cond
, tcg_rd
, tcg_rn
, 0);
9484 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
9486 case 0x8: /* CMGT, CMGE */
9487 cond
= u
? TCG_COND_GE
: TCG_COND_GT
;
9489 case 0x9: /* CMEQ, CMLE */
9490 cond
= u
? TCG_COND_LE
: TCG_COND_EQ
;
9492 case 0xb: /* ABS, NEG */
9494 tcg_gen_neg_i64(tcg_rd
, tcg_rn
);
9496 tcg_gen_abs_i64(tcg_rd
, tcg_rn
);
9499 case 0x2f: /* FABS */
9500 gen_helper_vfp_absd(tcg_rd
, tcg_rn
);
9502 case 0x6f: /* FNEG */
9503 gen_helper_vfp_negd(tcg_rd
, tcg_rn
);
9505 case 0x7f: /* FSQRT */
9506 gen_helper_vfp_sqrtd(tcg_rd
, tcg_rn
, cpu_env
);
9508 case 0x1a: /* FCVTNS */
9509 case 0x1b: /* FCVTMS */
9510 case 0x1c: /* FCVTAS */
9511 case 0x3a: /* FCVTPS */
9512 case 0x3b: /* FCVTZS */
9514 TCGv_i32 tcg_shift
= tcg_const_i32(0);
9515 gen_helper_vfp_tosqd(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
9516 tcg_temp_free_i32(tcg_shift
);
9519 case 0x5a: /* FCVTNU */
9520 case 0x5b: /* FCVTMU */
9521 case 0x5c: /* FCVTAU */
9522 case 0x7a: /* FCVTPU */
9523 case 0x7b: /* FCVTZU */
9525 TCGv_i32 tcg_shift
= tcg_const_i32(0);
9526 gen_helper_vfp_touqd(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
9527 tcg_temp_free_i32(tcg_shift
);
9530 case 0x18: /* FRINTN */
9531 case 0x19: /* FRINTM */
9532 case 0x38: /* FRINTP */
9533 case 0x39: /* FRINTZ */
9534 case 0x58: /* FRINTA */
9535 case 0x79: /* FRINTI */
9536 gen_helper_rintd(tcg_rd
, tcg_rn
, tcg_fpstatus
);
9538 case 0x59: /* FRINTX */
9539 gen_helper_rintd_exact(tcg_rd
, tcg_rn
, tcg_fpstatus
);
9541 case 0x1e: /* FRINT32Z */
9542 case 0x5e: /* FRINT32X */
9543 gen_helper_frint32_d(tcg_rd
, tcg_rn
, tcg_fpstatus
);
9545 case 0x1f: /* FRINT64Z */
9546 case 0x5f: /* FRINT64X */
9547 gen_helper_frint64_d(tcg_rd
, tcg_rn
, tcg_fpstatus
);
9550 g_assert_not_reached();
9554 static void handle_2misc_fcmp_zero(DisasContext
*s
, int opcode
,
9555 bool is_scalar
, bool is_u
, bool is_q
,
9556 int size
, int rn
, int rd
)
9558 bool is_double
= (size
== MO_64
);
9561 if (!fp_access_check(s
)) {
9565 fpst
= get_fpstatus_ptr(size
== MO_16
);
9568 TCGv_i64 tcg_op
= tcg_temp_new_i64();
9569 TCGv_i64 tcg_zero
= tcg_const_i64(0);
9570 TCGv_i64 tcg_res
= tcg_temp_new_i64();
9571 NeonGenTwoDoubleOPFn
*genfn
;
9576 case 0x2e: /* FCMLT (zero) */
9579 case 0x2c: /* FCMGT (zero) */
9580 genfn
= gen_helper_neon_cgt_f64
;
9582 case 0x2d: /* FCMEQ (zero) */
9583 genfn
= gen_helper_neon_ceq_f64
;
9585 case 0x6d: /* FCMLE (zero) */
9588 case 0x6c: /* FCMGE (zero) */
9589 genfn
= gen_helper_neon_cge_f64
;
9592 g_assert_not_reached();
9595 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
9596 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
9598 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
9600 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
9602 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
9604 tcg_temp_free_i64(tcg_res
);
9605 tcg_temp_free_i64(tcg_zero
);
9606 tcg_temp_free_i64(tcg_op
);
9608 clear_vec_high(s
, !is_scalar
, rd
);
9610 TCGv_i32 tcg_op
= tcg_temp_new_i32();
9611 TCGv_i32 tcg_zero
= tcg_const_i32(0);
9612 TCGv_i32 tcg_res
= tcg_temp_new_i32();
9613 NeonGenTwoSingleOPFn
*genfn
;
9615 int pass
, maxpasses
;
9617 if (size
== MO_16
) {
9619 case 0x2e: /* FCMLT (zero) */
9622 case 0x2c: /* FCMGT (zero) */
9623 genfn
= gen_helper_advsimd_cgt_f16
;
9625 case 0x2d: /* FCMEQ (zero) */
9626 genfn
= gen_helper_advsimd_ceq_f16
;
9628 case 0x6d: /* FCMLE (zero) */
9631 case 0x6c: /* FCMGE (zero) */
9632 genfn
= gen_helper_advsimd_cge_f16
;
9635 g_assert_not_reached();
9639 case 0x2e: /* FCMLT (zero) */
9642 case 0x2c: /* FCMGT (zero) */
9643 genfn
= gen_helper_neon_cgt_f32
;
9645 case 0x2d: /* FCMEQ (zero) */
9646 genfn
= gen_helper_neon_ceq_f32
;
9648 case 0x6d: /* FCMLE (zero) */
9651 case 0x6c: /* FCMGE (zero) */
9652 genfn
= gen_helper_neon_cge_f32
;
9655 g_assert_not_reached();
9662 int vector_size
= 8 << is_q
;
9663 maxpasses
= vector_size
>> size
;
9666 for (pass
= 0; pass
< maxpasses
; pass
++) {
9667 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
9669 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
9671 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
9674 write_fp_sreg(s
, rd
, tcg_res
);
9676 write_vec_element_i32(s
, tcg_res
, rd
, pass
, size
);
9679 tcg_temp_free_i32(tcg_res
);
9680 tcg_temp_free_i32(tcg_zero
);
9681 tcg_temp_free_i32(tcg_op
);
9683 clear_vec_high(s
, is_q
, rd
);
9687 tcg_temp_free_ptr(fpst
);
9690 static void handle_2misc_reciprocal(DisasContext
*s
, int opcode
,
9691 bool is_scalar
, bool is_u
, bool is_q
,
9692 int size
, int rn
, int rd
)
9694 bool is_double
= (size
== 3);
9695 TCGv_ptr fpst
= get_fpstatus_ptr(false);
9698 TCGv_i64 tcg_op
= tcg_temp_new_i64();
9699 TCGv_i64 tcg_res
= tcg_temp_new_i64();
9702 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
9703 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
9705 case 0x3d: /* FRECPE */
9706 gen_helper_recpe_f64(tcg_res
, tcg_op
, fpst
);
9708 case 0x3f: /* FRECPX */
9709 gen_helper_frecpx_f64(tcg_res
, tcg_op
, fpst
);
9711 case 0x7d: /* FRSQRTE */
9712 gen_helper_rsqrte_f64(tcg_res
, tcg_op
, fpst
);
9715 g_assert_not_reached();
9717 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
9719 tcg_temp_free_i64(tcg_res
);
9720 tcg_temp_free_i64(tcg_op
);
9721 clear_vec_high(s
, !is_scalar
, rd
);
9723 TCGv_i32 tcg_op
= tcg_temp_new_i32();
9724 TCGv_i32 tcg_res
= tcg_temp_new_i32();
9725 int pass
, maxpasses
;
9730 maxpasses
= is_q
? 4 : 2;
9733 for (pass
= 0; pass
< maxpasses
; pass
++) {
9734 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
9737 case 0x3c: /* URECPE */
9738 gen_helper_recpe_u32(tcg_res
, tcg_op
, fpst
);
9740 case 0x3d: /* FRECPE */
9741 gen_helper_recpe_f32(tcg_res
, tcg_op
, fpst
);
9743 case 0x3f: /* FRECPX */
9744 gen_helper_frecpx_f32(tcg_res
, tcg_op
, fpst
);
9746 case 0x7d: /* FRSQRTE */
9747 gen_helper_rsqrte_f32(tcg_res
, tcg_op
, fpst
);
9750 g_assert_not_reached();
9754 write_fp_sreg(s
, rd
, tcg_res
);
9756 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
9759 tcg_temp_free_i32(tcg_res
);
9760 tcg_temp_free_i32(tcg_op
);
9762 clear_vec_high(s
, is_q
, rd
);
9765 tcg_temp_free_ptr(fpst
);
9768 static void handle_2misc_narrow(DisasContext
*s
, bool scalar
,
9769 int opcode
, bool u
, bool is_q
,
9770 int size
, int rn
, int rd
)
9772 /* Handle 2-reg-misc ops which are narrowing (so each 2*size element
9773 * in the source becomes a size element in the destination).
9776 TCGv_i32 tcg_res
[2];
9777 int destelt
= is_q
? 2 : 0;
9778 int passes
= scalar
? 1 : 2;
9781 tcg_res
[1] = tcg_const_i32(0);
9784 for (pass
= 0; pass
< passes
; pass
++) {
9785 TCGv_i64 tcg_op
= tcg_temp_new_i64();
9786 NeonGenNarrowFn
*genfn
= NULL
;
9787 NeonGenNarrowEnvFn
*genenvfn
= NULL
;
9790 read_vec_element(s
, tcg_op
, rn
, pass
, size
+ 1);
9792 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
9794 tcg_res
[pass
] = tcg_temp_new_i32();
9797 case 0x12: /* XTN, SQXTUN */
9799 static NeonGenNarrowFn
* const xtnfns
[3] = {
9800 gen_helper_neon_narrow_u8
,
9801 gen_helper_neon_narrow_u16
,
9802 tcg_gen_extrl_i64_i32
,
9804 static NeonGenNarrowEnvFn
* const sqxtunfns
[3] = {
9805 gen_helper_neon_unarrow_sat8
,
9806 gen_helper_neon_unarrow_sat16
,
9807 gen_helper_neon_unarrow_sat32
,
9810 genenvfn
= sqxtunfns
[size
];
9812 genfn
= xtnfns
[size
];
9816 case 0x14: /* SQXTN, UQXTN */
9818 static NeonGenNarrowEnvFn
* const fns
[3][2] = {
9819 { gen_helper_neon_narrow_sat_s8
,
9820 gen_helper_neon_narrow_sat_u8
},
9821 { gen_helper_neon_narrow_sat_s16
,
9822 gen_helper_neon_narrow_sat_u16
},
9823 { gen_helper_neon_narrow_sat_s32
,
9824 gen_helper_neon_narrow_sat_u32
},
9826 genenvfn
= fns
[size
][u
];
9829 case 0x16: /* FCVTN, FCVTN2 */
9830 /* 32 bit to 16 bit or 64 bit to 32 bit float conversion */
9832 gen_helper_vfp_fcvtsd(tcg_res
[pass
], tcg_op
, cpu_env
);
9834 TCGv_i32 tcg_lo
= tcg_temp_new_i32();
9835 TCGv_i32 tcg_hi
= tcg_temp_new_i32();
9836 TCGv_ptr fpst
= get_fpstatus_ptr(false);
9837 TCGv_i32 ahp
= get_ahp_flag();
9839 tcg_gen_extr_i64_i32(tcg_lo
, tcg_hi
, tcg_op
);
9840 gen_helper_vfp_fcvt_f32_to_f16(tcg_lo
, tcg_lo
, fpst
, ahp
);
9841 gen_helper_vfp_fcvt_f32_to_f16(tcg_hi
, tcg_hi
, fpst
, ahp
);
9842 tcg_gen_deposit_i32(tcg_res
[pass
], tcg_lo
, tcg_hi
, 16, 16);
9843 tcg_temp_free_i32(tcg_lo
);
9844 tcg_temp_free_i32(tcg_hi
);
9845 tcg_temp_free_ptr(fpst
);
9846 tcg_temp_free_i32(ahp
);
9849 case 0x56: /* FCVTXN, FCVTXN2 */
9850 /* 64 bit to 32 bit float conversion
9851 * with von Neumann rounding (round to odd)
9854 gen_helper_fcvtx_f64_to_f32(tcg_res
[pass
], tcg_op
, cpu_env
);
9857 g_assert_not_reached();
9861 genfn(tcg_res
[pass
], tcg_op
);
9862 } else if (genenvfn
) {
9863 genenvfn(tcg_res
[pass
], cpu_env
, tcg_op
);
9866 tcg_temp_free_i64(tcg_op
);
9869 for (pass
= 0; pass
< 2; pass
++) {
9870 write_vec_element_i32(s
, tcg_res
[pass
], rd
, destelt
+ pass
, MO_32
);
9871 tcg_temp_free_i32(tcg_res
[pass
]);
9873 clear_vec_high(s
, is_q
, rd
);
9876 /* Remaining saturating accumulating ops */
9877 static void handle_2misc_satacc(DisasContext
*s
, bool is_scalar
, bool is_u
,
9878 bool is_q
, int size
, int rn
, int rd
)
9880 bool is_double
= (size
== 3);
9883 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
9884 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
9887 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
9888 read_vec_element(s
, tcg_rn
, rn
, pass
, MO_64
);
9889 read_vec_element(s
, tcg_rd
, rd
, pass
, MO_64
);
9891 if (is_u
) { /* USQADD */
9892 gen_helper_neon_uqadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9893 } else { /* SUQADD */
9894 gen_helper_neon_sqadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9896 write_vec_element(s
, tcg_rd
, rd
, pass
, MO_64
);
9898 tcg_temp_free_i64(tcg_rd
);
9899 tcg_temp_free_i64(tcg_rn
);
9900 clear_vec_high(s
, !is_scalar
, rd
);
9902 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
9903 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
9904 int pass
, maxpasses
;
9909 maxpasses
= is_q
? 4 : 2;
9912 for (pass
= 0; pass
< maxpasses
; pass
++) {
9914 read_vec_element_i32(s
, tcg_rn
, rn
, pass
, size
);
9915 read_vec_element_i32(s
, tcg_rd
, rd
, pass
, size
);
9917 read_vec_element_i32(s
, tcg_rn
, rn
, pass
, MO_32
);
9918 read_vec_element_i32(s
, tcg_rd
, rd
, pass
, MO_32
);
9921 if (is_u
) { /* USQADD */
9924 gen_helper_neon_uqadd_s8(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9927 gen_helper_neon_uqadd_s16(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9930 gen_helper_neon_uqadd_s32(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9933 g_assert_not_reached();
9935 } else { /* SUQADD */
9938 gen_helper_neon_sqadd_u8(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9941 gen_helper_neon_sqadd_u16(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9944 gen_helper_neon_sqadd_u32(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9947 g_assert_not_reached();
9952 TCGv_i64 tcg_zero
= tcg_const_i64(0);
9953 write_vec_element(s
, tcg_zero
, rd
, 0, MO_64
);
9954 tcg_temp_free_i64(tcg_zero
);
9956 write_vec_element_i32(s
, tcg_rd
, rd
, pass
, MO_32
);
9958 tcg_temp_free_i32(tcg_rd
);
9959 tcg_temp_free_i32(tcg_rn
);
9960 clear_vec_high(s
, is_q
, rd
);
9964 /* AdvSIMD scalar two reg misc
9965 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
9966 * +-----+---+-----------+------+-----------+--------+-----+------+------+
9967 * | 0 1 | U | 1 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
9968 * +-----+---+-----------+------+-----------+--------+-----+------+------+
9970 static void disas_simd_scalar_two_reg_misc(DisasContext
*s
, uint32_t insn
)
9972 int rd
= extract32(insn
, 0, 5);
9973 int rn
= extract32(insn
, 5, 5);
9974 int opcode
= extract32(insn
, 12, 5);
9975 int size
= extract32(insn
, 22, 2);
9976 bool u
= extract32(insn
, 29, 1);
9977 bool is_fcvt
= false;
9980 TCGv_ptr tcg_fpstatus
;
9983 case 0x3: /* USQADD / SUQADD*/
9984 if (!fp_access_check(s
)) {
9987 handle_2misc_satacc(s
, true, u
, false, size
, rn
, rd
);
9989 case 0x7: /* SQABS / SQNEG */
9991 case 0xa: /* CMLT */
9993 unallocated_encoding(s
);
9997 case 0x8: /* CMGT, CMGE */
9998 case 0x9: /* CMEQ, CMLE */
9999 case 0xb: /* ABS, NEG */
10001 unallocated_encoding(s
);
10005 case 0x12: /* SQXTUN */
10007 unallocated_encoding(s
);
10011 case 0x14: /* SQXTN, UQXTN */
10013 unallocated_encoding(s
);
10016 if (!fp_access_check(s
)) {
10019 handle_2misc_narrow(s
, true, opcode
, u
, false, size
, rn
, rd
);
10022 case 0x16 ... 0x1d:
10024 /* Floating point: U, size[1] and opcode indicate operation;
10025 * size[0] indicates single or double precision.
10027 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
10028 size
= extract32(size
, 0, 1) ? 3 : 2;
10030 case 0x2c: /* FCMGT (zero) */
10031 case 0x2d: /* FCMEQ (zero) */
10032 case 0x2e: /* FCMLT (zero) */
10033 case 0x6c: /* FCMGE (zero) */
10034 case 0x6d: /* FCMLE (zero) */
10035 handle_2misc_fcmp_zero(s
, opcode
, true, u
, true, size
, rn
, rd
);
10037 case 0x1d: /* SCVTF */
10038 case 0x5d: /* UCVTF */
10040 bool is_signed
= (opcode
== 0x1d);
10041 if (!fp_access_check(s
)) {
10044 handle_simd_intfp_conv(s
, rd
, rn
, 1, is_signed
, 0, size
);
10047 case 0x3d: /* FRECPE */
10048 case 0x3f: /* FRECPX */
10049 case 0x7d: /* FRSQRTE */
10050 if (!fp_access_check(s
)) {
10053 handle_2misc_reciprocal(s
, opcode
, true, u
, true, size
, rn
, rd
);
10055 case 0x1a: /* FCVTNS */
10056 case 0x1b: /* FCVTMS */
10057 case 0x3a: /* FCVTPS */
10058 case 0x3b: /* FCVTZS */
10059 case 0x5a: /* FCVTNU */
10060 case 0x5b: /* FCVTMU */
10061 case 0x7a: /* FCVTPU */
10062 case 0x7b: /* FCVTZU */
10064 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
10066 case 0x1c: /* FCVTAS */
10067 case 0x5c: /* FCVTAU */
10068 /* TIEAWAY doesn't fit in the usual rounding mode encoding */
10070 rmode
= FPROUNDING_TIEAWAY
;
10072 case 0x56: /* FCVTXN, FCVTXN2 */
10074 unallocated_encoding(s
);
10077 if (!fp_access_check(s
)) {
10080 handle_2misc_narrow(s
, true, opcode
, u
, false, size
- 1, rn
, rd
);
10083 unallocated_encoding(s
);
10088 unallocated_encoding(s
);
10092 if (!fp_access_check(s
)) {
10097 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
10098 tcg_fpstatus
= get_fpstatus_ptr(false);
10099 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
10102 tcg_fpstatus
= NULL
;
10106 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
10107 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
10109 handle_2misc_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rmode
, tcg_fpstatus
);
10110 write_fp_dreg(s
, rd
, tcg_rd
);
10111 tcg_temp_free_i64(tcg_rd
);
10112 tcg_temp_free_i64(tcg_rn
);
10114 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
10115 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
10117 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
10120 case 0x7: /* SQABS, SQNEG */
10122 NeonGenOneOpEnvFn
*genfn
;
10123 static NeonGenOneOpEnvFn
* const fns
[3][2] = {
10124 { gen_helper_neon_qabs_s8
, gen_helper_neon_qneg_s8
},
10125 { gen_helper_neon_qabs_s16
, gen_helper_neon_qneg_s16
},
10126 { gen_helper_neon_qabs_s32
, gen_helper_neon_qneg_s32
},
10128 genfn
= fns
[size
][u
];
10129 genfn(tcg_rd
, cpu_env
, tcg_rn
);
10132 case 0x1a: /* FCVTNS */
10133 case 0x1b: /* FCVTMS */
10134 case 0x1c: /* FCVTAS */
10135 case 0x3a: /* FCVTPS */
10136 case 0x3b: /* FCVTZS */
10138 TCGv_i32 tcg_shift
= tcg_const_i32(0);
10139 gen_helper_vfp_tosls(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
10140 tcg_temp_free_i32(tcg_shift
);
10143 case 0x5a: /* FCVTNU */
10144 case 0x5b: /* FCVTMU */
10145 case 0x5c: /* FCVTAU */
10146 case 0x7a: /* FCVTPU */
10147 case 0x7b: /* FCVTZU */
10149 TCGv_i32 tcg_shift
= tcg_const_i32(0);
10150 gen_helper_vfp_touls(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
10151 tcg_temp_free_i32(tcg_shift
);
10155 g_assert_not_reached();
10158 write_fp_sreg(s
, rd
, tcg_rd
);
10159 tcg_temp_free_i32(tcg_rd
);
10160 tcg_temp_free_i32(tcg_rn
);
10164 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
10165 tcg_temp_free_i32(tcg_rmode
);
10166 tcg_temp_free_ptr(tcg_fpstatus
);
10170 /* SSHR[RA]/USHR[RA] - Vector shift right (optional rounding/accumulate) */
10171 static void handle_vec_simd_shri(DisasContext
*s
, bool is_q
, bool is_u
,
10172 int immh
, int immb
, int opcode
, int rn
, int rd
)
10174 int size
= 32 - clz32(immh
) - 1;
10175 int immhb
= immh
<< 3 | immb
;
10176 int shift
= 2 * (8 << size
) - immhb
;
10177 bool accumulate
= false;
10178 int dsize
= is_q
? 128 : 64;
10179 int esize
= 8 << size
;
10180 int elements
= dsize
/esize
;
10181 MemOp memop
= size
| (is_u
? 0 : MO_SIGN
);
10182 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
10183 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
10184 TCGv_i64 tcg_round
;
10185 uint64_t round_const
;
10188 if (extract32(immh
, 3, 1) && !is_q
) {
10189 unallocated_encoding(s
);
10192 tcg_debug_assert(size
<= 3);
10194 if (!fp_access_check(s
)) {
10199 case 0x02: /* SSRA / USRA (accumulate) */
10201 /* Shift count same as element size produces zero to add. */
10202 if (shift
== 8 << size
) {
10205 gen_gvec_op2i(s
, is_q
, rd
, rn
, shift
, &usra_op
[size
]);
10207 /* Shift count same as element size produces all sign to add. */
10208 if (shift
== 8 << size
) {
10211 gen_gvec_op2i(s
, is_q
, rd
, rn
, shift
, &ssra_op
[size
]);
10214 case 0x08: /* SRI */
10215 /* Shift count same as element size is valid but does nothing. */
10216 if (shift
== 8 << size
) {
10219 gen_gvec_op2i(s
, is_q
, rd
, rn
, shift
, &sri_op
[size
]);
10222 case 0x00: /* SSHR / USHR */
10224 if (shift
== 8 << size
) {
10225 /* Shift count the same size as element size produces zero. */
10226 tcg_gen_gvec_dup8i(vec_full_reg_offset(s
, rd
),
10227 is_q
? 16 : 8, vec_full_reg_size(s
), 0);
10229 gen_gvec_fn2i(s
, is_q
, rd
, rn
, shift
, tcg_gen_gvec_shri
, size
);
10232 /* Shift count the same size as element size produces all sign. */
10233 if (shift
== 8 << size
) {
10236 gen_gvec_fn2i(s
, is_q
, rd
, rn
, shift
, tcg_gen_gvec_sari
, size
);
10240 case 0x04: /* SRSHR / URSHR (rounding) */
10242 case 0x06: /* SRSRA / URSRA (accum + rounding) */
10246 g_assert_not_reached();
10249 round_const
= 1ULL << (shift
- 1);
10250 tcg_round
= tcg_const_i64(round_const
);
10252 for (i
= 0; i
< elements
; i
++) {
10253 read_vec_element(s
, tcg_rn
, rn
, i
, memop
);
10255 read_vec_element(s
, tcg_rd
, rd
, i
, memop
);
10258 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
10259 accumulate
, is_u
, size
, shift
);
10261 write_vec_element(s
, tcg_rd
, rd
, i
, size
);
10263 tcg_temp_free_i64(tcg_round
);
10266 clear_vec_high(s
, is_q
, rd
);
10269 /* SHL/SLI - Vector shift left */
10270 static void handle_vec_simd_shli(DisasContext
*s
, bool is_q
, bool insert
,
10271 int immh
, int immb
, int opcode
, int rn
, int rd
)
10273 int size
= 32 - clz32(immh
) - 1;
10274 int immhb
= immh
<< 3 | immb
;
10275 int shift
= immhb
- (8 << size
);
10277 /* Range of size is limited by decode: immh is a non-zero 4 bit field */
10278 assert(size
>= 0 && size
<= 3);
10280 if (extract32(immh
, 3, 1) && !is_q
) {
10281 unallocated_encoding(s
);
10285 if (!fp_access_check(s
)) {
10290 gen_gvec_op2i(s
, is_q
, rd
, rn
, shift
, &sli_op
[size
]);
10292 gen_gvec_fn2i(s
, is_q
, rd
, rn
, shift
, tcg_gen_gvec_shli
, size
);
10296 /* USHLL/SHLL - Vector shift left with widening */
10297 static void handle_vec_simd_wshli(DisasContext
*s
, bool is_q
, bool is_u
,
10298 int immh
, int immb
, int opcode
, int rn
, int rd
)
10300 int size
= 32 - clz32(immh
) - 1;
10301 int immhb
= immh
<< 3 | immb
;
10302 int shift
= immhb
- (8 << size
);
10304 int esize
= 8 << size
;
10305 int elements
= dsize
/esize
;
10306 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
10307 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
10311 unallocated_encoding(s
);
10315 if (!fp_access_check(s
)) {
10319 /* For the LL variants the store is larger than the load,
10320 * so if rd == rn we would overwrite parts of our input.
10321 * So load everything right now and use shifts in the main loop.
10323 read_vec_element(s
, tcg_rn
, rn
, is_q
? 1 : 0, MO_64
);
10325 for (i
= 0; i
< elements
; i
++) {
10326 tcg_gen_shri_i64(tcg_rd
, tcg_rn
, i
* esize
);
10327 ext_and_shift_reg(tcg_rd
, tcg_rd
, size
| (!is_u
<< 2), 0);
10328 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, shift
);
10329 write_vec_element(s
, tcg_rd
, rd
, i
, size
+ 1);
10333 /* SHRN/RSHRN - Shift right with narrowing (and potential rounding) */
10334 static void handle_vec_simd_shrn(DisasContext
*s
, bool is_q
,
10335 int immh
, int immb
, int opcode
, int rn
, int rd
)
10337 int immhb
= immh
<< 3 | immb
;
10338 int size
= 32 - clz32(immh
) - 1;
10340 int esize
= 8 << size
;
10341 int elements
= dsize
/esize
;
10342 int shift
= (2 * esize
) - immhb
;
10343 bool round
= extract32(opcode
, 0, 1);
10344 TCGv_i64 tcg_rn
, tcg_rd
, tcg_final
;
10345 TCGv_i64 tcg_round
;
10348 if (extract32(immh
, 3, 1)) {
10349 unallocated_encoding(s
);
10353 if (!fp_access_check(s
)) {
10357 tcg_rn
= tcg_temp_new_i64();
10358 tcg_rd
= tcg_temp_new_i64();
10359 tcg_final
= tcg_temp_new_i64();
10360 read_vec_element(s
, tcg_final
, rd
, is_q
? 1 : 0, MO_64
);
10363 uint64_t round_const
= 1ULL << (shift
- 1);
10364 tcg_round
= tcg_const_i64(round_const
);
10369 for (i
= 0; i
< elements
; i
++) {
10370 read_vec_element(s
, tcg_rn
, rn
, i
, size
+1);
10371 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
10372 false, true, size
+1, shift
);
10374 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
10378 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
10380 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
10383 tcg_temp_free_i64(tcg_round
);
10385 tcg_temp_free_i64(tcg_rn
);
10386 tcg_temp_free_i64(tcg_rd
);
10387 tcg_temp_free_i64(tcg_final
);
10389 clear_vec_high(s
, is_q
, rd
);
10393 /* AdvSIMD shift by immediate
10394 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
10395 * +---+---+---+-------------+------+------+--------+---+------+------+
10396 * | 0 | Q | U | 0 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
10397 * +---+---+---+-------------+------+------+--------+---+------+------+
10399 static void disas_simd_shift_imm(DisasContext
*s
, uint32_t insn
)
10401 int rd
= extract32(insn
, 0, 5);
10402 int rn
= extract32(insn
, 5, 5);
10403 int opcode
= extract32(insn
, 11, 5);
10404 int immb
= extract32(insn
, 16, 3);
10405 int immh
= extract32(insn
, 19, 4);
10406 bool is_u
= extract32(insn
, 29, 1);
10407 bool is_q
= extract32(insn
, 30, 1);
10409 /* data_proc_simd[] has sent immh == 0 to disas_simd_mod_imm. */
10413 case 0x08: /* SRI */
10415 unallocated_encoding(s
);
10419 case 0x00: /* SSHR / USHR */
10420 case 0x02: /* SSRA / USRA (accumulate) */
10421 case 0x04: /* SRSHR / URSHR (rounding) */
10422 case 0x06: /* SRSRA / URSRA (accum + rounding) */
10423 handle_vec_simd_shri(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
10425 case 0x0a: /* SHL / SLI */
10426 handle_vec_simd_shli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
10428 case 0x10: /* SHRN */
10429 case 0x11: /* RSHRN / SQRSHRUN */
10431 handle_vec_simd_sqshrn(s
, false, is_q
, false, true, immh
, immb
,
10434 handle_vec_simd_shrn(s
, is_q
, immh
, immb
, opcode
, rn
, rd
);
10437 case 0x12: /* SQSHRN / UQSHRN */
10438 case 0x13: /* SQRSHRN / UQRSHRN */
10439 handle_vec_simd_sqshrn(s
, false, is_q
, is_u
, is_u
, immh
, immb
,
10442 case 0x14: /* SSHLL / USHLL */
10443 handle_vec_simd_wshli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
10445 case 0x1c: /* SCVTF / UCVTF */
10446 handle_simd_shift_intfp_conv(s
, false, is_q
, is_u
, immh
, immb
,
10449 case 0xc: /* SQSHLU */
10451 unallocated_encoding(s
);
10454 handle_simd_qshl(s
, false, is_q
, false, true, immh
, immb
, rn
, rd
);
10456 case 0xe: /* SQSHL, UQSHL */
10457 handle_simd_qshl(s
, false, is_q
, is_u
, is_u
, immh
, immb
, rn
, rd
);
10459 case 0x1f: /* FCVTZS/ FCVTZU */
10460 handle_simd_shift_fpint_conv(s
, false, is_q
, is_u
, immh
, immb
, rn
, rd
);
10463 unallocated_encoding(s
);
10468 /* Generate code to do a "long" addition or subtraction, ie one done in
10469 * TCGv_i64 on vector lanes twice the width specified by size.
10471 static void gen_neon_addl(int size
, bool is_sub
, TCGv_i64 tcg_res
,
10472 TCGv_i64 tcg_op1
, TCGv_i64 tcg_op2
)
10474 static NeonGenTwo64OpFn
* const fns
[3][2] = {
10475 { gen_helper_neon_addl_u16
, gen_helper_neon_subl_u16
},
10476 { gen_helper_neon_addl_u32
, gen_helper_neon_subl_u32
},
10477 { tcg_gen_add_i64
, tcg_gen_sub_i64
},
10479 NeonGenTwo64OpFn
*genfn
;
10482 genfn
= fns
[size
][is_sub
];
10483 genfn(tcg_res
, tcg_op1
, tcg_op2
);
10486 static void handle_3rd_widening(DisasContext
*s
, int is_q
, int is_u
, int size
,
10487 int opcode
, int rd
, int rn
, int rm
)
10489 /* 3-reg-different widening insns: 64 x 64 -> 128 */
10490 TCGv_i64 tcg_res
[2];
10493 tcg_res
[0] = tcg_temp_new_i64();
10494 tcg_res
[1] = tcg_temp_new_i64();
10496 /* Does this op do an adding accumulate, a subtracting accumulate,
10497 * or no accumulate at all?
10515 read_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
10516 read_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
10519 /* size == 2 means two 32x32->64 operations; this is worth special
10520 * casing because we can generally handle it inline.
10523 for (pass
= 0; pass
< 2; pass
++) {
10524 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10525 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
10526 TCGv_i64 tcg_passres
;
10527 MemOp memop
= MO_32
| (is_u
? 0 : MO_SIGN
);
10529 int elt
= pass
+ is_q
* 2;
10531 read_vec_element(s
, tcg_op1
, rn
, elt
, memop
);
10532 read_vec_element(s
, tcg_op2
, rm
, elt
, memop
);
10535 tcg_passres
= tcg_res
[pass
];
10537 tcg_passres
= tcg_temp_new_i64();
10541 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
10542 tcg_gen_add_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10544 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
10545 tcg_gen_sub_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10547 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
10548 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
10550 TCGv_i64 tcg_tmp1
= tcg_temp_new_i64();
10551 TCGv_i64 tcg_tmp2
= tcg_temp_new_i64();
10553 tcg_gen_sub_i64(tcg_tmp1
, tcg_op1
, tcg_op2
);
10554 tcg_gen_sub_i64(tcg_tmp2
, tcg_op2
, tcg_op1
);
10555 tcg_gen_movcond_i64(is_u
? TCG_COND_GEU
: TCG_COND_GE
,
10557 tcg_op1
, tcg_op2
, tcg_tmp1
, tcg_tmp2
);
10558 tcg_temp_free_i64(tcg_tmp1
);
10559 tcg_temp_free_i64(tcg_tmp2
);
10562 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10563 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10564 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
10565 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10567 case 9: /* SQDMLAL, SQDMLAL2 */
10568 case 11: /* SQDMLSL, SQDMLSL2 */
10569 case 13: /* SQDMULL, SQDMULL2 */
10570 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10571 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
10572 tcg_passres
, tcg_passres
);
10575 g_assert_not_reached();
10578 if (opcode
== 9 || opcode
== 11) {
10579 /* saturating accumulate ops */
10581 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
10583 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
10584 tcg_res
[pass
], tcg_passres
);
10585 } else if (accop
> 0) {
10586 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
10587 } else if (accop
< 0) {
10588 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
10592 tcg_temp_free_i64(tcg_passres
);
10595 tcg_temp_free_i64(tcg_op1
);
10596 tcg_temp_free_i64(tcg_op2
);
10599 /* size 0 or 1, generally helper functions */
10600 for (pass
= 0; pass
< 2; pass
++) {
10601 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
10602 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
10603 TCGv_i64 tcg_passres
;
10604 int elt
= pass
+ is_q
* 2;
10606 read_vec_element_i32(s
, tcg_op1
, rn
, elt
, MO_32
);
10607 read_vec_element_i32(s
, tcg_op2
, rm
, elt
, MO_32
);
10610 tcg_passres
= tcg_res
[pass
];
10612 tcg_passres
= tcg_temp_new_i64();
10616 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
10617 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
10619 TCGv_i64 tcg_op2_64
= tcg_temp_new_i64();
10620 static NeonGenWidenFn
* const widenfns
[2][2] = {
10621 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
10622 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
10624 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
10626 widenfn(tcg_op2_64
, tcg_op2
);
10627 widenfn(tcg_passres
, tcg_op1
);
10628 gen_neon_addl(size
, (opcode
== 2), tcg_passres
,
10629 tcg_passres
, tcg_op2_64
);
10630 tcg_temp_free_i64(tcg_op2_64
);
10633 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
10634 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
10637 gen_helper_neon_abdl_u16(tcg_passres
, tcg_op1
, tcg_op2
);
10639 gen_helper_neon_abdl_s16(tcg_passres
, tcg_op1
, tcg_op2
);
10643 gen_helper_neon_abdl_u32(tcg_passres
, tcg_op1
, tcg_op2
);
10645 gen_helper_neon_abdl_s32(tcg_passres
, tcg_op1
, tcg_op2
);
10649 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10650 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10651 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
10654 gen_helper_neon_mull_u8(tcg_passres
, tcg_op1
, tcg_op2
);
10656 gen_helper_neon_mull_s8(tcg_passres
, tcg_op1
, tcg_op2
);
10660 gen_helper_neon_mull_u16(tcg_passres
, tcg_op1
, tcg_op2
);
10662 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
10666 case 9: /* SQDMLAL, SQDMLAL2 */
10667 case 11: /* SQDMLSL, SQDMLSL2 */
10668 case 13: /* SQDMULL, SQDMULL2 */
10670 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
10671 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
10672 tcg_passres
, tcg_passres
);
10675 g_assert_not_reached();
10677 tcg_temp_free_i32(tcg_op1
);
10678 tcg_temp_free_i32(tcg_op2
);
10681 if (opcode
== 9 || opcode
== 11) {
10682 /* saturating accumulate ops */
10684 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
10686 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
10690 gen_neon_addl(size
, (accop
< 0), tcg_res
[pass
],
10691 tcg_res
[pass
], tcg_passres
);
10693 tcg_temp_free_i64(tcg_passres
);
10698 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
10699 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
10700 tcg_temp_free_i64(tcg_res
[0]);
10701 tcg_temp_free_i64(tcg_res
[1]);
10704 static void handle_3rd_wide(DisasContext
*s
, int is_q
, int is_u
, int size
,
10705 int opcode
, int rd
, int rn
, int rm
)
10707 TCGv_i64 tcg_res
[2];
10708 int part
= is_q
? 2 : 0;
10711 for (pass
= 0; pass
< 2; pass
++) {
10712 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10713 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
10714 TCGv_i64 tcg_op2_wide
= tcg_temp_new_i64();
10715 static NeonGenWidenFn
* const widenfns
[3][2] = {
10716 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
10717 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
10718 { tcg_gen_ext_i32_i64
, tcg_gen_extu_i32_i64
},
10720 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
10722 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
10723 read_vec_element_i32(s
, tcg_op2
, rm
, part
+ pass
, MO_32
);
10724 widenfn(tcg_op2_wide
, tcg_op2
);
10725 tcg_temp_free_i32(tcg_op2
);
10726 tcg_res
[pass
] = tcg_temp_new_i64();
10727 gen_neon_addl(size
, (opcode
== 3),
10728 tcg_res
[pass
], tcg_op1
, tcg_op2_wide
);
10729 tcg_temp_free_i64(tcg_op1
);
10730 tcg_temp_free_i64(tcg_op2_wide
);
10733 for (pass
= 0; pass
< 2; pass
++) {
10734 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
10735 tcg_temp_free_i64(tcg_res
[pass
]);
10739 static void do_narrow_round_high_u32(TCGv_i32 res
, TCGv_i64 in
)
10741 tcg_gen_addi_i64(in
, in
, 1U << 31);
10742 tcg_gen_extrh_i64_i32(res
, in
);
10745 static void handle_3rd_narrowing(DisasContext
*s
, int is_q
, int is_u
, int size
,
10746 int opcode
, int rd
, int rn
, int rm
)
10748 TCGv_i32 tcg_res
[2];
10749 int part
= is_q
? 2 : 0;
10752 for (pass
= 0; pass
< 2; pass
++) {
10753 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10754 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
10755 TCGv_i64 tcg_wideres
= tcg_temp_new_i64();
10756 static NeonGenNarrowFn
* const narrowfns
[3][2] = {
10757 { gen_helper_neon_narrow_high_u8
,
10758 gen_helper_neon_narrow_round_high_u8
},
10759 { gen_helper_neon_narrow_high_u16
,
10760 gen_helper_neon_narrow_round_high_u16
},
10761 { tcg_gen_extrh_i64_i32
, do_narrow_round_high_u32
},
10763 NeonGenNarrowFn
*gennarrow
= narrowfns
[size
][is_u
];
10765 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
10766 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
10768 gen_neon_addl(size
, (opcode
== 6), tcg_wideres
, tcg_op1
, tcg_op2
);
10770 tcg_temp_free_i64(tcg_op1
);
10771 tcg_temp_free_i64(tcg_op2
);
10773 tcg_res
[pass
] = tcg_temp_new_i32();
10774 gennarrow(tcg_res
[pass
], tcg_wideres
);
10775 tcg_temp_free_i64(tcg_wideres
);
10778 for (pass
= 0; pass
< 2; pass
++) {
10779 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
+ part
, MO_32
);
10780 tcg_temp_free_i32(tcg_res
[pass
]);
10782 clear_vec_high(s
, is_q
, rd
);
10785 /* AdvSIMD three different
10786 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
10787 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
10788 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
10789 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
10791 static void disas_simd_three_reg_diff(DisasContext
*s
, uint32_t insn
)
10793 /* Instructions in this group fall into three basic classes
10794 * (in each case with the operation working on each element in
10795 * the input vectors):
10796 * (1) widening 64 x 64 -> 128 (with possibly Vd as an extra
10798 * (2) wide 64 x 128 -> 128
10799 * (3) narrowing 128 x 128 -> 64
10800 * Here we do initial decode, catch unallocated cases and
10801 * dispatch to separate functions for each class.
10803 int is_q
= extract32(insn
, 30, 1);
10804 int is_u
= extract32(insn
, 29, 1);
10805 int size
= extract32(insn
, 22, 2);
10806 int opcode
= extract32(insn
, 12, 4);
10807 int rm
= extract32(insn
, 16, 5);
10808 int rn
= extract32(insn
, 5, 5);
10809 int rd
= extract32(insn
, 0, 5);
10812 case 1: /* SADDW, SADDW2, UADDW, UADDW2 */
10813 case 3: /* SSUBW, SSUBW2, USUBW, USUBW2 */
10814 /* 64 x 128 -> 128 */
10816 unallocated_encoding(s
);
10819 if (!fp_access_check(s
)) {
10822 handle_3rd_wide(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
10824 case 4: /* ADDHN, ADDHN2, RADDHN, RADDHN2 */
10825 case 6: /* SUBHN, SUBHN2, RSUBHN, RSUBHN2 */
10826 /* 128 x 128 -> 64 */
10828 unallocated_encoding(s
);
10831 if (!fp_access_check(s
)) {
10834 handle_3rd_narrowing(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
10836 case 14: /* PMULL, PMULL2 */
10838 unallocated_encoding(s
);
10842 case 0: /* PMULL.P8 */
10843 if (!fp_access_check(s
)) {
10846 /* The Q field specifies lo/hi half input for this insn. */
10847 gen_gvec_op3_ool(s
, true, rd
, rn
, rm
, is_q
,
10848 gen_helper_neon_pmull_h
);
10851 case 3: /* PMULL.P64 */
10852 if (!dc_isar_feature(aa64_pmull
, s
)) {
10853 unallocated_encoding(s
);
10856 if (!fp_access_check(s
)) {
10859 /* The Q field specifies lo/hi half input for this insn. */
10860 gen_gvec_op3_ool(s
, true, rd
, rn
, rm
, is_q
,
10861 gen_helper_gvec_pmull_q
);
10865 unallocated_encoding(s
);
10869 case 9: /* SQDMLAL, SQDMLAL2 */
10870 case 11: /* SQDMLSL, SQDMLSL2 */
10871 case 13: /* SQDMULL, SQDMULL2 */
10872 if (is_u
|| size
== 0) {
10873 unallocated_encoding(s
);
10877 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
10878 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
10879 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
10880 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
10881 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10882 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10883 case 12: /* SMULL, SMULL2, UMULL, UMULL2 */
10884 /* 64 x 64 -> 128 */
10886 unallocated_encoding(s
);
10889 if (!fp_access_check(s
)) {
10893 handle_3rd_widening(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
10896 /* opcode 15 not allocated */
10897 unallocated_encoding(s
);
10902 /* Logic op (opcode == 3) subgroup of C3.6.16. */
10903 static void disas_simd_3same_logic(DisasContext
*s
, uint32_t insn
)
10905 int rd
= extract32(insn
, 0, 5);
10906 int rn
= extract32(insn
, 5, 5);
10907 int rm
= extract32(insn
, 16, 5);
10908 int size
= extract32(insn
, 22, 2);
10909 bool is_u
= extract32(insn
, 29, 1);
10910 bool is_q
= extract32(insn
, 30, 1);
10912 if (!fp_access_check(s
)) {
10916 switch (size
+ 4 * is_u
) {
10918 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_and
, 0);
10921 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_andc
, 0);
10924 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_or
, 0);
10927 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_orc
, 0);
10930 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_xor
, 0);
10933 case 5: /* BSL bitwise select */
10934 gen_gvec_fn4(s
, is_q
, rd
, rd
, rn
, rm
, tcg_gen_gvec_bitsel
, 0);
10936 case 6: /* BIT, bitwise insert if true */
10937 gen_gvec_fn4(s
, is_q
, rd
, rm
, rn
, rd
, tcg_gen_gvec_bitsel
, 0);
10939 case 7: /* BIF, bitwise insert if false */
10940 gen_gvec_fn4(s
, is_q
, rd
, rm
, rd
, rn
, tcg_gen_gvec_bitsel
, 0);
10944 g_assert_not_reached();
10948 /* Pairwise op subgroup of C3.6.16.
10950 * This is called directly or via the handle_3same_float for float pairwise
10951 * operations where the opcode and size are calculated differently.
10953 static void handle_simd_3same_pair(DisasContext
*s
, int is_q
, int u
, int opcode
,
10954 int size
, int rn
, int rm
, int rd
)
10959 /* Floating point operations need fpst */
10960 if (opcode
>= 0x58) {
10961 fpst
= get_fpstatus_ptr(false);
10966 if (!fp_access_check(s
)) {
10970 /* These operations work on the concatenated rm:rn, with each pair of
10971 * adjacent elements being operated on to produce an element in the result.
10974 TCGv_i64 tcg_res
[2];
10976 for (pass
= 0; pass
< 2; pass
++) {
10977 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10978 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
10979 int passreg
= (pass
== 0) ? rn
: rm
;
10981 read_vec_element(s
, tcg_op1
, passreg
, 0, MO_64
);
10982 read_vec_element(s
, tcg_op2
, passreg
, 1, MO_64
);
10983 tcg_res
[pass
] = tcg_temp_new_i64();
10986 case 0x17: /* ADDP */
10987 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
10989 case 0x58: /* FMAXNMP */
10990 gen_helper_vfp_maxnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10992 case 0x5a: /* FADDP */
10993 gen_helper_vfp_addd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10995 case 0x5e: /* FMAXP */
10996 gen_helper_vfp_maxd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10998 case 0x78: /* FMINNMP */
10999 gen_helper_vfp_minnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11001 case 0x7e: /* FMINP */
11002 gen_helper_vfp_mind(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11005 g_assert_not_reached();
11008 tcg_temp_free_i64(tcg_op1
);
11009 tcg_temp_free_i64(tcg_op2
);
11012 for (pass
= 0; pass
< 2; pass
++) {
11013 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
11014 tcg_temp_free_i64(tcg_res
[pass
]);
11017 int maxpass
= is_q
? 4 : 2;
11018 TCGv_i32 tcg_res
[4];
11020 for (pass
= 0; pass
< maxpass
; pass
++) {
11021 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
11022 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
11023 NeonGenTwoOpFn
*genfn
= NULL
;
11024 int passreg
= pass
< (maxpass
/ 2) ? rn
: rm
;
11025 int passelt
= (is_q
&& (pass
& 1)) ? 2 : 0;
11027 read_vec_element_i32(s
, tcg_op1
, passreg
, passelt
, MO_32
);
11028 read_vec_element_i32(s
, tcg_op2
, passreg
, passelt
+ 1, MO_32
);
11029 tcg_res
[pass
] = tcg_temp_new_i32();
11032 case 0x17: /* ADDP */
11034 static NeonGenTwoOpFn
* const fns
[3] = {
11035 gen_helper_neon_padd_u8
,
11036 gen_helper_neon_padd_u16
,
11042 case 0x14: /* SMAXP, UMAXP */
11044 static NeonGenTwoOpFn
* const fns
[3][2] = {
11045 { gen_helper_neon_pmax_s8
, gen_helper_neon_pmax_u8
},
11046 { gen_helper_neon_pmax_s16
, gen_helper_neon_pmax_u16
},
11047 { tcg_gen_smax_i32
, tcg_gen_umax_i32
},
11049 genfn
= fns
[size
][u
];
11052 case 0x15: /* SMINP, UMINP */
11054 static NeonGenTwoOpFn
* const fns
[3][2] = {
11055 { gen_helper_neon_pmin_s8
, gen_helper_neon_pmin_u8
},
11056 { gen_helper_neon_pmin_s16
, gen_helper_neon_pmin_u16
},
11057 { tcg_gen_smin_i32
, tcg_gen_umin_i32
},
11059 genfn
= fns
[size
][u
];
11062 /* The FP operations are all on single floats (32 bit) */
11063 case 0x58: /* FMAXNMP */
11064 gen_helper_vfp_maxnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11066 case 0x5a: /* FADDP */
11067 gen_helper_vfp_adds(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11069 case 0x5e: /* FMAXP */
11070 gen_helper_vfp_maxs(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11072 case 0x78: /* FMINNMP */
11073 gen_helper_vfp_minnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11075 case 0x7e: /* FMINP */
11076 gen_helper_vfp_mins(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11079 g_assert_not_reached();
11082 /* FP ops called directly, otherwise call now */
11084 genfn(tcg_res
[pass
], tcg_op1
, tcg_op2
);
11087 tcg_temp_free_i32(tcg_op1
);
11088 tcg_temp_free_i32(tcg_op2
);
11091 for (pass
= 0; pass
< maxpass
; pass
++) {
11092 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
11093 tcg_temp_free_i32(tcg_res
[pass
]);
11095 clear_vec_high(s
, is_q
, rd
);
11099 tcg_temp_free_ptr(fpst
);
11103 /* Floating point op subgroup of C3.6.16. */
11104 static void disas_simd_3same_float(DisasContext
*s
, uint32_t insn
)
11106 /* For floating point ops, the U, size[1] and opcode bits
11107 * together indicate the operation. size[0] indicates single
11110 int fpopcode
= extract32(insn
, 11, 5)
11111 | (extract32(insn
, 23, 1) << 5)
11112 | (extract32(insn
, 29, 1) << 6);
11113 int is_q
= extract32(insn
, 30, 1);
11114 int size
= extract32(insn
, 22, 1);
11115 int rm
= extract32(insn
, 16, 5);
11116 int rn
= extract32(insn
, 5, 5);
11117 int rd
= extract32(insn
, 0, 5);
11119 int datasize
= is_q
? 128 : 64;
11120 int esize
= 32 << size
;
11121 int elements
= datasize
/ esize
;
11123 if (size
== 1 && !is_q
) {
11124 unallocated_encoding(s
);
11128 switch (fpopcode
) {
11129 case 0x58: /* FMAXNMP */
11130 case 0x5a: /* FADDP */
11131 case 0x5e: /* FMAXP */
11132 case 0x78: /* FMINNMP */
11133 case 0x7e: /* FMINP */
11134 if (size
&& !is_q
) {
11135 unallocated_encoding(s
);
11138 handle_simd_3same_pair(s
, is_q
, 0, fpopcode
, size
? MO_64
: MO_32
,
11141 case 0x1b: /* FMULX */
11142 case 0x1f: /* FRECPS */
11143 case 0x3f: /* FRSQRTS */
11144 case 0x5d: /* FACGE */
11145 case 0x7d: /* FACGT */
11146 case 0x19: /* FMLA */
11147 case 0x39: /* FMLS */
11148 case 0x18: /* FMAXNM */
11149 case 0x1a: /* FADD */
11150 case 0x1c: /* FCMEQ */
11151 case 0x1e: /* FMAX */
11152 case 0x38: /* FMINNM */
11153 case 0x3a: /* FSUB */
11154 case 0x3e: /* FMIN */
11155 case 0x5b: /* FMUL */
11156 case 0x5c: /* FCMGE */
11157 case 0x5f: /* FDIV */
11158 case 0x7a: /* FABD */
11159 case 0x7c: /* FCMGT */
11160 if (!fp_access_check(s
)) {
11163 handle_3same_float(s
, size
, elements
, fpopcode
, rd
, rn
, rm
);
11166 case 0x1d: /* FMLAL */
11167 case 0x3d: /* FMLSL */
11168 case 0x59: /* FMLAL2 */
11169 case 0x79: /* FMLSL2 */
11170 if (size
& 1 || !dc_isar_feature(aa64_fhm
, s
)) {
11171 unallocated_encoding(s
);
11174 if (fp_access_check(s
)) {
11175 int is_s
= extract32(insn
, 23, 1);
11176 int is_2
= extract32(insn
, 29, 1);
11177 int data
= (is_2
<< 1) | is_s
;
11178 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
11179 vec_full_reg_offset(s
, rn
),
11180 vec_full_reg_offset(s
, rm
), cpu_env
,
11181 is_q
? 16 : 8, vec_full_reg_size(s
),
11182 data
, gen_helper_gvec_fmlal_a64
);
11187 unallocated_encoding(s
);
11192 /* Integer op subgroup of C3.6.16. */
11193 static void disas_simd_3same_int(DisasContext
*s
, uint32_t insn
)
11195 int is_q
= extract32(insn
, 30, 1);
11196 int u
= extract32(insn
, 29, 1);
11197 int size
= extract32(insn
, 22, 2);
11198 int opcode
= extract32(insn
, 11, 5);
11199 int rm
= extract32(insn
, 16, 5);
11200 int rn
= extract32(insn
, 5, 5);
11201 int rd
= extract32(insn
, 0, 5);
11206 case 0x13: /* MUL, PMUL */
11207 if (u
&& size
!= 0) {
11208 unallocated_encoding(s
);
11212 case 0x0: /* SHADD, UHADD */
11213 case 0x2: /* SRHADD, URHADD */
11214 case 0x4: /* SHSUB, UHSUB */
11215 case 0xc: /* SMAX, UMAX */
11216 case 0xd: /* SMIN, UMIN */
11217 case 0xe: /* SABD, UABD */
11218 case 0xf: /* SABA, UABA */
11219 case 0x12: /* MLA, MLS */
11221 unallocated_encoding(s
);
11225 case 0x16: /* SQDMULH, SQRDMULH */
11226 if (size
== 0 || size
== 3) {
11227 unallocated_encoding(s
);
11232 if (size
== 3 && !is_q
) {
11233 unallocated_encoding(s
);
11239 if (!fp_access_check(s
)) {
11244 case 0x01: /* SQADD, UQADD */
11245 tcg_gen_gvec_4(vec_full_reg_offset(s
, rd
),
11246 offsetof(CPUARMState
, vfp
.qc
),
11247 vec_full_reg_offset(s
, rn
),
11248 vec_full_reg_offset(s
, rm
),
11249 is_q
? 16 : 8, vec_full_reg_size(s
),
11250 (u
? uqadd_op
: sqadd_op
) + size
);
11252 case 0x05: /* SQSUB, UQSUB */
11253 tcg_gen_gvec_4(vec_full_reg_offset(s
, rd
),
11254 offsetof(CPUARMState
, vfp
.qc
),
11255 vec_full_reg_offset(s
, rn
),
11256 vec_full_reg_offset(s
, rm
),
11257 is_q
? 16 : 8, vec_full_reg_size(s
),
11258 (u
? uqsub_op
: sqsub_op
) + size
);
11260 case 0x08: /* SSHL, USHL */
11261 gen_gvec_op3(s
, is_q
, rd
, rn
, rm
,
11262 u
? &ushl_op
[size
] : &sshl_op
[size
]);
11264 case 0x0c: /* SMAX, UMAX */
11266 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_umax
, size
);
11268 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_smax
, size
);
11271 case 0x0d: /* SMIN, UMIN */
11273 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_umin
, size
);
11275 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_smin
, size
);
11278 case 0x10: /* ADD, SUB */
11280 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_sub
, size
);
11282 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_add
, size
);
11285 case 0x13: /* MUL, PMUL */
11286 if (!u
) { /* MUL */
11287 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_mul
, size
);
11288 } else { /* PMUL */
11289 gen_gvec_op3_ool(s
, is_q
, rd
, rn
, rm
, 0, gen_helper_gvec_pmul_b
);
11292 case 0x12: /* MLA, MLS */
11294 gen_gvec_op3(s
, is_q
, rd
, rn
, rm
, &mls_op
[size
]);
11296 gen_gvec_op3(s
, is_q
, rd
, rn
, rm
, &mla_op
[size
]);
11300 if (!u
) { /* CMTST */
11301 gen_gvec_op3(s
, is_q
, rd
, rn
, rm
, &cmtst_op
[size
]);
11305 cond
= TCG_COND_EQ
;
11307 case 0x06: /* CMGT, CMHI */
11308 cond
= u
? TCG_COND_GTU
: TCG_COND_GT
;
11310 case 0x07: /* CMGE, CMHS */
11311 cond
= u
? TCG_COND_GEU
: TCG_COND_GE
;
11313 tcg_gen_gvec_cmp(cond
, size
, vec_full_reg_offset(s
, rd
),
11314 vec_full_reg_offset(s
, rn
),
11315 vec_full_reg_offset(s
, rm
),
11316 is_q
? 16 : 8, vec_full_reg_size(s
));
11322 for (pass
= 0; pass
< 2; pass
++) {
11323 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
11324 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
11325 TCGv_i64 tcg_res
= tcg_temp_new_i64();
11327 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
11328 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
11330 handle_3same_64(s
, opcode
, u
, tcg_res
, tcg_op1
, tcg_op2
);
11332 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
11334 tcg_temp_free_i64(tcg_res
);
11335 tcg_temp_free_i64(tcg_op1
);
11336 tcg_temp_free_i64(tcg_op2
);
11339 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
11340 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
11341 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
11342 TCGv_i32 tcg_res
= tcg_temp_new_i32();
11343 NeonGenTwoOpFn
*genfn
= NULL
;
11344 NeonGenTwoOpEnvFn
*genenvfn
= NULL
;
11346 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
11347 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
11350 case 0x0: /* SHADD, UHADD */
11352 static NeonGenTwoOpFn
* const fns
[3][2] = {
11353 { gen_helper_neon_hadd_s8
, gen_helper_neon_hadd_u8
},
11354 { gen_helper_neon_hadd_s16
, gen_helper_neon_hadd_u16
},
11355 { gen_helper_neon_hadd_s32
, gen_helper_neon_hadd_u32
},
11357 genfn
= fns
[size
][u
];
11360 case 0x2: /* SRHADD, URHADD */
11362 static NeonGenTwoOpFn
* const fns
[3][2] = {
11363 { gen_helper_neon_rhadd_s8
, gen_helper_neon_rhadd_u8
},
11364 { gen_helper_neon_rhadd_s16
, gen_helper_neon_rhadd_u16
},
11365 { gen_helper_neon_rhadd_s32
, gen_helper_neon_rhadd_u32
},
11367 genfn
= fns
[size
][u
];
11370 case 0x4: /* SHSUB, UHSUB */
11372 static NeonGenTwoOpFn
* const fns
[3][2] = {
11373 { gen_helper_neon_hsub_s8
, gen_helper_neon_hsub_u8
},
11374 { gen_helper_neon_hsub_s16
, gen_helper_neon_hsub_u16
},
11375 { gen_helper_neon_hsub_s32
, gen_helper_neon_hsub_u32
},
11377 genfn
= fns
[size
][u
];
11380 case 0x9: /* SQSHL, UQSHL */
11382 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
11383 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
11384 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
11385 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
11387 genenvfn
= fns
[size
][u
];
11390 case 0xa: /* SRSHL, URSHL */
11392 static NeonGenTwoOpFn
* const fns
[3][2] = {
11393 { gen_helper_neon_rshl_s8
, gen_helper_neon_rshl_u8
},
11394 { gen_helper_neon_rshl_s16
, gen_helper_neon_rshl_u16
},
11395 { gen_helper_neon_rshl_s32
, gen_helper_neon_rshl_u32
},
11397 genfn
= fns
[size
][u
];
11400 case 0xb: /* SQRSHL, UQRSHL */
11402 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
11403 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
11404 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
11405 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
11407 genenvfn
= fns
[size
][u
];
11410 case 0xe: /* SABD, UABD */
11411 case 0xf: /* SABA, UABA */
11413 static NeonGenTwoOpFn
* const fns
[3][2] = {
11414 { gen_helper_neon_abd_s8
, gen_helper_neon_abd_u8
},
11415 { gen_helper_neon_abd_s16
, gen_helper_neon_abd_u16
},
11416 { gen_helper_neon_abd_s32
, gen_helper_neon_abd_u32
},
11418 genfn
= fns
[size
][u
];
11421 case 0x16: /* SQDMULH, SQRDMULH */
11423 static NeonGenTwoOpEnvFn
* const fns
[2][2] = {
11424 { gen_helper_neon_qdmulh_s16
, gen_helper_neon_qrdmulh_s16
},
11425 { gen_helper_neon_qdmulh_s32
, gen_helper_neon_qrdmulh_s32
},
11427 assert(size
== 1 || size
== 2);
11428 genenvfn
= fns
[size
- 1][u
];
11432 g_assert_not_reached();
11436 genenvfn(tcg_res
, cpu_env
, tcg_op1
, tcg_op2
);
11438 genfn(tcg_res
, tcg_op1
, tcg_op2
);
11441 if (opcode
== 0xf) {
11442 /* SABA, UABA: accumulating ops */
11443 static NeonGenTwoOpFn
* const fns
[3] = {
11444 gen_helper_neon_add_u8
,
11445 gen_helper_neon_add_u16
,
11449 read_vec_element_i32(s
, tcg_op1
, rd
, pass
, MO_32
);
11450 fns
[size
](tcg_res
, tcg_op1
, tcg_res
);
11453 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
11455 tcg_temp_free_i32(tcg_res
);
11456 tcg_temp_free_i32(tcg_op1
);
11457 tcg_temp_free_i32(tcg_op2
);
11460 clear_vec_high(s
, is_q
, rd
);
11463 /* AdvSIMD three same
11464 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
11465 * +---+---+---+-----------+------+---+------+--------+---+------+------+
11466 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
11467 * +---+---+---+-----------+------+---+------+--------+---+------+------+
11469 static void disas_simd_three_reg_same(DisasContext
*s
, uint32_t insn
)
11471 int opcode
= extract32(insn
, 11, 5);
11474 case 0x3: /* logic ops */
11475 disas_simd_3same_logic(s
, insn
);
11477 case 0x17: /* ADDP */
11478 case 0x14: /* SMAXP, UMAXP */
11479 case 0x15: /* SMINP, UMINP */
11481 /* Pairwise operations */
11482 int is_q
= extract32(insn
, 30, 1);
11483 int u
= extract32(insn
, 29, 1);
11484 int size
= extract32(insn
, 22, 2);
11485 int rm
= extract32(insn
, 16, 5);
11486 int rn
= extract32(insn
, 5, 5);
11487 int rd
= extract32(insn
, 0, 5);
11488 if (opcode
== 0x17) {
11489 if (u
|| (size
== 3 && !is_q
)) {
11490 unallocated_encoding(s
);
11495 unallocated_encoding(s
);
11499 handle_simd_3same_pair(s
, is_q
, u
, opcode
, size
, rn
, rm
, rd
);
11502 case 0x18 ... 0x31:
11503 /* floating point ops, sz[1] and U are part of opcode */
11504 disas_simd_3same_float(s
, insn
);
11507 disas_simd_3same_int(s
, insn
);
11513 * Advanced SIMD three same (ARMv8.2 FP16 variants)
11515 * 31 30 29 28 24 23 22 21 20 16 15 14 13 11 10 9 5 4 0
11516 * +---+---+---+-----------+---------+------+-----+--------+---+------+------+
11517 * | 0 | Q | U | 0 1 1 1 0 | a | 1 0 | Rm | 0 0 | opcode | 1 | Rn | Rd |
11518 * +---+---+---+-----------+---------+------+-----+--------+---+------+------+
11520 * This includes FMULX, FCMEQ (register), FRECPS, FRSQRTS, FCMGE
11521 * (register), FACGE, FABD, FCMGT (register) and FACGT.
11524 static void disas_simd_three_reg_same_fp16(DisasContext
*s
, uint32_t insn
)
11526 int opcode
, fpopcode
;
11527 int is_q
, u
, a
, rm
, rn
, rd
;
11528 int datasize
, elements
;
11531 bool pairwise
= false;
11533 if (!dc_isar_feature(aa64_fp16
, s
)) {
11534 unallocated_encoding(s
);
11538 if (!fp_access_check(s
)) {
11542 /* For these floating point ops, the U, a and opcode bits
11543 * together indicate the operation.
11545 opcode
= extract32(insn
, 11, 3);
11546 u
= extract32(insn
, 29, 1);
11547 a
= extract32(insn
, 23, 1);
11548 is_q
= extract32(insn
, 30, 1);
11549 rm
= extract32(insn
, 16, 5);
11550 rn
= extract32(insn
, 5, 5);
11551 rd
= extract32(insn
, 0, 5);
11553 fpopcode
= opcode
| (a
<< 3) | (u
<< 4);
11554 datasize
= is_q
? 128 : 64;
11555 elements
= datasize
/ 16;
11557 switch (fpopcode
) {
11558 case 0x10: /* FMAXNMP */
11559 case 0x12: /* FADDP */
11560 case 0x16: /* FMAXP */
11561 case 0x18: /* FMINNMP */
11562 case 0x1e: /* FMINP */
11567 fpst
= get_fpstatus_ptr(true);
11570 int maxpass
= is_q
? 8 : 4;
11571 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
11572 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
11573 TCGv_i32 tcg_res
[8];
11575 for (pass
= 0; pass
< maxpass
; pass
++) {
11576 int passreg
= pass
< (maxpass
/ 2) ? rn
: rm
;
11577 int passelt
= (pass
<< 1) & (maxpass
- 1);
11579 read_vec_element_i32(s
, tcg_op1
, passreg
, passelt
, MO_16
);
11580 read_vec_element_i32(s
, tcg_op2
, passreg
, passelt
+ 1, MO_16
);
11581 tcg_res
[pass
] = tcg_temp_new_i32();
11583 switch (fpopcode
) {
11584 case 0x10: /* FMAXNMP */
11585 gen_helper_advsimd_maxnumh(tcg_res
[pass
], tcg_op1
, tcg_op2
,
11588 case 0x12: /* FADDP */
11589 gen_helper_advsimd_addh(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11591 case 0x16: /* FMAXP */
11592 gen_helper_advsimd_maxh(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11594 case 0x18: /* FMINNMP */
11595 gen_helper_advsimd_minnumh(tcg_res
[pass
], tcg_op1
, tcg_op2
,
11598 case 0x1e: /* FMINP */
11599 gen_helper_advsimd_minh(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11602 g_assert_not_reached();
11606 for (pass
= 0; pass
< maxpass
; pass
++) {
11607 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_16
);
11608 tcg_temp_free_i32(tcg_res
[pass
]);
11611 tcg_temp_free_i32(tcg_op1
);
11612 tcg_temp_free_i32(tcg_op2
);
11615 for (pass
= 0; pass
< elements
; pass
++) {
11616 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
11617 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
11618 TCGv_i32 tcg_res
= tcg_temp_new_i32();
11620 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_16
);
11621 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_16
);
11623 switch (fpopcode
) {
11624 case 0x0: /* FMAXNM */
11625 gen_helper_advsimd_maxnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11627 case 0x1: /* FMLA */
11628 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
11629 gen_helper_advsimd_muladdh(tcg_res
, tcg_op1
, tcg_op2
, tcg_res
,
11632 case 0x2: /* FADD */
11633 gen_helper_advsimd_addh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11635 case 0x3: /* FMULX */
11636 gen_helper_advsimd_mulxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11638 case 0x4: /* FCMEQ */
11639 gen_helper_advsimd_ceq_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11641 case 0x6: /* FMAX */
11642 gen_helper_advsimd_maxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11644 case 0x7: /* FRECPS */
11645 gen_helper_recpsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11647 case 0x8: /* FMINNM */
11648 gen_helper_advsimd_minnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11650 case 0x9: /* FMLS */
11651 /* As usual for ARM, separate negation for fused multiply-add */
11652 tcg_gen_xori_i32(tcg_op1
, tcg_op1
, 0x8000);
11653 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
11654 gen_helper_advsimd_muladdh(tcg_res
, tcg_op1
, tcg_op2
, tcg_res
,
11657 case 0xa: /* FSUB */
11658 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11660 case 0xe: /* FMIN */
11661 gen_helper_advsimd_minh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11663 case 0xf: /* FRSQRTS */
11664 gen_helper_rsqrtsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11666 case 0x13: /* FMUL */
11667 gen_helper_advsimd_mulh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11669 case 0x14: /* FCMGE */
11670 gen_helper_advsimd_cge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11672 case 0x15: /* FACGE */
11673 gen_helper_advsimd_acge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11675 case 0x17: /* FDIV */
11676 gen_helper_advsimd_divh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11678 case 0x1a: /* FABD */
11679 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11680 tcg_gen_andi_i32(tcg_res
, tcg_res
, 0x7fff);
11682 case 0x1c: /* FCMGT */
11683 gen_helper_advsimd_cgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11685 case 0x1d: /* FACGT */
11686 gen_helper_advsimd_acgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11689 fprintf(stderr
, "%s: insn %#04x, fpop %#2x @ %#" PRIx64
"\n",
11690 __func__
, insn
, fpopcode
, s
->pc_curr
);
11691 g_assert_not_reached();
11694 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
11695 tcg_temp_free_i32(tcg_res
);
11696 tcg_temp_free_i32(tcg_op1
);
11697 tcg_temp_free_i32(tcg_op2
);
11701 tcg_temp_free_ptr(fpst
);
11703 clear_vec_high(s
, is_q
, rd
);
11706 /* AdvSIMD three same extra
11707 * 31 30 29 28 24 23 22 21 20 16 15 14 11 10 9 5 4 0
11708 * +---+---+---+-----------+------+---+------+---+--------+---+----+----+
11709 * | 0 | Q | U | 0 1 1 1 0 | size | 0 | Rm | 1 | opcode | 1 | Rn | Rd |
11710 * +---+---+---+-----------+------+---+------+---+--------+---+----+----+
11712 static void disas_simd_three_reg_same_extra(DisasContext
*s
, uint32_t insn
)
11714 int rd
= extract32(insn
, 0, 5);
11715 int rn
= extract32(insn
, 5, 5);
11716 int opcode
= extract32(insn
, 11, 4);
11717 int rm
= extract32(insn
, 16, 5);
11718 int size
= extract32(insn
, 22, 2);
11719 bool u
= extract32(insn
, 29, 1);
11720 bool is_q
= extract32(insn
, 30, 1);
11724 switch (u
* 16 + opcode
) {
11725 case 0x10: /* SQRDMLAH (vector) */
11726 case 0x11: /* SQRDMLSH (vector) */
11727 if (size
!= 1 && size
!= 2) {
11728 unallocated_encoding(s
);
11731 feature
= dc_isar_feature(aa64_rdm
, s
);
11733 case 0x02: /* SDOT (vector) */
11734 case 0x12: /* UDOT (vector) */
11735 if (size
!= MO_32
) {
11736 unallocated_encoding(s
);
11739 feature
= dc_isar_feature(aa64_dp
, s
);
11741 case 0x18: /* FCMLA, #0 */
11742 case 0x19: /* FCMLA, #90 */
11743 case 0x1a: /* FCMLA, #180 */
11744 case 0x1b: /* FCMLA, #270 */
11745 case 0x1c: /* FCADD, #90 */
11746 case 0x1e: /* FCADD, #270 */
11748 || (size
== 1 && !dc_isar_feature(aa64_fp16
, s
))
11749 || (size
== 3 && !is_q
)) {
11750 unallocated_encoding(s
);
11753 feature
= dc_isar_feature(aa64_fcma
, s
);
11756 unallocated_encoding(s
);
11760 unallocated_encoding(s
);
11763 if (!fp_access_check(s
)) {
11768 case 0x0: /* SQRDMLAH (vector) */
11771 gen_gvec_op3_env(s
, is_q
, rd
, rn
, rm
, gen_helper_gvec_qrdmlah_s16
);
11774 gen_gvec_op3_env(s
, is_q
, rd
, rn
, rm
, gen_helper_gvec_qrdmlah_s32
);
11777 g_assert_not_reached();
11781 case 0x1: /* SQRDMLSH (vector) */
11784 gen_gvec_op3_env(s
, is_q
, rd
, rn
, rm
, gen_helper_gvec_qrdmlsh_s16
);
11787 gen_gvec_op3_env(s
, is_q
, rd
, rn
, rm
, gen_helper_gvec_qrdmlsh_s32
);
11790 g_assert_not_reached();
11794 case 0x2: /* SDOT / UDOT */
11795 gen_gvec_op3_ool(s
, is_q
, rd
, rn
, rm
, 0,
11796 u
? gen_helper_gvec_udot_b
: gen_helper_gvec_sdot_b
);
11799 case 0x8: /* FCMLA, #0 */
11800 case 0x9: /* FCMLA, #90 */
11801 case 0xa: /* FCMLA, #180 */
11802 case 0xb: /* FCMLA, #270 */
11803 rot
= extract32(opcode
, 0, 2);
11806 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, true, rot
,
11807 gen_helper_gvec_fcmlah
);
11810 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, false, rot
,
11811 gen_helper_gvec_fcmlas
);
11814 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, false, rot
,
11815 gen_helper_gvec_fcmlad
);
11818 g_assert_not_reached();
11822 case 0xc: /* FCADD, #90 */
11823 case 0xe: /* FCADD, #270 */
11824 rot
= extract32(opcode
, 1, 1);
11827 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, size
== 1, rot
,
11828 gen_helper_gvec_fcaddh
);
11831 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, size
== 1, rot
,
11832 gen_helper_gvec_fcadds
);
11835 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, size
== 1, rot
,
11836 gen_helper_gvec_fcaddd
);
11839 g_assert_not_reached();
11844 g_assert_not_reached();
11848 static void handle_2misc_widening(DisasContext
*s
, int opcode
, bool is_q
,
11849 int size
, int rn
, int rd
)
11851 /* Handle 2-reg-misc ops which are widening (so each size element
11852 * in the source becomes a 2*size element in the destination.
11853 * The only instruction like this is FCVTL.
11858 /* 32 -> 64 bit fp conversion */
11859 TCGv_i64 tcg_res
[2];
11860 int srcelt
= is_q
? 2 : 0;
11862 for (pass
= 0; pass
< 2; pass
++) {
11863 TCGv_i32 tcg_op
= tcg_temp_new_i32();
11864 tcg_res
[pass
] = tcg_temp_new_i64();
11866 read_vec_element_i32(s
, tcg_op
, rn
, srcelt
+ pass
, MO_32
);
11867 gen_helper_vfp_fcvtds(tcg_res
[pass
], tcg_op
, cpu_env
);
11868 tcg_temp_free_i32(tcg_op
);
11870 for (pass
= 0; pass
< 2; pass
++) {
11871 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
11872 tcg_temp_free_i64(tcg_res
[pass
]);
11875 /* 16 -> 32 bit fp conversion */
11876 int srcelt
= is_q
? 4 : 0;
11877 TCGv_i32 tcg_res
[4];
11878 TCGv_ptr fpst
= get_fpstatus_ptr(false);
11879 TCGv_i32 ahp
= get_ahp_flag();
11881 for (pass
= 0; pass
< 4; pass
++) {
11882 tcg_res
[pass
] = tcg_temp_new_i32();
11884 read_vec_element_i32(s
, tcg_res
[pass
], rn
, srcelt
+ pass
, MO_16
);
11885 gen_helper_vfp_fcvt_f16_to_f32(tcg_res
[pass
], tcg_res
[pass
],
11888 for (pass
= 0; pass
< 4; pass
++) {
11889 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
11890 tcg_temp_free_i32(tcg_res
[pass
]);
11893 tcg_temp_free_ptr(fpst
);
11894 tcg_temp_free_i32(ahp
);
11898 static void handle_rev(DisasContext
*s
, int opcode
, bool u
,
11899 bool is_q
, int size
, int rn
, int rd
)
11901 int op
= (opcode
<< 1) | u
;
11902 int opsz
= op
+ size
;
11903 int grp_size
= 3 - opsz
;
11904 int dsize
= is_q
? 128 : 64;
11908 unallocated_encoding(s
);
11912 if (!fp_access_check(s
)) {
11917 /* Special case bytes, use bswap op on each group of elements */
11918 int groups
= dsize
/ (8 << grp_size
);
11920 for (i
= 0; i
< groups
; i
++) {
11921 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
11923 read_vec_element(s
, tcg_tmp
, rn
, i
, grp_size
);
11924 switch (grp_size
) {
11926 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
11929 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
);
11932 tcg_gen_bswap64_i64(tcg_tmp
, tcg_tmp
);
11935 g_assert_not_reached();
11937 write_vec_element(s
, tcg_tmp
, rd
, i
, grp_size
);
11938 tcg_temp_free_i64(tcg_tmp
);
11940 clear_vec_high(s
, is_q
, rd
);
11942 int revmask
= (1 << grp_size
) - 1;
11943 int esize
= 8 << size
;
11944 int elements
= dsize
/ esize
;
11945 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
11946 TCGv_i64 tcg_rd
= tcg_const_i64(0);
11947 TCGv_i64 tcg_rd_hi
= tcg_const_i64(0);
11949 for (i
= 0; i
< elements
; i
++) {
11950 int e_rev
= (i
& 0xf) ^ revmask
;
11951 int off
= e_rev
* esize
;
11952 read_vec_element(s
, tcg_rn
, rn
, i
, size
);
11954 tcg_gen_deposit_i64(tcg_rd_hi
, tcg_rd_hi
,
11955 tcg_rn
, off
- 64, esize
);
11957 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, off
, esize
);
11960 write_vec_element(s
, tcg_rd
, rd
, 0, MO_64
);
11961 write_vec_element(s
, tcg_rd_hi
, rd
, 1, MO_64
);
11963 tcg_temp_free_i64(tcg_rd_hi
);
11964 tcg_temp_free_i64(tcg_rd
);
11965 tcg_temp_free_i64(tcg_rn
);
11969 static void handle_2misc_pairwise(DisasContext
*s
, int opcode
, bool u
,
11970 bool is_q
, int size
, int rn
, int rd
)
11972 /* Implement the pairwise operations from 2-misc:
11973 * SADDLP, UADDLP, SADALP, UADALP.
11974 * These all add pairs of elements in the input to produce a
11975 * double-width result element in the output (possibly accumulating).
11977 bool accum
= (opcode
== 0x6);
11978 int maxpass
= is_q
? 2 : 1;
11980 TCGv_i64 tcg_res
[2];
11983 /* 32 + 32 -> 64 op */
11984 MemOp memop
= size
+ (u
? 0 : MO_SIGN
);
11986 for (pass
= 0; pass
< maxpass
; pass
++) {
11987 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
11988 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
11990 tcg_res
[pass
] = tcg_temp_new_i64();
11992 read_vec_element(s
, tcg_op1
, rn
, pass
* 2, memop
);
11993 read_vec_element(s
, tcg_op2
, rn
, pass
* 2 + 1, memop
);
11994 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
11996 read_vec_element(s
, tcg_op1
, rd
, pass
, MO_64
);
11997 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
12000 tcg_temp_free_i64(tcg_op1
);
12001 tcg_temp_free_i64(tcg_op2
);
12004 for (pass
= 0; pass
< maxpass
; pass
++) {
12005 TCGv_i64 tcg_op
= tcg_temp_new_i64();
12006 NeonGenOneOpFn
*genfn
;
12007 static NeonGenOneOpFn
* const fns
[2][2] = {
12008 { gen_helper_neon_addlp_s8
, gen_helper_neon_addlp_u8
},
12009 { gen_helper_neon_addlp_s16
, gen_helper_neon_addlp_u16
},
12012 genfn
= fns
[size
][u
];
12014 tcg_res
[pass
] = tcg_temp_new_i64();
12016 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
12017 genfn(tcg_res
[pass
], tcg_op
);
12020 read_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
12022 gen_helper_neon_addl_u16(tcg_res
[pass
],
12023 tcg_res
[pass
], tcg_op
);
12025 gen_helper_neon_addl_u32(tcg_res
[pass
],
12026 tcg_res
[pass
], tcg_op
);
12029 tcg_temp_free_i64(tcg_op
);
12033 tcg_res
[1] = tcg_const_i64(0);
12035 for (pass
= 0; pass
< 2; pass
++) {
12036 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
12037 tcg_temp_free_i64(tcg_res
[pass
]);
12041 static void handle_shll(DisasContext
*s
, bool is_q
, int size
, int rn
, int rd
)
12043 /* Implement SHLL and SHLL2 */
12045 int part
= is_q
? 2 : 0;
12046 TCGv_i64 tcg_res
[2];
12048 for (pass
= 0; pass
< 2; pass
++) {
12049 static NeonGenWidenFn
* const widenfns
[3] = {
12050 gen_helper_neon_widen_u8
,
12051 gen_helper_neon_widen_u16
,
12052 tcg_gen_extu_i32_i64
,
12054 NeonGenWidenFn
*widenfn
= widenfns
[size
];
12055 TCGv_i32 tcg_op
= tcg_temp_new_i32();
12057 read_vec_element_i32(s
, tcg_op
, rn
, part
+ pass
, MO_32
);
12058 tcg_res
[pass
] = tcg_temp_new_i64();
12059 widenfn(tcg_res
[pass
], tcg_op
);
12060 tcg_gen_shli_i64(tcg_res
[pass
], tcg_res
[pass
], 8 << size
);
12062 tcg_temp_free_i32(tcg_op
);
12065 for (pass
= 0; pass
< 2; pass
++) {
12066 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
12067 tcg_temp_free_i64(tcg_res
[pass
]);
12071 /* AdvSIMD two reg misc
12072 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
12073 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
12074 * | 0 | Q | U | 0 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
12075 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
12077 static void disas_simd_two_reg_misc(DisasContext
*s
, uint32_t insn
)
12079 int size
= extract32(insn
, 22, 2);
12080 int opcode
= extract32(insn
, 12, 5);
12081 bool u
= extract32(insn
, 29, 1);
12082 bool is_q
= extract32(insn
, 30, 1);
12083 int rn
= extract32(insn
, 5, 5);
12084 int rd
= extract32(insn
, 0, 5);
12085 bool need_fpstatus
= false;
12086 bool need_rmode
= false;
12088 TCGv_i32 tcg_rmode
;
12089 TCGv_ptr tcg_fpstatus
;
12092 case 0x0: /* REV64, REV32 */
12093 case 0x1: /* REV16 */
12094 handle_rev(s
, opcode
, u
, is_q
, size
, rn
, rd
);
12096 case 0x5: /* CNT, NOT, RBIT */
12097 if (u
&& size
== 0) {
12100 } else if (u
&& size
== 1) {
12103 } else if (!u
&& size
== 0) {
12107 unallocated_encoding(s
);
12109 case 0x12: /* XTN, XTN2, SQXTUN, SQXTUN2 */
12110 case 0x14: /* SQXTN, SQXTN2, UQXTN, UQXTN2 */
12112 unallocated_encoding(s
);
12115 if (!fp_access_check(s
)) {
12119 handle_2misc_narrow(s
, false, opcode
, u
, is_q
, size
, rn
, rd
);
12121 case 0x4: /* CLS, CLZ */
12123 unallocated_encoding(s
);
12127 case 0x2: /* SADDLP, UADDLP */
12128 case 0x6: /* SADALP, UADALP */
12130 unallocated_encoding(s
);
12133 if (!fp_access_check(s
)) {
12136 handle_2misc_pairwise(s
, opcode
, u
, is_q
, size
, rn
, rd
);
12138 case 0x13: /* SHLL, SHLL2 */
12139 if (u
== 0 || size
== 3) {
12140 unallocated_encoding(s
);
12143 if (!fp_access_check(s
)) {
12146 handle_shll(s
, is_q
, size
, rn
, rd
);
12148 case 0xa: /* CMLT */
12150 unallocated_encoding(s
);
12154 case 0x8: /* CMGT, CMGE */
12155 case 0x9: /* CMEQ, CMLE */
12156 case 0xb: /* ABS, NEG */
12157 if (size
== 3 && !is_q
) {
12158 unallocated_encoding(s
);
12162 case 0x3: /* SUQADD, USQADD */
12163 if (size
== 3 && !is_q
) {
12164 unallocated_encoding(s
);
12167 if (!fp_access_check(s
)) {
12170 handle_2misc_satacc(s
, false, u
, is_q
, size
, rn
, rd
);
12172 case 0x7: /* SQABS, SQNEG */
12173 if (size
== 3 && !is_q
) {
12174 unallocated_encoding(s
);
12179 case 0x16 ... 0x1f:
12181 /* Floating point: U, size[1] and opcode indicate operation;
12182 * size[0] indicates single or double precision.
12184 int is_double
= extract32(size
, 0, 1);
12185 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
12186 size
= is_double
? 3 : 2;
12188 case 0x2f: /* FABS */
12189 case 0x6f: /* FNEG */
12190 if (size
== 3 && !is_q
) {
12191 unallocated_encoding(s
);
12195 case 0x1d: /* SCVTF */
12196 case 0x5d: /* UCVTF */
12198 bool is_signed
= (opcode
== 0x1d) ? true : false;
12199 int elements
= is_double
? 2 : is_q
? 4 : 2;
12200 if (is_double
&& !is_q
) {
12201 unallocated_encoding(s
);
12204 if (!fp_access_check(s
)) {
12207 handle_simd_intfp_conv(s
, rd
, rn
, elements
, is_signed
, 0, size
);
12210 case 0x2c: /* FCMGT (zero) */
12211 case 0x2d: /* FCMEQ (zero) */
12212 case 0x2e: /* FCMLT (zero) */
12213 case 0x6c: /* FCMGE (zero) */
12214 case 0x6d: /* FCMLE (zero) */
12215 if (size
== 3 && !is_q
) {
12216 unallocated_encoding(s
);
12219 handle_2misc_fcmp_zero(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
12221 case 0x7f: /* FSQRT */
12222 if (size
== 3 && !is_q
) {
12223 unallocated_encoding(s
);
12227 case 0x1a: /* FCVTNS */
12228 case 0x1b: /* FCVTMS */
12229 case 0x3a: /* FCVTPS */
12230 case 0x3b: /* FCVTZS */
12231 case 0x5a: /* FCVTNU */
12232 case 0x5b: /* FCVTMU */
12233 case 0x7a: /* FCVTPU */
12234 case 0x7b: /* FCVTZU */
12235 need_fpstatus
= true;
12237 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
12238 if (size
== 3 && !is_q
) {
12239 unallocated_encoding(s
);
12243 case 0x5c: /* FCVTAU */
12244 case 0x1c: /* FCVTAS */
12245 need_fpstatus
= true;
12247 rmode
= FPROUNDING_TIEAWAY
;
12248 if (size
== 3 && !is_q
) {
12249 unallocated_encoding(s
);
12253 case 0x3c: /* URECPE */
12255 unallocated_encoding(s
);
12259 case 0x3d: /* FRECPE */
12260 case 0x7d: /* FRSQRTE */
12261 if (size
== 3 && !is_q
) {
12262 unallocated_encoding(s
);
12265 if (!fp_access_check(s
)) {
12268 handle_2misc_reciprocal(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
12270 case 0x56: /* FCVTXN, FCVTXN2 */
12272 unallocated_encoding(s
);
12276 case 0x16: /* FCVTN, FCVTN2 */
12277 /* handle_2misc_narrow does a 2*size -> size operation, but these
12278 * instructions encode the source size rather than dest size.
12280 if (!fp_access_check(s
)) {
12283 handle_2misc_narrow(s
, false, opcode
, 0, is_q
, size
- 1, rn
, rd
);
12285 case 0x17: /* FCVTL, FCVTL2 */
12286 if (!fp_access_check(s
)) {
12289 handle_2misc_widening(s
, opcode
, is_q
, size
, rn
, rd
);
12291 case 0x18: /* FRINTN */
12292 case 0x19: /* FRINTM */
12293 case 0x38: /* FRINTP */
12294 case 0x39: /* FRINTZ */
12296 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
12298 case 0x59: /* FRINTX */
12299 case 0x79: /* FRINTI */
12300 need_fpstatus
= true;
12301 if (size
== 3 && !is_q
) {
12302 unallocated_encoding(s
);
12306 case 0x58: /* FRINTA */
12308 rmode
= FPROUNDING_TIEAWAY
;
12309 need_fpstatus
= true;
12310 if (size
== 3 && !is_q
) {
12311 unallocated_encoding(s
);
12315 case 0x7c: /* URSQRTE */
12317 unallocated_encoding(s
);
12320 need_fpstatus
= true;
12322 case 0x1e: /* FRINT32Z */
12323 case 0x1f: /* FRINT64Z */
12325 rmode
= FPROUNDING_ZERO
;
12327 case 0x5e: /* FRINT32X */
12328 case 0x5f: /* FRINT64X */
12329 need_fpstatus
= true;
12330 if ((size
== 3 && !is_q
) || !dc_isar_feature(aa64_frint
, s
)) {
12331 unallocated_encoding(s
);
12336 unallocated_encoding(s
);
12342 unallocated_encoding(s
);
12346 if (!fp_access_check(s
)) {
12350 if (need_fpstatus
|| need_rmode
) {
12351 tcg_fpstatus
= get_fpstatus_ptr(false);
12353 tcg_fpstatus
= NULL
;
12356 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
12357 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
12364 if (u
&& size
== 0) { /* NOT */
12365 gen_gvec_fn2(s
, is_q
, rd
, rn
, tcg_gen_gvec_not
, 0);
12370 if (u
) { /* ABS, NEG */
12371 gen_gvec_fn2(s
, is_q
, rd
, rn
, tcg_gen_gvec_neg
, size
);
12373 gen_gvec_fn2(s
, is_q
, rd
, rn
, tcg_gen_gvec_abs
, size
);
12379 /* All 64-bit element operations can be shared with scalar 2misc */
12382 /* Coverity claims (size == 3 && !is_q) has been eliminated
12383 * from all paths leading to here.
12385 tcg_debug_assert(is_q
);
12386 for (pass
= 0; pass
< 2; pass
++) {
12387 TCGv_i64 tcg_op
= tcg_temp_new_i64();
12388 TCGv_i64 tcg_res
= tcg_temp_new_i64();
12390 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
12392 handle_2misc_64(s
, opcode
, u
, tcg_res
, tcg_op
,
12393 tcg_rmode
, tcg_fpstatus
);
12395 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
12397 tcg_temp_free_i64(tcg_res
);
12398 tcg_temp_free_i64(tcg_op
);
12403 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
12404 TCGv_i32 tcg_op
= tcg_temp_new_i32();
12405 TCGv_i32 tcg_res
= tcg_temp_new_i32();
12408 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
12411 /* Special cases for 32 bit elements */
12413 case 0xa: /* CMLT */
12414 /* 32 bit integer comparison against zero, result is
12415 * test ? (2^32 - 1) : 0. We implement via setcond(test)
12418 cond
= TCG_COND_LT
;
12420 tcg_gen_setcondi_i32(cond
, tcg_res
, tcg_op
, 0);
12421 tcg_gen_neg_i32(tcg_res
, tcg_res
);
12423 case 0x8: /* CMGT, CMGE */
12424 cond
= u
? TCG_COND_GE
: TCG_COND_GT
;
12426 case 0x9: /* CMEQ, CMLE */
12427 cond
= u
? TCG_COND_LE
: TCG_COND_EQ
;
12429 case 0x4: /* CLS */
12431 tcg_gen_clzi_i32(tcg_res
, tcg_op
, 32);
12433 tcg_gen_clrsb_i32(tcg_res
, tcg_op
);
12436 case 0x7: /* SQABS, SQNEG */
12438 gen_helper_neon_qneg_s32(tcg_res
, cpu_env
, tcg_op
);
12440 gen_helper_neon_qabs_s32(tcg_res
, cpu_env
, tcg_op
);
12443 case 0x2f: /* FABS */
12444 gen_helper_vfp_abss(tcg_res
, tcg_op
);
12446 case 0x6f: /* FNEG */
12447 gen_helper_vfp_negs(tcg_res
, tcg_op
);
12449 case 0x7f: /* FSQRT */
12450 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
12452 case 0x1a: /* FCVTNS */
12453 case 0x1b: /* FCVTMS */
12454 case 0x1c: /* FCVTAS */
12455 case 0x3a: /* FCVTPS */
12456 case 0x3b: /* FCVTZS */
12458 TCGv_i32 tcg_shift
= tcg_const_i32(0);
12459 gen_helper_vfp_tosls(tcg_res
, tcg_op
,
12460 tcg_shift
, tcg_fpstatus
);
12461 tcg_temp_free_i32(tcg_shift
);
12464 case 0x5a: /* FCVTNU */
12465 case 0x5b: /* FCVTMU */
12466 case 0x5c: /* FCVTAU */
12467 case 0x7a: /* FCVTPU */
12468 case 0x7b: /* FCVTZU */
12470 TCGv_i32 tcg_shift
= tcg_const_i32(0);
12471 gen_helper_vfp_touls(tcg_res
, tcg_op
,
12472 tcg_shift
, tcg_fpstatus
);
12473 tcg_temp_free_i32(tcg_shift
);
12476 case 0x18: /* FRINTN */
12477 case 0x19: /* FRINTM */
12478 case 0x38: /* FRINTP */
12479 case 0x39: /* FRINTZ */
12480 case 0x58: /* FRINTA */
12481 case 0x79: /* FRINTI */
12482 gen_helper_rints(tcg_res
, tcg_op
, tcg_fpstatus
);
12484 case 0x59: /* FRINTX */
12485 gen_helper_rints_exact(tcg_res
, tcg_op
, tcg_fpstatus
);
12487 case 0x7c: /* URSQRTE */
12488 gen_helper_rsqrte_u32(tcg_res
, tcg_op
, tcg_fpstatus
);
12490 case 0x1e: /* FRINT32Z */
12491 case 0x5e: /* FRINT32X */
12492 gen_helper_frint32_s(tcg_res
, tcg_op
, tcg_fpstatus
);
12494 case 0x1f: /* FRINT64Z */
12495 case 0x5f: /* FRINT64X */
12496 gen_helper_frint64_s(tcg_res
, tcg_op
, tcg_fpstatus
);
12499 g_assert_not_reached();
12502 /* Use helpers for 8 and 16 bit elements */
12504 case 0x5: /* CNT, RBIT */
12505 /* For these two insns size is part of the opcode specifier
12506 * (handled earlier); they always operate on byte elements.
12509 gen_helper_neon_rbit_u8(tcg_res
, tcg_op
);
12511 gen_helper_neon_cnt_u8(tcg_res
, tcg_op
);
12514 case 0x7: /* SQABS, SQNEG */
12516 NeonGenOneOpEnvFn
*genfn
;
12517 static NeonGenOneOpEnvFn
* const fns
[2][2] = {
12518 { gen_helper_neon_qabs_s8
, gen_helper_neon_qneg_s8
},
12519 { gen_helper_neon_qabs_s16
, gen_helper_neon_qneg_s16
},
12521 genfn
= fns
[size
][u
];
12522 genfn(tcg_res
, cpu_env
, tcg_op
);
12525 case 0x8: /* CMGT, CMGE */
12526 case 0x9: /* CMEQ, CMLE */
12527 case 0xa: /* CMLT */
12529 static NeonGenTwoOpFn
* const fns
[3][2] = {
12530 { gen_helper_neon_cgt_s8
, gen_helper_neon_cgt_s16
},
12531 { gen_helper_neon_cge_s8
, gen_helper_neon_cge_s16
},
12532 { gen_helper_neon_ceq_u8
, gen_helper_neon_ceq_u16
},
12534 NeonGenTwoOpFn
*genfn
;
12537 TCGv_i32 tcg_zero
= tcg_const_i32(0);
12539 /* comp = index into [CMGT, CMGE, CMEQ, CMLE, CMLT] */
12540 comp
= (opcode
- 0x8) * 2 + u
;
12541 /* ...but LE, LT are implemented as reverse GE, GT */
12542 reverse
= (comp
> 2);
12546 genfn
= fns
[comp
][size
];
12548 genfn(tcg_res
, tcg_zero
, tcg_op
);
12550 genfn(tcg_res
, tcg_op
, tcg_zero
);
12552 tcg_temp_free_i32(tcg_zero
);
12555 case 0x4: /* CLS, CLZ */
12558 gen_helper_neon_clz_u8(tcg_res
, tcg_op
);
12560 gen_helper_neon_clz_u16(tcg_res
, tcg_op
);
12564 gen_helper_neon_cls_s8(tcg_res
, tcg_op
);
12566 gen_helper_neon_cls_s16(tcg_res
, tcg_op
);
12571 g_assert_not_reached();
12575 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
12577 tcg_temp_free_i32(tcg_res
);
12578 tcg_temp_free_i32(tcg_op
);
12581 clear_vec_high(s
, is_q
, rd
);
12584 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
12585 tcg_temp_free_i32(tcg_rmode
);
12587 if (need_fpstatus
) {
12588 tcg_temp_free_ptr(tcg_fpstatus
);
12592 /* AdvSIMD [scalar] two register miscellaneous (FP16)
12594 * 31 30 29 28 27 24 23 22 21 17 16 12 11 10 9 5 4 0
12595 * +---+---+---+---+---------+---+-------------+--------+-----+------+------+
12596 * | 0 | Q | U | S | 1 1 1 0 | a | 1 1 1 1 0 0 | opcode | 1 0 | Rn | Rd |
12597 * +---+---+---+---+---------+---+-------------+--------+-----+------+------+
12598 * mask: 1000 1111 0111 1110 0000 1100 0000 0000 0x8f7e 0c00
12599 * val: 0000 1110 0111 1000 0000 1000 0000 0000 0x0e78 0800
12601 * This actually covers two groups where scalar access is governed by
12602 * bit 28. A bunch of the instructions (float to integral) only exist
12603 * in the vector form and are un-allocated for the scalar decode. Also
12604 * in the scalar decode Q is always 1.
12606 static void disas_simd_two_reg_misc_fp16(DisasContext
*s
, uint32_t insn
)
12608 int fpop
, opcode
, a
, u
;
12612 bool only_in_vector
= false;
12615 TCGv_i32 tcg_rmode
= NULL
;
12616 TCGv_ptr tcg_fpstatus
= NULL
;
12617 bool need_rmode
= false;
12618 bool need_fpst
= true;
12621 if (!dc_isar_feature(aa64_fp16
, s
)) {
12622 unallocated_encoding(s
);
12626 rd
= extract32(insn
, 0, 5);
12627 rn
= extract32(insn
, 5, 5);
12629 a
= extract32(insn
, 23, 1);
12630 u
= extract32(insn
, 29, 1);
12631 is_scalar
= extract32(insn
, 28, 1);
12632 is_q
= extract32(insn
, 30, 1);
12634 opcode
= extract32(insn
, 12, 5);
12635 fpop
= deposit32(opcode
, 5, 1, a
);
12636 fpop
= deposit32(fpop
, 6, 1, u
);
12638 rd
= extract32(insn
, 0, 5);
12639 rn
= extract32(insn
, 5, 5);
12642 case 0x1d: /* SCVTF */
12643 case 0x5d: /* UCVTF */
12650 elements
= (is_q
? 8 : 4);
12653 if (!fp_access_check(s
)) {
12656 handle_simd_intfp_conv(s
, rd
, rn
, elements
, !u
, 0, MO_16
);
12660 case 0x2c: /* FCMGT (zero) */
12661 case 0x2d: /* FCMEQ (zero) */
12662 case 0x2e: /* FCMLT (zero) */
12663 case 0x6c: /* FCMGE (zero) */
12664 case 0x6d: /* FCMLE (zero) */
12665 handle_2misc_fcmp_zero(s
, fpop
, is_scalar
, 0, is_q
, MO_16
, rn
, rd
);
12667 case 0x3d: /* FRECPE */
12668 case 0x3f: /* FRECPX */
12670 case 0x18: /* FRINTN */
12672 only_in_vector
= true;
12673 rmode
= FPROUNDING_TIEEVEN
;
12675 case 0x19: /* FRINTM */
12677 only_in_vector
= true;
12678 rmode
= FPROUNDING_NEGINF
;
12680 case 0x38: /* FRINTP */
12682 only_in_vector
= true;
12683 rmode
= FPROUNDING_POSINF
;
12685 case 0x39: /* FRINTZ */
12687 only_in_vector
= true;
12688 rmode
= FPROUNDING_ZERO
;
12690 case 0x58: /* FRINTA */
12692 only_in_vector
= true;
12693 rmode
= FPROUNDING_TIEAWAY
;
12695 case 0x59: /* FRINTX */
12696 case 0x79: /* FRINTI */
12697 only_in_vector
= true;
12698 /* current rounding mode */
12700 case 0x1a: /* FCVTNS */
12702 rmode
= FPROUNDING_TIEEVEN
;
12704 case 0x1b: /* FCVTMS */
12706 rmode
= FPROUNDING_NEGINF
;
12708 case 0x1c: /* FCVTAS */
12710 rmode
= FPROUNDING_TIEAWAY
;
12712 case 0x3a: /* FCVTPS */
12714 rmode
= FPROUNDING_POSINF
;
12716 case 0x3b: /* FCVTZS */
12718 rmode
= FPROUNDING_ZERO
;
12720 case 0x5a: /* FCVTNU */
12722 rmode
= FPROUNDING_TIEEVEN
;
12724 case 0x5b: /* FCVTMU */
12726 rmode
= FPROUNDING_NEGINF
;
12728 case 0x5c: /* FCVTAU */
12730 rmode
= FPROUNDING_TIEAWAY
;
12732 case 0x7a: /* FCVTPU */
12734 rmode
= FPROUNDING_POSINF
;
12736 case 0x7b: /* FCVTZU */
12738 rmode
= FPROUNDING_ZERO
;
12740 case 0x2f: /* FABS */
12741 case 0x6f: /* FNEG */
12744 case 0x7d: /* FRSQRTE */
12745 case 0x7f: /* FSQRT (vector) */
12748 fprintf(stderr
, "%s: insn %#04x fpop %#2x\n", __func__
, insn
, fpop
);
12749 g_assert_not_reached();
12753 /* Check additional constraints for the scalar encoding */
12756 unallocated_encoding(s
);
12759 /* FRINTxx is only in the vector form */
12760 if (only_in_vector
) {
12761 unallocated_encoding(s
);
12766 if (!fp_access_check(s
)) {
12770 if (need_rmode
|| need_fpst
) {
12771 tcg_fpstatus
= get_fpstatus_ptr(true);
12775 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
12776 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
12780 TCGv_i32 tcg_op
= read_fp_hreg(s
, rn
);
12781 TCGv_i32 tcg_res
= tcg_temp_new_i32();
12784 case 0x1a: /* FCVTNS */
12785 case 0x1b: /* FCVTMS */
12786 case 0x1c: /* FCVTAS */
12787 case 0x3a: /* FCVTPS */
12788 case 0x3b: /* FCVTZS */
12789 gen_helper_advsimd_f16tosinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12791 case 0x3d: /* FRECPE */
12792 gen_helper_recpe_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12794 case 0x3f: /* FRECPX */
12795 gen_helper_frecpx_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12797 case 0x5a: /* FCVTNU */
12798 case 0x5b: /* FCVTMU */
12799 case 0x5c: /* FCVTAU */
12800 case 0x7a: /* FCVTPU */
12801 case 0x7b: /* FCVTZU */
12802 gen_helper_advsimd_f16touinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12804 case 0x6f: /* FNEG */
12805 tcg_gen_xori_i32(tcg_res
, tcg_op
, 0x8000);
12807 case 0x7d: /* FRSQRTE */
12808 gen_helper_rsqrte_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12811 g_assert_not_reached();
12814 /* limit any sign extension going on */
12815 tcg_gen_andi_i32(tcg_res
, tcg_res
, 0xffff);
12816 write_fp_sreg(s
, rd
, tcg_res
);
12818 tcg_temp_free_i32(tcg_res
);
12819 tcg_temp_free_i32(tcg_op
);
12821 for (pass
= 0; pass
< (is_q
? 8 : 4); pass
++) {
12822 TCGv_i32 tcg_op
= tcg_temp_new_i32();
12823 TCGv_i32 tcg_res
= tcg_temp_new_i32();
12825 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_16
);
12828 case 0x1a: /* FCVTNS */
12829 case 0x1b: /* FCVTMS */
12830 case 0x1c: /* FCVTAS */
12831 case 0x3a: /* FCVTPS */
12832 case 0x3b: /* FCVTZS */
12833 gen_helper_advsimd_f16tosinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12835 case 0x3d: /* FRECPE */
12836 gen_helper_recpe_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12838 case 0x5a: /* FCVTNU */
12839 case 0x5b: /* FCVTMU */
12840 case 0x5c: /* FCVTAU */
12841 case 0x7a: /* FCVTPU */
12842 case 0x7b: /* FCVTZU */
12843 gen_helper_advsimd_f16touinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12845 case 0x18: /* FRINTN */
12846 case 0x19: /* FRINTM */
12847 case 0x38: /* FRINTP */
12848 case 0x39: /* FRINTZ */
12849 case 0x58: /* FRINTA */
12850 case 0x79: /* FRINTI */
12851 gen_helper_advsimd_rinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12853 case 0x59: /* FRINTX */
12854 gen_helper_advsimd_rinth_exact(tcg_res
, tcg_op
, tcg_fpstatus
);
12856 case 0x2f: /* FABS */
12857 tcg_gen_andi_i32(tcg_res
, tcg_op
, 0x7fff);
12859 case 0x6f: /* FNEG */
12860 tcg_gen_xori_i32(tcg_res
, tcg_op
, 0x8000);
12862 case 0x7d: /* FRSQRTE */
12863 gen_helper_rsqrte_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12865 case 0x7f: /* FSQRT */
12866 gen_helper_sqrt_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12869 g_assert_not_reached();
12872 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
12874 tcg_temp_free_i32(tcg_res
);
12875 tcg_temp_free_i32(tcg_op
);
12878 clear_vec_high(s
, is_q
, rd
);
12882 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
12883 tcg_temp_free_i32(tcg_rmode
);
12886 if (tcg_fpstatus
) {
12887 tcg_temp_free_ptr(tcg_fpstatus
);
12891 /* AdvSIMD scalar x indexed element
12892 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
12893 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
12894 * | 0 1 | U | 1 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
12895 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
12896 * AdvSIMD vector x indexed element
12897 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
12898 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
12899 * | 0 | Q | U | 0 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
12900 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
12902 static void disas_simd_indexed(DisasContext
*s
, uint32_t insn
)
12904 /* This encoding has two kinds of instruction:
12905 * normal, where we perform elt x idxelt => elt for each
12906 * element in the vector
12907 * long, where we perform elt x idxelt and generate a result of
12908 * double the width of the input element
12909 * The long ops have a 'part' specifier (ie come in INSN, INSN2 pairs).
12911 bool is_scalar
= extract32(insn
, 28, 1);
12912 bool is_q
= extract32(insn
, 30, 1);
12913 bool u
= extract32(insn
, 29, 1);
12914 int size
= extract32(insn
, 22, 2);
12915 int l
= extract32(insn
, 21, 1);
12916 int m
= extract32(insn
, 20, 1);
12917 /* Note that the Rm field here is only 4 bits, not 5 as it usually is */
12918 int rm
= extract32(insn
, 16, 4);
12919 int opcode
= extract32(insn
, 12, 4);
12920 int h
= extract32(insn
, 11, 1);
12921 int rn
= extract32(insn
, 5, 5);
12922 int rd
= extract32(insn
, 0, 5);
12923 bool is_long
= false;
12925 bool is_fp16
= false;
12929 switch (16 * u
+ opcode
) {
12930 case 0x08: /* MUL */
12931 case 0x10: /* MLA */
12932 case 0x14: /* MLS */
12934 unallocated_encoding(s
);
12938 case 0x02: /* SMLAL, SMLAL2 */
12939 case 0x12: /* UMLAL, UMLAL2 */
12940 case 0x06: /* SMLSL, SMLSL2 */
12941 case 0x16: /* UMLSL, UMLSL2 */
12942 case 0x0a: /* SMULL, SMULL2 */
12943 case 0x1a: /* UMULL, UMULL2 */
12945 unallocated_encoding(s
);
12950 case 0x03: /* SQDMLAL, SQDMLAL2 */
12951 case 0x07: /* SQDMLSL, SQDMLSL2 */
12952 case 0x0b: /* SQDMULL, SQDMULL2 */
12955 case 0x0c: /* SQDMULH */
12956 case 0x0d: /* SQRDMULH */
12958 case 0x01: /* FMLA */
12959 case 0x05: /* FMLS */
12960 case 0x09: /* FMUL */
12961 case 0x19: /* FMULX */
12964 case 0x1d: /* SQRDMLAH */
12965 case 0x1f: /* SQRDMLSH */
12966 if (!dc_isar_feature(aa64_rdm
, s
)) {
12967 unallocated_encoding(s
);
12971 case 0x0e: /* SDOT */
12972 case 0x1e: /* UDOT */
12973 if (is_scalar
|| size
!= MO_32
|| !dc_isar_feature(aa64_dp
, s
)) {
12974 unallocated_encoding(s
);
12978 case 0x11: /* FCMLA #0 */
12979 case 0x13: /* FCMLA #90 */
12980 case 0x15: /* FCMLA #180 */
12981 case 0x17: /* FCMLA #270 */
12982 if (is_scalar
|| !dc_isar_feature(aa64_fcma
, s
)) {
12983 unallocated_encoding(s
);
12988 case 0x00: /* FMLAL */
12989 case 0x04: /* FMLSL */
12990 case 0x18: /* FMLAL2 */
12991 case 0x1c: /* FMLSL2 */
12992 if (is_scalar
|| size
!= MO_32
|| !dc_isar_feature(aa64_fhm
, s
)) {
12993 unallocated_encoding(s
);
12997 /* is_fp, but we pass cpu_env not fp_status. */
13000 unallocated_encoding(s
);
13005 case 1: /* normal fp */
13006 /* convert insn encoded size to MemOp size */
13008 case 0: /* half-precision */
13012 case MO_32
: /* single precision */
13013 case MO_64
: /* double precision */
13016 unallocated_encoding(s
);
13021 case 2: /* complex fp */
13022 /* Each indexable element is a complex pair. */
13027 unallocated_encoding(s
);
13035 unallocated_encoding(s
);
13040 default: /* integer */
13044 unallocated_encoding(s
);
13049 if (is_fp16
&& !dc_isar_feature(aa64_fp16
, s
)) {
13050 unallocated_encoding(s
);
13054 /* Given MemOp size, adjust register and indexing. */
13057 index
= h
<< 2 | l
<< 1 | m
;
13060 index
= h
<< 1 | l
;
13065 unallocated_encoding(s
);
13072 g_assert_not_reached();
13075 if (!fp_access_check(s
)) {
13080 fpst
= get_fpstatus_ptr(is_fp16
);
13085 switch (16 * u
+ opcode
) {
13086 case 0x0e: /* SDOT */
13087 case 0x1e: /* UDOT */
13088 gen_gvec_op3_ool(s
, is_q
, rd
, rn
, rm
, index
,
13089 u
? gen_helper_gvec_udot_idx_b
13090 : gen_helper_gvec_sdot_idx_b
);
13092 case 0x11: /* FCMLA #0 */
13093 case 0x13: /* FCMLA #90 */
13094 case 0x15: /* FCMLA #180 */
13095 case 0x17: /* FCMLA #270 */
13097 int rot
= extract32(insn
, 13, 2);
13098 int data
= (index
<< 2) | rot
;
13099 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
13100 vec_full_reg_offset(s
, rn
),
13101 vec_full_reg_offset(s
, rm
), fpst
,
13102 is_q
? 16 : 8, vec_full_reg_size(s
), data
,
13104 ? gen_helper_gvec_fcmlas_idx
13105 : gen_helper_gvec_fcmlah_idx
);
13106 tcg_temp_free_ptr(fpst
);
13110 case 0x00: /* FMLAL */
13111 case 0x04: /* FMLSL */
13112 case 0x18: /* FMLAL2 */
13113 case 0x1c: /* FMLSL2 */
13115 int is_s
= extract32(opcode
, 2, 1);
13117 int data
= (index
<< 2) | (is_2
<< 1) | is_s
;
13118 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
13119 vec_full_reg_offset(s
, rn
),
13120 vec_full_reg_offset(s
, rm
), cpu_env
,
13121 is_q
? 16 : 8, vec_full_reg_size(s
),
13122 data
, gen_helper_gvec_fmlal_idx_a64
);
13128 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
13131 assert(is_fp
&& is_q
&& !is_long
);
13133 read_vec_element(s
, tcg_idx
, rm
, index
, MO_64
);
13135 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
13136 TCGv_i64 tcg_op
= tcg_temp_new_i64();
13137 TCGv_i64 tcg_res
= tcg_temp_new_i64();
13139 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
13141 switch (16 * u
+ opcode
) {
13142 case 0x05: /* FMLS */
13143 /* As usual for ARM, separate negation for fused multiply-add */
13144 gen_helper_vfp_negd(tcg_op
, tcg_op
);
13146 case 0x01: /* FMLA */
13147 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
13148 gen_helper_vfp_muladdd(tcg_res
, tcg_op
, tcg_idx
, tcg_res
, fpst
);
13150 case 0x09: /* FMUL */
13151 gen_helper_vfp_muld(tcg_res
, tcg_op
, tcg_idx
, fpst
);
13153 case 0x19: /* FMULX */
13154 gen_helper_vfp_mulxd(tcg_res
, tcg_op
, tcg_idx
, fpst
);
13157 g_assert_not_reached();
13160 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
13161 tcg_temp_free_i64(tcg_op
);
13162 tcg_temp_free_i64(tcg_res
);
13165 tcg_temp_free_i64(tcg_idx
);
13166 clear_vec_high(s
, !is_scalar
, rd
);
13167 } else if (!is_long
) {
13168 /* 32 bit floating point, or 16 or 32 bit integer.
13169 * For the 16 bit scalar case we use the usual Neon helpers and
13170 * rely on the fact that 0 op 0 == 0 with no side effects.
13172 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
13173 int pass
, maxpasses
;
13178 maxpasses
= is_q
? 4 : 2;
13181 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
13183 if (size
== 1 && !is_scalar
) {
13184 /* The simplest way to handle the 16x16 indexed ops is to duplicate
13185 * the index into both halves of the 32 bit tcg_idx and then use
13186 * the usual Neon helpers.
13188 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
13191 for (pass
= 0; pass
< maxpasses
; pass
++) {
13192 TCGv_i32 tcg_op
= tcg_temp_new_i32();
13193 TCGv_i32 tcg_res
= tcg_temp_new_i32();
13195 read_vec_element_i32(s
, tcg_op
, rn
, pass
, is_scalar
? size
: MO_32
);
13197 switch (16 * u
+ opcode
) {
13198 case 0x08: /* MUL */
13199 case 0x10: /* MLA */
13200 case 0x14: /* MLS */
13202 static NeonGenTwoOpFn
* const fns
[2][2] = {
13203 { gen_helper_neon_add_u16
, gen_helper_neon_sub_u16
},
13204 { tcg_gen_add_i32
, tcg_gen_sub_i32
},
13206 NeonGenTwoOpFn
*genfn
;
13207 bool is_sub
= opcode
== 0x4;
13210 gen_helper_neon_mul_u16(tcg_res
, tcg_op
, tcg_idx
);
13212 tcg_gen_mul_i32(tcg_res
, tcg_op
, tcg_idx
);
13214 if (opcode
== 0x8) {
13217 read_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
13218 genfn
= fns
[size
- 1][is_sub
];
13219 genfn(tcg_res
, tcg_op
, tcg_res
);
13222 case 0x05: /* FMLS */
13223 case 0x01: /* FMLA */
13224 read_vec_element_i32(s
, tcg_res
, rd
, pass
,
13225 is_scalar
? size
: MO_32
);
13228 if (opcode
== 0x5) {
13229 /* As usual for ARM, separate negation for fused
13231 tcg_gen_xori_i32(tcg_op
, tcg_op
, 0x80008000);
13234 gen_helper_advsimd_muladdh(tcg_res
, tcg_op
, tcg_idx
,
13237 gen_helper_advsimd_muladd2h(tcg_res
, tcg_op
, tcg_idx
,
13242 if (opcode
== 0x5) {
13243 /* As usual for ARM, separate negation for
13244 * fused multiply-add */
13245 tcg_gen_xori_i32(tcg_op
, tcg_op
, 0x80000000);
13247 gen_helper_vfp_muladds(tcg_res
, tcg_op
, tcg_idx
,
13251 g_assert_not_reached();
13254 case 0x09: /* FMUL */
13258 gen_helper_advsimd_mulh(tcg_res
, tcg_op
,
13261 gen_helper_advsimd_mul2h(tcg_res
, tcg_op
,
13266 gen_helper_vfp_muls(tcg_res
, tcg_op
, tcg_idx
, fpst
);
13269 g_assert_not_reached();
13272 case 0x19: /* FMULX */
13276 gen_helper_advsimd_mulxh(tcg_res
, tcg_op
,
13279 gen_helper_advsimd_mulx2h(tcg_res
, tcg_op
,
13284 gen_helper_vfp_mulxs(tcg_res
, tcg_op
, tcg_idx
, fpst
);
13287 g_assert_not_reached();
13290 case 0x0c: /* SQDMULH */
13292 gen_helper_neon_qdmulh_s16(tcg_res
, cpu_env
,
13295 gen_helper_neon_qdmulh_s32(tcg_res
, cpu_env
,
13299 case 0x0d: /* SQRDMULH */
13301 gen_helper_neon_qrdmulh_s16(tcg_res
, cpu_env
,
13304 gen_helper_neon_qrdmulh_s32(tcg_res
, cpu_env
,
13308 case 0x1d: /* SQRDMLAH */
13309 read_vec_element_i32(s
, tcg_res
, rd
, pass
,
13310 is_scalar
? size
: MO_32
);
13312 gen_helper_neon_qrdmlah_s16(tcg_res
, cpu_env
,
13313 tcg_op
, tcg_idx
, tcg_res
);
13315 gen_helper_neon_qrdmlah_s32(tcg_res
, cpu_env
,
13316 tcg_op
, tcg_idx
, tcg_res
);
13319 case 0x1f: /* SQRDMLSH */
13320 read_vec_element_i32(s
, tcg_res
, rd
, pass
,
13321 is_scalar
? size
: MO_32
);
13323 gen_helper_neon_qrdmlsh_s16(tcg_res
, cpu_env
,
13324 tcg_op
, tcg_idx
, tcg_res
);
13326 gen_helper_neon_qrdmlsh_s32(tcg_res
, cpu_env
,
13327 tcg_op
, tcg_idx
, tcg_res
);
13331 g_assert_not_reached();
13335 write_fp_sreg(s
, rd
, tcg_res
);
13337 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
13340 tcg_temp_free_i32(tcg_op
);
13341 tcg_temp_free_i32(tcg_res
);
13344 tcg_temp_free_i32(tcg_idx
);
13345 clear_vec_high(s
, is_q
, rd
);
13347 /* long ops: 16x16->32 or 32x32->64 */
13348 TCGv_i64 tcg_res
[2];
13350 bool satop
= extract32(opcode
, 0, 1);
13351 MemOp memop
= MO_32
;
13358 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
13360 read_vec_element(s
, tcg_idx
, rm
, index
, memop
);
13362 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
13363 TCGv_i64 tcg_op
= tcg_temp_new_i64();
13364 TCGv_i64 tcg_passres
;
13370 passelt
= pass
+ (is_q
* 2);
13373 read_vec_element(s
, tcg_op
, rn
, passelt
, memop
);
13375 tcg_res
[pass
] = tcg_temp_new_i64();
13377 if (opcode
== 0xa || opcode
== 0xb) {
13378 /* Non-accumulating ops */
13379 tcg_passres
= tcg_res
[pass
];
13381 tcg_passres
= tcg_temp_new_i64();
13384 tcg_gen_mul_i64(tcg_passres
, tcg_op
, tcg_idx
);
13385 tcg_temp_free_i64(tcg_op
);
13388 /* saturating, doubling */
13389 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
13390 tcg_passres
, tcg_passres
);
13393 if (opcode
== 0xa || opcode
== 0xb) {
13397 /* Accumulating op: handle accumulate step */
13398 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
13401 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
13402 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
13404 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
13405 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
13407 case 0x7: /* SQDMLSL, SQDMLSL2 */
13408 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
13410 case 0x3: /* SQDMLAL, SQDMLAL2 */
13411 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
13416 g_assert_not_reached();
13418 tcg_temp_free_i64(tcg_passres
);
13420 tcg_temp_free_i64(tcg_idx
);
13422 clear_vec_high(s
, !is_scalar
, rd
);
13424 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
13427 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
13430 /* The simplest way to handle the 16x16 indexed ops is to
13431 * duplicate the index into both halves of the 32 bit tcg_idx
13432 * and then use the usual Neon helpers.
13434 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
13437 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
13438 TCGv_i32 tcg_op
= tcg_temp_new_i32();
13439 TCGv_i64 tcg_passres
;
13442 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
13444 read_vec_element_i32(s
, tcg_op
, rn
,
13445 pass
+ (is_q
* 2), MO_32
);
13448 tcg_res
[pass
] = tcg_temp_new_i64();
13450 if (opcode
== 0xa || opcode
== 0xb) {
13451 /* Non-accumulating ops */
13452 tcg_passres
= tcg_res
[pass
];
13454 tcg_passres
= tcg_temp_new_i64();
13457 if (memop
& MO_SIGN
) {
13458 gen_helper_neon_mull_s16(tcg_passres
, tcg_op
, tcg_idx
);
13460 gen_helper_neon_mull_u16(tcg_passres
, tcg_op
, tcg_idx
);
13463 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
13464 tcg_passres
, tcg_passres
);
13466 tcg_temp_free_i32(tcg_op
);
13468 if (opcode
== 0xa || opcode
== 0xb) {
13472 /* Accumulating op: handle accumulate step */
13473 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
13476 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
13477 gen_helper_neon_addl_u32(tcg_res
[pass
], tcg_res
[pass
],
13480 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
13481 gen_helper_neon_subl_u32(tcg_res
[pass
], tcg_res
[pass
],
13484 case 0x7: /* SQDMLSL, SQDMLSL2 */
13485 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
13487 case 0x3: /* SQDMLAL, SQDMLAL2 */
13488 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
13493 g_assert_not_reached();
13495 tcg_temp_free_i64(tcg_passres
);
13497 tcg_temp_free_i32(tcg_idx
);
13500 tcg_gen_ext32u_i64(tcg_res
[0], tcg_res
[0]);
13505 tcg_res
[1] = tcg_const_i64(0);
13508 for (pass
= 0; pass
< 2; pass
++) {
13509 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
13510 tcg_temp_free_i64(tcg_res
[pass
]);
13515 tcg_temp_free_ptr(fpst
);
13520 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
13521 * +-----------------+------+-----------+--------+-----+------+------+
13522 * | 0 1 0 0 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
13523 * +-----------------+------+-----------+--------+-----+------+------+
13525 static void disas_crypto_aes(DisasContext
*s
, uint32_t insn
)
13527 int size
= extract32(insn
, 22, 2);
13528 int opcode
= extract32(insn
, 12, 5);
13529 int rn
= extract32(insn
, 5, 5);
13530 int rd
= extract32(insn
, 0, 5);
13532 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
;
13533 TCGv_i32 tcg_decrypt
;
13534 CryptoThreeOpIntFn
*genfn
;
13536 if (!dc_isar_feature(aa64_aes
, s
) || size
!= 0) {
13537 unallocated_encoding(s
);
13542 case 0x4: /* AESE */
13544 genfn
= gen_helper_crypto_aese
;
13546 case 0x6: /* AESMC */
13548 genfn
= gen_helper_crypto_aesmc
;
13550 case 0x5: /* AESD */
13552 genfn
= gen_helper_crypto_aese
;
13554 case 0x7: /* AESIMC */
13556 genfn
= gen_helper_crypto_aesmc
;
13559 unallocated_encoding(s
);
13563 if (!fp_access_check(s
)) {
13567 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
13568 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
13569 tcg_decrypt
= tcg_const_i32(decrypt
);
13571 genfn(tcg_rd_ptr
, tcg_rn_ptr
, tcg_decrypt
);
13573 tcg_temp_free_ptr(tcg_rd_ptr
);
13574 tcg_temp_free_ptr(tcg_rn_ptr
);
13575 tcg_temp_free_i32(tcg_decrypt
);
13578 /* Crypto three-reg SHA
13579 * 31 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
13580 * +-----------------+------+---+------+---+--------+-----+------+------+
13581 * | 0 1 0 1 1 1 1 0 | size | 0 | Rm | 0 | opcode | 0 0 | Rn | Rd |
13582 * +-----------------+------+---+------+---+--------+-----+------+------+
13584 static void disas_crypto_three_reg_sha(DisasContext
*s
, uint32_t insn
)
13586 int size
= extract32(insn
, 22, 2);
13587 int opcode
= extract32(insn
, 12, 3);
13588 int rm
= extract32(insn
, 16, 5);
13589 int rn
= extract32(insn
, 5, 5);
13590 int rd
= extract32(insn
, 0, 5);
13591 CryptoThreeOpFn
*genfn
;
13592 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
;
13596 unallocated_encoding(s
);
13601 case 0: /* SHA1C */
13602 case 1: /* SHA1P */
13603 case 2: /* SHA1M */
13604 case 3: /* SHA1SU0 */
13606 feature
= dc_isar_feature(aa64_sha1
, s
);
13608 case 4: /* SHA256H */
13609 genfn
= gen_helper_crypto_sha256h
;
13610 feature
= dc_isar_feature(aa64_sha256
, s
);
13612 case 5: /* SHA256H2 */
13613 genfn
= gen_helper_crypto_sha256h2
;
13614 feature
= dc_isar_feature(aa64_sha256
, s
);
13616 case 6: /* SHA256SU1 */
13617 genfn
= gen_helper_crypto_sha256su1
;
13618 feature
= dc_isar_feature(aa64_sha256
, s
);
13621 unallocated_encoding(s
);
13626 unallocated_encoding(s
);
13630 if (!fp_access_check(s
)) {
13634 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
13635 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
13636 tcg_rm_ptr
= vec_full_reg_ptr(s
, rm
);
13639 genfn(tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
);
13641 TCGv_i32 tcg_opcode
= tcg_const_i32(opcode
);
13643 gen_helper_crypto_sha1_3reg(tcg_rd_ptr
, tcg_rn_ptr
,
13644 tcg_rm_ptr
, tcg_opcode
);
13645 tcg_temp_free_i32(tcg_opcode
);
13648 tcg_temp_free_ptr(tcg_rd_ptr
);
13649 tcg_temp_free_ptr(tcg_rn_ptr
);
13650 tcg_temp_free_ptr(tcg_rm_ptr
);
13653 /* Crypto two-reg SHA
13654 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
13655 * +-----------------+------+-----------+--------+-----+------+------+
13656 * | 0 1 0 1 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
13657 * +-----------------+------+-----------+--------+-----+------+------+
13659 static void disas_crypto_two_reg_sha(DisasContext
*s
, uint32_t insn
)
13661 int size
= extract32(insn
, 22, 2);
13662 int opcode
= extract32(insn
, 12, 5);
13663 int rn
= extract32(insn
, 5, 5);
13664 int rd
= extract32(insn
, 0, 5);
13665 CryptoTwoOpFn
*genfn
;
13667 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
;
13670 unallocated_encoding(s
);
13675 case 0: /* SHA1H */
13676 feature
= dc_isar_feature(aa64_sha1
, s
);
13677 genfn
= gen_helper_crypto_sha1h
;
13679 case 1: /* SHA1SU1 */
13680 feature
= dc_isar_feature(aa64_sha1
, s
);
13681 genfn
= gen_helper_crypto_sha1su1
;
13683 case 2: /* SHA256SU0 */
13684 feature
= dc_isar_feature(aa64_sha256
, s
);
13685 genfn
= gen_helper_crypto_sha256su0
;
13688 unallocated_encoding(s
);
13693 unallocated_encoding(s
);
13697 if (!fp_access_check(s
)) {
13701 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
13702 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
13704 genfn(tcg_rd_ptr
, tcg_rn_ptr
);
13706 tcg_temp_free_ptr(tcg_rd_ptr
);
13707 tcg_temp_free_ptr(tcg_rn_ptr
);
13710 /* Crypto three-reg SHA512
13711 * 31 21 20 16 15 14 13 12 11 10 9 5 4 0
13712 * +-----------------------+------+---+---+-----+--------+------+------+
13713 * | 1 1 0 0 1 1 1 0 0 1 1 | Rm | 1 | O | 0 0 | opcode | Rn | Rd |
13714 * +-----------------------+------+---+---+-----+--------+------+------+
13716 static void disas_crypto_three_reg_sha512(DisasContext
*s
, uint32_t insn
)
13718 int opcode
= extract32(insn
, 10, 2);
13719 int o
= extract32(insn
, 14, 1);
13720 int rm
= extract32(insn
, 16, 5);
13721 int rn
= extract32(insn
, 5, 5);
13722 int rd
= extract32(insn
, 0, 5);
13724 CryptoThreeOpFn
*genfn
;
13728 case 0: /* SHA512H */
13729 feature
= dc_isar_feature(aa64_sha512
, s
);
13730 genfn
= gen_helper_crypto_sha512h
;
13732 case 1: /* SHA512H2 */
13733 feature
= dc_isar_feature(aa64_sha512
, s
);
13734 genfn
= gen_helper_crypto_sha512h2
;
13736 case 2: /* SHA512SU1 */
13737 feature
= dc_isar_feature(aa64_sha512
, s
);
13738 genfn
= gen_helper_crypto_sha512su1
;
13741 feature
= dc_isar_feature(aa64_sha3
, s
);
13745 g_assert_not_reached();
13749 case 0: /* SM3PARTW1 */
13750 feature
= dc_isar_feature(aa64_sm3
, s
);
13751 genfn
= gen_helper_crypto_sm3partw1
;
13753 case 1: /* SM3PARTW2 */
13754 feature
= dc_isar_feature(aa64_sm3
, s
);
13755 genfn
= gen_helper_crypto_sm3partw2
;
13757 case 2: /* SM4EKEY */
13758 feature
= dc_isar_feature(aa64_sm4
, s
);
13759 genfn
= gen_helper_crypto_sm4ekey
;
13762 unallocated_encoding(s
);
13768 unallocated_encoding(s
);
13772 if (!fp_access_check(s
)) {
13777 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
;
13779 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
13780 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
13781 tcg_rm_ptr
= vec_full_reg_ptr(s
, rm
);
13783 genfn(tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
);
13785 tcg_temp_free_ptr(tcg_rd_ptr
);
13786 tcg_temp_free_ptr(tcg_rn_ptr
);
13787 tcg_temp_free_ptr(tcg_rm_ptr
);
13789 TCGv_i64 tcg_op1
, tcg_op2
, tcg_res
[2];
13792 tcg_op1
= tcg_temp_new_i64();
13793 tcg_op2
= tcg_temp_new_i64();
13794 tcg_res
[0] = tcg_temp_new_i64();
13795 tcg_res
[1] = tcg_temp_new_i64();
13797 for (pass
= 0; pass
< 2; pass
++) {
13798 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
13799 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
13801 tcg_gen_rotli_i64(tcg_res
[pass
], tcg_op2
, 1);
13802 tcg_gen_xor_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
13804 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
13805 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
13807 tcg_temp_free_i64(tcg_op1
);
13808 tcg_temp_free_i64(tcg_op2
);
13809 tcg_temp_free_i64(tcg_res
[0]);
13810 tcg_temp_free_i64(tcg_res
[1]);
13814 /* Crypto two-reg SHA512
13815 * 31 12 11 10 9 5 4 0
13816 * +-----------------------------------------+--------+------+------+
13817 * | 1 1 0 0 1 1 1 0 1 1 0 0 0 0 0 0 1 0 0 0 | opcode | Rn | Rd |
13818 * +-----------------------------------------+--------+------+------+
13820 static void disas_crypto_two_reg_sha512(DisasContext
*s
, uint32_t insn
)
13822 int opcode
= extract32(insn
, 10, 2);
13823 int rn
= extract32(insn
, 5, 5);
13824 int rd
= extract32(insn
, 0, 5);
13825 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
;
13827 CryptoTwoOpFn
*genfn
;
13830 case 0: /* SHA512SU0 */
13831 feature
= dc_isar_feature(aa64_sha512
, s
);
13832 genfn
= gen_helper_crypto_sha512su0
;
13835 feature
= dc_isar_feature(aa64_sm4
, s
);
13836 genfn
= gen_helper_crypto_sm4e
;
13839 unallocated_encoding(s
);
13844 unallocated_encoding(s
);
13848 if (!fp_access_check(s
)) {
13852 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
13853 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
13855 genfn(tcg_rd_ptr
, tcg_rn_ptr
);
13857 tcg_temp_free_ptr(tcg_rd_ptr
);
13858 tcg_temp_free_ptr(tcg_rn_ptr
);
13861 /* Crypto four-register
13862 * 31 23 22 21 20 16 15 14 10 9 5 4 0
13863 * +-------------------+-----+------+---+------+------+------+
13864 * | 1 1 0 0 1 1 1 0 0 | Op0 | Rm | 0 | Ra | Rn | Rd |
13865 * +-------------------+-----+------+---+------+------+------+
13867 static void disas_crypto_four_reg(DisasContext
*s
, uint32_t insn
)
13869 int op0
= extract32(insn
, 21, 2);
13870 int rm
= extract32(insn
, 16, 5);
13871 int ra
= extract32(insn
, 10, 5);
13872 int rn
= extract32(insn
, 5, 5);
13873 int rd
= extract32(insn
, 0, 5);
13879 feature
= dc_isar_feature(aa64_sha3
, s
);
13881 case 2: /* SM3SS1 */
13882 feature
= dc_isar_feature(aa64_sm3
, s
);
13885 unallocated_encoding(s
);
13890 unallocated_encoding(s
);
13894 if (!fp_access_check(s
)) {
13899 TCGv_i64 tcg_op1
, tcg_op2
, tcg_op3
, tcg_res
[2];
13902 tcg_op1
= tcg_temp_new_i64();
13903 tcg_op2
= tcg_temp_new_i64();
13904 tcg_op3
= tcg_temp_new_i64();
13905 tcg_res
[0] = tcg_temp_new_i64();
13906 tcg_res
[1] = tcg_temp_new_i64();
13908 for (pass
= 0; pass
< 2; pass
++) {
13909 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
13910 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
13911 read_vec_element(s
, tcg_op3
, ra
, pass
, MO_64
);
13915 tcg_gen_xor_i64(tcg_res
[pass
], tcg_op2
, tcg_op3
);
13918 tcg_gen_andc_i64(tcg_res
[pass
], tcg_op2
, tcg_op3
);
13920 tcg_gen_xor_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
13922 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
13923 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
13925 tcg_temp_free_i64(tcg_op1
);
13926 tcg_temp_free_i64(tcg_op2
);
13927 tcg_temp_free_i64(tcg_op3
);
13928 tcg_temp_free_i64(tcg_res
[0]);
13929 tcg_temp_free_i64(tcg_res
[1]);
13931 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
, tcg_res
, tcg_zero
;
13933 tcg_op1
= tcg_temp_new_i32();
13934 tcg_op2
= tcg_temp_new_i32();
13935 tcg_op3
= tcg_temp_new_i32();
13936 tcg_res
= tcg_temp_new_i32();
13937 tcg_zero
= tcg_const_i32(0);
13939 read_vec_element_i32(s
, tcg_op1
, rn
, 3, MO_32
);
13940 read_vec_element_i32(s
, tcg_op2
, rm
, 3, MO_32
);
13941 read_vec_element_i32(s
, tcg_op3
, ra
, 3, MO_32
);
13943 tcg_gen_rotri_i32(tcg_res
, tcg_op1
, 20);
13944 tcg_gen_add_i32(tcg_res
, tcg_res
, tcg_op2
);
13945 tcg_gen_add_i32(tcg_res
, tcg_res
, tcg_op3
);
13946 tcg_gen_rotri_i32(tcg_res
, tcg_res
, 25);
13948 write_vec_element_i32(s
, tcg_zero
, rd
, 0, MO_32
);
13949 write_vec_element_i32(s
, tcg_zero
, rd
, 1, MO_32
);
13950 write_vec_element_i32(s
, tcg_zero
, rd
, 2, MO_32
);
13951 write_vec_element_i32(s
, tcg_res
, rd
, 3, MO_32
);
13953 tcg_temp_free_i32(tcg_op1
);
13954 tcg_temp_free_i32(tcg_op2
);
13955 tcg_temp_free_i32(tcg_op3
);
13956 tcg_temp_free_i32(tcg_res
);
13957 tcg_temp_free_i32(tcg_zero
);
13962 * 31 21 20 16 15 10 9 5 4 0
13963 * +-----------------------+------+--------+------+------+
13964 * | 1 1 0 0 1 1 1 0 1 0 0 | Rm | imm6 | Rn | Rd |
13965 * +-----------------------+------+--------+------+------+
13967 static void disas_crypto_xar(DisasContext
*s
, uint32_t insn
)
13969 int rm
= extract32(insn
, 16, 5);
13970 int imm6
= extract32(insn
, 10, 6);
13971 int rn
= extract32(insn
, 5, 5);
13972 int rd
= extract32(insn
, 0, 5);
13973 TCGv_i64 tcg_op1
, tcg_op2
, tcg_res
[2];
13976 if (!dc_isar_feature(aa64_sha3
, s
)) {
13977 unallocated_encoding(s
);
13981 if (!fp_access_check(s
)) {
13985 tcg_op1
= tcg_temp_new_i64();
13986 tcg_op2
= tcg_temp_new_i64();
13987 tcg_res
[0] = tcg_temp_new_i64();
13988 tcg_res
[1] = tcg_temp_new_i64();
13990 for (pass
= 0; pass
< 2; pass
++) {
13991 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
13992 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
13994 tcg_gen_xor_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
13995 tcg_gen_rotri_i64(tcg_res
[pass
], tcg_res
[pass
], imm6
);
13997 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
13998 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
14000 tcg_temp_free_i64(tcg_op1
);
14001 tcg_temp_free_i64(tcg_op2
);
14002 tcg_temp_free_i64(tcg_res
[0]);
14003 tcg_temp_free_i64(tcg_res
[1]);
14006 /* Crypto three-reg imm2
14007 * 31 21 20 16 15 14 13 12 11 10 9 5 4 0
14008 * +-----------------------+------+-----+------+--------+------+------+
14009 * | 1 1 0 0 1 1 1 0 0 1 0 | Rm | 1 0 | imm2 | opcode | Rn | Rd |
14010 * +-----------------------+------+-----+------+--------+------+------+
14012 static void disas_crypto_three_reg_imm2(DisasContext
*s
, uint32_t insn
)
14014 int opcode
= extract32(insn
, 10, 2);
14015 int imm2
= extract32(insn
, 12, 2);
14016 int rm
= extract32(insn
, 16, 5);
14017 int rn
= extract32(insn
, 5, 5);
14018 int rd
= extract32(insn
, 0, 5);
14019 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
;
14020 TCGv_i32 tcg_imm2
, tcg_opcode
;
14022 if (!dc_isar_feature(aa64_sm3
, s
)) {
14023 unallocated_encoding(s
);
14027 if (!fp_access_check(s
)) {
14031 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
14032 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
14033 tcg_rm_ptr
= vec_full_reg_ptr(s
, rm
);
14034 tcg_imm2
= tcg_const_i32(imm2
);
14035 tcg_opcode
= tcg_const_i32(opcode
);
14037 gen_helper_crypto_sm3tt(tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
, tcg_imm2
,
14040 tcg_temp_free_ptr(tcg_rd_ptr
);
14041 tcg_temp_free_ptr(tcg_rn_ptr
);
14042 tcg_temp_free_ptr(tcg_rm_ptr
);
14043 tcg_temp_free_i32(tcg_imm2
);
14044 tcg_temp_free_i32(tcg_opcode
);
14047 /* C3.6 Data processing - SIMD, inc Crypto
14049 * As the decode gets a little complex we are using a table based
14050 * approach for this part of the decode.
14052 static const AArch64DecodeTable data_proc_simd
[] = {
14053 /* pattern , mask , fn */
14054 { 0x0e200400, 0x9f200400, disas_simd_three_reg_same
},
14055 { 0x0e008400, 0x9f208400, disas_simd_three_reg_same_extra
},
14056 { 0x0e200000, 0x9f200c00, disas_simd_three_reg_diff
},
14057 { 0x0e200800, 0x9f3e0c00, disas_simd_two_reg_misc
},
14058 { 0x0e300800, 0x9f3e0c00, disas_simd_across_lanes
},
14059 { 0x0e000400, 0x9fe08400, disas_simd_copy
},
14060 { 0x0f000000, 0x9f000400, disas_simd_indexed
}, /* vector indexed */
14061 /* simd_mod_imm decode is a subset of simd_shift_imm, so must precede it */
14062 { 0x0f000400, 0x9ff80400, disas_simd_mod_imm
},
14063 { 0x0f000400, 0x9f800400, disas_simd_shift_imm
},
14064 { 0x0e000000, 0xbf208c00, disas_simd_tb
},
14065 { 0x0e000800, 0xbf208c00, disas_simd_zip_trn
},
14066 { 0x2e000000, 0xbf208400, disas_simd_ext
},
14067 { 0x5e200400, 0xdf200400, disas_simd_scalar_three_reg_same
},
14068 { 0x5e008400, 0xdf208400, disas_simd_scalar_three_reg_same_extra
},
14069 { 0x5e200000, 0xdf200c00, disas_simd_scalar_three_reg_diff
},
14070 { 0x5e200800, 0xdf3e0c00, disas_simd_scalar_two_reg_misc
},
14071 { 0x5e300800, 0xdf3e0c00, disas_simd_scalar_pairwise
},
14072 { 0x5e000400, 0xdfe08400, disas_simd_scalar_copy
},
14073 { 0x5f000000, 0xdf000400, disas_simd_indexed
}, /* scalar indexed */
14074 { 0x5f000400, 0xdf800400, disas_simd_scalar_shift_imm
},
14075 { 0x4e280800, 0xff3e0c00, disas_crypto_aes
},
14076 { 0x5e000000, 0xff208c00, disas_crypto_three_reg_sha
},
14077 { 0x5e280800, 0xff3e0c00, disas_crypto_two_reg_sha
},
14078 { 0xce608000, 0xffe0b000, disas_crypto_three_reg_sha512
},
14079 { 0xcec08000, 0xfffff000, disas_crypto_two_reg_sha512
},
14080 { 0xce000000, 0xff808000, disas_crypto_four_reg
},
14081 { 0xce800000, 0xffe00000, disas_crypto_xar
},
14082 { 0xce408000, 0xffe0c000, disas_crypto_three_reg_imm2
},
14083 { 0x0e400400, 0x9f60c400, disas_simd_three_reg_same_fp16
},
14084 { 0x0e780800, 0x8f7e0c00, disas_simd_two_reg_misc_fp16
},
14085 { 0x5e400400, 0xdf60c400, disas_simd_scalar_three_reg_same_fp16
},
14086 { 0x00000000, 0x00000000, NULL
}
14089 static void disas_data_proc_simd(DisasContext
*s
, uint32_t insn
)
14091 /* Note that this is called with all non-FP cases from
14092 * table C3-6 so it must UNDEF for entries not specifically
14093 * allocated to instructions in that table.
14095 AArch64DecodeFn
*fn
= lookup_disas_fn(&data_proc_simd
[0], insn
);
14099 unallocated_encoding(s
);
14103 /* C3.6 Data processing - SIMD and floating point */
14104 static void disas_data_proc_simd_fp(DisasContext
*s
, uint32_t insn
)
14106 if (extract32(insn
, 28, 1) == 1 && extract32(insn
, 30, 1) == 0) {
14107 disas_data_proc_fp(s
, insn
);
14109 /* SIMD, including crypto */
14110 disas_data_proc_simd(s
, insn
);
14116 * @env: The cpu environment
14117 * @s: The DisasContext
14119 * Return true if the page is guarded.
14121 static bool is_guarded_page(CPUARMState
*env
, DisasContext
*s
)
14123 #ifdef CONFIG_USER_ONLY
14124 return false; /* FIXME */
14126 uint64_t addr
= s
->base
.pc_first
;
14127 int mmu_idx
= arm_to_core_mmu_idx(s
->mmu_idx
);
14128 unsigned int index
= tlb_index(env
, mmu_idx
, addr
);
14129 CPUTLBEntry
*entry
= tlb_entry(env
, mmu_idx
, addr
);
14132 * We test this immediately after reading an insn, which means
14133 * that any normal page must be in the TLB. The only exception
14134 * would be for executing from flash or device memory, which
14135 * does not retain the TLB entry.
14137 * FIXME: Assume false for those, for now. We could use
14138 * arm_cpu_get_phys_page_attrs_debug to re-read the page
14139 * table entry even for that case.
14141 return (tlb_hit(entry
->addr_code
, addr
) &&
14142 env_tlb(env
)->d
[mmu_idx
].iotlb
[index
].attrs
.target_tlb_bit0
);
14147 * btype_destination_ok:
14148 * @insn: The instruction at the branch destination
14149 * @bt: SCTLR_ELx.BT
14150 * @btype: PSTATE.BTYPE, and is non-zero
14152 * On a guarded page, there are a limited number of insns
14153 * that may be present at the branch target:
14154 * - branch target identifiers,
14155 * - paciasp, pacibsp,
14158 * Anything else causes a Branch Target Exception.
14160 * Return true if the branch is compatible, false to raise BTITRAP.
14162 static bool btype_destination_ok(uint32_t insn
, bool bt
, int btype
)
14164 if ((insn
& 0xfffff01fu
) == 0xd503201fu
) {
14166 switch (extract32(insn
, 5, 7)) {
14167 case 0b011001: /* PACIASP */
14168 case 0b011011: /* PACIBSP */
14170 * If SCTLR_ELx.BT, then PACI*SP are not compatible
14171 * with btype == 3. Otherwise all btype are ok.
14173 return !bt
|| btype
!= 3;
14174 case 0b100000: /* BTI */
14175 /* Not compatible with any btype. */
14177 case 0b100010: /* BTI c */
14178 /* Not compatible with btype == 3 */
14180 case 0b100100: /* BTI j */
14181 /* Not compatible with btype == 2 */
14183 case 0b100110: /* BTI jc */
14184 /* Compatible with any btype. */
14188 switch (insn
& 0xffe0001fu
) {
14189 case 0xd4200000u
: /* BRK */
14190 case 0xd4400000u
: /* HLT */
14191 /* Give priority to the breakpoint exception. */
14198 /* C3.1 A64 instruction index by encoding */
14199 static void disas_a64_insn(CPUARMState
*env
, DisasContext
*s
)
14203 s
->pc_curr
= s
->base
.pc_next
;
14204 insn
= arm_ldl_code(env
, s
->base
.pc_next
, s
->sctlr_b
);
14206 s
->base
.pc_next
+= 4;
14208 s
->fp_access_checked
= false;
14210 if (dc_isar_feature(aa64_bti
, s
)) {
14211 if (s
->base
.num_insns
== 1) {
14213 * At the first insn of the TB, compute s->guarded_page.
14214 * We delayed computing this until successfully reading
14215 * the first insn of the TB, above. This (mostly) ensures
14216 * that the softmmu tlb entry has been populated, and the
14217 * page table GP bit is available.
14219 * Note that we need to compute this even if btype == 0,
14220 * because this value is used for BR instructions later
14221 * where ENV is not available.
14223 s
->guarded_page
= is_guarded_page(env
, s
);
14225 /* First insn can have btype set to non-zero. */
14226 tcg_debug_assert(s
->btype
>= 0);
14229 * Note that the Branch Target Exception has fairly high
14230 * priority -- below debugging exceptions but above most
14231 * everything else. This allows us to handle this now
14232 * instead of waiting until the insn is otherwise decoded.
14236 && !btype_destination_ok(insn
, s
->bt
, s
->btype
)) {
14237 gen_exception_insn(s
, s
->pc_curr
, EXCP_UDEF
,
14238 syn_btitrap(s
->btype
),
14239 default_exception_el(s
));
14243 /* Not the first insn: btype must be 0. */
14244 tcg_debug_assert(s
->btype
== 0);
14248 switch (extract32(insn
, 25, 4)) {
14249 case 0x0: case 0x1: case 0x3: /* UNALLOCATED */
14250 unallocated_encoding(s
);
14253 if (!dc_isar_feature(aa64_sve
, s
) || !disas_sve(s
, insn
)) {
14254 unallocated_encoding(s
);
14257 case 0x8: case 0x9: /* Data processing - immediate */
14258 disas_data_proc_imm(s
, insn
);
14260 case 0xa: case 0xb: /* Branch, exception generation and system insns */
14261 disas_b_exc_sys(s
, insn
);
14266 case 0xe: /* Loads and stores */
14267 disas_ldst(s
, insn
);
14270 case 0xd: /* Data processing - register */
14271 disas_data_proc_reg(s
, insn
);
14274 case 0xf: /* Data processing - SIMD and floating point */
14275 disas_data_proc_simd_fp(s
, insn
);
14278 assert(FALSE
); /* all 15 cases should be handled above */
14282 /* if we allocated any temporaries, free them here */
14286 * After execution of most insns, btype is reset to 0.
14287 * Note that we set btype == -1 when the insn sets btype.
14289 if (s
->btype
> 0 && s
->base
.is_jmp
!= DISAS_NORETURN
) {
14294 static void aarch64_tr_init_disas_context(DisasContextBase
*dcbase
,
14297 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14298 CPUARMState
*env
= cpu
->env_ptr
;
14299 ARMCPU
*arm_cpu
= env_archcpu(env
);
14300 uint32_t tb_flags
= dc
->base
.tb
->flags
;
14301 int bound
, core_mmu_idx
;
14303 dc
->isar
= &arm_cpu
->isar
;
14307 /* If we are coming from secure EL0 in a system with a 32-bit EL3, then
14308 * there is no secure EL1, so we route exceptions to EL3.
14310 dc
->secure_routed_to_el3
= arm_feature(env
, ARM_FEATURE_EL3
) &&
14311 !arm_el_is_aa64(env
, 3);
14314 dc
->be_data
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, BE_DATA
) ? MO_BE
: MO_LE
;
14315 dc
->condexec_mask
= 0;
14316 dc
->condexec_cond
= 0;
14317 core_mmu_idx
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, MMUIDX
);
14318 dc
->mmu_idx
= core_to_aa64_mmu_idx(core_mmu_idx
);
14319 dc
->tbii
= FIELD_EX32(tb_flags
, TBFLAG_A64
, TBII
);
14320 dc
->tbid
= FIELD_EX32(tb_flags
, TBFLAG_A64
, TBID
);
14321 dc
->current_el
= arm_mmu_idx_to_el(dc
->mmu_idx
);
14322 #if !defined(CONFIG_USER_ONLY)
14323 dc
->user
= (dc
->current_el
== 0);
14325 dc
->fp_excp_el
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, FPEXC_EL
);
14326 dc
->sve_excp_el
= FIELD_EX32(tb_flags
, TBFLAG_A64
, SVEEXC_EL
);
14327 dc
->sve_len
= (FIELD_EX32(tb_flags
, TBFLAG_A64
, ZCR_LEN
) + 1) * 16;
14328 dc
->pauth_active
= FIELD_EX32(tb_flags
, TBFLAG_A64
, PAUTH_ACTIVE
);
14329 dc
->bt
= FIELD_EX32(tb_flags
, TBFLAG_A64
, BT
);
14330 dc
->btype
= FIELD_EX32(tb_flags
, TBFLAG_A64
, BTYPE
);
14331 dc
->unpriv
= FIELD_EX32(tb_flags
, TBFLAG_A64
, UNPRIV
);
14333 dc
->vec_stride
= 0;
14334 dc
->cp_regs
= arm_cpu
->cp_regs
;
14335 dc
->features
= env
->features
;
14337 /* Single step state. The code-generation logic here is:
14339 * generate code with no special handling for single-stepping (except
14340 * that anything that can make us go to SS_ACTIVE == 1 must end the TB;
14341 * this happens anyway because those changes are all system register or
14343 * SS_ACTIVE == 1, PSTATE.SS == 1: (active-not-pending)
14344 * emit code for one insn
14345 * emit code to clear PSTATE.SS
14346 * emit code to generate software step exception for completed step
14347 * end TB (as usual for having generated an exception)
14348 * SS_ACTIVE == 1, PSTATE.SS == 0: (active-pending)
14349 * emit code to generate a software step exception
14352 dc
->ss_active
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, SS_ACTIVE
);
14353 dc
->pstate_ss
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, PSTATE_SS
);
14354 dc
->is_ldex
= false;
14355 dc
->debug_target_el
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, DEBUG_TARGET_EL
);
14357 /* Bound the number of insns to execute to those left on the page. */
14358 bound
= -(dc
->base
.pc_first
| TARGET_PAGE_MASK
) / 4;
14360 /* If architectural single step active, limit to 1. */
14361 if (dc
->ss_active
) {
14364 dc
->base
.max_insns
= MIN(dc
->base
.max_insns
, bound
);
14366 init_tmp_a64_array(dc
);
14369 static void aarch64_tr_tb_start(DisasContextBase
*db
, CPUState
*cpu
)
14373 static void aarch64_tr_insn_start(DisasContextBase
*dcbase
, CPUState
*cpu
)
14375 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14377 tcg_gen_insn_start(dc
->base
.pc_next
, 0, 0);
14378 dc
->insn_start
= tcg_last_op();
14381 static bool aarch64_tr_breakpoint_check(DisasContextBase
*dcbase
, CPUState
*cpu
,
14382 const CPUBreakpoint
*bp
)
14384 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14386 if (bp
->flags
& BP_CPU
) {
14387 gen_a64_set_pc_im(dc
->base
.pc_next
);
14388 gen_helper_check_breakpoints(cpu_env
);
14389 /* End the TB early; it likely won't be executed */
14390 dc
->base
.is_jmp
= DISAS_TOO_MANY
;
14392 gen_exception_internal_insn(dc
, dc
->base
.pc_next
, EXCP_DEBUG
);
14393 /* The address covered by the breakpoint must be
14394 included in [tb->pc, tb->pc + tb->size) in order
14395 to for it to be properly cleared -- thus we
14396 increment the PC here so that the logic setting
14397 tb->size below does the right thing. */
14398 dc
->base
.pc_next
+= 4;
14399 dc
->base
.is_jmp
= DISAS_NORETURN
;
14405 static void aarch64_tr_translate_insn(DisasContextBase
*dcbase
, CPUState
*cpu
)
14407 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14408 CPUARMState
*env
= cpu
->env_ptr
;
14410 if (dc
->ss_active
&& !dc
->pstate_ss
) {
14411 /* Singlestep state is Active-pending.
14412 * If we're in this state at the start of a TB then either
14413 * a) we just took an exception to an EL which is being debugged
14414 * and this is the first insn in the exception handler
14415 * b) debug exceptions were masked and we just unmasked them
14416 * without changing EL (eg by clearing PSTATE.D)
14417 * In either case we're going to take a swstep exception in the
14418 * "did not step an insn" case, and so the syndrome ISV and EX
14419 * bits should be zero.
14421 assert(dc
->base
.num_insns
== 1);
14422 gen_swstep_exception(dc
, 0, 0);
14423 dc
->base
.is_jmp
= DISAS_NORETURN
;
14425 disas_a64_insn(env
, dc
);
14428 translator_loop_temp_check(&dc
->base
);
14431 static void aarch64_tr_tb_stop(DisasContextBase
*dcbase
, CPUState
*cpu
)
14433 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14435 if (unlikely(dc
->base
.singlestep_enabled
|| dc
->ss_active
)) {
14436 /* Note that this means single stepping WFI doesn't halt the CPU.
14437 * For conditional branch insns this is harmless unreachable code as
14438 * gen_goto_tb() has already handled emitting the debug exception
14439 * (and thus a tb-jump is not possible when singlestepping).
14441 switch (dc
->base
.is_jmp
) {
14443 gen_a64_set_pc_im(dc
->base
.pc_next
);
14447 if (dc
->base
.singlestep_enabled
) {
14448 gen_exception_internal(EXCP_DEBUG
);
14450 gen_step_complete_exception(dc
);
14453 case DISAS_NORETURN
:
14457 switch (dc
->base
.is_jmp
) {
14459 case DISAS_TOO_MANY
:
14460 gen_goto_tb(dc
, 1, dc
->base
.pc_next
);
14464 gen_a64_set_pc_im(dc
->base
.pc_next
);
14467 tcg_gen_exit_tb(NULL
, 0);
14470 tcg_gen_lookup_and_goto_ptr();
14472 case DISAS_NORETURN
:
14476 gen_a64_set_pc_im(dc
->base
.pc_next
);
14477 gen_helper_wfe(cpu_env
);
14480 gen_a64_set_pc_im(dc
->base
.pc_next
);
14481 gen_helper_yield(cpu_env
);
14485 /* This is a special case because we don't want to just halt the CPU
14486 * if trying to debug across a WFI.
14488 TCGv_i32 tmp
= tcg_const_i32(4);
14490 gen_a64_set_pc_im(dc
->base
.pc_next
);
14491 gen_helper_wfi(cpu_env
, tmp
);
14492 tcg_temp_free_i32(tmp
);
14493 /* The helper doesn't necessarily throw an exception, but we
14494 * must go back to the main loop to check for interrupts anyway.
14496 tcg_gen_exit_tb(NULL
, 0);
14503 static void aarch64_tr_disas_log(const DisasContextBase
*dcbase
,
14506 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14508 qemu_log("IN: %s\n", lookup_symbol(dc
->base
.pc_first
));
14509 log_target_disas(cpu
, dc
->base
.pc_first
, dc
->base
.tb
->size
);
14512 const TranslatorOps aarch64_translator_ops
= {
14513 .init_disas_context
= aarch64_tr_init_disas_context
,
14514 .tb_start
= aarch64_tr_tb_start
,
14515 .insn_start
= aarch64_tr_insn_start
,
14516 .breakpoint_check
= aarch64_tr_breakpoint_check
,
14517 .translate_insn
= aarch64_tr_translate_insn
,
14518 .tb_stop
= aarch64_tr_tb_stop
,
14519 .disas_log
= aarch64_tr_disas_log
,