include/hw/misc/mos6522.h

   1 /*
   2  * QEMU MOS6522 VIA emulation
   3  *
   4  * Copyright (c) 2004-2007 Fabrice Bellard
   5  * Copyright (c) 2007 Jocelyn Mayer
   6  * Copyright (c) 2018 Mark Cave-Ayland
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a copy
   9  * of this software and associated documentation files (the "Software"), to deal
  10  * in the Software without restriction, including without limitation the rights
  11  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  12  * copies of the Software, and to permit persons to whom the Software is
  13  * furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice shall be included in
  16  * all copies or substantial portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  21  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  23  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  24  * THE SOFTWARE.
  25  */
  26
  27 #ifndef MOS6522_H
  28 #define MOS6522_H
  29
  30 #include "exec/memory.h"
  31 #include "hw/sysbus.h"
  32 #include "hw/input/adb.h"
  33 #include "qom/object.h"
  34
  35 /* Bits in ACR */
  36 #define SR_CTRL            0x1c    /* Shift register control bits */
  37 #define SR_EXT             0x0c    /* Shift on external clock */
  38 #define SR_OUT             0x10    /* Shift out if 1 */
  39
  40 /* Bits in IFR and IER */
  41 #define IER_SET            0x80    /* set bits in IER */
  42 #define IER_CLR            0       /* clear bits in IER */
  43
  44 #define CA2_INT_BIT        0
  45 #define CA1_INT_BIT        1
  46 #define SR_INT_BIT         2       /* Shift register full/empty */
  47 #define CB2_INT_BIT        3
  48 #define CB1_INT_BIT        4
  49 #define T2_INT_BIT         5       /* Timer 2 interrupt */
  50 #define T1_INT_BIT         6       /* Timer 1 interrupt */
  51
  52 #define CA2_INT            BIT(CA2_INT_BIT)
  53 #define CA1_INT            BIT(CA1_INT_BIT)
  54 #define SR_INT             BIT(SR_INT_BIT)
  55 #define CB2_INT            BIT(CB2_INT_BIT)
  56 #define CB1_INT            BIT(CB1_INT_BIT)
  57 #define T2_INT             BIT(T2_INT_BIT)
  58 #define T1_INT             BIT(T1_INT_BIT)
  59
  60 #define VIA_NUM_INTS       5
  61
  62 /* Bits in ACR */
  63 #define T1MODE             0xc0    /* Timer 1 mode */
  64 #define T1MODE_CONT        0x40    /*  continuous interrupts */
  65
  66 /* VIA registers */
  67 #define VIA_REG_B       0x00
  68 #define VIA_REG_A       0x01
  69 #define VIA_REG_DIRB    0x02
  70 #define VIA_REG_DIRA    0x03
  71 #define VIA_REG_T1CL    0x04
  72 #define VIA_REG_T1CH    0x05
  73 #define VIA_REG_T1LL    0x06
  74 #define VIA_REG_T1LH    0x07
  75 #define VIA_REG_T2CL    0x08
  76 #define VIA_REG_T2CH    0x09
  77 #define VIA_REG_SR      0x0a
  78 #define VIA_REG_ACR     0x0b
  79 #define VIA_REG_PCR     0x0c
  80 #define VIA_REG_IFR     0x0d
  81 #define VIA_REG_IER     0x0e
  82 #define VIA_REG_ANH     0x0f
  83
  84 /**
  85  * MOS6522Timer:
  86  * @counter_value: counter value at load time
  87  */
  88 typedef struct MOS6522Timer {
  89     int index;
  90     uint16_t latch;
  91     uint16_t counter_value;
  92     int64_t load_time;
  93     int64_t next_irq_time;
  94     uint64_t frequency;
  95     QEMUTimer *timer;
  96 } MOS6522Timer;
  97
  98 /**
  99  * MOS6522State:
 100  * @b: B-side data
 101  * @a: A-side data
 102  * @dirb: B-side direction (1=output)
 103  * @dira: A-side direction (1=output)
 104  * @sr: Shift register
 105  * @acr: Auxiliary control register
 106  * @pcr: Peripheral control register
 107  * @ifr: Interrupt flag register
 108  * @ier: Interrupt enable register
 109  * @anh: A-side data, no handshake
 110  * @last_b: last value of B register
 111  * @last_acr: last value of ACR register
 112  */
 113 struct MOS6522State {
 114     /*< private >*/
 115     SysBusDevice parent_obj;
 116     /*< public >*/
 117
 118     MemoryRegion mem;
 119     /* VIA registers */
 120     uint8_t b;
 121     uint8_t a;
 122     uint8_t dirb;
 123     uint8_t dira;
 124     uint8_t sr;
 125     uint8_t acr;
 126     uint8_t pcr;
 127     uint8_t ifr;
 128     uint8_t ier;
 129
 130     MOS6522Timer timers[2];
 131     uint64_t frequency;
 132
 133     qemu_irq irq;
 134 };
 135
 136 #define TYPE_MOS6522 "mos6522"
 137 OBJECT_DECLARE_TYPE(MOS6522State, MOS6522DeviceClass, MOS6522)
 138
 139 struct MOS6522DeviceClass {
 140     DeviceClass parent_class;
 141
 142     DeviceReset parent_reset;
 143     void (*portB_write)(MOS6522State *dev);
 144     void (*portA_write)(MOS6522State *dev);
 145     /* These are used to influence the CUDA MacOS timebase calibration */
 146     uint64_t (*get_timer1_counter_value)(MOS6522State *dev, MOS6522Timer *ti);
 147     uint64_t (*get_timer2_counter_value)(MOS6522State *dev, MOS6522Timer *ti);
 148     uint64_t (*get_timer1_load_time)(MOS6522State *dev, MOS6522Timer *ti);
 149     uint64_t (*get_timer2_load_time)(MOS6522State *dev, MOS6522Timer *ti);
 150 };
 151
 152
 153 extern const VMStateDescription vmstate_mos6522;
 154
 155 uint64_t mos6522_read(void *opaque, hwaddr addr, unsigned size);
 156 void mos6522_write(void *opaque, hwaddr addr, uint64_t val, unsigned size);
 157
 158 #endif /* MOS6522_H */