2 * PowerPC CPU initialization for qemu.
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright 2011 Freescale Semiconductor, Inc.
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2.1 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 #include "qemu/osdep.h"
22 #include "disas/dis-asm.h"
23 #include "gdbstub/helpers.h"
25 #include "sysemu/cpus.h"
26 #include "sysemu/hw_accel.h"
27 #include "sysemu/tcg.h"
28 #include "cpu-models.h"
29 #include "mmu-hash32.h"
30 #include "mmu-hash64.h"
31 #include "qemu/error-report.h"
32 #include "qemu/module.h"
33 #include "qemu/qemu-print.h"
34 #include "qapi/error.h"
35 #include "qapi/qmp/qnull.h"
36 #include "qapi/visitor.h"
37 #include "hw/qdev-properties.h"
38 #include "hw/ppc/ppc.h"
39 #include "mmu-book3s-v3.h"
40 #include "qemu/cutils.h"
41 #include "disas/capstone.h"
42 #include "fpu/softfloat.h"
44 #include "helper_regs.h"
46 #include "spr_common.h"
47 #include "power8-pmu.h"
49 #ifndef CONFIG_USER_ONLY
50 #include "hw/boards.h"
51 #include "hw/intc/intc.h"
54 /* #define PPC_DEBUG_SPR */
55 /* #define USE_APPLE_GDB */
57 static inline void vscr_init(CPUPPCState
*env
, uint32_t val
)
59 /* Altivec always uses round-to-nearest */
60 set_float_rounding_mode(float_round_nearest_even
, &env
->vec_status
);
61 ppc_store_vscr(env
, val
);
64 static void register_745_sprs(CPUPPCState
*env
)
67 spr_register(env
, SPR_SPRG4
, "SPRG4",
68 SPR_NOACCESS
, SPR_NOACCESS
,
69 &spr_read_generic
, &spr_write_generic
,
71 spr_register(env
, SPR_SPRG5
, "SPRG5",
72 SPR_NOACCESS
, SPR_NOACCESS
,
73 &spr_read_generic
, &spr_write_generic
,
75 spr_register(env
, SPR_SPRG6
, "SPRG6",
76 SPR_NOACCESS
, SPR_NOACCESS
,
77 &spr_read_generic
, &spr_write_generic
,
79 spr_register(env
, SPR_SPRG7
, "SPRG7",
80 SPR_NOACCESS
, SPR_NOACCESS
,
81 &spr_read_generic
, &spr_write_generic
,
84 /* Hardware implementation registers */
85 spr_register(env
, SPR_HID0
, "HID0",
86 SPR_NOACCESS
, SPR_NOACCESS
,
87 &spr_read_generic
, &spr_write_generic
,
90 spr_register(env
, SPR_HID1
, "HID1",
91 SPR_NOACCESS
, SPR_NOACCESS
,
92 &spr_read_generic
, &spr_write_generic
,
95 spr_register(env
, SPR_HID2
, "HID2",
96 SPR_NOACCESS
, SPR_NOACCESS
,
97 &spr_read_generic
, &spr_write_generic
,
101 static void register_755_sprs(CPUPPCState
*env
)
103 /* L2 cache control */
104 spr_register(env
, SPR_L2CR
, "L2CR",
105 SPR_NOACCESS
, SPR_NOACCESS
,
106 &spr_read_generic
, spr_access_nop
,
109 spr_register(env
, SPR_L2PMCR
, "L2PMCR",
110 SPR_NOACCESS
, SPR_NOACCESS
,
111 &spr_read_generic
, &spr_write_generic
,
115 /* SPR common to all 7xx PowerPC implementations */
116 static void register_7xx_sprs(CPUPPCState
*env
)
119 spr_register_kvm(env
, SPR_DABR
, "DABR",
120 SPR_NOACCESS
, SPR_NOACCESS
,
121 &spr_read_generic
, &spr_write_generic
,
122 KVM_REG_PPC_DABR
, 0x00000000);
124 spr_register(env
, SPR_IABR
, "IABR",
125 SPR_NOACCESS
, SPR_NOACCESS
,
126 &spr_read_generic
, &spr_write_generic
,
128 /* Cache management */
129 spr_register(env
, SPR_ICTC
, "ICTC",
130 SPR_NOACCESS
, SPR_NOACCESS
,
131 &spr_read_generic
, &spr_write_generic
,
133 /* Performance monitors */
134 spr_register(env
, SPR_7XX_MMCR0
, "MMCR0",
135 SPR_NOACCESS
, SPR_NOACCESS
,
136 &spr_read_generic
, &spr_write_generic
,
139 spr_register(env
, SPR_7XX_MMCR1
, "MMCR1",
140 SPR_NOACCESS
, SPR_NOACCESS
,
141 &spr_read_generic
, &spr_write_generic
,
144 spr_register(env
, SPR_7XX_PMC1
, "PMC1",
145 SPR_NOACCESS
, SPR_NOACCESS
,
146 &spr_read_generic
, &spr_write_generic
,
149 spr_register(env
, SPR_7XX_PMC2
, "PMC2",
150 SPR_NOACCESS
, SPR_NOACCESS
,
151 &spr_read_generic
, &spr_write_generic
,
154 spr_register(env
, SPR_7XX_PMC3
, "PMC3",
155 SPR_NOACCESS
, SPR_NOACCESS
,
156 &spr_read_generic
, &spr_write_generic
,
159 spr_register(env
, SPR_7XX_PMC4
, "PMC4",
160 SPR_NOACCESS
, SPR_NOACCESS
,
161 &spr_read_generic
, &spr_write_generic
,
164 spr_register(env
, SPR_7XX_SIAR
, "SIAR",
165 SPR_NOACCESS
, SPR_NOACCESS
,
166 &spr_read_generic
, SPR_NOACCESS
,
169 spr_register(env
, SPR_7XX_UMMCR0
, "UMMCR0",
170 &spr_read_ureg
, SPR_NOACCESS
,
171 &spr_read_ureg
, SPR_NOACCESS
,
174 spr_register(env
, SPR_7XX_UMMCR1
, "UMMCR1",
175 &spr_read_ureg
, SPR_NOACCESS
,
176 &spr_read_ureg
, SPR_NOACCESS
,
179 spr_register(env
, SPR_7XX_UPMC1
, "UPMC1",
180 &spr_read_ureg
, SPR_NOACCESS
,
181 &spr_read_ureg
, SPR_NOACCESS
,
184 spr_register(env
, SPR_7XX_UPMC2
, "UPMC2",
185 &spr_read_ureg
, SPR_NOACCESS
,
186 &spr_read_ureg
, SPR_NOACCESS
,
189 spr_register(env
, SPR_7XX_UPMC3
, "UPMC3",
190 &spr_read_ureg
, SPR_NOACCESS
,
191 &spr_read_ureg
, SPR_NOACCESS
,
194 spr_register(env
, SPR_7XX_UPMC4
, "UPMC4",
195 &spr_read_ureg
, SPR_NOACCESS
,
196 &spr_read_ureg
, SPR_NOACCESS
,
199 spr_register(env
, SPR_7XX_USIAR
, "USIAR",
200 &spr_read_ureg
, SPR_NOACCESS
,
201 &spr_read_ureg
, SPR_NOACCESS
,
203 /* External access control */
204 spr_register(env
, SPR_EAR
, "EAR",
205 SPR_NOACCESS
, SPR_NOACCESS
,
206 &spr_read_generic
, &spr_write_generic
,
209 /* Hardware implementation registers */
210 spr_register(env
, SPR_HID0
, "HID0",
211 SPR_NOACCESS
, SPR_NOACCESS
,
212 &spr_read_generic
, &spr_write_generic
,
215 spr_register(env
, SPR_HID1
, "HID1",
216 SPR_NOACCESS
, SPR_NOACCESS
,
217 &spr_read_generic
, &spr_write_generic
,
222 static void register_amr_sprs(CPUPPCState
*env
)
224 #ifndef CONFIG_USER_ONLY
226 * Virtual Page Class Key protection
228 * The AMR is accessible either via SPR 13 or SPR 29. 13 is
229 * userspace accessible, 29 is privileged. So we only need to set
230 * the kvm ONE_REG id on one of them, we use 29
232 spr_register(env
, SPR_UAMR
, "UAMR",
233 &spr_read_generic
, &spr_write_amr
,
234 &spr_read_generic
, &spr_write_amr
,
236 spr_register_kvm_hv(env
, SPR_AMR
, "AMR",
237 SPR_NOACCESS
, SPR_NOACCESS
,
238 &spr_read_generic
, &spr_write_amr
,
239 &spr_read_generic
, &spr_write_generic
,
241 spr_register_kvm_hv(env
, SPR_UAMOR
, "UAMOR",
242 SPR_NOACCESS
, SPR_NOACCESS
,
243 &spr_read_generic
, &spr_write_uamor
,
244 &spr_read_generic
, &spr_write_generic
,
245 KVM_REG_PPC_UAMOR
, 0);
246 spr_register_hv(env
, SPR_AMOR
, "AMOR",
247 SPR_NOACCESS
, SPR_NOACCESS
,
248 SPR_NOACCESS
, SPR_NOACCESS
,
249 &spr_read_generic
, &spr_write_generic
,
251 #endif /* !CONFIG_USER_ONLY */
254 static void register_iamr_sprs(CPUPPCState
*env
)
256 #ifndef CONFIG_USER_ONLY
257 spr_register_kvm_hv(env
, SPR_IAMR
, "IAMR",
258 SPR_NOACCESS
, SPR_NOACCESS
,
259 &spr_read_generic
, &spr_write_iamr
,
260 &spr_read_generic
, &spr_write_generic
,
261 KVM_REG_PPC_IAMR
, 0);
262 #endif /* !CONFIG_USER_ONLY */
264 #endif /* TARGET_PPC64 */
266 /* SPR specific to PowerPC 604 implementation */
267 static void register_604_sprs(CPUPPCState
*env
)
269 /* Processor identification */
270 spr_register(env
, SPR_PIR
, "PIR",
271 SPR_NOACCESS
, SPR_NOACCESS
,
272 &spr_read_generic
, &spr_write_pir
,
275 spr_register(env
, SPR_IABR
, "IABR",
276 SPR_NOACCESS
, SPR_NOACCESS
,
277 &spr_read_generic
, &spr_write_generic
,
280 spr_register_kvm(env
, SPR_DABR
, "DABR",
281 SPR_NOACCESS
, SPR_NOACCESS
,
282 &spr_read_generic
, &spr_write_generic
,
283 KVM_REG_PPC_DABR
, 0x00000000);
284 /* Performance counters */
285 spr_register(env
, SPR_7XX_MMCR0
, "MMCR0",
286 SPR_NOACCESS
, SPR_NOACCESS
,
287 &spr_read_generic
, &spr_write_generic
,
290 spr_register(env
, SPR_7XX_PMC1
, "PMC1",
291 SPR_NOACCESS
, SPR_NOACCESS
,
292 &spr_read_generic
, &spr_write_generic
,
295 spr_register(env
, SPR_7XX_PMC2
, "PMC2",
296 SPR_NOACCESS
, SPR_NOACCESS
,
297 &spr_read_generic
, &spr_write_generic
,
300 spr_register(env
, SPR_7XX_SIAR
, "SIAR",
301 SPR_NOACCESS
, SPR_NOACCESS
,
302 &spr_read_generic
, SPR_NOACCESS
,
305 spr_register(env
, SPR_SDA
, "SDA",
306 SPR_NOACCESS
, SPR_NOACCESS
,
307 &spr_read_generic
, SPR_NOACCESS
,
309 /* External access control */
310 spr_register(env
, SPR_EAR
, "EAR",
311 SPR_NOACCESS
, SPR_NOACCESS
,
312 &spr_read_generic
, &spr_write_generic
,
315 /* Hardware implementation registers */
316 spr_register(env
, SPR_HID0
, "HID0",
317 SPR_NOACCESS
, SPR_NOACCESS
,
318 &spr_read_generic
, &spr_write_generic
,
322 static void register_604e_sprs(CPUPPCState
*env
)
324 spr_register(env
, SPR_7XX_MMCR1
, "MMCR1",
325 SPR_NOACCESS
, SPR_NOACCESS
,
326 &spr_read_generic
, &spr_write_generic
,
329 spr_register(env
, SPR_7XX_PMC3
, "PMC3",
330 SPR_NOACCESS
, SPR_NOACCESS
,
331 &spr_read_generic
, &spr_write_generic
,
334 spr_register(env
, SPR_7XX_PMC4
, "PMC4",
335 SPR_NOACCESS
, SPR_NOACCESS
,
336 &spr_read_generic
, &spr_write_generic
,
338 /* Hardware implementation registers */
339 spr_register(env
, SPR_HID1
, "HID1",
340 SPR_NOACCESS
, SPR_NOACCESS
,
341 &spr_read_generic
, &spr_write_generic
,
345 /* SPR specific to PowerPC 603 implementation */
346 static void register_603_sprs(CPUPPCState
*env
)
348 /* External access control */
349 spr_register(env
, SPR_EAR
, "EAR",
350 SPR_NOACCESS
, SPR_NOACCESS
,
351 &spr_read_generic
, &spr_write_generic
,
354 spr_register(env
, SPR_IABR
, "IABR",
355 SPR_NOACCESS
, SPR_NOACCESS
,
356 &spr_read_generic
, &spr_write_generic
,
359 spr_register(env
, SPR_HID0
, "HID0",
360 SPR_NOACCESS
, SPR_NOACCESS
,
361 &spr_read_generic
, &spr_write_generic
,
364 spr_register(env
, SPR_HID1
, "HID1",
365 SPR_NOACCESS
, SPR_NOACCESS
,
366 &spr_read_generic
, &spr_write_generic
,
370 static void register_e300_sprs(CPUPPCState
*env
)
372 /* hardware implementation registers */
373 spr_register(env
, SPR_HID2
, "HID2",
374 SPR_NOACCESS
, SPR_NOACCESS
,
375 &spr_read_generic
, &spr_write_generic
,
378 spr_register(env
, SPR_DABR
, "DABR",
379 SPR_NOACCESS
, SPR_NOACCESS
,
380 &spr_read_generic
, &spr_write_generic
,
383 spr_register(env
, SPR_DABR2
, "DABR2",
384 SPR_NOACCESS
, SPR_NOACCESS
,
385 &spr_read_generic
, &spr_write_generic
,
388 spr_register(env
, SPR_IABR2
, "IABR2",
389 SPR_NOACCESS
, SPR_NOACCESS
,
390 &spr_read_generic
, &spr_write_generic
,
393 spr_register(env
, SPR_IBCR
, "IBCR",
394 SPR_NOACCESS
, SPR_NOACCESS
,
395 &spr_read_generic
, &spr_write_generic
,
398 spr_register(env
, SPR_DBCR
, "DBCR",
399 SPR_NOACCESS
, SPR_NOACCESS
,
400 &spr_read_generic
, &spr_write_generic
,
404 /* SPR specific to PowerPC G2 implementation */
405 static void register_G2_sprs(CPUPPCState
*env
)
407 /* Memory base address */
409 spr_register(env
, SPR_MBAR
, "MBAR",
410 SPR_NOACCESS
, SPR_NOACCESS
,
411 &spr_read_generic
, &spr_write_generic
,
413 /* Exception processing */
414 spr_register(env
, SPR_BOOKE_CSRR0
, "CSRR0",
415 SPR_NOACCESS
, SPR_NOACCESS
,
416 &spr_read_generic
, &spr_write_generic
,
418 spr_register(env
, SPR_BOOKE_CSRR1
, "CSRR1",
419 SPR_NOACCESS
, SPR_NOACCESS
,
420 &spr_read_generic
, &spr_write_generic
,
423 spr_register(env
, SPR_DABR
, "DABR",
424 SPR_NOACCESS
, SPR_NOACCESS
,
425 &spr_read_generic
, &spr_write_generic
,
428 spr_register(env
, SPR_DABR2
, "DABR2",
429 SPR_NOACCESS
, SPR_NOACCESS
,
430 &spr_read_generic
, &spr_write_generic
,
433 spr_register(env
, SPR_IABR
, "IABR",
434 SPR_NOACCESS
, SPR_NOACCESS
,
435 &spr_read_generic
, &spr_write_generic
,
438 spr_register(env
, SPR_IABR2
, "IABR2",
439 SPR_NOACCESS
, SPR_NOACCESS
,
440 &spr_read_generic
, &spr_write_generic
,
443 spr_register(env
, SPR_IBCR
, "IBCR",
444 SPR_NOACCESS
, SPR_NOACCESS
,
445 &spr_read_generic
, &spr_write_generic
,
448 spr_register(env
, SPR_DBCR
, "DBCR",
449 SPR_NOACCESS
, SPR_NOACCESS
,
450 &spr_read_generic
, &spr_write_generic
,
453 /* External access control */
454 spr_register(env
, SPR_EAR
, "EAR",
455 SPR_NOACCESS
, SPR_NOACCESS
,
456 &spr_read_generic
, &spr_write_generic
,
458 /* Hardware implementation register */
459 spr_register(env
, SPR_HID0
, "HID0",
460 SPR_NOACCESS
, SPR_NOACCESS
,
461 &spr_read_generic
, &spr_write_generic
,
464 spr_register(env
, SPR_HID1
, "HID1",
465 SPR_NOACCESS
, SPR_NOACCESS
,
466 &spr_read_generic
, &spr_write_generic
,
469 spr_register(env
, SPR_HID2
, "HID2",
470 SPR_NOACCESS
, SPR_NOACCESS
,
471 &spr_read_generic
, &spr_write_generic
,
475 spr_register(env
, SPR_SPRG4
, "SPRG4",
476 SPR_NOACCESS
, SPR_NOACCESS
,
477 &spr_read_generic
, &spr_write_generic
,
479 spr_register(env
, SPR_SPRG5
, "SPRG5",
480 SPR_NOACCESS
, SPR_NOACCESS
,
481 &spr_read_generic
, &spr_write_generic
,
483 spr_register(env
, SPR_SPRG6
, "SPRG6",
484 SPR_NOACCESS
, SPR_NOACCESS
,
485 &spr_read_generic
, &spr_write_generic
,
487 spr_register(env
, SPR_SPRG7
, "SPRG7",
488 SPR_NOACCESS
, SPR_NOACCESS
,
489 &spr_read_generic
, &spr_write_generic
,
493 static void register_74xx_sprs(CPUPPCState
*env
)
496 spr_register_kvm(env
, SPR_DABR
, "DABR",
497 SPR_NOACCESS
, SPR_NOACCESS
,
498 &spr_read_generic
, &spr_write_generic
,
499 KVM_REG_PPC_DABR
, 0x00000000);
501 spr_register(env
, SPR_IABR
, "IABR",
502 SPR_NOACCESS
, SPR_NOACCESS
,
503 &spr_read_generic
, &spr_write_generic
,
505 /* Cache management */
506 spr_register(env
, SPR_ICTC
, "ICTC",
507 SPR_NOACCESS
, SPR_NOACCESS
,
508 &spr_read_generic
, &spr_write_generic
,
510 /* Performance monitors */
511 spr_register(env
, SPR_7XX_MMCR0
, "MMCR0",
512 SPR_NOACCESS
, SPR_NOACCESS
,
513 &spr_read_generic
, &spr_write_generic
,
516 spr_register(env
, SPR_7XX_MMCR1
, "MMCR1",
517 SPR_NOACCESS
, SPR_NOACCESS
,
518 &spr_read_generic
, &spr_write_generic
,
521 spr_register(env
, SPR_7XX_PMC1
, "PMC1",
522 SPR_NOACCESS
, SPR_NOACCESS
,
523 &spr_read_generic
, &spr_write_generic
,
526 spr_register(env
, SPR_7XX_PMC2
, "PMC2",
527 SPR_NOACCESS
, SPR_NOACCESS
,
528 &spr_read_generic
, &spr_write_generic
,
531 spr_register(env
, SPR_7XX_PMC3
, "PMC3",
532 SPR_NOACCESS
, SPR_NOACCESS
,
533 &spr_read_generic
, &spr_write_generic
,
536 spr_register(env
, SPR_7XX_PMC4
, "PMC4",
537 SPR_NOACCESS
, SPR_NOACCESS
,
538 &spr_read_generic
, &spr_write_generic
,
541 spr_register(env
, SPR_7XX_SIAR
, "SIAR",
542 SPR_NOACCESS
, SPR_NOACCESS
,
543 &spr_read_generic
, SPR_NOACCESS
,
546 spr_register(env
, SPR_7XX_UMMCR0
, "UMMCR0",
547 &spr_read_ureg
, SPR_NOACCESS
,
548 &spr_read_ureg
, SPR_NOACCESS
,
551 spr_register(env
, SPR_7XX_UMMCR1
, "UMMCR1",
552 &spr_read_ureg
, SPR_NOACCESS
,
553 &spr_read_ureg
, SPR_NOACCESS
,
556 spr_register(env
, SPR_7XX_UPMC1
, "UPMC1",
557 &spr_read_ureg
, SPR_NOACCESS
,
558 &spr_read_ureg
, SPR_NOACCESS
,
561 spr_register(env
, SPR_7XX_UPMC2
, "UPMC2",
562 &spr_read_ureg
, SPR_NOACCESS
,
563 &spr_read_ureg
, SPR_NOACCESS
,
566 spr_register(env
, SPR_7XX_UPMC3
, "UPMC3",
567 &spr_read_ureg
, SPR_NOACCESS
,
568 &spr_read_ureg
, SPR_NOACCESS
,
571 spr_register(env
, SPR_7XX_UPMC4
, "UPMC4",
572 &spr_read_ureg
, SPR_NOACCESS
,
573 &spr_read_ureg
, SPR_NOACCESS
,
576 spr_register(env
, SPR_7XX_USIAR
, "USIAR",
577 &spr_read_ureg
, SPR_NOACCESS
,
578 &spr_read_ureg
, SPR_NOACCESS
,
580 /* External access control */
581 spr_register(env
, SPR_EAR
, "EAR",
582 SPR_NOACCESS
, SPR_NOACCESS
,
583 &spr_read_generic
, &spr_write_generic
,
586 /* Processor identification */
587 spr_register(env
, SPR_PIR
, "PIR",
588 SPR_NOACCESS
, SPR_NOACCESS
,
589 &spr_read_generic
, &spr_write_pir
,
592 spr_register(env
, SPR_74XX_MMCR2
, "MMCR2",
593 SPR_NOACCESS
, SPR_NOACCESS
,
594 &spr_read_generic
, &spr_write_generic
,
597 spr_register(env
, SPR_74XX_UMMCR2
, "UMMCR2",
598 &spr_read_ureg
, SPR_NOACCESS
,
599 &spr_read_ureg
, SPR_NOACCESS
,
602 spr_register(env
, SPR_BAMR
, "BAMR",
603 SPR_NOACCESS
, SPR_NOACCESS
,
604 &spr_read_generic
, &spr_write_generic
,
607 spr_register(env
, SPR_MSSCR0
, "MSSCR0",
608 SPR_NOACCESS
, SPR_NOACCESS
,
609 &spr_read_generic
, &spr_write_generic
,
611 /* Hardware implementation registers */
612 spr_register(env
, SPR_HID0
, "HID0",
613 SPR_NOACCESS
, SPR_NOACCESS
,
614 &spr_read_generic
, &spr_write_generic
,
617 spr_register(env
, SPR_HID1
, "HID1",
618 SPR_NOACCESS
, SPR_NOACCESS
,
619 &spr_read_generic
, &spr_write_generic
,
622 spr_register(env
, SPR_VRSAVE
, "VRSAVE",
623 &spr_read_generic
, &spr_write_generic
,
624 &spr_read_generic
, &spr_write_generic
,
627 spr_register(env
, SPR_L2CR
, "L2CR",
628 SPR_NOACCESS
, SPR_NOACCESS
,
629 &spr_read_generic
, spr_access_nop
,
633 static void register_l3_ctrl(CPUPPCState
*env
)
636 spr_register(env
, SPR_L3CR
, "L3CR",
637 SPR_NOACCESS
, SPR_NOACCESS
,
638 &spr_read_generic
, &spr_write_generic
,
641 spr_register(env
, SPR_L3ITCR0
, "L3ITCR0",
642 SPR_NOACCESS
, SPR_NOACCESS
,
643 &spr_read_generic
, &spr_write_generic
,
646 spr_register(env
, SPR_L3PM
, "L3PM",
647 SPR_NOACCESS
, SPR_NOACCESS
,
648 &spr_read_generic
, &spr_write_generic
,
652 /* PowerPC BookE SPR */
653 static void register_BookE_sprs(CPUPPCState
*env
, uint64_t ivor_mask
)
655 const char *ivor_names
[64] = {
656 "IVOR0", "IVOR1", "IVOR2", "IVOR3",
657 "IVOR4", "IVOR5", "IVOR6", "IVOR7",
658 "IVOR8", "IVOR9", "IVOR10", "IVOR11",
659 "IVOR12", "IVOR13", "IVOR14", "IVOR15",
660 "IVOR16", "IVOR17", "IVOR18", "IVOR19",
661 "IVOR20", "IVOR21", "IVOR22", "IVOR23",
662 "IVOR24", "IVOR25", "IVOR26", "IVOR27",
663 "IVOR28", "IVOR29", "IVOR30", "IVOR31",
664 "IVOR32", "IVOR33", "IVOR34", "IVOR35",
665 "IVOR36", "IVOR37", "IVOR38", "IVOR39",
666 "IVOR40", "IVOR41", "IVOR42", "IVOR43",
667 "IVOR44", "IVOR45", "IVOR46", "IVOR47",
668 "IVOR48", "IVOR49", "IVOR50", "IVOR51",
669 "IVOR52", "IVOR53", "IVOR54", "IVOR55",
670 "IVOR56", "IVOR57", "IVOR58", "IVOR59",
671 "IVOR60", "IVOR61", "IVOR62", "IVOR63",
673 #define SPR_BOOKE_IVORxx (-1)
674 int ivor_sprn
[64] = {
675 SPR_BOOKE_IVOR0
, SPR_BOOKE_IVOR1
, SPR_BOOKE_IVOR2
, SPR_BOOKE_IVOR3
,
676 SPR_BOOKE_IVOR4
, SPR_BOOKE_IVOR5
, SPR_BOOKE_IVOR6
, SPR_BOOKE_IVOR7
,
677 SPR_BOOKE_IVOR8
, SPR_BOOKE_IVOR9
, SPR_BOOKE_IVOR10
, SPR_BOOKE_IVOR11
,
678 SPR_BOOKE_IVOR12
, SPR_BOOKE_IVOR13
, SPR_BOOKE_IVOR14
, SPR_BOOKE_IVOR15
,
679 SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
,
680 SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
,
681 SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
,
682 SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
,
683 SPR_BOOKE_IVOR32
, SPR_BOOKE_IVOR33
, SPR_BOOKE_IVOR34
, SPR_BOOKE_IVOR35
,
684 SPR_BOOKE_IVOR36
, SPR_BOOKE_IVOR37
, SPR_BOOKE_IVOR38
, SPR_BOOKE_IVOR39
,
685 SPR_BOOKE_IVOR40
, SPR_BOOKE_IVOR41
, SPR_BOOKE_IVOR42
, SPR_BOOKE_IVORxx
,
686 SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
,
687 SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
,
688 SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
,
689 SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
,
690 SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
,
694 /* Interrupt processing */
695 spr_register(env
, SPR_BOOKE_CSRR0
, "CSRR0",
696 SPR_NOACCESS
, SPR_NOACCESS
,
697 &spr_read_generic
, &spr_write_generic
,
699 spr_register(env
, SPR_BOOKE_CSRR1
, "CSRR1",
700 SPR_NOACCESS
, SPR_NOACCESS
,
701 &spr_read_generic
, &spr_write_generic
,
704 spr_register(env
, SPR_BOOKE_IAC1
, "IAC1",
705 SPR_NOACCESS
, SPR_NOACCESS
,
706 &spr_read_generic
, &spr_write_generic
,
709 spr_register(env
, SPR_BOOKE_IAC2
, "IAC2",
710 SPR_NOACCESS
, SPR_NOACCESS
,
711 &spr_read_generic
, &spr_write_generic
,
714 spr_register(env
, SPR_BOOKE_DAC1
, "DAC1",
715 SPR_NOACCESS
, SPR_NOACCESS
,
716 &spr_read_generic
, &spr_write_generic
,
719 spr_register(env
, SPR_BOOKE_DAC2
, "DAC2",
720 SPR_NOACCESS
, SPR_NOACCESS
,
721 &spr_read_generic
, &spr_write_generic
,
724 spr_register(env
, SPR_BOOKE_DBCR0
, "DBCR0",
725 SPR_NOACCESS
, SPR_NOACCESS
,
726 &spr_read_generic
, &spr_write_40x_dbcr0
,
729 spr_register(env
, SPR_BOOKE_DBCR1
, "DBCR1",
730 SPR_NOACCESS
, SPR_NOACCESS
,
731 &spr_read_generic
, &spr_write_generic
,
734 spr_register(env
, SPR_BOOKE_DBCR2
, "DBCR2",
735 SPR_NOACCESS
, SPR_NOACCESS
,
736 &spr_read_generic
, &spr_write_generic
,
738 spr_register(env
, SPR_BOOKE_DSRR0
, "DSRR0",
739 SPR_NOACCESS
, SPR_NOACCESS
,
740 &spr_read_generic
, &spr_write_generic
,
742 spr_register(env
, SPR_BOOKE_DSRR1
, "DSRR1",
743 SPR_NOACCESS
, SPR_NOACCESS
,
744 &spr_read_generic
, &spr_write_generic
,
747 spr_register(env
, SPR_BOOKE_DBSR
, "DBSR",
748 SPR_NOACCESS
, SPR_NOACCESS
,
749 &spr_read_generic
, &spr_write_clear
,
751 spr_register(env
, SPR_BOOKE_DEAR
, "DEAR",
752 SPR_NOACCESS
, SPR_NOACCESS
,
753 &spr_read_generic
, &spr_write_generic
,
755 spr_register(env
, SPR_BOOKE_ESR
, "ESR",
756 SPR_NOACCESS
, SPR_NOACCESS
,
757 &spr_read_generic
, &spr_write_generic
,
759 spr_register(env
, SPR_BOOKE_IVPR
, "IVPR",
760 SPR_NOACCESS
, SPR_NOACCESS
,
761 &spr_read_generic
, &spr_write_excp_prefix
,
763 /* Exception vectors */
764 for (i
= 0; i
< 64; i
++) {
765 if (ivor_mask
& (1ULL << i
)) {
766 if (ivor_sprn
[i
] == SPR_BOOKE_IVORxx
) {
767 fprintf(stderr
, "ERROR: IVOR %d SPR is not defined\n", i
);
770 spr_register(env
, ivor_sprn
[i
], ivor_names
[i
],
771 SPR_NOACCESS
, SPR_NOACCESS
,
772 &spr_read_generic
, &spr_write_excp_vector
,
776 spr_register(env
, SPR_BOOKE_PID
, "PID",
777 SPR_NOACCESS
, SPR_NOACCESS
,
778 &spr_read_generic
, &spr_write_booke_pid
,
780 spr_register(env
, SPR_BOOKE_TCR
, "TCR",
781 SPR_NOACCESS
, SPR_NOACCESS
,
782 &spr_read_generic
, &spr_write_booke_tcr
,
784 spr_register(env
, SPR_BOOKE_TSR
, "TSR",
785 SPR_NOACCESS
, SPR_NOACCESS
,
786 &spr_read_generic
, &spr_write_booke_tsr
,
789 spr_register(env
, SPR_DECR
, "DECR",
790 SPR_NOACCESS
, SPR_NOACCESS
,
791 &spr_read_decr
, &spr_write_decr
,
793 spr_register(env
, SPR_BOOKE_DECAR
, "DECAR",
794 SPR_NOACCESS
, SPR_NOACCESS
,
795 SPR_NOACCESS
, &spr_write_generic
,
798 spr_register(env
, SPR_USPRG0
, "USPRG0",
799 &spr_read_generic
, &spr_write_generic
,
800 &spr_read_generic
, &spr_write_generic
,
802 spr_register(env
, SPR_SPRG4
, "SPRG4",
803 SPR_NOACCESS
, SPR_NOACCESS
,
804 &spr_read_generic
, &spr_write_generic
,
806 spr_register(env
, SPR_SPRG5
, "SPRG5",
807 SPR_NOACCESS
, SPR_NOACCESS
,
808 &spr_read_generic
, &spr_write_generic
,
810 spr_register(env
, SPR_SPRG6
, "SPRG6",
811 SPR_NOACCESS
, SPR_NOACCESS
,
812 &spr_read_generic
, &spr_write_generic
,
814 spr_register(env
, SPR_SPRG7
, "SPRG7",
815 SPR_NOACCESS
, SPR_NOACCESS
,
816 &spr_read_generic
, &spr_write_generic
,
818 spr_register(env
, SPR_BOOKE_SPRG8
, "SPRG8",
819 SPR_NOACCESS
, SPR_NOACCESS
,
820 &spr_read_generic
, &spr_write_generic
,
822 spr_register(env
, SPR_BOOKE_SPRG9
, "SPRG9",
823 SPR_NOACCESS
, SPR_NOACCESS
,
824 &spr_read_generic
, &spr_write_generic
,
828 #if !defined(CONFIG_USER_ONLY)
829 static inline uint32_t register_tlbncfg(uint32_t assoc
, uint32_t minsize
,
830 uint32_t maxsize
, uint32_t flags
,
833 return (assoc
<< TLBnCFG_ASSOC_SHIFT
) |
834 (minsize
<< TLBnCFG_MINSIZE_SHIFT
) |
835 (maxsize
<< TLBnCFG_MAXSIZE_SHIFT
) |
838 #endif /* !CONFIG_USER_ONLY */
840 /* BookE 2.06 storage control registers */
841 static void register_BookE206_sprs(CPUPPCState
*env
, uint32_t mas_mask
,
842 uint32_t *tlbncfg
, uint32_t mmucfg
)
844 #if !defined(CONFIG_USER_ONLY)
845 const char *mas_names
[8] = {
846 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
849 SPR_BOOKE_MAS0
, SPR_BOOKE_MAS1
, SPR_BOOKE_MAS2
, SPR_BOOKE_MAS3
,
850 SPR_BOOKE_MAS4
, SPR_BOOKE_MAS5
, SPR_BOOKE_MAS6
, SPR_BOOKE_MAS7
,
854 /* TLB assist registers */
855 for (i
= 0; i
< 8; i
++) {
856 if (mas_mask
& (1 << i
)) {
857 spr_register(env
, mas_sprn
[i
], mas_names
[i
],
858 SPR_NOACCESS
, SPR_NOACCESS
,
860 (i
== 2 && (env
->insns_flags
& PPC_64B
))
861 ? &spr_write_generic
: &spr_write_generic32
,
865 if (env
->nb_pids
> 1) {
866 spr_register(env
, SPR_BOOKE_PID1
, "PID1",
867 SPR_NOACCESS
, SPR_NOACCESS
,
868 &spr_read_generic
, &spr_write_booke_pid
,
871 if (env
->nb_pids
> 2) {
872 spr_register(env
, SPR_BOOKE_PID2
, "PID2",
873 SPR_NOACCESS
, SPR_NOACCESS
,
874 &spr_read_generic
, &spr_write_booke_pid
,
878 spr_register(env
, SPR_BOOKE_EPLC
, "EPLC",
879 SPR_NOACCESS
, SPR_NOACCESS
,
880 &spr_read_generic
, &spr_write_eplc
,
882 spr_register(env
, SPR_BOOKE_EPSC
, "EPSC",
883 SPR_NOACCESS
, SPR_NOACCESS
,
884 &spr_read_generic
, &spr_write_epsc
,
887 spr_register(env
, SPR_MMUCFG
, "MMUCFG",
888 SPR_NOACCESS
, SPR_NOACCESS
,
889 &spr_read_generic
, SPR_NOACCESS
,
891 switch (env
->nb_ways
) {
893 spr_register(env
, SPR_BOOKE_TLB3CFG
, "TLB3CFG",
894 SPR_NOACCESS
, SPR_NOACCESS
,
895 &spr_read_generic
, SPR_NOACCESS
,
899 spr_register(env
, SPR_BOOKE_TLB2CFG
, "TLB2CFG",
900 SPR_NOACCESS
, SPR_NOACCESS
,
901 &spr_read_generic
, SPR_NOACCESS
,
905 spr_register(env
, SPR_BOOKE_TLB1CFG
, "TLB1CFG",
906 SPR_NOACCESS
, SPR_NOACCESS
,
907 &spr_read_generic
, SPR_NOACCESS
,
911 spr_register(env
, SPR_BOOKE_TLB0CFG
, "TLB0CFG",
912 SPR_NOACCESS
, SPR_NOACCESS
,
913 &spr_read_generic
, SPR_NOACCESS
,
923 /* SPR specific to PowerPC 440 implementation */
924 static void register_440_sprs(CPUPPCState
*env
)
927 spr_register(env
, SPR_440_DNV0
, "DNV0",
928 SPR_NOACCESS
, SPR_NOACCESS
,
929 &spr_read_generic
, &spr_write_generic
,
932 spr_register(env
, SPR_440_DNV1
, "DNV1",
933 SPR_NOACCESS
, SPR_NOACCESS
,
934 &spr_read_generic
, &spr_write_generic
,
937 spr_register(env
, SPR_440_DNV2
, "DNV2",
938 SPR_NOACCESS
, SPR_NOACCESS
,
939 &spr_read_generic
, &spr_write_generic
,
942 spr_register(env
, SPR_440_DNV3
, "DNV3",
943 SPR_NOACCESS
, SPR_NOACCESS
,
944 &spr_read_generic
, &spr_write_generic
,
947 spr_register(env
, SPR_440_DTV0
, "DTV0",
948 SPR_NOACCESS
, SPR_NOACCESS
,
949 &spr_read_generic
, &spr_write_generic
,
952 spr_register(env
, SPR_440_DTV1
, "DTV1",
953 SPR_NOACCESS
, SPR_NOACCESS
,
954 &spr_read_generic
, &spr_write_generic
,
957 spr_register(env
, SPR_440_DTV2
, "DTV2",
958 SPR_NOACCESS
, SPR_NOACCESS
,
959 &spr_read_generic
, &spr_write_generic
,
962 spr_register(env
, SPR_440_DTV3
, "DTV3",
963 SPR_NOACCESS
, SPR_NOACCESS
,
964 &spr_read_generic
, &spr_write_generic
,
967 spr_register(env
, SPR_440_DVLIM
, "DVLIM",
968 SPR_NOACCESS
, SPR_NOACCESS
,
969 &spr_read_generic
, &spr_write_generic
,
972 spr_register(env
, SPR_440_INV0
, "INV0",
973 SPR_NOACCESS
, SPR_NOACCESS
,
974 &spr_read_generic
, &spr_write_generic
,
977 spr_register(env
, SPR_440_INV1
, "INV1",
978 SPR_NOACCESS
, SPR_NOACCESS
,
979 &spr_read_generic
, &spr_write_generic
,
982 spr_register(env
, SPR_440_INV2
, "INV2",
983 SPR_NOACCESS
, SPR_NOACCESS
,
984 &spr_read_generic
, &spr_write_generic
,
987 spr_register(env
, SPR_440_INV3
, "INV3",
988 SPR_NOACCESS
, SPR_NOACCESS
,
989 &spr_read_generic
, &spr_write_generic
,
992 spr_register(env
, SPR_440_ITV0
, "ITV0",
993 SPR_NOACCESS
, SPR_NOACCESS
,
994 &spr_read_generic
, &spr_write_generic
,
997 spr_register(env
, SPR_440_ITV1
, "ITV1",
998 SPR_NOACCESS
, SPR_NOACCESS
,
999 &spr_read_generic
, &spr_write_generic
,
1002 spr_register(env
, SPR_440_ITV2
, "ITV2",
1003 SPR_NOACCESS
, SPR_NOACCESS
,
1004 &spr_read_generic
, &spr_write_generic
,
1007 spr_register(env
, SPR_440_ITV3
, "ITV3",
1008 SPR_NOACCESS
, SPR_NOACCESS
,
1009 &spr_read_generic
, &spr_write_generic
,
1012 spr_register(env
, SPR_440_IVLIM
, "IVLIM",
1013 SPR_NOACCESS
, SPR_NOACCESS
,
1014 &spr_read_generic
, &spr_write_generic
,
1017 spr_register(env
, SPR_BOOKE_DCDBTRH
, "DCDBTRH",
1018 SPR_NOACCESS
, SPR_NOACCESS
,
1019 &spr_read_generic
, SPR_NOACCESS
,
1022 spr_register(env
, SPR_BOOKE_DCDBTRL
, "DCDBTRL",
1023 SPR_NOACCESS
, SPR_NOACCESS
,
1024 &spr_read_generic
, SPR_NOACCESS
,
1027 spr_register(env
, SPR_BOOKE_ICDBDR
, "ICDBDR",
1028 SPR_NOACCESS
, SPR_NOACCESS
,
1029 &spr_read_generic
, SPR_NOACCESS
,
1032 spr_register(env
, SPR_BOOKE_ICDBTRH
, "ICDBTRH",
1033 SPR_NOACCESS
, SPR_NOACCESS
,
1034 &spr_read_generic
, SPR_NOACCESS
,
1037 spr_register(env
, SPR_BOOKE_ICDBTRL
, "ICDBTRL",
1038 SPR_NOACCESS
, SPR_NOACCESS
,
1039 &spr_read_generic
, SPR_NOACCESS
,
1042 spr_register(env
, SPR_440_DBDR
, "DBDR",
1043 SPR_NOACCESS
, SPR_NOACCESS
,
1044 &spr_read_generic
, &spr_write_generic
,
1046 /* Processor control */
1047 spr_register(env
, SPR_4xx_CCR0
, "CCR0",
1048 SPR_NOACCESS
, SPR_NOACCESS
,
1049 &spr_read_generic
, &spr_write_generic
,
1051 spr_register(env
, SPR_440_RSTCFG
, "RSTCFG",
1052 SPR_NOACCESS
, SPR_NOACCESS
,
1053 &spr_read_generic
, SPR_NOACCESS
,
1055 /* Storage control */
1056 spr_register(env
, SPR_440_MMUCR
, "MMUCR",
1057 SPR_NOACCESS
, SPR_NOACCESS
,
1058 &spr_read_generic
, &spr_write_generic
,
1061 /* Processor identification */
1062 spr_register(env
, SPR_BOOKE_PIR
, "PIR",
1063 SPR_NOACCESS
, SPR_NOACCESS
,
1064 &spr_read_generic
, &spr_write_pir
,
1067 spr_register(env
, SPR_BOOKE_IAC3
, "IAC3",
1068 SPR_NOACCESS
, SPR_NOACCESS
,
1069 &spr_read_generic
, &spr_write_generic
,
1072 spr_register(env
, SPR_BOOKE_IAC4
, "IAC4",
1073 SPR_NOACCESS
, SPR_NOACCESS
,
1074 &spr_read_generic
, &spr_write_generic
,
1077 spr_register(env
, SPR_BOOKE_DVC1
, "DVC1",
1078 SPR_NOACCESS
, SPR_NOACCESS
,
1079 &spr_read_generic
, &spr_write_generic
,
1082 spr_register(env
, SPR_BOOKE_DVC2
, "DVC2",
1083 SPR_NOACCESS
, SPR_NOACCESS
,
1084 &spr_read_generic
, &spr_write_generic
,
1088 /* SPR shared between PowerPC 40x implementations */
1089 static void register_40x_sprs(CPUPPCState
*env
)
1092 /* not emulated, as QEMU do not emulate caches */
1093 spr_register(env
, SPR_40x_DCCR
, "DCCR",
1094 SPR_NOACCESS
, SPR_NOACCESS
,
1095 &spr_read_generic
, &spr_write_generic
,
1097 /* not emulated, as QEMU do not emulate caches */
1098 spr_register(env
, SPR_40x_ICCR
, "ICCR",
1099 SPR_NOACCESS
, SPR_NOACCESS
,
1100 &spr_read_generic
, &spr_write_generic
,
1102 /* not emulated, as QEMU do not emulate caches */
1103 spr_register(env
, SPR_BOOKE_ICDBDR
, "ICDBDR",
1104 SPR_NOACCESS
, SPR_NOACCESS
,
1105 &spr_read_generic
, SPR_NOACCESS
,
1108 spr_register(env
, SPR_40x_DEAR
, "DEAR",
1109 SPR_NOACCESS
, SPR_NOACCESS
,
1110 &spr_read_generic
, &spr_write_generic
,
1112 spr_register(env
, SPR_40x_ESR
, "ESR",
1113 SPR_NOACCESS
, SPR_NOACCESS
,
1114 &spr_read_generic
, &spr_write_generic
,
1116 spr_register(env
, SPR_40x_EVPR
, "EVPR",
1117 SPR_NOACCESS
, SPR_NOACCESS
,
1118 &spr_read_generic
, &spr_write_excp_prefix
,
1120 spr_register(env
, SPR_40x_SRR2
, "SRR2",
1121 &spr_read_generic
, &spr_write_generic
,
1122 &spr_read_generic
, &spr_write_generic
,
1124 spr_register(env
, SPR_40x_SRR3
, "SRR3",
1125 &spr_read_generic
, &spr_write_generic
,
1126 &spr_read_generic
, &spr_write_generic
,
1129 spr_register(env
, SPR_40x_PIT
, "PIT",
1130 SPR_NOACCESS
, SPR_NOACCESS
,
1131 &spr_read_40x_pit
, &spr_write_40x_pit
,
1133 spr_register(env
, SPR_40x_TCR
, "TCR",
1134 SPR_NOACCESS
, SPR_NOACCESS
,
1135 &spr_read_generic
, &spr_write_40x_tcr
,
1137 spr_register(env
, SPR_40x_TSR
, "TSR",
1138 SPR_NOACCESS
, SPR_NOACCESS
,
1139 &spr_read_generic
, &spr_write_40x_tsr
,
1143 /* SPR specific to PowerPC 405 implementation */
1144 static void register_405_sprs(CPUPPCState
*env
)
1147 spr_register(env
, SPR_40x_PID
, "PID",
1148 SPR_NOACCESS
, SPR_NOACCESS
,
1149 &spr_read_generic
, &spr_write_40x_pid
,
1151 spr_register(env
, SPR_4xx_CCR0
, "CCR0",
1152 SPR_NOACCESS
, SPR_NOACCESS
,
1153 &spr_read_generic
, &spr_write_generic
,
1155 /* Debug interface */
1156 spr_register(env
, SPR_40x_DBCR0
, "DBCR0",
1157 SPR_NOACCESS
, SPR_NOACCESS
,
1158 &spr_read_generic
, &spr_write_40x_dbcr0
,
1161 spr_register(env
, SPR_405_DBCR1
, "DBCR1",
1162 SPR_NOACCESS
, SPR_NOACCESS
,
1163 &spr_read_generic
, &spr_write_generic
,
1166 spr_register(env
, SPR_40x_DBSR
, "DBSR",
1167 SPR_NOACCESS
, SPR_NOACCESS
,
1168 &spr_read_generic
, &spr_write_clear
,
1169 /* Last reset was system reset */
1172 spr_register(env
, SPR_40x_DAC1
, "DAC1",
1173 SPR_NOACCESS
, SPR_NOACCESS
,
1174 &spr_read_generic
, &spr_write_generic
,
1176 spr_register(env
, SPR_40x_DAC2
, "DAC2",
1177 SPR_NOACCESS
, SPR_NOACCESS
,
1178 &spr_read_generic
, &spr_write_generic
,
1181 spr_register(env
, SPR_405_DVC1
, "DVC1",
1182 SPR_NOACCESS
, SPR_NOACCESS
,
1183 &spr_read_generic
, &spr_write_generic
,
1186 spr_register(env
, SPR_405_DVC2
, "DVC2",
1187 SPR_NOACCESS
, SPR_NOACCESS
,
1188 &spr_read_generic
, &spr_write_generic
,
1191 spr_register(env
, SPR_40x_IAC1
, "IAC1",
1192 SPR_NOACCESS
, SPR_NOACCESS
,
1193 &spr_read_generic
, &spr_write_generic
,
1195 spr_register(env
, SPR_40x_IAC2
, "IAC2",
1196 SPR_NOACCESS
, SPR_NOACCESS
,
1197 &spr_read_generic
, &spr_write_generic
,
1200 spr_register(env
, SPR_405_IAC3
, "IAC3",
1201 SPR_NOACCESS
, SPR_NOACCESS
,
1202 &spr_read_generic
, &spr_write_generic
,
1205 spr_register(env
, SPR_405_IAC4
, "IAC4",
1206 SPR_NOACCESS
, SPR_NOACCESS
,
1207 &spr_read_generic
, &spr_write_generic
,
1209 /* Storage control */
1210 spr_register(env
, SPR_405_SLER
, "SLER",
1211 SPR_NOACCESS
, SPR_NOACCESS
,
1212 &spr_read_generic
, &spr_write_40x_sler
,
1214 spr_register(env
, SPR_40x_ZPR
, "ZPR",
1215 SPR_NOACCESS
, SPR_NOACCESS
,
1216 &spr_read_generic
, &spr_write_generic
,
1219 spr_register(env
, SPR_405_SU0R
, "SU0R",
1220 SPR_NOACCESS
, SPR_NOACCESS
,
1221 &spr_read_generic
, &spr_write_generic
,
1224 spr_register(env
, SPR_USPRG0
, "USPRG0",
1225 &spr_read_ureg
, SPR_NOACCESS
,
1226 &spr_read_ureg
, SPR_NOACCESS
,
1228 spr_register(env
, SPR_SPRG4
, "SPRG4",
1229 SPR_NOACCESS
, SPR_NOACCESS
,
1230 &spr_read_generic
, &spr_write_generic
,
1232 spr_register(env
, SPR_SPRG5
, "SPRG5",
1233 SPR_NOACCESS
, SPR_NOACCESS
,
1234 spr_read_generic
, &spr_write_generic
,
1236 spr_register(env
, SPR_SPRG6
, "SPRG6",
1237 SPR_NOACCESS
, SPR_NOACCESS
,
1238 spr_read_generic
, &spr_write_generic
,
1240 spr_register(env
, SPR_SPRG7
, "SPRG7",
1241 SPR_NOACCESS
, SPR_NOACCESS
,
1242 spr_read_generic
, &spr_write_generic
,
1245 /* Bus access control */
1246 /* not emulated, as QEMU never does speculative access */
1247 spr_register(env
, SPR_40x_SGR
, "SGR",
1248 SPR_NOACCESS
, SPR_NOACCESS
,
1249 &spr_read_generic
, &spr_write_generic
,
1251 /* not emulated, as QEMU do not emulate caches */
1252 spr_register(env
, SPR_40x_DCWR
, "DCWR",
1253 SPR_NOACCESS
, SPR_NOACCESS
,
1254 &spr_read_generic
, &spr_write_generic
,
1259 static void register_5xx_8xx_sprs(CPUPPCState
*env
)
1261 /* Exception processing */
1262 spr_register_kvm(env
, SPR_DSISR
, "DSISR",
1263 SPR_NOACCESS
, SPR_NOACCESS
,
1264 &spr_read_generic
, &spr_write_generic
,
1265 KVM_REG_PPC_DSISR
, 0x00000000);
1266 spr_register_kvm(env
, SPR_DAR
, "DAR",
1267 SPR_NOACCESS
, SPR_NOACCESS
,
1268 &spr_read_generic
, &spr_write_generic
,
1269 KVM_REG_PPC_DAR
, 0x00000000);
1271 spr_register(env
, SPR_DECR
, "DECR",
1272 SPR_NOACCESS
, SPR_NOACCESS
,
1273 &spr_read_decr
, &spr_write_decr
,
1276 spr_register(env
, SPR_MPC_EIE
, "EIE",
1277 SPR_NOACCESS
, SPR_NOACCESS
,
1278 &spr_read_generic
, &spr_write_generic
,
1281 spr_register(env
, SPR_MPC_EID
, "EID",
1282 SPR_NOACCESS
, SPR_NOACCESS
,
1283 &spr_read_generic
, &spr_write_generic
,
1286 spr_register(env
, SPR_MPC_NRI
, "NRI",
1287 SPR_NOACCESS
, SPR_NOACCESS
,
1288 &spr_read_generic
, &spr_write_generic
,
1291 spr_register(env
, SPR_MPC_CMPA
, "CMPA",
1292 SPR_NOACCESS
, SPR_NOACCESS
,
1293 &spr_read_generic
, &spr_write_generic
,
1296 spr_register(env
, SPR_MPC_CMPB
, "CMPB",
1297 SPR_NOACCESS
, SPR_NOACCESS
,
1298 &spr_read_generic
, &spr_write_generic
,
1301 spr_register(env
, SPR_MPC_CMPC
, "CMPC",
1302 SPR_NOACCESS
, SPR_NOACCESS
,
1303 &spr_read_generic
, &spr_write_generic
,
1306 spr_register(env
, SPR_MPC_CMPD
, "CMPD",
1307 SPR_NOACCESS
, SPR_NOACCESS
,
1308 &spr_read_generic
, &spr_write_generic
,
1311 spr_register(env
, SPR_MPC_ECR
, "ECR",
1312 SPR_NOACCESS
, SPR_NOACCESS
,
1313 &spr_read_generic
, &spr_write_generic
,
1316 spr_register(env
, SPR_MPC_DER
, "DER",
1317 SPR_NOACCESS
, SPR_NOACCESS
,
1318 &spr_read_generic
, &spr_write_generic
,
1321 spr_register(env
, SPR_MPC_COUNTA
, "COUNTA",
1322 SPR_NOACCESS
, SPR_NOACCESS
,
1323 &spr_read_generic
, &spr_write_generic
,
1326 spr_register(env
, SPR_MPC_COUNTB
, "COUNTB",
1327 SPR_NOACCESS
, SPR_NOACCESS
,
1328 &spr_read_generic
, &spr_write_generic
,
1331 spr_register(env
, SPR_MPC_CMPE
, "CMPE",
1332 SPR_NOACCESS
, SPR_NOACCESS
,
1333 &spr_read_generic
, &spr_write_generic
,
1336 spr_register(env
, SPR_MPC_CMPF
, "CMPF",
1337 SPR_NOACCESS
, SPR_NOACCESS
,
1338 &spr_read_generic
, &spr_write_generic
,
1341 spr_register(env
, SPR_MPC_CMPG
, "CMPG",
1342 SPR_NOACCESS
, SPR_NOACCESS
,
1343 &spr_read_generic
, &spr_write_generic
,
1346 spr_register(env
, SPR_MPC_CMPH
, "CMPH",
1347 SPR_NOACCESS
, SPR_NOACCESS
,
1348 &spr_read_generic
, &spr_write_generic
,
1351 spr_register(env
, SPR_MPC_LCTRL1
, "LCTRL1",
1352 SPR_NOACCESS
, SPR_NOACCESS
,
1353 &spr_read_generic
, &spr_write_generic
,
1356 spr_register(env
, SPR_MPC_LCTRL2
, "LCTRL2",
1357 SPR_NOACCESS
, SPR_NOACCESS
,
1358 &spr_read_generic
, &spr_write_generic
,
1361 spr_register(env
, SPR_MPC_BAR
, "BAR",
1362 SPR_NOACCESS
, SPR_NOACCESS
,
1363 &spr_read_generic
, &spr_write_generic
,
1366 spr_register(env
, SPR_MPC_DPDR
, "DPDR",
1367 SPR_NOACCESS
, SPR_NOACCESS
,
1368 &spr_read_generic
, &spr_write_generic
,
1371 spr_register(env
, SPR_MPC_IMMR
, "IMMR",
1372 SPR_NOACCESS
, SPR_NOACCESS
,
1373 &spr_read_generic
, &spr_write_generic
,
1377 static void register_5xx_sprs(CPUPPCState
*env
)
1379 spr_register(env
, SPR_RCPU_MI_GRA
, "MI_GRA",
1380 SPR_NOACCESS
, SPR_NOACCESS
,
1381 &spr_read_generic
, &spr_write_generic
,
1384 spr_register(env
, SPR_RCPU_L2U_GRA
, "L2U_GRA",
1385 SPR_NOACCESS
, SPR_NOACCESS
,
1386 &spr_read_generic
, &spr_write_generic
,
1389 spr_register(env
, SPR_RPCU_BBCMCR
, "L2U_BBCMCR",
1390 SPR_NOACCESS
, SPR_NOACCESS
,
1391 &spr_read_generic
, &spr_write_generic
,
1394 spr_register(env
, SPR_RCPU_L2U_MCR
, "L2U_MCR",
1395 SPR_NOACCESS
, SPR_NOACCESS
,
1396 &spr_read_generic
, &spr_write_generic
,
1399 spr_register(env
, SPR_RCPU_MI_RBA0
, "MI_RBA0",
1400 SPR_NOACCESS
, SPR_NOACCESS
,
1401 &spr_read_generic
, &spr_write_generic
,
1404 spr_register(env
, SPR_RCPU_MI_RBA1
, "MI_RBA1",
1405 SPR_NOACCESS
, SPR_NOACCESS
,
1406 &spr_read_generic
, &spr_write_generic
,
1409 spr_register(env
, SPR_RCPU_MI_RBA2
, "MI_RBA2",
1410 SPR_NOACCESS
, SPR_NOACCESS
,
1411 &spr_read_generic
, &spr_write_generic
,
1414 spr_register(env
, SPR_RCPU_MI_RBA3
, "MI_RBA3",
1415 SPR_NOACCESS
, SPR_NOACCESS
,
1416 &spr_read_generic
, &spr_write_generic
,
1419 spr_register(env
, SPR_RCPU_L2U_RBA0
, "L2U_RBA0",
1420 SPR_NOACCESS
, SPR_NOACCESS
,
1421 &spr_read_generic
, &spr_write_generic
,
1424 spr_register(env
, SPR_RCPU_L2U_RBA1
, "L2U_RBA1",
1425 SPR_NOACCESS
, SPR_NOACCESS
,
1426 &spr_read_generic
, &spr_write_generic
,
1429 spr_register(env
, SPR_RCPU_L2U_RBA2
, "L2U_RBA2",
1430 SPR_NOACCESS
, SPR_NOACCESS
,
1431 &spr_read_generic
, &spr_write_generic
,
1434 spr_register(env
, SPR_RCPU_L2U_RBA3
, "L2U_RBA3",
1435 SPR_NOACCESS
, SPR_NOACCESS
,
1436 &spr_read_generic
, &spr_write_generic
,
1439 spr_register(env
, SPR_RCPU_MI_RA0
, "MI_RA0",
1440 SPR_NOACCESS
, SPR_NOACCESS
,
1441 &spr_read_generic
, &spr_write_generic
,
1444 spr_register(env
, SPR_RCPU_MI_RA1
, "MI_RA1",
1445 SPR_NOACCESS
, SPR_NOACCESS
,
1446 &spr_read_generic
, &spr_write_generic
,
1449 spr_register(env
, SPR_RCPU_MI_RA2
, "MI_RA2",
1450 SPR_NOACCESS
, SPR_NOACCESS
,
1451 &spr_read_generic
, &spr_write_generic
,
1454 spr_register(env
, SPR_RCPU_MI_RA3
, "MI_RA3",
1455 SPR_NOACCESS
, SPR_NOACCESS
,
1456 &spr_read_generic
, &spr_write_generic
,
1459 spr_register(env
, SPR_RCPU_L2U_RA0
, "L2U_RA0",
1460 SPR_NOACCESS
, SPR_NOACCESS
,
1461 &spr_read_generic
, &spr_write_generic
,
1464 spr_register(env
, SPR_RCPU_L2U_RA1
, "L2U_RA1",
1465 SPR_NOACCESS
, SPR_NOACCESS
,
1466 &spr_read_generic
, &spr_write_generic
,
1469 spr_register(env
, SPR_RCPU_L2U_RA2
, "L2U_RA2",
1470 SPR_NOACCESS
, SPR_NOACCESS
,
1471 &spr_read_generic
, &spr_write_generic
,
1474 spr_register(env
, SPR_RCPU_L2U_RA3
, "L2U_RA3",
1475 SPR_NOACCESS
, SPR_NOACCESS
,
1476 &spr_read_generic
, &spr_write_generic
,
1479 spr_register(env
, SPR_RCPU_FPECR
, "FPECR",
1480 SPR_NOACCESS
, SPR_NOACCESS
,
1481 &spr_read_generic
, &spr_write_generic
,
1485 static void register_8xx_sprs(CPUPPCState
*env
)
1488 spr_register(env
, SPR_MPC_IC_CST
, "IC_CST",
1489 SPR_NOACCESS
, SPR_NOACCESS
,
1490 &spr_read_generic
, &spr_write_generic
,
1493 spr_register(env
, SPR_MPC_IC_ADR
, "IC_ADR",
1494 SPR_NOACCESS
, SPR_NOACCESS
,
1495 &spr_read_generic
, &spr_write_generic
,
1498 spr_register(env
, SPR_MPC_IC_DAT
, "IC_DAT",
1499 SPR_NOACCESS
, SPR_NOACCESS
,
1500 &spr_read_generic
, &spr_write_generic
,
1503 spr_register(env
, SPR_MPC_DC_CST
, "DC_CST",
1504 SPR_NOACCESS
, SPR_NOACCESS
,
1505 &spr_read_generic
, &spr_write_generic
,
1508 spr_register(env
, SPR_MPC_DC_ADR
, "DC_ADR",
1509 SPR_NOACCESS
, SPR_NOACCESS
,
1510 &spr_read_generic
, &spr_write_generic
,
1513 spr_register(env
, SPR_MPC_DC_DAT
, "DC_DAT",
1514 SPR_NOACCESS
, SPR_NOACCESS
,
1515 &spr_read_generic
, &spr_write_generic
,
1518 spr_register(env
, SPR_MPC_MI_CTR
, "MI_CTR",
1519 SPR_NOACCESS
, SPR_NOACCESS
,
1520 &spr_read_generic
, &spr_write_generic
,
1523 spr_register(env
, SPR_MPC_MI_AP
, "MI_AP",
1524 SPR_NOACCESS
, SPR_NOACCESS
,
1525 &spr_read_generic
, &spr_write_generic
,
1528 spr_register(env
, SPR_MPC_MI_EPN
, "MI_EPN",
1529 SPR_NOACCESS
, SPR_NOACCESS
,
1530 &spr_read_generic
, &spr_write_generic
,
1533 spr_register(env
, SPR_MPC_MI_TWC
, "MI_TWC",
1534 SPR_NOACCESS
, SPR_NOACCESS
,
1535 &spr_read_generic
, &spr_write_generic
,
1538 spr_register(env
, SPR_MPC_MI_RPN
, "MI_RPN",
1539 SPR_NOACCESS
, SPR_NOACCESS
,
1540 &spr_read_generic
, &spr_write_generic
,
1543 spr_register(env
, SPR_MPC_MI_DBCAM
, "MI_DBCAM",
1544 SPR_NOACCESS
, SPR_NOACCESS
,
1545 &spr_read_generic
, &spr_write_generic
,
1548 spr_register(env
, SPR_MPC_MI_DBRAM0
, "MI_DBRAM0",
1549 SPR_NOACCESS
, SPR_NOACCESS
,
1550 &spr_read_generic
, &spr_write_generic
,
1553 spr_register(env
, SPR_MPC_MI_DBRAM1
, "MI_DBRAM1",
1554 SPR_NOACCESS
, SPR_NOACCESS
,
1555 &spr_read_generic
, &spr_write_generic
,
1558 spr_register(env
, SPR_MPC_MD_CTR
, "MD_CTR",
1559 SPR_NOACCESS
, SPR_NOACCESS
,
1560 &spr_read_generic
, &spr_write_generic
,
1563 spr_register(env
, SPR_MPC_MD_CASID
, "MD_CASID",
1564 SPR_NOACCESS
, SPR_NOACCESS
,
1565 &spr_read_generic
, &spr_write_generic
,
1568 spr_register(env
, SPR_MPC_MD_AP
, "MD_AP",
1569 SPR_NOACCESS
, SPR_NOACCESS
,
1570 &spr_read_generic
, &spr_write_generic
,
1573 spr_register(env
, SPR_MPC_MD_EPN
, "MD_EPN",
1574 SPR_NOACCESS
, SPR_NOACCESS
,
1575 &spr_read_generic
, &spr_write_generic
,
1578 spr_register(env
, SPR_MPC_MD_TWB
, "MD_TWB",
1579 SPR_NOACCESS
, SPR_NOACCESS
,
1580 &spr_read_generic
, &spr_write_generic
,
1583 spr_register(env
, SPR_MPC_MD_TWC
, "MD_TWC",
1584 SPR_NOACCESS
, SPR_NOACCESS
,
1585 &spr_read_generic
, &spr_write_generic
,
1588 spr_register(env
, SPR_MPC_MD_RPN
, "MD_RPN",
1589 SPR_NOACCESS
, SPR_NOACCESS
,
1590 &spr_read_generic
, &spr_write_generic
,
1593 spr_register(env
, SPR_MPC_MD_TW
, "MD_TW",
1594 SPR_NOACCESS
, SPR_NOACCESS
,
1595 &spr_read_generic
, &spr_write_generic
,
1598 spr_register(env
, SPR_MPC_MD_DBCAM
, "MD_DBCAM",
1599 SPR_NOACCESS
, SPR_NOACCESS
,
1600 &spr_read_generic
, &spr_write_generic
,
1603 spr_register(env
, SPR_MPC_MD_DBRAM0
, "MD_DBRAM0",
1604 SPR_NOACCESS
, SPR_NOACCESS
,
1605 &spr_read_generic
, &spr_write_generic
,
1608 spr_register(env
, SPR_MPC_MD_DBRAM1
, "MD_DBRAM1",
1609 SPR_NOACCESS
, SPR_NOACCESS
,
1610 &spr_read_generic
, &spr_write_generic
,
1615 * AMR => SPR 29 (Power 2.04)
1616 * CTRL => SPR 136 (Power 2.04)
1617 * CTRL => SPR 152 (Power 2.04)
1618 * SCOMC => SPR 276 (64 bits ?)
1619 * SCOMD => SPR 277 (64 bits ?)
1620 * TBU40 => SPR 286 (Power 2.04 hypv)
1621 * HSPRG0 => SPR 304 (Power 2.04 hypv)
1622 * HSPRG1 => SPR 305 (Power 2.04 hypv)
1623 * HDSISR => SPR 306 (Power 2.04 hypv)
1624 * HDAR => SPR 307 (Power 2.04 hypv)
1625 * PURR => SPR 309 (Power 2.04 hypv)
1626 * HDEC => SPR 310 (Power 2.04 hypv)
1627 * HIOR => SPR 311 (hypv)
1628 * RMOR => SPR 312 (970)
1629 * HRMOR => SPR 313 (Power 2.04 hypv)
1630 * HSRR0 => SPR 314 (Power 2.04 hypv)
1631 * HSRR1 => SPR 315 (Power 2.04 hypv)
1632 * LPIDR => SPR 317 (970)
1633 * HEIR => SPR 339 (Power 2.05 hypv) (64-bit reg from 3.1)
1634 * EPR => SPR 702 (Power 2.04 emb)
1635 * perf => 768-783 (Power 2.04)
1636 * perf => 784-799 (Power 2.04)
1637 * PPR => SPR 896 (Power 2.04)
1638 * DABRX => 1015 (Power 2.04 hypv)
1639 * FPECR => SPR 1022 (?)
1640 * ... and more (thermal management, performance counters, ...)
1643 /*****************************************************************************/
1644 /* Exception vectors models */
1645 static void init_excp_4xx_softmmu(CPUPPCState
*env
)
1647 #if !defined(CONFIG_USER_ONLY)
1648 env
->excp_vectors
[POWERPC_EXCP_CRITICAL
] = 0x00000100;
1649 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
1650 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000300;
1651 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000400;
1652 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
1653 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
1654 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
1655 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
1656 env
->excp_vectors
[POWERPC_EXCP_PIT
] = 0x00001000;
1657 env
->excp_vectors
[POWERPC_EXCP_FIT
] = 0x00001010;
1658 env
->excp_vectors
[POWERPC_EXCP_WDT
] = 0x00001020;
1659 env
->excp_vectors
[POWERPC_EXCP_DTLB
] = 0x00001100;
1660 env
->excp_vectors
[POWERPC_EXCP_ITLB
] = 0x00001200;
1661 env
->excp_vectors
[POWERPC_EXCP_DEBUG
] = 0x00002000;
1662 env
->ivor_mask
= 0x0000FFF0UL
;
1663 env
->ivpr_mask
= 0xFFFF0000UL
;
1664 /* Hardware reset vector */
1665 env
->hreset_vector
= 0xFFFFFFFCUL
;
1669 static void init_excp_MPC5xx(CPUPPCState
*env
)
1671 #if !defined(CONFIG_USER_ONLY)
1672 env
->excp_vectors
[POWERPC_EXCP_RESET
] = 0x00000100;
1673 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
1674 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
1675 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
1676 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
1677 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000800;
1678 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000900;
1679 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
1680 env
->excp_vectors
[POWERPC_EXCP_TRACE
] = 0x00000D00;
1681 env
->excp_vectors
[POWERPC_EXCP_FPA
] = 0x00000E00;
1682 env
->excp_vectors
[POWERPC_EXCP_EMUL
] = 0x00001000;
1683 env
->excp_vectors
[POWERPC_EXCP_DABR
] = 0x00001C00;
1684 env
->excp_vectors
[POWERPC_EXCP_IABR
] = 0x00001C00;
1685 env
->excp_vectors
[POWERPC_EXCP_MEXTBR
] = 0x00001E00;
1686 env
->excp_vectors
[POWERPC_EXCP_NMEXTBR
] = 0x00001F00;
1687 env
->ivor_mask
= 0x0000FFF0UL
;
1688 env
->ivpr_mask
= 0xFFFF0000UL
;
1689 /* Hardware reset vector */
1690 env
->hreset_vector
= 0x00000100UL
;
1694 static void init_excp_MPC8xx(CPUPPCState
*env
)
1696 #if !defined(CONFIG_USER_ONLY)
1697 env
->excp_vectors
[POWERPC_EXCP_RESET
] = 0x00000100;
1698 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
1699 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000300;
1700 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000400;
1701 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
1702 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
1703 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
1704 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000800;
1705 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000900;
1706 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
1707 env
->excp_vectors
[POWERPC_EXCP_TRACE
] = 0x00000D00;
1708 env
->excp_vectors
[POWERPC_EXCP_FPA
] = 0x00000E00;
1709 env
->excp_vectors
[POWERPC_EXCP_EMUL
] = 0x00001000;
1710 env
->excp_vectors
[POWERPC_EXCP_ITLB
] = 0x00001100;
1711 env
->excp_vectors
[POWERPC_EXCP_DTLB
] = 0x00001200;
1712 env
->excp_vectors
[POWERPC_EXCP_ITLBE
] = 0x00001300;
1713 env
->excp_vectors
[POWERPC_EXCP_DTLBE
] = 0x00001400;
1714 env
->excp_vectors
[POWERPC_EXCP_DABR
] = 0x00001C00;
1715 env
->excp_vectors
[POWERPC_EXCP_IABR
] = 0x00001C00;
1716 env
->excp_vectors
[POWERPC_EXCP_MEXTBR
] = 0x00001E00;
1717 env
->excp_vectors
[POWERPC_EXCP_NMEXTBR
] = 0x00001F00;
1718 env
->ivor_mask
= 0x0000FFF0UL
;
1719 env
->ivpr_mask
= 0xFFFF0000UL
;
1720 /* Hardware reset vector */
1721 env
->hreset_vector
= 0x00000100UL
;
1725 static void init_excp_G2(CPUPPCState
*env
)
1727 #if !defined(CONFIG_USER_ONLY)
1728 env
->excp_vectors
[POWERPC_EXCP_RESET
] = 0x00000100;
1729 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
1730 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000300;
1731 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000400;
1732 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
1733 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
1734 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
1735 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000800;
1736 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000900;
1737 env
->excp_vectors
[POWERPC_EXCP_CRITICAL
] = 0x00000A00;
1738 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
1739 env
->excp_vectors
[POWERPC_EXCP_TRACE
] = 0x00000D00;
1740 env
->excp_vectors
[POWERPC_EXCP_IFTLB
] = 0x00001000;
1741 env
->excp_vectors
[POWERPC_EXCP_DLTLB
] = 0x00001100;
1742 env
->excp_vectors
[POWERPC_EXCP_DSTLB
] = 0x00001200;
1743 env
->excp_vectors
[POWERPC_EXCP_IABR
] = 0x00001300;
1744 env
->excp_vectors
[POWERPC_EXCP_SMI
] = 0x00001400;
1745 /* Hardware reset vector */
1746 env
->hreset_vector
= 0x00000100UL
;
1750 static void init_excp_e200(CPUPPCState
*env
, target_ulong ivpr_mask
)
1752 #if !defined(CONFIG_USER_ONLY)
1753 env
->excp_vectors
[POWERPC_EXCP_RESET
] = 0x00000FFC;
1754 env
->excp_vectors
[POWERPC_EXCP_CRITICAL
] = 0x00000000;
1755 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000000;
1756 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000000;
1757 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000000;
1758 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000000;
1759 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000000;
1760 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000000;
1761 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000000;
1762 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000000;
1763 env
->excp_vectors
[POWERPC_EXCP_APU
] = 0x00000000;
1764 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000000;
1765 env
->excp_vectors
[POWERPC_EXCP_FIT
] = 0x00000000;
1766 env
->excp_vectors
[POWERPC_EXCP_WDT
] = 0x00000000;
1767 env
->excp_vectors
[POWERPC_EXCP_DTLB
] = 0x00000000;
1768 env
->excp_vectors
[POWERPC_EXCP_ITLB
] = 0x00000000;
1769 env
->excp_vectors
[POWERPC_EXCP_DEBUG
] = 0x00000000;
1771 * These two are the same IVOR as POWERPC_EXCP_VPU and
1772 * POWERPC_EXCP_VPUA. We deal with that when dispatching at
1775 env
->excp_vectors
[POWERPC_EXCP_SPEU
] = 0x00000000;
1776 env
->excp_vectors
[POWERPC_EXCP_EFPDI
] = 0x00000000;
1778 env
->excp_vectors
[POWERPC_EXCP_EFPRI
] = 0x00000000;
1779 env
->ivor_mask
= 0x0000FFF7UL
;
1780 env
->ivpr_mask
= ivpr_mask
;
1781 /* Hardware reset vector */
1782 env
->hreset_vector
= 0xFFFFFFFCUL
;
1786 static void init_excp_BookE(CPUPPCState
*env
)
1788 #if !defined(CONFIG_USER_ONLY)
1789 env
->excp_vectors
[POWERPC_EXCP_CRITICAL
] = 0x00000000;
1790 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000000;
1791 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000000;
1792 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000000;
1793 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000000;
1794 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000000;
1795 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000000;
1796 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000000;
1797 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000000;
1798 env
->excp_vectors
[POWERPC_EXCP_APU
] = 0x00000000;
1799 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000000;
1800 env
->excp_vectors
[POWERPC_EXCP_FIT
] = 0x00000000;
1801 env
->excp_vectors
[POWERPC_EXCP_WDT
] = 0x00000000;
1802 env
->excp_vectors
[POWERPC_EXCP_DTLB
] = 0x00000000;
1803 env
->excp_vectors
[POWERPC_EXCP_ITLB
] = 0x00000000;
1804 env
->excp_vectors
[POWERPC_EXCP_DEBUG
] = 0x00000000;
1805 env
->ivor_mask
= 0x0000FFF0UL
;
1806 env
->ivpr_mask
= 0xFFFF0000UL
;
1807 /* Hardware reset vector */
1808 env
->hreset_vector
= 0xFFFFFFFCUL
;
1812 static void init_excp_603(CPUPPCState
*env
)
1814 #if !defined(CONFIG_USER_ONLY)
1815 env
->excp_vectors
[POWERPC_EXCP_RESET
] = 0x00000100;
1816 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
1817 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000300;
1818 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000400;
1819 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
1820 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
1821 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
1822 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000800;
1823 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000900;
1824 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
1825 env
->excp_vectors
[POWERPC_EXCP_TRACE
] = 0x00000D00;
1826 env
->excp_vectors
[POWERPC_EXCP_IFTLB
] = 0x00001000;
1827 env
->excp_vectors
[POWERPC_EXCP_DLTLB
] = 0x00001100;
1828 env
->excp_vectors
[POWERPC_EXCP_DSTLB
] = 0x00001200;
1829 env
->excp_vectors
[POWERPC_EXCP_IABR
] = 0x00001300;
1830 env
->excp_vectors
[POWERPC_EXCP_SMI
] = 0x00001400;
1831 /* Hardware reset vector */
1832 env
->hreset_vector
= 0x00000100UL
;
1836 static void init_excp_604(CPUPPCState
*env
)
1838 #if !defined(CONFIG_USER_ONLY)
1839 env
->excp_vectors
[POWERPC_EXCP_RESET
] = 0x00000100;
1840 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
1841 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000300;
1842 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000400;
1843 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
1844 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
1845 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
1846 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000800;
1847 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000900;
1848 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
1849 env
->excp_vectors
[POWERPC_EXCP_TRACE
] = 0x00000D00;
1850 env
->excp_vectors
[POWERPC_EXCP_PERFM
] = 0x00000F00;
1851 env
->excp_vectors
[POWERPC_EXCP_IABR
] = 0x00001300;
1852 env
->excp_vectors
[POWERPC_EXCP_SMI
] = 0x00001400;
1853 /* Hardware reset vector */
1854 env
->hreset_vector
= 0x00000100UL
;
1858 static void init_excp_7x0(CPUPPCState
*env
)
1860 #if !defined(CONFIG_USER_ONLY)
1861 env
->excp_vectors
[POWERPC_EXCP_RESET
] = 0x00000100;
1862 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
1863 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000300;
1864 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000400;
1865 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
1866 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
1867 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
1868 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000800;
1869 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000900;
1870 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
1871 env
->excp_vectors
[POWERPC_EXCP_TRACE
] = 0x00000D00;
1872 env
->excp_vectors
[POWERPC_EXCP_PERFM
] = 0x00000F00;
1873 env
->excp_vectors
[POWERPC_EXCP_IABR
] = 0x00001300;
1874 env
->excp_vectors
[POWERPC_EXCP_SMI
] = 0x00001400;
1875 env
->excp_vectors
[POWERPC_EXCP_THERM
] = 0x00001700;
1876 /* Hardware reset vector */
1877 env
->hreset_vector
= 0x00000100UL
;
1881 static void init_excp_750cl(CPUPPCState
*env
)
1883 #if !defined(CONFIG_USER_ONLY)
1884 env
->excp_vectors
[POWERPC_EXCP_RESET
] = 0x00000100;
1885 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
1886 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000300;
1887 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000400;
1888 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
1889 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
1890 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
1891 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000800;
1892 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000900;
1893 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
1894 env
->excp_vectors
[POWERPC_EXCP_TRACE
] = 0x00000D00;
1895 env
->excp_vectors
[POWERPC_EXCP_PERFM
] = 0x00000F00;
1896 env
->excp_vectors
[POWERPC_EXCP_IABR
] = 0x00001300;
1897 env
->excp_vectors
[POWERPC_EXCP_SMI
] = 0x00001400;
1898 /* Hardware reset vector */
1899 env
->hreset_vector
= 0x00000100UL
;
1903 static void init_excp_750cx(CPUPPCState
*env
)
1905 #if !defined(CONFIG_USER_ONLY)
1906 env
->excp_vectors
[POWERPC_EXCP_RESET
] = 0x00000100;
1907 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
1908 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000300;
1909 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000400;
1910 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
1911 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
1912 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
1913 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000800;
1914 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000900;
1915 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
1916 env
->excp_vectors
[POWERPC_EXCP_TRACE
] = 0x00000D00;
1917 env
->excp_vectors
[POWERPC_EXCP_PERFM
] = 0x00000F00;
1918 env
->excp_vectors
[POWERPC_EXCP_IABR
] = 0x00001300;
1919 env
->excp_vectors
[POWERPC_EXCP_THERM
] = 0x00001700;
1920 /* Hardware reset vector */
1921 env
->hreset_vector
= 0x00000100UL
;
1925 /* XXX: Check if this is correct */
1926 static void init_excp_7x5(CPUPPCState
*env
)
1928 #if !defined(CONFIG_USER_ONLY)
1929 env
->excp_vectors
[POWERPC_EXCP_RESET
] = 0x00000100;
1930 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
1931 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000300;
1932 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000400;
1933 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
1934 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
1935 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
1936 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000800;
1937 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000900;
1938 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
1939 env
->excp_vectors
[POWERPC_EXCP_TRACE
] = 0x00000D00;
1940 env
->excp_vectors
[POWERPC_EXCP_PERFM
] = 0x00000F00;
1941 env
->excp_vectors
[POWERPC_EXCP_IFTLB
] = 0x00001000;
1942 env
->excp_vectors
[POWERPC_EXCP_DLTLB
] = 0x00001100;
1943 env
->excp_vectors
[POWERPC_EXCP_DSTLB
] = 0x00001200;
1944 env
->excp_vectors
[POWERPC_EXCP_IABR
] = 0x00001300;
1945 env
->excp_vectors
[POWERPC_EXCP_SMI
] = 0x00001400;
1946 env
->excp_vectors
[POWERPC_EXCP_THERM
] = 0x00001700;
1947 /* Hardware reset vector */
1948 env
->hreset_vector
= 0x00000100UL
;
1952 static void init_excp_7400(CPUPPCState
*env
)
1954 #if !defined(CONFIG_USER_ONLY)
1955 env
->excp_vectors
[POWERPC_EXCP_RESET
] = 0x00000100;
1956 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
1957 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000300;
1958 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000400;
1959 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
1960 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
1961 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
1962 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000800;
1963 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000900;
1964 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
1965 env
->excp_vectors
[POWERPC_EXCP_TRACE
] = 0x00000D00;
1966 env
->excp_vectors
[POWERPC_EXCP_PERFM
] = 0x00000F00;
1967 env
->excp_vectors
[POWERPC_EXCP_VPU
] = 0x00000F20;
1968 env
->excp_vectors
[POWERPC_EXCP_IABR
] = 0x00001300;
1969 env
->excp_vectors
[POWERPC_EXCP_SMI
] = 0x00001400;
1970 env
->excp_vectors
[POWERPC_EXCP_VPUA
] = 0x00001600;
1971 env
->excp_vectors
[POWERPC_EXCP_THERM
] = 0x00001700;
1972 /* Hardware reset vector */
1973 env
->hreset_vector
= 0x00000100UL
;
1977 static void init_excp_7450(CPUPPCState
*env
)
1979 #if !defined(CONFIG_USER_ONLY)
1980 env
->excp_vectors
[POWERPC_EXCP_RESET
] = 0x00000100;
1981 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
1982 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000300;
1983 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000400;
1984 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
1985 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
1986 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
1987 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000800;
1988 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000900;
1989 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
1990 env
->excp_vectors
[POWERPC_EXCP_TRACE
] = 0x00000D00;
1991 env
->excp_vectors
[POWERPC_EXCP_PERFM
] = 0x00000F00;
1992 env
->excp_vectors
[POWERPC_EXCP_VPU
] = 0x00000F20;
1993 env
->excp_vectors
[POWERPC_EXCP_IABR
] = 0x00001300;
1994 env
->excp_vectors
[POWERPC_EXCP_SMI
] = 0x00001400;
1995 env
->excp_vectors
[POWERPC_EXCP_VPUA
] = 0x00001600;
1996 /* Hardware reset vector */
1997 env
->hreset_vector
= 0x00000100UL
;
2001 #if defined(TARGET_PPC64)
2002 static void init_excp_970(CPUPPCState
*env
)
2004 #if !defined(CONFIG_USER_ONLY)
2005 env
->excp_vectors
[POWERPC_EXCP_RESET
] = 0x00000100;
2006 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
2007 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000300;
2008 env
->excp_vectors
[POWERPC_EXCP_DSEG
] = 0x00000380;
2009 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000400;
2010 env
->excp_vectors
[POWERPC_EXCP_ISEG
] = 0x00000480;
2011 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
2012 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
2013 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
2014 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000800;
2015 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000900;
2016 env
->excp_vectors
[POWERPC_EXCP_HDECR
] = 0x00000980;
2017 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
2018 env
->excp_vectors
[POWERPC_EXCP_TRACE
] = 0x00000D00;
2019 env
->excp_vectors
[POWERPC_EXCP_PERFM
] = 0x00000F00;
2020 env
->excp_vectors
[POWERPC_EXCP_VPU
] = 0x00000F20;
2021 env
->excp_vectors
[POWERPC_EXCP_IABR
] = 0x00001300;
2022 env
->excp_vectors
[POWERPC_EXCP_MAINT
] = 0x00001600;
2023 env
->excp_vectors
[POWERPC_EXCP_VPUA
] = 0x00001700;
2024 env
->excp_vectors
[POWERPC_EXCP_THERM
] = 0x00001800;
2025 /* Hardware reset vector */
2026 env
->hreset_vector
= 0x0000000000000100ULL
;
2030 static void init_excp_POWER7(CPUPPCState
*env
)
2032 #if !defined(CONFIG_USER_ONLY)
2033 env
->excp_vectors
[POWERPC_EXCP_RESET
] = 0x00000100;
2034 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
2035 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000300;
2036 env
->excp_vectors
[POWERPC_EXCP_DSEG
] = 0x00000380;
2037 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000400;
2038 env
->excp_vectors
[POWERPC_EXCP_ISEG
] = 0x00000480;
2039 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
2040 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
2041 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
2042 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000800;
2043 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000900;
2044 env
->excp_vectors
[POWERPC_EXCP_HDECR
] = 0x00000980;
2045 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
2046 env
->excp_vectors
[POWERPC_EXCP_TRACE
] = 0x00000D00;
2047 env
->excp_vectors
[POWERPC_EXCP_HDSI
] = 0x00000E00;
2048 env
->excp_vectors
[POWERPC_EXCP_HISI
] = 0x00000E20;
2049 env
->excp_vectors
[POWERPC_EXCP_HV_EMU
] = 0x00000E40;
2050 env
->excp_vectors
[POWERPC_EXCP_HV_MAINT
] = 0x00000E60;
2051 env
->excp_vectors
[POWERPC_EXCP_PERFM
] = 0x00000F00;
2052 env
->excp_vectors
[POWERPC_EXCP_VPU
] = 0x00000F20;
2053 env
->excp_vectors
[POWERPC_EXCP_VSXU
] = 0x00000F40;
2054 /* Hardware reset vector */
2055 env
->hreset_vector
= 0x0000000000000100ULL
;
2059 static void init_excp_POWER8(CPUPPCState
*env
)
2061 init_excp_POWER7(env
);
2063 #if !defined(CONFIG_USER_ONLY)
2064 env
->excp_vectors
[POWERPC_EXCP_SDOOR
] = 0x00000A00;
2065 env
->excp_vectors
[POWERPC_EXCP_FU
] = 0x00000F60;
2066 env
->excp_vectors
[POWERPC_EXCP_HV_FU
] = 0x00000F80;
2067 env
->excp_vectors
[POWERPC_EXCP_SDOOR_HV
] = 0x00000E80;
2069 /* Userland exceptions without vector value in PowerISA v3.1 */
2070 env
->excp_vectors
[POWERPC_EXCP_PERFM_EBB
] = 0x0;
2071 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL_EBB
] = 0x0;
2075 static void init_excp_POWER9(CPUPPCState
*env
)
2077 init_excp_POWER8(env
);
2079 #if !defined(CONFIG_USER_ONLY)
2080 env
->excp_vectors
[POWERPC_EXCP_HVIRT
] = 0x00000EA0;
2081 env
->excp_vectors
[POWERPC_EXCP_SYSCALL_VECTORED
] = 0x00017000;
2085 static void init_excp_POWER10(CPUPPCState
*env
)
2087 init_excp_POWER9(env
);
2092 static int check_pow_hid0(CPUPPCState
*env
)
2094 if (env
->spr
[SPR_HID0
] & 0x00E00000) {
2101 static int check_pow_hid0_74xx(CPUPPCState
*env
)
2103 if (env
->spr
[SPR_HID0
] & 0x00600000) {
2110 static void init_proc_405(CPUPPCState
*env
)
2112 register_40x_sprs(env
);
2113 register_405_sprs(env
);
2114 register_usprgh_sprs(env
);
2116 /* Memory management */
2117 #if !defined(CONFIG_USER_ONLY)
2121 env
->tlb_type
= TLB_EMB
;
2123 init_excp_4xx_softmmu(env
);
2124 env
->dcache_line_size
= 32;
2125 env
->icache_line_size
= 32;
2126 /* Allocate hardware IRQ controller */
2127 ppc40x_irq_init(env_archcpu(env
));
2129 SET_FIT_PERIOD(8, 12, 16, 20);
2130 SET_WDT_PERIOD(16, 20, 24, 28);
2133 POWERPC_FAMILY(405)(ObjectClass
*oc
, void *data
)
2135 DeviceClass
*dc
= DEVICE_CLASS(oc
);
2136 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
2138 dc
->desc
= "PowerPC 405";
2139 pcc
->init_proc
= init_proc_405
;
2140 pcc
->check_pow
= check_pow_nocheck
;
2141 pcc
->insns_flags
= PPC_INSNS_BASE
| PPC_STRING
| PPC_MFTB
|
2142 PPC_DCR
| PPC_WRTEE
|
2143 PPC_CACHE
| PPC_CACHE_ICBI
| PPC_40x_ICBT
|
2144 PPC_CACHE_DCBZ
| PPC_CACHE_DCBA
|
2145 PPC_MEM_SYNC
| PPC_MEM_EIEIO
|
2146 PPC_40x_TLB
| PPC_MEM_TLBIA
| PPC_MEM_TLBSYNC
|
2147 PPC_4xx_COMMON
| PPC_405_MAC
| PPC_40x_EXCP
;
2148 pcc
->msr_mask
= (1ull << MSR_WE
) |
2158 pcc
->mmu_model
= POWERPC_MMU_SOFT_4xx
;
2159 pcc
->excp_model
= POWERPC_EXCP_40x
;
2160 pcc
->bus_model
= PPC_FLAGS_INPUT_405
;
2161 pcc
->bfd_mach
= bfd_mach_ppc_403
;
2162 pcc
->flags
= POWERPC_FLAG_CE
| POWERPC_FLAG_DWE
|
2163 POWERPC_FLAG_DE
| POWERPC_FLAG_BUS_CLK
;
2166 static void init_proc_440EP(CPUPPCState
*env
)
2168 register_BookE_sprs(env
, 0x000000000000FFFFULL
);
2169 register_440_sprs(env
);
2170 register_usprgh_sprs(env
);
2172 spr_register(env
, SPR_BOOKE_MCSR
, "MCSR",
2173 SPR_NOACCESS
, SPR_NOACCESS
,
2174 &spr_read_generic
, &spr_write_generic
,
2176 spr_register(env
, SPR_BOOKE_MCSRR0
, "MCSRR0",
2177 SPR_NOACCESS
, SPR_NOACCESS
,
2178 &spr_read_generic
, &spr_write_generic
,
2180 spr_register(env
, SPR_BOOKE_MCSRR1
, "MCSRR1",
2181 SPR_NOACCESS
, SPR_NOACCESS
,
2182 &spr_read_generic
, &spr_write_generic
,
2185 spr_register(env
, SPR_440_CCR1
, "CCR1",
2186 SPR_NOACCESS
, SPR_NOACCESS
,
2187 &spr_read_generic
, &spr_write_generic
,
2189 /* Memory management */
2190 #if !defined(CONFIG_USER_ONLY)
2194 env
->tlb_type
= TLB_EMB
;
2196 init_excp_BookE(env
);
2197 env
->dcache_line_size
= 32;
2198 env
->icache_line_size
= 32;
2199 ppc40x_irq_init(env_archcpu(env
));
2201 SET_FIT_PERIOD(12, 16, 20, 24);
2202 SET_WDT_PERIOD(20, 24, 28, 32);
2205 POWERPC_FAMILY(440EP
)(ObjectClass
*oc
, void *data
)
2207 DeviceClass
*dc
= DEVICE_CLASS(oc
);
2208 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
2210 dc
->desc
= "PowerPC 440 EP";
2211 pcc
->init_proc
= init_proc_440EP
;
2212 pcc
->check_pow
= check_pow_nocheck
;
2213 pcc
->insns_flags
= PPC_INSNS_BASE
| PPC_STRING
|
2214 PPC_FLOAT
| PPC_FLOAT_FRES
| PPC_FLOAT_FSEL
|
2215 PPC_FLOAT_FSQRT
| PPC_FLOAT_FRSQRTE
|
2217 PPC_DCR
| PPC_WRTEE
| PPC_RFMCI
|
2218 PPC_CACHE
| PPC_CACHE_ICBI
|
2219 PPC_CACHE_DCBZ
| PPC_CACHE_DCBA
|
2220 PPC_MEM_TLBSYNC
| PPC_MFTB
|
2221 PPC_BOOKE
| PPC_4xx_COMMON
| PPC_405_MAC
|
2223 pcc
->msr_mask
= (1ull << MSR_POW
) |
2235 pcc
->mmu_model
= POWERPC_MMU_BOOKE
;
2236 pcc
->excp_model
= POWERPC_EXCP_BOOKE
;
2237 pcc
->bus_model
= PPC_FLAGS_INPUT_BookE
;
2238 pcc
->bfd_mach
= bfd_mach_ppc_403
;
2239 pcc
->flags
= POWERPC_FLAG_CE
| POWERPC_FLAG_DWE
|
2240 POWERPC_FLAG_DE
| POWERPC_FLAG_BUS_CLK
;
2243 POWERPC_FAMILY(460EX
)(ObjectClass
*oc
, void *data
)
2245 DeviceClass
*dc
= DEVICE_CLASS(oc
);
2246 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
2248 dc
->desc
= "PowerPC 460 EX";
2249 pcc
->init_proc
= init_proc_440EP
;
2250 pcc
->check_pow
= check_pow_nocheck
;
2251 pcc
->insns_flags
= PPC_INSNS_BASE
| PPC_STRING
|
2252 PPC_FLOAT
| PPC_FLOAT_FRES
| PPC_FLOAT_FSEL
|
2253 PPC_FLOAT_FSQRT
| PPC_FLOAT_FRSQRTE
|
2255 PPC_DCR
| PPC_DCRX
| PPC_WRTEE
| PPC_RFMCI
|
2256 PPC_CACHE
| PPC_CACHE_ICBI
|
2257 PPC_CACHE_DCBZ
| PPC_CACHE_DCBA
|
2258 PPC_MEM_TLBSYNC
| PPC_MFTB
|
2259 PPC_BOOKE
| PPC_4xx_COMMON
| PPC_405_MAC
|
2261 pcc
->msr_mask
= (1ull << MSR_POW
) |
2273 pcc
->mmu_model
= POWERPC_MMU_BOOKE
;
2274 pcc
->excp_model
= POWERPC_EXCP_BOOKE
;
2275 pcc
->bus_model
= PPC_FLAGS_INPUT_BookE
;
2276 pcc
->bfd_mach
= bfd_mach_ppc_403
;
2277 pcc
->flags
= POWERPC_FLAG_CE
| POWERPC_FLAG_DWE
|
2278 POWERPC_FLAG_DE
| POWERPC_FLAG_BUS_CLK
;
2281 static void init_proc_440GP(CPUPPCState
*env
)
2283 register_BookE_sprs(env
, 0x000000000000FFFFULL
);
2284 register_440_sprs(env
);
2285 register_usprgh_sprs(env
);
2287 /* Memory management */
2288 #if !defined(CONFIG_USER_ONLY)
2292 env
->tlb_type
= TLB_EMB
;
2294 init_excp_BookE(env
);
2295 env
->dcache_line_size
= 32;
2296 env
->icache_line_size
= 32;
2297 /* XXX: TODO: allocate internal IRQ controller */
2299 SET_FIT_PERIOD(12, 16, 20, 24);
2300 SET_WDT_PERIOD(20, 24, 28, 32);
2303 POWERPC_FAMILY(440GP
)(ObjectClass
*oc
, void *data
)
2305 DeviceClass
*dc
= DEVICE_CLASS(oc
);
2306 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
2308 dc
->desc
= "PowerPC 440 GP";
2309 pcc
->init_proc
= init_proc_440GP
;
2310 pcc
->check_pow
= check_pow_nocheck
;
2311 pcc
->insns_flags
= PPC_INSNS_BASE
| PPC_STRING
|
2312 PPC_DCR
| PPC_DCRX
| PPC_WRTEE
| PPC_MFAPIDI
|
2313 PPC_CACHE
| PPC_CACHE_ICBI
|
2314 PPC_CACHE_DCBZ
| PPC_CACHE_DCBA
|
2315 PPC_MEM_TLBSYNC
| PPC_TLBIVA
| PPC_MFTB
|
2316 PPC_BOOKE
| PPC_4xx_COMMON
| PPC_405_MAC
|
2318 pcc
->msr_mask
= (1ull << MSR_POW
) |
2330 pcc
->mmu_model
= POWERPC_MMU_BOOKE
;
2331 pcc
->excp_model
= POWERPC_EXCP_BOOKE
;
2332 pcc
->bus_model
= PPC_FLAGS_INPUT_BookE
;
2333 pcc
->bfd_mach
= bfd_mach_ppc_403
;
2334 pcc
->flags
= POWERPC_FLAG_CE
| POWERPC_FLAG_DWE
|
2335 POWERPC_FLAG_DE
| POWERPC_FLAG_BUS_CLK
;
2338 static void init_proc_440x5(CPUPPCState
*env
)
2340 register_BookE_sprs(env
, 0x000000000000FFFFULL
);
2341 register_440_sprs(env
);
2342 register_usprgh_sprs(env
);
2344 spr_register(env
, SPR_BOOKE_MCSR
, "MCSR",
2345 SPR_NOACCESS
, SPR_NOACCESS
,
2346 &spr_read_generic
, &spr_write_generic
,
2348 spr_register(env
, SPR_BOOKE_MCSRR0
, "MCSRR0",
2349 SPR_NOACCESS
, SPR_NOACCESS
,
2350 &spr_read_generic
, &spr_write_generic
,
2352 spr_register(env
, SPR_BOOKE_MCSRR1
, "MCSRR1",
2353 SPR_NOACCESS
, SPR_NOACCESS
,
2354 &spr_read_generic
, &spr_write_generic
,
2357 spr_register(env
, SPR_440_CCR1
, "CCR1",
2358 SPR_NOACCESS
, SPR_NOACCESS
,
2359 &spr_read_generic
, &spr_write_generic
,
2361 /* Memory management */
2362 #if !defined(CONFIG_USER_ONLY)
2366 env
->tlb_type
= TLB_EMB
;
2368 init_excp_BookE(env
);
2369 env
->dcache_line_size
= 32;
2370 env
->icache_line_size
= 32;
2371 ppc40x_irq_init(env_archcpu(env
));
2373 SET_FIT_PERIOD(12, 16, 20, 24);
2374 SET_WDT_PERIOD(20, 24, 28, 32);
2377 POWERPC_FAMILY(440x5
)(ObjectClass
*oc
, void *data
)
2379 DeviceClass
*dc
= DEVICE_CLASS(oc
);
2380 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
2382 dc
->desc
= "PowerPC 440x5";
2383 pcc
->init_proc
= init_proc_440x5
;
2384 pcc
->check_pow
= check_pow_nocheck
;
2385 pcc
->insns_flags
= PPC_INSNS_BASE
| PPC_STRING
|
2386 PPC_DCR
| PPC_WRTEE
| PPC_RFMCI
|
2387 PPC_CACHE
| PPC_CACHE_ICBI
|
2388 PPC_CACHE_DCBZ
| PPC_CACHE_DCBA
|
2389 PPC_MEM_TLBSYNC
| PPC_MFTB
|
2390 PPC_BOOKE
| PPC_4xx_COMMON
| PPC_405_MAC
|
2392 pcc
->msr_mask
= (1ull << MSR_POW
) |
2404 pcc
->mmu_model
= POWERPC_MMU_BOOKE
;
2405 pcc
->excp_model
= POWERPC_EXCP_BOOKE
;
2406 pcc
->bus_model
= PPC_FLAGS_INPUT_BookE
;
2407 pcc
->bfd_mach
= bfd_mach_ppc_403
;
2408 pcc
->flags
= POWERPC_FLAG_CE
| POWERPC_FLAG_DWE
|
2409 POWERPC_FLAG_DE
| POWERPC_FLAG_BUS_CLK
;
2412 POWERPC_FAMILY(440x5wDFPU
)(ObjectClass
*oc
, void *data
)
2414 DeviceClass
*dc
= DEVICE_CLASS(oc
);
2415 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
2417 dc
->desc
= "PowerPC 440x5 with double precision FPU";
2418 pcc
->init_proc
= init_proc_440x5
;
2419 pcc
->check_pow
= check_pow_nocheck
;
2420 pcc
->insns_flags
= PPC_INSNS_BASE
| PPC_STRING
|
2421 PPC_FLOAT
| PPC_FLOAT_FSQRT
|
2423 PPC_DCR
| PPC_WRTEE
| PPC_RFMCI
|
2424 PPC_CACHE
| PPC_CACHE_ICBI
|
2425 PPC_CACHE_DCBZ
| PPC_CACHE_DCBA
|
2426 PPC_MEM_TLBSYNC
| PPC_MFTB
|
2427 PPC_BOOKE
| PPC_4xx_COMMON
| PPC_405_MAC
|
2429 pcc
->insns_flags2
= PPC2_FP_CVT_S64
;
2430 pcc
->msr_mask
= (1ull << MSR_POW
) |
2442 pcc
->mmu_model
= POWERPC_MMU_BOOKE
;
2443 pcc
->excp_model
= POWERPC_EXCP_BOOKE
;
2444 pcc
->bus_model
= PPC_FLAGS_INPUT_BookE
;
2445 pcc
->bfd_mach
= bfd_mach_ppc_403
;
2446 pcc
->flags
= POWERPC_FLAG_CE
| POWERPC_FLAG_DWE
|
2447 POWERPC_FLAG_DE
| POWERPC_FLAG_BUS_CLK
;
2450 static void init_proc_MPC5xx(CPUPPCState
*env
)
2452 register_5xx_8xx_sprs(env
);
2453 register_5xx_sprs(env
);
2454 init_excp_MPC5xx(env
);
2455 env
->dcache_line_size
= 32;
2456 env
->icache_line_size
= 32;
2457 /* XXX: TODO: allocate internal IRQ controller */
2460 POWERPC_FAMILY(MPC5xx
)(ObjectClass
*oc
, void *data
)
2462 DeviceClass
*dc
= DEVICE_CLASS(oc
);
2463 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
2465 dc
->desc
= "Freescale 5xx cores (aka RCPU)";
2466 pcc
->init_proc
= init_proc_MPC5xx
;
2467 pcc
->check_pow
= check_pow_none
;
2468 pcc
->insns_flags
= PPC_INSNS_BASE
| PPC_STRING
|
2469 PPC_MEM_EIEIO
| PPC_MEM_SYNC
|
2470 PPC_CACHE_ICBI
| PPC_FLOAT
| PPC_FLOAT_STFIWX
|
2472 pcc
->msr_mask
= (1ull << MSR_ILE
) |
2484 pcc
->mmu_model
= POWERPC_MMU_REAL
;
2485 pcc
->excp_model
= POWERPC_EXCP_6xx
;
2486 pcc
->bus_model
= PPC_FLAGS_INPUT_RCPU
;
2487 pcc
->bfd_mach
= bfd_mach_ppc_505
;
2488 pcc
->flags
= POWERPC_FLAG_SE
| POWERPC_FLAG_BE
|
2489 POWERPC_FLAG_BUS_CLK
;
2492 static void init_proc_MPC8xx(CPUPPCState
*env
)
2494 register_5xx_8xx_sprs(env
);
2495 register_8xx_sprs(env
);
2496 init_excp_MPC8xx(env
);
2497 env
->dcache_line_size
= 32;
2498 env
->icache_line_size
= 32;
2499 /* XXX: TODO: allocate internal IRQ controller */
2502 POWERPC_FAMILY(MPC8xx
)(ObjectClass
*oc
, void *data
)
2504 DeviceClass
*dc
= DEVICE_CLASS(oc
);
2505 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
2507 dc
->desc
= "Freescale 8xx cores (aka PowerQUICC)";
2508 pcc
->init_proc
= init_proc_MPC8xx
;
2509 pcc
->check_pow
= check_pow_none
;
2510 pcc
->insns_flags
= PPC_INSNS_BASE
| PPC_STRING
|
2511 PPC_MEM_EIEIO
| PPC_MEM_SYNC
|
2512 PPC_CACHE_ICBI
| PPC_MFTB
;
2513 pcc
->msr_mask
= (1ull << MSR_ILE
) |
2525 pcc
->mmu_model
= POWERPC_MMU_MPC8xx
;
2526 pcc
->excp_model
= POWERPC_EXCP_6xx
;
2527 pcc
->bus_model
= PPC_FLAGS_INPUT_RCPU
;
2528 pcc
->bfd_mach
= bfd_mach_ppc_860
;
2529 pcc
->flags
= POWERPC_FLAG_SE
| POWERPC_FLAG_BE
|
2530 POWERPC_FLAG_BUS_CLK
;
2533 /* Freescale 82xx cores (aka PowerQUICC-II) */
2535 static void init_proc_G2(CPUPPCState
*env
)
2537 register_non_embedded_sprs(env
);
2538 register_sdr1_sprs(env
);
2539 register_G2_sprs(env
);
2541 /* Memory management */
2542 register_low_BATs(env
);
2543 register_high_BATs(env
);
2544 register_6xx_7xx_soft_tlb(env
, 64, 2);
2546 env
->dcache_line_size
= 32;
2547 env
->icache_line_size
= 32;
2548 /* Allocate hardware IRQ controller */
2549 ppc6xx_irq_init(env_archcpu(env
));
2552 POWERPC_FAMILY(G2
)(ObjectClass
*oc
, void *data
)
2554 DeviceClass
*dc
= DEVICE_CLASS(oc
);
2555 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
2557 dc
->desc
= "PowerPC G2";
2558 pcc
->init_proc
= init_proc_G2
;
2559 pcc
->check_pow
= check_pow_hid0
;
2560 pcc
->insns_flags
= PPC_INSNS_BASE
| PPC_STRING
| PPC_MFTB
|
2561 PPC_FLOAT
| PPC_FLOAT_FSEL
| PPC_FLOAT_FRES
|
2563 PPC_CACHE
| PPC_CACHE_ICBI
| PPC_CACHE_DCBZ
|
2564 PPC_MEM_SYNC
| PPC_MEM_EIEIO
|
2565 PPC_MEM_TLBIE
| PPC_MEM_TLBSYNC
| PPC_6xx_TLB
|
2566 PPC_SEGMENT
| PPC_EXTERN
;
2567 pcc
->msr_mask
= (1ull << MSR_POW
) |
2568 (1ull << MSR_TGPR
) |
2582 pcc
->mmu_model
= POWERPC_MMU_SOFT_6xx
;
2583 pcc
->excp_model
= POWERPC_EXCP_6xx
;
2584 pcc
->bus_model
= PPC_FLAGS_INPUT_6xx
;
2585 pcc
->bfd_mach
= bfd_mach_ppc_ec603e
;
2586 pcc
->flags
= POWERPC_FLAG_TGPR
| POWERPC_FLAG_SE
|
2587 POWERPC_FLAG_BE
| POWERPC_FLAG_BUS_CLK
;
2590 POWERPC_FAMILY(G2LE
)(ObjectClass
*oc
, void *data
)
2592 DeviceClass
*dc
= DEVICE_CLASS(oc
);
2593 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
2595 dc
->desc
= "PowerPC G2LE";
2596 pcc
->init_proc
= init_proc_G2
;
2597 pcc
->check_pow
= check_pow_hid0
;
2598 pcc
->insns_flags
= PPC_INSNS_BASE
| PPC_STRING
| PPC_MFTB
|
2599 PPC_FLOAT
| PPC_FLOAT_FSEL
| PPC_FLOAT_FRES
|
2601 PPC_CACHE
| PPC_CACHE_ICBI
| PPC_CACHE_DCBZ
|
2602 PPC_MEM_SYNC
| PPC_MEM_EIEIO
|
2603 PPC_MEM_TLBIE
| PPC_MEM_TLBSYNC
| PPC_6xx_TLB
|
2604 PPC_SEGMENT
| PPC_EXTERN
;
2605 pcc
->msr_mask
= (1ull << MSR_POW
) |
2606 (1ull << MSR_TGPR
) |
2622 pcc
->mmu_model
= POWERPC_MMU_SOFT_6xx
;
2623 pcc
->excp_model
= POWERPC_EXCP_6xx
;
2624 pcc
->bus_model
= PPC_FLAGS_INPUT_6xx
;
2625 pcc
->bfd_mach
= bfd_mach_ppc_ec603e
;
2626 pcc
->flags
= POWERPC_FLAG_TGPR
| POWERPC_FLAG_SE
|
2627 POWERPC_FLAG_BE
| POWERPC_FLAG_BUS_CLK
;
2630 static void init_proc_e200(CPUPPCState
*env
)
2632 register_BookE_sprs(env
, 0x000000070000FFFFULL
);
2634 spr_register(env
, SPR_BOOKE_SPEFSCR
, "SPEFSCR",
2635 &spr_read_spefscr
, &spr_write_spefscr
,
2636 &spr_read_spefscr
, &spr_write_spefscr
,
2638 /* Memory management */
2639 register_BookE206_sprs(env
, 0x0000005D, NULL
, 0);
2640 register_usprgh_sprs(env
);
2642 spr_register(env
, SPR_HID0
, "HID0",
2643 SPR_NOACCESS
, SPR_NOACCESS
,
2644 &spr_read_generic
, &spr_write_generic
,
2647 spr_register(env
, SPR_HID1
, "HID1",
2648 SPR_NOACCESS
, SPR_NOACCESS
,
2649 &spr_read_generic
, &spr_write_generic
,
2652 spr_register(env
, SPR_Exxx_ALTCTXCR
, "ALTCTXCR",
2653 SPR_NOACCESS
, SPR_NOACCESS
,
2654 &spr_read_generic
, &spr_write_generic
,
2657 spr_register(env
, SPR_Exxx_BUCSR
, "BUCSR",
2658 SPR_NOACCESS
, SPR_NOACCESS
,
2659 &spr_read_generic
, &spr_write_generic
,
2662 spr_register(env
, SPR_Exxx_CTXCR
, "CTXCR",
2663 SPR_NOACCESS
, SPR_NOACCESS
,
2664 &spr_read_generic
, &spr_write_generic
,
2667 spr_register(env
, SPR_Exxx_DBCNT
, "DBCNT",
2668 SPR_NOACCESS
, SPR_NOACCESS
,
2669 &spr_read_generic
, &spr_write_generic
,
2672 spr_register(env
, SPR_Exxx_DBCR3
, "DBCR3",
2673 SPR_NOACCESS
, SPR_NOACCESS
,
2674 &spr_read_generic
, &spr_write_generic
,
2677 spr_register(env
, SPR_Exxx_L1CFG0
, "L1CFG0",
2678 &spr_read_generic
, SPR_NOACCESS
,
2679 &spr_read_generic
, SPR_NOACCESS
,
2682 spr_register(env
, SPR_Exxx_L1CSR0
, "L1CSR0",
2683 SPR_NOACCESS
, SPR_NOACCESS
,
2684 &spr_read_generic
, &spr_write_generic
,
2687 spr_register(env
, SPR_Exxx_L1FINV0
, "L1FINV0",
2688 SPR_NOACCESS
, SPR_NOACCESS
,
2689 &spr_read_generic
, &spr_write_generic
,
2692 spr_register(env
, SPR_BOOKE_TLB0CFG
, "TLB0CFG",
2693 SPR_NOACCESS
, SPR_NOACCESS
,
2694 &spr_read_generic
, &spr_write_generic
,
2697 spr_register(env
, SPR_BOOKE_TLB1CFG
, "TLB1CFG",
2698 SPR_NOACCESS
, SPR_NOACCESS
,
2699 &spr_read_generic
, &spr_write_generic
,
2702 spr_register(env
, SPR_BOOKE_IAC3
, "IAC3",
2703 SPR_NOACCESS
, SPR_NOACCESS
,
2704 &spr_read_generic
, &spr_write_generic
,
2707 spr_register(env
, SPR_BOOKE_IAC4
, "IAC4",
2708 SPR_NOACCESS
, SPR_NOACCESS
,
2709 &spr_read_generic
, &spr_write_generic
,
2712 spr_register(env
, SPR_MMUCSR0
, "MMUCSR0",
2713 SPR_NOACCESS
, SPR_NOACCESS
,
2714 &spr_read_generic
, &spr_write_generic
,
2715 0x00000000); /* TOFIX */
2716 spr_register(env
, SPR_BOOKE_DSRR0
, "DSRR0",
2717 SPR_NOACCESS
, SPR_NOACCESS
,
2718 &spr_read_generic
, &spr_write_generic
,
2720 spr_register(env
, SPR_BOOKE_DSRR1
, "DSRR1",
2721 SPR_NOACCESS
, SPR_NOACCESS
,
2722 &spr_read_generic
, &spr_write_generic
,
2724 #if !defined(CONFIG_USER_ONLY)
2728 env
->tlb_type
= TLB_EMB
;
2730 init_excp_e200(env
, 0xFFFF0000UL
);
2731 env
->dcache_line_size
= 32;
2732 env
->icache_line_size
= 32;
2733 /* XXX: TODO: allocate internal IRQ controller */
2736 POWERPC_FAMILY(e200
)(ObjectClass
*oc
, void *data
)
2738 DeviceClass
*dc
= DEVICE_CLASS(oc
);
2739 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
2741 dc
->desc
= "e200 core";
2742 pcc
->init_proc
= init_proc_e200
;
2743 pcc
->check_pow
= check_pow_hid0
;
2745 * XXX: unimplemented instructions:
2752 * all SPE multiply-accumulate instructions
2754 pcc
->insns_flags
= PPC_INSNS_BASE
| PPC_ISEL
|
2755 PPC_SPE
| PPC_SPE_SINGLE
|
2756 PPC_WRTEE
| PPC_RFDI
|
2757 PPC_CACHE
| PPC_CACHE_LOCK
| PPC_CACHE_ICBI
|
2758 PPC_CACHE_DCBZ
| PPC_CACHE_DCBA
|
2759 PPC_MEM_TLBSYNC
| PPC_TLBIVAX
|
2761 pcc
->msr_mask
= (1ull << MSR_UCLE
) |
2775 pcc
->mmu_model
= POWERPC_MMU_BOOKE206
;
2776 pcc
->excp_model
= POWERPC_EXCP_BOOKE
;
2777 pcc
->bus_model
= PPC_FLAGS_INPUT_BookE
;
2778 pcc
->bfd_mach
= bfd_mach_ppc_860
;
2779 pcc
->flags
= POWERPC_FLAG_SPE
| POWERPC_FLAG_CE
|
2780 POWERPC_FLAG_UBLE
| POWERPC_FLAG_DE
|
2781 POWERPC_FLAG_BUS_CLK
;
2784 enum fsl_e500_version
{
2792 static void init_proc_e500(CPUPPCState
*env
, int version
)
2794 uint32_t tlbncfg
[2];
2796 uint64_t ivpr_mask
= 0xFFFF0000ULL
;
2797 uint32_t l1cfg0
= 0x3800 /* 8 ways */
2798 | 0x0020; /* 32 kb */
2799 uint32_t l1cfg1
= 0x3800 /* 8 ways */
2800 | 0x0020; /* 32 kb */
2801 uint32_t mmucfg
= 0;
2802 #if !defined(CONFIG_USER_ONLY)
2807 * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't
2808 * complain when accessing them.
2809 * register_BookE_sprs(env, 0x0000000F0000FD7FULL);
2815 ivor_mask
= 0x0000000F0000FFFFULL
;
2819 ivor_mask
= 0x000003FE0000FFFFULL
;
2822 ivor_mask
= 0x000003FF0000FFFFULL
;
2825 register_BookE_sprs(env
, ivor_mask
);
2827 spr_register(env
, SPR_USPRG3
, "USPRG3",
2828 &spr_read_ureg
, SPR_NOACCESS
,
2829 &spr_read_ureg
, SPR_NOACCESS
,
2832 /* Processor identification */
2833 spr_register(env
, SPR_BOOKE_PIR
, "PIR",
2834 SPR_NOACCESS
, SPR_NOACCESS
,
2835 &spr_read_generic
, &spr_write_pir
,
2838 spr_register(env
, SPR_BOOKE_SPEFSCR
, "SPEFSCR",
2839 &spr_read_spefscr
, &spr_write_spefscr
,
2840 &spr_read_spefscr
, &spr_write_spefscr
,
2842 #if !defined(CONFIG_USER_ONLY)
2843 /* Memory management */
2849 tlbncfg
[0] = register_tlbncfg(2, 1, 1, 0, 256);
2850 tlbncfg
[1] = register_tlbncfg(16, 1, 9, TLBnCFG_AVAIL
| TLBnCFG_IPROT
, 16);
2853 tlbncfg
[0] = register_tlbncfg(4, 1, 1, 0, 512);
2854 tlbncfg
[1] = register_tlbncfg(16, 1, 12, TLBnCFG_AVAIL
| TLBnCFG_IPROT
, 16);
2858 tlbncfg
[0] = register_tlbncfg(4, 1, 1, 0, 512);
2859 tlbncfg
[1] = register_tlbncfg(64, 1, 12, TLBnCFG_AVAIL
| TLBnCFG_IPROT
, 64);
2864 tlbncfg
[0] = 0x08052400;
2865 tlbncfg
[1] = 0x40028040;
2868 cpu_abort(env_cpu(env
), "Unknown CPU: " TARGET_FMT_lx
"\n",
2876 env
->dcache_line_size
= 32;
2877 env
->icache_line_size
= 32;
2881 env
->dcache_line_size
= 64;
2882 env
->icache_line_size
= 64;
2883 l1cfg0
|= 0x1000000; /* 64 byte cache block size */
2884 l1cfg1
|= 0x1000000; /* 64 byte cache block size */
2887 env
->dcache_line_size
= 32;
2888 env
->icache_line_size
= 32;
2889 l1cfg0
|= 0x0F83820;
2890 l1cfg1
|= 0x0B83820;
2893 cpu_abort(env_cpu(env
), "Unknown CPU: " TARGET_FMT_lx
"\n",
2896 register_BookE206_sprs(env
, 0x000000DF, tlbncfg
, mmucfg
);
2897 register_usprgh_sprs(env
);
2899 spr_register(env
, SPR_HID0
, "HID0",
2900 SPR_NOACCESS
, SPR_NOACCESS
,
2901 &spr_read_generic
, &spr_write_generic
,
2904 spr_register(env
, SPR_HID1
, "HID1",
2905 SPR_NOACCESS
, SPR_NOACCESS
,
2906 &spr_read_generic
, &spr_write_generic
,
2909 spr_register(env
, SPR_Exxx_BBEAR
, "BBEAR",
2910 SPR_NOACCESS
, SPR_NOACCESS
,
2911 &spr_read_generic
, &spr_write_generic
,
2914 spr_register(env
, SPR_Exxx_BBTAR
, "BBTAR",
2915 SPR_NOACCESS
, SPR_NOACCESS
,
2916 &spr_read_generic
, &spr_write_generic
,
2919 spr_register(env
, SPR_Exxx_MCAR
, "MCAR",
2920 SPR_NOACCESS
, SPR_NOACCESS
,
2921 &spr_read_generic
, &spr_write_generic
,
2924 spr_register(env
, SPR_BOOKE_MCSR
, "MCSR",
2925 SPR_NOACCESS
, SPR_NOACCESS
,
2926 &spr_read_generic
, &spr_write_generic
,
2929 spr_register(env
, SPR_Exxx_NPIDR
, "NPIDR",
2930 SPR_NOACCESS
, SPR_NOACCESS
,
2931 &spr_read_generic
, &spr_write_generic
,
2934 spr_register(env
, SPR_Exxx_BUCSR
, "BUCSR",
2935 SPR_NOACCESS
, SPR_NOACCESS
,
2936 &spr_read_generic
, &spr_write_generic
,
2939 spr_register(env
, SPR_Exxx_L1CFG0
, "L1CFG0",
2940 &spr_read_generic
, SPR_NOACCESS
,
2941 &spr_read_generic
, SPR_NOACCESS
,
2943 spr_register(env
, SPR_Exxx_L1CFG1
, "L1CFG1",
2944 &spr_read_generic
, SPR_NOACCESS
,
2945 &spr_read_generic
, SPR_NOACCESS
,
2947 spr_register(env
, SPR_Exxx_L1CSR0
, "L1CSR0",
2948 SPR_NOACCESS
, SPR_NOACCESS
,
2949 &spr_read_generic
, &spr_write_e500_l1csr0
,
2951 spr_register(env
, SPR_Exxx_L1CSR1
, "L1CSR1",
2952 SPR_NOACCESS
, SPR_NOACCESS
,
2953 &spr_read_generic
, &spr_write_e500_l1csr1
,
2955 if (version
!= fsl_e500v1
&& version
!= fsl_e500v2
) {
2956 spr_register(env
, SPR_Exxx_L2CSR0
, "L2CSR0",
2957 SPR_NOACCESS
, SPR_NOACCESS
,
2958 &spr_read_generic
, &spr_write_e500_l2csr0
,
2961 spr_register(env
, SPR_BOOKE_MCSRR0
, "MCSRR0",
2962 SPR_NOACCESS
, SPR_NOACCESS
,
2963 &spr_read_generic
, &spr_write_generic
,
2965 spr_register(env
, SPR_BOOKE_MCSRR1
, "MCSRR1",
2966 SPR_NOACCESS
, SPR_NOACCESS
,
2967 &spr_read_generic
, &spr_write_generic
,
2969 spr_register(env
, SPR_MMUCSR0
, "MMUCSR0",
2970 SPR_NOACCESS
, SPR_NOACCESS
,
2971 &spr_read_generic
, &spr_write_booke206_mmucsr0
,
2973 spr_register(env
, SPR_BOOKE_EPR
, "EPR",
2974 SPR_NOACCESS
, SPR_NOACCESS
,
2975 &spr_read_generic
, SPR_NOACCESS
,
2977 /* XXX better abstract into Emb.xxx features */
2978 if ((version
== fsl_e5500
) || (version
== fsl_e6500
)) {
2979 spr_register(env
, SPR_BOOKE_EPCR
, "EPCR",
2980 SPR_NOACCESS
, SPR_NOACCESS
,
2981 &spr_read_generic
, &spr_write_generic
,
2983 spr_register(env
, SPR_BOOKE_MAS7_MAS3
, "MAS7_MAS3",
2984 SPR_NOACCESS
, SPR_NOACCESS
,
2985 &spr_read_mas73
, &spr_write_mas73
,
2987 ivpr_mask
= (target_ulong
)~0xFFFFULL
;
2990 if (version
== fsl_e6500
) {
2991 /* Thread identification */
2992 spr_register(env
, SPR_TIR
, "TIR",
2993 SPR_NOACCESS
, SPR_NOACCESS
,
2994 &spr_read_generic
, SPR_NOACCESS
,
2996 spr_register(env
, SPR_BOOKE_TLB0PS
, "TLB0PS",
2997 SPR_NOACCESS
, SPR_NOACCESS
,
2998 &spr_read_generic
, SPR_NOACCESS
,
3000 spr_register(env
, SPR_BOOKE_TLB1PS
, "TLB1PS",
3001 SPR_NOACCESS
, SPR_NOACCESS
,
3002 &spr_read_generic
, SPR_NOACCESS
,
3006 #if !defined(CONFIG_USER_ONLY)
3008 env
->tlb_type
= TLB_MAS
;
3009 for (i
= 0; i
< BOOKE206_MAX_TLBN
; i
++) {
3010 env
->nb_tlb
+= booke206_tlb_size(env
, i
);
3014 init_excp_e200(env
, ivpr_mask
);
3015 /* Allocate hardware IRQ controller */
3016 ppce500_irq_init(env_archcpu(env
));
3019 static void init_proc_e500v1(CPUPPCState
*env
)
3021 init_proc_e500(env
, fsl_e500v1
);
3024 POWERPC_FAMILY(e500v1
)(ObjectClass
*oc
, void *data
)
3026 DeviceClass
*dc
= DEVICE_CLASS(oc
);
3027 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
3029 dc
->desc
= "e500v1 core";
3030 pcc
->init_proc
= init_proc_e500v1
;
3031 pcc
->check_pow
= check_pow_hid0
;
3032 pcc
->insns_flags
= PPC_INSNS_BASE
| PPC_ISEL
|
3033 PPC_SPE
| PPC_SPE_SINGLE
|
3034 PPC_WRTEE
| PPC_RFDI
|
3035 PPC_CACHE
| PPC_CACHE_LOCK
| PPC_CACHE_ICBI
|
3036 PPC_CACHE_DCBZ
| PPC_CACHE_DCBA
|
3037 PPC_MEM_TLBSYNC
| PPC_TLBIVAX
| PPC_MEM_SYNC
;
3038 pcc
->insns_flags2
= PPC2_BOOKE206
;
3039 pcc
->msr_mask
= (1ull << MSR_UCLE
) |
3053 pcc
->mmu_model
= POWERPC_MMU_BOOKE206
;
3054 pcc
->excp_model
= POWERPC_EXCP_BOOKE
;
3055 pcc
->bus_model
= PPC_FLAGS_INPUT_BookE
;
3056 pcc
->bfd_mach
= bfd_mach_ppc_860
;
3057 pcc
->flags
= POWERPC_FLAG_SPE
| POWERPC_FLAG_CE
|
3058 POWERPC_FLAG_UBLE
| POWERPC_FLAG_DE
|
3059 POWERPC_FLAG_BUS_CLK
;
3062 static void init_proc_e500v2(CPUPPCState
*env
)
3064 init_proc_e500(env
, fsl_e500v2
);
3067 POWERPC_FAMILY(e500v2
)(ObjectClass
*oc
, void *data
)
3069 DeviceClass
*dc
= DEVICE_CLASS(oc
);
3070 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
3072 dc
->desc
= "e500v2 core";
3073 pcc
->init_proc
= init_proc_e500v2
;
3074 pcc
->check_pow
= check_pow_hid0
;
3075 pcc
->insns_flags
= PPC_INSNS_BASE
| PPC_ISEL
|
3076 PPC_SPE
| PPC_SPE_SINGLE
| PPC_SPE_DOUBLE
|
3077 PPC_WRTEE
| PPC_RFDI
|
3078 PPC_CACHE
| PPC_CACHE_LOCK
| PPC_CACHE_ICBI
|
3079 PPC_CACHE_DCBZ
| PPC_CACHE_DCBA
|
3080 PPC_MEM_TLBSYNC
| PPC_TLBIVAX
| PPC_MEM_SYNC
;
3081 pcc
->insns_flags2
= PPC2_BOOKE206
;
3082 pcc
->msr_mask
= (1ull << MSR_UCLE
) |
3096 pcc
->mmu_model
= POWERPC_MMU_BOOKE206
;
3097 pcc
->excp_model
= POWERPC_EXCP_BOOKE
;
3098 pcc
->bus_model
= PPC_FLAGS_INPUT_BookE
;
3099 pcc
->bfd_mach
= bfd_mach_ppc_860
;
3100 pcc
->flags
= POWERPC_FLAG_SPE
| POWERPC_FLAG_CE
|
3101 POWERPC_FLAG_UBLE
| POWERPC_FLAG_DE
|
3102 POWERPC_FLAG_BUS_CLK
;
3105 static void init_proc_e500mc(CPUPPCState
*env
)
3107 init_proc_e500(env
, fsl_e500mc
);
3110 POWERPC_FAMILY(e500mc
)(ObjectClass
*oc
, void *data
)
3112 DeviceClass
*dc
= DEVICE_CLASS(oc
);
3113 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
3115 dc
->desc
= "e500mc core";
3116 pcc
->init_proc
= init_proc_e500mc
;
3117 pcc
->check_pow
= check_pow_none
;
3118 pcc
->insns_flags
= PPC_INSNS_BASE
| PPC_ISEL
| PPC_MFTB
|
3119 PPC_WRTEE
| PPC_RFDI
| PPC_RFMCI
|
3120 PPC_CACHE
| PPC_CACHE_LOCK
| PPC_CACHE_ICBI
|
3121 PPC_CACHE_DCBZ
| PPC_CACHE_DCBA
|
3122 PPC_FLOAT
| PPC_FLOAT_FRES
|
3123 PPC_FLOAT_FRSQRTE
| PPC_FLOAT_FSEL
|
3124 PPC_FLOAT_STFIWX
| PPC_WAIT
|
3125 PPC_MEM_TLBSYNC
| PPC_TLBIVAX
| PPC_MEM_SYNC
;
3126 pcc
->insns_flags2
= PPC2_BOOKE206
| PPC2_PRCNTL
;
3127 pcc
->msr_mask
= (1ull << MSR_GS
) |
3128 (1ull << MSR_UCLE
) |
3141 pcc
->mmu_model
= POWERPC_MMU_BOOKE206
;
3142 pcc
->excp_model
= POWERPC_EXCP_BOOKE
;
3143 pcc
->bus_model
= PPC_FLAGS_INPUT_BookE
;
3144 /* FIXME: figure out the correct flag for e500mc */
3145 pcc
->bfd_mach
= bfd_mach_ppc_e500
;
3146 pcc
->flags
= POWERPC_FLAG_CE
| POWERPC_FLAG_DE
|
3147 POWERPC_FLAG_PMM
| POWERPC_FLAG_BUS_CLK
;
3151 static void init_proc_e5500(CPUPPCState
*env
)
3153 init_proc_e500(env
, fsl_e5500
);
3156 POWERPC_FAMILY(e5500
)(ObjectClass
*oc
, void *data
)
3158 DeviceClass
*dc
= DEVICE_CLASS(oc
);
3159 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
3161 dc
->desc
= "e5500 core";
3162 pcc
->init_proc
= init_proc_e5500
;
3163 pcc
->check_pow
= check_pow_none
;
3164 pcc
->insns_flags
= PPC_INSNS_BASE
| PPC_ISEL
| PPC_MFTB
|
3165 PPC_WRTEE
| PPC_RFDI
| PPC_RFMCI
|
3166 PPC_CACHE
| PPC_CACHE_LOCK
| PPC_CACHE_ICBI
|
3167 PPC_CACHE_DCBZ
| PPC_CACHE_DCBA
|
3168 PPC_FLOAT
| PPC_FLOAT_FRES
|
3169 PPC_FLOAT_FRSQRTE
| PPC_FLOAT_FSEL
|
3170 PPC_FLOAT_STFIWX
| PPC_WAIT
|
3171 PPC_MEM_TLBSYNC
| PPC_TLBIVAX
| PPC_MEM_SYNC
|
3172 PPC_64B
| PPC_POPCNTB
| PPC_POPCNTWD
;
3173 pcc
->insns_flags2
= PPC2_BOOKE206
| PPC2_PRCNTL
| PPC2_PERM_ISA206
|
3175 pcc
->msr_mask
= (1ull << MSR_CM
) |
3177 (1ull << MSR_UCLE
) |
3190 pcc
->mmu_model
= POWERPC_MMU_BOOKE206
;
3191 pcc
->excp_model
= POWERPC_EXCP_BOOKE
;
3192 pcc
->bus_model
= PPC_FLAGS_INPUT_BookE
;
3193 /* FIXME: figure out the correct flag for e5500 */
3194 pcc
->bfd_mach
= bfd_mach_ppc_e500
;
3195 pcc
->flags
= POWERPC_FLAG_CE
| POWERPC_FLAG_DE
|
3196 POWERPC_FLAG_PMM
| POWERPC_FLAG_BUS_CLK
;
3199 static void init_proc_e6500(CPUPPCState
*env
)
3201 init_proc_e500(env
, fsl_e6500
);
3204 POWERPC_FAMILY(e6500
)(ObjectClass
*oc
, void *data
)
3206 DeviceClass
*dc
= DEVICE_CLASS(oc
);
3207 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
3209 dc
->desc
= "e6500 core";
3210 pcc
->init_proc
= init_proc_e6500
;
3211 pcc
->check_pow
= check_pow_none
;
3212 pcc
->insns_flags
= PPC_INSNS_BASE
| PPC_ISEL
| PPC_MFTB
|
3213 PPC_WRTEE
| PPC_RFDI
| PPC_RFMCI
|
3214 PPC_CACHE
| PPC_CACHE_LOCK
| PPC_CACHE_ICBI
|
3215 PPC_CACHE_DCBZ
| PPC_CACHE_DCBA
|
3216 PPC_FLOAT
| PPC_FLOAT_FRES
|
3217 PPC_FLOAT_FRSQRTE
| PPC_FLOAT_FSEL
|
3218 PPC_FLOAT_STFIWX
| PPC_WAIT
|
3219 PPC_MEM_TLBSYNC
| PPC_TLBIVAX
| PPC_MEM_SYNC
|
3220 PPC_64B
| PPC_POPCNTB
| PPC_POPCNTWD
| PPC_ALTIVEC
;
3221 pcc
->insns_flags2
= PPC2_BOOKE206
| PPC2_PRCNTL
| PPC2_PERM_ISA206
|
3222 PPC2_FP_CVT_S64
| PPC2_ATOMIC_ISA206
;
3223 pcc
->msr_mask
= (1ull << MSR_CM
) |
3225 (1ull << MSR_UCLE
) |
3239 pcc
->mmu_model
= POWERPC_MMU_BOOKE206
;
3240 pcc
->excp_model
= POWERPC_EXCP_BOOKE
;
3241 pcc
->bus_model
= PPC_FLAGS_INPUT_BookE
;
3242 pcc
->bfd_mach
= bfd_mach_ppc_e500
;
3243 pcc
->flags
= POWERPC_FLAG_CE
| POWERPC_FLAG_DE
|
3244 POWERPC_FLAG_PMM
| POWERPC_FLAG_BUS_CLK
| POWERPC_FLAG_VRE
;
3249 /* Non-embedded PowerPC */
3250 static void init_proc_603(CPUPPCState
*env
)
3252 register_non_embedded_sprs(env
);
3253 register_sdr1_sprs(env
);
3254 register_603_sprs(env
);
3256 /* Memory management */
3257 register_low_BATs(env
);
3258 register_6xx_7xx_soft_tlb(env
, 64, 2);
3260 env
->dcache_line_size
= 32;
3261 env
->icache_line_size
= 32;
3262 /* Allocate hardware IRQ controller */
3263 ppc6xx_irq_init(env_archcpu(env
));
3266 POWERPC_FAMILY(603)(ObjectClass
*oc
, void *data
)
3268 DeviceClass
*dc
= DEVICE_CLASS(oc
);
3269 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
3271 dc
->desc
= "PowerPC 603";
3272 pcc
->init_proc
= init_proc_603
;
3273 pcc
->check_pow
= check_pow_hid0
;
3274 pcc
->insns_flags
= PPC_INSNS_BASE
| PPC_STRING
| PPC_MFTB
|
3275 PPC_FLOAT
| PPC_FLOAT_FSEL
| PPC_FLOAT_FRES
|
3276 PPC_FLOAT_FRSQRTE
| PPC_FLOAT_STFIWX
|
3277 PPC_CACHE
| PPC_CACHE_ICBI
| PPC_CACHE_DCBZ
|
3278 PPC_MEM_SYNC
| PPC_MEM_EIEIO
|
3279 PPC_MEM_TLBIE
| PPC_MEM_TLBSYNC
| PPC_6xx_TLB
|
3280 PPC_SEGMENT
| PPC_EXTERN
;
3281 pcc
->msr_mask
= (1ull << MSR_POW
) |
3282 (1ull << MSR_TGPR
) |
3297 pcc
->mmu_model
= POWERPC_MMU_SOFT_6xx
;
3298 pcc
->excp_model
= POWERPC_EXCP_6xx
;
3299 pcc
->bus_model
= PPC_FLAGS_INPUT_6xx
;
3300 pcc
->bfd_mach
= bfd_mach_ppc_603
;
3301 pcc
->flags
= POWERPC_FLAG_TGPR
| POWERPC_FLAG_SE
|
3302 POWERPC_FLAG_BE
| POWERPC_FLAG_BUS_CLK
;
3305 POWERPC_FAMILY(603E
)(ObjectClass
*oc
, void *data
)
3307 DeviceClass
*dc
= DEVICE_CLASS(oc
);
3308 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
3310 dc
->desc
= "PowerPC 603e";
3311 pcc
->init_proc
= init_proc_603
;
3312 pcc
->check_pow
= check_pow_hid0
;
3313 pcc
->insns_flags
= PPC_INSNS_BASE
| PPC_STRING
| PPC_MFTB
|
3314 PPC_FLOAT
| PPC_FLOAT_FSEL
| PPC_FLOAT_FRES
|
3315 PPC_FLOAT_FRSQRTE
| PPC_FLOAT_STFIWX
|
3316 PPC_CACHE
| PPC_CACHE_ICBI
| PPC_CACHE_DCBZ
|
3317 PPC_MEM_SYNC
| PPC_MEM_EIEIO
|
3318 PPC_MEM_TLBIE
| PPC_MEM_TLBSYNC
| PPC_6xx_TLB
|
3319 PPC_SEGMENT
| PPC_EXTERN
;
3320 pcc
->msr_mask
= (1ull << MSR_POW
) |
3321 (1ull << MSR_TGPR
) |
3336 pcc
->mmu_model
= POWERPC_MMU_SOFT_6xx
;
3337 pcc
->excp_model
= POWERPC_EXCP_6xx
;
3338 pcc
->bus_model
= PPC_FLAGS_INPUT_6xx
;
3339 pcc
->bfd_mach
= bfd_mach_ppc_ec603e
;
3340 pcc
->flags
= POWERPC_FLAG_TGPR
| POWERPC_FLAG_SE
|
3341 POWERPC_FLAG_BE
| POWERPC_FLAG_BUS_CLK
;
3344 static void init_proc_e300(CPUPPCState
*env
)
3347 register_e300_sprs(env
);
3350 POWERPC_FAMILY(e300
)(ObjectClass
*oc
, void *data
)
3352 DeviceClass
*dc
= DEVICE_CLASS(oc
);
3353 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
3355 dc
->desc
= "e300 core";
3356 pcc
->init_proc
= init_proc_e300
;
3357 pcc
->check_pow
= check_pow_hid0
;
3358 pcc
->insns_flags
= PPC_INSNS_BASE
| PPC_STRING
| PPC_MFTB
|
3359 PPC_FLOAT
| PPC_FLOAT_FSEL
| PPC_FLOAT_FRES
|
3361 PPC_CACHE
| PPC_CACHE_ICBI
| PPC_CACHE_DCBZ
|
3362 PPC_MEM_SYNC
| PPC_MEM_EIEIO
|
3363 PPC_MEM_TLBIE
| PPC_MEM_TLBSYNC
| PPC_6xx_TLB
|
3364 PPC_SEGMENT
| PPC_EXTERN
;
3365 pcc
->msr_mask
= (1ull << MSR_POW
) |
3366 (1ull << MSR_TGPR
) |
3382 pcc
->mmu_model
= POWERPC_MMU_SOFT_6xx
;
3383 pcc
->excp_model
= POWERPC_EXCP_6xx
;
3384 pcc
->bus_model
= PPC_FLAGS_INPUT_6xx
;
3385 pcc
->bfd_mach
= bfd_mach_ppc_603
;
3386 pcc
->flags
= POWERPC_FLAG_TGPR
| POWERPC_FLAG_SE
|
3387 POWERPC_FLAG_BE
| POWERPC_FLAG_BUS_CLK
;
3390 static void init_proc_604(CPUPPCState
*env
)
3392 register_non_embedded_sprs(env
);
3393 register_sdr1_sprs(env
);
3394 register_604_sprs(env
);
3396 /* Memory management */
3397 register_low_BATs(env
);
3399 env
->dcache_line_size
= 32;
3400 env
->icache_line_size
= 32;
3401 /* Allocate hardware IRQ controller */
3402 ppc6xx_irq_init(env_archcpu(env
));
3405 POWERPC_FAMILY(604)(ObjectClass
*oc
, void *data
)
3407 DeviceClass
*dc
= DEVICE_CLASS(oc
);
3408 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
3410 dc
->desc
= "PowerPC 604";
3411 pcc
->init_proc
= init_proc_604
;
3412 pcc
->check_pow
= check_pow_nocheck
;
3413 pcc
->insns_flags
= PPC_INSNS_BASE
| PPC_STRING
| PPC_MFTB
|
3414 PPC_FLOAT
| PPC_FLOAT_FSEL
| PPC_FLOAT_FRES
|
3415 PPC_FLOAT_FRSQRTE
| PPC_FLOAT_STFIWX
|
3416 PPC_CACHE
| PPC_CACHE_ICBI
| PPC_CACHE_DCBZ
|
3417 PPC_MEM_SYNC
| PPC_MEM_EIEIO
|
3418 PPC_MEM_TLBIE
| PPC_MEM_TLBSYNC
|
3419 PPC_SEGMENT
| PPC_EXTERN
;
3420 pcc
->msr_mask
= (1ull << MSR_POW
) |
3436 pcc
->mmu_model
= POWERPC_MMU_32B
;
3437 pcc
->excp_model
= POWERPC_EXCP_6xx
;
3438 pcc
->bus_model
= PPC_FLAGS_INPUT_6xx
;
3439 pcc
->bfd_mach
= bfd_mach_ppc_604
;
3440 pcc
->flags
= POWERPC_FLAG_SE
| POWERPC_FLAG_BE
|
3441 POWERPC_FLAG_PMM
| POWERPC_FLAG_BUS_CLK
;
3444 static void init_proc_604E(CPUPPCState
*env
)
3447 register_604e_sprs(env
);
3450 POWERPC_FAMILY(604E
)(ObjectClass
*oc
, void *data
)
3452 DeviceClass
*dc
= DEVICE_CLASS(oc
);
3453 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
3455 dc
->desc
= "PowerPC 604E";
3456 pcc
->init_proc
= init_proc_604E
;
3457 pcc
->check_pow
= check_pow_nocheck
;
3458 pcc
->insns_flags
= PPC_INSNS_BASE
| PPC_STRING
| PPC_MFTB
|
3459 PPC_FLOAT
| PPC_FLOAT_FSEL
| PPC_FLOAT_FRES
|
3460 PPC_FLOAT_FRSQRTE
| PPC_FLOAT_STFIWX
|
3461 PPC_CACHE
| PPC_CACHE_ICBI
| PPC_CACHE_DCBZ
|
3462 PPC_MEM_SYNC
| PPC_MEM_EIEIO
|
3463 PPC_MEM_TLBIE
| PPC_MEM_TLBSYNC
|
3464 PPC_SEGMENT
| PPC_EXTERN
;
3465 pcc
->msr_mask
= (1ull << MSR_POW
) |
3481 pcc
->mmu_model
= POWERPC_MMU_32B
;
3482 pcc
->excp_model
= POWERPC_EXCP_6xx
;
3483 pcc
->bus_model
= PPC_FLAGS_INPUT_6xx
;
3484 pcc
->bfd_mach
= bfd_mach_ppc_604
;
3485 pcc
->flags
= POWERPC_FLAG_SE
| POWERPC_FLAG_BE
|
3486 POWERPC_FLAG_PMM
| POWERPC_FLAG_BUS_CLK
;
3489 static void init_proc_740(CPUPPCState
*env
)
3491 register_non_embedded_sprs(env
);
3492 register_sdr1_sprs(env
);
3493 register_7xx_sprs(env
);
3494 /* Thermal management */
3495 register_thrm_sprs(env
);
3497 /* Memory management */
3498 register_low_BATs(env
);
3500 env
->dcache_line_size
= 32;
3501 env
->icache_line_size
= 32;
3502 /* Allocate hardware IRQ controller */
3503 ppc6xx_irq_init(env_archcpu(env
));
3506 POWERPC_FAMILY(740)(ObjectClass
*oc
, void *data
)
3508 DeviceClass
*dc
= DEVICE_CLASS(oc
);
3509 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
3511 dc
->desc
= "PowerPC 740";
3512 pcc
->init_proc
= init_proc_740
;
3513 pcc
->check_pow
= check_pow_hid0
;
3514 pcc
->insns_flags
= PPC_INSNS_BASE
| PPC_STRING
| PPC_MFTB
|
3515 PPC_FLOAT
| PPC_FLOAT_FSEL
| PPC_FLOAT_FRES
|
3516 PPC_FLOAT_FRSQRTE
| PPC_FLOAT_STFIWX
|
3517 PPC_CACHE
| PPC_CACHE_ICBI
| PPC_CACHE_DCBZ
|
3518 PPC_MEM_SYNC
| PPC_MEM_EIEIO
|
3519 PPC_MEM_TLBIE
| PPC_MEM_TLBSYNC
|
3520 PPC_SEGMENT
| PPC_EXTERN
;
3521 pcc
->msr_mask
= (1ull << MSR_POW
) |
3537 pcc
->mmu_model
= POWERPC_MMU_32B
;
3538 pcc
->excp_model
= POWERPC_EXCP_7xx
;
3539 pcc
->bus_model
= PPC_FLAGS_INPUT_6xx
;
3540 pcc
->bfd_mach
= bfd_mach_ppc_750
;
3541 pcc
->flags
= POWERPC_FLAG_SE
| POWERPC_FLAG_BE
|
3542 POWERPC_FLAG_PMM
| POWERPC_FLAG_BUS_CLK
;
3545 static void init_proc_750(CPUPPCState
*env
)
3547 register_non_embedded_sprs(env
);
3548 register_sdr1_sprs(env
);
3549 register_7xx_sprs(env
);
3551 spr_register(env
, SPR_L2CR
, "L2CR",
3552 SPR_NOACCESS
, SPR_NOACCESS
,
3553 &spr_read_generic
, spr_access_nop
,
3555 /* Thermal management */
3556 register_thrm_sprs(env
);
3558 /* Memory management */
3559 register_low_BATs(env
);
3561 * XXX: high BATs are also present but are known to be bugged on
3565 env
->dcache_line_size
= 32;
3566 env
->icache_line_size
= 32;
3567 /* Allocate hardware IRQ controller */
3568 ppc6xx_irq_init(env_archcpu(env
));
3571 POWERPC_FAMILY(750)(ObjectClass
*oc
, void *data
)
3573 DeviceClass
*dc
= DEVICE_CLASS(oc
);
3574 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
3576 dc
->desc
= "PowerPC 750";
3577 pcc
->init_proc
= init_proc_750
;
3578 pcc
->check_pow
= check_pow_hid0
;
3579 pcc
->insns_flags
= PPC_INSNS_BASE
| PPC_STRING
| PPC_MFTB
|
3580 PPC_FLOAT
| PPC_FLOAT_FSEL
| PPC_FLOAT_FRES
|
3581 PPC_FLOAT_FRSQRTE
| PPC_FLOAT_STFIWX
|
3582 PPC_CACHE
| PPC_CACHE_ICBI
| PPC_CACHE_DCBZ
|
3583 PPC_MEM_SYNC
| PPC_MEM_EIEIO
|
3584 PPC_MEM_TLBIE
| PPC_MEM_TLBSYNC
|
3585 PPC_SEGMENT
| PPC_EXTERN
;
3586 pcc
->msr_mask
= (1ull << MSR_POW
) |
3602 pcc
->mmu_model
= POWERPC_MMU_32B
;
3603 pcc
->excp_model
= POWERPC_EXCP_7xx
;
3604 pcc
->bus_model
= PPC_FLAGS_INPUT_6xx
;
3605 pcc
->bfd_mach
= bfd_mach_ppc_750
;
3606 pcc
->flags
= POWERPC_FLAG_SE
| POWERPC_FLAG_BE
|
3607 POWERPC_FLAG_PMM
| POWERPC_FLAG_BUS_CLK
;
3610 static void init_proc_750cl(CPUPPCState
*env
)
3612 register_non_embedded_sprs(env
);
3613 register_sdr1_sprs(env
);
3614 register_7xx_sprs(env
);
3616 spr_register(env
, SPR_L2CR
, "L2CR",
3617 SPR_NOACCESS
, SPR_NOACCESS
,
3618 &spr_read_generic
, spr_access_nop
,
3620 /* Thermal management */
3621 /* Those registers are fake on 750CL */
3622 spr_register(env
, SPR_THRM1
, "THRM1",
3623 SPR_NOACCESS
, SPR_NOACCESS
,
3624 &spr_read_generic
, &spr_write_generic
,
3626 spr_register(env
, SPR_THRM2
, "THRM2",
3627 SPR_NOACCESS
, SPR_NOACCESS
,
3628 &spr_read_generic
, &spr_write_generic
,
3630 spr_register(env
, SPR_THRM3
, "THRM3",
3631 SPR_NOACCESS
, SPR_NOACCESS
,
3632 &spr_read_generic
, &spr_write_generic
,
3635 spr_register(env
, SPR_750_TDCL
, "TDCL",
3636 SPR_NOACCESS
, SPR_NOACCESS
,
3637 &spr_read_generic
, &spr_write_generic
,
3639 spr_register(env
, SPR_750_TDCH
, "TDCH",
3640 SPR_NOACCESS
, SPR_NOACCESS
,
3641 &spr_read_generic
, &spr_write_generic
,
3644 spr_register(env
, SPR_750_WPAR
, "WPAR",
3645 SPR_NOACCESS
, SPR_NOACCESS
,
3646 &spr_read_generic
, &spr_write_generic
,
3648 spr_register(env
, SPR_750_DMAL
, "DMAL",
3649 SPR_NOACCESS
, SPR_NOACCESS
,
3650 &spr_read_generic
, &spr_write_generic
,
3652 spr_register(env
, SPR_750_DMAU
, "DMAU",
3653 SPR_NOACCESS
, SPR_NOACCESS
,
3654 &spr_read_generic
, &spr_write_generic
,
3656 /* Hardware implementation registers */
3657 spr_register(env
, SPR_750CL_HID2
, "HID2",
3658 SPR_NOACCESS
, SPR_NOACCESS
,
3659 &spr_read_generic
, &spr_write_generic
,
3662 spr_register(env
, SPR_750CL_HID4
, "HID4",
3663 SPR_NOACCESS
, SPR_NOACCESS
,
3664 &spr_read_generic
, &spr_write_generic
,
3666 /* Quantization registers */
3667 spr_register(env
, SPR_750_GQR0
, "GQR0",
3668 SPR_NOACCESS
, SPR_NOACCESS
,
3669 &spr_read_generic
, &spr_write_generic
,
3672 spr_register(env
, SPR_750_GQR1
, "GQR1",
3673 SPR_NOACCESS
, SPR_NOACCESS
,
3674 &spr_read_generic
, &spr_write_generic
,
3677 spr_register(env
, SPR_750_GQR2
, "GQR2",
3678 SPR_NOACCESS
, SPR_NOACCESS
,
3679 &spr_read_generic
, &spr_write_generic
,
3682 spr_register(env
, SPR_750_GQR3
, "GQR3",
3683 SPR_NOACCESS
, SPR_NOACCESS
,
3684 &spr_read_generic
, &spr_write_generic
,
3687 spr_register(env
, SPR_750_GQR4
, "GQR4",
3688 SPR_NOACCESS
, SPR_NOACCESS
,
3689 &spr_read_generic
, &spr_write_generic
,
3692 spr_register(env
, SPR_750_GQR5
, "GQR5",
3693 SPR_NOACCESS
, SPR_NOACCESS
,
3694 &spr_read_generic
, &spr_write_generic
,
3697 spr_register(env
, SPR_750_GQR6
, "GQR6",
3698 SPR_NOACCESS
, SPR_NOACCESS
,
3699 &spr_read_generic
, &spr_write_generic
,
3702 spr_register(env
, SPR_750_GQR7
, "GQR7",
3703 SPR_NOACCESS
, SPR_NOACCESS
,
3704 &spr_read_generic
, &spr_write_generic
,
3706 /* Memory management */
3707 register_low_BATs(env
);
3708 /* PowerPC 750cl has 8 DBATs and 8 IBATs */
3709 register_high_BATs(env
);
3710 init_excp_750cl(env
);
3711 env
->dcache_line_size
= 32;
3712 env
->icache_line_size
= 32;
3713 /* Allocate hardware IRQ controller */
3714 ppc6xx_irq_init(env_archcpu(env
));
3717 POWERPC_FAMILY(750cl
)(ObjectClass
*oc
, void *data
)
3719 DeviceClass
*dc
= DEVICE_CLASS(oc
);
3720 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
3722 dc
->desc
= "PowerPC 750 CL";
3723 pcc
->init_proc
= init_proc_750cl
;
3724 pcc
->check_pow
= check_pow_hid0
;
3726 * XXX: not implemented:
3727 * cache lock instructions:
3729 * floating point paired instructions
3764 pcc
->insns_flags
= PPC_INSNS_BASE
| PPC_STRING
| PPC_MFTB
|
3765 PPC_FLOAT
| PPC_FLOAT_FSEL
| PPC_FLOAT_FRES
|
3766 PPC_FLOAT_FRSQRTE
| PPC_FLOAT_STFIWX
|
3767 PPC_CACHE
| PPC_CACHE_ICBI
| PPC_CACHE_DCBZ
|
3768 PPC_MEM_SYNC
| PPC_MEM_EIEIO
|
3769 PPC_MEM_TLBIE
| PPC_MEM_TLBSYNC
|
3770 PPC_SEGMENT
| PPC_EXTERN
;
3771 pcc
->msr_mask
= (1ull << MSR_POW
) |
3787 pcc
->mmu_model
= POWERPC_MMU_32B
;
3788 pcc
->excp_model
= POWERPC_EXCP_7xx
;
3789 pcc
->bus_model
= PPC_FLAGS_INPUT_6xx
;
3790 pcc
->bfd_mach
= bfd_mach_ppc_750
;
3791 pcc
->flags
= POWERPC_FLAG_SE
| POWERPC_FLAG_BE
|
3792 POWERPC_FLAG_PMM
| POWERPC_FLAG_BUS_CLK
;
3795 static void init_proc_750cx(CPUPPCState
*env
)
3797 register_non_embedded_sprs(env
);
3798 register_sdr1_sprs(env
);
3799 register_7xx_sprs(env
);
3801 spr_register(env
, SPR_L2CR
, "L2CR",
3802 SPR_NOACCESS
, SPR_NOACCESS
,
3803 &spr_read_generic
, spr_access_nop
,
3805 /* Thermal management */
3806 register_thrm_sprs(env
);
3808 spr_register(env
, SPR_SDA
, "SDA",
3809 SPR_NOACCESS
, SPR_NOACCESS
,
3810 &spr_read_generic
, &spr_write_generic
,
3813 /* Memory management */
3814 register_low_BATs(env
);
3815 /* PowerPC 750cx has 8 DBATs and 8 IBATs */
3816 register_high_BATs(env
);
3817 init_excp_750cx(env
);
3818 env
->dcache_line_size
= 32;
3819 env
->icache_line_size
= 32;
3820 /* Allocate hardware IRQ controller */
3821 ppc6xx_irq_init(env_archcpu(env
));
3824 POWERPC_FAMILY(750cx
)(ObjectClass
*oc
, void *data
)
3826 DeviceClass
*dc
= DEVICE_CLASS(oc
);
3827 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
3829 dc
->desc
= "PowerPC 750CX";
3830 pcc
->init_proc
= init_proc_750cx
;
3831 pcc
->check_pow
= check_pow_hid0
;
3832 pcc
->insns_flags
= PPC_INSNS_BASE
| PPC_STRING
| PPC_MFTB
|
3833 PPC_FLOAT
| PPC_FLOAT_FSEL
| PPC_FLOAT_FRES
|
3834 PPC_FLOAT_FRSQRTE
| PPC_FLOAT_STFIWX
|
3835 PPC_CACHE
| PPC_CACHE_ICBI
| PPC_CACHE_DCBZ
|
3836 PPC_MEM_SYNC
| PPC_MEM_EIEIO
|
3837 PPC_MEM_TLBIE
| PPC_MEM_TLBSYNC
|
3838 PPC_SEGMENT
| PPC_EXTERN
;
3839 pcc
->msr_mask
= (1ull << MSR_POW
) |
3855 pcc
->mmu_model
= POWERPC_MMU_32B
;
3856 pcc
->excp_model
= POWERPC_EXCP_7xx
;
3857 pcc
->bus_model
= PPC_FLAGS_INPUT_6xx
;
3858 pcc
->bfd_mach
= bfd_mach_ppc_750
;
3859 pcc
->flags
= POWERPC_FLAG_SE
| POWERPC_FLAG_BE
|
3860 POWERPC_FLAG_PMM
| POWERPC_FLAG_BUS_CLK
;
3863 static void init_proc_750fx(CPUPPCState
*env
)
3865 register_non_embedded_sprs(env
);
3866 register_sdr1_sprs(env
);
3867 register_7xx_sprs(env
);
3869 spr_register(env
, SPR_L2CR
, "L2CR",
3870 SPR_NOACCESS
, SPR_NOACCESS
,
3871 &spr_read_generic
, spr_access_nop
,
3873 /* Thermal management */
3874 register_thrm_sprs(env
);
3876 spr_register(env
, SPR_750_THRM4
, "THRM4",
3877 SPR_NOACCESS
, SPR_NOACCESS
,
3878 &spr_read_generic
, &spr_write_generic
,
3880 /* Hardware implementation registers */
3881 spr_register(env
, SPR_750FX_HID2
, "HID2",
3882 SPR_NOACCESS
, SPR_NOACCESS
,
3883 &spr_read_generic
, &spr_write_generic
,
3885 /* Memory management */
3886 register_low_BATs(env
);
3887 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
3888 register_high_BATs(env
);
3890 env
->dcache_line_size
= 32;
3891 env
->icache_line_size
= 32;
3892 /* Allocate hardware IRQ controller */
3893 ppc6xx_irq_init(env_archcpu(env
));
3896 POWERPC_FAMILY(750fx
)(ObjectClass
*oc
, void *data
)
3898 DeviceClass
*dc
= DEVICE_CLASS(oc
);
3899 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
3901 dc
->desc
= "PowerPC 750FX";
3902 pcc
->init_proc
= init_proc_750fx
;
3903 pcc
->check_pow
= check_pow_hid0
;
3904 pcc
->insns_flags
= PPC_INSNS_BASE
| PPC_STRING
| PPC_MFTB
|
3905 PPC_FLOAT
| PPC_FLOAT_FSEL
| PPC_FLOAT_FRES
|
3906 PPC_FLOAT_FRSQRTE
| PPC_FLOAT_STFIWX
|
3907 PPC_CACHE
| PPC_CACHE_ICBI
| PPC_CACHE_DCBZ
|
3908 PPC_MEM_SYNC
| PPC_MEM_EIEIO
|
3909 PPC_MEM_TLBIE
| PPC_MEM_TLBSYNC
|
3910 PPC_SEGMENT
| PPC_EXTERN
;
3911 pcc
->msr_mask
= (1ull << MSR_POW
) |
3927 pcc
->mmu_model
= POWERPC_MMU_32B
;
3928 pcc
->excp_model
= POWERPC_EXCP_7xx
;
3929 pcc
->bus_model
= PPC_FLAGS_INPUT_6xx
;
3930 pcc
->bfd_mach
= bfd_mach_ppc_750
;
3931 pcc
->flags
= POWERPC_FLAG_SE
| POWERPC_FLAG_BE
|
3932 POWERPC_FLAG_PMM
| POWERPC_FLAG_BUS_CLK
;
3935 static void init_proc_750gx(CPUPPCState
*env
)
3937 register_non_embedded_sprs(env
);
3938 register_sdr1_sprs(env
);
3939 register_7xx_sprs(env
);
3941 spr_register(env
, SPR_L2CR
, "L2CR",
3942 SPR_NOACCESS
, SPR_NOACCESS
,
3943 &spr_read_generic
, spr_access_nop
,
3945 /* Thermal management */
3946 register_thrm_sprs(env
);
3948 spr_register(env
, SPR_750_THRM4
, "THRM4",
3949 SPR_NOACCESS
, SPR_NOACCESS
,
3950 &spr_read_generic
, &spr_write_generic
,
3952 /* Hardware implementation registers */
3953 spr_register(env
, SPR_750FX_HID2
, "HID2",
3954 SPR_NOACCESS
, SPR_NOACCESS
,
3955 &spr_read_generic
, &spr_write_generic
,
3957 /* Memory management */
3958 register_low_BATs(env
);
3959 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
3960 register_high_BATs(env
);
3962 env
->dcache_line_size
= 32;
3963 env
->icache_line_size
= 32;
3964 /* Allocate hardware IRQ controller */
3965 ppc6xx_irq_init(env_archcpu(env
));
3968 POWERPC_FAMILY(750gx
)(ObjectClass
*oc
, void *data
)
3970 DeviceClass
*dc
= DEVICE_CLASS(oc
);
3971 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
3973 dc
->desc
= "PowerPC 750GX";
3974 pcc
->init_proc
= init_proc_750gx
;
3975 pcc
->check_pow
= check_pow_hid0
;
3976 pcc
->insns_flags
= PPC_INSNS_BASE
| PPC_STRING
| PPC_MFTB
|
3977 PPC_FLOAT
| PPC_FLOAT_FSEL
| PPC_FLOAT_FRES
|
3978 PPC_FLOAT_FRSQRTE
| PPC_FLOAT_STFIWX
|
3979 PPC_CACHE
| PPC_CACHE_ICBI
| PPC_CACHE_DCBZ
|
3980 PPC_MEM_SYNC
| PPC_MEM_EIEIO
|
3981 PPC_MEM_TLBIE
| PPC_MEM_TLBSYNC
|
3982 PPC_SEGMENT
| PPC_EXTERN
;
3983 pcc
->msr_mask
= (1ull << MSR_POW
) |
3999 pcc
->mmu_model
= POWERPC_MMU_32B
;
4000 pcc
->excp_model
= POWERPC_EXCP_7xx
;
4001 pcc
->bus_model
= PPC_FLAGS_INPUT_6xx
;
4002 pcc
->bfd_mach
= bfd_mach_ppc_750
;
4003 pcc
->flags
= POWERPC_FLAG_SE
| POWERPC_FLAG_BE
|
4004 POWERPC_FLAG_PMM
| POWERPC_FLAG_BUS_CLK
;
4007 static void init_proc_745(CPUPPCState
*env
)
4009 register_non_embedded_sprs(env
);
4010 register_sdr1_sprs(env
);
4011 register_7xx_sprs(env
);
4012 register_745_sprs(env
);
4013 /* Thermal management */
4014 register_thrm_sprs(env
);
4016 /* Memory management */
4017 register_low_BATs(env
);
4018 register_high_BATs(env
);
4019 register_6xx_7xx_soft_tlb(env
, 64, 2);
4021 env
->dcache_line_size
= 32;
4022 env
->icache_line_size
= 32;
4023 /* Allocate hardware IRQ controller */
4024 ppc6xx_irq_init(env_archcpu(env
));
4027 POWERPC_FAMILY(745)(ObjectClass
*oc
, void *data
)
4029 DeviceClass
*dc
= DEVICE_CLASS(oc
);
4030 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
4032 dc
->desc
= "PowerPC 745";
4033 pcc
->init_proc
= init_proc_745
;
4034 pcc
->check_pow
= check_pow_hid0
;
4035 pcc
->insns_flags
= PPC_INSNS_BASE
| PPC_STRING
| PPC_MFTB
|
4036 PPC_FLOAT
| PPC_FLOAT_FSEL
| PPC_FLOAT_FRES
|
4037 PPC_FLOAT_FRSQRTE
| PPC_FLOAT_STFIWX
|
4038 PPC_CACHE
| PPC_CACHE_ICBI
| PPC_CACHE_DCBZ
|
4039 PPC_MEM_SYNC
| PPC_MEM_EIEIO
|
4040 PPC_MEM_TLBIE
| PPC_MEM_TLBSYNC
| PPC_6xx_TLB
|
4041 PPC_SEGMENT
| PPC_EXTERN
;
4042 pcc
->msr_mask
= (1ull << MSR_POW
) |
4058 pcc
->mmu_model
= POWERPC_MMU_SOFT_6xx
;
4059 pcc
->excp_model
= POWERPC_EXCP_7xx
;
4060 pcc
->bus_model
= PPC_FLAGS_INPUT_6xx
;
4061 pcc
->bfd_mach
= bfd_mach_ppc_750
;
4062 pcc
->flags
= POWERPC_FLAG_SE
| POWERPC_FLAG_BE
|
4063 POWERPC_FLAG_PMM
| POWERPC_FLAG_BUS_CLK
;
4066 static void init_proc_755(CPUPPCState
*env
)
4069 register_755_sprs(env
);
4072 POWERPC_FAMILY(755)(ObjectClass
*oc
, void *data
)
4074 DeviceClass
*dc
= DEVICE_CLASS(oc
);
4075 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
4077 dc
->desc
= "PowerPC 755";
4078 pcc
->init_proc
= init_proc_755
;
4079 pcc
->check_pow
= check_pow_hid0
;
4080 pcc
->insns_flags
= PPC_INSNS_BASE
| PPC_STRING
| PPC_MFTB
|
4081 PPC_FLOAT
| PPC_FLOAT_FSEL
| PPC_FLOAT_FRES
|
4082 PPC_FLOAT_FRSQRTE
| PPC_FLOAT_STFIWX
|
4083 PPC_CACHE
| PPC_CACHE_ICBI
| PPC_CACHE_DCBZ
|
4084 PPC_MEM_SYNC
| PPC_MEM_EIEIO
|
4085 PPC_MEM_TLBIE
| PPC_MEM_TLBSYNC
| PPC_6xx_TLB
|
4086 PPC_SEGMENT
| PPC_EXTERN
;
4087 pcc
->msr_mask
= (1ull << MSR_POW
) |
4103 pcc
->mmu_model
= POWERPC_MMU_SOFT_6xx
;
4104 pcc
->excp_model
= POWERPC_EXCP_7xx
;
4105 pcc
->bus_model
= PPC_FLAGS_INPUT_6xx
;
4106 pcc
->bfd_mach
= bfd_mach_ppc_750
;
4107 pcc
->flags
= POWERPC_FLAG_SE
| POWERPC_FLAG_BE
|
4108 POWERPC_FLAG_PMM
| POWERPC_FLAG_BUS_CLK
;
4111 static void init_proc_7400(CPUPPCState
*env
)
4113 register_non_embedded_sprs(env
);
4114 register_sdr1_sprs(env
);
4115 register_74xx_sprs(env
);
4116 vscr_init(env
, 0x00010000);
4118 spr_register(env
, SPR_UBAMR
, "UBAMR",
4119 &spr_read_ureg
, SPR_NOACCESS
,
4120 &spr_read_ureg
, SPR_NOACCESS
,
4123 spr_register(env
, SPR_MSSCR1
, "MSSCR1",
4124 SPR_NOACCESS
, SPR_NOACCESS
,
4125 &spr_read_generic
, &spr_write_generic
,
4127 /* Thermal management */
4128 register_thrm_sprs(env
);
4129 /* Memory management */
4130 register_low_BATs(env
);
4131 init_excp_7400(env
);
4132 env
->dcache_line_size
= 32;
4133 env
->icache_line_size
= 32;
4134 /* Allocate hardware IRQ controller */
4135 ppc6xx_irq_init(env_archcpu(env
));
4138 POWERPC_FAMILY(7400)(ObjectClass
*oc
, void *data
)
4140 DeviceClass
*dc
= DEVICE_CLASS(oc
);
4141 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
4143 dc
->desc
= "PowerPC 7400 (aka G4)";
4144 pcc
->init_proc
= init_proc_7400
;
4145 pcc
->check_pow
= check_pow_hid0
;
4146 pcc
->insns_flags
= PPC_INSNS_BASE
| PPC_STRING
| PPC_MFTB
|
4147 PPC_FLOAT
| PPC_FLOAT_FSEL
| PPC_FLOAT_FRES
|
4148 PPC_FLOAT_FSQRT
| PPC_FLOAT_FRSQRTE
|
4150 PPC_CACHE
| PPC_CACHE_ICBI
|
4151 PPC_CACHE_DCBA
| PPC_CACHE_DCBZ
|
4152 PPC_MEM_SYNC
| PPC_MEM_EIEIO
|
4153 PPC_MEM_TLBIE
| PPC_MEM_TLBSYNC
|
4155 PPC_SEGMENT
| PPC_EXTERN
|
4157 pcc
->msr_mask
= (1ull << MSR_VR
) |
4174 pcc
->mmu_model
= POWERPC_MMU_32B
;
4175 pcc
->excp_model
= POWERPC_EXCP_74xx
;
4176 pcc
->bus_model
= PPC_FLAGS_INPUT_6xx
;
4177 pcc
->bfd_mach
= bfd_mach_ppc_7400
;
4178 pcc
->flags
= POWERPC_FLAG_VRE
| POWERPC_FLAG_SE
|
4179 POWERPC_FLAG_BE
| POWERPC_FLAG_PMM
|
4180 POWERPC_FLAG_BUS_CLK
;
4183 static void init_proc_7410(CPUPPCState
*env
)
4185 register_non_embedded_sprs(env
);
4186 register_sdr1_sprs(env
);
4187 register_74xx_sprs(env
);
4188 vscr_init(env
, 0x00010000);
4190 spr_register(env
, SPR_UBAMR
, "UBAMR",
4191 &spr_read_ureg
, SPR_NOACCESS
,
4192 &spr_read_ureg
, SPR_NOACCESS
,
4194 /* Thermal management */
4195 register_thrm_sprs(env
);
4198 spr_register(env
, SPR_L2PMCR
, "L2PMCR",
4199 SPR_NOACCESS
, SPR_NOACCESS
,
4200 &spr_read_generic
, &spr_write_generic
,
4204 spr_register(env
, SPR_LDSTDB
, "LDSTDB",
4205 SPR_NOACCESS
, SPR_NOACCESS
,
4206 &spr_read_generic
, &spr_write_generic
,
4208 /* Memory management */
4209 register_low_BATs(env
);
4210 init_excp_7400(env
);
4211 env
->dcache_line_size
= 32;
4212 env
->icache_line_size
= 32;
4213 /* Allocate hardware IRQ controller */
4214 ppc6xx_irq_init(env_archcpu(env
));
4217 POWERPC_FAMILY(7410)(ObjectClass
*oc
, void *data
)
4219 DeviceClass
*dc
= DEVICE_CLASS(oc
);
4220 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
4222 dc
->desc
= "PowerPC 7410 (aka G4)";
4223 pcc
->init_proc
= init_proc_7410
;
4224 pcc
->check_pow
= check_pow_hid0
;
4225 pcc
->insns_flags
= PPC_INSNS_BASE
| PPC_STRING
| PPC_MFTB
|
4226 PPC_FLOAT
| PPC_FLOAT_FSEL
| PPC_FLOAT_FRES
|
4227 PPC_FLOAT_FSQRT
| PPC_FLOAT_FRSQRTE
|
4229 PPC_CACHE
| PPC_CACHE_ICBI
|
4230 PPC_CACHE_DCBA
| PPC_CACHE_DCBZ
|
4231 PPC_MEM_SYNC
| PPC_MEM_EIEIO
|
4232 PPC_MEM_TLBIE
| PPC_MEM_TLBSYNC
|
4234 PPC_SEGMENT
| PPC_EXTERN
|
4236 pcc
->msr_mask
= (1ull << MSR_VR
) |
4253 pcc
->mmu_model
= POWERPC_MMU_32B
;
4254 pcc
->excp_model
= POWERPC_EXCP_74xx
;
4255 pcc
->bus_model
= PPC_FLAGS_INPUT_6xx
;
4256 pcc
->bfd_mach
= bfd_mach_ppc_7400
;
4257 pcc
->flags
= POWERPC_FLAG_VRE
| POWERPC_FLAG_SE
|
4258 POWERPC_FLAG_BE
| POWERPC_FLAG_PMM
|
4259 POWERPC_FLAG_BUS_CLK
;
4262 static void init_proc_7440(CPUPPCState
*env
)
4264 register_non_embedded_sprs(env
);
4265 register_sdr1_sprs(env
);
4266 register_74xx_sprs(env
);
4267 vscr_init(env
, 0x00010000);
4269 spr_register(env
, SPR_UBAMR
, "UBAMR",
4270 &spr_read_ureg
, SPR_NOACCESS
,
4271 &spr_read_ureg
, SPR_NOACCESS
,
4274 spr_register(env
, SPR_LDSTCR
, "LDSTCR",
4275 SPR_NOACCESS
, SPR_NOACCESS
,
4276 &spr_read_generic
, &spr_write_generic
,
4279 spr_register(env
, SPR_ICTRL
, "ICTRL",
4280 SPR_NOACCESS
, SPR_NOACCESS
,
4281 &spr_read_generic
, &spr_write_generic
,
4284 spr_register(env
, SPR_MSSSR0
, "MSSSR0",
4285 SPR_NOACCESS
, SPR_NOACCESS
,
4286 &spr_read_generic
, &spr_write_generic
,
4289 spr_register(env
, SPR_7XX_PMC5
, "PMC5",
4290 SPR_NOACCESS
, SPR_NOACCESS
,
4291 &spr_read_generic
, &spr_write_generic
,
4294 spr_register(env
, SPR_7XX_UPMC5
, "UPMC5",
4295 &spr_read_ureg
, SPR_NOACCESS
,
4296 &spr_read_ureg
, SPR_NOACCESS
,
4299 spr_register(env
, SPR_7XX_PMC6
, "PMC6",
4300 SPR_NOACCESS
, SPR_NOACCESS
,
4301 &spr_read_generic
, &spr_write_generic
,
4304 spr_register(env
, SPR_7XX_UPMC6
, "UPMC6",
4305 &spr_read_ureg
, SPR_NOACCESS
,
4306 &spr_read_ureg
, SPR_NOACCESS
,
4308 /* Memory management */
4309 register_low_BATs(env
);
4310 init_excp_7450(env
);
4311 env
->dcache_line_size
= 32;
4312 env
->icache_line_size
= 32;
4313 /* Allocate hardware IRQ controller */
4314 ppc6xx_irq_init(env_archcpu(env
));
4317 POWERPC_FAMILY(7440)(ObjectClass
*oc
, void *data
)
4319 DeviceClass
*dc
= DEVICE_CLASS(oc
);
4320 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
4322 dc
->desc
= "PowerPC 7440 (aka G4)";
4323 pcc
->init_proc
= init_proc_7440
;
4324 pcc
->check_pow
= check_pow_hid0_74xx
;
4325 pcc
->insns_flags
= PPC_INSNS_BASE
| PPC_STRING
| PPC_MFTB
|
4326 PPC_FLOAT
| PPC_FLOAT_FSEL
| PPC_FLOAT_FRES
|
4327 PPC_FLOAT_FSQRT
| PPC_FLOAT_FRSQRTE
|
4329 PPC_CACHE
| PPC_CACHE_ICBI
|
4330 PPC_CACHE_DCBA
| PPC_CACHE_DCBZ
|
4331 PPC_MEM_SYNC
| PPC_MEM_EIEIO
|
4332 PPC_MEM_TLBIE
| PPC_MEM_TLBSYNC
|
4334 PPC_SEGMENT
| PPC_EXTERN
|
4336 pcc
->msr_mask
= (1ull << MSR_VR
) |
4353 pcc
->mmu_model
= POWERPC_MMU_32B
;
4354 pcc
->excp_model
= POWERPC_EXCP_74xx
;
4355 pcc
->bus_model
= PPC_FLAGS_INPUT_6xx
;
4356 pcc
->bfd_mach
= bfd_mach_ppc_7400
;
4357 pcc
->flags
= POWERPC_FLAG_VRE
| POWERPC_FLAG_SE
|
4358 POWERPC_FLAG_BE
| POWERPC_FLAG_PMM
|
4359 POWERPC_FLAG_BUS_CLK
;
4362 static void init_proc_7450(CPUPPCState
*env
)
4364 register_non_embedded_sprs(env
);
4365 register_sdr1_sprs(env
);
4366 register_74xx_sprs(env
);
4367 vscr_init(env
, 0x00010000);
4368 /* Level 3 cache control */
4369 register_l3_ctrl(env
);
4371 spr_register(env
, SPR_L3ITCR1
, "L3ITCR1",
4372 SPR_NOACCESS
, SPR_NOACCESS
,
4373 &spr_read_generic
, &spr_write_generic
,
4376 spr_register(env
, SPR_L3ITCR2
, "L3ITCR2",
4377 SPR_NOACCESS
, SPR_NOACCESS
,
4378 &spr_read_generic
, &spr_write_generic
,
4381 spr_register(env
, SPR_L3ITCR3
, "L3ITCR3",
4382 SPR_NOACCESS
, SPR_NOACCESS
,
4383 &spr_read_generic
, &spr_write_generic
,
4386 spr_register(env
, SPR_L3OHCR
, "L3OHCR",
4387 SPR_NOACCESS
, SPR_NOACCESS
,
4388 &spr_read_generic
, &spr_write_generic
,
4391 spr_register(env
, SPR_UBAMR
, "UBAMR",
4392 &spr_read_ureg
, SPR_NOACCESS
,
4393 &spr_read_ureg
, SPR_NOACCESS
,
4396 spr_register(env
, SPR_LDSTCR
, "LDSTCR",
4397 SPR_NOACCESS
, SPR_NOACCESS
,
4398 &spr_read_generic
, &spr_write_generic
,
4401 spr_register(env
, SPR_ICTRL
, "ICTRL",
4402 SPR_NOACCESS
, SPR_NOACCESS
,
4403 &spr_read_generic
, &spr_write_generic
,
4406 spr_register(env
, SPR_MSSSR0
, "MSSSR0",
4407 SPR_NOACCESS
, SPR_NOACCESS
,
4408 &spr_read_generic
, &spr_write_generic
,
4411 spr_register(env
, SPR_7XX_PMC5
, "PMC5",
4412 SPR_NOACCESS
, SPR_NOACCESS
,
4413 &spr_read_generic
, &spr_write_generic
,
4416 spr_register(env
, SPR_7XX_UPMC5
, "UPMC5",
4417 &spr_read_ureg
, SPR_NOACCESS
,
4418 &spr_read_ureg
, SPR_NOACCESS
,
4421 spr_register(env
, SPR_7XX_PMC6
, "PMC6",
4422 SPR_NOACCESS
, SPR_NOACCESS
,
4423 &spr_read_generic
, &spr_write_generic
,
4426 spr_register(env
, SPR_7XX_UPMC6
, "UPMC6",
4427 &spr_read_ureg
, SPR_NOACCESS
,
4428 &spr_read_ureg
, SPR_NOACCESS
,
4430 /* Memory management */
4431 register_low_BATs(env
);
4432 init_excp_7450(env
);
4433 env
->dcache_line_size
= 32;
4434 env
->icache_line_size
= 32;
4435 /* Allocate hardware IRQ controller */
4436 ppc6xx_irq_init(env_archcpu(env
));
4439 POWERPC_FAMILY(7450)(ObjectClass
*oc
, void *data
)
4441 DeviceClass
*dc
= DEVICE_CLASS(oc
);
4442 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
4444 dc
->desc
= "PowerPC 7450 (aka G4)";
4445 pcc
->init_proc
= init_proc_7450
;
4446 pcc
->check_pow
= check_pow_hid0_74xx
;
4447 pcc
->insns_flags
= PPC_INSNS_BASE
| PPC_STRING
| PPC_MFTB
|
4448 PPC_FLOAT
| PPC_FLOAT_FSEL
| PPC_FLOAT_FRES
|
4449 PPC_FLOAT_FSQRT
| PPC_FLOAT_FRSQRTE
|
4451 PPC_CACHE
| PPC_CACHE_ICBI
|
4452 PPC_CACHE_DCBA
| PPC_CACHE_DCBZ
|
4453 PPC_MEM_SYNC
| PPC_MEM_EIEIO
|
4454 PPC_MEM_TLBIE
| PPC_MEM_TLBSYNC
|
4456 PPC_SEGMENT
| PPC_EXTERN
|
4458 pcc
->msr_mask
= (1ull << MSR_VR
) |
4475 pcc
->mmu_model
= POWERPC_MMU_32B
;
4476 pcc
->excp_model
= POWERPC_EXCP_74xx
;
4477 pcc
->bus_model
= PPC_FLAGS_INPUT_6xx
;
4478 pcc
->bfd_mach
= bfd_mach_ppc_7400
;
4479 pcc
->flags
= POWERPC_FLAG_VRE
| POWERPC_FLAG_SE
|
4480 POWERPC_FLAG_BE
| POWERPC_FLAG_PMM
|
4481 POWERPC_FLAG_BUS_CLK
;
4484 static void init_proc_7445(CPUPPCState
*env
)
4486 register_non_embedded_sprs(env
);
4487 register_sdr1_sprs(env
);
4488 register_74xx_sprs(env
);
4489 vscr_init(env
, 0x00010000);
4491 spr_register(env
, SPR_LDSTCR
, "LDSTCR",
4492 SPR_NOACCESS
, SPR_NOACCESS
,
4493 &spr_read_generic
, &spr_write_generic
,
4496 spr_register(env
, SPR_ICTRL
, "ICTRL",
4497 SPR_NOACCESS
, SPR_NOACCESS
,
4498 &spr_read_generic
, &spr_write_generic
,
4501 spr_register(env
, SPR_MSSSR0
, "MSSSR0",
4502 SPR_NOACCESS
, SPR_NOACCESS
,
4503 &spr_read_generic
, &spr_write_generic
,
4506 spr_register(env
, SPR_7XX_PMC5
, "PMC5",
4507 SPR_NOACCESS
, SPR_NOACCESS
,
4508 &spr_read_generic
, &spr_write_generic
,
4511 spr_register(env
, SPR_7XX_UPMC5
, "UPMC5",
4512 &spr_read_ureg
, SPR_NOACCESS
,
4513 &spr_read_ureg
, SPR_NOACCESS
,
4516 spr_register(env
, SPR_7XX_PMC6
, "PMC6",
4517 SPR_NOACCESS
, SPR_NOACCESS
,
4518 &spr_read_generic
, &spr_write_generic
,
4521 spr_register(env
, SPR_7XX_UPMC6
, "UPMC6",
4522 &spr_read_ureg
, SPR_NOACCESS
,
4523 &spr_read_ureg
, SPR_NOACCESS
,
4526 spr_register(env
, SPR_SPRG4
, "SPRG4",
4527 SPR_NOACCESS
, SPR_NOACCESS
,
4528 &spr_read_generic
, &spr_write_generic
,
4530 spr_register(env
, SPR_USPRG4
, "USPRG4",
4531 &spr_read_ureg
, SPR_NOACCESS
,
4532 &spr_read_ureg
, SPR_NOACCESS
,
4534 spr_register(env
, SPR_SPRG5
, "SPRG5",
4535 SPR_NOACCESS
, SPR_NOACCESS
,
4536 &spr_read_generic
, &spr_write_generic
,
4538 spr_register(env
, SPR_USPRG5
, "USPRG5",
4539 &spr_read_ureg
, SPR_NOACCESS
,
4540 &spr_read_ureg
, SPR_NOACCESS
,
4542 spr_register(env
, SPR_SPRG6
, "SPRG6",
4543 SPR_NOACCESS
, SPR_NOACCESS
,
4544 &spr_read_generic
, &spr_write_generic
,
4546 spr_register(env
, SPR_USPRG6
, "USPRG6",
4547 &spr_read_ureg
, SPR_NOACCESS
,
4548 &spr_read_ureg
, SPR_NOACCESS
,
4550 spr_register(env
, SPR_SPRG7
, "SPRG7",
4551 SPR_NOACCESS
, SPR_NOACCESS
,
4552 &spr_read_generic
, &spr_write_generic
,
4554 spr_register(env
, SPR_USPRG7
, "USPRG7",
4555 &spr_read_ureg
, SPR_NOACCESS
,
4556 &spr_read_ureg
, SPR_NOACCESS
,
4558 /* Memory management */
4559 register_low_BATs(env
);
4560 register_high_BATs(env
);
4561 init_excp_7450(env
);
4562 env
->dcache_line_size
= 32;
4563 env
->icache_line_size
= 32;
4564 /* Allocate hardware IRQ controller */
4565 ppc6xx_irq_init(env_archcpu(env
));
4568 POWERPC_FAMILY(7445)(ObjectClass
*oc
, void *data
)
4570 DeviceClass
*dc
= DEVICE_CLASS(oc
);
4571 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
4573 dc
->desc
= "PowerPC 7445 (aka G4)";
4574 pcc
->init_proc
= init_proc_7445
;
4575 pcc
->check_pow
= check_pow_hid0_74xx
;
4576 pcc
->insns_flags
= PPC_INSNS_BASE
| PPC_STRING
| PPC_MFTB
|
4577 PPC_FLOAT
| PPC_FLOAT_FSEL
| PPC_FLOAT_FRES
|
4578 PPC_FLOAT_FSQRT
| PPC_FLOAT_FRSQRTE
|
4580 PPC_CACHE
| PPC_CACHE_ICBI
|
4581 PPC_CACHE_DCBA
| PPC_CACHE_DCBZ
|
4582 PPC_MEM_SYNC
| PPC_MEM_EIEIO
|
4583 PPC_MEM_TLBIE
| PPC_MEM_TLBSYNC
|
4585 PPC_SEGMENT
| PPC_EXTERN
|
4587 pcc
->msr_mask
= (1ull << MSR_VR
) |
4604 pcc
->mmu_model
= POWERPC_MMU_32B
;
4605 pcc
->excp_model
= POWERPC_EXCP_74xx
;
4606 pcc
->bus_model
= PPC_FLAGS_INPUT_6xx
;
4607 pcc
->bfd_mach
= bfd_mach_ppc_7400
;
4608 pcc
->flags
= POWERPC_FLAG_VRE
| POWERPC_FLAG_SE
|
4609 POWERPC_FLAG_BE
| POWERPC_FLAG_PMM
|
4610 POWERPC_FLAG_BUS_CLK
;
4613 static void init_proc_7455(CPUPPCState
*env
)
4615 register_non_embedded_sprs(env
);
4616 register_sdr1_sprs(env
);
4617 register_74xx_sprs(env
);
4618 vscr_init(env
, 0x00010000);
4619 /* Level 3 cache control */
4620 register_l3_ctrl(env
);
4622 spr_register(env
, SPR_LDSTCR
, "LDSTCR",
4623 SPR_NOACCESS
, SPR_NOACCESS
,
4624 &spr_read_generic
, &spr_write_generic
,
4627 spr_register(env
, SPR_ICTRL
, "ICTRL",
4628 SPR_NOACCESS
, SPR_NOACCESS
,
4629 &spr_read_generic
, &spr_write_generic
,
4632 spr_register(env
, SPR_MSSSR0
, "MSSSR0",
4633 SPR_NOACCESS
, SPR_NOACCESS
,
4634 &spr_read_generic
, &spr_write_generic
,
4637 spr_register(env
, SPR_7XX_PMC5
, "PMC5",
4638 SPR_NOACCESS
, SPR_NOACCESS
,
4639 &spr_read_generic
, &spr_write_generic
,
4642 spr_register(env
, SPR_7XX_UPMC5
, "UPMC5",
4643 &spr_read_ureg
, SPR_NOACCESS
,
4644 &spr_read_ureg
, SPR_NOACCESS
,
4647 spr_register(env
, SPR_7XX_PMC6
, "PMC6",
4648 SPR_NOACCESS
, SPR_NOACCESS
,
4649 &spr_read_generic
, &spr_write_generic
,
4652 spr_register(env
, SPR_7XX_UPMC6
, "UPMC6",
4653 &spr_read_ureg
, SPR_NOACCESS
,
4654 &spr_read_ureg
, SPR_NOACCESS
,
4657 spr_register(env
, SPR_SPRG4
, "SPRG4",
4658 SPR_NOACCESS
, SPR_NOACCESS
,
4659 &spr_read_generic
, &spr_write_generic
,
4661 spr_register(env
, SPR_USPRG4
, "USPRG4",
4662 &spr_read_ureg
, SPR_NOACCESS
,
4663 &spr_read_ureg
, SPR_NOACCESS
,
4665 spr_register(env
, SPR_SPRG5
, "SPRG5",
4666 SPR_NOACCESS
, SPR_NOACCESS
,
4667 &spr_read_generic
, &spr_write_generic
,
4669 spr_register(env
, SPR_USPRG5
, "USPRG5",
4670 &spr_read_ureg
, SPR_NOACCESS
,
4671 &spr_read_ureg
, SPR_NOACCESS
,
4673 spr_register(env
, SPR_SPRG6
, "SPRG6",
4674 SPR_NOACCESS
, SPR_NOACCESS
,
4675 &spr_read_generic
, &spr_write_generic
,
4677 spr_register(env
, SPR_USPRG6
, "USPRG6",
4678 &spr_read_ureg
, SPR_NOACCESS
,
4679 &spr_read_ureg
, SPR_NOACCESS
,
4681 spr_register(env
, SPR_SPRG7
, "SPRG7",
4682 SPR_NOACCESS
, SPR_NOACCESS
,
4683 &spr_read_generic
, &spr_write_generic
,
4685 spr_register(env
, SPR_USPRG7
, "USPRG7",
4686 &spr_read_ureg
, SPR_NOACCESS
,
4687 &spr_read_ureg
, SPR_NOACCESS
,
4689 /* Memory management */
4690 register_low_BATs(env
);
4691 register_high_BATs(env
);
4692 init_excp_7450(env
);
4693 env
->dcache_line_size
= 32;
4694 env
->icache_line_size
= 32;
4695 /* Allocate hardware IRQ controller */
4696 ppc6xx_irq_init(env_archcpu(env
));
4699 POWERPC_FAMILY(7455)(ObjectClass
*oc
, void *data
)
4701 DeviceClass
*dc
= DEVICE_CLASS(oc
);
4702 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
4704 dc
->desc
= "PowerPC 7455 (aka G4)";
4705 pcc
->init_proc
= init_proc_7455
;
4706 pcc
->check_pow
= check_pow_hid0_74xx
;
4707 pcc
->insns_flags
= PPC_INSNS_BASE
| PPC_STRING
| PPC_MFTB
|
4708 PPC_FLOAT
| PPC_FLOAT_FSEL
| PPC_FLOAT_FRES
|
4709 PPC_FLOAT_FSQRT
| PPC_FLOAT_FRSQRTE
|
4711 PPC_CACHE
| PPC_CACHE_ICBI
|
4712 PPC_CACHE_DCBA
| PPC_CACHE_DCBZ
|
4713 PPC_MEM_SYNC
| PPC_MEM_EIEIO
|
4714 PPC_MEM_TLBIE
| PPC_MEM_TLBSYNC
|
4716 PPC_SEGMENT
| PPC_EXTERN
|
4718 pcc
->msr_mask
= (1ull << MSR_VR
) |
4735 pcc
->mmu_model
= POWERPC_MMU_32B
;
4736 pcc
->excp_model
= POWERPC_EXCP_74xx
;
4737 pcc
->bus_model
= PPC_FLAGS_INPUT_6xx
;
4738 pcc
->bfd_mach
= bfd_mach_ppc_7400
;
4739 pcc
->flags
= POWERPC_FLAG_VRE
| POWERPC_FLAG_SE
|
4740 POWERPC_FLAG_BE
| POWERPC_FLAG_PMM
|
4741 POWERPC_FLAG_BUS_CLK
;
4744 static void init_proc_7457(CPUPPCState
*env
)
4746 register_non_embedded_sprs(env
);
4747 register_sdr1_sprs(env
);
4748 register_74xx_sprs(env
);
4749 vscr_init(env
, 0x00010000);
4750 /* Level 3 cache control */
4751 register_l3_ctrl(env
);
4753 spr_register(env
, SPR_L3ITCR1
, "L3ITCR1",
4754 SPR_NOACCESS
, SPR_NOACCESS
,
4755 &spr_read_generic
, &spr_write_generic
,
4758 spr_register(env
, SPR_L3ITCR2
, "L3ITCR2",
4759 SPR_NOACCESS
, SPR_NOACCESS
,
4760 &spr_read_generic
, &spr_write_generic
,
4763 spr_register(env
, SPR_L3ITCR3
, "L3ITCR3",
4764 SPR_NOACCESS
, SPR_NOACCESS
,
4765 &spr_read_generic
, &spr_write_generic
,
4768 spr_register(env
, SPR_L3OHCR
, "L3OHCR",
4769 SPR_NOACCESS
, SPR_NOACCESS
,
4770 &spr_read_generic
, &spr_write_generic
,
4773 spr_register(env
, SPR_LDSTCR
, "LDSTCR",
4774 SPR_NOACCESS
, SPR_NOACCESS
,
4775 &spr_read_generic
, &spr_write_generic
,
4778 spr_register(env
, SPR_ICTRL
, "ICTRL",
4779 SPR_NOACCESS
, SPR_NOACCESS
,
4780 &spr_read_generic
, &spr_write_generic
,
4783 spr_register(env
, SPR_MSSSR0
, "MSSSR0",
4784 SPR_NOACCESS
, SPR_NOACCESS
,
4785 &spr_read_generic
, &spr_write_generic
,
4788 spr_register(env
, SPR_7XX_PMC5
, "PMC5",
4789 SPR_NOACCESS
, SPR_NOACCESS
,
4790 &spr_read_generic
, &spr_write_generic
,
4793 spr_register(env
, SPR_7XX_UPMC5
, "UPMC5",
4794 &spr_read_ureg
, SPR_NOACCESS
,
4795 &spr_read_ureg
, SPR_NOACCESS
,
4798 spr_register(env
, SPR_7XX_PMC6
, "PMC6",
4799 SPR_NOACCESS
, SPR_NOACCESS
,
4800 &spr_read_generic
, &spr_write_generic
,
4803 spr_register(env
, SPR_7XX_UPMC6
, "UPMC6",
4804 &spr_read_ureg
, SPR_NOACCESS
,
4805 &spr_read_ureg
, SPR_NOACCESS
,
4808 spr_register(env
, SPR_SPRG4
, "SPRG4",
4809 SPR_NOACCESS
, SPR_NOACCESS
,
4810 &spr_read_generic
, &spr_write_generic
,
4812 spr_register(env
, SPR_USPRG4
, "USPRG4",
4813 &spr_read_ureg
, SPR_NOACCESS
,
4814 &spr_read_ureg
, SPR_NOACCESS
,
4816 spr_register(env
, SPR_SPRG5
, "SPRG5",
4817 SPR_NOACCESS
, SPR_NOACCESS
,
4818 &spr_read_generic
, &spr_write_generic
,
4820 spr_register(env
, SPR_USPRG5
, "USPRG5",
4821 &spr_read_ureg
, SPR_NOACCESS
,
4822 &spr_read_ureg
, SPR_NOACCESS
,
4824 spr_register(env
, SPR_SPRG6
, "SPRG6",
4825 SPR_NOACCESS
, SPR_NOACCESS
,
4826 &spr_read_generic
, &spr_write_generic
,
4828 spr_register(env
, SPR_USPRG6
, "USPRG6",
4829 &spr_read_ureg
, SPR_NOACCESS
,
4830 &spr_read_ureg
, SPR_NOACCESS
,
4832 spr_register(env
, SPR_SPRG7
, "SPRG7",
4833 SPR_NOACCESS
, SPR_NOACCESS
,
4834 &spr_read_generic
, &spr_write_generic
,
4836 spr_register(env
, SPR_USPRG7
, "USPRG7",
4837 &spr_read_ureg
, SPR_NOACCESS
,
4838 &spr_read_ureg
, SPR_NOACCESS
,
4840 /* Memory management */
4841 register_low_BATs(env
);
4842 register_high_BATs(env
);
4843 init_excp_7450(env
);
4844 env
->dcache_line_size
= 32;
4845 env
->icache_line_size
= 32;
4846 /* Allocate hardware IRQ controller */
4847 ppc6xx_irq_init(env_archcpu(env
));
4850 POWERPC_FAMILY(7457)(ObjectClass
*oc
, void *data
)
4852 DeviceClass
*dc
= DEVICE_CLASS(oc
);
4853 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
4855 dc
->desc
= "PowerPC 7457 (aka G4)";
4856 pcc
->init_proc
= init_proc_7457
;
4857 pcc
->check_pow
= check_pow_hid0_74xx
;
4858 pcc
->insns_flags
= PPC_INSNS_BASE
| PPC_STRING
| PPC_MFTB
|
4859 PPC_FLOAT
| PPC_FLOAT_FSEL
| PPC_FLOAT_FRES
|
4860 PPC_FLOAT_FSQRT
| PPC_FLOAT_FRSQRTE
|
4862 PPC_CACHE
| PPC_CACHE_ICBI
|
4863 PPC_CACHE_DCBA
| PPC_CACHE_DCBZ
|
4864 PPC_MEM_SYNC
| PPC_MEM_EIEIO
|
4865 PPC_MEM_TLBIE
| PPC_MEM_TLBSYNC
|
4867 PPC_SEGMENT
| PPC_EXTERN
|
4869 pcc
->msr_mask
= (1ull << MSR_VR
) |
4886 pcc
->mmu_model
= POWERPC_MMU_32B
;
4887 pcc
->excp_model
= POWERPC_EXCP_74xx
;
4888 pcc
->bus_model
= PPC_FLAGS_INPUT_6xx
;
4889 pcc
->bfd_mach
= bfd_mach_ppc_7400
;
4890 pcc
->flags
= POWERPC_FLAG_VRE
| POWERPC_FLAG_SE
|
4891 POWERPC_FLAG_BE
| POWERPC_FLAG_PMM
|
4892 POWERPC_FLAG_BUS_CLK
;
4895 static void init_proc_e600(CPUPPCState
*env
)
4897 register_non_embedded_sprs(env
);
4898 register_sdr1_sprs(env
);
4899 register_74xx_sprs(env
);
4900 vscr_init(env
, 0x00010000);
4902 spr_register(env
, SPR_UBAMR
, "UBAMR",
4903 &spr_read_ureg
, SPR_NOACCESS
,
4904 &spr_read_ureg
, SPR_NOACCESS
,
4907 spr_register(env
, SPR_LDSTCR
, "LDSTCR",
4908 SPR_NOACCESS
, SPR_NOACCESS
,
4909 &spr_read_generic
, &spr_write_generic
,
4912 spr_register(env
, SPR_ICTRL
, "ICTRL",
4913 SPR_NOACCESS
, SPR_NOACCESS
,
4914 &spr_read_generic
, &spr_write_generic
,
4917 spr_register(env
, SPR_MSSSR0
, "MSSSR0",
4918 SPR_NOACCESS
, SPR_NOACCESS
,
4919 &spr_read_generic
, &spr_write_generic
,
4922 spr_register(env
, SPR_7XX_PMC5
, "PMC5",
4923 SPR_NOACCESS
, SPR_NOACCESS
,
4924 &spr_read_generic
, &spr_write_generic
,
4927 spr_register(env
, SPR_7XX_UPMC5
, "UPMC5",
4928 &spr_read_ureg
, SPR_NOACCESS
,
4929 &spr_read_ureg
, SPR_NOACCESS
,
4932 spr_register(env
, SPR_7XX_PMC6
, "PMC6",
4933 SPR_NOACCESS
, SPR_NOACCESS
,
4934 &spr_read_generic
, &spr_write_generic
,
4937 spr_register(env
, SPR_7XX_UPMC6
, "UPMC6",
4938 &spr_read_ureg
, SPR_NOACCESS
,
4939 &spr_read_ureg
, SPR_NOACCESS
,
4942 spr_register(env
, SPR_SPRG4
, "SPRG4",
4943 SPR_NOACCESS
, SPR_NOACCESS
,
4944 &spr_read_generic
, &spr_write_generic
,
4946 spr_register(env
, SPR_USPRG4
, "USPRG4",
4947 &spr_read_ureg
, SPR_NOACCESS
,
4948 &spr_read_ureg
, SPR_NOACCESS
,
4950 spr_register(env
, SPR_SPRG5
, "SPRG5",
4951 SPR_NOACCESS
, SPR_NOACCESS
,
4952 &spr_read_generic
, &spr_write_generic
,
4954 spr_register(env
, SPR_USPRG5
, "USPRG5",
4955 &spr_read_ureg
, SPR_NOACCESS
,
4956 &spr_read_ureg
, SPR_NOACCESS
,
4958 spr_register(env
, SPR_SPRG6
, "SPRG6",
4959 SPR_NOACCESS
, SPR_NOACCESS
,
4960 &spr_read_generic
, &spr_write_generic
,
4962 spr_register(env
, SPR_USPRG6
, "USPRG6",
4963 &spr_read_ureg
, SPR_NOACCESS
,
4964 &spr_read_ureg
, SPR_NOACCESS
,
4966 spr_register(env
, SPR_SPRG7
, "SPRG7",
4967 SPR_NOACCESS
, SPR_NOACCESS
,
4968 &spr_read_generic
, &spr_write_generic
,
4970 spr_register(env
, SPR_USPRG7
, "USPRG7",
4971 &spr_read_ureg
, SPR_NOACCESS
,
4972 &spr_read_ureg
, SPR_NOACCESS
,
4974 /* Memory management */
4975 register_low_BATs(env
);
4976 register_high_BATs(env
);
4977 init_excp_7450(env
);
4978 env
->dcache_line_size
= 32;
4979 env
->icache_line_size
= 32;
4980 /* Allocate hardware IRQ controller */
4981 ppc6xx_irq_init(env_archcpu(env
));
4984 POWERPC_FAMILY(e600
)(ObjectClass
*oc
, void *data
)
4986 DeviceClass
*dc
= DEVICE_CLASS(oc
);
4987 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
4989 dc
->desc
= "PowerPC e600";
4990 pcc
->init_proc
= init_proc_e600
;
4991 pcc
->check_pow
= check_pow_hid0_74xx
;
4992 pcc
->insns_flags
= PPC_INSNS_BASE
| PPC_STRING
| PPC_MFTB
|
4993 PPC_FLOAT
| PPC_FLOAT_FSEL
| PPC_FLOAT_FRES
|
4994 PPC_FLOAT_FSQRT
| PPC_FLOAT_FRSQRTE
|
4996 PPC_CACHE
| PPC_CACHE_ICBI
|
4997 PPC_CACHE_DCBA
| PPC_CACHE_DCBZ
|
4998 PPC_MEM_SYNC
| PPC_MEM_EIEIO
|
4999 PPC_MEM_TLBIE
| PPC_MEM_TLBSYNC
|
5001 PPC_SEGMENT
| PPC_EXTERN
|
5003 pcc
->insns_flags2
= PPC_NONE
;
5004 pcc
->msr_mask
= (1ull << MSR_VR
) |
5021 pcc
->mmu_model
= POWERPC_MMU_32B
;
5022 pcc
->excp_model
= POWERPC_EXCP_74xx
;
5023 pcc
->bus_model
= PPC_FLAGS_INPUT_6xx
;
5024 pcc
->bfd_mach
= bfd_mach_ppc_7400
;
5025 pcc
->flags
= POWERPC_FLAG_VRE
| POWERPC_FLAG_SE
|
5026 POWERPC_FLAG_BE
| POWERPC_FLAG_PMM
|
5027 POWERPC_FLAG_BUS_CLK
;
5030 #if defined(TARGET_PPC64)
5031 #if defined(CONFIG_USER_ONLY)
5032 #define POWERPC970_HID5_INIT 0x00000080
5034 #define POWERPC970_HID5_INIT 0x00000000
5037 static int check_pow_970(CPUPPCState
*env
)
5039 if (env
->spr
[SPR_HID0
] & (HID0_DEEPNAP
| HID0_DOZE
| HID0_NAP
)) {
5046 static void register_970_hid_sprs(CPUPPCState
*env
)
5048 /* Hardware implementation registers */
5049 spr_register(env
, SPR_HID0
, "HID0",
5050 SPR_NOACCESS
, SPR_NOACCESS
,
5051 &spr_read_generic
, &spr_write_clear
,
5053 spr_register(env
, SPR_HID1
, "HID1",
5054 SPR_NOACCESS
, SPR_NOACCESS
,
5055 &spr_read_generic
, &spr_write_generic
,
5057 spr_register(env
, SPR_970_HID5
, "HID5",
5058 SPR_NOACCESS
, SPR_NOACCESS
,
5059 &spr_read_generic
, &spr_write_generic
,
5060 POWERPC970_HID5_INIT
);
5063 static void register_970_hior_sprs(CPUPPCState
*env
)
5065 spr_register(env
, SPR_HIOR
, "SPR_HIOR",
5066 SPR_NOACCESS
, SPR_NOACCESS
,
5067 &spr_read_hior
, &spr_write_hior
,
5071 static void register_book3s_ctrl_sprs(CPUPPCState
*env
)
5073 spr_register(env
, SPR_CTRL
, "SPR_CTRL",
5074 SPR_NOACCESS
, SPR_NOACCESS
,
5075 SPR_NOACCESS
, &spr_write_CTRL
,
5077 spr_register(env
, SPR_UCTRL
, "SPR_UCTRL",
5078 &spr_read_ureg
, SPR_NOACCESS
,
5079 &spr_read_ureg
, SPR_NOACCESS
,
5083 static void register_book3s_altivec_sprs(CPUPPCState
*env
)
5085 if (!(env
->insns_flags
& PPC_ALTIVEC
)) {
5089 spr_register_kvm(env
, SPR_VRSAVE
, "VRSAVE",
5090 &spr_read_generic
, &spr_write_generic32
,
5091 &spr_read_generic
, &spr_write_generic32
,
5092 KVM_REG_PPC_VRSAVE
, 0x00000000);
5096 static void register_book3s_dbg_sprs(CPUPPCState
*env
)
5099 * TODO: different specs define different scopes for these,
5100 * will have to address this:
5101 * 970: super/write and super/read
5102 * powerisa 2.03..2.04: hypv/write and super/read.
5103 * powerisa 2.05 and newer: hypv/write and hypv/read.
5105 spr_register_kvm(env
, SPR_DABR
, "DABR",
5106 SPR_NOACCESS
, SPR_NOACCESS
,
5107 &spr_read_generic
, &spr_write_generic
,
5108 KVM_REG_PPC_DABR
, 0x00000000);
5109 spr_register_kvm(env
, SPR_DABRX
, "DABRX",
5110 SPR_NOACCESS
, SPR_NOACCESS
,
5111 &spr_read_generic
, &spr_write_generic
,
5112 KVM_REG_PPC_DABRX
, 0x00000000);
5115 static void register_book3s_207_dbg_sprs(CPUPPCState
*env
)
5117 spr_register_kvm_hv(env
, SPR_DAWR0
, "DAWR0",
5118 SPR_NOACCESS
, SPR_NOACCESS
,
5119 SPR_NOACCESS
, SPR_NOACCESS
,
5120 &spr_read_generic
, &spr_write_generic
,
5121 KVM_REG_PPC_DAWR
, 0x00000000);
5122 spr_register_kvm_hv(env
, SPR_DAWRX0
, "DAWRX0",
5123 SPR_NOACCESS
, SPR_NOACCESS
,
5124 SPR_NOACCESS
, SPR_NOACCESS
,
5125 &spr_read_generic
, &spr_write_generic32
,
5126 KVM_REG_PPC_DAWRX
, 0x00000000);
5127 spr_register_kvm_hv(env
, SPR_CIABR
, "CIABR",
5128 SPR_NOACCESS
, SPR_NOACCESS
,
5129 SPR_NOACCESS
, SPR_NOACCESS
,
5130 &spr_read_generic
, &spr_write_generic
,
5131 KVM_REG_PPC_CIABR
, 0x00000000);
5134 static void register_970_dbg_sprs(CPUPPCState
*env
)
5137 spr_register(env
, SPR_IABR
, "IABR",
5138 SPR_NOACCESS
, SPR_NOACCESS
,
5139 &spr_read_generic
, &spr_write_generic
,
5143 static void register_book3s_pmu_sup_sprs(CPUPPCState
*env
)
5145 spr_register_kvm(env
, SPR_POWER_MMCR0
, "MMCR0",
5146 SPR_NOACCESS
, SPR_NOACCESS
,
5147 &spr_read_generic
, &spr_write_MMCR0
,
5148 KVM_REG_PPC_MMCR0
, 0x80000000);
5149 spr_register_kvm(env
, SPR_POWER_MMCR1
, "MMCR1",
5150 SPR_NOACCESS
, SPR_NOACCESS
,
5151 &spr_read_generic
, &spr_write_MMCR1
,
5152 KVM_REG_PPC_MMCR1
, 0x00000000);
5153 spr_register_kvm(env
, SPR_POWER_MMCRA
, "MMCRA",
5154 SPR_NOACCESS
, SPR_NOACCESS
,
5155 &spr_read_generic
, &spr_write_generic
,
5156 KVM_REG_PPC_MMCRA
, 0x00000000);
5157 spr_register_kvm(env
, SPR_POWER_PMC1
, "PMC1",
5158 SPR_NOACCESS
, SPR_NOACCESS
,
5159 &spr_read_PMC
, &spr_write_PMC
,
5160 KVM_REG_PPC_PMC1
, 0x00000000);
5161 spr_register_kvm(env
, SPR_POWER_PMC2
, "PMC2",
5162 SPR_NOACCESS
, SPR_NOACCESS
,
5163 &spr_read_PMC
, &spr_write_PMC
,
5164 KVM_REG_PPC_PMC2
, 0x00000000);
5165 spr_register_kvm(env
, SPR_POWER_PMC3
, "PMC3",
5166 SPR_NOACCESS
, SPR_NOACCESS
,
5167 &spr_read_PMC
, &spr_write_PMC
,
5168 KVM_REG_PPC_PMC3
, 0x00000000);
5169 spr_register_kvm(env
, SPR_POWER_PMC4
, "PMC4",
5170 SPR_NOACCESS
, SPR_NOACCESS
,
5171 &spr_read_PMC
, &spr_write_PMC
,
5172 KVM_REG_PPC_PMC4
, 0x00000000);
5173 spr_register_kvm(env
, SPR_POWER_PMC5
, "PMC5",
5174 SPR_NOACCESS
, SPR_NOACCESS
,
5175 &spr_read_PMC
, &spr_write_PMC
,
5176 KVM_REG_PPC_PMC5
, 0x00000000);
5177 spr_register_kvm(env
, SPR_POWER_PMC6
, "PMC6",
5178 SPR_NOACCESS
, SPR_NOACCESS
,
5179 &spr_read_PMC
, &spr_write_PMC
,
5180 KVM_REG_PPC_PMC6
, 0x00000000);
5181 spr_register_kvm(env
, SPR_POWER_SIAR
, "SIAR",
5182 SPR_NOACCESS
, SPR_NOACCESS
,
5183 &spr_read_generic
, &spr_write_generic
,
5184 KVM_REG_PPC_SIAR
, 0x00000000);
5185 spr_register_kvm(env
, SPR_POWER_SDAR
, "SDAR",
5186 SPR_NOACCESS
, SPR_NOACCESS
,
5187 &spr_read_generic
, &spr_write_generic
,
5188 KVM_REG_PPC_SDAR
, 0x00000000);
5191 static void register_book3s_pmu_user_sprs(CPUPPCState
*env
)
5193 spr_register(env
, SPR_POWER_UMMCR0
, "UMMCR0",
5194 &spr_read_MMCR0_ureg
, &spr_write_MMCR0_ureg
,
5195 &spr_read_ureg
, &spr_write_ureg
,
5197 spr_register(env
, SPR_POWER_UMMCR1
, "UMMCR1",
5198 &spr_read_ureg
, SPR_NOACCESS
,
5199 &spr_read_ureg
, &spr_write_ureg
,
5201 spr_register(env
, SPR_POWER_UMMCRA
, "UMMCRA",
5202 &spr_read_ureg
, SPR_NOACCESS
,
5203 &spr_read_ureg
, &spr_write_ureg
,
5205 spr_register(env
, SPR_POWER_UPMC1
, "UPMC1",
5206 &spr_read_PMC14_ureg
, &spr_write_PMC14_ureg
,
5207 &spr_read_ureg
, &spr_write_ureg
,
5209 spr_register(env
, SPR_POWER_UPMC2
, "UPMC2",
5210 &spr_read_PMC14_ureg
, &spr_write_PMC14_ureg
,
5211 &spr_read_ureg
, &spr_write_ureg
,
5213 spr_register(env
, SPR_POWER_UPMC3
, "UPMC3",
5214 &spr_read_PMC14_ureg
, &spr_write_PMC14_ureg
,
5215 &spr_read_ureg
, &spr_write_ureg
,
5217 spr_register(env
, SPR_POWER_UPMC4
, "UPMC4",
5218 &spr_read_PMC14_ureg
, &spr_write_PMC14_ureg
,
5219 &spr_read_ureg
, &spr_write_ureg
,
5221 spr_register(env
, SPR_POWER_UPMC5
, "UPMC5",
5222 &spr_read_PMC56_ureg
, &spr_write_PMC56_ureg
,
5223 &spr_read_ureg
, &spr_write_ureg
,
5225 spr_register(env
, SPR_POWER_UPMC6
, "UPMC6",
5226 &spr_read_PMC56_ureg
, &spr_write_PMC56_ureg
,
5227 &spr_read_ureg
, &spr_write_ureg
,
5229 spr_register(env
, SPR_POWER_USIAR
, "USIAR",
5230 &spr_read_ureg
, SPR_NOACCESS
,
5231 &spr_read_ureg
, &spr_write_ureg
,
5233 spr_register(env
, SPR_POWER_USDAR
, "USDAR",
5234 &spr_read_ureg
, SPR_NOACCESS
,
5235 &spr_read_ureg
, &spr_write_ureg
,
5239 static void register_970_pmu_sup_sprs(CPUPPCState
*env
)
5241 spr_register_kvm(env
, SPR_970_PMC7
, "PMC7",
5242 SPR_NOACCESS
, SPR_NOACCESS
,
5243 &spr_read_generic
, &spr_write_generic
,
5244 KVM_REG_PPC_PMC7
, 0x00000000);
5245 spr_register_kvm(env
, SPR_970_PMC8
, "PMC8",
5246 SPR_NOACCESS
, SPR_NOACCESS
,
5247 &spr_read_generic
, &spr_write_generic
,
5248 KVM_REG_PPC_PMC8
, 0x00000000);
5251 static void register_970_pmu_user_sprs(CPUPPCState
*env
)
5253 spr_register(env
, SPR_970_UPMC7
, "UPMC7",
5254 &spr_read_ureg
, SPR_NOACCESS
,
5255 &spr_read_ureg
, &spr_write_ureg
,
5257 spr_register(env
, SPR_970_UPMC8
, "UPMC8",
5258 &spr_read_ureg
, SPR_NOACCESS
,
5259 &spr_read_ureg
, &spr_write_ureg
,
5263 static void register_power8_pmu_sup_sprs(CPUPPCState
*env
)
5265 spr_register_kvm(env
, SPR_POWER_MMCR2
, "MMCR2",
5266 SPR_NOACCESS
, SPR_NOACCESS
,
5267 &spr_read_generic
, &spr_write_generic
,
5268 KVM_REG_PPC_MMCR2
, 0x00000000);
5269 spr_register_kvm(env
, SPR_POWER_MMCRS
, "MMCRS",
5270 SPR_NOACCESS
, SPR_NOACCESS
,
5271 &spr_read_generic
, &spr_write_generic
,
5272 KVM_REG_PPC_MMCRS
, 0x00000000);
5273 spr_register_kvm(env
, SPR_POWER_SIER
, "SIER",
5274 SPR_NOACCESS
, SPR_NOACCESS
,
5275 &spr_read_generic
, &spr_write_generic
,
5276 KVM_REG_PPC_SIER
, 0x00000000);
5277 spr_register_kvm(env
, SPR_POWER_SPMC1
, "SPMC1",
5278 SPR_NOACCESS
, SPR_NOACCESS
,
5279 &spr_read_generic
, &spr_write_generic
,
5280 KVM_REG_PPC_SPMC1
, 0x00000000);
5281 spr_register_kvm(env
, SPR_POWER_SPMC2
, "SPMC2",
5282 SPR_NOACCESS
, SPR_NOACCESS
,
5283 &spr_read_generic
, &spr_write_generic
,
5284 KVM_REG_PPC_SPMC2
, 0x00000000);
5285 spr_register_kvm(env
, SPR_TACR
, "TACR",
5286 SPR_NOACCESS
, SPR_NOACCESS
,
5287 &spr_read_generic
, &spr_write_generic
,
5288 KVM_REG_PPC_TACR
, 0x00000000);
5289 spr_register_kvm(env
, SPR_TCSCR
, "TCSCR",
5290 SPR_NOACCESS
, SPR_NOACCESS
,
5291 &spr_read_generic
, &spr_write_generic
,
5292 KVM_REG_PPC_TCSCR
, 0x00000000);
5293 spr_register_kvm(env
, SPR_CSIGR
, "CSIGR",
5294 SPR_NOACCESS
, SPR_NOACCESS
,
5295 &spr_read_generic
, &spr_write_generic
,
5296 KVM_REG_PPC_CSIGR
, 0x00000000);
5299 static void register_power8_pmu_user_sprs(CPUPPCState
*env
)
5301 spr_register(env
, SPR_POWER_UMMCR2
, "UMMCR2",
5302 &spr_read_MMCR2_ureg
, &spr_write_MMCR2_ureg
,
5303 &spr_read_ureg
, &spr_write_ureg
,
5305 spr_register(env
, SPR_POWER_USIER
, "USIER",
5306 &spr_read_generic
, SPR_NOACCESS
,
5307 &spr_read_generic
, &spr_write_generic
,
5311 static void register_power5p_ear_sprs(CPUPPCState
*env
)
5313 /* External access control */
5314 spr_register(env
, SPR_EAR
, "EAR",
5315 SPR_NOACCESS
, SPR_NOACCESS
,
5316 &spr_read_generic
, &spr_write_generic
,
5320 static void register_power5p_tb_sprs(CPUPPCState
*env
)
5322 /* TBU40 (High 40 bits of the Timebase register */
5323 spr_register_hv(env
, SPR_TBU40
, "TBU40",
5324 SPR_NOACCESS
, SPR_NOACCESS
,
5325 SPR_NOACCESS
, SPR_NOACCESS
,
5326 SPR_NOACCESS
, &spr_write_tbu40
,
5330 static void register_970_lpar_sprs(CPUPPCState
*env
)
5332 #if !defined(CONFIG_USER_ONLY)
5334 * PPC970: HID4 covers things later controlled by the LPCR and
5335 * RMOR in later CPUs, but with a different encoding. We only
5336 * support the 970 in "Apple mode" which has all hypervisor
5337 * facilities disabled by strapping, so we can basically just
5340 spr_register(env
, SPR_970_HID4
, "HID4",
5341 SPR_NOACCESS
, SPR_NOACCESS
,
5342 &spr_read_generic
, &spr_write_generic
,
5347 static void register_power5p_lpar_sprs(CPUPPCState
*env
)
5349 #if !defined(CONFIG_USER_ONLY)
5350 /* Logical partitionning */
5351 spr_register_kvm_hv(env
, SPR_LPCR
, "LPCR",
5352 SPR_NOACCESS
, SPR_NOACCESS
,
5353 SPR_NOACCESS
, SPR_NOACCESS
,
5354 &spr_read_generic
, &spr_write_lpcr
,
5355 KVM_REG_PPC_LPCR
, LPCR_LPES0
| LPCR_LPES1
);
5356 spr_register_hv(env
, SPR_HDEC
, "HDEC",
5357 SPR_NOACCESS
, SPR_NOACCESS
,
5358 SPR_NOACCESS
, SPR_NOACCESS
,
5359 &spr_read_hdecr
, &spr_write_hdecr
, 0);
5363 static void register_book3s_ids_sprs(CPUPPCState
*env
)
5365 /* FIXME: Will need to deal with thread vs core only SPRs */
5367 /* Processor identification */
5368 spr_register_hv(env
, SPR_PIR
, "PIR",
5369 SPR_NOACCESS
, SPR_NOACCESS
,
5370 &spr_read_generic
, SPR_NOACCESS
,
5371 &spr_read_generic
, NULL
,
5373 spr_register_hv(env
, SPR_LPIDR
, "LPIDR",
5374 SPR_NOACCESS
, SPR_NOACCESS
,
5375 SPR_NOACCESS
, SPR_NOACCESS
,
5376 &spr_read_generic
, &spr_write_lpidr
,
5378 spr_register_hv(env
, SPR_HFSCR
, "HFSCR",
5379 SPR_NOACCESS
, SPR_NOACCESS
,
5380 SPR_NOACCESS
, SPR_NOACCESS
,
5381 &spr_read_generic
, &spr_write_generic
,
5383 spr_register_hv(env
, SPR_MMCRC
, "MMCRC",
5384 SPR_NOACCESS
, SPR_NOACCESS
,
5385 SPR_NOACCESS
, SPR_NOACCESS
,
5386 &spr_read_generic
, &spr_write_generic32
,
5388 spr_register_hv(env
, SPR_MMCRH
, "MMCRH",
5389 SPR_NOACCESS
, SPR_NOACCESS
,
5390 SPR_NOACCESS
, SPR_NOACCESS
,
5391 &spr_read_generic
, &spr_write_generic
,
5393 spr_register_hv(env
, SPR_HSPRG0
, "HSPRG0",
5394 SPR_NOACCESS
, SPR_NOACCESS
,
5395 SPR_NOACCESS
, SPR_NOACCESS
,
5396 &spr_read_generic
, &spr_write_generic
,
5398 spr_register_hv(env
, SPR_HSPRG1
, "HSPRG1",
5399 SPR_NOACCESS
, SPR_NOACCESS
,
5400 SPR_NOACCESS
, SPR_NOACCESS
,
5401 &spr_read_generic
, &spr_write_generic
,
5403 spr_register_hv(env
, SPR_HSRR0
, "HSRR0",
5404 SPR_NOACCESS
, SPR_NOACCESS
,
5405 SPR_NOACCESS
, SPR_NOACCESS
,
5406 &spr_read_generic
, &spr_write_generic
,
5408 spr_register_hv(env
, SPR_HSRR1
, "HSRR1",
5409 SPR_NOACCESS
, SPR_NOACCESS
,
5410 SPR_NOACCESS
, SPR_NOACCESS
,
5411 &spr_read_generic
, &spr_write_generic
,
5413 spr_register_hv(env
, SPR_HDAR
, "HDAR",
5414 SPR_NOACCESS
, SPR_NOACCESS
,
5415 SPR_NOACCESS
, SPR_NOACCESS
,
5416 &spr_read_generic
, &spr_write_generic
,
5418 spr_register_hv(env
, SPR_HDSISR
, "HDSISR",
5419 SPR_NOACCESS
, SPR_NOACCESS
,
5420 SPR_NOACCESS
, SPR_NOACCESS
,
5421 &spr_read_generic
, &spr_write_generic32
,
5423 spr_register_hv(env
, SPR_HRMOR
, "HRMOR",
5424 SPR_NOACCESS
, SPR_NOACCESS
,
5425 SPR_NOACCESS
, SPR_NOACCESS
,
5426 &spr_read_generic
, &spr_write_generic
,
5430 static void register_rmor_sprs(CPUPPCState
*env
)
5432 spr_register_hv(env
, SPR_RMOR
, "RMOR",
5433 SPR_NOACCESS
, SPR_NOACCESS
,
5434 SPR_NOACCESS
, SPR_NOACCESS
,
5435 &spr_read_generic
, &spr_write_generic
,
5439 static void register_power8_ids_sprs(CPUPPCState
*env
)
5441 /* Thread identification */
5442 spr_register(env
, SPR_TIR
, "TIR",
5443 SPR_NOACCESS
, SPR_NOACCESS
,
5444 &spr_read_generic
, SPR_NOACCESS
,
5448 static void register_book3s_purr_sprs(CPUPPCState
*env
)
5450 #if !defined(CONFIG_USER_ONLY)
5451 /* PURR & SPURR: Hack - treat these as aliases for the TB for now */
5452 spr_register_kvm_hv(env
, SPR_PURR
, "PURR",
5453 &spr_read_purr
, SPR_NOACCESS
,
5454 &spr_read_purr
, SPR_NOACCESS
,
5455 &spr_read_purr
, &spr_write_purr
,
5456 KVM_REG_PPC_PURR
, 0x00000000);
5457 spr_register_kvm_hv(env
, SPR_SPURR
, "SPURR",
5458 &spr_read_purr
, SPR_NOACCESS
,
5459 &spr_read_purr
, SPR_NOACCESS
,
5460 &spr_read_purr
, &spr_write_purr
,
5461 KVM_REG_PPC_SPURR
, 0x00000000);
5465 static void register_power6_dbg_sprs(CPUPPCState
*env
)
5467 #if !defined(CONFIG_USER_ONLY)
5468 spr_register(env
, SPR_CFAR
, "SPR_CFAR",
5469 SPR_NOACCESS
, SPR_NOACCESS
,
5470 &spr_read_cfar
, &spr_write_cfar
,
5475 static void register_power5p_common_sprs(CPUPPCState
*env
)
5477 spr_register_kvm(env
, SPR_PPR
, "PPR",
5478 &spr_read_generic
, &spr_write_generic
,
5479 &spr_read_generic
, &spr_write_generic
,
5480 KVM_REG_PPC_PPR
, 0x00000000);
5483 static void register_power6_common_sprs(CPUPPCState
*env
)
5485 #if !defined(CONFIG_USER_ONLY)
5486 spr_register_kvm(env
, SPR_DSCR
, "SPR_DSCR",
5487 SPR_NOACCESS
, SPR_NOACCESS
,
5488 &spr_read_generic
, &spr_write_generic
,
5489 KVM_REG_PPC_DSCR
, 0x00000000);
5492 * Register PCR to report POWERPC_EXCP_PRIV_REG instead of
5493 * POWERPC_EXCP_INVAL_SPR in userspace. Permit hypervisor access.
5495 spr_register_hv(env
, SPR_PCR
, "PCR",
5496 SPR_NOACCESS
, SPR_NOACCESS
,
5497 SPR_NOACCESS
, SPR_NOACCESS
,
5498 &spr_read_generic
, &spr_write_pcr
,
5502 static void register_HEIR32_spr(CPUPPCState
*env
)
5504 spr_register_hv(env
, SPR_HEIR
, "HEIR",
5505 SPR_NOACCESS
, SPR_NOACCESS
,
5506 SPR_NOACCESS
, SPR_NOACCESS
,
5507 &spr_read_generic
, &spr_write_generic32
,
5511 static void register_HEIR64_spr(CPUPPCState
*env
)
5513 spr_register_hv(env
, SPR_HEIR
, "HEIR",
5514 SPR_NOACCESS
, SPR_NOACCESS
,
5515 SPR_NOACCESS
, SPR_NOACCESS
,
5516 &spr_read_generic
, &spr_write_generic
,
5520 static void register_power8_tce_address_control_sprs(CPUPPCState
*env
)
5522 spr_register_kvm(env
, SPR_TAR
, "TAR",
5523 &spr_read_tar
, &spr_write_tar
,
5524 &spr_read_generic
, &spr_write_generic
,
5525 KVM_REG_PPC_TAR
, 0x00000000);
5528 static void register_power8_tm_sprs(CPUPPCState
*env
)
5530 spr_register_kvm(env
, SPR_TFHAR
, "TFHAR",
5531 &spr_read_tm
, &spr_write_tm
,
5532 &spr_read_tm
, &spr_write_tm
,
5533 KVM_REG_PPC_TFHAR
, 0x00000000);
5534 spr_register_kvm(env
, SPR_TFIAR
, "TFIAR",
5535 &spr_read_tm
, &spr_write_tm
,
5536 &spr_read_tm
, &spr_write_tm
,
5537 KVM_REG_PPC_TFIAR
, 0x00000000);
5538 spr_register_kvm(env
, SPR_TEXASR
, "TEXASR",
5539 &spr_read_tm
, &spr_write_tm
,
5540 &spr_read_tm
, &spr_write_tm
,
5541 KVM_REG_PPC_TEXASR
, 0x00000000);
5542 spr_register(env
, SPR_TEXASRU
, "TEXASRU",
5543 &spr_read_tm_upper32
, &spr_write_tm_upper32
,
5544 &spr_read_tm_upper32
, &spr_write_tm_upper32
,
5548 static void register_power8_ebb_sprs(CPUPPCState
*env
)
5550 spr_register(env
, SPR_BESCRS
, "BESCRS",
5551 &spr_read_ebb
, &spr_write_ebb
,
5552 &spr_read_generic
, &spr_write_generic
,
5554 spr_register(env
, SPR_BESCRSU
, "BESCRSU",
5555 &spr_read_ebb_upper32
, &spr_write_ebb_upper32
,
5556 &spr_read_prev_upper32
, &spr_write_prev_upper32
,
5558 spr_register(env
, SPR_BESCRR
, "BESCRR",
5559 &spr_read_ebb
, &spr_write_ebb
,
5560 &spr_read_generic
, &spr_write_generic
,
5562 spr_register(env
, SPR_BESCRRU
, "BESCRRU",
5563 &spr_read_ebb_upper32
, &spr_write_ebb_upper32
,
5564 &spr_read_prev_upper32
, &spr_write_prev_upper32
,
5566 spr_register_kvm(env
, SPR_EBBHR
, "EBBHR",
5567 &spr_read_ebb
, &spr_write_ebb
,
5568 &spr_read_generic
, &spr_write_generic
,
5569 KVM_REG_PPC_EBBHR
, 0x00000000);
5570 spr_register_kvm(env
, SPR_EBBRR
, "EBBRR",
5571 &spr_read_ebb
, &spr_write_ebb
,
5572 &spr_read_generic
, &spr_write_generic
,
5573 KVM_REG_PPC_EBBRR
, 0x00000000);
5574 spr_register_kvm(env
, SPR_BESCR
, "BESCR",
5575 &spr_read_ebb
, &spr_write_ebb
,
5576 &spr_read_generic
, &spr_write_generic
,
5577 KVM_REG_PPC_BESCR
, 0x00000000);
5580 /* Virtual Time Base */
5581 static void register_vtb_sprs(CPUPPCState
*env
)
5583 spr_register_kvm_hv(env
, SPR_VTB
, "VTB",
5584 SPR_NOACCESS
, SPR_NOACCESS
,
5585 &spr_read_vtb
, SPR_NOACCESS
,
5586 &spr_read_vtb
, &spr_write_vtb
,
5587 KVM_REG_PPC_VTB
, 0x00000000);
5590 static void register_power8_fscr_sprs(CPUPPCState
*env
)
5592 #if defined(CONFIG_USER_ONLY)
5593 target_ulong initval
= 1ULL << FSCR_TAR
;
5595 target_ulong initval
= 0;
5597 spr_register_kvm(env
, SPR_FSCR
, "FSCR",
5598 SPR_NOACCESS
, SPR_NOACCESS
,
5599 &spr_read_generic
, &spr_write_generic
,
5600 KVM_REG_PPC_FSCR
, initval
);
5603 static void register_power8_pspb_sprs(CPUPPCState
*env
)
5605 spr_register_kvm(env
, SPR_PSPB
, "PSPB",
5606 SPR_NOACCESS
, SPR_NOACCESS
,
5607 &spr_read_generic
, &spr_write_generic32
,
5608 KVM_REG_PPC_PSPB
, 0);
5611 static void register_power8_dpdes_sprs(CPUPPCState
*env
)
5613 #if !defined(CONFIG_USER_ONLY)
5614 /* Directed Privileged Door-bell Exception State, used for IPI */
5615 spr_register_kvm_hv(env
, SPR_DPDES
, "DPDES",
5616 SPR_NOACCESS
, SPR_NOACCESS
,
5617 &spr_read_dpdes
, SPR_NOACCESS
,
5618 &spr_read_dpdes
, &spr_write_dpdes
,
5619 KVM_REG_PPC_DPDES
, 0x00000000);
5623 static void register_power8_ic_sprs(CPUPPCState
*env
)
5625 #if !defined(CONFIG_USER_ONLY)
5626 spr_register_hv(env
, SPR_IC
, "IC",
5627 SPR_NOACCESS
, SPR_NOACCESS
,
5628 &spr_read_generic
, SPR_NOACCESS
,
5629 &spr_read_generic
, &spr_write_generic
,
5634 /* SPRs specific to IBM POWER CPUs */
5635 static void register_power_common_book4_sprs(CPUPPCState
*env
)
5637 #if !defined(CONFIG_USER_ONLY)
5638 spr_register_hv(env
, SPR_HID0
, "HID0",
5639 SPR_NOACCESS
, SPR_NOACCESS
,
5640 SPR_NOACCESS
, SPR_NOACCESS
,
5641 &spr_read_generic
, &spr_core_write_generic
,
5643 spr_register_hv(env
, SPR_TSCR
, "TSCR",
5644 SPR_NOACCESS
, SPR_NOACCESS
,
5645 SPR_NOACCESS
, SPR_NOACCESS
,
5646 &spr_read_generic
, &spr_write_generic32
,
5648 spr_register_hv(env
, SPR_HMER
, "HMER",
5649 SPR_NOACCESS
, SPR_NOACCESS
,
5650 SPR_NOACCESS
, SPR_NOACCESS
,
5651 &spr_read_generic
, &spr_write_hmer
,
5653 spr_register_hv(env
, SPR_HMEER
, "HMEER",
5654 SPR_NOACCESS
, SPR_NOACCESS
,
5655 SPR_NOACCESS
, SPR_NOACCESS
,
5656 &spr_read_generic
, &spr_write_generic
,
5658 spr_register_hv(env
, SPR_TFMR
, "TFMR",
5659 SPR_NOACCESS
, SPR_NOACCESS
,
5660 SPR_NOACCESS
, SPR_NOACCESS
,
5661 &spr_read_tfmr
, &spr_write_tfmr
,
5666 static void register_power9_book4_sprs(CPUPPCState
*env
)
5668 /* Add a number of P9 book4 registers */
5669 register_power_common_book4_sprs(env
);
5670 #if !defined(CONFIG_USER_ONLY)
5671 spr_register_kvm(env
, SPR_WORT
, "WORT",
5672 SPR_NOACCESS
, SPR_NOACCESS
,
5673 &spr_read_generic
, &spr_write_generic
,
5674 KVM_REG_PPC_WORT
, 0);
5678 static void register_power8_book4_sprs(CPUPPCState
*env
)
5680 /* Add a number of P8 book4 registers */
5681 register_power_common_book4_sprs(env
);
5682 #if !defined(CONFIG_USER_ONLY)
5683 spr_register_kvm(env
, SPR_ACOP
, "ACOP",
5684 SPR_NOACCESS
, SPR_NOACCESS
,
5685 &spr_read_generic
, &spr_write_generic
,
5686 KVM_REG_PPC_ACOP
, 0);
5687 /* PID is only in BookE in ISA v2.07 */
5688 spr_register_kvm(env
, SPR_BOOKS_PID
, "PID",
5689 SPR_NOACCESS
, SPR_NOACCESS
,
5690 &spr_read_generic
, &spr_write_pidr
,
5691 KVM_REG_PPC_PID
, 0);
5692 spr_register_kvm(env
, SPR_WORT
, "WORT",
5693 SPR_NOACCESS
, SPR_NOACCESS
,
5694 &spr_read_generic
, &spr_write_generic
,
5695 KVM_REG_PPC_WORT
, 0);
5699 static void register_power7_book4_sprs(CPUPPCState
*env
)
5701 /* Add a number of P7 book4 registers */
5702 #if !defined(CONFIG_USER_ONLY)
5703 register_power_common_book4_sprs(env
);
5704 spr_register_kvm(env
, SPR_ACOP
, "ACOP",
5705 SPR_NOACCESS
, SPR_NOACCESS
,
5706 &spr_read_generic
, &spr_write_generic
,
5707 KVM_REG_PPC_ACOP
, 0);
5708 /* PID is only in BookE in ISA v2.06 */
5709 spr_register_kvm(env
, SPR_BOOKS_PID
, "PID",
5710 SPR_NOACCESS
, SPR_NOACCESS
,
5711 &spr_read_generic
, &spr_write_generic32
,
5712 KVM_REG_PPC_PID
, 0);
5716 static void register_power8_rpr_sprs(CPUPPCState
*env
)
5718 #if !defined(CONFIG_USER_ONLY)
5719 spr_register_hv(env
, SPR_RPR
, "RPR",
5720 SPR_NOACCESS
, SPR_NOACCESS
,
5721 SPR_NOACCESS
, SPR_NOACCESS
,
5722 &spr_read_generic
, &spr_write_generic
,
5723 0x00000103070F1F3F);
5727 static void register_power9_mmu_sprs(CPUPPCState
*env
)
5729 #if !defined(CONFIG_USER_ONLY)
5730 /* Partition Table Control */
5731 spr_register_kvm_hv(env
, SPR_PTCR
, "PTCR",
5732 SPR_NOACCESS
, SPR_NOACCESS
,
5733 SPR_NOACCESS
, SPR_NOACCESS
,
5734 &spr_read_generic
, &spr_write_ptcr
,
5735 KVM_REG_PPC_PTCR
, 0x00000000);
5736 /* Address Segment Descriptor Register */
5737 spr_register_hv(env
, SPR_ASDR
, "ASDR",
5738 SPR_NOACCESS
, SPR_NOACCESS
,
5739 SPR_NOACCESS
, SPR_NOACCESS
,
5740 &spr_read_generic
, &spr_write_generic
,
5741 0x0000000000000000);
5742 /* PID is part of the BookS ISA from v3.0 */
5743 spr_register_kvm(env
, SPR_BOOKS_PID
, "PID",
5744 SPR_NOACCESS
, SPR_NOACCESS
,
5745 &spr_read_generic
, &spr_write_pidr
,
5746 KVM_REG_PPC_PID
, 0);
5750 static void register_power10_hash_sprs(CPUPPCState
*env
)
5753 * it's the OS responsability to generate a random value for the registers
5754 * in each process' context. So, initialize it with 0 here.
5756 uint64_t hashkeyr_initial_value
= 0, hashpkeyr_initial_value
= 0;
5757 #if defined(CONFIG_USER_ONLY)
5758 /* in linux-user, setup the hash register with a random value */
5759 GRand
*rand
= g_rand_new();
5760 hashkeyr_initial_value
=
5761 ((uint64_t)g_rand_int(rand
) << 32) | (uint64_t)g_rand_int(rand
);
5762 hashpkeyr_initial_value
=
5763 ((uint64_t)g_rand_int(rand
) << 32) | (uint64_t)g_rand_int(rand
);
5766 spr_register(env
, SPR_HASHKEYR
, "HASHKEYR",
5767 SPR_NOACCESS
, SPR_NOACCESS
,
5768 &spr_read_generic
, &spr_write_generic
,
5769 hashkeyr_initial_value
);
5770 spr_register_hv(env
, SPR_HASHPKEYR
, "HASHPKEYR",
5771 SPR_NOACCESS
, SPR_NOACCESS
,
5772 SPR_NOACCESS
, SPR_NOACCESS
,
5773 &spr_read_generic
, &spr_write_generic
,
5774 hashpkeyr_initial_value
);
5777 static void register_power10_dexcr_sprs(CPUPPCState
*env
)
5779 spr_register(env
, SPR_DEXCR
, "DEXCR",
5780 SPR_NOACCESS
, SPR_NOACCESS
,
5781 &spr_read_generic
, &spr_write_generic32
,
5784 spr_register(env
, SPR_UDEXCR
, "DEXCR",
5785 &spr_read_dexcr_ureg
, SPR_NOACCESS
,
5786 &spr_read_dexcr_ureg
, SPR_NOACCESS
,
5789 spr_register_hv(env
, SPR_HDEXCR
, "HDEXCR",
5790 SPR_NOACCESS
, SPR_NOACCESS
,
5791 SPR_NOACCESS
, SPR_NOACCESS
,
5792 &spr_read_generic
, &spr_write_generic32
,
5795 spr_register(env
, SPR_UHDEXCR
, "HDEXCR",
5796 &spr_read_dexcr_ureg
, SPR_NOACCESS
,
5797 &spr_read_dexcr_ureg
, SPR_NOACCESS
,
5802 * Initialize PMU counter overflow timers for Power8 and
5803 * newer Power chips when using TCG.
5805 static void init_tcg_pmu_power8(CPUPPCState
*env
)
5807 /* Init PMU overflow timers */
5808 if (tcg_enabled()) {
5809 cpu_ppc_pmu_init(env
);
5813 static void init_proc_book3s_common(CPUPPCState
*env
)
5815 register_non_embedded_sprs(env
);
5816 register_book3s_altivec_sprs(env
);
5817 register_book3s_pmu_sup_sprs(env
);
5818 register_book3s_pmu_user_sprs(env
);
5819 register_book3s_ctrl_sprs(env
);
5821 * Can't find information on what this should be on reset. This
5822 * value is the one used by 74xx processors.
5824 vscr_init(env
, 0x00010000);
5826 spr_register(env
, SPR_USPRG3
, "USPRG3",
5827 &spr_read_ureg
, SPR_NOACCESS
,
5828 &spr_read_ureg
, SPR_NOACCESS
,
5832 static void init_proc_970(CPUPPCState
*env
)
5834 /* Common Registers */
5835 init_proc_book3s_common(env
);
5836 register_sdr1_sprs(env
);
5837 register_book3s_dbg_sprs(env
);
5839 /* 970 Specific Registers */
5840 register_970_hid_sprs(env
);
5841 register_970_hior_sprs(env
);
5842 register_low_BATs(env
);
5843 register_970_pmu_sup_sprs(env
);
5844 register_970_pmu_user_sprs(env
);
5845 register_970_lpar_sprs(env
);
5846 register_970_dbg_sprs(env
);
5849 env
->dcache_line_size
= 128;
5850 env
->icache_line_size
= 128;
5852 /* Allocate hardware IRQ controller */
5854 ppc970_irq_init(env_archcpu(env
));
5857 POWERPC_FAMILY(970)(ObjectClass
*oc
, void *data
)
5859 DeviceClass
*dc
= DEVICE_CLASS(oc
);
5860 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
5862 dc
->desc
= "PowerPC 970";
5863 pcc
->init_proc
= init_proc_970
;
5864 pcc
->check_pow
= check_pow_970
;
5865 pcc
->insns_flags
= PPC_INSNS_BASE
| PPC_STRING
| PPC_MFTB
|
5866 PPC_FLOAT
| PPC_FLOAT_FSEL
| PPC_FLOAT_FRES
|
5867 PPC_FLOAT_FSQRT
| PPC_FLOAT_FRSQRTE
|
5869 PPC_CACHE
| PPC_CACHE_ICBI
| PPC_CACHE_DCBZ
|
5870 PPC_MEM_SYNC
| PPC_MEM_EIEIO
|
5871 PPC_MEM_TLBIE
| PPC_MEM_TLBSYNC
|
5872 PPC_64B
| PPC_ALTIVEC
|
5873 PPC_SEGMENT_64B
| PPC_SLBI
;
5874 pcc
->insns_flags2
= PPC2_FP_CVT_S64
| PPC2_MEM_LWSYNC
;
5875 pcc
->msr_mask
= (1ull << MSR_SF
) |
5890 pcc
->mmu_model
= POWERPC_MMU_64B
;
5891 #if !defined(CONFIG_USER_ONLY)
5892 pcc
->hash64_opts
= &ppc_hash64_opts_basic
;
5894 pcc
->excp_model
= POWERPC_EXCP_970
;
5895 pcc
->bus_model
= PPC_FLAGS_INPUT_970
;
5896 pcc
->bfd_mach
= bfd_mach_ppc64
;
5897 pcc
->flags
= POWERPC_FLAG_VRE
| POWERPC_FLAG_SE
|
5898 POWERPC_FLAG_BE
| POWERPC_FLAG_PMM
|
5899 POWERPC_FLAG_BUS_CLK
;
5900 pcc
->l1_dcache_size
= 0x8000;
5901 pcc
->l1_icache_size
= 0x10000;
5904 static void init_proc_power5plus(CPUPPCState
*env
)
5906 /* Common Registers */
5907 init_proc_book3s_common(env
);
5908 register_sdr1_sprs(env
);
5909 register_book3s_dbg_sprs(env
);
5911 /* POWER5+ Specific Registers */
5912 register_970_hid_sprs(env
);
5913 register_970_hior_sprs(env
);
5914 register_low_BATs(env
);
5915 register_970_pmu_sup_sprs(env
);
5916 register_970_pmu_user_sprs(env
);
5917 register_power5p_common_sprs(env
);
5918 register_power5p_lpar_sprs(env
);
5919 register_power5p_ear_sprs(env
);
5920 register_power5p_tb_sprs(env
);
5923 env
->dcache_line_size
= 128;
5924 env
->icache_line_size
= 128;
5926 /* Allocate hardware IRQ controller */
5928 ppc970_irq_init(env_archcpu(env
));
5931 POWERPC_FAMILY(POWER5P
)(ObjectClass
*oc
, void *data
)
5933 DeviceClass
*dc
= DEVICE_CLASS(oc
);
5934 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
5936 dc
->fw_name
= "PowerPC,POWER5";
5937 dc
->desc
= "POWER5+";
5938 pcc
->init_proc
= init_proc_power5plus
;
5939 pcc
->check_pow
= check_pow_970
;
5940 pcc
->insns_flags
= PPC_INSNS_BASE
| PPC_STRING
| PPC_MFTB
|
5941 PPC_FLOAT
| PPC_FLOAT_FSEL
| PPC_FLOAT_FRES
|
5942 PPC_FLOAT_FSQRT
| PPC_FLOAT_FRSQRTE
|
5945 PPC_CACHE
| PPC_CACHE_ICBI
| PPC_CACHE_DCBZ
|
5946 PPC_MEM_SYNC
| PPC_MEM_EIEIO
|
5947 PPC_MEM_TLBIE
| PPC_MEM_TLBSYNC
|
5950 PPC_SEGMENT_64B
| PPC_SLBI
;
5951 pcc
->insns_flags2
= PPC2_FP_CVT_S64
| PPC2_MEM_LWSYNC
;
5952 pcc
->msr_mask
= (1ull << MSR_SF
) |
5967 pcc
->lpcr_mask
= LPCR_RMLS
| LPCR_ILE
| LPCR_LPES0
| LPCR_LPES1
|
5968 LPCR_RMI
| LPCR_HDICE
;
5969 pcc
->mmu_model
= POWERPC_MMU_2_03
;
5970 #if !defined(CONFIG_USER_ONLY)
5971 pcc
->hash64_opts
= &ppc_hash64_opts_basic
;
5972 pcc
->lrg_decr_bits
= 32;
5974 pcc
->excp_model
= POWERPC_EXCP_970
;
5975 pcc
->bus_model
= PPC_FLAGS_INPUT_970
;
5976 pcc
->bfd_mach
= bfd_mach_ppc64
;
5977 pcc
->flags
= POWERPC_FLAG_VRE
| POWERPC_FLAG_SE
|
5978 POWERPC_FLAG_BE
| POWERPC_FLAG_PMM
|
5979 POWERPC_FLAG_BUS_CLK
;
5980 pcc
->l1_dcache_size
= 0x8000;
5981 pcc
->l1_icache_size
= 0x10000;
5984 static void init_proc_POWER7(CPUPPCState
*env
)
5986 /* Common Registers */
5987 init_proc_book3s_common(env
);
5988 register_sdr1_sprs(env
);
5989 register_book3s_dbg_sprs(env
);
5991 /* POWER7 Specific Registers */
5992 register_book3s_ids_sprs(env
);
5993 register_rmor_sprs(env
);
5994 register_amr_sprs(env
);
5995 register_book3s_purr_sprs(env
);
5996 register_power5p_common_sprs(env
);
5997 register_power5p_lpar_sprs(env
);
5998 register_power5p_ear_sprs(env
);
5999 register_power5p_tb_sprs(env
);
6000 register_power6_common_sprs(env
);
6001 register_HEIR32_spr(env
);
6002 register_power6_dbg_sprs(env
);
6003 register_power7_book4_sprs(env
);
6006 env
->dcache_line_size
= 128;
6007 env
->icache_line_size
= 128;
6009 /* Allocate hardware IRQ controller */
6010 init_excp_POWER7(env
);
6011 ppcPOWER7_irq_init(env_archcpu(env
));
6014 static bool ppc_pvr_match_power7(PowerPCCPUClass
*pcc
, uint32_t pvr
, bool best
)
6016 uint32_t base
= pvr
& CPU_POWERPC_POWER_SERVER_MASK
;
6017 uint32_t pcc_base
= pcc
->pvr
& CPU_POWERPC_POWER_SERVER_MASK
;
6020 if (base
== CPU_POWERPC_POWER7_BASE
) {
6023 if (base
== CPU_POWERPC_POWER7P_BASE
) {
6028 if (base
!= pcc_base
) {
6035 POWERPC_FAMILY(POWER7
)(ObjectClass
*oc
, void *data
)
6037 DeviceClass
*dc
= DEVICE_CLASS(oc
);
6038 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
6040 dc
->fw_name
= "PowerPC,POWER7";
6041 dc
->desc
= "POWER7";
6042 pcc
->pvr_match
= ppc_pvr_match_power7
;
6043 pcc
->pcr_mask
= PCR_VEC_DIS
| PCR_VSX_DIS
| PCR_COMPAT_2_05
;
6044 pcc
->pcr_supported
= PCR_COMPAT_2_06
| PCR_COMPAT_2_05
;
6045 pcc
->init_proc
= init_proc_POWER7
;
6046 pcc
->check_pow
= check_pow_nocheck
;
6047 pcc
->insns_flags
= PPC_INSNS_BASE
| PPC_ISEL
| PPC_STRING
| PPC_MFTB
|
6048 PPC_FLOAT
| PPC_FLOAT_FSEL
| PPC_FLOAT_FRES
|
6049 PPC_FLOAT_FSQRT
| PPC_FLOAT_FRSQRTE
|
6050 PPC_FLOAT_FRSQRTES
|
6053 PPC_CACHE
| PPC_CACHE_ICBI
| PPC_CACHE_DCBZ
|
6054 PPC_MEM_SYNC
| PPC_MEM_EIEIO
|
6055 PPC_MEM_TLBIE
| PPC_MEM_TLBSYNC
|
6056 PPC_64B
| PPC_64H
| PPC_64BX
| PPC_ALTIVEC
|
6057 PPC_SEGMENT_64B
| PPC_SLBI
|
6058 PPC_POPCNTB
| PPC_POPCNTWD
|
6060 pcc
->insns_flags2
= PPC2_VSX
| PPC2_DFP
| PPC2_DBRX
| PPC2_ISA205
|
6061 PPC2_PERM_ISA206
| PPC2_DIVE_ISA206
|
6062 PPC2_ATOMIC_ISA206
| PPC2_FP_CVT_ISA206
|
6063 PPC2_FP_TST_ISA206
| PPC2_FP_CVT_S64
|
6064 PPC2_PM_ISA206
| PPC2_MEM_LWSYNC
| PPC2_BCDA_ISA206
;
6065 pcc
->msr_mask
= (1ull << MSR_SF
) |
6081 pcc
->lpcr_mask
= LPCR_VPM0
| LPCR_VPM1
| LPCR_ISL
| LPCR_DPFD
|
6082 LPCR_VRMASD
| LPCR_RMLS
| LPCR_ILE
|
6083 LPCR_P7_PECE0
| LPCR_P7_PECE1
| LPCR_P7_PECE2
|
6084 LPCR_MER
| LPCR_TC
|
6085 LPCR_LPES0
| LPCR_LPES1
| LPCR_HDICE
;
6086 pcc
->lpcr_pm
= LPCR_P7_PECE0
| LPCR_P7_PECE1
| LPCR_P7_PECE2
;
6087 pcc
->mmu_model
= POWERPC_MMU_2_06
;
6088 #if !defined(CONFIG_USER_ONLY)
6089 pcc
->hash64_opts
= &ppc_hash64_opts_POWER7
;
6090 pcc
->lrg_decr_bits
= 32;
6092 pcc
->excp_model
= POWERPC_EXCP_POWER7
;
6093 pcc
->bus_model
= PPC_FLAGS_INPUT_POWER7
;
6094 pcc
->bfd_mach
= bfd_mach_ppc64
;
6095 pcc
->flags
= POWERPC_FLAG_VRE
| POWERPC_FLAG_SE
|
6096 POWERPC_FLAG_BE
| POWERPC_FLAG_PMM
|
6097 POWERPC_FLAG_BUS_CLK
| POWERPC_FLAG_CFAR
|
6099 pcc
->l1_dcache_size
= 0x8000;
6100 pcc
->l1_icache_size
= 0x8000;
6103 static void init_proc_POWER8(CPUPPCState
*env
)
6105 /* Common Registers */
6106 init_proc_book3s_common(env
);
6107 register_sdr1_sprs(env
);
6108 register_book3s_207_dbg_sprs(env
);
6110 /* Common TCG PMU */
6111 init_tcg_pmu_power8(env
);
6113 /* POWER8 Specific Registers */
6114 register_book3s_ids_sprs(env
);
6115 register_rmor_sprs(env
);
6116 register_amr_sprs(env
);
6117 register_iamr_sprs(env
);
6118 register_book3s_purr_sprs(env
);
6119 register_power5p_common_sprs(env
);
6120 register_power5p_lpar_sprs(env
);
6121 register_power5p_ear_sprs(env
);
6122 register_power5p_tb_sprs(env
);
6123 register_power6_common_sprs(env
);
6124 register_HEIR32_spr(env
);
6125 register_power6_dbg_sprs(env
);
6126 register_power8_tce_address_control_sprs(env
);
6127 register_power8_ids_sprs(env
);
6128 register_power8_ebb_sprs(env
);
6129 register_power8_fscr_sprs(env
);
6130 register_power8_pmu_sup_sprs(env
);
6131 register_power8_pmu_user_sprs(env
);
6132 register_power8_tm_sprs(env
);
6133 register_power8_pspb_sprs(env
);
6134 register_power8_dpdes_sprs(env
);
6135 register_vtb_sprs(env
);
6136 register_power8_ic_sprs(env
);
6137 register_power8_book4_sprs(env
);
6138 register_power8_rpr_sprs(env
);
6141 env
->dcache_line_size
= 128;
6142 env
->icache_line_size
= 128;
6144 /* Allocate hardware IRQ controller */
6145 init_excp_POWER8(env
);
6146 ppcPOWER7_irq_init(env_archcpu(env
));
6149 static bool ppc_pvr_match_power8(PowerPCCPUClass
*pcc
, uint32_t pvr
, bool best
)
6151 uint32_t base
= pvr
& CPU_POWERPC_POWER_SERVER_MASK
;
6152 uint32_t pcc_base
= pcc
->pvr
& CPU_POWERPC_POWER_SERVER_MASK
;
6155 if (base
== CPU_POWERPC_POWER8_BASE
) {
6158 if (base
== CPU_POWERPC_POWER8E_BASE
) {
6161 if (base
== CPU_POWERPC_POWER8NVL_BASE
) {
6165 if (base
!= pcc_base
) {
6172 POWERPC_FAMILY(POWER8
)(ObjectClass
*oc
, void *data
)
6174 DeviceClass
*dc
= DEVICE_CLASS(oc
);
6175 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
6177 dc
->fw_name
= "PowerPC,POWER8";
6178 dc
->desc
= "POWER8";
6179 pcc
->pvr_match
= ppc_pvr_match_power8
;
6180 pcc
->pcr_mask
= PCR_TM_DIS
| PCR_COMPAT_2_06
| PCR_COMPAT_2_05
;
6181 pcc
->pcr_supported
= PCR_COMPAT_2_07
| PCR_COMPAT_2_06
| PCR_COMPAT_2_05
;
6182 pcc
->init_proc
= init_proc_POWER8
;
6183 pcc
->check_pow
= check_pow_nocheck
;
6184 pcc
->insns_flags
= PPC_INSNS_BASE
| PPC_ISEL
| PPC_STRING
| PPC_MFTB
|
6185 PPC_FLOAT
| PPC_FLOAT_FSEL
| PPC_FLOAT_FRES
|
6186 PPC_FLOAT_FSQRT
| PPC_FLOAT_FRSQRTE
|
6187 PPC_FLOAT_FRSQRTES
|
6190 PPC_CACHE
| PPC_CACHE_ICBI
| PPC_CACHE_DCBZ
|
6191 PPC_MEM_SYNC
| PPC_MEM_EIEIO
|
6192 PPC_MEM_TLBIE
| PPC_MEM_TLBSYNC
|
6193 PPC_64B
| PPC_64H
| PPC_64BX
| PPC_ALTIVEC
|
6194 PPC_SEGMENT_64B
| PPC_SLBI
|
6195 PPC_POPCNTB
| PPC_POPCNTWD
|
6197 pcc
->insns_flags2
= PPC2_VSX
| PPC2_VSX207
| PPC2_DFP
| PPC2_DBRX
|
6198 PPC2_PERM_ISA206
| PPC2_DIVE_ISA206
|
6199 PPC2_ATOMIC_ISA206
| PPC2_FP_CVT_ISA206
|
6200 PPC2_FP_TST_ISA206
| PPC2_BCTAR_ISA207
|
6201 PPC2_LSQ_ISA207
| PPC2_ALTIVEC_207
|
6202 PPC2_ISA205
| PPC2_ISA207S
| PPC2_FP_CVT_S64
|
6203 PPC2_TM
| PPC2_PM_ISA206
| PPC2_MEM_LWSYNC
|
6205 pcc
->msr_mask
= (1ull << MSR_SF
) |
6225 pcc
->lpcr_mask
= LPCR_VPM0
| LPCR_VPM1
| LPCR_ISL
| LPCR_KBV
|
6226 LPCR_DPFD
| LPCR_VRMASD
| LPCR_RMLS
| LPCR_ILE
|
6227 LPCR_AIL
| LPCR_ONL
| LPCR_P8_PECE0
| LPCR_P8_PECE1
|
6228 LPCR_P8_PECE2
| LPCR_P8_PECE3
| LPCR_P8_PECE4
|
6229 LPCR_MER
| LPCR_TC
| LPCR_LPES0
| LPCR_HDICE
;
6230 pcc
->lpcr_pm
= LPCR_P8_PECE0
| LPCR_P8_PECE1
| LPCR_P8_PECE2
|
6231 LPCR_P8_PECE3
| LPCR_P8_PECE4
;
6232 pcc
->mmu_model
= POWERPC_MMU_2_07
;
6233 #if !defined(CONFIG_USER_ONLY)
6234 pcc
->hash64_opts
= &ppc_hash64_opts_POWER7
;
6235 pcc
->lrg_decr_bits
= 32;
6236 pcc
->n_host_threads
= 8;
6238 pcc
->excp_model
= POWERPC_EXCP_POWER8
;
6239 pcc
->bus_model
= PPC_FLAGS_INPUT_POWER7
;
6240 pcc
->bfd_mach
= bfd_mach_ppc64
;
6241 pcc
->flags
= POWERPC_FLAG_VRE
| POWERPC_FLAG_SE
|
6242 POWERPC_FLAG_BE
| POWERPC_FLAG_PMM
|
6243 POWERPC_FLAG_BUS_CLK
| POWERPC_FLAG_CFAR
|
6244 POWERPC_FLAG_VSX
| POWERPC_FLAG_TM
;
6245 pcc
->l1_dcache_size
= 0x8000;
6246 pcc
->l1_icache_size
= 0x8000;
6249 #ifndef CONFIG_USER_ONLY
6251 * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings
6252 * Encoded as array of int_32s in the form:
6253 * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy
6255 * y -> radix mode supported page size (encoded as a shift)
6257 static struct ppc_radix_page_info POWER9_radix_page_info
= {
6260 0x0000000c, /* 4K - enc: 0x0 */
6261 0xa0000010, /* 64K - enc: 0x5 */
6262 0x20000015, /* 2M - enc: 0x1 */
6263 0x4000001e /* 1G - enc: 0x2 */
6266 #endif /* CONFIG_USER_ONLY */
6268 static void init_proc_POWER9(CPUPPCState
*env
)
6270 /* Common Registers */
6271 init_proc_book3s_common(env
);
6272 register_book3s_207_dbg_sprs(env
);
6274 /* Common TCG PMU */
6275 init_tcg_pmu_power8(env
);
6277 /* POWER8 Specific Registers */
6278 register_book3s_ids_sprs(env
);
6279 register_amr_sprs(env
);
6280 register_iamr_sprs(env
);
6281 register_book3s_purr_sprs(env
);
6282 register_power5p_common_sprs(env
);
6283 register_power5p_lpar_sprs(env
);
6284 register_power5p_ear_sprs(env
);
6285 register_power5p_tb_sprs(env
);
6286 register_power6_common_sprs(env
);
6287 register_HEIR32_spr(env
);
6288 register_power6_dbg_sprs(env
);
6289 register_power8_tce_address_control_sprs(env
);
6290 register_power8_ids_sprs(env
);
6291 register_power8_ebb_sprs(env
);
6292 register_power8_fscr_sprs(env
);
6293 register_power8_pmu_sup_sprs(env
);
6294 register_power8_pmu_user_sprs(env
);
6295 register_power8_tm_sprs(env
);
6296 register_power8_pspb_sprs(env
);
6297 register_power8_dpdes_sprs(env
);
6298 register_vtb_sprs(env
);
6299 register_power8_ic_sprs(env
);
6300 register_power9_book4_sprs(env
);
6301 register_power8_rpr_sprs(env
);
6302 register_power9_mmu_sprs(env
);
6304 /* POWER9 Specific registers */
6305 spr_register_kvm(env
, SPR_TIDR
, "TIDR", NULL
, NULL
,
6306 spr_read_generic
, spr_write_generic
,
6307 KVM_REG_PPC_TIDR
, 0);
6309 /* FIXME: Filter fields properly based on privilege level */
6310 spr_register_kvm_hv(env
, SPR_PSSCR
, "PSSCR", NULL
, NULL
, NULL
, NULL
,
6311 spr_read_generic
, spr_write_generic
,
6312 KVM_REG_PPC_PSSCR
, 0);
6315 env
->dcache_line_size
= 128;
6316 env
->icache_line_size
= 128;
6318 /* Allocate hardware IRQ controller */
6319 init_excp_POWER9(env
);
6320 ppcPOWER9_irq_init(env_archcpu(env
));
6323 static bool ppc_pvr_match_power9(PowerPCCPUClass
*pcc
, uint32_t pvr
, bool best
)
6325 uint32_t base
= pvr
& CPU_POWERPC_POWER_SERVER_MASK
;
6326 uint32_t pcc_base
= pcc
->pvr
& CPU_POWERPC_POWER_SERVER_MASK
;
6329 if (base
== CPU_POWERPC_POWER9_BASE
) {
6334 if (base
!= pcc_base
) {
6338 if ((pvr
& 0x0f00) != (pcc
->pvr
& 0x0f00)) {
6339 /* Major DD version does not match */
6343 if ((pvr
& 0x0f00) == 0x100) {
6344 /* DD1.x always matches power9_v1.0 */
6346 } else if ((pvr
& 0x0f00) == 0x200) {
6347 if ((pvr
& 0xf) < 2) {
6348 /* DD2.0, DD2.1 match power9_v2.0 */
6349 if ((pcc
->pvr
& 0xf) == 0) {
6353 /* DD2.2, DD2.3 match power9_v2.2 */
6354 if ((pcc
->pvr
& 0xf) == 2) {
6363 POWERPC_FAMILY(POWER9
)(ObjectClass
*oc
, void *data
)
6365 DeviceClass
*dc
= DEVICE_CLASS(oc
);
6366 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
6368 dc
->fw_name
= "PowerPC,POWER9";
6369 dc
->desc
= "POWER9";
6370 pcc
->pvr_match
= ppc_pvr_match_power9
;
6371 pcc
->pcr_mask
= PCR_COMPAT_2_05
| PCR_COMPAT_2_06
| PCR_COMPAT_2_07
;
6372 pcc
->pcr_supported
= PCR_COMPAT_3_00
| PCR_COMPAT_2_07
| PCR_COMPAT_2_06
|
6374 pcc
->init_proc
= init_proc_POWER9
;
6375 pcc
->check_pow
= check_pow_nocheck
;
6376 pcc
->insns_flags
= PPC_INSNS_BASE
| PPC_ISEL
| PPC_STRING
| PPC_MFTB
|
6377 PPC_FLOAT
| PPC_FLOAT_FSEL
| PPC_FLOAT_FRES
|
6378 PPC_FLOAT_FSQRT
| PPC_FLOAT_FRSQRTE
|
6379 PPC_FLOAT_FRSQRTES
|
6382 PPC_CACHE
| PPC_CACHE_ICBI
| PPC_CACHE_DCBZ
|
6383 PPC_MEM_SYNC
| PPC_MEM_EIEIO
|
6384 PPC_MEM_TLBIE
| PPC_MEM_TLBSYNC
|
6385 PPC_64B
| PPC_64H
| PPC_64BX
| PPC_ALTIVEC
|
6386 PPC_SEGMENT_64B
| PPC_SLBI
|
6387 PPC_POPCNTB
| PPC_POPCNTWD
|
6389 pcc
->insns_flags2
= PPC2_VSX
| PPC2_VSX207
| PPC2_DFP
| PPC2_DBRX
|
6390 PPC2_PERM_ISA206
| PPC2_DIVE_ISA206
|
6391 PPC2_ATOMIC_ISA206
| PPC2_FP_CVT_ISA206
|
6392 PPC2_FP_TST_ISA206
| PPC2_BCTAR_ISA207
|
6393 PPC2_LSQ_ISA207
| PPC2_ALTIVEC_207
|
6394 PPC2_ISA205
| PPC2_ISA207S
| PPC2_FP_CVT_S64
|
6395 PPC2_TM
| PPC2_ISA300
| PPC2_PRCNTL
| PPC2_MEM_LWSYNC
|
6397 pcc
->msr_mask
= (1ull << MSR_SF
) |
6415 pcc
->lpcr_mask
= LPCR_VPM1
| LPCR_ISL
| LPCR_KBV
| LPCR_DPFD
|
6416 (LPCR_PECE_U_MASK
& LPCR_HVEE
) | LPCR_ILE
| LPCR_AIL
|
6417 LPCR_UPRT
| LPCR_EVIRT
| LPCR_ONL
| LPCR_HR
| LPCR_LD
|
6418 (LPCR_PECE_L_MASK
& (LPCR_PDEE
| LPCR_HDEE
| LPCR_EEE
|
6419 LPCR_DEE
| LPCR_OEE
))
6420 | LPCR_MER
| LPCR_GTSE
| LPCR_TC
|
6421 LPCR_HEIC
| LPCR_LPES0
| LPCR_HVICE
| LPCR_HDICE
;
6422 pcc
->lpcr_pm
= LPCR_PDEE
| LPCR_HDEE
| LPCR_EEE
| LPCR_DEE
| LPCR_OEE
;
6423 pcc
->mmu_model
= POWERPC_MMU_3_00
;
6424 #if !defined(CONFIG_USER_ONLY)
6425 /* segment page size remain the same */
6426 pcc
->hash64_opts
= &ppc_hash64_opts_POWER7
;
6427 pcc
->radix_page_info
= &POWER9_radix_page_info
;
6428 pcc
->lrg_decr_bits
= 56;
6429 pcc
->n_host_threads
= 4;
6431 pcc
->excp_model
= POWERPC_EXCP_POWER9
;
6432 pcc
->bus_model
= PPC_FLAGS_INPUT_POWER9
;
6433 pcc
->bfd_mach
= bfd_mach_ppc64
;
6434 pcc
->flags
= POWERPC_FLAG_VRE
| POWERPC_FLAG_SE
|
6435 POWERPC_FLAG_BE
| POWERPC_FLAG_PMM
|
6436 POWERPC_FLAG_BUS_CLK
| POWERPC_FLAG_CFAR
|
6437 POWERPC_FLAG_VSX
| POWERPC_FLAG_TM
| POWERPC_FLAG_SCV
;
6438 pcc
->l1_dcache_size
= 0x8000;
6439 pcc
->l1_icache_size
= 0x8000;
6442 #ifndef CONFIG_USER_ONLY
6444 * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings
6445 * Encoded as array of int_32s in the form:
6446 * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy
6448 * y -> radix mode supported page size (encoded as a shift)
6450 static struct ppc_radix_page_info POWER10_radix_page_info
= {
6453 0x0000000c, /* 4K - enc: 0x0 */
6454 0xa0000010, /* 64K - enc: 0x5 */
6455 0x20000015, /* 2M - enc: 0x1 */
6456 0x4000001e /* 1G - enc: 0x2 */
6459 #endif /* !CONFIG_USER_ONLY */
6461 static void init_proc_POWER10(CPUPPCState
*env
)
6463 /* Common Registers */
6464 init_proc_book3s_common(env
);
6465 register_book3s_207_dbg_sprs(env
);
6467 /* Common TCG PMU */
6468 init_tcg_pmu_power8(env
);
6470 /* POWER8 Specific Registers */
6471 register_book3s_ids_sprs(env
);
6472 register_amr_sprs(env
);
6473 register_iamr_sprs(env
);
6474 register_book3s_purr_sprs(env
);
6475 register_power5p_common_sprs(env
);
6476 register_power5p_lpar_sprs(env
);
6477 register_power5p_ear_sprs(env
);
6478 register_power5p_tb_sprs(env
);
6479 register_power6_common_sprs(env
);
6480 register_HEIR64_spr(env
);
6481 register_power6_dbg_sprs(env
);
6482 register_power8_tce_address_control_sprs(env
);
6483 register_power8_ids_sprs(env
);
6484 register_power8_ebb_sprs(env
);
6485 register_power8_fscr_sprs(env
);
6486 register_power8_pmu_sup_sprs(env
);
6487 register_power8_pmu_user_sprs(env
);
6488 register_power8_tm_sprs(env
);
6489 register_power8_pspb_sprs(env
);
6490 register_power8_dpdes_sprs(env
);
6491 register_vtb_sprs(env
);
6492 register_power8_ic_sprs(env
);
6493 register_power9_book4_sprs(env
);
6494 register_power8_rpr_sprs(env
);
6495 register_power9_mmu_sprs(env
);
6496 register_power10_hash_sprs(env
);
6497 register_power10_dexcr_sprs(env
);
6499 /* FIXME: Filter fields properly based on privilege level */
6500 spr_register_kvm_hv(env
, SPR_PSSCR
, "PSSCR", NULL
, NULL
, NULL
, NULL
,
6501 spr_read_generic
, spr_write_generic
,
6502 KVM_REG_PPC_PSSCR
, 0);
6505 env
->dcache_line_size
= 128;
6506 env
->icache_line_size
= 128;
6508 /* Allocate hardware IRQ controller */
6509 init_excp_POWER10(env
);
6510 ppcPOWER9_irq_init(env_archcpu(env
));
6513 static bool ppc_pvr_match_power10(PowerPCCPUClass
*pcc
, uint32_t pvr
, bool best
)
6515 uint32_t base
= pvr
& CPU_POWERPC_POWER_SERVER_MASK
;
6516 uint32_t pcc_base
= pcc
->pvr
& CPU_POWERPC_POWER_SERVER_MASK
;
6519 if (base
== CPU_POWERPC_POWER10_BASE
) {
6524 if (base
!= pcc_base
) {
6528 if ((pvr
& 0x0f00) == (pcc
->pvr
& 0x0f00)) {
6529 /* Major DD version matches to power10_v1.0 and power10_v2.0 */
6536 POWERPC_FAMILY(POWER10
)(ObjectClass
*oc
, void *data
)
6538 DeviceClass
*dc
= DEVICE_CLASS(oc
);
6539 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
6541 dc
->fw_name
= "PowerPC,POWER10";
6542 dc
->desc
= "POWER10";
6543 pcc
->pvr_match
= ppc_pvr_match_power10
;
6544 pcc
->pcr_mask
= PCR_COMPAT_2_05
| PCR_COMPAT_2_06
| PCR_COMPAT_2_07
|
6546 pcc
->pcr_supported
= PCR_COMPAT_3_10
| PCR_COMPAT_3_00
| PCR_COMPAT_2_07
|
6547 PCR_COMPAT_2_06
| PCR_COMPAT_2_05
;
6548 pcc
->init_proc
= init_proc_POWER10
;
6549 pcc
->check_pow
= check_pow_nocheck
;
6550 pcc
->insns_flags
= PPC_INSNS_BASE
| PPC_ISEL
| PPC_STRING
| PPC_MFTB
|
6551 PPC_FLOAT
| PPC_FLOAT_FSEL
| PPC_FLOAT_FRES
|
6552 PPC_FLOAT_FSQRT
| PPC_FLOAT_FRSQRTE
|
6553 PPC_FLOAT_FRSQRTES
|
6556 PPC_CACHE
| PPC_CACHE_ICBI
| PPC_CACHE_DCBZ
|
6557 PPC_MEM_SYNC
| PPC_MEM_EIEIO
|
6558 PPC_MEM_TLBIE
| PPC_MEM_TLBSYNC
|
6559 PPC_64B
| PPC_64H
| PPC_64BX
| PPC_ALTIVEC
|
6560 PPC_SEGMENT_64B
| PPC_SLBI
|
6561 PPC_POPCNTB
| PPC_POPCNTWD
|
6563 pcc
->insns_flags2
= PPC2_VSX
| PPC2_VSX207
| PPC2_DFP
| PPC2_DBRX
|
6564 PPC2_PERM_ISA206
| PPC2_DIVE_ISA206
|
6565 PPC2_ATOMIC_ISA206
| PPC2_FP_CVT_ISA206
|
6566 PPC2_FP_TST_ISA206
| PPC2_BCTAR_ISA207
|
6567 PPC2_LSQ_ISA207
| PPC2_ALTIVEC_207
|
6568 PPC2_ISA205
| PPC2_ISA207S
| PPC2_FP_CVT_S64
|
6569 PPC2_TM
| PPC2_ISA300
| PPC2_PRCNTL
| PPC2_ISA310
|
6570 PPC2_MEM_LWSYNC
| PPC2_BCDA_ISA206
;
6571 pcc
->msr_mask
= (1ull << MSR_SF
) |
6589 pcc
->lpcr_mask
= LPCR_VPM1
| LPCR_ISL
| LPCR_KBV
| LPCR_DPFD
|
6590 (LPCR_PECE_U_MASK
& LPCR_HVEE
) | LPCR_ILE
| LPCR_AIL
|
6591 LPCR_UPRT
| LPCR_EVIRT
| LPCR_ONL
| LPCR_HR
| LPCR_LD
|
6592 (LPCR_PECE_L_MASK
& (LPCR_PDEE
| LPCR_HDEE
| LPCR_EEE
|
6593 LPCR_DEE
| LPCR_OEE
))
6594 | LPCR_MER
| LPCR_GTSE
| LPCR_TC
|
6595 LPCR_HEIC
| LPCR_LPES0
| LPCR_HVICE
| LPCR_HDICE
;
6596 /* DD2 adds an extra HAIL bit */
6597 pcc
->lpcr_mask
|= LPCR_HAIL
;
6599 pcc
->lpcr_pm
= LPCR_PDEE
| LPCR_HDEE
| LPCR_EEE
| LPCR_DEE
| LPCR_OEE
;
6600 pcc
->mmu_model
= POWERPC_MMU_3_00
;
6601 #if !defined(CONFIG_USER_ONLY)
6602 /* segment page size remain the same */
6603 pcc
->hash64_opts
= &ppc_hash64_opts_POWER7
;
6604 pcc
->radix_page_info
= &POWER10_radix_page_info
;
6605 pcc
->lrg_decr_bits
= 56;
6607 pcc
->excp_model
= POWERPC_EXCP_POWER10
;
6608 pcc
->bus_model
= PPC_FLAGS_INPUT_POWER9
;
6609 pcc
->bfd_mach
= bfd_mach_ppc64
;
6610 pcc
->flags
= POWERPC_FLAG_VRE
| POWERPC_FLAG_SE
|
6611 POWERPC_FLAG_BE
| POWERPC_FLAG_PMM
|
6612 POWERPC_FLAG_BUS_CLK
| POWERPC_FLAG_CFAR
|
6613 POWERPC_FLAG_VSX
| POWERPC_FLAG_TM
| POWERPC_FLAG_SCV
;
6614 pcc
->l1_dcache_size
= 0x8000;
6615 pcc
->l1_icache_size
= 0x8000;
6618 #if !defined(CONFIG_USER_ONLY)
6619 void cpu_ppc_set_vhyp(PowerPCCPU
*cpu
, PPCVirtualHypervisor
*vhyp
)
6621 CPUPPCState
*env
= &cpu
->env
;
6626 * With a virtual hypervisor mode we never allow the CPU to go
6627 * hypervisor mode itself
6629 env
->msr_mask
&= ~MSR_HVB
;
6632 void cpu_ppc_set_1lpar(PowerPCCPU
*cpu
)
6634 CPUPPCState
*env
= &cpu
->env
;
6637 * pseries SMT means "LPAR per core" mode, e.g., msgsndp is usable
6640 if (env
->flags
& POWERPC_FLAG_SMT
) {
6641 env
->flags
|= POWERPC_FLAG_SMT_1LPAR
;
6644 #endif /* !defined(CONFIG_USER_ONLY) */
6646 #endif /* defined(TARGET_PPC64) */
6648 /*****************************************************************************/
6649 /* Generic CPU instantiation routine */
6650 static void init_ppc_proc(PowerPCCPU
*cpu
)
6652 PowerPCCPUClass
*pcc
= POWERPC_CPU_GET_CLASS(cpu
);
6653 CPUPPCState
*env
= &cpu
->env
;
6654 #if !defined(CONFIG_USER_ONLY)
6657 /* Set all exception vectors to an invalid address */
6658 for (i
= 0; i
< POWERPC_EXCP_NB
; i
++) {
6659 env
->excp_vectors
[i
] = (target_ulong
)(-1ULL);
6661 env
->ivor_mask
= 0x00000000;
6662 env
->ivpr_mask
= 0x00000000;
6663 /* Default MMU definitions */
6667 env
->tlb_type
= TLB_NONE
;
6669 /* Register SPR common to all PowerPC implementations */
6670 register_generic_sprs(cpu
);
6672 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */
6673 (*pcc
->init_proc
)(env
);
6675 #if !defined(CONFIG_USER_ONLY)
6676 ppc_gdb_gen_spr_xml(cpu
);
6679 /* MSR bits & flags consistency checks */
6680 if (env
->msr_mask
& (1 << 25)) {
6681 switch (env
->flags
& (POWERPC_FLAG_SPE
| POWERPC_FLAG_VRE
)) {
6682 case POWERPC_FLAG_SPE
:
6683 case POWERPC_FLAG_VRE
:
6686 fprintf(stderr
, "PowerPC MSR definition inconsistency\n"
6687 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n");
6690 } else if (env
->flags
& (POWERPC_FLAG_SPE
| POWERPC_FLAG_VRE
)) {
6691 fprintf(stderr
, "PowerPC MSR definition inconsistency\n"
6692 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n");
6695 if (env
->msr_mask
& (1 << 17)) {
6696 switch (env
->flags
& (POWERPC_FLAG_TGPR
| POWERPC_FLAG_CE
)) {
6697 case POWERPC_FLAG_TGPR
:
6698 case POWERPC_FLAG_CE
:
6701 fprintf(stderr
, "PowerPC MSR definition inconsistency\n"
6702 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n");
6705 } else if (env
->flags
& (POWERPC_FLAG_TGPR
| POWERPC_FLAG_CE
)) {
6706 fprintf(stderr
, "PowerPC MSR definition inconsistency\n"
6707 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n");
6710 if (env
->msr_mask
& (1 << 10)) {
6711 switch (env
->flags
& (POWERPC_FLAG_SE
| POWERPC_FLAG_DWE
|
6712 POWERPC_FLAG_UBLE
)) {
6713 case POWERPC_FLAG_SE
:
6714 case POWERPC_FLAG_DWE
:
6715 case POWERPC_FLAG_UBLE
:
6718 fprintf(stderr
, "PowerPC MSR definition inconsistency\n"
6719 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or "
6720 "POWERPC_FLAG_UBLE\n");
6723 } else if (env
->flags
& (POWERPC_FLAG_SE
| POWERPC_FLAG_DWE
|
6724 POWERPC_FLAG_UBLE
)) {
6725 fprintf(stderr
, "PowerPC MSR definition inconsistency\n"
6726 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor "
6727 "POWERPC_FLAG_UBLE\n");
6730 if (env
->msr_mask
& (1 << 9)) {
6731 switch (env
->flags
& (POWERPC_FLAG_BE
| POWERPC_FLAG_DE
)) {
6732 case POWERPC_FLAG_BE
:
6733 case POWERPC_FLAG_DE
:
6736 fprintf(stderr
, "PowerPC MSR definition inconsistency\n"
6737 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n");
6740 } else if (env
->flags
& (POWERPC_FLAG_BE
| POWERPC_FLAG_DE
)) {
6741 fprintf(stderr
, "PowerPC MSR definition inconsistency\n"
6742 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n");
6745 if (env
->msr_mask
& (1 << 2)) {
6746 switch (env
->flags
& (POWERPC_FLAG_PX
| POWERPC_FLAG_PMM
)) {
6747 case POWERPC_FLAG_PX
:
6748 case POWERPC_FLAG_PMM
:
6751 fprintf(stderr
, "PowerPC MSR definition inconsistency\n"
6752 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n");
6755 } else if (env
->flags
& (POWERPC_FLAG_PX
| POWERPC_FLAG_PMM
)) {
6756 fprintf(stderr
, "PowerPC MSR definition inconsistency\n"
6757 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n");
6760 if ((env
->flags
& POWERPC_FLAG_BUS_CLK
) == 0) {
6761 fprintf(stderr
, "PowerPC flags inconsistency\n"
6762 "Should define the time-base and decrementer clock source\n");
6765 /* Allocate TLBs buffer when needed */
6766 #if !defined(CONFIG_USER_ONLY)
6767 if (env
->nb_tlb
!= 0) {
6768 int nb_tlb
= env
->nb_tlb
;
6769 if (env
->id_tlbs
!= 0) {
6772 switch (env
->tlb_type
) {
6774 env
->tlb
.tlb6
= g_new0(ppc6xx_tlb_t
, nb_tlb
);
6777 env
->tlb
.tlbe
= g_new0(ppcemb_tlb_t
, nb_tlb
);
6780 env
->tlb
.tlbm
= g_new0(ppcmas_tlb_t
, nb_tlb
);
6783 /* Pre-compute some useful values */
6784 env
->tlb_per_way
= env
->nb_tlb
/ env
->nb_ways
;
6787 if (env
->check_pow
== NULL
) {
6788 warn_report("no power management check handler registered."
6789 " Attempt QEMU to crash very soon !");
6794 static void ppc_cpu_realize(DeviceState
*dev
, Error
**errp
)
6796 CPUState
*cs
= CPU(dev
);
6797 PowerPCCPU
*cpu
= POWERPC_CPU(dev
);
6798 CPUPPCState
*env
= &cpu
->env
;
6799 PowerPCCPUClass
*pcc
= POWERPC_CPU_GET_CLASS(cpu
);
6800 Error
*local_err
= NULL
;
6802 cpu_exec_realizefn(cs
, &local_err
);
6803 if (local_err
!= NULL
) {
6804 error_propagate(errp
, local_err
);
6807 if (cpu
->vcpu_id
== UNASSIGNED_CPU_INDEX
) {
6808 cpu
->vcpu_id
= cs
->cpu_index
;
6811 if (tcg_enabled()) {
6812 if (ppc_fixup_cpu(cpu
) != 0) {
6813 error_setg(errp
, "Unable to emulate selected CPU with TCG");
6818 create_ppc_opcodes(cpu
, &local_err
);
6819 if (local_err
!= NULL
) {
6820 error_propagate(errp
, local_err
);
6825 ppc_gdb_init(cs
, pcc
);
6828 pcc
->parent_realize(dev
, errp
);
6830 if (env_cpu(env
)->nr_threads
> 1) {
6831 env
->flags
|= POWERPC_FLAG_SMT
;
6837 cpu_exec_unrealizefn(cs
);
6840 static void ppc_cpu_unrealize(DeviceState
*dev
)
6842 PowerPCCPU
*cpu
= POWERPC_CPU(dev
);
6843 PowerPCCPUClass
*pcc
= POWERPC_CPU_GET_CLASS(cpu
);
6845 pcc
->parent_unrealize(dev
);
6847 cpu_remove_sync(CPU(cpu
));
6849 destroy_ppc_opcodes(cpu
);
6852 static gint
ppc_cpu_compare_class_pvr(gconstpointer a
, gconstpointer b
)
6854 ObjectClass
*oc
= (ObjectClass
*)a
;
6855 uint32_t pvr
= *(uint32_t *)b
;
6856 PowerPCCPUClass
*pcc
= (PowerPCCPUClass
*)a
;
6858 /* -cpu host does a PVR lookup during construction */
6859 if (unlikely(strcmp(object_class_get_name(oc
),
6860 TYPE_HOST_POWERPC_CPU
) == 0)) {
6864 return pcc
->pvr
== pvr
? 0 : -1;
6867 PowerPCCPUClass
*ppc_cpu_class_by_pvr(uint32_t pvr
)
6869 GSList
*list
, *item
;
6870 PowerPCCPUClass
*pcc
= NULL
;
6872 list
= object_class_get_list(TYPE_POWERPC_CPU
, false);
6873 item
= g_slist_find_custom(list
, &pvr
, ppc_cpu_compare_class_pvr
);
6875 pcc
= POWERPC_CPU_CLASS(item
->data
);
6882 static gint
ppc_cpu_compare_class_pvr_mask(gconstpointer a
, gconstpointer b
)
6884 ObjectClass
*oc
= (ObjectClass
*)a
;
6885 uint32_t pvr
= *(uint32_t *)b
;
6886 PowerPCCPUClass
*pcc
= (PowerPCCPUClass
*)a
;
6888 /* -cpu host does a PVR lookup during construction */
6889 if (unlikely(strcmp(object_class_get_name(oc
),
6890 TYPE_HOST_POWERPC_CPU
) == 0)) {
6894 if (pcc
->pvr_match(pcc
, pvr
, true)) {
6901 PowerPCCPUClass
*ppc_cpu_class_by_pvr_mask(uint32_t pvr
)
6903 GSList
*list
, *item
;
6904 PowerPCCPUClass
*pcc
= NULL
;
6906 list
= object_class_get_list(TYPE_POWERPC_CPU
, true);
6907 item
= g_slist_find_custom(list
, &pvr
, ppc_cpu_compare_class_pvr_mask
);
6909 pcc
= POWERPC_CPU_CLASS(item
->data
);
6916 static const char *ppc_cpu_lookup_alias(const char *alias
)
6920 for (ai
= 0; ppc_cpu_aliases
[ai
].alias
!= NULL
; ai
++) {
6921 if (strcmp(ppc_cpu_aliases
[ai
].alias
, alias
) == 0) {
6922 return ppc_cpu_aliases
[ai
].model
;
6929 ObjectClass
*ppc_cpu_class_by_name(const char *name
)
6931 char *cpu_model
, *typename
;
6937 * Lookup by PVR if cpu_model is valid 8 digit hex number (excl:
6938 * 0x prefix if present)
6940 if (!qemu_strtoul(name
, &p
, 16, &pvr
)) {
6942 len
= (len
== 10) && (name
[1] == 'x') ? len
- 2 : len
;
6943 if ((len
== 8) && (*p
== '\0')) {
6944 return OBJECT_CLASS(ppc_cpu_class_by_pvr(pvr
));
6949 * All ppc CPUs represent hardware that exists in the real world, i.e.: we
6950 * do not have a "max" CPU with all possible emulated features enabled.
6951 * Return the default CPU type for the machine because that has greater
6952 * chance of being useful as the "max" CPU.
6954 #if !defined(CONFIG_USER_ONLY)
6955 if (strcmp(name
, "max") == 0) {
6956 MachineClass
*mc
= MACHINE_GET_CLASS(qdev_get_machine());
6958 return object_class_by_name(mc
->default_cpu_type
);
6963 cpu_model
= g_ascii_strdown(name
, -1);
6964 p
= ppc_cpu_lookup_alias(cpu_model
);
6967 cpu_model
= g_strdup(p
);
6970 typename
= g_strdup_printf("%s" POWERPC_CPU_TYPE_SUFFIX
, cpu_model
);
6971 oc
= object_class_by_name(typename
);
6978 PowerPCCPUClass
*ppc_cpu_get_family_class(PowerPCCPUClass
*pcc
)
6980 ObjectClass
*oc
= OBJECT_CLASS(pcc
);
6982 while (oc
&& !object_class_is_abstract(oc
)) {
6983 oc
= object_class_get_parent(oc
);
6987 return POWERPC_CPU_CLASS(oc
);
6990 /* Sort by PVR, ordering special case "host" last. */
6991 static gint
ppc_cpu_list_compare(gconstpointer a
, gconstpointer b
)
6993 ObjectClass
*oc_a
= (ObjectClass
*)a
;
6994 ObjectClass
*oc_b
= (ObjectClass
*)b
;
6995 PowerPCCPUClass
*pcc_a
= POWERPC_CPU_CLASS(oc_a
);
6996 PowerPCCPUClass
*pcc_b
= POWERPC_CPU_CLASS(oc_b
);
6997 const char *name_a
= object_class_get_name(oc_a
);
6998 const char *name_b
= object_class_get_name(oc_b
);
7000 if (strcmp(name_a
, TYPE_HOST_POWERPC_CPU
) == 0) {
7002 } else if (strcmp(name_b
, TYPE_HOST_POWERPC_CPU
) == 0) {
7005 /* Avoid an integer overflow during subtraction */
7006 if (pcc_a
->pvr
< pcc_b
->pvr
) {
7008 } else if (pcc_a
->pvr
> pcc_b
->pvr
) {
7016 static void ppc_cpu_list_entry(gpointer data
, gpointer user_data
)
7018 ObjectClass
*oc
= data
;
7019 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
7020 DeviceClass
*family
= DEVICE_CLASS(ppc_cpu_get_family_class(pcc
));
7021 const char *typename
= object_class_get_name(oc
);
7025 if (unlikely(strcmp(typename
, TYPE_HOST_POWERPC_CPU
) == 0)) {
7029 name
= g_strndup(typename
,
7030 strlen(typename
) - strlen(POWERPC_CPU_TYPE_SUFFIX
));
7031 qemu_printf("PowerPC %-16s PVR %08x\n", name
, pcc
->pvr
);
7032 for (i
= 0; ppc_cpu_aliases
[i
].alias
!= NULL
; i
++) {
7033 PowerPCCPUAlias
*alias
= &ppc_cpu_aliases
[i
];
7034 ObjectClass
*alias_oc
= ppc_cpu_class_by_name(alias
->model
);
7036 if (alias_oc
!= oc
) {
7040 * If running with KVM, we might update the family alias later, so
7041 * avoid printing the wrong alias here and use "preferred" instead
7043 if (strcmp(alias
->alias
, family
->desc
) == 0) {
7044 qemu_printf("PowerPC %-16s (alias for preferred %s CPU)\n",
7045 alias
->alias
, family
->desc
);
7047 qemu_printf("PowerPC %-16s (alias for %s)\n",
7048 alias
->alias
, name
);
7054 void ppc_cpu_list(void)
7058 list
= object_class_get_list(TYPE_POWERPC_CPU
, false);
7059 list
= g_slist_sort(list
, ppc_cpu_list_compare
);
7060 g_slist_foreach(list
, ppc_cpu_list_entry
, NULL
);
7065 qemu_printf("PowerPC %s\n", "host");
7069 static void ppc_cpu_set_pc(CPUState
*cs
, vaddr value
)
7071 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
7073 cpu
->env
.nip
= value
;
7076 static vaddr
ppc_cpu_get_pc(CPUState
*cs
)
7078 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
7080 return cpu
->env
.nip
;
7084 static void ppc_restore_state_to_opc(CPUState
*cs
,
7085 const TranslationBlock
*tb
,
7086 const uint64_t *data
)
7088 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
7090 cpu
->env
.nip
= data
[0];
7092 #endif /* CONFIG_TCG */
7094 static bool ppc_cpu_has_work(CPUState
*cs
)
7096 return cs
->interrupt_request
& CPU_INTERRUPT_HARD
;
7099 static void ppc_cpu_reset_hold(Object
*obj
)
7101 CPUState
*s
= CPU(obj
);
7102 PowerPCCPU
*cpu
= POWERPC_CPU(s
);
7103 PowerPCCPUClass
*pcc
= POWERPC_CPU_GET_CLASS(cpu
);
7104 CPUPPCState
*env
= &cpu
->env
;
7108 if (pcc
->parent_phases
.hold
) {
7109 pcc
->parent_phases
.hold(obj
);
7112 msr
= (target_ulong
)0;
7113 msr
|= (target_ulong
)MSR_HVB
;
7114 msr
|= (target_ulong
)1 << MSR_EP
;
7115 #if defined(DO_SINGLE_STEP) && 0
7116 /* Single step trace mode */
7117 msr
|= (target_ulong
)1 << MSR_SE
;
7118 msr
|= (target_ulong
)1 << MSR_BE
;
7120 #if defined(CONFIG_USER_ONLY)
7121 msr
|= (target_ulong
)1 << MSR_FP
; /* Allow floating point usage */
7122 msr
|= (target_ulong
)1 << MSR_FE0
; /* Allow floating point exceptions */
7123 msr
|= (target_ulong
)1 << MSR_FE1
;
7124 msr
|= (target_ulong
)1 << MSR_VR
; /* Allow altivec usage */
7125 msr
|= (target_ulong
)1 << MSR_VSX
; /* Allow VSX usage */
7126 msr
|= (target_ulong
)1 << MSR_SPE
; /* Allow SPE usage */
7127 msr
|= (target_ulong
)1 << MSR_PR
;
7128 #if defined(TARGET_PPC64)
7129 msr
|= (target_ulong
)1 << MSR_TM
; /* Transactional memory */
7131 #if !TARGET_BIG_ENDIAN
7132 msr
|= (target_ulong
)1 << MSR_LE
; /* Little-endian user mode */
7133 if (!((env
->msr_mask
>> MSR_LE
) & 1)) {
7134 fprintf(stderr
, "Selected CPU does not support little-endian.\n");
7140 #if defined(TARGET_PPC64)
7141 if (mmu_is_64bit(env
->mmu_model
)) {
7142 msr
|= (1ULL << MSR_SF
);
7146 hreg_store_msr(env
, msr
, 1);
7148 #if !defined(CONFIG_USER_ONLY)
7149 env
->nip
= env
->hreset_vector
| env
->excp_prefix
;
7151 if (tcg_enabled()) {
7152 if (env
->mmu_model
!= POWERPC_MMU_REAL
) {
7153 ppc_tlb_invalidate_all(env
);
7155 pmu_mmcr01_updated(env
);
7158 /* clean any pending stop state */
7159 env
->resume_as_sreset
= 0;
7161 hreg_compute_hflags(env
);
7162 env
->reserve_addr
= (target_ulong
)-1ULL;
7163 /* Be sure no exception or interrupt is pending */
7164 env
->pending_interrupts
= 0;
7165 s
->exception_index
= POWERPC_EXCP_NONE
;
7166 env
->error_code
= 0;
7169 /* tininess for underflow is detected before rounding */
7170 set_float_detect_tininess(float_tininess_before_rounding
,
7173 for (i
= 0; i
< ARRAY_SIZE(env
->spr_cb
); i
++) {
7174 ppc_spr_t
*spr
= &env
->spr_cb
[i
];
7179 env
->spr
[i
] = spr
->default_value
;
7183 #ifndef CONFIG_USER_ONLY
7185 static bool ppc_cpu_is_big_endian(CPUState
*cs
)
7187 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
7188 CPUPPCState
*env
= &cpu
->env
;
7190 cpu_synchronize_state(cs
);
7192 return !FIELD_EX64(env
->msr
, MSR
, LE
);
7195 static bool ppc_get_irq_stats(InterruptStatsProvider
*obj
,
7196 uint64_t **irq_counts
, unsigned int *nb_irqs
)
7198 CPUPPCState
*env
= &POWERPC_CPU(obj
)->env
;
7200 *irq_counts
= env
->excp_stats
;
7201 *nb_irqs
= ARRAY_SIZE(env
->excp_stats
);
7206 static void ppc_cpu_exec_enter(CPUState
*cs
)
7208 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
7211 PPCVirtualHypervisorClass
*vhc
=
7212 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu
->vhyp
);
7213 vhc
->cpu_exec_enter(cpu
->vhyp
, cpu
);
7217 static void ppc_cpu_exec_exit(CPUState
*cs
)
7219 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
7222 PPCVirtualHypervisorClass
*vhc
=
7223 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu
->vhyp
);
7224 vhc
->cpu_exec_exit(cpu
->vhyp
, cpu
);
7227 #endif /* CONFIG_TCG */
7229 #endif /* !CONFIG_USER_ONLY */
7231 static void ppc_cpu_instance_init(Object
*obj
)
7233 PowerPCCPU
*cpu
= POWERPC_CPU(obj
);
7234 PowerPCCPUClass
*pcc
= POWERPC_CPU_GET_CLASS(cpu
);
7235 CPUPPCState
*env
= &cpu
->env
;
7237 cpu_set_cpustate_pointers(cpu
);
7238 cpu
->vcpu_id
= UNASSIGNED_CPU_INDEX
;
7240 env
->msr_mask
= pcc
->msr_mask
;
7241 env
->mmu_model
= pcc
->mmu_model
;
7242 env
->excp_model
= pcc
->excp_model
;
7243 env
->bus_model
= pcc
->bus_model
;
7244 env
->insns_flags
= pcc
->insns_flags
;
7245 env
->insns_flags2
= pcc
->insns_flags2
;
7246 env
->flags
= pcc
->flags
;
7247 env
->bfd_mach
= pcc
->bfd_mach
;
7248 env
->check_pow
= pcc
->check_pow
;
7251 * Mark HV mode as supported if the CPU has an MSR_HV bit in the
7252 * msr_mask. The mask can later be cleared by PAPR mode but the hv
7253 * mode support will remain, thus enforcing that we cannot use
7254 * priv. instructions in guest in PAPR mode. For 970 we currently
7255 * simply don't set HV in msr_mask thus simulating an "Apple mode"
7256 * 970. If we ever want to support 970 HV mode, we'll have to add
7257 * a processor attribute of some sort.
7259 #if !defined(CONFIG_USER_ONLY)
7260 env
->has_hv_mode
= !!(env
->msr_mask
& MSR_HVB
);
7263 ppc_hash64_init(cpu
);
7266 static void ppc_cpu_instance_finalize(Object
*obj
)
7268 PowerPCCPU
*cpu
= POWERPC_CPU(obj
);
7270 ppc_hash64_finalize(cpu
);
7273 static bool ppc_pvr_match_default(PowerPCCPUClass
*pcc
, uint32_t pvr
, bool best
)
7275 return pcc
->pvr
== pvr
;
7278 static void ppc_disas_set_info(CPUState
*cs
, disassemble_info
*info
)
7280 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
7281 CPUPPCState
*env
= &cpu
->env
;
7283 if ((env
->hflags
>> MSR_LE
) & 1) {
7284 info
->endian
= BFD_ENDIAN_LITTLE
;
7286 info
->mach
= env
->bfd_mach
;
7287 if (!env
->bfd_mach
) {
7289 info
->mach
= bfd_mach_ppc64
;
7291 info
->mach
= bfd_mach_ppc
;
7295 info
->cap_arch
= CS_ARCH_PPC
;
7297 info
->cap_mode
= CS_MODE_64
;
7301 static Property ppc_cpu_properties
[] = {
7302 DEFINE_PROP_BOOL("pre-2.8-migration", PowerPCCPU
, pre_2_8_migration
, false),
7303 DEFINE_PROP_BOOL("pre-2.10-migration", PowerPCCPU
, pre_2_10_migration
,
7305 DEFINE_PROP_BOOL("pre-3.0-migration", PowerPCCPU
, pre_3_0_migration
,
7307 DEFINE_PROP_END_OF_LIST(),
7310 #ifndef CONFIG_USER_ONLY
7311 #include "hw/core/sysemu-cpu-ops.h"
7313 static const struct SysemuCPUOps ppc_sysemu_ops
= {
7314 .get_phys_page_debug
= ppc_cpu_get_phys_page_debug
,
7315 .write_elf32_note
= ppc32_cpu_write_elf32_note
,
7316 .write_elf64_note
= ppc64_cpu_write_elf64_note
,
7317 .virtio_is_big_endian
= ppc_cpu_is_big_endian
,
7318 .legacy_vmsd
= &vmstate_ppc_cpu
,
7323 #include "hw/core/tcg-cpu-ops.h"
7325 static const struct TCGCPUOps ppc_tcg_ops
= {
7326 .initialize
= ppc_translate_init
,
7327 .restore_state_to_opc
= ppc_restore_state_to_opc
,
7329 #ifdef CONFIG_USER_ONLY
7330 .record_sigsegv
= ppc_cpu_record_sigsegv
,
7332 .tlb_fill
= ppc_cpu_tlb_fill
,
7333 .cpu_exec_interrupt
= ppc_cpu_exec_interrupt
,
7334 .do_interrupt
= ppc_cpu_do_interrupt
,
7335 .cpu_exec_enter
= ppc_cpu_exec_enter
,
7336 .cpu_exec_exit
= ppc_cpu_exec_exit
,
7337 .do_unaligned_access
= ppc_cpu_do_unaligned_access
,
7338 #endif /* !CONFIG_USER_ONLY */
7340 #endif /* CONFIG_TCG */
7342 static void ppc_cpu_class_init(ObjectClass
*oc
, void *data
)
7344 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
7345 CPUClass
*cc
= CPU_CLASS(oc
);
7346 DeviceClass
*dc
= DEVICE_CLASS(oc
);
7347 ResettableClass
*rc
= RESETTABLE_CLASS(oc
);
7349 device_class_set_parent_realize(dc
, ppc_cpu_realize
,
7350 &pcc
->parent_realize
);
7351 device_class_set_parent_unrealize(dc
, ppc_cpu_unrealize
,
7352 &pcc
->parent_unrealize
);
7353 pcc
->pvr_match
= ppc_pvr_match_default
;
7354 device_class_set_props(dc
, ppc_cpu_properties
);
7356 resettable_class_set_parent_phases(rc
, NULL
, ppc_cpu_reset_hold
, NULL
,
7357 &pcc
->parent_phases
);
7359 cc
->class_by_name
= ppc_cpu_class_by_name
;
7360 cc
->has_work
= ppc_cpu_has_work
;
7361 cc
->dump_state
= ppc_cpu_dump_state
;
7362 cc
->set_pc
= ppc_cpu_set_pc
;
7363 cc
->get_pc
= ppc_cpu_get_pc
;
7364 cc
->gdb_read_register
= ppc_cpu_gdb_read_register
;
7365 cc
->gdb_write_register
= ppc_cpu_gdb_write_register
;
7366 #ifndef CONFIG_USER_ONLY
7367 cc
->sysemu_ops
= &ppc_sysemu_ops
;
7368 INTERRUPT_STATS_PROVIDER_CLASS(oc
)->get_statistics
= ppc_get_irq_stats
;
7371 cc
->gdb_num_core_regs
= 71;
7372 #ifndef CONFIG_USER_ONLY
7373 cc
->gdb_get_dynamic_xml
= ppc_gdb_get_dynamic_xml
;
7375 #ifdef USE_APPLE_GDB
7376 cc
->gdb_read_register
= ppc_cpu_gdb_read_register_apple
;
7377 cc
->gdb_write_register
= ppc_cpu_gdb_write_register_apple
;
7378 cc
->gdb_num_core_regs
= 71 + 32;
7381 cc
->gdb_arch_name
= ppc_gdb_arch_name
;
7382 #if defined(TARGET_PPC64)
7383 cc
->gdb_core_xml_file
= "power64-core.xml";
7385 cc
->gdb_core_xml_file
= "power-core.xml";
7387 cc
->disas_set_info
= ppc_disas_set_info
;
7389 dc
->fw_name
= "PowerPC,UNKNOWN";
7392 cc
->tcg_ops
= &ppc_tcg_ops
;
7393 #endif /* CONFIG_TCG */
7396 static const TypeInfo ppc_cpu_type_info
= {
7397 .name
= TYPE_POWERPC_CPU
,
7399 .instance_size
= sizeof(PowerPCCPU
),
7400 .instance_align
= __alignof__(PowerPCCPU
),
7401 .instance_init
= ppc_cpu_instance_init
,
7402 .instance_finalize
= ppc_cpu_instance_finalize
,
7404 .class_size
= sizeof(PowerPCCPUClass
),
7405 .class_init
= ppc_cpu_class_init
,
7406 #ifndef CONFIG_USER_ONLY
7407 .interfaces
= (InterfaceInfo
[]) {
7408 { TYPE_INTERRUPT_STATS_PROVIDER
},
7414 #ifndef CONFIG_USER_ONLY
7415 static const TypeInfo ppc_vhyp_type_info
= {
7416 .name
= TYPE_PPC_VIRTUAL_HYPERVISOR
,
7417 .parent
= TYPE_INTERFACE
,
7418 .class_size
= sizeof(PPCVirtualHypervisorClass
),
7422 static void ppc_cpu_register_types(void)
7424 type_register_static(&ppc_cpu_type_info
);
7425 #ifndef CONFIG_USER_ONLY
7426 type_register_static(&ppc_vhyp_type_info
);
7430 void ppc_cpu_dump_state(CPUState
*cs
, FILE *f
, int flags
)
7435 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
7436 CPUPPCState
*env
= &cpu
->env
;
7439 qemu_fprintf(f
, "NIP " TARGET_FMT_lx
" LR " TARGET_FMT_lx
" CTR "
7440 TARGET_FMT_lx
" XER " TARGET_FMT_lx
" CPU#%d\n",
7441 env
->nip
, env
->lr
, env
->ctr
, cpu_read_xer(env
),
7443 qemu_fprintf(f
, "MSR " TARGET_FMT_lx
" HID0 " TARGET_FMT_lx
" HF "
7444 "%08x iidx %d didx %d\n",
7445 env
->msr
, env
->spr
[SPR_HID0
], env
->hflags
,
7446 cpu_mmu_index(env
, true), cpu_mmu_index(env
, false));
7447 #if !defined(CONFIG_USER_ONLY)
7449 qemu_fprintf(f
, "TB %08" PRIu32
" %08" PRIu64
7450 " DECR " TARGET_FMT_lu
"\n", cpu_ppc_load_tbu(env
),
7451 cpu_ppc_load_tbl(env
), cpu_ppc_load_decr(env
));
7454 qemu_fprintf(f
, "TB %08" PRIu32
" %08" PRIu64
"\n", cpu_ppc_load_tbu(env
),
7455 cpu_ppc_load_tbl(env
));
7457 for (i
= 0; i
< 32; i
++) {
7458 if ((i
& (RGPL
- 1)) == 0) {
7459 qemu_fprintf(f
, "GPR%02d", i
);
7461 qemu_fprintf(f
, " %016" PRIx64
, ppc_dump_gpr(env
, i
));
7462 if ((i
& (RGPL
- 1)) == (RGPL
- 1)) {
7463 qemu_fprintf(f
, "\n");
7466 qemu_fprintf(f
, "CR ");
7467 for (i
= 0; i
< 8; i
++)
7468 qemu_fprintf(f
, "%01x", env
->crf
[i
]);
7469 qemu_fprintf(f
, " [");
7470 for (i
= 0; i
< 8; i
++) {
7472 if (env
->crf
[i
] & 0x08) {
7474 } else if (env
->crf
[i
] & 0x04) {
7476 } else if (env
->crf
[i
] & 0x02) {
7479 qemu_fprintf(f
, " %c%c", a
, env
->crf
[i
] & 0x01 ? 'O' : ' ');
7481 qemu_fprintf(f
, " ] RES %03x@" TARGET_FMT_lx
"\n",
7482 (int)env
->reserve_length
, env
->reserve_addr
);
7484 if (flags
& CPU_DUMP_FPU
) {
7485 for (i
= 0; i
< 32; i
++) {
7486 if ((i
& (RFPL
- 1)) == 0) {
7487 qemu_fprintf(f
, "FPR%02d", i
);
7489 qemu_fprintf(f
, " %016" PRIx64
, *cpu_fpr_ptr(env
, i
));
7490 if ((i
& (RFPL
- 1)) == (RFPL
- 1)) {
7491 qemu_fprintf(f
, "\n");
7494 qemu_fprintf(f
, "FPSCR " TARGET_FMT_lx
"\n", env
->fpscr
);
7497 #if !defined(CONFIG_USER_ONLY)
7498 qemu_fprintf(f
, " SRR0 " TARGET_FMT_lx
" SRR1 " TARGET_FMT_lx
7499 " PVR " TARGET_FMT_lx
" VRSAVE " TARGET_FMT_lx
"\n",
7500 env
->spr
[SPR_SRR0
], env
->spr
[SPR_SRR1
],
7501 env
->spr
[SPR_PVR
], env
->spr
[SPR_VRSAVE
]);
7503 qemu_fprintf(f
, "SPRG0 " TARGET_FMT_lx
" SPRG1 " TARGET_FMT_lx
7504 " SPRG2 " TARGET_FMT_lx
" SPRG3 " TARGET_FMT_lx
"\n",
7505 env
->spr
[SPR_SPRG0
], env
->spr
[SPR_SPRG1
],
7506 env
->spr
[SPR_SPRG2
], env
->spr
[SPR_SPRG3
]);
7508 qemu_fprintf(f
, "SPRG4 " TARGET_FMT_lx
" SPRG5 " TARGET_FMT_lx
7509 " SPRG6 " TARGET_FMT_lx
" SPRG7 " TARGET_FMT_lx
"\n",
7510 env
->spr
[SPR_SPRG4
], env
->spr
[SPR_SPRG5
],
7511 env
->spr
[SPR_SPRG6
], env
->spr
[SPR_SPRG7
]);
7513 switch (env
->excp_model
) {
7514 #if defined(TARGET_PPC64)
7515 case POWERPC_EXCP_POWER7
:
7516 case POWERPC_EXCP_POWER8
:
7517 case POWERPC_EXCP_POWER9
:
7518 case POWERPC_EXCP_POWER10
:
7519 qemu_fprintf(f
, "HSRR0 " TARGET_FMT_lx
" HSRR1 " TARGET_FMT_lx
"\n",
7520 env
->spr
[SPR_HSRR0
], env
->spr
[SPR_HSRR1
]);
7523 case POWERPC_EXCP_BOOKE
:
7524 qemu_fprintf(f
, "CSRR0 " TARGET_FMT_lx
" CSRR1 " TARGET_FMT_lx
7525 " MCSRR0 " TARGET_FMT_lx
" MCSRR1 " TARGET_FMT_lx
"\n",
7526 env
->spr
[SPR_BOOKE_CSRR0
], env
->spr
[SPR_BOOKE_CSRR1
],
7527 env
->spr
[SPR_BOOKE_MCSRR0
], env
->spr
[SPR_BOOKE_MCSRR1
]);
7529 qemu_fprintf(f
, " TCR " TARGET_FMT_lx
" TSR " TARGET_FMT_lx
7530 " ESR " TARGET_FMT_lx
" DEAR " TARGET_FMT_lx
"\n",
7531 env
->spr
[SPR_BOOKE_TCR
], env
->spr
[SPR_BOOKE_TSR
],
7532 env
->spr
[SPR_BOOKE_ESR
], env
->spr
[SPR_BOOKE_DEAR
]);
7534 qemu_fprintf(f
, " PIR " TARGET_FMT_lx
" DECAR " TARGET_FMT_lx
7535 " IVPR " TARGET_FMT_lx
" EPCR " TARGET_FMT_lx
"\n",
7536 env
->spr
[SPR_BOOKE_PIR
], env
->spr
[SPR_BOOKE_DECAR
],
7537 env
->spr
[SPR_BOOKE_IVPR
], env
->spr
[SPR_BOOKE_EPCR
]);
7539 qemu_fprintf(f
, " MCSR " TARGET_FMT_lx
" SPRG8 " TARGET_FMT_lx
7540 " EPR " TARGET_FMT_lx
"\n",
7541 env
->spr
[SPR_BOOKE_MCSR
], env
->spr
[SPR_BOOKE_SPRG8
],
7542 env
->spr
[SPR_BOOKE_EPR
]);
7545 qemu_fprintf(f
, " MCAR " TARGET_FMT_lx
" PID1 " TARGET_FMT_lx
7546 " PID2 " TARGET_FMT_lx
" SVR " TARGET_FMT_lx
"\n",
7547 env
->spr
[SPR_Exxx_MCAR
], env
->spr
[SPR_BOOKE_PID1
],
7548 env
->spr
[SPR_BOOKE_PID2
], env
->spr
[SPR_E500_SVR
]);
7551 * IVORs are left out as they are large and do not change often --
7552 * they can be read with "p $ivor0", "p $ivor1", etc.
7555 case POWERPC_EXCP_40x
:
7556 qemu_fprintf(f
, " TCR " TARGET_FMT_lx
" TSR " TARGET_FMT_lx
7557 " ESR " TARGET_FMT_lx
" DEAR " TARGET_FMT_lx
"\n",
7558 env
->spr
[SPR_40x_TCR
], env
->spr
[SPR_40x_TSR
],
7559 env
->spr
[SPR_40x_ESR
], env
->spr
[SPR_40x_DEAR
]);
7561 qemu_fprintf(f
, " EVPR " TARGET_FMT_lx
" SRR2 " TARGET_FMT_lx
7562 " SRR3 " TARGET_FMT_lx
" PID " TARGET_FMT_lx
"\n",
7563 env
->spr
[SPR_40x_EVPR
], env
->spr
[SPR_40x_SRR2
],
7564 env
->spr
[SPR_40x_SRR3
], env
->spr
[SPR_40x_PID
]);
7570 #if defined(TARGET_PPC64)
7571 if (env
->flags
& POWERPC_FLAG_CFAR
) {
7572 qemu_fprintf(f
, " CFAR " TARGET_FMT_lx
"\n", env
->cfar
);
7576 if (env
->spr_cb
[SPR_LPCR
].name
) {
7577 qemu_fprintf(f
, " LPCR " TARGET_FMT_lx
"\n", env
->spr
[SPR_LPCR
]);
7580 switch (env
->mmu_model
) {
7581 case POWERPC_MMU_32B
:
7582 case POWERPC_MMU_SOFT_6xx
:
7583 #if defined(TARGET_PPC64)
7584 case POWERPC_MMU_64B
:
7585 case POWERPC_MMU_2_03
:
7586 case POWERPC_MMU_2_06
:
7587 case POWERPC_MMU_2_07
:
7588 case POWERPC_MMU_3_00
:
7590 if (env
->spr_cb
[SPR_SDR1
].name
) { /* SDR1 Exists */
7591 qemu_fprintf(f
, " SDR1 " TARGET_FMT_lx
" ", env
->spr
[SPR_SDR1
]);
7593 if (env
->spr_cb
[SPR_PTCR
].name
) { /* PTCR Exists */
7594 qemu_fprintf(f
, " PTCR " TARGET_FMT_lx
" ", env
->spr
[SPR_PTCR
]);
7596 qemu_fprintf(f
, " DAR " TARGET_FMT_lx
" DSISR " TARGET_FMT_lx
"\n",
7597 env
->spr
[SPR_DAR
], env
->spr
[SPR_DSISR
]);
7599 case POWERPC_MMU_BOOKE206
:
7600 qemu_fprintf(f
, " MAS0 " TARGET_FMT_lx
" MAS1 " TARGET_FMT_lx
7601 " MAS2 " TARGET_FMT_lx
" MAS3 " TARGET_FMT_lx
"\n",
7602 env
->spr
[SPR_BOOKE_MAS0
], env
->spr
[SPR_BOOKE_MAS1
],
7603 env
->spr
[SPR_BOOKE_MAS2
], env
->spr
[SPR_BOOKE_MAS3
]);
7605 qemu_fprintf(f
, " MAS4 " TARGET_FMT_lx
" MAS6 " TARGET_FMT_lx
7606 " MAS7 " TARGET_FMT_lx
" PID " TARGET_FMT_lx
"\n",
7607 env
->spr
[SPR_BOOKE_MAS4
], env
->spr
[SPR_BOOKE_MAS6
],
7608 env
->spr
[SPR_BOOKE_MAS7
], env
->spr
[SPR_BOOKE_PID
]);
7610 qemu_fprintf(f
, "MMUCFG " TARGET_FMT_lx
" TLB0CFG " TARGET_FMT_lx
7611 " TLB1CFG " TARGET_FMT_lx
"\n",
7612 env
->spr
[SPR_MMUCFG
], env
->spr
[SPR_BOOKE_TLB0CFG
],
7613 env
->spr
[SPR_BOOKE_TLB1CFG
]);
7623 type_init(ppc_cpu_register_types
)