include/exec/cpu_ldst.h

   1 /*
   2  *  Software MMU support
   3  *
   4  * This library is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU Lesser General Public
   6  * License as published by the Free Software Foundation; either
   7  * version 2.1 of the License, or (at your option) any later version.
   8  *
   9  * This library is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  12  * Lesser General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU Lesser General Public
  15  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  16  *
  17  */
  18
  19 /*
  20  * Generate inline load/store functions for all MMU modes (typically
  21  * at least _user and _kernel) as well as _data versions, for all data
  22  * sizes.
  23  *
  24  * Used by target op helpers.
  25  *
  26  * The syntax for the accessors is:
  27  *
  28  * load:  cpu_ld{sign}{size}{end}_{mmusuffix}(env, ptr)
  29  *        cpu_ld{sign}{size}{end}_{mmusuffix}_ra(env, ptr, retaddr)
  30  *        cpu_ld{sign}{size}{end}_mmuidx_ra(env, ptr, mmu_idx, retaddr)
  31  *        cpu_ld{sign}{size}{end}_mmu(env, ptr, oi, retaddr)
  32  *
  33  * store: cpu_st{size}{end}_{mmusuffix}(env, ptr, val)
  34  *        cpu_st{size}{end}_{mmusuffix}_ra(env, ptr, val, retaddr)
  35  *        cpu_st{size}{end}_mmuidx_ra(env, ptr, val, mmu_idx, retaddr)
  36  *        cpu_st{size}{end}_mmu(env, ptr, val, oi, retaddr)
  37  *
  38  * sign is:
  39  * (empty): for 32 and 64 bit sizes
  40  *   u    : unsigned
  41  *   s    : signed
  42  *
  43  * size is:
  44  *   b: 8 bits
  45  *   w: 16 bits
  46  *   l: 32 bits
  47  *   q: 64 bits
  48  *
  49  * end is:
  50  * (empty): for target native endian, or for 8 bit access
  51  *     _be: for forced big endian
  52  *     _le: for forced little endian
  53  *
  54  * mmusuffix is one of the generic suffixes "data" or "code", or "mmuidx".
  55  * The "mmuidx" suffix carries an extra mmu_idx argument that specifies
  56  * the index to use; the "data" and "code" suffixes take the index from
  57  * cpu_mmu_index().
  58  *
  59  * The "mmu" suffix carries the full MemOpIdx, with both mmu_idx and the
  60  * MemOp including alignment requirements.  The alignment will be enforced.
  61  */
  62 #ifndef CPU_LDST_H
  63 #define CPU_LDST_H
  64
  65 #include "exec/memopidx.h"
  66 #include "exec/abi_ptr.h"
  67 #include "exec/mmu-access-type.h"
  68 #include "qemu/int128.h"
  69 #include "cpu.h"
  70
  71 #if defined(CONFIG_USER_ONLY)
  72
  73 #ifndef TARGET_TAGGED_ADDRESSES
  74 static inline abi_ptr cpu_untagged_addr(CPUState *cs, abi_ptr x)
  75 {
  76     return x;
  77 }
  78 #endif
  79
  80 /* All direct uses of g2h and h2g need to go away for usermode softmmu.  */
  81 static inline void *g2h_untagged(abi_ptr x)
  82 {
  83     return (void *)((uintptr_t)(x) + guest_base);
  84 }
  85
  86 static inline void *g2h(CPUState *cs, abi_ptr x)
  87 {
  88     return g2h_untagged(cpu_untagged_addr(cs, x));
  89 }
  90
  91 static inline bool guest_addr_valid_untagged(abi_ulong x)
  92 {
  93     return x <= GUEST_ADDR_MAX;
  94 }
  95
  96 static inline bool guest_range_valid_untagged(abi_ulong start, abi_ulong len)
  97 {
  98     return len - 1 <= GUEST_ADDR_MAX && start <= GUEST_ADDR_MAX - len + 1;
  99 }
 100
 101 #define h2g_valid(x) \
 102     (HOST_LONG_BITS <= TARGET_VIRT_ADDR_SPACE_BITS || \
 103      (uintptr_t)(x) - guest_base <= GUEST_ADDR_MAX)
 104
 105 #define h2g_nocheck(x) ({ \
 106     uintptr_t __ret = (uintptr_t)(x) - guest_base; \
 107     (abi_ptr)__ret; \
 108 })
 109
 110 #define h2g(x) ({ \
 111     /* Check if given address fits target address space */ \
 112     assert(h2g_valid(x)); \
 113     h2g_nocheck(x); \
 114 })
 115
 116 #endif /* CONFIG_USER_ONLY */
 117
 118 uint32_t cpu_ldub_data(CPUArchState *env, abi_ptr ptr);
 119 int cpu_ldsb_data(CPUArchState *env, abi_ptr ptr);
 120 uint32_t cpu_lduw_be_data(CPUArchState *env, abi_ptr ptr);
 121 int cpu_ldsw_be_data(CPUArchState *env, abi_ptr ptr);
 122 uint32_t cpu_ldl_be_data(CPUArchState *env, abi_ptr ptr);
 123 uint64_t cpu_ldq_be_data(CPUArchState *env, abi_ptr ptr);
 124 uint32_t cpu_lduw_le_data(CPUArchState *env, abi_ptr ptr);
 125 int cpu_ldsw_le_data(CPUArchState *env, abi_ptr ptr);
 126 uint32_t cpu_ldl_le_data(CPUArchState *env, abi_ptr ptr);
 127 uint64_t cpu_ldq_le_data(CPUArchState *env, abi_ptr ptr);
 128
 129 uint32_t cpu_ldub_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
 130 int cpu_ldsb_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
 131 uint32_t cpu_lduw_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
 132 int cpu_ldsw_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
 133 uint32_t cpu_ldl_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
 134 uint64_t cpu_ldq_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
 135 uint32_t cpu_lduw_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
 136 int cpu_ldsw_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
 137 uint32_t cpu_ldl_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
 138 uint64_t cpu_ldq_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
 139
 140 void cpu_stb_data(CPUArchState *env, abi_ptr ptr, uint32_t val);
 141 void cpu_stw_be_data(CPUArchState *env, abi_ptr ptr, uint32_t val);
 142 void cpu_stl_be_data(CPUArchState *env, abi_ptr ptr, uint32_t val);
 143 void cpu_stq_be_data(CPUArchState *env, abi_ptr ptr, uint64_t val);
 144 void cpu_stw_le_data(CPUArchState *env, abi_ptr ptr, uint32_t val);
 145 void cpu_stl_le_data(CPUArchState *env, abi_ptr ptr, uint32_t val);
 146 void cpu_stq_le_data(CPUArchState *env, abi_ptr ptr, uint64_t val);
 147
 148 void cpu_stb_data_ra(CPUArchState *env, abi_ptr ptr,
 149                      uint32_t val, uintptr_t ra);
 150 void cpu_stw_be_data_ra(CPUArchState *env, abi_ptr ptr,
 151                         uint32_t val, uintptr_t ra);
 152 void cpu_stl_be_data_ra(CPUArchState *env, abi_ptr ptr,
 153                         uint32_t val, uintptr_t ra);
 154 void cpu_stq_be_data_ra(CPUArchState *env, abi_ptr ptr,
 155                         uint64_t val, uintptr_t ra);
 156 void cpu_stw_le_data_ra(CPUArchState *env, abi_ptr ptr,
 157                         uint32_t val, uintptr_t ra);
 158 void cpu_stl_le_data_ra(CPUArchState *env, abi_ptr ptr,
 159                         uint32_t val, uintptr_t ra);
 160 void cpu_stq_le_data_ra(CPUArchState *env, abi_ptr ptr,
 161                         uint64_t val, uintptr_t ra);
 162
 163 uint32_t cpu_ldub_mmuidx_ra(CPUArchState *env, abi_ptr ptr,
 164                             int mmu_idx, uintptr_t ra);
 165 int cpu_ldsb_mmuidx_ra(CPUArchState *env, abi_ptr ptr,
 166                        int mmu_idx, uintptr_t ra);
 167 uint32_t cpu_lduw_be_mmuidx_ra(CPUArchState *env, abi_ptr ptr,
 168                                int mmu_idx, uintptr_t ra);
 169 int cpu_ldsw_be_mmuidx_ra(CPUArchState *env, abi_ptr ptr,
 170                           int mmu_idx, uintptr_t ra);
 171 uint32_t cpu_ldl_be_mmuidx_ra(CPUArchState *env, abi_ptr ptr,
 172                               int mmu_idx, uintptr_t ra);
 173 uint64_t cpu_ldq_be_mmuidx_ra(CPUArchState *env, abi_ptr ptr,
 174                               int mmu_idx, uintptr_t ra);
 175 uint32_t cpu_lduw_le_mmuidx_ra(CPUArchState *env, abi_ptr ptr,
 176                                int mmu_idx, uintptr_t ra);
 177 int cpu_ldsw_le_mmuidx_ra(CPUArchState *env, abi_ptr ptr,
 178                           int mmu_idx, uintptr_t ra);
 179 uint32_t cpu_ldl_le_mmuidx_ra(CPUArchState *env, abi_ptr ptr,
 180                               int mmu_idx, uintptr_t ra);
 181 uint64_t cpu_ldq_le_mmuidx_ra(CPUArchState *env, abi_ptr ptr,
 182                               int mmu_idx, uintptr_t ra);
 183
 184 void cpu_stb_mmuidx_ra(CPUArchState *env, abi_ptr ptr, uint32_t val,
 185                        int mmu_idx, uintptr_t ra);
 186 void cpu_stw_be_mmuidx_ra(CPUArchState *env, abi_ptr ptr, uint32_t val,
 187                           int mmu_idx, uintptr_t ra);
 188 void cpu_stl_be_mmuidx_ra(CPUArchState *env, abi_ptr ptr, uint32_t val,
 189                           int mmu_idx, uintptr_t ra);
 190 void cpu_stq_be_mmuidx_ra(CPUArchState *env, abi_ptr ptr, uint64_t val,
 191                           int mmu_idx, uintptr_t ra);
 192 void cpu_stw_le_mmuidx_ra(CPUArchState *env, abi_ptr ptr, uint32_t val,
 193                           int mmu_idx, uintptr_t ra);
 194 void cpu_stl_le_mmuidx_ra(CPUArchState *env, abi_ptr ptr, uint32_t val,
 195                           int mmu_idx, uintptr_t ra);
 196 void cpu_stq_le_mmuidx_ra(CPUArchState *env, abi_ptr ptr, uint64_t val,
 197                           int mmu_idx, uintptr_t ra);
 198
 199 uint8_t cpu_ldb_mmu(CPUArchState *env, abi_ptr ptr, MemOpIdx oi, uintptr_t ra);
 200 uint16_t cpu_ldw_mmu(CPUArchState *env, abi_ptr ptr, MemOpIdx oi, uintptr_t ra);
 201 uint32_t cpu_ldl_mmu(CPUArchState *env, abi_ptr ptr, MemOpIdx oi, uintptr_t ra);
 202 uint64_t cpu_ldq_mmu(CPUArchState *env, abi_ptr ptr, MemOpIdx oi, uintptr_t ra);
 203 Int128 cpu_ld16_mmu(CPUArchState *env, abi_ptr addr, MemOpIdx oi, uintptr_t ra);
 204
 205 void cpu_stb_mmu(CPUArchState *env, abi_ptr ptr, uint8_t val,
 206                  MemOpIdx oi, uintptr_t ra);
 207 void cpu_stw_mmu(CPUArchState *env, abi_ptr ptr, uint16_t val,
 208                  MemOpIdx oi, uintptr_t ra);
 209 void cpu_stl_mmu(CPUArchState *env, abi_ptr ptr, uint32_t val,
 210                  MemOpIdx oi, uintptr_t ra);
 211 void cpu_stq_mmu(CPUArchState *env, abi_ptr ptr, uint64_t val,
 212                  MemOpIdx oi, uintptr_t ra);
 213 void cpu_st16_mmu(CPUArchState *env, abi_ptr addr, Int128 val,
 214                   MemOpIdx oi, uintptr_t ra);
 215
 216 uint32_t cpu_atomic_cmpxchgb_mmu(CPUArchState *env, abi_ptr addr,
 217                                  uint32_t cmpv, uint32_t newv,
 218                                  MemOpIdx oi, uintptr_t retaddr);
 219 uint32_t cpu_atomic_cmpxchgw_le_mmu(CPUArchState *env, abi_ptr addr,
 220                                     uint32_t cmpv, uint32_t newv,
 221                                     MemOpIdx oi, uintptr_t retaddr);
 222 uint32_t cpu_atomic_cmpxchgl_le_mmu(CPUArchState *env, abi_ptr addr,
 223                                     uint32_t cmpv, uint32_t newv,
 224                                     MemOpIdx oi, uintptr_t retaddr);
 225 uint64_t cpu_atomic_cmpxchgq_le_mmu(CPUArchState *env, abi_ptr addr,
 226                                     uint64_t cmpv, uint64_t newv,
 227                                     MemOpIdx oi, uintptr_t retaddr);
 228 uint32_t cpu_atomic_cmpxchgw_be_mmu(CPUArchState *env, abi_ptr addr,
 229                                     uint32_t cmpv, uint32_t newv,
 230                                     MemOpIdx oi, uintptr_t retaddr);
 231 uint32_t cpu_atomic_cmpxchgl_be_mmu(CPUArchState *env, abi_ptr addr,
 232                                     uint32_t cmpv, uint32_t newv,
 233                                     MemOpIdx oi, uintptr_t retaddr);
 234 uint64_t cpu_atomic_cmpxchgq_be_mmu(CPUArchState *env, abi_ptr addr,
 235                                     uint64_t cmpv, uint64_t newv,
 236                                     MemOpIdx oi, uintptr_t retaddr);
 237
 238 #define GEN_ATOMIC_HELPER(NAME, TYPE, SUFFIX)   \
 239 TYPE cpu_atomic_ ## NAME ## SUFFIX ## _mmu      \
 240     (CPUArchState *env, abi_ptr addr, TYPE val, \
 241      MemOpIdx oi, uintptr_t retaddr);
 242
 243 #ifdef CONFIG_ATOMIC64
 244 #define GEN_ATOMIC_HELPER_ALL(NAME)          \
 245     GEN_ATOMIC_HELPER(NAME, uint32_t, b)     \
 246     GEN_ATOMIC_HELPER(NAME, uint32_t, w_le)  \
 247     GEN_ATOMIC_HELPER(NAME, uint32_t, w_be)  \
 248     GEN_ATOMIC_HELPER(NAME, uint32_t, l_le)  \
 249     GEN_ATOMIC_HELPER(NAME, uint32_t, l_be)  \
 250     GEN_ATOMIC_HELPER(NAME, uint64_t, q_le)  \
 251     GEN_ATOMIC_HELPER(NAME, uint64_t, q_be)
 252 #else
 253 #define GEN_ATOMIC_HELPER_ALL(NAME)          \
 254     GEN_ATOMIC_HELPER(NAME, uint32_t, b)     \
 255     GEN_ATOMIC_HELPER(NAME, uint32_t, w_le)  \
 256     GEN_ATOMIC_HELPER(NAME, uint32_t, w_be)  \
 257     GEN_ATOMIC_HELPER(NAME, uint32_t, l_le)  \
 258     GEN_ATOMIC_HELPER(NAME, uint32_t, l_be)
 259 #endif
 260
 261 GEN_ATOMIC_HELPER_ALL(fetch_add)
 262 GEN_ATOMIC_HELPER_ALL(fetch_sub)
 263 GEN_ATOMIC_HELPER_ALL(fetch_and)
 264 GEN_ATOMIC_HELPER_ALL(fetch_or)
 265 GEN_ATOMIC_HELPER_ALL(fetch_xor)
 266 GEN_ATOMIC_HELPER_ALL(fetch_smin)
 267 GEN_ATOMIC_HELPER_ALL(fetch_umin)
 268 GEN_ATOMIC_HELPER_ALL(fetch_smax)
 269 GEN_ATOMIC_HELPER_ALL(fetch_umax)
 270
 271 GEN_ATOMIC_HELPER_ALL(add_fetch)
 272 GEN_ATOMIC_HELPER_ALL(sub_fetch)
 273 GEN_ATOMIC_HELPER_ALL(and_fetch)
 274 GEN_ATOMIC_HELPER_ALL(or_fetch)
 275 GEN_ATOMIC_HELPER_ALL(xor_fetch)
 276 GEN_ATOMIC_HELPER_ALL(smin_fetch)
 277 GEN_ATOMIC_HELPER_ALL(umin_fetch)
 278 GEN_ATOMIC_HELPER_ALL(smax_fetch)
 279 GEN_ATOMIC_HELPER_ALL(umax_fetch)
 280
 281 GEN_ATOMIC_HELPER_ALL(xchg)
 282
 283 #undef GEN_ATOMIC_HELPER_ALL
 284 #undef GEN_ATOMIC_HELPER
 285
 286 Int128 cpu_atomic_cmpxchgo_le_mmu(CPUArchState *env, abi_ptr addr,
 287                                   Int128 cmpv, Int128 newv,
 288                                   MemOpIdx oi, uintptr_t retaddr);
 289 Int128 cpu_atomic_cmpxchgo_be_mmu(CPUArchState *env, abi_ptr addr,
 290                                   Int128 cmpv, Int128 newv,
 291                                   MemOpIdx oi, uintptr_t retaddr);
 292
 293 #if !defined(CONFIG_USER_ONLY)
 294
 295 #include "tcg/oversized-guest.h"
 296
 297 static inline uint64_t tlb_read_idx(const CPUTLBEntry *entry,
 298                                     MMUAccessType access_type)
 299 {
 300     /* Do not rearrange the CPUTLBEntry structure members. */
 301     QEMU_BUILD_BUG_ON(offsetof(CPUTLBEntry, addr_read) !=
 302                       MMU_DATA_LOAD * sizeof(uint64_t));
 303     QEMU_BUILD_BUG_ON(offsetof(CPUTLBEntry, addr_write) !=
 304                       MMU_DATA_STORE * sizeof(uint64_t));
 305     QEMU_BUILD_BUG_ON(offsetof(CPUTLBEntry, addr_code) !=
 306                       MMU_INST_FETCH * sizeof(uint64_t));
 307
 308 #if TARGET_LONG_BITS == 32
 309     /* Use qatomic_read, in case of addr_write; only care about low bits. */
 310     const uint32_t *ptr = (uint32_t *)&entry->addr_idx[access_type];
 311     ptr += HOST_BIG_ENDIAN;
 312     return qatomic_read(ptr);
 313 #else
 314     const uint64_t *ptr = &entry->addr_idx[access_type];
 315 # if TCG_OVERSIZED_GUEST
 316     return *ptr;
 317 # else
 318     /* ofs might correspond to .addr_write, so use qatomic_read */
 319     return qatomic_read(ptr);
 320 # endif
 321 #endif
 322 }
 323
 324 static inline uint64_t tlb_addr_write(const CPUTLBEntry *entry)
 325 {
 326     return tlb_read_idx(entry, MMU_DATA_STORE);
 327 }
 328
 329 /* Find the TLB index corresponding to the mmu_idx + address pair.  */
 330 static inline uintptr_t tlb_index(CPUState *cpu, uintptr_t mmu_idx,
 331                                   vaddr addr)
 332 {
 333     uintptr_t size_mask = cpu->neg.tlb.f[mmu_idx].mask >> CPU_TLB_ENTRY_BITS;
 334
 335     return (addr >> TARGET_PAGE_BITS) & size_mask;
 336 }
 337
 338 /* Find the TLB entry corresponding to the mmu_idx + address pair.  */
 339 static inline CPUTLBEntry *tlb_entry(CPUState *cpu, uintptr_t mmu_idx,
 340                                      vaddr addr)
 341 {
 342     return &cpu->neg.tlb.f[mmu_idx].table[tlb_index(cpu, mmu_idx, addr)];
 343 }
 344
 345 #endif /* !defined(CONFIG_USER_ONLY) */
 346
 347 #if TARGET_BIG_ENDIAN
 348 # define cpu_lduw_data        cpu_lduw_be_data
 349 # define cpu_ldsw_data        cpu_ldsw_be_data
 350 # define cpu_ldl_data         cpu_ldl_be_data
 351 # define cpu_ldq_data         cpu_ldq_be_data
 352 # define cpu_lduw_data_ra     cpu_lduw_be_data_ra
 353 # define cpu_ldsw_data_ra     cpu_ldsw_be_data_ra
 354 # define cpu_ldl_data_ra      cpu_ldl_be_data_ra
 355 # define cpu_ldq_data_ra      cpu_ldq_be_data_ra
 356 # define cpu_lduw_mmuidx_ra   cpu_lduw_be_mmuidx_ra
 357 # define cpu_ldsw_mmuidx_ra   cpu_ldsw_be_mmuidx_ra
 358 # define cpu_ldl_mmuidx_ra    cpu_ldl_be_mmuidx_ra
 359 # define cpu_ldq_mmuidx_ra    cpu_ldq_be_mmuidx_ra
 360 # define cpu_stw_data         cpu_stw_be_data
 361 # define cpu_stl_data         cpu_stl_be_data
 362 # define cpu_stq_data         cpu_stq_be_data
 363 # define cpu_stw_data_ra      cpu_stw_be_data_ra
 364 # define cpu_stl_data_ra      cpu_stl_be_data_ra
 365 # define cpu_stq_data_ra      cpu_stq_be_data_ra
 366 # define cpu_stw_mmuidx_ra    cpu_stw_be_mmuidx_ra
 367 # define cpu_stl_mmuidx_ra    cpu_stl_be_mmuidx_ra
 368 # define cpu_stq_mmuidx_ra    cpu_stq_be_mmuidx_ra
 369 #else
 370 # define cpu_lduw_data        cpu_lduw_le_data
 371 # define cpu_ldsw_data        cpu_ldsw_le_data
 372 # define cpu_ldl_data         cpu_ldl_le_data
 373 # define cpu_ldq_data         cpu_ldq_le_data
 374 # define cpu_lduw_data_ra     cpu_lduw_le_data_ra
 375 # define cpu_ldsw_data_ra     cpu_ldsw_le_data_ra
 376 # define cpu_ldl_data_ra      cpu_ldl_le_data_ra
 377 # define cpu_ldq_data_ra      cpu_ldq_le_data_ra
 378 # define cpu_lduw_mmuidx_ra   cpu_lduw_le_mmuidx_ra
 379 # define cpu_ldsw_mmuidx_ra   cpu_ldsw_le_mmuidx_ra
 380 # define cpu_ldl_mmuidx_ra    cpu_ldl_le_mmuidx_ra
 381 # define cpu_ldq_mmuidx_ra    cpu_ldq_le_mmuidx_ra
 382 # define cpu_stw_data         cpu_stw_le_data
 383 # define cpu_stl_data         cpu_stl_le_data
 384 # define cpu_stq_data         cpu_stq_le_data
 385 # define cpu_stw_data_ra      cpu_stw_le_data_ra
 386 # define cpu_stl_data_ra      cpu_stl_le_data_ra
 387 # define cpu_stq_data_ra      cpu_stq_le_data_ra
 388 # define cpu_stw_mmuidx_ra    cpu_stw_le_mmuidx_ra
 389 # define cpu_stl_mmuidx_ra    cpu_stl_le_mmuidx_ra
 390 # define cpu_stq_mmuidx_ra    cpu_stq_le_mmuidx_ra
 391 #endif
 392
 393 uint8_t cpu_ldb_code_mmu(CPUArchState *env, abi_ptr addr,
 394                          MemOpIdx oi, uintptr_t ra);
 395 uint16_t cpu_ldw_code_mmu(CPUArchState *env, abi_ptr addr,
 396                           MemOpIdx oi, uintptr_t ra);
 397 uint32_t cpu_ldl_code_mmu(CPUArchState *env, abi_ptr addr,
 398                           MemOpIdx oi, uintptr_t ra);
 399 uint64_t cpu_ldq_code_mmu(CPUArchState *env, abi_ptr addr,
 400                           MemOpIdx oi, uintptr_t ra);
 401
 402 uint32_t cpu_ldub_code(CPUArchState *env, abi_ptr addr);
 403 uint32_t cpu_lduw_code(CPUArchState *env, abi_ptr addr);
 404 uint32_t cpu_ldl_code(CPUArchState *env, abi_ptr addr);
 405 uint64_t cpu_ldq_code(CPUArchState *env, abi_ptr addr);
 406
 407 static inline int cpu_ldsb_code(CPUArchState *env, abi_ptr addr)
 408 {
 409     return (int8_t)cpu_ldub_code(env, addr);
 410 }
 411
 412 static inline int cpu_ldsw_code(CPUArchState *env, abi_ptr addr)
 413 {
 414     return (int16_t)cpu_lduw_code(env, addr);
 415 }
 416
 417 /**
 418  * tlb_vaddr_to_host:
 419  * @env: CPUArchState
 420  * @addr: guest virtual address to look up
 421  * @access_type: 0 for read, 1 for write, 2 for execute
 422  * @mmu_idx: MMU index to use for lookup
 423  *
 424  * Look up the specified guest virtual index in the TCG softmmu TLB.
 425  * If we can translate a host virtual address suitable for direct RAM
 426  * access, without causing a guest exception, then return it.
 427  * Otherwise (TLB entry is for an I/O access, guest software
 428  * TLB fill required, etc) return NULL.
 429  */
 430 #ifdef CONFIG_USER_ONLY
 431 static inline void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr,
 432                                       MMUAccessType access_type, int mmu_idx)
 433 {
 434     return g2h(env_cpu(env), addr);
 435 }
 436 #else
 437 void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr,
 438                         MMUAccessType access_type, int mmu_idx);
 439 #endif
 440
 441 #endif /* CPU_LDST_H */