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hw/usb/ohci: Code style fix white space errors
[qemu/armbru.git] / hw / usb / hcd-ohci.c
blob9d6bb8312e36dde2ed761d04e176d40afec60bc7
1 /*
2 * QEMU USB OHCI Emulation
3 * Copyright (c) 2004 Gianni Tedesco
4 * Copyright (c) 2006 CodeSourcery
5 * Copyright (c) 2006 Openedhand Ltd.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2.1 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 *
20 * TODO:
21 * o Isochronous transfers
22 * o Allocate bandwidth in frames properly
23 * o Disable timers when nothing needs to be done, or remove timer usage
24 * all together.
25 * o BIOS work to boot from USB storage
26 */
27
28 #include "qemu/osdep.h"
29 #include "hw/irq.h"
30 #include "qapi/error.h"
31 #include "qemu/module.h"
32 #include "qemu/timer.h"
33 #include "hw/usb.h"
34 #include "migration/vmstate.h"
35 #include "hw/sysbus.h"
36 #include "hw/qdev-dma.h"
37 #include "hw/qdev-properties.h"
38 #include "trace.h"
39 #include "hcd-ohci.h"
40
41 /* This causes frames to occur 1000x slower */
42 /*#define OHCI_TIME_WARP 1*/
43
44 #define ED_LINK_LIMIT 32
45
46 static int64_t usb_frame_time;
47 static int64_t usb_bit_time;
48
49 /* Host Controller Communications Area */
50 struct ohci_hcca {
51 uint32_t intr[32];
52 uint16_t frame, pad;
53 uint32_t done;
54 };
55 #define HCCA_WRITEBACK_OFFSET offsetof(struct ohci_hcca, frame)
56 #define HCCA_WRITEBACK_SIZE 8 /* frame, pad, done */
57
58 #define ED_WBACK_OFFSET offsetof(struct ohci_ed, head)
59 #define ED_WBACK_SIZE 4
60
61 /* Bitfields for the first word of an Endpoint Desciptor. */
62 #define OHCI_ED_FA_SHIFT 0
63 #define OHCI_ED_FA_MASK (0x7f << OHCI_ED_FA_SHIFT)
64 #define OHCI_ED_EN_SHIFT 7
65 #define OHCI_ED_EN_MASK (0xf << OHCI_ED_EN_SHIFT)
66 #define OHCI_ED_D_SHIFT 11
67 #define OHCI_ED_D_MASK (3 << OHCI_ED_D_SHIFT)
68 #define OHCI_ED_S (1 << 13)
69 #define OHCI_ED_K (1 << 14)
70 #define OHCI_ED_F (1 << 15)
71 #define OHCI_ED_MPS_SHIFT 16
72 #define OHCI_ED_MPS_MASK (0x7ff << OHCI_ED_MPS_SHIFT)
73
74 /* Flags in the head field of an Endpoint Desciptor. */
75 #define OHCI_ED_H 1
76 #define OHCI_ED_C 2
77
78 /* Bitfields for the first word of a Transfer Desciptor. */
79 #define OHCI_TD_R (1 << 18)
80 #define OHCI_TD_DP_SHIFT 19
81 #define OHCI_TD_DP_MASK (3 << OHCI_TD_DP_SHIFT)
82 #define OHCI_TD_DI_SHIFT 21
83 #define OHCI_TD_DI_MASK (7 << OHCI_TD_DI_SHIFT)
84 #define OHCI_TD_T0 (1 << 24)
85 #define OHCI_TD_T1 (1 << 25)
86 #define OHCI_TD_EC_SHIFT 26
87 #define OHCI_TD_EC_MASK (3 << OHCI_TD_EC_SHIFT)
88 #define OHCI_TD_CC_SHIFT 28
89 #define OHCI_TD_CC_MASK (0xf << OHCI_TD_CC_SHIFT)
90
91 /* Bitfields for the first word of an Isochronous Transfer Desciptor. */
92 /* CC & DI - same as in the General Transfer Desciptor */
93 #define OHCI_TD_SF_SHIFT 0
94 #define OHCI_TD_SF_MASK (0xffff << OHCI_TD_SF_SHIFT)
95 #define OHCI_TD_FC_SHIFT 24
96 #define OHCI_TD_FC_MASK (7 << OHCI_TD_FC_SHIFT)
97
98 /* Isochronous Transfer Desciptor - Offset / PacketStatusWord */
99 #define OHCI_TD_PSW_CC_SHIFT 12
100 #define OHCI_TD_PSW_CC_MASK (0xf << OHCI_TD_PSW_CC_SHIFT)
101 #define OHCI_TD_PSW_SIZE_SHIFT 0
102 #define OHCI_TD_PSW_SIZE_MASK (0xfff << OHCI_TD_PSW_SIZE_SHIFT)
103
104 #define OHCI_PAGE_MASK 0xfffff000
105 #define OHCI_OFFSET_MASK 0xfff
106
107 #define OHCI_DPTR_MASK 0xfffffff0
108
109 #define OHCI_BM(val, field) \
110 (((val) & OHCI_##field##_MASK) >> OHCI_##field##_SHIFT)
111
112 #define OHCI_SET_BM(val, field, newval) do { \
113 val &= ~OHCI_##field##_MASK; \
114 val |= ((newval) << OHCI_##field##_SHIFT) & OHCI_##field##_MASK; \
115 } while (0)
116
117 /* endpoint descriptor */
118 struct ohci_ed {
119 uint32_t flags;
120 uint32_t tail;
121 uint32_t head;
122 uint32_t next;
123 };
124
125 /* General transfer descriptor */
126 struct ohci_td {
127 uint32_t flags;
128 uint32_t cbp;
129 uint32_t next;
130 uint32_t be;
131 };
132
133 /* Isochronous transfer descriptor */
134 struct ohci_iso_td {
135 uint32_t flags;
136 uint32_t bp;
137 uint32_t next;
138 uint32_t be;
139 uint16_t offset[8];
140 };
141
142 #define USB_HZ 12000000
143
144 /* OHCI Local stuff */
145 #define OHCI_CTL_CBSR ((1 << 0) | (1 << 1))
146 #define OHCI_CTL_PLE (1 << 2)
147 #define OHCI_CTL_IE (1 << 3)
148 #define OHCI_CTL_CLE (1 << 4)
149 #define OHCI_CTL_BLE (1 << 5)
150 #define OHCI_CTL_HCFS ((1 << 6) | (1 << 7))
151 #define OHCI_USB_RESET 0x00
152 #define OHCI_USB_RESUME 0x40
153 #define OHCI_USB_OPERATIONAL 0x80
154 #define OHCI_USB_SUSPEND 0xc0
155 #define OHCI_CTL_IR (1 << 8)
156 #define OHCI_CTL_RWC (1 << 9)
157 #define OHCI_CTL_RWE (1 << 10)
158
159 #define OHCI_STATUS_HCR (1 << 0)
160 #define OHCI_STATUS_CLF (1 << 1)
161 #define OHCI_STATUS_BLF (1 << 2)
162 #define OHCI_STATUS_OCR (1 << 3)
163 #define OHCI_STATUS_SOC ((1 << 6) | (1 << 7))
164
165 #define OHCI_INTR_SO (1U << 0) /* Scheduling overrun */
166 #define OHCI_INTR_WD (1U << 1) /* HcDoneHead writeback */
167 #define OHCI_INTR_SF (1U << 2) /* Start of frame */
168 #define OHCI_INTR_RD (1U << 3) /* Resume detect */
169 #define OHCI_INTR_UE (1U << 4) /* Unrecoverable error */
170 #define OHCI_INTR_FNO (1U << 5) /* Frame number overflow */
171 #define OHCI_INTR_RHSC (1U << 6) /* Root hub status change */
172 #define OHCI_INTR_OC (1U << 30) /* Ownership change */
173 #define OHCI_INTR_MIE (1U << 31) /* Master Interrupt Enable */
174
175 #define OHCI_HCCA_SIZE 0x100
176 #define OHCI_HCCA_MASK 0xffffff00
177
178 #define OHCI_EDPTR_MASK 0xfffffff0
179
180 #define OHCI_FMI_FI 0x00003fff
181 #define OHCI_FMI_FSMPS 0xffff0000
182 #define OHCI_FMI_FIT 0x80000000
183
184 #define OHCI_FR_RT (1U << 31)
185
186 #define OHCI_LS_THRESH 0x628
187
188 #define OHCI_RHA_RW_MASK 0x00000000 /* Mask of supported features. */
189 #define OHCI_RHA_PSM (1 << 8)
190 #define OHCI_RHA_NPS (1 << 9)
191 #define OHCI_RHA_DT (1 << 10)
192 #define OHCI_RHA_OCPM (1 << 11)
193 #define OHCI_RHA_NOCP (1 << 12)
194 #define OHCI_RHA_POTPGT_MASK 0xff000000
195
196 #define OHCI_RHS_LPS (1U << 0)
197 #define OHCI_RHS_OCI (1U << 1)
198 #define OHCI_RHS_DRWE (1U << 15)
199 #define OHCI_RHS_LPSC (1U << 16)
200 #define OHCI_RHS_OCIC (1U << 17)
201 #define OHCI_RHS_CRWE (1U << 31)
202
203 #define OHCI_PORT_CCS (1 << 0)
204 #define OHCI_PORT_PES (1 << 1)
205 #define OHCI_PORT_PSS (1 << 2)
206 #define OHCI_PORT_POCI (1 << 3)
207 #define OHCI_PORT_PRS (1 << 4)
208 #define OHCI_PORT_PPS (1 << 8)
209 #define OHCI_PORT_LSDA (1 << 9)
210 #define OHCI_PORT_CSC (1 << 16)
211 #define OHCI_PORT_PESC (1 << 17)
212 #define OHCI_PORT_PSSC (1 << 18)
213 #define OHCI_PORT_OCIC (1 << 19)
214 #define OHCI_PORT_PRSC (1 << 20)
215 #define OHCI_PORT_WTC (OHCI_PORT_CSC | OHCI_PORT_PESC | \
216 OHCI_PORT_PSSC | OHCI_PORT_OCIC | \
217 OHCI_PORT_PRSC)
218 #define OHCI_TD_DIR_SETUP 0x0
219 #define OHCI_TD_DIR_OUT 0x1
220 #define OHCI_TD_DIR_IN 0x2
221 #define OHCI_TD_DIR_RESERVED 0x3
222
223 #define OHCI_CC_NOERROR 0x0
224 #define OHCI_CC_CRC 0x1
225 #define OHCI_CC_BITSTUFFING 0x2
226 #define OHCI_CC_DATATOGGLEMISMATCH 0x3
227 #define OHCI_CC_STALL 0x4
228 #define OHCI_CC_DEVICENOTRESPONDING 0x5
229 #define OHCI_CC_PIDCHECKFAILURE 0x6
230 #define OHCI_CC_UNDEXPETEDPID 0x7
231 #define OHCI_CC_DATAOVERRUN 0x8
232 #define OHCI_CC_DATAUNDERRUN 0x9
233 #define OHCI_CC_BUFFEROVERRUN 0xc
234 #define OHCI_CC_BUFFERUNDERRUN 0xd
235
236 #define OHCI_HRESET_FSBIR (1 << 0)
237
238 static void ohci_die(OHCIState *ohci)
239 {
240 ohci->ohci_die(ohci);
241 }
242
243 /* Update IRQ levels */
244 static inline void ohci_intr_update(OHCIState *ohci)
245 {
246 int level = 0;
247
248 if ((ohci->intr & OHCI_INTR_MIE) &&
249 (ohci->intr_status & ohci->intr))
250 level = 1;
251
252 qemu_set_irq(ohci->irq, level);
253 }
254
255 /* Set an interrupt */
256 static inline void ohci_set_interrupt(OHCIState *ohci, uint32_t intr)
257 {
258 ohci->intr_status |= intr;
259 ohci_intr_update(ohci);
260 }
261
262 static USBDevice *ohci_find_device(OHCIState *ohci, uint8_t addr)
263 {
264 USBDevice *dev;
265 int i;
266
267 for (i = 0; i < ohci->num_ports; i++) {
268 if ((ohci->rhport[i].ctrl & OHCI_PORT_PES) == 0) {
269 continue;
270 }
271 dev = usb_find_device(&ohci->rhport[i].port, addr);
272 if (dev != NULL) {
273 return dev;
274 }
275 }
276 return NULL;
277 }
278
279 void ohci_stop_endpoints(OHCIState *ohci)
280 {
281 USBDevice *dev;
282 int i, j;
283
284 if (ohci->async_td) {
285 usb_cancel_packet(&ohci->usb_packet);
286 ohci->async_td = 0;
287 }
288 for (i = 0; i < ohci->num_ports; i++) {
289 dev = ohci->rhport[i].port.dev;
290 if (dev && dev->attached) {
291 usb_device_ep_stopped(dev, &dev->ep_ctl);
292 for (j = 0; j < USB_MAX_ENDPOINTS; j++) {
293 usb_device_ep_stopped(dev, &dev->ep_in[j]);
294 usb_device_ep_stopped(dev, &dev->ep_out[j]);
295 }
296 }
297 }
298 }
299
300 static void ohci_roothub_reset(OHCIState *ohci)
301 {
302 OHCIPort *port;
303 int i;
304
305 ohci_bus_stop(ohci);
306 ohci->rhdesc_a = OHCI_RHA_NPS | ohci->num_ports;
307 ohci->rhdesc_b = 0x0; /* Impl. specific */
308 ohci->rhstatus = 0;
309
310 for (i = 0; i < ohci->num_ports; i++) {
311 port = &ohci->rhport[i];
312 port->ctrl = 0;
313 if (port->port.dev && port->port.dev->attached) {
314 usb_port_reset(&port->port);
315 }
316 }
317 ohci_stop_endpoints(ohci);
318 }
319
320 /* Reset the controller */
321 static void ohci_soft_reset(OHCIState *ohci)
322 {
323 trace_usb_ohci_reset(ohci->name);
324
325 ohci_bus_stop(ohci);
326 ohci->ctl = (ohci->ctl & OHCI_CTL_IR) | OHCI_USB_SUSPEND;
327 ohci->old_ctl = 0;
328 ohci->status = 0;
329 ohci->intr_status = 0;
330 ohci->intr = OHCI_INTR_MIE;
331
332 ohci->hcca = 0;
333 ohci->ctrl_head = ohci->ctrl_cur = 0;
334 ohci->bulk_head = ohci->bulk_cur = 0;
335 ohci->per_cur = 0;
336 ohci->done = 0;
337 ohci->done_count = 7;
338 /*
339 * FSMPS is marked TBD in OCHI 1.0, what gives ffs?
340 * I took the value linux sets ...
341 */
342 ohci->fsmps = 0x2778;
343 ohci->fi = 0x2edf;
344 ohci->fit = 0;
345 ohci->frt = 0;
346 ohci->frame_number = 0;
347 ohci->pstart = 0;
348 ohci->lst = OHCI_LS_THRESH;
349 }
350
351 void ohci_hard_reset(OHCIState *ohci)
352 {
353 ohci_soft_reset(ohci);
354 ohci->ctl = 0;
355 ohci_roothub_reset(ohci);
356 }
357
358 /* Get an array of dwords from main memory */
359 static inline int get_dwords(OHCIState *ohci,
360 dma_addr_t addr, uint32_t *buf, int num)
361 {
362 int i;
363
364 addr += ohci->localmem_base;
365
366 for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
367 if (dma_memory_read(ohci->as, addr,
368 buf, sizeof(*buf), MEMTXATTRS_UNSPECIFIED)) {
369 return -1;
370 }
371 *buf = le32_to_cpu(*buf);
372 }
373
374 return 0;
375 }
376
377 /* Put an array of dwords in to main memory */
378 static inline int put_dwords(OHCIState *ohci,
379 dma_addr_t addr, uint32_t *buf, int num)
380 {
381 int i;
382
383 addr += ohci->localmem_base;
384
385 for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
386 uint32_t tmp = cpu_to_le32(*buf);
387 if (dma_memory_write(ohci->as, addr,
388 &tmp, sizeof(tmp), MEMTXATTRS_UNSPECIFIED)) {
389 return -1;
390 }
391 }
392
393 return 0;
394 }
395
396 /* Get an array of words from main memory */
397 static inline int get_words(OHCIState *ohci,
398 dma_addr_t addr, uint16_t *buf, int num)
399 {
400 int i;
401
402 addr += ohci->localmem_base;
403
404 for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
405 if (dma_memory_read(ohci->as, addr,
406 buf, sizeof(*buf), MEMTXATTRS_UNSPECIFIED)) {
407 return -1;
408 }
409 *buf = le16_to_cpu(*buf);
410 }
411
412 return 0;
413 }
414
415 /* Put an array of words in to main memory */
416 static inline int put_words(OHCIState *ohci,
417 dma_addr_t addr, uint16_t *buf, int num)
418 {
419 int i;
420
421 addr += ohci->localmem_base;
422
423 for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
424 uint16_t tmp = cpu_to_le16(*buf);
425 if (dma_memory_write(ohci->as, addr,
426 &tmp, sizeof(tmp), MEMTXATTRS_UNSPECIFIED)) {
427 return -1;
428 }
429 }
430
431 return 0;
432 }
433
434 static inline int ohci_read_ed(OHCIState *ohci,
435 dma_addr_t addr, struct ohci_ed *ed)
436 {
437 return get_dwords(ohci, addr, (uint32_t *)ed, sizeof(*ed) >> 2);
438 }
439
440 static inline int ohci_read_td(OHCIState *ohci,
441 dma_addr_t addr, struct ohci_td *td)
442 {
443 return get_dwords(ohci, addr, (uint32_t *)td, sizeof(*td) >> 2);
444 }
445
446 static inline int ohci_read_iso_td(OHCIState *ohci,
447 dma_addr_t addr, struct ohci_iso_td *td)
448 {
449 return get_dwords(ohci, addr, (uint32_t *)td, 4) ||
450 get_words(ohci, addr + 16, td->offset, 8);
451 }
452
453 static inline int ohci_read_hcca(OHCIState *ohci,
454 dma_addr_t addr, struct ohci_hcca *hcca)
455 {
456 return dma_memory_read(ohci->as, addr + ohci->localmem_base, hcca,
457 sizeof(*hcca), MEMTXATTRS_UNSPECIFIED);
458 }
459
460 static inline int ohci_put_ed(OHCIState *ohci,
461 dma_addr_t addr, struct ohci_ed *ed)
462 {
463 /*
464 * ed->tail is under control of the HCD.
465 * Since just ed->head is changed by HC, just write back this
466 */
467 return put_dwords(ohci, addr + ED_WBACK_OFFSET,
468 (uint32_t *)((char *)ed + ED_WBACK_OFFSET),
469 ED_WBACK_SIZE >> 2);
470 }
471
472 static inline int ohci_put_td(OHCIState *ohci,
473 dma_addr_t addr, struct ohci_td *td)
474 {
475 return put_dwords(ohci, addr, (uint32_t *)td, sizeof(*td) >> 2);
476 }
477
478 static inline int ohci_put_iso_td(OHCIState *ohci,
479 dma_addr_t addr, struct ohci_iso_td *td)
480 {
481 return put_dwords(ohci, addr, (uint32_t *)td, 4) ||
482 put_words(ohci, addr + 16, td->offset, 8);
483 }
484
485 static inline int ohci_put_hcca(OHCIState *ohci,
486 dma_addr_t addr, struct ohci_hcca *hcca)
487 {
488 return dma_memory_write(ohci->as,
489 addr + ohci->localmem_base + HCCA_WRITEBACK_OFFSET,
490 (char *)hcca + HCCA_WRITEBACK_OFFSET,
491 HCCA_WRITEBACK_SIZE, MEMTXATTRS_UNSPECIFIED);
492 }
493
494 /* Read/Write the contents of a TD from/to main memory. */
495 static int ohci_copy_td(OHCIState *ohci, struct ohci_td *td,
496 uint8_t *buf, int len, DMADirection dir)
497 {
498 dma_addr_t ptr, n;
499
500 ptr = td->cbp;
501 n = 0x1000 - (ptr & 0xfff);
502 if (n > len)
503 n = len;
504
505 if (dma_memory_rw(ohci->as, ptr + ohci->localmem_base, buf,
506 n, dir, MEMTXATTRS_UNSPECIFIED)) {
507 return -1;
508 }
509 if (n == len) {
510 return 0;
511 }
512 ptr = td->be & ~0xfffu;
513 buf += n;
514 if (dma_memory_rw(ohci->as, ptr + ohci->localmem_base, buf,
515 len - n, dir, MEMTXATTRS_UNSPECIFIED)) {
516 return -1;
517 }
518 return 0;
519 }
520
521 /* Read/Write the contents of an ISO TD from/to main memory. */
522 static int ohci_copy_iso_td(OHCIState *ohci,
523 uint32_t start_addr, uint32_t end_addr,
524 uint8_t *buf, int len, DMADirection dir)
525 {
526 dma_addr_t ptr, n;
527
528 ptr = start_addr;
529 n = 0x1000 - (ptr & 0xfff);
530 if (n > len)
531 n = len;
532
533 if (dma_memory_rw(ohci->as, ptr + ohci->localmem_base, buf,
534 n, dir, MEMTXATTRS_UNSPECIFIED)) {
535 return -1;
536 }
537 if (n == len) {
538 return 0;
539 }
540 ptr = end_addr & ~0xfffu;
541 buf += n;
542 if (dma_memory_rw(ohci->as, ptr + ohci->localmem_base, buf,
543 len - n, dir, MEMTXATTRS_UNSPECIFIED)) {
544 return -1;
545 }
546 return 0;
547 }
548
549 #define USUB(a, b) ((int16_t)((uint16_t)(a) - (uint16_t)(b)))
550
551 static int ohci_service_iso_td(OHCIState *ohci, struct ohci_ed *ed)
552 {
553 int dir;
554 size_t len = 0;
555 const char *str = NULL;
556 int pid;
557 int ret;
558 int i;
559 USBDevice *dev;
560 USBEndpoint *ep;
561 USBPacket *pkt;
562 uint8_t buf[8192];
563 bool int_req;
564 struct ohci_iso_td iso_td;
565 uint32_t addr;
566 uint16_t starting_frame;
567 int16_t relative_frame_number;
568 int frame_count;
569 uint32_t start_offset, next_offset, end_offset = 0;
570 uint32_t start_addr, end_addr;
571
572 addr = ed->head & OHCI_DPTR_MASK;
573
574 if (addr == 0) {
575 ohci_die(ohci);
576 return 1;
577 }
578
579 if (ohci_read_iso_td(ohci, addr, &iso_td)) {
580 trace_usb_ohci_iso_td_read_failed(addr);
581 ohci_die(ohci);
582 return 1;
583 }
584
585 starting_frame = OHCI_BM(iso_td.flags, TD_SF);
586 frame_count = OHCI_BM(iso_td.flags, TD_FC);
587 relative_frame_number = USUB(ohci->frame_number, starting_frame);
588
589 trace_usb_ohci_iso_td_head(
590 ed->head & OHCI_DPTR_MASK, ed->tail & OHCI_DPTR_MASK,
591 iso_td.flags, iso_td.bp, iso_td.next, iso_td.be,
592 ohci->frame_number, starting_frame,
593 frame_count, relative_frame_number);
594 trace_usb_ohci_iso_td_head_offset(
595 iso_td.offset[0], iso_td.offset[1],
596 iso_td.offset[2], iso_td.offset[3],
597 iso_td.offset[4], iso_td.offset[5],
598 iso_td.offset[6], iso_td.offset[7]);
599
600 if (relative_frame_number < 0) {
601 trace_usb_ohci_iso_td_relative_frame_number_neg(relative_frame_number);
602 return 1;
603 } else if (relative_frame_number > frame_count) {
604 /*
605 * ISO TD expired - retire the TD to the Done Queue and continue with
606 * the next ISO TD of the same ED
607 */
608 trace_usb_ohci_iso_td_relative_frame_number_big(relative_frame_number,
609 frame_count);
610 if (OHCI_CC_DATAOVERRUN == OHCI_BM(iso_td.flags, TD_CC)) {
611 /* avoid infinite loop */
612 return 1;
613 }
614 OHCI_SET_BM(iso_td.flags, TD_CC, OHCI_CC_DATAOVERRUN);
615 ed->head &= ~OHCI_DPTR_MASK;
616 ed->head |= (iso_td.next & OHCI_DPTR_MASK);
617 iso_td.next = ohci->done;
618 ohci->done = addr;
619 i = OHCI_BM(iso_td.flags, TD_DI);
620 if (i < ohci->done_count)
621 ohci->done_count = i;
622 if (ohci_put_iso_td(ohci, addr, &iso_td)) {
623 ohci_die(ohci);
624 return 1;
625 }
626 return 0;
627 }
628
629 dir = OHCI_BM(ed->flags, ED_D);
630 switch (dir) {
631 case OHCI_TD_DIR_IN:
632 str = "in";
633 pid = USB_TOKEN_IN;
634 break;
635 case OHCI_TD_DIR_OUT:
636 str = "out";
637 pid = USB_TOKEN_OUT;
638 break;
639 case OHCI_TD_DIR_SETUP:
640 str = "setup";
641 pid = USB_TOKEN_SETUP;
642 break;
643 default:
644 trace_usb_ohci_iso_td_bad_direction(dir);
645 return 1;
646 }
647
648 if (!iso_td.bp || !iso_td.be) {
649 trace_usb_ohci_iso_td_bad_bp_be(iso_td.bp, iso_td.be);
650 return 1;
651 }
652
653 start_offset = iso_td.offset[relative_frame_number];
654 if (relative_frame_number < frame_count) {
655 next_offset = iso_td.offset[relative_frame_number + 1];
656 } else {
657 next_offset = iso_td.be;
658 }
659
660 if (!(OHCI_BM(start_offset, TD_PSW_CC) & 0xe) ||
661 ((relative_frame_number < frame_count) &&
662 !(OHCI_BM(next_offset, TD_PSW_CC) & 0xe))) {
663 trace_usb_ohci_iso_td_bad_cc_not_accessed(start_offset, next_offset);
664 return 1;
665 }
666
667 if ((relative_frame_number < frame_count) && (start_offset > next_offset)) {
668 trace_usb_ohci_iso_td_bad_cc_overrun(start_offset, next_offset);
669 return 1;
670 }
671
672 if ((start_offset & 0x1000) == 0) {
673 start_addr = (iso_td.bp & OHCI_PAGE_MASK) |
674 (start_offset & OHCI_OFFSET_MASK);
675 } else {
676 start_addr = (iso_td.be & OHCI_PAGE_MASK) |
677 (start_offset & OHCI_OFFSET_MASK);
678 }
679
680 if (relative_frame_number < frame_count) {
681 end_offset = next_offset - 1;
682 if ((end_offset & 0x1000) == 0) {
683 end_addr = (iso_td.bp & OHCI_PAGE_MASK) |
684 (end_offset & OHCI_OFFSET_MASK);
685 } else {
686 end_addr = (iso_td.be & OHCI_PAGE_MASK) |
687 (end_offset & OHCI_OFFSET_MASK);
688 }
689 } else {
690 /* Last packet in the ISO TD */
691 end_addr = next_offset;
692 }
693
694 if (start_addr > end_addr) {
695 trace_usb_ohci_iso_td_bad_cc_overrun(start_addr, end_addr);
696 return 1;
697 }
698
699 if ((start_addr & OHCI_PAGE_MASK) != (end_addr & OHCI_PAGE_MASK)) {
700 len = (end_addr & OHCI_OFFSET_MASK) + 0x1001
701 - (start_addr & OHCI_OFFSET_MASK);
702 } else {
703 len = end_addr - start_addr + 1;
704 }
705 if (len > sizeof(buf)) {
706 len = sizeof(buf);
707 }
708
709 if (len && dir != OHCI_TD_DIR_IN) {
710 if (ohci_copy_iso_td(ohci, start_addr, end_addr, buf, len,
711 DMA_DIRECTION_TO_DEVICE)) {
712 ohci_die(ohci);
713 return 1;
714 }
715 }
716
717 dev = ohci_find_device(ohci, OHCI_BM(ed->flags, ED_FA));
718 if (dev == NULL) {
719 trace_usb_ohci_td_dev_error();
720 return 1;
721 }
722 ep = usb_ep_get(dev, pid, OHCI_BM(ed->flags, ED_EN));
723 pkt = g_new0(USBPacket, 1);
724 usb_packet_init(pkt);
725 int_req = relative_frame_number == frame_count &&
726 OHCI_BM(iso_td.flags, TD_DI) == 0;
727 usb_packet_setup(pkt, pid, ep, 0, addr, false, int_req);
728 usb_packet_addbuf(pkt, buf, len);
729 usb_handle_packet(dev, pkt);
730 if (pkt->status == USB_RET_ASYNC) {
731 usb_device_flush_ep_queue(dev, ep);
732 g_free(pkt);
733 return 1;
734 }
735 if (pkt->status == USB_RET_SUCCESS) {
736 ret = pkt->actual_length;
737 } else {
738 ret = pkt->status;
739 }
740 g_free(pkt);
741
742 trace_usb_ohci_iso_td_so(start_offset, end_offset, start_addr, end_addr,
743 str, len, ret);
744
745 /* Writeback */
746 if (dir == OHCI_TD_DIR_IN && ret >= 0 && ret <= len) {
747 /* IN transfer succeeded */
748 if (ohci_copy_iso_td(ohci, start_addr, end_addr, buf, ret,
749 DMA_DIRECTION_FROM_DEVICE)) {
750 ohci_die(ohci);
751 return 1;
752 }
753 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
754 OHCI_CC_NOERROR);
755 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE, ret);
756 } else if (dir == OHCI_TD_DIR_OUT && ret == len) {
757 /* OUT transfer succeeded */
758 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
759 OHCI_CC_NOERROR);
760 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE, 0);
761 } else {
762 if (ret > (ssize_t) len) {
763 trace_usb_ohci_iso_td_data_overrun(ret, len);
764 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
765 OHCI_CC_DATAOVERRUN);
766 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE,
767 len);
768 } else if (ret >= 0) {
769 trace_usb_ohci_iso_td_data_underrun(ret);
770 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
771 OHCI_CC_DATAUNDERRUN);
772 } else {
773 switch (ret) {
774 case USB_RET_IOERROR:
775 case USB_RET_NODEV:
776 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
777 OHCI_CC_DEVICENOTRESPONDING);
778 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE,
779 0);
780 break;
781 case USB_RET_NAK:
782 case USB_RET_STALL:
783 trace_usb_ohci_iso_td_nak(ret);
784 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
785 OHCI_CC_STALL);
786 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE,
787 0);
788 break;
789 default:
790 trace_usb_ohci_iso_td_bad_response(ret);
791 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
792 OHCI_CC_UNDEXPETEDPID);
793 break;
794 }
795 }
796 }
797
798 if (relative_frame_number == frame_count) {
799 /* Last data packet of ISO TD - retire the TD to the Done Queue */
800 OHCI_SET_BM(iso_td.flags, TD_CC, OHCI_CC_NOERROR);
801 ed->head &= ~OHCI_DPTR_MASK;
802 ed->head |= (iso_td.next & OHCI_DPTR_MASK);
803 iso_td.next = ohci->done;
804 ohci->done = addr;
805 i = OHCI_BM(iso_td.flags, TD_DI);
806 if (i < ohci->done_count)
807 ohci->done_count = i;
808 }
809 if (ohci_put_iso_td(ohci, addr, &iso_td)) {
810 ohci_die(ohci);
811 }
812 return 1;
813 }
814
815 #define HEX_CHAR_PER_LINE 16
816
817 static void ohci_td_pkt(const char *msg, const uint8_t *buf, size_t len)
818 {
819 bool print16;
820 bool printall;
821 int i;
822 char tmp[3 * HEX_CHAR_PER_LINE + 1];
823 char *p = tmp;
824
825 print16 = !!trace_event_get_state_backends(TRACE_USB_OHCI_TD_PKT_SHORT);
826 printall = !!trace_event_get_state_backends(TRACE_USB_OHCI_TD_PKT_FULL);
827
828 if (!printall && !print16) {
829 return;
830 }
831
832 for (i = 0; ; i++) {
833 if (i && (!(i % HEX_CHAR_PER_LINE) || (i == len))) {
834 if (!printall) {
835 trace_usb_ohci_td_pkt_short(msg, tmp);
836 break;
837 }
838 trace_usb_ohci_td_pkt_full(msg, tmp);
839 p = tmp;
840 *p = 0;
841 }
842 if (i == len) {
843 break;
844 }
845
846 p += sprintf(p, " %.2x", buf[i]);
847 }
848 }
849
850 /*
851 * Service a transport descriptor.
852 * Returns nonzero to terminate processing of this endpoint.
853 */
854 static int ohci_service_td(OHCIState *ohci, struct ohci_ed *ed)
855 {
856 int dir;
857 size_t len = 0, pktlen = 0;
858 const char *str = NULL;
859 int pid;
860 int ret;
861 int i;
862 USBDevice *dev;
863 USBEndpoint *ep;
864 struct ohci_td td;
865 uint32_t addr;
866 int flag_r;
867 int completion;
868
869 addr = ed->head & OHCI_DPTR_MASK;
870 if (addr == 0) {
871 ohci_die(ohci);
872 return 1;
873 }
874
875 /* See if this TD has already been submitted to the device. */
876 completion = (addr == ohci->async_td);
877 if (completion && !ohci->async_complete) {
878 trace_usb_ohci_td_skip_async();
879 return 1;
880 }
881 if (ohci_read_td(ohci, addr, &td)) {
882 trace_usb_ohci_td_read_error(addr);
883 ohci_die(ohci);
884 return 1;
885 }
886
887 dir = OHCI_BM(ed->flags, ED_D);
888 switch (dir) {
889 case OHCI_TD_DIR_OUT:
890 case OHCI_TD_DIR_IN:
891 /* Same value. */
892 break;
893 default:
894 dir = OHCI_BM(td.flags, TD_DP);
895 break;
896 }
897
898 switch (dir) {
899 case OHCI_TD_DIR_IN:
900 str = "in";
901 pid = USB_TOKEN_IN;
902 break;
903 case OHCI_TD_DIR_OUT:
904 str = "out";
905 pid = USB_TOKEN_OUT;
906 break;
907 case OHCI_TD_DIR_SETUP:
908 str = "setup";
909 pid = USB_TOKEN_SETUP;
910 break;
911 default:
912 trace_usb_ohci_td_bad_direction(dir);
913 return 1;
914 }
915 if (td.cbp && td.be) {
916 if ((td.cbp & 0xfffff000) != (td.be & 0xfffff000)) {
917 len = (td.be & 0xfff) + 0x1001 - (td.cbp & 0xfff);
918 } else {
919 if (td.cbp > td.be) {
920 trace_usb_ohci_iso_td_bad_cc_overrun(td.cbp, td.be);
921 ohci_die(ohci);
922 return 1;
923 }
924 len = (td.be - td.cbp) + 1;
925 }
926 if (len > sizeof(ohci->usb_buf)) {
927 len = sizeof(ohci->usb_buf);
928 }
929
930 pktlen = len;
931 if (len && dir != OHCI_TD_DIR_IN) {
932 /* The endpoint may not allow us to transfer it all now */
933 pktlen = (ed->flags & OHCI_ED_MPS_MASK) >> OHCI_ED_MPS_SHIFT;
934 if (pktlen > len) {
935 pktlen = len;
936 }
937 if (!completion) {
938 if (ohci_copy_td(ohci, &td, ohci->usb_buf, pktlen,
939 DMA_DIRECTION_TO_DEVICE)) {
940 ohci_die(ohci);
941 }
942 }
943 }
944 }
945
946 flag_r = (td.flags & OHCI_TD_R) != 0;
947 trace_usb_ohci_td_pkt_hdr(addr, (int64_t)pktlen, (int64_t)len, str,
948 flag_r, td.cbp, td.be);
949 ohci_td_pkt("OUT", ohci->usb_buf, pktlen);
950
951 if (completion) {
952 ohci->async_td = 0;
953 ohci->async_complete = false;
954 } else {
955 dev = ohci_find_device(ohci, OHCI_BM(ed->flags, ED_FA));
956 if (dev == NULL) {
957 trace_usb_ohci_td_dev_error();
958 return 1;
959 }
960 ep = usb_ep_get(dev, pid, OHCI_BM(ed->flags, ED_EN));
961 if (ohci->async_td) {
962 /*
963 * ??? The hardware should allow one active packet per
964 * endpoint. We only allow one active packet per controller.
965 * This should be sufficient as long as devices respond in a
966 * timely manner.
967 */
968 trace_usb_ohci_td_too_many_pending(ep->nr);
969 return 1;
970 }
971 usb_packet_setup(&ohci->usb_packet, pid, ep, 0, addr, !flag_r,
972 OHCI_BM(td.flags, TD_DI) == 0);
973 usb_packet_addbuf(&ohci->usb_packet, ohci->usb_buf, pktlen);
974 usb_handle_packet(dev, &ohci->usb_packet);
975 trace_usb_ohci_td_packet_status(ohci->usb_packet.status);
976
977 if (ohci->usb_packet.status == USB_RET_ASYNC) {
978 usb_device_flush_ep_queue(dev, ep);
979 ohci->async_td = addr;
980 return 1;
981 }
982 }
983 if (ohci->usb_packet.status == USB_RET_SUCCESS) {
984 ret = ohci->usb_packet.actual_length;
985 } else {
986 ret = ohci->usb_packet.status;
987 }
988
989 if (ret >= 0) {
990 if (dir == OHCI_TD_DIR_IN) {
991 if (ohci_copy_td(ohci, &td, ohci->usb_buf, ret,
992 DMA_DIRECTION_FROM_DEVICE)) {
993 ohci_die(ohci);
994 }
995 ohci_td_pkt("IN", ohci->usb_buf, pktlen);
996 } else {
997 ret = pktlen;
998 }
999 }
1000
1001 /* Writeback */
1002 if (ret == pktlen || (dir == OHCI_TD_DIR_IN && ret >= 0 && flag_r)) {
1003 /* Transmission succeeded. */
1004 if (ret == len) {
1005 td.cbp = 0;
1006 } else {
1007 if ((td.cbp & 0xfff) + ret > 0xfff) {
1008 td.cbp = (td.be & ~0xfff) + ((td.cbp + ret) & 0xfff);
1009 } else {
1010 td.cbp += ret;
1011 }
1012 }
1013 td.flags |= OHCI_TD_T1;
1014 td.flags ^= OHCI_TD_T0;
1015 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_NOERROR);
1016 OHCI_SET_BM(td.flags, TD_EC, 0);
1017
1018 if ((dir != OHCI_TD_DIR_IN) && (ret != len)) {
1019 /* Partial packet transfer: TD not ready to retire yet */
1020 goto exit_no_retire;
1021 }
1022
1023 /* Setting ED_C is part of the TD retirement process */
1024 ed->head &= ~OHCI_ED_C;
1025 if (td.flags & OHCI_TD_T0)
1026 ed->head |= OHCI_ED_C;
1027 } else {
1028 if (ret >= 0) {
1029 trace_usb_ohci_td_underrun();
1030 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DATAUNDERRUN);
1031 } else {
1032 switch (ret) {
1033 case USB_RET_IOERROR:
1034 case USB_RET_NODEV:
1035 trace_usb_ohci_td_dev_error();
1036 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DEVICENOTRESPONDING);
1037 break;
1038 case USB_RET_NAK:
1039 trace_usb_ohci_td_nak();
1040 return 1;
1041 case USB_RET_STALL:
1042 trace_usb_ohci_td_stall();
1043 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_STALL);
1044 break;
1045 case USB_RET_BABBLE:
1046 trace_usb_ohci_td_babble();
1047 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DATAOVERRUN);
1048 break;
1049 default:
1050 trace_usb_ohci_td_bad_device_response(ret);
1051 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_UNDEXPETEDPID);
1052 OHCI_SET_BM(td.flags, TD_EC, 3);
1053 break;
1054 }
1055 /*
1056 * An error occurred so we have to clear the interrupt counter.
1057 * See spec at 6.4.4 on page 104
1058 */
1059 ohci->done_count = 0;
1060 }
1061 ed->head |= OHCI_ED_H;
1062 }
1063
1064 /* Retire this TD */
1065 ed->head &= ~OHCI_DPTR_MASK;
1066 ed->head |= td.next & OHCI_DPTR_MASK;
1067 td.next = ohci->done;
1068 ohci->done = addr;
1069 i = OHCI_BM(td.flags, TD_DI);
1070 if (i < ohci->done_count)
1071 ohci->done_count = i;
1072 exit_no_retire:
1073 if (ohci_put_td(ohci, addr, &td)) {
1074 ohci_die(ohci);
1075 return 1;
1076 }
1077 return OHCI_BM(td.flags, TD_CC) != OHCI_CC_NOERROR;
1078 }
1079
1080 /* Service an endpoint list. Returns nonzero if active TD were found. */
1081 static int ohci_service_ed_list(OHCIState *ohci, uint32_t head)
1082 {
1083 struct ohci_ed ed;
1084 uint32_t next_ed;
1085 uint32_t cur;
1086 int active;
1087 uint32_t link_cnt = 0;
1088 active = 0;
1089
1090 if (head == 0)
1091 return 0;
1092
1093 for (cur = head; cur && link_cnt++ < ED_LINK_LIMIT; cur = next_ed) {
1094 if (ohci_read_ed(ohci, cur, &ed)) {
1095 trace_usb_ohci_ed_read_error(cur);
1096 ohci_die(ohci);
1097 return 0;
1098 }
1099
1100 next_ed = ed.next & OHCI_DPTR_MASK;
1101
1102 if ((ed.head & OHCI_ED_H) || (ed.flags & OHCI_ED_K)) {
1103 uint32_t addr;
1104 /* Cancel pending packets for ED that have been paused. */
1105 addr = ed.head & OHCI_DPTR_MASK;
1106 if (ohci->async_td && addr == ohci->async_td) {
1107 usb_cancel_packet(&ohci->usb_packet);
1108 ohci->async_td = 0;
1109 usb_device_ep_stopped(ohci->usb_packet.ep->dev,
1110 ohci->usb_packet.ep);
1111 }
1112 continue;
1113 }
1114
1115 while ((ed.head & OHCI_DPTR_MASK) != ed.tail) {
1116 trace_usb_ohci_ed_pkt(cur, (ed.head & OHCI_ED_H) != 0,
1117 (ed.head & OHCI_ED_C) != 0, ed.head & OHCI_DPTR_MASK,
1118 ed.tail & OHCI_DPTR_MASK, ed.next & OHCI_DPTR_MASK);
1119 trace_usb_ohci_ed_pkt_flags(
1120 OHCI_BM(ed.flags, ED_FA), OHCI_BM(ed.flags, ED_EN),
1121 OHCI_BM(ed.flags, ED_D), (ed.flags & OHCI_ED_S) != 0,
1122 (ed.flags & OHCI_ED_K) != 0, (ed.flags & OHCI_ED_F) != 0,
1123 OHCI_BM(ed.flags, ED_MPS));
1124
1125 active = 1;
1126
1127 if ((ed.flags & OHCI_ED_F) == 0) {
1128 if (ohci_service_td(ohci, &ed))
1129 break;
1130 } else {
1131 /* Handle isochronous endpoints */
1132 if (ohci_service_iso_td(ohci, &ed)) {
1133 break;
1134 }
1135 }
1136 }
1137
1138 if (ohci_put_ed(ohci, cur, &ed)) {
1139 ohci_die(ohci);
1140 return 0;
1141 }
1142 }
1143
1144 return active;
1145 }
1146
1147 /* set a timer for EOF */
1148 static void ohci_eof_timer(OHCIState *ohci)
1149 {
1150 timer_mod(ohci->eof_timer, ohci->sof_time + usb_frame_time);
1151 }
1152 /* Set a timer for EOF and generate a SOF event */
1153 static void ohci_sof(OHCIState *ohci)
1154 {
1155 ohci->sof_time += usb_frame_time;
1156 ohci_eof_timer(ohci);
1157 ohci_set_interrupt(ohci, OHCI_INTR_SF);
1158 }
1159
1160 /* Process Control and Bulk lists. */
1161 static void ohci_process_lists(OHCIState *ohci)
1162 {
1163 if ((ohci->ctl & OHCI_CTL_CLE) && (ohci->status & OHCI_STATUS_CLF)) {
1164 if (ohci->ctrl_cur && ohci->ctrl_cur != ohci->ctrl_head) {
1165 trace_usb_ohci_process_lists(ohci->ctrl_head, ohci->ctrl_cur);
1166 }
1167 if (!ohci_service_ed_list(ohci, ohci->ctrl_head)) {
1168 ohci->ctrl_cur = 0;
1169 ohci->status &= ~OHCI_STATUS_CLF;
1170 }
1171 }
1172
1173 if ((ohci->ctl & OHCI_CTL_BLE) && (ohci->status & OHCI_STATUS_BLF)) {
1174 if (!ohci_service_ed_list(ohci, ohci->bulk_head)) {
1175 ohci->bulk_cur = 0;
1176 ohci->status &= ~OHCI_STATUS_BLF;
1177 }
1178 }
1179 }
1180
1181 /* Do frame processing on frame boundary */
1182 static void ohci_frame_boundary(void *opaque)
1183 {
1184 OHCIState *ohci = opaque;
1185 struct ohci_hcca hcca;
1186
1187 if (ohci_read_hcca(ohci, ohci->hcca, &hcca)) {
1188 trace_usb_ohci_hcca_read_error(ohci->hcca);
1189 ohci_die(ohci);
1190 return;
1191 }
1192
1193 /* Process all the lists at the end of the frame */
1194 if (ohci->ctl & OHCI_CTL_PLE) {
1195 int n;
1196
1197 n = ohci->frame_number & 0x1f;
1198 ohci_service_ed_list(ohci, le32_to_cpu(hcca.intr[n]));
1199 }
1200
1201 /* Cancel all pending packets if either of the lists has been disabled. */
1202 if (ohci->old_ctl & (~ohci->ctl) & (OHCI_CTL_BLE | OHCI_CTL_CLE)) {
1203 ohci_stop_endpoints(ohci);
1204 }
1205 ohci->old_ctl = ohci->ctl;
1206 ohci_process_lists(ohci);
1207
1208 /* Stop if UnrecoverableError happened or ohci_sof will crash */
1209 if (ohci->intr_status & OHCI_INTR_UE) {
1210 return;
1211 }
1212
1213 /* Frame boundary, so do EOF stuf here */
1214 ohci->frt = ohci->fit;
1215
1216 /* Increment frame number and take care of endianness. */
1217 ohci->frame_number = (ohci->frame_number + 1) & 0xffff;
1218 hcca.frame = cpu_to_le16(ohci->frame_number);
1219
1220 if (ohci->done_count == 0 && !(ohci->intr_status & OHCI_INTR_WD)) {
1221 if (!ohci->done)
1222 abort();
1223 if (ohci->intr & ohci->intr_status)
1224 ohci->done |= 1;
1225 hcca.done = cpu_to_le32(ohci->done);
1226 ohci->done = 0;
1227 ohci->done_count = 7;
1228 ohci_set_interrupt(ohci, OHCI_INTR_WD);
1229 }
1230
1231 if (ohci->done_count != 7 && ohci->done_count != 0)
1232 ohci->done_count--;
1233
1234 /* Do SOF stuff here */
1235 ohci_sof(ohci);
1236
1237 /* Writeback HCCA */
1238 if (ohci_put_hcca(ohci, ohci->hcca, &hcca)) {
1239 ohci_die(ohci);
1240 }
1241 }
1242
1243 /*
1244 * Start sending SOF tokens across the USB bus, lists are processed in
1245 * next frame
1246 */
1247 static int ohci_bus_start(OHCIState *ohci)
1248 {
1249 trace_usb_ohci_start(ohci->name);
1250 /*
1251 * Delay the first SOF event by one frame time as linux driver is
1252 * not ready to receive it and can meet some race conditions
1253 */
1254 ohci->sof_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
1255 ohci_eof_timer(ohci);
1256
1257 return 1;
1258 }
1259
1260 /* Stop sending SOF tokens on the bus */
1261 void ohci_bus_stop(OHCIState *ohci)
1262 {
1263 trace_usb_ohci_stop(ohci->name);
1264 timer_del(ohci->eof_timer);
1265 }
1266
1267 /*
1268 * Sets a flag in a port status reg but only set it if the port is connected.
1269 * If not set ConnectStatusChange flag. If flag is enabled return 1.
1270 */
1271 static int ohci_port_set_if_connected(OHCIState *ohci, int i, uint32_t val)
1272 {
1273 int ret = 1;
1274
1275 /* writing a 0 has no effect */
1276 if (val == 0)
1277 return 0;
1278
1279 /* If CurrentConnectStatus is cleared we set ConnectStatusChange */
1280 if (!(ohci->rhport[i].ctrl & OHCI_PORT_CCS)) {
1281 ohci->rhport[i].ctrl |= OHCI_PORT_CSC;
1282 if (ohci->rhstatus & OHCI_RHS_DRWE) {
1283 /* TODO: CSC is a wakeup event */
1284 }
1285 return 0;
1286 }
1287
1288 if (ohci->rhport[i].ctrl & val)
1289 ret = 0;
1290
1291 /* set the bit */
1292 ohci->rhport[i].ctrl |= val;
1293
1294 return ret;
1295 }
1296
1297 /* Frame interval toggle is manipulated by the hcd only */
1298 static void ohci_set_frame_interval(OHCIState *ohci, uint16_t val)
1299 {
1300 val &= OHCI_FMI_FI;
1301
1302 if (val != ohci->fi) {
1303 trace_usb_ohci_set_frame_interval(ohci->name, ohci->fi, ohci->fi);
1304 }
1305
1306 ohci->fi = val;
1307 }
1308
1309 static void ohci_port_power(OHCIState *ohci, int i, int p)
1310 {
1311 if (p) {
1312 ohci->rhport[i].ctrl |= OHCI_PORT_PPS;
1313 } else {
1314 ohci->rhport[i].ctrl &= ~(OHCI_PORT_PPS | OHCI_PORT_CCS |
1315 OHCI_PORT_PSS | OHCI_PORT_PRS);
1316 }
1317 }
1318
1319 /* Set HcControlRegister */
1320 static void ohci_set_ctl(OHCIState *ohci, uint32_t val)
1321 {
1322 uint32_t old_state;
1323 uint32_t new_state;
1324
1325 old_state = ohci->ctl & OHCI_CTL_HCFS;
1326 ohci->ctl = val;
1327 new_state = ohci->ctl & OHCI_CTL_HCFS;
1328
1329 /* no state change */
1330 if (old_state == new_state)
1331 return;
1332
1333 trace_usb_ohci_set_ctl(ohci->name, new_state);
1334 switch (new_state) {
1335 case OHCI_USB_OPERATIONAL:
1336 ohci_bus_start(ohci);
1337 break;
1338 case OHCI_USB_SUSPEND:
1339 ohci_bus_stop(ohci);
1340 /* clear pending SF otherwise linux driver loops in ohci_irq() */
1341 ohci->intr_status &= ~OHCI_INTR_SF;
1342 ohci_intr_update(ohci);
1343 break;
1344 case OHCI_USB_RESUME:
1345 trace_usb_ohci_resume(ohci->name);
1346 break;
1347 case OHCI_USB_RESET:
1348 ohci_roothub_reset(ohci);
1349 break;
1350 }
1351 }
1352
1353 static uint32_t ohci_get_frame_remaining(OHCIState *ohci)
1354 {
1355 uint16_t fr;
1356 int64_t tks;
1357
1358 if ((ohci->ctl & OHCI_CTL_HCFS) != OHCI_USB_OPERATIONAL)
1359 return (ohci->frt << 31);
1360
1361 /* Being in USB operational state guarnatees sof_time was set already. */
1362 tks = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - ohci->sof_time;
1363 if (tks < 0) {
1364 tks = 0;
1365 }
1366
1367 /* avoid muldiv if possible */
1368 if (tks >= usb_frame_time)
1369 return (ohci->frt << 31);
1370
1371 tks = tks / usb_bit_time;
1372 fr = (uint16_t)(ohci->fi - tks);
1373
1374 return (ohci->frt << 31) | fr;
1375 }
1376
1377
1378 /* Set root hub status */
1379 static void ohci_set_hub_status(OHCIState *ohci, uint32_t val)
1380 {
1381 uint32_t old_state;
1382
1383 old_state = ohci->rhstatus;
1384
1385 /* write 1 to clear OCIC */
1386 if (val & OHCI_RHS_OCIC)
1387 ohci->rhstatus &= ~OHCI_RHS_OCIC;
1388
1389 if (val & OHCI_RHS_LPS) {
1390 int i;
1391
1392 for (i = 0; i < ohci->num_ports; i++)
1393 ohci_port_power(ohci, i, 0);
1394 trace_usb_ohci_hub_power_down();
1395 }
1396
1397 if (val & OHCI_RHS_LPSC) {
1398 int i;
1399
1400 for (i = 0; i < ohci->num_ports; i++)
1401 ohci_port_power(ohci, i, 1);
1402 trace_usb_ohci_hub_power_up();
1403 }
1404
1405 if (val & OHCI_RHS_DRWE)
1406 ohci->rhstatus |= OHCI_RHS_DRWE;
1407
1408 if (val & OHCI_RHS_CRWE)
1409 ohci->rhstatus &= ~OHCI_RHS_DRWE;
1410
1411 if (old_state != ohci->rhstatus)
1412 ohci_set_interrupt(ohci, OHCI_INTR_RHSC);
1413 }
1414
1415 /* Set root hub port status */
1416 static void ohci_port_set_status(OHCIState *ohci, int portnum, uint32_t val)
1417 {
1418 uint32_t old_state;
1419 OHCIPort *port;
1420
1421 port = &ohci->rhport[portnum];
1422 old_state = port->ctrl;
1423
1424 /* Write to clear CSC, PESC, PSSC, OCIC, PRSC */
1425 if (val & OHCI_PORT_WTC)
1426 port->ctrl &= ~(val & OHCI_PORT_WTC);
1427
1428 if (val & OHCI_PORT_CCS)
1429 port->ctrl &= ~OHCI_PORT_PES;
1430
1431 ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PES);
1432
1433 if (ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PSS)) {
1434 trace_usb_ohci_port_suspend(portnum);
1435 }
1436
1437 if (ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PRS)) {
1438 trace_usb_ohci_port_reset(portnum);
1439 usb_device_reset(port->port.dev);
1440 port->ctrl &= ~OHCI_PORT_PRS;
1441 /* ??? Should this also set OHCI_PORT_PESC. */
1442 port->ctrl |= OHCI_PORT_PES | OHCI_PORT_PRSC;
1443 }
1444
1445 /* Invert order here to ensure in ambiguous case, device is powered up. */
1446 if (val & OHCI_PORT_LSDA)
1447 ohci_port_power(ohci, portnum, 0);
1448 if (val & OHCI_PORT_PPS)
1449 ohci_port_power(ohci, portnum, 1);
1450
1451 if (old_state != port->ctrl)
1452 ohci_set_interrupt(ohci, OHCI_INTR_RHSC);
1453 }
1454
1455 static uint64_t ohci_mem_read(void *opaque,
1456 hwaddr addr,
1457 unsigned size)
1458 {
1459 OHCIState *ohci = opaque;
1460 uint32_t retval;
1461
1462 /* Only aligned reads are allowed on OHCI */
1463 if (addr & 3) {
1464 trace_usb_ohci_mem_read_unaligned(addr);
1465 return 0xffffffff;
1466 } else if (addr >= 0x54 && addr < 0x54 + ohci->num_ports * 4) {
1467 /* HcRhPortStatus */
1468 retval = ohci->rhport[(addr - 0x54) >> 2].ctrl | OHCI_PORT_PPS;
1469 } else {
1470 switch (addr >> 2) {
1471 case 0: /* HcRevision */
1472 retval = 0x10;
1473 break;
1474
1475 case 1: /* HcControl */
1476 retval = ohci->ctl;
1477 break;
1478
1479 case 2: /* HcCommandStatus */
1480 retval = ohci->status;
1481 break;
1482
1483 case 3: /* HcInterruptStatus */
1484 retval = ohci->intr_status;
1485 break;
1486
1487 case 4: /* HcInterruptEnable */
1488 case 5: /* HcInterruptDisable */
1489 retval = ohci->intr;
1490 break;
1491
1492 case 6: /* HcHCCA */
1493 retval = ohci->hcca;
1494 break;
1495
1496 case 7: /* HcPeriodCurrentED */
1497 retval = ohci->per_cur;
1498 break;
1499
1500 case 8: /* HcControlHeadED */
1501 retval = ohci->ctrl_head;
1502 break;
1503
1504 case 9: /* HcControlCurrentED */
1505 retval = ohci->ctrl_cur;
1506 break;
1507
1508 case 10: /* HcBulkHeadED */
1509 retval = ohci->bulk_head;
1510 break;
1511
1512 case 11: /* HcBulkCurrentED */
1513 retval = ohci->bulk_cur;
1514 break;
1515
1516 case 12: /* HcDoneHead */
1517 retval = ohci->done;
1518 break;
1519
1520 case 13: /* HcFmInterretval */
1521 retval = (ohci->fit << 31) | (ohci->fsmps << 16) | (ohci->fi);
1522 break;
1523
1524 case 14: /* HcFmRemaining */
1525 retval = ohci_get_frame_remaining(ohci);
1526 break;
1527
1528 case 15: /* HcFmNumber */
1529 retval = ohci->frame_number;
1530 break;
1531
1532 case 16: /* HcPeriodicStart */
1533 retval = ohci->pstart;
1534 break;
1535
1536 case 17: /* HcLSThreshold */
1537 retval = ohci->lst;
1538 break;
1539
1540 case 18: /* HcRhDescriptorA */
1541 retval = ohci->rhdesc_a;
1542 break;
1543
1544 case 19: /* HcRhDescriptorB */
1545 retval = ohci->rhdesc_b;
1546 break;
1547
1548 case 20: /* HcRhStatus */
1549 retval = ohci->rhstatus;
1550 break;
1551
1552 /* PXA27x specific registers */
1553 case 24: /* HcStatus */
1554 retval = ohci->hstatus & ohci->hmask;
1555 break;
1556
1557 case 25: /* HcHReset */
1558 retval = ohci->hreset;
1559 break;
1560
1561 case 26: /* HcHInterruptEnable */
1562 retval = ohci->hmask;
1563 break;
1564
1565 case 27: /* HcHInterruptTest */
1566 retval = ohci->htest;
1567 break;
1568
1569 default:
1570 trace_usb_ohci_mem_read_bad_offset(addr);
1571 retval = 0xffffffff;
1572 }
1573 }
1574
1575 return retval;
1576 }
1577
1578 static void ohci_mem_write(void *opaque,
1579 hwaddr addr,
1580 uint64_t val,
1581 unsigned size)
1582 {
1583 OHCIState *ohci = opaque;
1584
1585 /* Only aligned reads are allowed on OHCI */
1586 if (addr & 3) {
1587 trace_usb_ohci_mem_write_unaligned(addr);
1588 return;
1589 }
1590
1591 if (addr >= 0x54 && addr < 0x54 + ohci->num_ports * 4) {
1592 /* HcRhPortStatus */
1593 ohci_port_set_status(ohci, (addr - 0x54) >> 2, val);
1594 return;
1595 }
1596
1597 switch (addr >> 2) {
1598 case 1: /* HcControl */
1599 ohci_set_ctl(ohci, val);
1600 break;
1601
1602 case 2: /* HcCommandStatus */
1603 /* SOC is read-only */
1604 val = (val & ~OHCI_STATUS_SOC);
1605
1606 /* Bits written as '0' remain unchanged in the register */
1607 ohci->status |= val;
1608
1609 if (ohci->status & OHCI_STATUS_HCR)
1610 ohci_soft_reset(ohci);
1611 break;
1612
1613 case 3: /* HcInterruptStatus */
1614 ohci->intr_status &= ~val;
1615 ohci_intr_update(ohci);
1616 break;
1617
1618 case 4: /* HcInterruptEnable */
1619 ohci->intr |= val;
1620 ohci_intr_update(ohci);
1621 break;
1622
1623 case 5: /* HcInterruptDisable */
1624 ohci->intr &= ~val;
1625 ohci_intr_update(ohci);
1626 break;
1627
1628 case 6: /* HcHCCA */
1629 ohci->hcca = val & OHCI_HCCA_MASK;
1630 break;
1631
1632 case 7: /* HcPeriodCurrentED */
1633 /* Ignore writes to this read-only register, Linux does them */
1634 break;
1635
1636 case 8: /* HcControlHeadED */
1637 ohci->ctrl_head = val & OHCI_EDPTR_MASK;
1638 break;
1639
1640 case 9: /* HcControlCurrentED */
1641 ohci->ctrl_cur = val & OHCI_EDPTR_MASK;
1642 break;
1643
1644 case 10: /* HcBulkHeadED */
1645 ohci->bulk_head = val & OHCI_EDPTR_MASK;
1646 break;
1647
1648 case 11: /* HcBulkCurrentED */
1649 ohci->bulk_cur = val & OHCI_EDPTR_MASK;
1650 break;
1651
1652 case 13: /* HcFmInterval */
1653 ohci->fsmps = (val & OHCI_FMI_FSMPS) >> 16;
1654 ohci->fit = (val & OHCI_FMI_FIT) >> 31;
1655 ohci_set_frame_interval(ohci, val);
1656 break;
1657
1658 case 15: /* HcFmNumber */
1659 break;
1660
1661 case 16: /* HcPeriodicStart */
1662 ohci->pstart = val & 0xffff;
1663 break;
1664
1665 case 17: /* HcLSThreshold */
1666 ohci->lst = val & 0xffff;
1667 break;
1668
1669 case 18: /* HcRhDescriptorA */
1670 ohci->rhdesc_a &= ~OHCI_RHA_RW_MASK;
1671 ohci->rhdesc_a |= val & OHCI_RHA_RW_MASK;
1672 break;
1673
1674 case 19: /* HcRhDescriptorB */
1675 break;
1676
1677 case 20: /* HcRhStatus */
1678 ohci_set_hub_status(ohci, val);
1679 break;
1680
1681 /* PXA27x specific registers */
1682 case 24: /* HcStatus */
1683 ohci->hstatus &= ~(val & ohci->hmask);
1684 break;
1685
1686 case 25: /* HcHReset */
1687 ohci->hreset = val & ~OHCI_HRESET_FSBIR;
1688 if (val & OHCI_HRESET_FSBIR)
1689 ohci_hard_reset(ohci);
1690 break;
1691
1692 case 26: /* HcHInterruptEnable */
1693 ohci->hmask = val;
1694 break;
1695
1696 case 27: /* HcHInterruptTest */
1697 ohci->htest = val;
1698 break;
1699
1700 default:
1701 trace_usb_ohci_mem_write_bad_offset(addr);
1702 break;
1703 }
1704 }
1705
1706 static const MemoryRegionOps ohci_mem_ops = {
1707 .read = ohci_mem_read,
1708 .write = ohci_mem_write,
1709 .endianness = DEVICE_LITTLE_ENDIAN,
1710 };
1711
1712 /* USBPortOps */
1713 static void ohci_attach(USBPort *port1)
1714 {
1715 OHCIState *s = port1->opaque;
1716 OHCIPort *port = &s->rhport[port1->index];
1717 uint32_t old_state = port->ctrl;
1718
1719 /* set connect status */
1720 port->ctrl |= OHCI_PORT_CCS | OHCI_PORT_CSC;
1721
1722 /* update speed */
1723 if (port->port.dev->speed == USB_SPEED_LOW) {
1724 port->ctrl |= OHCI_PORT_LSDA;
1725 } else {
1726 port->ctrl &= ~OHCI_PORT_LSDA;
1727 }
1728
1729 /* notify of remote-wakeup */
1730 if ((s->ctl & OHCI_CTL_HCFS) == OHCI_USB_SUSPEND) {
1731 ohci_set_interrupt(s, OHCI_INTR_RD);
1732 }
1733
1734 trace_usb_ohci_port_attach(port1->index);
1735
1736 if (old_state != port->ctrl) {
1737 ohci_set_interrupt(s, OHCI_INTR_RHSC);
1738 }
1739 }
1740
1741 static void ohci_child_detach(USBPort *port1, USBDevice *dev)
1742 {
1743 OHCIState *ohci = port1->opaque;
1744
1745 if (ohci->async_td &&
1746 usb_packet_is_inflight(&ohci->usb_packet) &&
1747 ohci->usb_packet.ep->dev == dev) {
1748 usb_cancel_packet(&ohci->usb_packet);
1749 ohci->async_td = 0;
1750 }
1751 }
1752
1753 static void ohci_detach(USBPort *port1)
1754 {
1755 OHCIState *s = port1->opaque;
1756 OHCIPort *port = &s->rhport[port1->index];
1757 uint32_t old_state = port->ctrl;
1758
1759 ohci_child_detach(port1, port1->dev);
1760
1761 /* set connect status */
1762 if (port->ctrl & OHCI_PORT_CCS) {
1763 port->ctrl &= ~OHCI_PORT_CCS;
1764 port->ctrl |= OHCI_PORT_CSC;
1765 }
1766 /* disable port */
1767 if (port->ctrl & OHCI_PORT_PES) {
1768 port->ctrl &= ~OHCI_PORT_PES;
1769 port->ctrl |= OHCI_PORT_PESC;
1770 }
1771 trace_usb_ohci_port_detach(port1->index);
1772
1773 if (old_state != port->ctrl) {
1774 ohci_set_interrupt(s, OHCI_INTR_RHSC);
1775 }
1776 }
1777
1778 static void ohci_wakeup(USBPort *port1)
1779 {
1780 OHCIState *s = port1->opaque;
1781 OHCIPort *port = &s->rhport[port1->index];
1782 uint32_t intr = 0;
1783 if (port->ctrl & OHCI_PORT_PSS) {
1784 trace_usb_ohci_port_wakeup(port1->index);
1785 port->ctrl |= OHCI_PORT_PSSC;
1786 port->ctrl &= ~OHCI_PORT_PSS;
1787 intr = OHCI_INTR_RHSC;
1788 }
1789 /* Note that the controller can be suspended even if this port is not */
1790 if ((s->ctl & OHCI_CTL_HCFS) == OHCI_USB_SUSPEND) {
1791 trace_usb_ohci_remote_wakeup(s->name);
1792 /* This is the one state transition the controller can do by itself */
1793 s->ctl &= ~OHCI_CTL_HCFS;
1794 s->ctl |= OHCI_USB_RESUME;
1795 /*
1796 * In suspend mode only ResumeDetected is possible, not RHSC:
1797 * see the OHCI spec 5.1.2.3.
1798 */
1799 intr = OHCI_INTR_RD;
1800 }
1801 ohci_set_interrupt(s, intr);
1802 }
1803
1804 static void ohci_async_complete_packet(USBPort *port, USBPacket *packet)
1805 {
1806 OHCIState *ohci = container_of(packet, OHCIState, usb_packet);
1807
1808 trace_usb_ohci_async_complete();
1809 ohci->async_complete = true;
1810 ohci_process_lists(ohci);
1811 }
1812
1813 static USBPortOps ohci_port_ops = {
1814 .attach = ohci_attach,
1815 .detach = ohci_detach,
1816 .child_detach = ohci_child_detach,
1817 .wakeup = ohci_wakeup,
1818 .complete = ohci_async_complete_packet,
1819 };
1820
1821 static USBBusOps ohci_bus_ops = {
1822 };
1823
1824 void usb_ohci_init(OHCIState *ohci, DeviceState *dev, uint32_t num_ports,
1825 dma_addr_t localmem_base, char *masterbus,
1826 uint32_t firstport, AddressSpace *as,
1827 void (*ohci_die_fn)(OHCIState *), Error **errp)
1828 {
1829 Error *err = NULL;
1830 int i;
1831
1832 ohci->as = as;
1833 ohci->ohci_die = ohci_die_fn;
1834
1835 if (num_ports > OHCI_MAX_PORTS) {
1836 error_setg(errp, "OHCI num-ports=%u is too big (limit is %u ports)",
1837 num_ports, OHCI_MAX_PORTS);
1838 return;
1839 }
1840
1841 if (usb_frame_time == 0) {
1842 #ifdef OHCI_TIME_WARP
1843 usb_frame_time = NANOSECONDS_PER_SECOND;
1844 usb_bit_time = NANOSECONDS_PER_SECOND / (USB_HZ / 1000);
1845 #else
1846 usb_frame_time = NANOSECONDS_PER_SECOND / 1000;
1847 if (NANOSECONDS_PER_SECOND >= USB_HZ) {
1848 usb_bit_time = NANOSECONDS_PER_SECOND / USB_HZ;
1849 } else {
1850 usb_bit_time = 1;
1851 }
1852 #endif
1853 trace_usb_ohci_init_time(usb_frame_time, usb_bit_time);
1854 }
1855
1856 ohci->num_ports = num_ports;
1857 if (masterbus) {
1858 USBPort *ports[OHCI_MAX_PORTS];
1859 for (i = 0; i < num_ports; i++) {
1860 ports[i] = &ohci->rhport[i].port;
1861 }
1862 usb_register_companion(masterbus, ports, num_ports,
1863 firstport, ohci, &ohci_port_ops,
1864 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL,
1865 &err);
1866 if (err) {
1867 error_propagate(errp, err);
1868 return;
1869 }
1870 } else {
1871 usb_bus_new(&ohci->bus, sizeof(ohci->bus), &ohci_bus_ops, dev);
1872 for (i = 0; i < num_ports; i++) {
1873 usb_register_port(&ohci->bus, &ohci->rhport[i].port,
1874 ohci, i, &ohci_port_ops,
1875 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL);
1876 }
1877 }
1878
1879 memory_region_init_io(&ohci->mem, OBJECT(dev), &ohci_mem_ops,
1880 ohci, "ohci", 256);
1881 ohci->localmem_base = localmem_base;
1882
1883 ohci->name = object_get_typename(OBJECT(dev));
1884 usb_packet_init(&ohci->usb_packet);
1885
1886 ohci->async_td = 0;
1887
1888 ohci->eof_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
1889 ohci_frame_boundary, ohci);
1890 }
1891
1892 /*
1893 * A typical OHCI will stop operating and set itself into error state
1894 * (which can be queried by MMIO) to signal that it got an error.
1895 */
1896 void ohci_sysbus_die(struct OHCIState *ohci)
1897 {
1898 trace_usb_ohci_die();
1899
1900 ohci_set_interrupt(ohci, OHCI_INTR_UE);
1901 ohci_bus_stop(ohci);
1902 }
1903
1904 static void ohci_realize_pxa(DeviceState *dev, Error **errp)
1905 {
1906 OHCISysBusState *s = SYSBUS_OHCI(dev);
1907 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
1908 Error *err = NULL;
1909
1910 usb_ohci_init(&s->ohci, dev, s->num_ports, s->dma_offset,
1911 s->masterbus, s->firstport,
1912 &address_space_memory, ohci_sysbus_die, &err);
1913 if (err) {
1914 error_propagate(errp, err);
1915 return;
1916 }
1917 sysbus_init_irq(sbd, &s->ohci.irq);
1918 sysbus_init_mmio(sbd, &s->ohci.mem);
1919 }
1920
1921 static void usb_ohci_reset_sysbus(DeviceState *dev)
1922 {
1923 OHCISysBusState *s = SYSBUS_OHCI(dev);
1924 OHCIState *ohci = &s->ohci;
1925
1926 ohci_hard_reset(ohci);
1927 }
1928
1929 static const VMStateDescription vmstate_ohci_state_port = {
1930 .name = "ohci-core/port",
1931 .version_id = 1,
1932 .minimum_version_id = 1,
1933 .fields = (VMStateField[]) {
1934 VMSTATE_UINT32(ctrl, OHCIPort),
1935 VMSTATE_END_OF_LIST()
1936 },
1937 };
1938
1939 static bool ohci_eof_timer_needed(void *opaque)
1940 {
1941 OHCIState *ohci = opaque;
1942
1943 return timer_pending(ohci->eof_timer);
1944 }
1945
1946 static const VMStateDescription vmstate_ohci_eof_timer = {
1947 .name = "ohci-core/eof-timer",
1948 .version_id = 1,
1949 .minimum_version_id = 1,
1950 .needed = ohci_eof_timer_needed,
1951 .fields = (VMStateField[]) {
1952 VMSTATE_TIMER_PTR(eof_timer, OHCIState),
1953 VMSTATE_END_OF_LIST()
1954 },
1955 };
1956
1957 const VMStateDescription vmstate_ohci_state = {
1958 .name = "ohci-core",
1959 .version_id = 1,
1960 .minimum_version_id = 1,
1961 .fields = (VMStateField[]) {
1962 VMSTATE_INT64(sof_time, OHCIState),
1963 VMSTATE_UINT32(ctl, OHCIState),
1964 VMSTATE_UINT32(status, OHCIState),
1965 VMSTATE_UINT32(intr_status, OHCIState),
1966 VMSTATE_UINT32(intr, OHCIState),
1967 VMSTATE_UINT32(hcca, OHCIState),
1968 VMSTATE_UINT32(ctrl_head, OHCIState),
1969 VMSTATE_UINT32(ctrl_cur, OHCIState),
1970 VMSTATE_UINT32(bulk_head, OHCIState),
1971 VMSTATE_UINT32(bulk_cur, OHCIState),
1972 VMSTATE_UINT32(per_cur, OHCIState),
1973 VMSTATE_UINT32(done, OHCIState),
1974 VMSTATE_INT32(done_count, OHCIState),
1975 VMSTATE_UINT16(fsmps, OHCIState),
1976 VMSTATE_UINT8(fit, OHCIState),
1977 VMSTATE_UINT16(fi, OHCIState),
1978 VMSTATE_UINT8(frt, OHCIState),
1979 VMSTATE_UINT16(frame_number, OHCIState),
1980 VMSTATE_UINT16(padding, OHCIState),
1981 VMSTATE_UINT32(pstart, OHCIState),
1982 VMSTATE_UINT32(lst, OHCIState),
1983 VMSTATE_UINT32(rhdesc_a, OHCIState),
1984 VMSTATE_UINT32(rhdesc_b, OHCIState),
1985 VMSTATE_UINT32(rhstatus, OHCIState),
1986 VMSTATE_STRUCT_ARRAY(rhport, OHCIState, OHCI_MAX_PORTS, 0,
1987 vmstate_ohci_state_port, OHCIPort),
1988 VMSTATE_UINT32(hstatus, OHCIState),
1989 VMSTATE_UINT32(hmask, OHCIState),
1990 VMSTATE_UINT32(hreset, OHCIState),
1991 VMSTATE_UINT32(htest, OHCIState),
1992 VMSTATE_UINT32(old_ctl, OHCIState),
1993 VMSTATE_UINT8_ARRAY(usb_buf, OHCIState, 8192),
1994 VMSTATE_UINT32(async_td, OHCIState),
1995 VMSTATE_BOOL(async_complete, OHCIState),
1996 VMSTATE_END_OF_LIST()
1997 },
1998 .subsections = (const VMStateDescription*[]) {
1999 &vmstate_ohci_eof_timer,
2000 NULL
2001 }
2002 };
2003
2004 static Property ohci_sysbus_properties[] = {
2005 DEFINE_PROP_STRING("masterbus", OHCISysBusState, masterbus),
2006 DEFINE_PROP_UINT32("num-ports", OHCISysBusState, num_ports, 3),
2007 DEFINE_PROP_UINT32("firstport", OHCISysBusState, firstport, 0),
2008 DEFINE_PROP_DMAADDR("dma-offset", OHCISysBusState, dma_offset, 0),
2009 DEFINE_PROP_END_OF_LIST(),
2010 };
2011
2012 static void ohci_sysbus_class_init(ObjectClass *klass, void *data)
2013 {
2014 DeviceClass *dc = DEVICE_CLASS(klass);
2015
2016 dc->realize = ohci_realize_pxa;
2017 set_bit(DEVICE_CATEGORY_USB, dc->categories);
2018 dc->desc = "OHCI USB Controller";
2019 device_class_set_props(dc, ohci_sysbus_properties);
2020 dc->reset = usb_ohci_reset_sysbus;
2021 }
2022
2023 static const TypeInfo ohci_sysbus_info = {
2024 .name = TYPE_SYSBUS_OHCI,
2025 .parent = TYPE_SYS_BUS_DEVICE,
2026 .instance_size = sizeof(OHCISysBusState),
2027 .class_init = ohci_sysbus_class_init,
2028 };
2029
2030 static void ohci_register_types(void)
2031 {
2032 type_register_static(&ohci_sysbus_info);
2033 }
2034
2035 type_init(ohci_register_types)
armbru's QEMU hackery