2 * QEMU PowerPC PowerNV XSCOM bus
4 * Copyright (c) 2016, IBM Corporation.
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
22 #include "qemu/module.h"
23 #include "sysemu/hw_accel.h"
24 #include "target/ppc/cpu.h"
25 #include "hw/sysbus.h"
27 #include "hw/ppc/fdt.h"
28 #include "hw/ppc/pnv.h"
29 #include "hw/ppc/pnv_chip.h"
30 #include "hw/ppc/pnv_xscom.h"
35 #define PRD_P8_IPOLL_REG_MASK 0x01020013
36 #define PRD_P8_IPOLL_REG_STATUS 0x01020014
37 #define PRD_P9_IPOLL_REG_MASK 0x000F0033
38 #define PRD_P9_IPOLL_REG_STATUS 0x000F0034
40 static void xscom_complete(CPUState
*cs
, uint64_t hmer_bits
)
43 * TODO: When the read/write comes from the monitor, NULL is
44 * passed for the cpu, and no CPU completion is generated.
48 * TODO: Need a CPU helper to set HMER, also handle generation
51 cpu_synchronize_state(cs
);
52 cpu_env(cs
)->spr
[SPR_HMER
] |= hmer_bits
;
56 static uint32_t pnv_xscom_pcba(PnvChip
*chip
, uint64_t addr
)
58 return PNV_CHIP_GET_CLASS(chip
)->xscom_pcba(chip
, addr
);
61 static uint64_t xscom_read_default(PnvChip
*chip
, uint32_t pcba
)
65 return PNV_CHIP_GET_CLASS(chip
)->chip_cfam_id
;
66 case 0x18002: /* ECID2 */
69 case 0x1010c00: /* PIBAM FIR */
70 case 0x1010c03: /* PIBAM FIR MASK */
73 case PRD_P8_IPOLL_REG_MASK
:
74 case PRD_P8_IPOLL_REG_STATUS
:
75 case PRD_P9_IPOLL_REG_MASK
:
76 case PRD_P9_IPOLL_REG_STATUS
:
79 case 0x0090018: /* Receive status reg */
80 case 0x0090012: /* log register */
81 case 0x0090013: /* error register */
84 case 0x2020007: /* ADU stuff, log register */
85 case 0x2020009: /* ADU stuff, error register */
86 case 0x202000f: /* ADU stuff, receive status register*/
88 case 0x2013f01: /* PBA stuff */
89 case 0x2013f05: /* PBA stuff */
91 case 0x2013028: /* CAPP stuff */
92 case 0x201302a: /* CAPP stuff */
93 case 0x2013801: /* CAPP stuff */
94 case 0x2013802: /* CAPP stuff */
111 static bool xscom_write_default(PnvChip
*chip
, uint32_t pcba
, uint64_t val
)
113 /* We ignore writes to these */
115 case 0xf000f: /* chip id is RO */
116 case 0x1010c00: /* PIBAM FIR */
117 case 0x1010c01: /* PIBAM FIR */
118 case 0x1010c02: /* PIBAM FIR */
119 case 0x1010c03: /* PIBAM FIR MASK */
120 case 0x1010c04: /* PIBAM FIR MASK */
121 case 0x1010c05: /* PIBAM FIR MASK */
123 case 0x0090018: /* Receive status reg */
124 case 0x0090012: /* log register */
125 case 0x0090013: /* error register */
128 case 0x2020007: /* ADU stuff, log register */
129 case 0x2020009: /* ADU stuff, error register */
130 case 0x202000f: /* ADU stuff, receive status register*/
132 case 0x2013028: /* CAPP stuff */
133 case 0x201302a: /* CAPP stuff */
134 case 0x2013801: /* CAPP stuff */
135 case 0x2013802: /* CAPP stuff */
147 /* P8 PRD registers */
148 case PRD_P8_IPOLL_REG_MASK
:
149 case PRD_P8_IPOLL_REG_STATUS
:
150 case PRD_P9_IPOLL_REG_MASK
:
151 case PRD_P9_IPOLL_REG_STATUS
:
158 static uint64_t xscom_read(void *opaque
, hwaddr addr
, unsigned width
)
160 PnvChip
*chip
= opaque
;
161 uint32_t pcba
= pnv_xscom_pcba(chip
, addr
);
165 /* Handle some SCOMs here before dispatch */
166 val
= xscom_read_default(chip
, pcba
);
171 val
= address_space_ldq(&chip
->xscom_as
, (uint64_t) pcba
<< 3,
172 MEMTXATTRS_UNSPECIFIED
, &result
);
173 if (result
!= MEMTX_OK
) {
174 qemu_log_mask(LOG_GUEST_ERROR
, "XSCOM read failed at @0x%"
175 HWADDR_PRIx
" pcba=0x%08x\n", addr
, pcba
);
176 xscom_complete(current_cpu
, HMER_XSCOM_FAIL
| HMER_XSCOM_DONE
);
181 xscom_complete(current_cpu
, HMER_XSCOM_DONE
);
185 static void xscom_write(void *opaque
, hwaddr addr
, uint64_t val
,
188 PnvChip
*chip
= opaque
;
189 uint32_t pcba
= pnv_xscom_pcba(chip
, addr
);
192 /* Handle some SCOMs here before dispatch */
193 if (xscom_write_default(chip
, pcba
, val
)) {
197 address_space_stq(&chip
->xscom_as
, (uint64_t) pcba
<< 3, val
,
198 MEMTXATTRS_UNSPECIFIED
, &result
);
199 if (result
!= MEMTX_OK
) {
200 qemu_log_mask(LOG_GUEST_ERROR
, "XSCOM write failed at @0x%"
201 HWADDR_PRIx
" pcba=0x%08x data=0x%" PRIx64
"\n",
203 xscom_complete(current_cpu
, HMER_XSCOM_FAIL
| HMER_XSCOM_DONE
);
208 xscom_complete(current_cpu
, HMER_XSCOM_DONE
);
211 const MemoryRegionOps pnv_xscom_ops
= {
213 .write
= xscom_write
,
214 .valid
.min_access_size
= 8,
215 .valid
.max_access_size
= 8,
216 .impl
.min_access_size
= 8,
217 .impl
.max_access_size
= 8,
218 .endianness
= DEVICE_BIG_ENDIAN
,
221 void pnv_xscom_init(PnvChip
*chip
, uint64_t size
, hwaddr addr
)
225 name
= g_strdup_printf("xscom-%x", chip
->chip_id
);
226 memory_region_init_io(&chip
->xscom_mmio
, OBJECT(chip
), &pnv_xscom_ops
,
228 memory_region_add_subregion(get_system_memory(), addr
, &chip
->xscom_mmio
);
230 memory_region_init(&chip
->xscom
, OBJECT(chip
), name
, size
);
231 address_space_init(&chip
->xscom_as
, &chip
->xscom
, name
);
235 static const TypeInfo pnv_xscom_interface_info
= {
236 .name
= TYPE_PNV_XSCOM_INTERFACE
,
237 .parent
= TYPE_INTERFACE
,
238 .class_size
= sizeof(PnvXScomInterfaceClass
),
241 static void pnv_xscom_register_types(void)
243 type_register_static(&pnv_xscom_interface_info
);
246 type_init(pnv_xscom_register_types
)
248 typedef struct ForeachPopulateArgs
{
251 } ForeachPopulateArgs
;
253 static int xscom_dt_child(Object
*child
, void *opaque
)
255 if (object_dynamic_cast(child
, TYPE_PNV_XSCOM_INTERFACE
)) {
256 ForeachPopulateArgs
*args
= opaque
;
257 PnvXScomInterface
*xd
= PNV_XSCOM_INTERFACE(child
);
258 PnvXScomInterfaceClass
*xc
= PNV_XSCOM_INTERFACE_GET_CLASS(xd
);
261 * Only "realized" devices should be configured in the DT
263 if (xc
->dt_xscom
&& DEVICE(child
)->realized
) {
264 _FDT((xc
->dt_xscom(xd
, args
->fdt
, args
->xscom_offset
)));
270 int pnv_dt_xscom(PnvChip
*chip
, void *fdt
, int root_offset
,
271 uint64_t xscom_base
, uint64_t xscom_size
,
272 const char *compat
, int compat_size
)
274 uint64_t reg
[] = { xscom_base
, xscom_size
};
276 ForeachPopulateArgs args
;
279 name
= g_strdup_printf("xscom@%" PRIx64
, be64_to_cpu(reg
[0]));
280 xscom_offset
= fdt_add_subnode(fdt
, root_offset
, name
);
283 _FDT((fdt_setprop_cell(fdt
, xscom_offset
, "ibm,chip-id", chip
->chip_id
)));
285 * On P10, the xscom bus id has been deprecated and the chip id is
286 * calculated from the "Primary topology table index". See skiboot.
288 _FDT((fdt_setprop_cell(fdt
, xscom_offset
, "ibm,primary-topology-index",
290 _FDT((fdt_setprop_cell(fdt
, xscom_offset
, "#address-cells", 1)));
291 _FDT((fdt_setprop_cell(fdt
, xscom_offset
, "#size-cells", 1)));
292 _FDT((fdt_setprop(fdt
, xscom_offset
, "reg", reg
, sizeof(reg
))));
293 _FDT((fdt_setprop(fdt
, xscom_offset
, "compatible", compat
, compat_size
)));
294 _FDT((fdt_setprop(fdt
, xscom_offset
, "scom-controller", NULL
, 0)));
295 if (chip
->chip_id
== 0) {
296 _FDT((fdt_setprop(fdt
, xscom_offset
, "primary", NULL
, 0)));
300 args
.xscom_offset
= xscom_offset
;
303 * Loop on the whole object hierarchy to catch all
304 * PnvXScomInterface objects which can lie a bit deeper than the
307 object_child_foreach_recursive(OBJECT(chip
), xscom_dt_child
, &args
);
311 void pnv_xscom_add_subregion(PnvChip
*chip
, hwaddr offset
, MemoryRegion
*mr
)
313 memory_region_add_subregion(&chip
->xscom
, offset
<< 3, mr
);
316 void pnv_xscom_region_init(MemoryRegion
*mr
,
318 const MemoryRegionOps
*ops
,
323 memory_region_init_io(mr
, owner
, ops
, opaque
, name
, size
<< 3);