2 * QEMU CXL PCI interfaces
4 * Copyright (c) 2020 Intel
6 * This work is licensed under the terms of the GNU GPL, version 2. See the
7 * COPYING file in the top-level directory.
14 #define CXL_VENDOR_ID 0x1e98
16 #define PCIE_DVSEC_HEADER1_OFFSET 0x4 /* Offset from start of extend cap */
17 #define PCIE_DVSEC_ID_OFFSET 0x8
19 #define PCIE_CXL_DEVICE_DVSEC_LENGTH 0x38
20 #define PCIE_CXL1_DEVICE_DVSEC_REVID 0
21 #define PCIE_CXL2_DEVICE_DVSEC_REVID 1
23 #define EXTENSIONS_PORT_DVSEC_LENGTH 0x28
24 #define EXTENSIONS_PORT_DVSEC_REVID 0
26 #define GPF_PORT_DVSEC_LENGTH 0x10
27 #define GPF_PORT_DVSEC_REVID 0
29 #define GPF_DEVICE_DVSEC_LENGTH 0x10
30 #define GPF_DEVICE_DVSEC_REVID 0
32 #define PCIE_FLEXBUS_PORT_DVSEC_LENGTH_2_0 0x14
33 #define PCIE_FLEXBUS_PORT_DVSEC_REVID_2_0 1
35 #define REG_LOC_DVSEC_LENGTH 0x24
36 #define REG_LOC_DVSEC_REVID 0
39 PCIE_CXL_DEVICE_DVSEC
= 0,
40 NON_CXL_FUNCTION_MAP_DVSEC
= 2,
41 EXTENSIONS_PORT_DVSEC
= 3,
44 PCIE_FLEXBUS_PORT_DVSEC
= 7,
50 typedef struct DVSECHeader
{
54 } QEMU_PACKED DVSECHeader
;
55 QEMU_BUILD_BUG_ON(sizeof(DVSECHeader
) != 10);
58 * CXL 2.0 devices must implement certain DVSEC IDs, and can [optionally]
61 * CXL 2.0 Device: 0, [2], 5, 8
62 * CXL 2.0 RP: 3, 4, 7, 8
63 * CXL 2.0 Upstream Port: [2], 7, 8
64 * CXL 2.0 Downstream Port: 3, 4, 7, 8
67 /* CXL 2.0 - 8.1.3 (ID 0001) */
68 typedef struct CXLDVSECDevice
{
77 uint32_t range1_size_hi
;
78 uint32_t range1_size_lo
;
79 uint32_t range1_base_hi
;
80 uint32_t range1_base_lo
;
81 uint32_t range2_size_hi
;
82 uint32_t range2_size_lo
;
83 uint32_t range2_base_hi
;
84 uint32_t range2_base_lo
;
86 QEMU_BUILD_BUG_ON(sizeof(CXLDVSECDevice
) != 0x38);
88 /* CXL 2.0 - 8.1.5 (ID 0003) */
89 typedef struct CXLDVSECPortExtensions
{
94 uint8_t alt_bus_limit
;
95 uint16_t alt_memory_base
;
96 uint16_t alt_memory_limit
;
97 uint16_t alt_prefetch_base
;
98 uint16_t alt_prefetch_limit
;
99 uint32_t alt_prefetch_base_high
;
100 uint32_t alt_prefetch_limit_high
;
102 uint32_t rcrb_base_high
;
103 } CXLDVSECPortExtensions
;
104 QEMU_BUILD_BUG_ON(sizeof(CXLDVSECPortExtensions
) != 0x28);
106 #define PORT_CONTROL_OFFSET 0xc
107 #define PORT_CONTROL_UNMASK_SBR 1
108 #define PORT_CONTROL_ALT_MEMID_EN 4
110 /* CXL 2.0 - 8.1.6 GPF DVSEC (ID 0004) */
111 typedef struct CXLDVSECPortGPF
{
114 uint16_t phase1_ctrl
;
115 uint16_t phase2_ctrl
;
117 QEMU_BUILD_BUG_ON(sizeof(CXLDVSECPortGPF
) != 0x10);
119 /* CXL 2.0 - 8.1.7 GPF DVSEC for CXL Device */
120 typedef struct CXLDVSECDeviceGPF
{
122 uint16_t phase2_duration
;
123 uint32_t phase2_power
;
125 QEMU_BUILD_BUG_ON(sizeof(CXLDVSECDeviceGPF
) != 0x10);
127 /* CXL 2.0 - 8.1.8/8.2.1.3 Flex Bus DVSEC (ID 0007) */
128 typedef struct CXLDVSECPortFlexBus
{
133 uint32_t rcvd_mod_ts_data_phase1
;
134 } CXLDVSECPortFlexBus
;
135 QEMU_BUILD_BUG_ON(sizeof(CXLDVSECPortFlexBus
) != 0x14);
137 /* CXL 2.0 - 8.1.9 Register Locator DVSEC (ID 0008) */
138 typedef struct CXLDVSECRegisterLocator
{
141 uint32_t reg0_base_lo
;
142 uint32_t reg0_base_hi
;
143 uint32_t reg1_base_lo
;
144 uint32_t reg1_base_hi
;
145 uint32_t reg2_base_lo
;
146 uint32_t reg2_base_hi
;
147 } CXLDVSECRegisterLocator
;
148 QEMU_BUILD_BUG_ON(sizeof(CXLDVSECRegisterLocator
) != 0x24);
150 /* BAR Equivalence Indicator */
151 #define BEI_BAR_10H 0
152 #define BEI_BAR_14H 1
153 #define BEI_BAR_18H 2
154 #define BEI_BAR_1cH 3
155 #define BEI_BAR_20H 4
156 #define BEI_BAR_24H 5
158 /* Register Block Identifier */
160 #define RBI_COMPONENT_REG (1 << 8)
161 #define RBI_BAR_VIRT_ACL (2 << 8)
162 #define RBI_CXL_DEVICE_REG (3 << 8)