4 * Copyright (c) 2024, IBM Corporation.
6 * SPDX-License-Identifier: GPL-2.0-or-later
12 #define SMT 4 /* some tests will break if less than 4 */
14 typedef enum PnvChipType
{
15 PNV_CHIP_POWER8E
, /* AKA Murano (default) */
16 PNV_CHIP_POWER8
, /* AKA Venice */
17 PNV_CHIP_POWER8NVL
, /* AKA Naples */
18 PNV_CHIP_POWER9
, /* AKA Nimbus */
22 typedef struct PnvChip
{
23 PnvChipType chip_type
;
24 const char *cpu_model
;
31 static const PnvChip pnv_chips
[] = {
33 .chip_type
= PNV_CHIP_POWER8
,
34 .cpu_model
= "POWER8",
35 .xscom_base
= 0x0003fc0000000000ull
,
36 .cfam_id
= 0x220ea04980000000ull
,
40 .chip_type
= PNV_CHIP_POWER8NVL
,
41 .cpu_model
= "POWER8NVL",
42 .xscom_base
= 0x0003fc0000000000ull
,
43 .cfam_id
= 0x120d304980000000ull
,
48 .chip_type
= PNV_CHIP_POWER9
,
49 .cpu_model
= "POWER9",
50 .xscom_base
= 0x000603fc00000000ull
,
51 .cfam_id
= 0x220d104900008000ull
,
56 .chip_type
= PNV_CHIP_POWER10
,
57 .cpu_model
= "POWER10",
58 .xscom_base
= 0x000603fc00000000ull
,
59 .cfam_id
= 0x120da04900008000ull
,
65 static inline uint64_t pnv_xscom_addr(const PnvChip
*chip
, uint32_t pcba
)
67 uint64_t addr
= chip
->xscom_base
;
69 if (chip
->chip_type
== PNV_CHIP_POWER10
) {
70 addr
|= ((uint64_t) pcba
<< 3);
71 } else if (chip
->chip_type
== PNV_CHIP_POWER9
) {
72 addr
|= ((uint64_t) pcba
<< 3);
74 addr
|= (((uint64_t) pcba
<< 4) & ~0xffull
) |
75 (((uint64_t) pcba
<< 3) & 0x78);
80 #endif /* PNV_XSCOM_H */