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ppc/pnv: Introduce pnv_chip_foreach_cpu()
[qemu/armbru.git] / hw / ppc / pnv.c
blob6b41d1d2dd1aaa4c16cbc84455f18cfc707a8ac6
1 /*
2 * QEMU PowerPC PowerNV machine model
3 *
4 * Copyright (c) 2016, IBM Corporation.
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "qemu/datadir.h"
22 #include "qemu/units.h"
23 #include "qemu/cutils.h"
24 #include "qapi/error.h"
25 #include "sysemu/qtest.h"
26 #include "sysemu/sysemu.h"
27 #include "sysemu/numa.h"
28 #include "sysemu/reset.h"
29 #include "sysemu/runstate.h"
30 #include "sysemu/cpus.h"
31 #include "sysemu/device_tree.h"
32 #include "sysemu/hw_accel.h"
33 #include "target/ppc/cpu.h"
34 #include "hw/ppc/fdt.h"
35 #include "hw/ppc/ppc.h"
36 #include "hw/ppc/pnv.h"
37 #include "hw/ppc/pnv_core.h"
38 #include "hw/loader.h"
39 #include "hw/nmi.h"
40 #include "qapi/visitor.h"
41 #include "hw/intc/intc.h"
42 #include "hw/ipmi/ipmi.h"
43 #include "target/ppc/mmu-hash64.h"
44 #include "hw/pci/msi.h"
45 #include "hw/pci-host/pnv_phb.h"
46 #include "hw/pci-host/pnv_phb3.h"
47 #include "hw/pci-host/pnv_phb4.h"
48
49 #include "hw/ppc/xics.h"
50 #include "hw/qdev-properties.h"
51 #include "hw/ppc/pnv_chip.h"
52 #include "hw/ppc/pnv_xscom.h"
53 #include "hw/ppc/pnv_pnor.h"
54
55 #include "hw/isa/isa.h"
56 #include "hw/char/serial.h"
57 #include "hw/rtc/mc146818rtc.h"
58
59 #include <libfdt.h>
60
61 #define FDT_MAX_SIZE (1 * MiB)
62
63 #define FW_FILE_NAME "skiboot.lid"
64 #define FW_LOAD_ADDR 0x0
65 #define FW_MAX_SIZE (16 * MiB)
66
67 #define KERNEL_LOAD_ADDR 0x20000000
68 #define KERNEL_MAX_SIZE (128 * MiB)
69 #define INITRD_LOAD_ADDR 0x28000000
70 #define INITRD_MAX_SIZE (128 * MiB)
71
72 static const char *pnv_chip_core_typename(const PnvChip *o)
73 {
74 const char *chip_type = object_class_get_name(object_get_class(OBJECT(o)));
75 int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX);
76 char *s = g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len, chip_type);
77 const char *core_type = object_class_get_name(object_class_by_name(s));
78 g_free(s);
79 return core_type;
80 }
81
82 /*
83 * On Power Systems E880 (POWER8), the max cpus (threads) should be :
84 * 4 * 4 sockets * 12 cores * 8 threads = 1536
85 * Let's make it 2^11
86 */
87 #define MAX_CPUS 2048
88
89 /*
90 * Memory nodes are created by hostboot, one for each range of memory
91 * that has a different "affinity". In practice, it means one range
92 * per chip.
93 */
94 static void pnv_dt_memory(void *fdt, int chip_id, hwaddr start, hwaddr size)
95 {
96 char *mem_name;
97 uint64_t mem_reg_property[2];
98 int off;
99
100 mem_reg_property[0] = cpu_to_be64(start);
101 mem_reg_property[1] = cpu_to_be64(size);
102
103 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start);
104 off = fdt_add_subnode(fdt, 0, mem_name);
105 g_free(mem_name);
106
107 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory")));
108 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property,
109 sizeof(mem_reg_property))));
110 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id)));
111 }
112
113 static int get_cpus_node(void *fdt)
114 {
115 int cpus_offset = fdt_path_offset(fdt, "/cpus");
116
117 if (cpus_offset < 0) {
118 cpus_offset = fdt_add_subnode(fdt, 0, "cpus");
119 if (cpus_offset) {
120 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1)));
121 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0)));
122 }
123 }
124 _FDT(cpus_offset);
125 return cpus_offset;
126 }
127
128 /*
129 * The PowerNV cores (and threads) need to use real HW ids and not an
130 * incremental index like it has been done on other platforms. This HW
131 * id is stored in the CPU PIR, it is used to create cpu nodes in the
132 * device tree, used in XSCOM to address cores and in interrupt
133 * servers.
134 */
135 static int pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt)
136 {
137 PowerPCCPU *cpu = pc->threads[0];
138 CPUState *cs = CPU(cpu);
139 DeviceClass *dc = DEVICE_GET_CLASS(cs);
140 int smt_threads = CPU_CORE(pc)->nr_threads;
141 CPUPPCState *env = &cpu->env;
142 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
143 PnvChipClass *pnv_cc = PNV_CHIP_GET_CLASS(chip);
144 g_autofree uint32_t *servers_prop = g_new(uint32_t, smt_threads);
145 int i;
146 uint32_t pir;
147 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
148 0xffffffff, 0xffffffff};
149 uint32_t tbfreq = PNV_TIMEBASE_FREQ;
150 uint32_t cpufreq = 1000000000;
151 uint32_t page_sizes_prop[64];
152 size_t page_sizes_prop_size;
153 int offset;
154 char *nodename;
155 int cpus_offset = get_cpus_node(fdt);
156
157 pir = pnv_cc->chip_pir(chip, pc->hwid, 0);
158
159 nodename = g_strdup_printf("%s@%x", dc->fw_name, pir);
160 offset = fdt_add_subnode(fdt, cpus_offset, nodename);
161 _FDT(offset);
162 g_free(nodename);
163
164 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id)));
165
166 _FDT((fdt_setprop_cell(fdt, offset, "reg", pir)));
167 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pir)));
168 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu")));
169
170 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR])));
171 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size",
172 env->dcache_line_size)));
173 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size",
174 env->dcache_line_size)));
175 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size",
176 env->icache_line_size)));
177 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size",
178 env->icache_line_size)));
179
180 if (pcc->l1_dcache_size) {
181 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size",
182 pcc->l1_dcache_size)));
183 } else {
184 warn_report("Unknown L1 dcache size for cpu");
185 }
186 if (pcc->l1_icache_size) {
187 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size",
188 pcc->l1_icache_size)));
189 } else {
190 warn_report("Unknown L1 icache size for cpu");
191 }
192
193 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq)));
194 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq)));
195 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size",
196 cpu->hash64_opts->slb_size)));
197 _FDT((fdt_setprop_string(fdt, offset, "status", "okay")));
198 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0)));
199
200 if (ppc_has_spr(cpu, SPR_PURR)) {
201 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0)));
202 }
203
204 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) {
205 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes",
206 segs, sizeof(segs))));
207 }
208
209 /*
210 * Advertise VMX/VSX (vector extensions) if available
211 * 0 / no property == no vector extensions
212 * 1 == VMX / Altivec available
213 * 2 == VSX available
214 */
215 if (env->insns_flags & PPC_ALTIVEC) {
216 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1;
217
218 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx)));
219 }
220
221 /*
222 * Advertise DFP (Decimal Floating Point) if available
223 * 0 / no property == no DFP
224 * 1 == DFP available
225 */
226 if (env->insns_flags2 & PPC2_DFP) {
227 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1)));
228 }
229
230 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop,
231 sizeof(page_sizes_prop));
232 if (page_sizes_prop_size) {
233 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes",
234 page_sizes_prop, page_sizes_prop_size)));
235 }
236
237 /* Build interrupt servers properties */
238 for (i = 0; i < smt_threads; i++) {
239 servers_prop[i] = cpu_to_be32(pnv_cc->chip_pir(chip, pc->hwid, i));
240 }
241 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
242 servers_prop, sizeof(*servers_prop) * smt_threads)));
243
244 return offset;
245 }
246
247 static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t hwid,
248 uint32_t nr_threads)
249 {
250 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
251 uint32_t pir = pcc->chip_pir(chip, hwid, 0);
252 uint64_t addr = PNV_ICP_BASE(chip) | (pir << 12);
253 char *name;
254 const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp";
255 uint32_t irange[2], i, rsize;
256 uint64_t *reg;
257 int offset;
258
259 irange[0] = cpu_to_be32(pir);
260 irange[1] = cpu_to_be32(nr_threads);
261
262 rsize = sizeof(uint64_t) * 2 * nr_threads;
263 reg = g_malloc(rsize);
264 for (i = 0; i < nr_threads; i++) {
265 /* We know P8 PIR is linear with thread id */
266 reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000));
267 reg[i * 2 + 1] = cpu_to_be64(0x1000);
268 }
269
270 name = g_strdup_printf("interrupt-controller@%"PRIX64, addr);
271 offset = fdt_add_subnode(fdt, 0, name);
272 _FDT(offset);
273 g_free(name);
274
275 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat))));
276 _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize)));
277 _FDT((fdt_setprop_string(fdt, offset, "device_type",
278 "PowerPC-External-Interrupt-Presentation")));
279 _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0)));
280 _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges",
281 irange, sizeof(irange))));
282 _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1)));
283 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0)));
284 g_free(reg);
285 }
286
287 /*
288 * Adds a PnvPHB to the chip on P8.
289 * Implemented here, like for defaults PHBs
290 */
291 PnvChip *pnv_chip_add_phb(PnvChip *chip, PnvPHB *phb)
292 {
293 Pnv8Chip *chip8 = PNV8_CHIP(chip);
294
295 phb->chip = chip;
296
297 chip8->phbs[chip8->num_phbs] = phb;
298 chip8->num_phbs++;
299 return chip;
300 }
301
302 /*
303 * Same as spapr pa_features_207 except pnv always enables CI largepages bit.
304 * HTM is always enabled because TCG does implement HTM, it's just a
305 * degenerate implementation.
306 */
307 static const uint8_t pa_features_207[] = { 24, 0,
308 0xf6, 0x3f, 0xc7, 0xc0, 0x00, 0xf0,
309 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
310 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
311 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 };
312
313 static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt)
314 {
315 static const char compat[] = "ibm,power8-xscom\0ibm,xscom";
316 int i;
317
318 pnv_dt_xscom(chip, fdt, 0,
319 cpu_to_be64(PNV_XSCOM_BASE(chip)),
320 cpu_to_be64(PNV_XSCOM_SIZE),
321 compat, sizeof(compat));
322
323 for (i = 0; i < chip->nr_cores; i++) {
324 PnvCore *pnv_core = chip->cores[i];
325 int offset;
326
327 offset = pnv_dt_core(chip, pnv_core, fdt);
328
329 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features",
330 pa_features_207, sizeof(pa_features_207))));
331
332 /* Interrupt Control Presenters (ICP). One per core. */
333 pnv_dt_icp(chip, fdt, pnv_core->hwid, CPU_CORE(pnv_core)->nr_threads);
334 }
335
336 if (chip->ram_size) {
337 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size);
338 }
339 }
340
341 /*
342 * Same as spapr pa_features_300 except pnv always enables CI largepages bit.
343 */
344 static const uint8_t pa_features_300[] = { 66, 0,
345 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: CILRG|fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */
346 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, 5: LE|CFAR|EB|LSQ */
347 0xf6, 0x3f, 0xc7, 0xc0, 0x00, 0xf0, /* 0 - 5 */
348 /* 6: DS207 */
349 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */
350 /* 16: Vector */
351 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */
352 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */
353 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 18 - 23 */
354 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */
355 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */
356 /* 32: LE atomic, 34: EBB + ext EBB */
357 0x00, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */
358 /* 40: Radix MMU */
359 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 36 - 41 */
360 /* 42: PM, 44: PC RA, 46: SC vec'd */
361 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */
362 /* 48: SIMD, 50: QP BFP, 52: String */
363 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */
364 /* 54: DecFP, 56: DecI, 58: SHA */
365 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */
366 /* 60: NM atomic, 62: RNG */
367 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */
368 };
369
370 static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt)
371 {
372 static const char compat[] = "ibm,power9-xscom\0ibm,xscom";
373 int i;
374
375 pnv_dt_xscom(chip, fdt, 0,
376 cpu_to_be64(PNV9_XSCOM_BASE(chip)),
377 cpu_to_be64(PNV9_XSCOM_SIZE),
378 compat, sizeof(compat));
379
380 for (i = 0; i < chip->nr_cores; i++) {
381 PnvCore *pnv_core = chip->cores[i];
382 int offset;
383
384 offset = pnv_dt_core(chip, pnv_core, fdt);
385
386 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features",
387 pa_features_300, sizeof(pa_features_300))));
388 }
389
390 if (chip->ram_size) {
391 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size);
392 }
393
394 pnv_dt_lpc(chip, fdt, 0, PNV9_LPCM_BASE(chip), PNV9_LPCM_SIZE);
395 }
396
397 /*
398 * Same as spapr pa_features_31 except pnv always enables CI largepages bit,
399 * always disables copy/paste.
400 */
401 static const uint8_t pa_features_31[] = { 74, 0,
402 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: CILRG|fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */
403 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, 5: LE|CFAR|EB|LSQ */
404 0xf6, 0x3f, 0xc7, 0xc0, 0x00, 0xf0, /* 0 - 5 */
405 /* 6: DS207 */
406 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */
407 /* 16: Vector */
408 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */
409 /* 18: Vec. Scalar, 20: Vec. XOR */
410 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */
411 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */
412 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */
413 /* 32: LE atomic, 34: EBB + ext EBB */
414 0x00, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */
415 /* 40: Radix MMU */
416 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 36 - 41 */
417 /* 42: PM, 44: PC RA, 46: SC vec'd */
418 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */
419 /* 48: SIMD, 50: QP BFP, 52: String */
420 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */
421 /* 54: DecFP, 56: DecI, 58: SHA */
422 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */
423 /* 60: NM atomic, 62: RNG */
424 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */
425 /* 68: DEXCR[SBHE|IBRTPDUS|SRAPD|NPHIE|PHIE] */
426 0x00, 0x00, 0xce, 0x00, 0x00, 0x00, /* 66 - 71 */
427 /* 72: [P]HASHST/[P]HASHCHK */
428 0x80, 0x00, /* 72 - 73 */
429 };
430
431 static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt)
432 {
433 static const char compat[] = "ibm,power10-xscom\0ibm,xscom";
434 int i;
435
436 pnv_dt_xscom(chip, fdt, 0,
437 cpu_to_be64(PNV10_XSCOM_BASE(chip)),
438 cpu_to_be64(PNV10_XSCOM_SIZE),
439 compat, sizeof(compat));
440
441 for (i = 0; i < chip->nr_cores; i++) {
442 PnvCore *pnv_core = chip->cores[i];
443 int offset;
444
445 offset = pnv_dt_core(chip, pnv_core, fdt);
446
447 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features",
448 pa_features_31, sizeof(pa_features_31))));
449 }
450
451 if (chip->ram_size) {
452 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size);
453 }
454
455 pnv_dt_lpc(chip, fdt, 0, PNV10_LPCM_BASE(chip), PNV10_LPCM_SIZE);
456 }
457
458 static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off)
459 {
460 uint32_t io_base = d->ioport_id;
461 uint32_t io_regs[] = {
462 cpu_to_be32(1),
463 cpu_to_be32(io_base),
464 cpu_to_be32(2)
465 };
466 char *name;
467 int node;
468
469 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base);
470 node = fdt_add_subnode(fdt, lpc_off, name);
471 _FDT(node);
472 g_free(name);
473
474 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs))));
475 _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00")));
476 }
477
478 static void pnv_dt_serial(ISADevice *d, void *fdt, int lpc_off)
479 {
480 const char compatible[] = "ns16550\0pnpPNP,501";
481 uint32_t io_base = d->ioport_id;
482 uint32_t io_regs[] = {
483 cpu_to_be32(1),
484 cpu_to_be32(io_base),
485 cpu_to_be32(8)
486 };
487 uint32_t irq;
488 char *name;
489 int node;
490
491 irq = object_property_get_uint(OBJECT(d), "irq", &error_fatal);
492
493 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base);
494 node = fdt_add_subnode(fdt, lpc_off, name);
495 _FDT(node);
496 g_free(name);
497
498 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs))));
499 _FDT((fdt_setprop(fdt, node, "compatible", compatible,
500 sizeof(compatible))));
501
502 _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200)));
503 _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200)));
504 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq)));
505 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent",
506 fdt_get_phandle(fdt, lpc_off))));
507
508 /* This is needed by Linux */
509 _FDT((fdt_setprop_string(fdt, node, "device_type", "serial")));
510 }
511
512 static void pnv_dt_ipmi_bt(ISADevice *d, void *fdt, int lpc_off)
513 {
514 const char compatible[] = "bt\0ipmi-bt";
515 uint32_t io_base;
516 uint32_t io_regs[] = {
517 cpu_to_be32(1),
518 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */
519 cpu_to_be32(3)
520 };
521 uint32_t irq;
522 char *name;
523 int node;
524
525 io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal);
526 io_regs[1] = cpu_to_be32(io_base);
527
528 irq = object_property_get_int(OBJECT(d), "irq", &error_fatal);
529
530 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base);
531 node = fdt_add_subnode(fdt, lpc_off, name);
532 _FDT(node);
533 g_free(name);
534
535 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs))));
536 _FDT((fdt_setprop(fdt, node, "compatible", compatible,
537 sizeof(compatible))));
538
539 /* Mark it as reserved to avoid Linux trying to claim it */
540 _FDT((fdt_setprop_string(fdt, node, "status", "reserved")));
541 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq)));
542 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent",
543 fdt_get_phandle(fdt, lpc_off))));
544 }
545
546 typedef struct ForeachPopulateArgs {
547 void *fdt;
548 int offset;
549 } ForeachPopulateArgs;
550
551 static int pnv_dt_isa_device(DeviceState *dev, void *opaque)
552 {
553 ForeachPopulateArgs *args = opaque;
554 ISADevice *d = ISA_DEVICE(dev);
555
556 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) {
557 pnv_dt_rtc(d, args->fdt, args->offset);
558 } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) {
559 pnv_dt_serial(d, args->fdt, args->offset);
560 } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) {
561 pnv_dt_ipmi_bt(d, args->fdt, args->offset);
562 } else {
563 error_report("unknown isa device %s@i%x", qdev_fw_name(dev),
564 d->ioport_id);
565 }
566
567 return 0;
568 }
569
570 /*
571 * The default LPC bus of a multichip system is on chip 0. It's
572 * recognized by the firmware (skiboot) using a "primary" property.
573 */
574 static void pnv_dt_isa(PnvMachineState *pnv, void *fdt)
575 {
576 int isa_offset = fdt_path_offset(fdt, pnv->chips[0]->dt_isa_nodename);
577 ForeachPopulateArgs args = {
578 .fdt = fdt,
579 .offset = isa_offset,
580 };
581 uint32_t phandle;
582
583 _FDT((fdt_setprop(fdt, isa_offset, "primary", NULL, 0)));
584
585 phandle = qemu_fdt_alloc_phandle(fdt);
586 assert(phandle > 0);
587 _FDT((fdt_setprop_cell(fdt, isa_offset, "phandle", phandle)));
588
589 /*
590 * ISA devices are not necessarily parented to the ISA bus so we
591 * can not use object_child_foreach()
592 */
593 qbus_walk_children(BUS(pnv->isa_bus), pnv_dt_isa_device, NULL, NULL, NULL,
594 &args);
595 }
596
597 static void pnv_dt_power_mgt(PnvMachineState *pnv, void *fdt)
598 {
599 int off;
600
601 off = fdt_add_subnode(fdt, 0, "ibm,opal");
602 off = fdt_add_subnode(fdt, off, "power-mgt");
603
604 _FDT(fdt_setprop_cell(fdt, off, "ibm,enabled-stop-levels", 0xc0000000));
605 }
606
607 static void *pnv_dt_create(MachineState *machine)
608 {
609 PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(machine);
610 PnvMachineState *pnv = PNV_MACHINE(machine);
611 void *fdt;
612 char *buf;
613 int off;
614 int i;
615
616 fdt = g_malloc0(FDT_MAX_SIZE);
617 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE)));
618
619 /* /qemu node */
620 _FDT((fdt_add_subnode(fdt, 0, "qemu")));
621
622 /* Root node */
623 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2)));
624 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2)));
625 _FDT((fdt_setprop_string(fdt, 0, "model",
626 "IBM PowerNV (emulated by qemu)")));
627 _FDT((fdt_setprop(fdt, 0, "compatible", pmc->compat, pmc->compat_size)));
628
629 buf = qemu_uuid_unparse_strdup(&qemu_uuid);
630 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf)));
631 if (qemu_uuid_set) {
632 _FDT((fdt_setprop_string(fdt, 0, "system-id", buf)));
633 }
634 g_free(buf);
635
636 off = fdt_add_subnode(fdt, 0, "chosen");
637 if (machine->kernel_cmdline) {
638 _FDT((fdt_setprop_string(fdt, off, "bootargs",
639 machine->kernel_cmdline)));
640 }
641
642 if (pnv->initrd_size) {
643 uint32_t start_prop = cpu_to_be32(pnv->initrd_base);
644 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size);
645
646 _FDT((fdt_setprop(fdt, off, "linux,initrd-start",
647 &start_prop, sizeof(start_prop))));
648 _FDT((fdt_setprop(fdt, off, "linux,initrd-end",
649 &end_prop, sizeof(end_prop))));
650 }
651
652 /* Populate device tree for each chip */
653 for (i = 0; i < pnv->num_chips; i++) {
654 PNV_CHIP_GET_CLASS(pnv->chips[i])->dt_populate(pnv->chips[i], fdt);
655 }
656
657 /* Populate ISA devices on chip 0 */
658 pnv_dt_isa(pnv, fdt);
659
660 if (pnv->bmc) {
661 pnv_dt_bmc_sensors(pnv->bmc, fdt);
662 }
663
664 /* Create an extra node for power management on machines that support it */
665 if (pmc->dt_power_mgt) {
666 pmc->dt_power_mgt(pnv, fdt);
667 }
668
669 return fdt;
670 }
671
672 static void pnv_powerdown_notify(Notifier *n, void *opaque)
673 {
674 PnvMachineState *pnv = container_of(n, PnvMachineState, powerdown_notifier);
675
676 if (pnv->bmc) {
677 pnv_bmc_powerdown(pnv->bmc);
678 }
679 }
680
681 static void pnv_reset(MachineState *machine, ShutdownCause reason)
682 {
683 PnvMachineState *pnv = PNV_MACHINE(machine);
684 IPMIBmc *bmc;
685 void *fdt;
686
687 qemu_devices_reset(reason);
688
689 /*
690 * The machine should provide by default an internal BMC simulator.
691 * If not, try to use the BMC device that was provided on the command
692 * line.
693 */
694 bmc = pnv_bmc_find(&error_fatal);
695 if (!pnv->bmc) {
696 if (!bmc) {
697 if (!qtest_enabled()) {
698 warn_report("machine has no BMC device. Use '-device "
699 "ipmi-bmc-sim,id=bmc0 -device isa-ipmi-bt,bmc=bmc0,irq=10' "
700 "to define one");
701 }
702 } else {
703 pnv_bmc_set_pnor(bmc, pnv->pnor);
704 pnv->bmc = bmc;
705 }
706 }
707
708 fdt = pnv_dt_create(machine);
709
710 /* Pack resulting tree */
711 _FDT((fdt_pack(fdt)));
712
713 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt));
714 cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt));
715
716 /*
717 * Set machine->fdt for 'dumpdtb' QMP/HMP command. Free
718 * the existing machine->fdt to avoid leaking it during
719 * a reset.
720 */
721 g_free(machine->fdt);
722 machine->fdt = fdt;
723 }
724
725 static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp)
726 {
727 Pnv8Chip *chip8 = PNV8_CHIP(chip);
728 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_EXTERNAL);
729
730 qdev_connect_gpio_out(DEVICE(&chip8->lpc), 0, irq);
731 return pnv_lpc_isa_create(&chip8->lpc, true, errp);
732 }
733
734 static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp)
735 {
736 Pnv8Chip *chip8 = PNV8_CHIP(chip);
737 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_LPC_I2C);
738
739 qdev_connect_gpio_out(DEVICE(&chip8->lpc), 0, irq);
740 return pnv_lpc_isa_create(&chip8->lpc, false, errp);
741 }
742
743 static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp)
744 {
745 Pnv9Chip *chip9 = PNV9_CHIP(chip);
746 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPCHC);
747
748 qdev_connect_gpio_out(DEVICE(&chip9->lpc), 0, irq);
749 return pnv_lpc_isa_create(&chip9->lpc, false, errp);
750 }
751
752 static ISABus *pnv_chip_power10_isa_create(PnvChip *chip, Error **errp)
753 {
754 Pnv10Chip *chip10 = PNV10_CHIP(chip);
755 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPCHC);
756
757 qdev_connect_gpio_out(DEVICE(&chip10->lpc), 0, irq);
758 return pnv_lpc_isa_create(&chip10->lpc, false, errp);
759 }
760
761 static ISABus *pnv_isa_create(PnvChip *chip, Error **errp)
762 {
763 return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp);
764 }
765
766 static void pnv_chip_power8_pic_print_info(PnvChip *chip, GString *buf)
767 {
768 Pnv8Chip *chip8 = PNV8_CHIP(chip);
769 int i;
770
771 ics_pic_print_info(&chip8->psi.ics, buf);
772
773 for (i = 0; i < chip8->num_phbs; i++) {
774 PnvPHB *phb = chip8->phbs[i];
775 PnvPHB3 *phb3 = PNV_PHB3(phb->backend);
776
777 pnv_phb3_msi_pic_print_info(&phb3->msis, buf);
778 ics_pic_print_info(&phb3->lsis, buf);
779 }
780 }
781
782 static int pnv_chip_power9_pic_print_info_child(Object *child, void *opaque)
783 {
784 GString *buf = opaque;
785 PnvPHB *phb = (PnvPHB *) object_dynamic_cast(child, TYPE_PNV_PHB);
786
787 if (!phb) {
788 return 0;
789 }
790
791 pnv_phb4_pic_print_info(PNV_PHB4(phb->backend), buf);
792
793 return 0;
794 }
795
796 static void pnv_chip_power9_pic_print_info(PnvChip *chip, GString *buf)
797 {
798 Pnv9Chip *chip9 = PNV9_CHIP(chip);
799
800 pnv_xive_pic_print_info(&chip9->xive, buf);
801 pnv_psi_pic_print_info(&chip9->psi, buf);
802 object_child_foreach_recursive(OBJECT(chip),
803 pnv_chip_power9_pic_print_info_child, buf);
804 }
805
806 static uint64_t pnv_chip_power8_xscom_core_base(PnvChip *chip,
807 uint32_t core_id)
808 {
809 return PNV_XSCOM_EX_BASE(core_id);
810 }
811
812 static uint64_t pnv_chip_power9_xscom_core_base(PnvChip *chip,
813 uint32_t core_id)
814 {
815 return PNV9_XSCOM_EC_BASE(core_id);
816 }
817
818 static uint64_t pnv_chip_power10_xscom_core_base(PnvChip *chip,
819 uint32_t core_id)
820 {
821 return PNV10_XSCOM_EC_BASE(core_id);
822 }
823
824 static bool pnv_match_cpu(const char *default_type, const char *cpu_type)
825 {
826 PowerPCCPUClass *ppc_default =
827 POWERPC_CPU_CLASS(object_class_by_name(default_type));
828 PowerPCCPUClass *ppc =
829 POWERPC_CPU_CLASS(object_class_by_name(cpu_type));
830
831 return ppc_default->pvr_match(ppc_default, ppc->pvr, false);
832 }
833
834 static void pnv_ipmi_bt_init(ISABus *bus, IPMIBmc *bmc, uint32_t irq)
835 {
836 ISADevice *dev = isa_new("isa-ipmi-bt");
837
838 object_property_set_link(OBJECT(dev), "bmc", OBJECT(bmc), &error_fatal);
839 object_property_set_int(OBJECT(dev), "irq", irq, &error_fatal);
840 isa_realize_and_unref(dev, bus, &error_fatal);
841 }
842
843 static void pnv_chip_power10_pic_print_info(PnvChip *chip, GString *buf)
844 {
845 Pnv10Chip *chip10 = PNV10_CHIP(chip);
846
847 pnv_xive2_pic_print_info(&chip10->xive, buf);
848 pnv_psi_pic_print_info(&chip10->psi, buf);
849 object_child_foreach_recursive(OBJECT(chip),
850 pnv_chip_power9_pic_print_info_child, buf);
851 }
852
853 /* Always give the first 1GB to chip 0 else we won't boot */
854 static uint64_t pnv_chip_get_ram_size(PnvMachineState *pnv, int chip_id)
855 {
856 MachineState *machine = MACHINE(pnv);
857 uint64_t ram_per_chip;
858
859 assert(machine->ram_size >= 1 * GiB);
860
861 ram_per_chip = machine->ram_size / pnv->num_chips;
862 if (ram_per_chip >= 1 * GiB) {
863 return QEMU_ALIGN_DOWN(ram_per_chip, 1 * MiB);
864 }
865
866 assert(pnv->num_chips > 1);
867
868 ram_per_chip = (machine->ram_size - 1 * GiB) / (pnv->num_chips - 1);
869 return chip_id == 0 ? 1 * GiB : QEMU_ALIGN_DOWN(ram_per_chip, 1 * MiB);
870 }
871
872 static void pnv_init(MachineState *machine)
873 {
874 const char *bios_name = machine->firmware ?: FW_FILE_NAME;
875 PnvMachineState *pnv = PNV_MACHINE(machine);
876 MachineClass *mc = MACHINE_GET_CLASS(machine);
877 PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(machine);
878 char *fw_filename;
879 long fw_size;
880 uint64_t chip_ram_start = 0;
881 int i;
882 char *chip_typename;
883 DriveInfo *pnor = drive_get(IF_MTD, 0, 0);
884 DeviceState *dev;
885
886 if (kvm_enabled()) {
887 error_report("machine %s does not support the KVM accelerator",
888 mc->name);
889 exit(EXIT_FAILURE);
890 }
891
892 /* allocate RAM */
893 if (machine->ram_size < mc->default_ram_size) {
894 char *sz = size_to_str(mc->default_ram_size);
895 error_report("Invalid RAM size, should be bigger than %s", sz);
896 g_free(sz);
897 exit(EXIT_FAILURE);
898 }
899 memory_region_add_subregion(get_system_memory(), 0, machine->ram);
900
901 /*
902 * Create our simple PNOR device
903 */
904 dev = qdev_new(TYPE_PNV_PNOR);
905 if (pnor) {
906 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(pnor));
907 }
908 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
909 pnv->pnor = PNV_PNOR(dev);
910
911 /* load skiboot firmware */
912 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
913 if (!fw_filename) {
914 error_report("Could not find OPAL firmware '%s'", bios_name);
915 exit(1);
916 }
917
918 fw_size = load_image_targphys(fw_filename, pnv->fw_load_addr, FW_MAX_SIZE);
919 if (fw_size < 0) {
920 error_report("Could not load OPAL firmware '%s'", fw_filename);
921 exit(1);
922 }
923 g_free(fw_filename);
924
925 /* load kernel */
926 if (machine->kernel_filename) {
927 long kernel_size;
928
929 kernel_size = load_image_targphys(machine->kernel_filename,
930 KERNEL_LOAD_ADDR, KERNEL_MAX_SIZE);
931 if (kernel_size < 0) {
932 error_report("Could not load kernel '%s'",
933 machine->kernel_filename);
934 exit(1);
935 }
936 }
937
938 /* load initrd */
939 if (machine->initrd_filename) {
940 pnv->initrd_base = INITRD_LOAD_ADDR;
941 pnv->initrd_size = load_image_targphys(machine->initrd_filename,
942 pnv->initrd_base, INITRD_MAX_SIZE);
943 if (pnv->initrd_size < 0) {
944 error_report("Could not load initial ram disk '%s'",
945 machine->initrd_filename);
946 exit(1);
947 }
948 }
949
950 /* MSIs are supported on this platform */
951 msi_nonbroken = true;
952
953 /*
954 * Check compatibility of the specified CPU with the machine
955 * default.
956 */
957 if (!pnv_match_cpu(mc->default_cpu_type, machine->cpu_type)) {
958 error_report("invalid CPU model '%s' for %s machine",
959 machine->cpu_type, mc->name);
960 exit(1);
961 }
962
963 /* Create the processor chips */
964 i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX);
965 chip_typename = g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"),
966 i, machine->cpu_type);
967 if (!object_class_by_name(chip_typename)) {
968 error_report("invalid chip model '%.*s' for %s machine",
969 i, machine->cpu_type, mc->name);
970 exit(1);
971 }
972
973 pnv->num_chips =
974 machine->smp.max_cpus / (machine->smp.cores * machine->smp.threads);
975
976 if (machine->smp.threads > 8) {
977 error_report("Cannot support more than 8 threads/core "
978 "on a powernv machine");
979 exit(1);
980 }
981 if (!is_power_of_2(machine->smp.threads)) {
982 error_report("Cannot support %d threads/core on a powernv"
983 "machine because it must be a power of 2",
984 machine->smp.threads);
985 exit(1);
986 }
987 /*
988 * TODO: should we decide on how many chips we can create based
989 * on #cores and Venice vs. Murano vs. Naples chip type etc...,
990 */
991 if (!is_power_of_2(pnv->num_chips) || pnv->num_chips > 16) {
992 error_report("invalid number of chips: '%d'", pnv->num_chips);
993 error_printf(
994 "Try '-smp sockets=N'. Valid values are : 1, 2, 4, 8 and 16.\n");
995 exit(1);
996 }
997
998 pnv->chips = g_new0(PnvChip *, pnv->num_chips);
999 for (i = 0; i < pnv->num_chips; i++) {
1000 char chip_name[32];
1001 Object *chip = OBJECT(qdev_new(chip_typename));
1002 uint64_t chip_ram_size = pnv_chip_get_ram_size(pnv, i);
1003
1004 pnv->chips[i] = PNV_CHIP(chip);
1005
1006 /* Distribute RAM among the chips */
1007 object_property_set_int(chip, "ram-start", chip_ram_start,
1008 &error_fatal);
1009 object_property_set_int(chip, "ram-size", chip_ram_size,
1010 &error_fatal);
1011 chip_ram_start += chip_ram_size;
1012
1013 snprintf(chip_name, sizeof(chip_name), "chip[%d]", i);
1014 object_property_add_child(OBJECT(pnv), chip_name, chip);
1015 object_property_set_int(chip, "chip-id", i, &error_fatal);
1016 object_property_set_int(chip, "nr-cores", machine->smp.cores,
1017 &error_fatal);
1018 object_property_set_int(chip, "nr-threads", machine->smp.threads,
1019 &error_fatal);
1020 /*
1021 * The POWER8 machine use the XICS interrupt interface.
1022 * Propagate the XICS fabric to the chip and its controllers.
1023 */
1024 if (object_dynamic_cast(OBJECT(pnv), TYPE_XICS_FABRIC)) {
1025 object_property_set_link(chip, "xics", OBJECT(pnv), &error_abort);
1026 }
1027 if (object_dynamic_cast(OBJECT(pnv), TYPE_XIVE_FABRIC)) {
1028 object_property_set_link(chip, "xive-fabric", OBJECT(pnv),
1029 &error_abort);
1030 }
1031 sysbus_realize_and_unref(SYS_BUS_DEVICE(chip), &error_fatal);
1032 }
1033 g_free(chip_typename);
1034
1035 /* Instantiate ISA bus on chip 0 */
1036 pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal);
1037
1038 /* Create serial port */
1039 serial_hds_isa_init(pnv->isa_bus, 0, MAX_ISA_SERIAL_PORTS);
1040
1041 /* Create an RTC ISA device too */
1042 mc146818_rtc_init(pnv->isa_bus, 2000, NULL);
1043
1044 /*
1045 * Create the machine BMC simulator and the IPMI BT device for
1046 * communication with the BMC
1047 */
1048 if (defaults_enabled()) {
1049 pnv->bmc = pnv_bmc_create(pnv->pnor);
1050 pnv_ipmi_bt_init(pnv->isa_bus, pnv->bmc, 10);
1051 }
1052
1053 /*
1054 * The PNOR is mapped on the LPC FW address space by the BMC.
1055 * Since we can not reach the remote BMC machine with LPC memops,
1056 * map it always for now.
1057 */
1058 memory_region_add_subregion(pnv->chips[0]->fw_mr, PNOR_SPI_OFFSET,
1059 &pnv->pnor->mmio);
1060
1061 /*
1062 * OpenPOWER systems use a IPMI SEL Event message to notify the
1063 * host to powerdown
1064 */
1065 pnv->powerdown_notifier.notify = pnv_powerdown_notify;
1066 qemu_register_powerdown_notifier(&pnv->powerdown_notifier);
1067
1068 /*
1069 * Create/Connect any machine-specific I2C devices
1070 */
1071 if (pmc->i2c_init) {
1072 pmc->i2c_init(pnv);
1073 }
1074 }
1075
1076 /*
1077 * 0:21 Reserved - Read as zeros
1078 * 22:24 Chip ID
1079 * 25:28 Core number
1080 * 29:31 Thread ID
1081 */
1082 static uint32_t pnv_chip_pir_p8(PnvChip *chip, uint32_t core_id,
1083 uint32_t thread_id)
1084 {
1085 return (chip->chip_id << 7) | (core_id << 3) | thread_id;
1086 }
1087
1088 static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu,
1089 Error **errp)
1090 {
1091 Pnv8Chip *chip8 = PNV8_CHIP(chip);
1092 Error *local_err = NULL;
1093 Object *obj;
1094 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1095
1096 obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, chip8->xics, &local_err);
1097 if (local_err) {
1098 error_propagate(errp, local_err);
1099 return;
1100 }
1101
1102 pnv_cpu->intc = obj;
1103 }
1104
1105
1106 static void pnv_chip_power8_intc_reset(PnvChip *chip, PowerPCCPU *cpu)
1107 {
1108 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1109
1110 icp_reset(ICP(pnv_cpu->intc));
1111 }
1112
1113 static void pnv_chip_power8_intc_destroy(PnvChip *chip, PowerPCCPU *cpu)
1114 {
1115 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1116
1117 icp_destroy(ICP(pnv_cpu->intc));
1118 pnv_cpu->intc = NULL;
1119 }
1120
1121 static void pnv_chip_power8_intc_print_info(PnvChip *chip, PowerPCCPU *cpu,
1122 GString *buf)
1123 {
1124 icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), buf);
1125 }
1126
1127 /*
1128 * 0:48 Reserved - Read as zeroes
1129 * 49:52 Node ID
1130 * 53:55 Chip ID
1131 * 56 Reserved - Read as zero
1132 * 57:61 Core number
1133 * 62:63 Thread ID
1134 *
1135 * We only care about the lower bits. uint32_t is fine for the moment.
1136 */
1137 static uint32_t pnv_chip_pir_p9(PnvChip *chip, uint32_t core_id,
1138 uint32_t thread_id)
1139 {
1140 if (chip->nr_threads == 8) {
1141 return (chip->chip_id << 8) | ((thread_id & 1) << 2) | (core_id << 3) |
1142 (thread_id >> 1);
1143 } else {
1144 return (chip->chip_id << 8) | (core_id << 2) | thread_id;
1145 }
1146 }
1147
1148 /*
1149 * 0:48 Reserved - Read as zeroes
1150 * 49:52 Node ID
1151 * 53:55 Chip ID
1152 * 56 Reserved - Read as zero
1153 * 57:59 Quad ID
1154 * 60 Core Chiplet Pair ID
1155 * 61:63 Thread/Core Chiplet ID t0-t2
1156 *
1157 * We only care about the lower bits. uint32_t is fine for the moment.
1158 */
1159 static uint32_t pnv_chip_pir_p10(PnvChip *chip, uint32_t core_id,
1160 uint32_t thread_id)
1161 {
1162 if (chip->nr_threads == 8) {
1163 return (chip->chip_id << 8) | ((core_id / 4) << 4) |
1164 ((core_id % 2) << 3) | thread_id;
1165 } else {
1166 return (chip->chip_id << 8) | (core_id << 2) | thread_id;
1167 }
1168 }
1169
1170 static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu,
1171 Error **errp)
1172 {
1173 Pnv9Chip *chip9 = PNV9_CHIP(chip);
1174 Error *local_err = NULL;
1175 Object *obj;
1176 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1177
1178 /*
1179 * The core creates its interrupt presenter but the XIVE interrupt
1180 * controller object is initialized afterwards. Hopefully, it's
1181 * only used at runtime.
1182 */
1183 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip9->xive),
1184 &local_err);
1185 if (local_err) {
1186 error_propagate(errp, local_err);
1187 return;
1188 }
1189
1190 pnv_cpu->intc = obj;
1191 }
1192
1193 static void pnv_chip_power9_intc_reset(PnvChip *chip, PowerPCCPU *cpu)
1194 {
1195 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1196
1197 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc));
1198 }
1199
1200 static void pnv_chip_power9_intc_destroy(PnvChip *chip, PowerPCCPU *cpu)
1201 {
1202 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1203
1204 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc));
1205 pnv_cpu->intc = NULL;
1206 }
1207
1208 static void pnv_chip_power9_intc_print_info(PnvChip *chip, PowerPCCPU *cpu,
1209 GString *buf)
1210 {
1211 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), buf);
1212 }
1213
1214 static void pnv_chip_power10_intc_create(PnvChip *chip, PowerPCCPU *cpu,
1215 Error **errp)
1216 {
1217 Pnv10Chip *chip10 = PNV10_CHIP(chip);
1218 Error *local_err = NULL;
1219 Object *obj;
1220 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1221
1222 /*
1223 * The core creates its interrupt presenter but the XIVE2 interrupt
1224 * controller object is initialized afterwards. Hopefully, it's
1225 * only used at runtime.
1226 */
1227 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip10->xive),
1228 &local_err);
1229 if (local_err) {
1230 error_propagate(errp, local_err);
1231 return;
1232 }
1233
1234 pnv_cpu->intc = obj;
1235 }
1236
1237 static void pnv_chip_power10_intc_reset(PnvChip *chip, PowerPCCPU *cpu)
1238 {
1239 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1240
1241 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc));
1242 }
1243
1244 static void pnv_chip_power10_intc_destroy(PnvChip *chip, PowerPCCPU *cpu)
1245 {
1246 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1247
1248 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc));
1249 pnv_cpu->intc = NULL;
1250 }
1251
1252 static void pnv_chip_power10_intc_print_info(PnvChip *chip, PowerPCCPU *cpu,
1253 GString *buf)
1254 {
1255 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), buf);
1256 }
1257
1258 /*
1259 * Allowed core identifiers on a POWER8 Processor Chip :
1260 *
1261 * <EX0 reserved>
1262 * EX1 - Venice only
1263 * EX2 - Venice only
1264 * EX3 - Venice only
1265 * EX4
1266 * EX5
1267 * EX6
1268 * <EX7,8 reserved> <reserved>
1269 * EX9 - Venice only
1270 * EX10 - Venice only
1271 * EX11 - Venice only
1272 * EX12
1273 * EX13
1274 * EX14
1275 * <EX15 reserved>
1276 */
1277 #define POWER8E_CORE_MASK (0x7070ull)
1278 #define POWER8_CORE_MASK (0x7e7eull)
1279
1280 /*
1281 * POWER9 has 24 cores, ids starting at 0x0
1282 */
1283 #define POWER9_CORE_MASK (0xffffffffffffffull)
1284
1285
1286 #define POWER10_CORE_MASK (0xffffffffffffffull)
1287
1288 static void pnv_chip_power8_instance_init(Object *obj)
1289 {
1290 Pnv8Chip *chip8 = PNV8_CHIP(obj);
1291 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj);
1292 int i;
1293
1294 object_property_add_link(obj, "xics", TYPE_XICS_FABRIC,
1295 (Object **)&chip8->xics,
1296 object_property_allow_set_link,
1297 OBJ_PROP_LINK_STRONG);
1298
1299 object_initialize_child(obj, "psi", &chip8->psi, TYPE_PNV8_PSI);
1300
1301 object_initialize_child(obj, "lpc", &chip8->lpc, TYPE_PNV8_LPC);
1302
1303 object_initialize_child(obj, "occ", &chip8->occ, TYPE_PNV8_OCC);
1304
1305 object_initialize_child(obj, "homer", &chip8->homer, TYPE_PNV8_HOMER);
1306
1307 if (defaults_enabled()) {
1308 chip8->num_phbs = pcc->num_phbs;
1309
1310 for (i = 0; i < chip8->num_phbs; i++) {
1311 Object *phb = object_new(TYPE_PNV_PHB);
1312
1313 /*
1314 * We need the chip to parent the PHB to allow the DT
1315 * to build correctly (via pnv_xscom_dt()).
1316 *
1317 * TODO: the PHB should be parented by a PEC device that, at
1318 * this moment, is not modelled powernv8/phb3.
1319 */
1320 object_property_add_child(obj, "phb[*]", phb);
1321 chip8->phbs[i] = PNV_PHB(phb);
1322 }
1323 }
1324
1325 }
1326
1327 static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp)
1328 {
1329 PnvChip *chip = PNV_CHIP(chip8);
1330 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
1331 int i, j;
1332 char *name;
1333
1334 name = g_strdup_printf("icp-%x", chip->chip_id);
1335 memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE);
1336 g_free(name);
1337 memory_region_add_subregion(get_system_memory(), PNV_ICP_BASE(chip),
1338 &chip8->icp_mmio);
1339
1340 /* Map the ICP registers for each thread */
1341 for (i = 0; i < chip->nr_cores; i++) {
1342 PnvCore *pnv_core = chip->cores[i];
1343 int core_hwid = CPU_CORE(pnv_core)->core_id;
1344
1345 for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) {
1346 uint32_t pir = pcc->chip_pir(chip, core_hwid, j);
1347 PnvICPState *icp = PNV_ICP(xics_icp_get(chip8->xics, pir));
1348
1349 memory_region_add_subregion(&chip8->icp_mmio, pir << 12,
1350 &icp->mmio);
1351 }
1352 }
1353 }
1354
1355 static void pnv_chip_power8_realize(DeviceState *dev, Error **errp)
1356 {
1357 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev);
1358 PnvChip *chip = PNV_CHIP(dev);
1359 Pnv8Chip *chip8 = PNV8_CHIP(dev);
1360 Pnv8Psi *psi8 = &chip8->psi;
1361 Error *local_err = NULL;
1362 int i;
1363
1364 assert(chip8->xics);
1365
1366 /* XSCOM bridge is first */
1367 pnv_xscom_init(chip, PNV_XSCOM_SIZE, PNV_XSCOM_BASE(chip));
1368
1369 pcc->parent_realize(dev, &local_err);
1370 if (local_err) {
1371 error_propagate(errp, local_err);
1372 return;
1373 }
1374
1375 /* Processor Service Interface (PSI) Host Bridge */
1376 object_property_set_int(OBJECT(psi8), "bar", PNV_PSIHB_BASE(chip),
1377 &error_fatal);
1378 object_property_set_link(OBJECT(psi8), ICS_PROP_XICS,
1379 OBJECT(chip8->xics), &error_abort);
1380 if (!qdev_realize(DEVICE(psi8), NULL, errp)) {
1381 return;
1382 }
1383 pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE,
1384 &PNV_PSI(psi8)->xscom_regs);
1385
1386 /* Create LPC controller */
1387 qdev_realize(DEVICE(&chip8->lpc), NULL, &error_fatal);
1388 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs);
1389
1390 chip->fw_mr = &chip8->lpc.isa_fw;
1391 chip->dt_isa_nodename = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x",
1392 (uint64_t) PNV_XSCOM_BASE(chip),
1393 PNV_XSCOM_LPC_BASE);
1394
1395 /*
1396 * Interrupt Management Area. This is the memory region holding
1397 * all the Interrupt Control Presenter (ICP) registers
1398 */
1399 pnv_chip_icp_realize(chip8, &local_err);
1400 if (local_err) {
1401 error_propagate(errp, local_err);
1402 return;
1403 }
1404
1405 /* Create the simplified OCC model */
1406 if (!qdev_realize(DEVICE(&chip8->occ), NULL, errp)) {
1407 return;
1408 }
1409 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs);
1410 qdev_connect_gpio_out(DEVICE(&chip8->occ), 0,
1411 qdev_get_gpio_in(DEVICE(psi8), PSIHB_IRQ_OCC));
1412
1413 /* OCC SRAM model */
1414 memory_region_add_subregion(get_system_memory(), PNV_OCC_SENSOR_BASE(chip),
1415 &chip8->occ.sram_regs);
1416
1417 /* HOMER */
1418 object_property_set_link(OBJECT(&chip8->homer), "chip", OBJECT(chip),
1419 &error_abort);
1420 if (!qdev_realize(DEVICE(&chip8->homer), NULL, errp)) {
1421 return;
1422 }
1423 /* Homer Xscom region */
1424 pnv_xscom_add_subregion(chip, PNV_XSCOM_PBA_BASE, &chip8->homer.pba_regs);
1425
1426 /* Homer mmio region */
1427 memory_region_add_subregion(get_system_memory(), PNV_HOMER_BASE(chip),
1428 &chip8->homer.regs);
1429
1430 /* PHB controllers */
1431 for (i = 0; i < chip8->num_phbs; i++) {
1432 PnvPHB *phb = chip8->phbs[i];
1433
1434 object_property_set_int(OBJECT(phb), "index", i, &error_fatal);
1435 object_property_set_int(OBJECT(phb), "chip-id", chip->chip_id,
1436 &error_fatal);
1437 object_property_set_link(OBJECT(phb), "chip", OBJECT(chip),
1438 &error_fatal);
1439 if (!sysbus_realize(SYS_BUS_DEVICE(phb), errp)) {
1440 return;
1441 }
1442 }
1443 }
1444
1445 static uint32_t pnv_chip_power8_xscom_pcba(PnvChip *chip, uint64_t addr)
1446 {
1447 addr &= (PNV_XSCOM_SIZE - 1);
1448 return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf);
1449 }
1450
1451 static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data)
1452 {
1453 DeviceClass *dc = DEVICE_CLASS(klass);
1454 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1455
1456 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */
1457 k->cores_mask = POWER8E_CORE_MASK;
1458 k->num_phbs = 3;
1459 k->chip_pir = pnv_chip_pir_p8;
1460 k->intc_create = pnv_chip_power8_intc_create;
1461 k->intc_reset = pnv_chip_power8_intc_reset;
1462 k->intc_destroy = pnv_chip_power8_intc_destroy;
1463 k->intc_print_info = pnv_chip_power8_intc_print_info;
1464 k->isa_create = pnv_chip_power8_isa_create;
1465 k->dt_populate = pnv_chip_power8_dt_populate;
1466 k->pic_print_info = pnv_chip_power8_pic_print_info;
1467 k->xscom_core_base = pnv_chip_power8_xscom_core_base;
1468 k->xscom_pcba = pnv_chip_power8_xscom_pcba;
1469 dc->desc = "PowerNV Chip POWER8E";
1470
1471 device_class_set_parent_realize(dc, pnv_chip_power8_realize,
1472 &k->parent_realize);
1473 }
1474
1475 static void pnv_chip_power8_class_init(ObjectClass *klass, void *data)
1476 {
1477 DeviceClass *dc = DEVICE_CLASS(klass);
1478 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1479
1480 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */
1481 k->cores_mask = POWER8_CORE_MASK;
1482 k->num_phbs = 3;
1483 k->chip_pir = pnv_chip_pir_p8;
1484 k->intc_create = pnv_chip_power8_intc_create;
1485 k->intc_reset = pnv_chip_power8_intc_reset;
1486 k->intc_destroy = pnv_chip_power8_intc_destroy;
1487 k->intc_print_info = pnv_chip_power8_intc_print_info;
1488 k->isa_create = pnv_chip_power8_isa_create;
1489 k->dt_populate = pnv_chip_power8_dt_populate;
1490 k->pic_print_info = pnv_chip_power8_pic_print_info;
1491 k->xscom_core_base = pnv_chip_power8_xscom_core_base;
1492 k->xscom_pcba = pnv_chip_power8_xscom_pcba;
1493 dc->desc = "PowerNV Chip POWER8";
1494
1495 device_class_set_parent_realize(dc, pnv_chip_power8_realize,
1496 &k->parent_realize);
1497 }
1498
1499 static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data)
1500 {
1501 DeviceClass *dc = DEVICE_CLASS(klass);
1502 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1503
1504 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */
1505 k->cores_mask = POWER8_CORE_MASK;
1506 k->num_phbs = 4;
1507 k->chip_pir = pnv_chip_pir_p8;
1508 k->intc_create = pnv_chip_power8_intc_create;
1509 k->intc_reset = pnv_chip_power8_intc_reset;
1510 k->intc_destroy = pnv_chip_power8_intc_destroy;
1511 k->intc_print_info = pnv_chip_power8_intc_print_info;
1512 k->isa_create = pnv_chip_power8nvl_isa_create;
1513 k->dt_populate = pnv_chip_power8_dt_populate;
1514 k->pic_print_info = pnv_chip_power8_pic_print_info;
1515 k->xscom_core_base = pnv_chip_power8_xscom_core_base;
1516 k->xscom_pcba = pnv_chip_power8_xscom_pcba;
1517 dc->desc = "PowerNV Chip POWER8NVL";
1518
1519 device_class_set_parent_realize(dc, pnv_chip_power8_realize,
1520 &k->parent_realize);
1521 }
1522
1523 static void pnv_chip_power9_instance_init(Object *obj)
1524 {
1525 PnvChip *chip = PNV_CHIP(obj);
1526 Pnv9Chip *chip9 = PNV9_CHIP(obj);
1527 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj);
1528 int i;
1529
1530 object_initialize_child(obj, "xive", &chip9->xive, TYPE_PNV_XIVE);
1531 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip9->xive),
1532 "xive-fabric");
1533
1534 object_initialize_child(obj, "psi", &chip9->psi, TYPE_PNV9_PSI);
1535
1536 object_initialize_child(obj, "lpc", &chip9->lpc, TYPE_PNV9_LPC);
1537
1538 object_initialize_child(obj, "chiptod", &chip9->chiptod, TYPE_PNV9_CHIPTOD);
1539
1540 object_initialize_child(obj, "occ", &chip9->occ, TYPE_PNV9_OCC);
1541
1542 object_initialize_child(obj, "sbe", &chip9->sbe, TYPE_PNV9_SBE);
1543
1544 object_initialize_child(obj, "homer", &chip9->homer, TYPE_PNV9_HOMER);
1545
1546 /* Number of PECs is the chip default */
1547 chip->num_pecs = pcc->num_pecs;
1548
1549 for (i = 0; i < chip->num_pecs; i++) {
1550 object_initialize_child(obj, "pec[*]", &chip9->pecs[i],
1551 TYPE_PNV_PHB4_PEC);
1552 }
1553
1554 for (i = 0; i < pcc->i2c_num_engines; i++) {
1555 object_initialize_child(obj, "i2c[*]", &chip9->i2c[i], TYPE_PNV_I2C);
1556 }
1557 }
1558
1559 static void pnv_chip_quad_realize_one(PnvChip *chip, PnvQuad *eq,
1560 PnvCore *pnv_core,
1561 const char *type)
1562 {
1563 char eq_name[32];
1564 int core_id = CPU_CORE(pnv_core)->core_id;
1565
1566 snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id);
1567 object_initialize_child_with_props(OBJECT(chip), eq_name, eq,
1568 sizeof(*eq), type,
1569 &error_fatal, NULL);
1570
1571 object_property_set_int(OBJECT(eq), "quad-id", core_id, &error_fatal);
1572 qdev_realize(DEVICE(eq), NULL, &error_fatal);
1573 }
1574
1575 static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp)
1576 {
1577 PnvChip *chip = PNV_CHIP(chip9);
1578 int i;
1579
1580 chip9->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4);
1581 chip9->quads = g_new0(PnvQuad, chip9->nr_quads);
1582
1583 for (i = 0; i < chip9->nr_quads; i++) {
1584 PnvQuad *eq = &chip9->quads[i];
1585
1586 pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4],
1587 PNV_QUAD_TYPE_NAME("power9"));
1588
1589 pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->quad_id),
1590 &eq->xscom_regs);
1591 }
1592 }
1593
1594 static void pnv_chip_power9_pec_realize(PnvChip *chip, Error **errp)
1595 {
1596 Pnv9Chip *chip9 = PNV9_CHIP(chip);
1597 int i;
1598
1599 for (i = 0; i < chip->num_pecs; i++) {
1600 PnvPhb4PecState *pec = &chip9->pecs[i];
1601 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec);
1602 uint32_t pec_nest_base;
1603 uint32_t pec_pci_base;
1604
1605 object_property_set_int(OBJECT(pec), "index", i, &error_fatal);
1606 object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id,
1607 &error_fatal);
1608 object_property_set_link(OBJECT(pec), "chip", OBJECT(chip),
1609 &error_fatal);
1610 if (!qdev_realize(DEVICE(pec), NULL, errp)) {
1611 return;
1612 }
1613
1614 pec_nest_base = pecc->xscom_nest_base(pec);
1615 pec_pci_base = pecc->xscom_pci_base(pec);
1616
1617 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr);
1618 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr);
1619 }
1620 }
1621
1622 static void pnv_chip_power9_realize(DeviceState *dev, Error **errp)
1623 {
1624 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev);
1625 Pnv9Chip *chip9 = PNV9_CHIP(dev);
1626 PnvChip *chip = PNV_CHIP(dev);
1627 Pnv9Psi *psi9 = &chip9->psi;
1628 Error *local_err = NULL;
1629 int i;
1630
1631 /* XSCOM bridge is first */
1632 pnv_xscom_init(chip, PNV9_XSCOM_SIZE, PNV9_XSCOM_BASE(chip));
1633
1634 pcc->parent_realize(dev, &local_err);
1635 if (local_err) {
1636 error_propagate(errp, local_err);
1637 return;
1638 }
1639
1640 pnv_chip_quad_realize(chip9, &local_err);
1641 if (local_err) {
1642 error_propagate(errp, local_err);
1643 return;
1644 }
1645
1646 /* XIVE interrupt controller (POWER9) */
1647 object_property_set_int(OBJECT(&chip9->xive), "ic-bar",
1648 PNV9_XIVE_IC_BASE(chip), &error_fatal);
1649 object_property_set_int(OBJECT(&chip9->xive), "vc-bar",
1650 PNV9_XIVE_VC_BASE(chip), &error_fatal);
1651 object_property_set_int(OBJECT(&chip9->xive), "pc-bar",
1652 PNV9_XIVE_PC_BASE(chip), &error_fatal);
1653 object_property_set_int(OBJECT(&chip9->xive), "tm-bar",
1654 PNV9_XIVE_TM_BASE(chip), &error_fatal);
1655 object_property_set_link(OBJECT(&chip9->xive), "chip", OBJECT(chip),
1656 &error_abort);
1657 if (!sysbus_realize(SYS_BUS_DEVICE(&chip9->xive), errp)) {
1658 return;
1659 }
1660 pnv_xscom_add_subregion(chip, PNV9_XSCOM_XIVE_BASE,
1661 &chip9->xive.xscom_regs);
1662
1663 /* Processor Service Interface (PSI) Host Bridge */
1664 object_property_set_int(OBJECT(psi9), "bar", PNV9_PSIHB_BASE(chip),
1665 &error_fatal);
1666 /* This is the only device with 4k ESB pages */
1667 object_property_set_int(OBJECT(psi9), "shift", XIVE_ESB_4K,
1668 &error_fatal);
1669 if (!qdev_realize(DEVICE(psi9), NULL, errp)) {
1670 return;
1671 }
1672 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PSIHB_BASE,
1673 &PNV_PSI(psi9)->xscom_regs);
1674
1675 /* LPC */
1676 if (!qdev_realize(DEVICE(&chip9->lpc), NULL, errp)) {
1677 return;
1678 }
1679 memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip),
1680 &chip9->lpc.xscom_regs);
1681
1682 chip->fw_mr = &chip9->lpc.isa_fw;
1683 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0",
1684 (uint64_t) PNV9_LPCM_BASE(chip));
1685
1686 /* ChipTOD */
1687 object_property_set_bool(OBJECT(&chip9->chiptod), "primary",
1688 chip->chip_id == 0, &error_abort);
1689 object_property_set_bool(OBJECT(&chip9->chiptod), "secondary",
1690 chip->chip_id == 1, &error_abort);
1691 object_property_set_link(OBJECT(&chip9->chiptod), "chip", OBJECT(chip),
1692 &error_abort);
1693 if (!qdev_realize(DEVICE(&chip9->chiptod), NULL, errp)) {
1694 return;
1695 }
1696 pnv_xscom_add_subregion(chip, PNV9_XSCOM_CHIPTOD_BASE,
1697 &chip9->chiptod.xscom_regs);
1698
1699 /* Create the simplified OCC model */
1700 if (!qdev_realize(DEVICE(&chip9->occ), NULL, errp)) {
1701 return;
1702 }
1703 pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs);
1704 qdev_connect_gpio_out(DEVICE(&chip9->occ), 0, qdev_get_gpio_in(
1705 DEVICE(psi9), PSIHB9_IRQ_OCC));
1706
1707 /* OCC SRAM model */
1708 memory_region_add_subregion(get_system_memory(), PNV9_OCC_SENSOR_BASE(chip),
1709 &chip9->occ.sram_regs);
1710
1711 /* SBE */
1712 if (!qdev_realize(DEVICE(&chip9->sbe), NULL, errp)) {
1713 return;
1714 }
1715 pnv_xscom_add_subregion(chip, PNV9_XSCOM_SBE_CTRL_BASE,
1716 &chip9->sbe.xscom_ctrl_regs);
1717 pnv_xscom_add_subregion(chip, PNV9_XSCOM_SBE_MBOX_BASE,
1718 &chip9->sbe.xscom_mbox_regs);
1719 qdev_connect_gpio_out(DEVICE(&chip9->sbe), 0, qdev_get_gpio_in(
1720 DEVICE(psi9), PSIHB9_IRQ_PSU));
1721
1722 /* HOMER */
1723 object_property_set_link(OBJECT(&chip9->homer), "chip", OBJECT(chip),
1724 &error_abort);
1725 if (!qdev_realize(DEVICE(&chip9->homer), NULL, errp)) {
1726 return;
1727 }
1728 /* Homer Xscom region */
1729 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PBA_BASE, &chip9->homer.pba_regs);
1730
1731 /* Homer mmio region */
1732 memory_region_add_subregion(get_system_memory(), PNV9_HOMER_BASE(chip),
1733 &chip9->homer.regs);
1734
1735 /* PEC PHBs */
1736 pnv_chip_power9_pec_realize(chip, &local_err);
1737 if (local_err) {
1738 error_propagate(errp, local_err);
1739 return;
1740 }
1741
1742 /*
1743 * I2C
1744 */
1745 for (i = 0; i < pcc->i2c_num_engines; i++) {
1746 Object *obj = OBJECT(&chip9->i2c[i]);
1747
1748 object_property_set_int(obj, "engine", i + 1, &error_fatal);
1749 object_property_set_int(obj, "num-busses",
1750 pcc->i2c_ports_per_engine[i],
1751 &error_fatal);
1752 object_property_set_link(obj, "chip", OBJECT(chip), &error_abort);
1753 if (!qdev_realize(DEVICE(obj), NULL, errp)) {
1754 return;
1755 }
1756 pnv_xscom_add_subregion(chip, PNV9_XSCOM_I2CM_BASE +
1757 (chip9->i2c[i].engine - 1) *
1758 PNV9_XSCOM_I2CM_SIZE,
1759 &chip9->i2c[i].xscom_regs);
1760 qdev_connect_gpio_out(DEVICE(&chip9->i2c[i]), 0,
1761 qdev_get_gpio_in(DEVICE(psi9),
1762 PSIHB9_IRQ_SBE_I2C));
1763 }
1764 }
1765
1766 static uint32_t pnv_chip_power9_xscom_pcba(PnvChip *chip, uint64_t addr)
1767 {
1768 addr &= (PNV9_XSCOM_SIZE - 1);
1769 return addr >> 3;
1770 }
1771
1772 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data)
1773 {
1774 DeviceClass *dc = DEVICE_CLASS(klass);
1775 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1776 static const int i2c_ports_per_engine[PNV9_CHIP_MAX_I2C] = {2, 13, 2, 2};
1777
1778 k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */
1779 k->cores_mask = POWER9_CORE_MASK;
1780 k->chip_pir = pnv_chip_pir_p9;
1781 k->intc_create = pnv_chip_power9_intc_create;
1782 k->intc_reset = pnv_chip_power9_intc_reset;
1783 k->intc_destroy = pnv_chip_power9_intc_destroy;
1784 k->intc_print_info = pnv_chip_power9_intc_print_info;
1785 k->isa_create = pnv_chip_power9_isa_create;
1786 k->dt_populate = pnv_chip_power9_dt_populate;
1787 k->pic_print_info = pnv_chip_power9_pic_print_info;
1788 k->xscom_core_base = pnv_chip_power9_xscom_core_base;
1789 k->xscom_pcba = pnv_chip_power9_xscom_pcba;
1790 dc->desc = "PowerNV Chip POWER9";
1791 k->num_pecs = PNV9_CHIP_MAX_PEC;
1792 k->i2c_num_engines = PNV9_CHIP_MAX_I2C;
1793 k->i2c_ports_per_engine = i2c_ports_per_engine;
1794
1795 device_class_set_parent_realize(dc, pnv_chip_power9_realize,
1796 &k->parent_realize);
1797 }
1798
1799 static void pnv_chip_power10_instance_init(Object *obj)
1800 {
1801 PnvChip *chip = PNV_CHIP(obj);
1802 Pnv10Chip *chip10 = PNV10_CHIP(obj);
1803 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj);
1804 int i;
1805
1806 object_initialize_child(obj, "xive", &chip10->xive, TYPE_PNV_XIVE2);
1807 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip10->xive),
1808 "xive-fabric");
1809 object_initialize_child(obj, "psi", &chip10->psi, TYPE_PNV10_PSI);
1810 object_initialize_child(obj, "lpc", &chip10->lpc, TYPE_PNV10_LPC);
1811 object_initialize_child(obj, "chiptod", &chip10->chiptod,
1812 TYPE_PNV10_CHIPTOD);
1813 object_initialize_child(obj, "occ", &chip10->occ, TYPE_PNV10_OCC);
1814 object_initialize_child(obj, "sbe", &chip10->sbe, TYPE_PNV10_SBE);
1815 object_initialize_child(obj, "homer", &chip10->homer, TYPE_PNV10_HOMER);
1816 object_initialize_child(obj, "n1-chiplet", &chip10->n1_chiplet,
1817 TYPE_PNV_N1_CHIPLET);
1818
1819 chip->num_pecs = pcc->num_pecs;
1820
1821 for (i = 0; i < chip->num_pecs; i++) {
1822 object_initialize_child(obj, "pec[*]", &chip10->pecs[i],
1823 TYPE_PNV_PHB5_PEC);
1824 }
1825
1826 for (i = 0; i < pcc->i2c_num_engines; i++) {
1827 object_initialize_child(obj, "i2c[*]", &chip10->i2c[i], TYPE_PNV_I2C);
1828 }
1829 }
1830
1831 static void pnv_chip_power10_quad_realize(Pnv10Chip *chip10, Error **errp)
1832 {
1833 PnvChip *chip = PNV_CHIP(chip10);
1834 int i;
1835
1836 chip10->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4);
1837 chip10->quads = g_new0(PnvQuad, chip10->nr_quads);
1838
1839 for (i = 0; i < chip10->nr_quads; i++) {
1840 PnvQuad *eq = &chip10->quads[i];
1841
1842 pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4],
1843 PNV_QUAD_TYPE_NAME("power10"));
1844
1845 pnv_xscom_add_subregion(chip, PNV10_XSCOM_EQ_BASE(eq->quad_id),
1846 &eq->xscom_regs);
1847
1848 pnv_xscom_add_subregion(chip, PNV10_XSCOM_QME_BASE(eq->quad_id),
1849 &eq->xscom_qme_regs);
1850 }
1851 }
1852
1853 static void pnv_chip_power10_phb_realize(PnvChip *chip, Error **errp)
1854 {
1855 Pnv10Chip *chip10 = PNV10_CHIP(chip);
1856 int i;
1857
1858 for (i = 0; i < chip->num_pecs; i++) {
1859 PnvPhb4PecState *pec = &chip10->pecs[i];
1860 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec);
1861 uint32_t pec_nest_base;
1862 uint32_t pec_pci_base;
1863
1864 object_property_set_int(OBJECT(pec), "index", i, &error_fatal);
1865 object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id,
1866 &error_fatal);
1867 object_property_set_link(OBJECT(pec), "chip", OBJECT(chip),
1868 &error_fatal);
1869 if (!qdev_realize(DEVICE(pec), NULL, errp)) {
1870 return;
1871 }
1872
1873 pec_nest_base = pecc->xscom_nest_base(pec);
1874 pec_pci_base = pecc->xscom_pci_base(pec);
1875
1876 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr);
1877 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr);
1878 }
1879 }
1880
1881 static void pnv_chip_power10_realize(DeviceState *dev, Error **errp)
1882 {
1883 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev);
1884 PnvChip *chip = PNV_CHIP(dev);
1885 Pnv10Chip *chip10 = PNV10_CHIP(dev);
1886 Error *local_err = NULL;
1887 int i;
1888
1889 /* XSCOM bridge is first */
1890 pnv_xscom_init(chip, PNV10_XSCOM_SIZE, PNV10_XSCOM_BASE(chip));
1891
1892 pcc->parent_realize(dev, &local_err);
1893 if (local_err) {
1894 error_propagate(errp, local_err);
1895 return;
1896 }
1897
1898 pnv_chip_power10_quad_realize(chip10, &local_err);
1899 if (local_err) {
1900 error_propagate(errp, local_err);
1901 return;
1902 }
1903
1904 /* XIVE2 interrupt controller (POWER10) */
1905 object_property_set_int(OBJECT(&chip10->xive), "ic-bar",
1906 PNV10_XIVE2_IC_BASE(chip), &error_fatal);
1907 object_property_set_int(OBJECT(&chip10->xive), "esb-bar",
1908 PNV10_XIVE2_ESB_BASE(chip), &error_fatal);
1909 object_property_set_int(OBJECT(&chip10->xive), "end-bar",
1910 PNV10_XIVE2_END_BASE(chip), &error_fatal);
1911 object_property_set_int(OBJECT(&chip10->xive), "nvpg-bar",
1912 PNV10_XIVE2_NVPG_BASE(chip), &error_fatal);
1913 object_property_set_int(OBJECT(&chip10->xive), "nvc-bar",
1914 PNV10_XIVE2_NVC_BASE(chip), &error_fatal);
1915 object_property_set_int(OBJECT(&chip10->xive), "tm-bar",
1916 PNV10_XIVE2_TM_BASE(chip), &error_fatal);
1917 object_property_set_link(OBJECT(&chip10->xive), "chip", OBJECT(chip),
1918 &error_abort);
1919 if (!sysbus_realize(SYS_BUS_DEVICE(&chip10->xive), errp)) {
1920 return;
1921 }
1922 pnv_xscom_add_subregion(chip, PNV10_XSCOM_XIVE2_BASE,
1923 &chip10->xive.xscom_regs);
1924
1925 /* Processor Service Interface (PSI) Host Bridge */
1926 object_property_set_int(OBJECT(&chip10->psi), "bar",
1927 PNV10_PSIHB_BASE(chip), &error_fatal);
1928 /* PSI can now be configured to use 64k ESB pages on POWER10 */
1929 object_property_set_int(OBJECT(&chip10->psi), "shift", XIVE_ESB_64K,
1930 &error_fatal);
1931 if (!qdev_realize(DEVICE(&chip10->psi), NULL, errp)) {
1932 return;
1933 }
1934 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PSIHB_BASE,
1935 &PNV_PSI(&chip10->psi)->xscom_regs);
1936
1937 /* LPC */
1938 if (!qdev_realize(DEVICE(&chip10->lpc), NULL, errp)) {
1939 return;
1940 }
1941 memory_region_add_subregion(get_system_memory(), PNV10_LPCM_BASE(chip),
1942 &chip10->lpc.xscom_regs);
1943
1944 chip->fw_mr = &chip10->lpc.isa_fw;
1945 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0",
1946 (uint64_t) PNV10_LPCM_BASE(chip));
1947
1948 /* ChipTOD */
1949 object_property_set_bool(OBJECT(&chip10->chiptod), "primary",
1950 chip->chip_id == 0, &error_abort);
1951 object_property_set_bool(OBJECT(&chip10->chiptod), "secondary",
1952 chip->chip_id == 1, &error_abort);
1953 object_property_set_link(OBJECT(&chip10->chiptod), "chip", OBJECT(chip),
1954 &error_abort);
1955 if (!qdev_realize(DEVICE(&chip10->chiptod), NULL, errp)) {
1956 return;
1957 }
1958 pnv_xscom_add_subregion(chip, PNV10_XSCOM_CHIPTOD_BASE,
1959 &chip10->chiptod.xscom_regs);
1960
1961 /* Create the simplified OCC model */
1962 if (!qdev_realize(DEVICE(&chip10->occ), NULL, errp)) {
1963 return;
1964 }
1965 pnv_xscom_add_subregion(chip, PNV10_XSCOM_OCC_BASE,
1966 &chip10->occ.xscom_regs);
1967 qdev_connect_gpio_out(DEVICE(&chip10->occ), 0, qdev_get_gpio_in(
1968 DEVICE(&chip10->psi), PSIHB9_IRQ_OCC));
1969
1970 /* OCC SRAM model */
1971 memory_region_add_subregion(get_system_memory(),
1972 PNV10_OCC_SENSOR_BASE(chip),
1973 &chip10->occ.sram_regs);
1974
1975 /* SBE */
1976 if (!qdev_realize(DEVICE(&chip10->sbe), NULL, errp)) {
1977 return;
1978 }
1979 pnv_xscom_add_subregion(chip, PNV10_XSCOM_SBE_CTRL_BASE,
1980 &chip10->sbe.xscom_ctrl_regs);
1981 pnv_xscom_add_subregion(chip, PNV10_XSCOM_SBE_MBOX_BASE,
1982 &chip10->sbe.xscom_mbox_regs);
1983 qdev_connect_gpio_out(DEVICE(&chip10->sbe), 0, qdev_get_gpio_in(
1984 DEVICE(&chip10->psi), PSIHB9_IRQ_PSU));
1985
1986 /* HOMER */
1987 object_property_set_link(OBJECT(&chip10->homer), "chip", OBJECT(chip),
1988 &error_abort);
1989 if (!qdev_realize(DEVICE(&chip10->homer), NULL, errp)) {
1990 return;
1991 }
1992 /* Homer Xscom region */
1993 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PBA_BASE,
1994 &chip10->homer.pba_regs);
1995
1996 /* Homer mmio region */
1997 memory_region_add_subregion(get_system_memory(), PNV10_HOMER_BASE(chip),
1998 &chip10->homer.regs);
1999
2000 /* N1 chiplet */
2001 if (!qdev_realize(DEVICE(&chip10->n1_chiplet), NULL, errp)) {
2002 return;
2003 }
2004 pnv_xscom_add_subregion(chip, PNV10_XSCOM_N1_CHIPLET_CTRL_REGS_BASE,
2005 &chip10->n1_chiplet.nest_pervasive.xscom_ctrl_regs_mr);
2006
2007 pnv_xscom_add_subregion(chip, PNV10_XSCOM_N1_PB_SCOM_EQ_BASE,
2008 &chip10->n1_chiplet.xscom_pb_eq_mr);
2009
2010 pnv_xscom_add_subregion(chip, PNV10_XSCOM_N1_PB_SCOM_ES_BASE,
2011 &chip10->n1_chiplet.xscom_pb_es_mr);
2012
2013 /* PHBs */
2014 pnv_chip_power10_phb_realize(chip, &local_err);
2015 if (local_err) {
2016 error_propagate(errp, local_err);
2017 return;
2018 }
2019
2020
2021 /*
2022 * I2C
2023 */
2024 for (i = 0; i < pcc->i2c_num_engines; i++) {
2025 Object *obj = OBJECT(&chip10->i2c[i]);
2026
2027 object_property_set_int(obj, "engine", i + 1, &error_fatal);
2028 object_property_set_int(obj, "num-busses",
2029 pcc->i2c_ports_per_engine[i],
2030 &error_fatal);
2031 object_property_set_link(obj, "chip", OBJECT(chip), &error_abort);
2032 if (!qdev_realize(DEVICE(obj), NULL, errp)) {
2033 return;
2034 }
2035 pnv_xscom_add_subregion(chip, PNV10_XSCOM_I2CM_BASE +
2036 (chip10->i2c[i].engine - 1) *
2037 PNV10_XSCOM_I2CM_SIZE,
2038 &chip10->i2c[i].xscom_regs);
2039 qdev_connect_gpio_out(DEVICE(&chip10->i2c[i]), 0,
2040 qdev_get_gpio_in(DEVICE(&chip10->psi),
2041 PSIHB9_IRQ_SBE_I2C));
2042 }
2043
2044 }
2045
2046 static void pnv_rainier_i2c_init(PnvMachineState *pnv)
2047 {
2048 int i;
2049 for (i = 0; i < pnv->num_chips; i++) {
2050 Pnv10Chip *chip10 = PNV10_CHIP(pnv->chips[i]);
2051
2052 /*
2053 * Add a PCA9552 I2C device for PCIe hotplug control
2054 * to engine 2, bus 1, address 0x63
2055 */
2056 I2CSlave *dev = i2c_slave_create_simple(chip10->i2c[2].busses[1],
2057 "pca9552", 0x63);
2058
2059 /*
2060 * Connect PCA9552 GPIO pins 0-4 (SLOTx_EN) outputs to GPIO pins 5-9
2061 * (SLOTx_PG) inputs in order to fake the pgood state of PCIe slots
2062 * after hypervisor code sets a SLOTx_EN pin high.
2063 */
2064 qdev_connect_gpio_out(DEVICE(dev), 0, qdev_get_gpio_in(DEVICE(dev), 5));
2065 qdev_connect_gpio_out(DEVICE(dev), 1, qdev_get_gpio_in(DEVICE(dev), 6));
2066 qdev_connect_gpio_out(DEVICE(dev), 2, qdev_get_gpio_in(DEVICE(dev), 7));
2067 qdev_connect_gpio_out(DEVICE(dev), 3, qdev_get_gpio_in(DEVICE(dev), 8));
2068 qdev_connect_gpio_out(DEVICE(dev), 4, qdev_get_gpio_in(DEVICE(dev), 9));
2069
2070 /*
2071 * Add a PCA9554 I2C device for cable card presence detection
2072 * to engine 2, bus 1, address 0x25
2073 */
2074 i2c_slave_create_simple(chip10->i2c[2].busses[1], "pca9554", 0x25);
2075 }
2076 }
2077
2078 static uint32_t pnv_chip_power10_xscom_pcba(PnvChip *chip, uint64_t addr)
2079 {
2080 addr &= (PNV10_XSCOM_SIZE - 1);
2081 return addr >> 3;
2082 }
2083
2084 static void pnv_chip_power10_class_init(ObjectClass *klass, void *data)
2085 {
2086 DeviceClass *dc = DEVICE_CLASS(klass);
2087 PnvChipClass *k = PNV_CHIP_CLASS(klass);
2088 static const int i2c_ports_per_engine[PNV10_CHIP_MAX_I2C] = {14, 14, 2, 16};
2089
2090 k->chip_cfam_id = 0x120da04900008000ull; /* P10 DD1.0 (with NX) */
2091 k->cores_mask = POWER10_CORE_MASK;
2092 k->chip_pir = pnv_chip_pir_p10;
2093 k->intc_create = pnv_chip_power10_intc_create;
2094 k->intc_reset = pnv_chip_power10_intc_reset;
2095 k->intc_destroy = pnv_chip_power10_intc_destroy;
2096 k->intc_print_info = pnv_chip_power10_intc_print_info;
2097 k->isa_create = pnv_chip_power10_isa_create;
2098 k->dt_populate = pnv_chip_power10_dt_populate;
2099 k->pic_print_info = pnv_chip_power10_pic_print_info;
2100 k->xscom_core_base = pnv_chip_power10_xscom_core_base;
2101 k->xscom_pcba = pnv_chip_power10_xscom_pcba;
2102 dc->desc = "PowerNV Chip POWER10";
2103 k->num_pecs = PNV10_CHIP_MAX_PEC;
2104 k->i2c_num_engines = PNV10_CHIP_MAX_I2C;
2105 k->i2c_ports_per_engine = i2c_ports_per_engine;
2106
2107 device_class_set_parent_realize(dc, pnv_chip_power10_realize,
2108 &k->parent_realize);
2109 }
2110
2111 static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp)
2112 {
2113 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
2114 int cores_max;
2115
2116 /*
2117 * No custom mask for this chip, let's use the default one from *
2118 * the chip class
2119 */
2120 if (!chip->cores_mask) {
2121 chip->cores_mask = pcc->cores_mask;
2122 }
2123
2124 /* filter alien core ids ! some are reserved */
2125 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) {
2126 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !",
2127 chip->cores_mask);
2128 return;
2129 }
2130 chip->cores_mask &= pcc->cores_mask;
2131
2132 /* now that we have a sane layout, let check the number of cores */
2133 cores_max = ctpop64(chip->cores_mask);
2134 if (chip->nr_cores > cores_max) {
2135 error_setg(errp, "warning: too many cores for chip ! Limit is %d",
2136 cores_max);
2137 return;
2138 }
2139 }
2140
2141 static void pnv_chip_core_realize(PnvChip *chip, Error **errp)
2142 {
2143 Error *error = NULL;
2144 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
2145 const char *typename = pnv_chip_core_typename(chip);
2146 int i, core_hwid;
2147 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine());
2148
2149 if (!object_class_by_name(typename)) {
2150 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename);
2151 return;
2152 }
2153
2154 /* Cores */
2155 pnv_chip_core_sanitize(chip, &error);
2156 if (error) {
2157 error_propagate(errp, error);
2158 return;
2159 }
2160
2161 chip->cores = g_new0(PnvCore *, chip->nr_cores);
2162
2163 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8)
2164 && (i < chip->nr_cores); core_hwid++) {
2165 char core_name[32];
2166 PnvCore *pnv_core;
2167 uint64_t xscom_core_base;
2168
2169 if (!(chip->cores_mask & (1ull << core_hwid))) {
2170 continue;
2171 }
2172
2173 pnv_core = PNV_CORE(object_new(typename));
2174
2175 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid);
2176 object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core));
2177 chip->cores[i] = pnv_core;
2178 object_property_set_int(OBJECT(pnv_core), "nr-threads",
2179 chip->nr_threads, &error_fatal);
2180 object_property_set_int(OBJECT(pnv_core), CPU_CORE_PROP_CORE_ID,
2181 core_hwid, &error_fatal);
2182 object_property_set_int(OBJECT(pnv_core), "hwid", core_hwid,
2183 &error_fatal);
2184 object_property_set_int(OBJECT(pnv_core), "hrmor", pnv->fw_load_addr,
2185 &error_fatal);
2186 object_property_set_link(OBJECT(pnv_core), "chip", OBJECT(chip),
2187 &error_abort);
2188 qdev_realize(DEVICE(pnv_core), NULL, &error_fatal);
2189
2190 /* Each core has an XSCOM MMIO region */
2191 xscom_core_base = pcc->xscom_core_base(chip, core_hwid);
2192
2193 pnv_xscom_add_subregion(chip, xscom_core_base,
2194 &pnv_core->xscom_regs);
2195 i++;
2196 }
2197 }
2198
2199 static void pnv_chip_realize(DeviceState *dev, Error **errp)
2200 {
2201 PnvChip *chip = PNV_CHIP(dev);
2202 Error *error = NULL;
2203
2204 /* Cores */
2205 pnv_chip_core_realize(chip, &error);
2206 if (error) {
2207 error_propagate(errp, error);
2208 return;
2209 }
2210 }
2211
2212 static Property pnv_chip_properties[] = {
2213 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0),
2214 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0),
2215 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0),
2216 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1),
2217 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0),
2218 DEFINE_PROP_UINT32("nr-threads", PnvChip, nr_threads, 1),
2219 DEFINE_PROP_END_OF_LIST(),
2220 };
2221
2222 static void pnv_chip_class_init(ObjectClass *klass, void *data)
2223 {
2224 DeviceClass *dc = DEVICE_CLASS(klass);
2225
2226 set_bit(DEVICE_CATEGORY_CPU, dc->categories);
2227 dc->realize = pnv_chip_realize;
2228 device_class_set_props(dc, pnv_chip_properties);
2229 dc->desc = "PowerNV Chip";
2230 }
2231
2232 PnvCore *pnv_chip_find_core(PnvChip *chip, uint32_t core_id)
2233 {
2234 int i;
2235
2236 for (i = 0; i < chip->nr_cores; i++) {
2237 PnvCore *pc = chip->cores[i];
2238 CPUCore *cc = CPU_CORE(pc);
2239
2240 if (cc->core_id == core_id) {
2241 return pc;
2242 }
2243 }
2244 return NULL;
2245 }
2246
2247 PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir)
2248 {
2249 int i, j;
2250
2251 for (i = 0; i < chip->nr_cores; i++) {
2252 PnvCore *pc = chip->cores[i];
2253 CPUCore *cc = CPU_CORE(pc);
2254
2255 for (j = 0; j < cc->nr_threads; j++) {
2256 if (ppc_cpu_pir(pc->threads[j]) == pir) {
2257 return pc->threads[j];
2258 }
2259 }
2260 }
2261 return NULL;
2262 }
2263
2264 static void pnv_chip_foreach_cpu(PnvChip *chip,
2265 void (*fn)(PnvChip *chip, PowerPCCPU *cpu, void *opaque),
2266 void *opaque)
2267 {
2268 int i, j;
2269
2270 for (i = 0; i < chip->nr_cores; i++) {
2271 PnvCore *pc = chip->cores[i];
2272
2273 for (j = 0; j < CPU_CORE(pc)->nr_threads; j++) {
2274 fn(chip, pc->threads[j], opaque);
2275 }
2276 }
2277 }
2278
2279 static ICSState *pnv_ics_get(XICSFabric *xi, int irq)
2280 {
2281 PnvMachineState *pnv = PNV_MACHINE(xi);
2282 int i, j;
2283
2284 for (i = 0; i < pnv->num_chips; i++) {
2285 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]);
2286
2287 if (ics_valid_irq(&chip8->psi.ics, irq)) {
2288 return &chip8->psi.ics;
2289 }
2290
2291 for (j = 0; j < chip8->num_phbs; j++) {
2292 PnvPHB *phb = chip8->phbs[j];
2293 PnvPHB3 *phb3 = PNV_PHB3(phb->backend);
2294
2295 if (ics_valid_irq(&phb3->lsis, irq)) {
2296 return &phb3->lsis;
2297 }
2298
2299 if (ics_valid_irq(ICS(&phb3->msis), irq)) {
2300 return ICS(&phb3->msis);
2301 }
2302 }
2303 }
2304 return NULL;
2305 }
2306
2307 PnvChip *pnv_get_chip(PnvMachineState *pnv, uint32_t chip_id)
2308 {
2309 int i;
2310
2311 for (i = 0; i < pnv->num_chips; i++) {
2312 PnvChip *chip = pnv->chips[i];
2313 if (chip->chip_id == chip_id) {
2314 return chip;
2315 }
2316 }
2317 return NULL;
2318 }
2319
2320 static void pnv_ics_resend(XICSFabric *xi)
2321 {
2322 PnvMachineState *pnv = PNV_MACHINE(xi);
2323 int i, j;
2324
2325 for (i = 0; i < pnv->num_chips; i++) {
2326 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]);
2327
2328 ics_resend(&chip8->psi.ics);
2329
2330 for (j = 0; j < chip8->num_phbs; j++) {
2331 PnvPHB *phb = chip8->phbs[j];
2332 PnvPHB3 *phb3 = PNV_PHB3(phb->backend);
2333
2334 ics_resend(&phb3->lsis);
2335 ics_resend(ICS(&phb3->msis));
2336 }
2337 }
2338 }
2339
2340 static ICPState *pnv_icp_get(XICSFabric *xi, int pir)
2341 {
2342 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir);
2343
2344 return cpu ? ICP(pnv_cpu_state(cpu)->intc) : NULL;
2345 }
2346
2347 static void pnv_pic_intc_print_info(PnvChip *chip, PowerPCCPU *cpu,
2348 void *opaque)
2349 {
2350 PNV_CHIP_GET_CLASS(chip)->intc_print_info(chip, cpu, opaque);
2351 }
2352
2353 static void pnv_pic_print_info(InterruptStatsProvider *obj, GString *buf)
2354 {
2355 PnvMachineState *pnv = PNV_MACHINE(obj);
2356 int i;
2357
2358 for (i = 0; i < pnv->num_chips; i++) {
2359 PnvChip *chip = pnv->chips[i];
2360
2361 /* First CPU presenters */
2362 pnv_chip_foreach_cpu(chip, pnv_pic_intc_print_info, buf);
2363
2364 /* Then other devices, PHB, PSI, XIVE */
2365 PNV_CHIP_GET_CLASS(chip)->pic_print_info(chip, buf);
2366 }
2367 }
2368
2369 static int pnv_match_nvt(XiveFabric *xfb, uint8_t format,
2370 uint8_t nvt_blk, uint32_t nvt_idx,
2371 bool cam_ignore, uint8_t priority,
2372 uint32_t logic_serv,
2373 XiveTCTXMatch *match)
2374 {
2375 PnvMachineState *pnv = PNV_MACHINE(xfb);
2376 int total_count = 0;
2377 int i;
2378
2379 for (i = 0; i < pnv->num_chips; i++) {
2380 Pnv9Chip *chip9 = PNV9_CHIP(pnv->chips[i]);
2381 XivePresenter *xptr = XIVE_PRESENTER(&chip9->xive);
2382 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr);
2383 int count;
2384
2385 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore,
2386 priority, logic_serv, match);
2387
2388 if (count < 0) {
2389 return count;
2390 }
2391
2392 total_count += count;
2393 }
2394
2395 return total_count;
2396 }
2397
2398 static int pnv10_xive_match_nvt(XiveFabric *xfb, uint8_t format,
2399 uint8_t nvt_blk, uint32_t nvt_idx,
2400 bool cam_ignore, uint8_t priority,
2401 uint32_t logic_serv,
2402 XiveTCTXMatch *match)
2403 {
2404 PnvMachineState *pnv = PNV_MACHINE(xfb);
2405 int total_count = 0;
2406 int i;
2407
2408 for (i = 0; i < pnv->num_chips; i++) {
2409 Pnv10Chip *chip10 = PNV10_CHIP(pnv->chips[i]);
2410 XivePresenter *xptr = XIVE_PRESENTER(&chip10->xive);
2411 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr);
2412 int count;
2413
2414 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore,
2415 priority, logic_serv, match);
2416
2417 if (count < 0) {
2418 return count;
2419 }
2420
2421 total_count += count;
2422 }
2423
2424 return total_count;
2425 }
2426
2427 static void pnv_machine_power8_class_init(ObjectClass *oc, void *data)
2428 {
2429 MachineClass *mc = MACHINE_CLASS(oc);
2430 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc);
2431 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc);
2432 static const char compat[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv";
2433
2434 static GlobalProperty phb_compat[] = {
2435 { TYPE_PNV_PHB, "version", "3" },
2436 { TYPE_PNV_PHB_ROOT_PORT, "version", "3" },
2437 };
2438
2439 mc->desc = "IBM PowerNV (Non-Virtualized) POWER8";
2440 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0");
2441 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat));
2442
2443 xic->icp_get = pnv_icp_get;
2444 xic->ics_get = pnv_ics_get;
2445 xic->ics_resend = pnv_ics_resend;
2446
2447 pmc->compat = compat;
2448 pmc->compat_size = sizeof(compat);
2449
2450 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB);
2451 }
2452
2453 static void pnv_machine_power9_class_init(ObjectClass *oc, void *data)
2454 {
2455 MachineClass *mc = MACHINE_CLASS(oc);
2456 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc);
2457 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc);
2458 static const char compat[] = "qemu,powernv9\0ibm,powernv";
2459
2460 static GlobalProperty phb_compat[] = {
2461 { TYPE_PNV_PHB, "version", "4" },
2462 { TYPE_PNV_PHB_ROOT_PORT, "version", "4" },
2463 };
2464
2465 mc->desc = "IBM PowerNV (Non-Virtualized) POWER9";
2466 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.2");
2467 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat));
2468
2469 xfc->match_nvt = pnv_match_nvt;
2470
2471 pmc->compat = compat;
2472 pmc->compat_size = sizeof(compat);
2473 pmc->dt_power_mgt = pnv_dt_power_mgt;
2474
2475 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB);
2476 }
2477
2478 static void pnv_machine_p10_common_class_init(ObjectClass *oc, void *data)
2479 {
2480 MachineClass *mc = MACHINE_CLASS(oc);
2481 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc);
2482 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc);
2483 static const char compat[] = "qemu,powernv10\0ibm,powernv";
2484
2485 static GlobalProperty phb_compat[] = {
2486 { TYPE_PNV_PHB, "version", "5" },
2487 { TYPE_PNV_PHB_ROOT_PORT, "version", "5" },
2488 };
2489
2490 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v2.0");
2491 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat));
2492
2493 mc->alias = "powernv";
2494
2495 pmc->compat = compat;
2496 pmc->compat_size = sizeof(compat);
2497 pmc->dt_power_mgt = pnv_dt_power_mgt;
2498
2499 xfc->match_nvt = pnv10_xive_match_nvt;
2500
2501 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB);
2502 }
2503
2504 static void pnv_machine_power10_class_init(ObjectClass *oc, void *data)
2505 {
2506 MachineClass *mc = MACHINE_CLASS(oc);
2507
2508 pnv_machine_p10_common_class_init(oc, data);
2509 mc->desc = "IBM PowerNV (Non-Virtualized) POWER10";
2510 }
2511
2512 static void pnv_machine_p10_rainier_class_init(ObjectClass *oc, void *data)
2513 {
2514 MachineClass *mc = MACHINE_CLASS(oc);
2515 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc);
2516
2517 pnv_machine_p10_common_class_init(oc, data);
2518 mc->desc = "IBM PowerNV (Non-Virtualized) POWER10 Rainier";
2519 pmc->i2c_init = pnv_rainier_i2c_init;
2520 }
2521
2522 static bool pnv_machine_get_hb(Object *obj, Error **errp)
2523 {
2524 PnvMachineState *pnv = PNV_MACHINE(obj);
2525
2526 return !!pnv->fw_load_addr;
2527 }
2528
2529 static void pnv_machine_set_hb(Object *obj, bool value, Error **errp)
2530 {
2531 PnvMachineState *pnv = PNV_MACHINE(obj);
2532
2533 if (value) {
2534 pnv->fw_load_addr = 0x8000000;
2535 }
2536 }
2537
2538 static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, run_on_cpu_data arg)
2539 {
2540 CPUPPCState *env = cpu_env(cs);
2541
2542 cpu_synchronize_state(cs);
2543 ppc_cpu_do_system_reset(cs);
2544 if (env->spr[SPR_SRR1] & SRR1_WAKESTATE) {
2545 /*
2546 * Power-save wakeups, as indicated by non-zero SRR1[46:47] put the
2547 * wakeup reason in SRR1[42:45], system reset is indicated with 0b0100
2548 * (PPC_BIT(43)).
2549 */
2550 if (!(env->spr[SPR_SRR1] & SRR1_WAKERESET)) {
2551 warn_report("ppc_cpu_do_system_reset does not set system reset wakeup reason");
2552 env->spr[SPR_SRR1] |= SRR1_WAKERESET;
2553 }
2554 } else {
2555 /*
2556 * For non-powersave system resets, SRR1[42:45] are defined to be
2557 * implementation-dependent. The POWER9 User Manual specifies that
2558 * an external (SCOM driven, which may come from a BMC nmi command or
2559 * another CPU requesting a NMI IPI) system reset exception should be
2560 * 0b0010 (PPC_BIT(44)).
2561 */
2562 env->spr[SPR_SRR1] |= SRR1_WAKESCOM;
2563 }
2564 }
2565
2566 static void pnv_cpu_do_nmi(PnvChip *chip, PowerPCCPU *cpu, void *opaque)
2567 {
2568 async_run_on_cpu(CPU(cpu), pnv_cpu_do_nmi_on_cpu, RUN_ON_CPU_NULL);
2569 }
2570
2571 static void pnv_nmi(NMIState *n, int cpu_index, Error **errp)
2572 {
2573 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine());
2574 int i;
2575
2576 for (i = 0; i < pnv->num_chips; i++) {
2577 pnv_chip_foreach_cpu(pnv->chips[i], pnv_cpu_do_nmi, NULL);
2578 }
2579 }
2580
2581 static void pnv_machine_class_init(ObjectClass *oc, void *data)
2582 {
2583 MachineClass *mc = MACHINE_CLASS(oc);
2584 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc);
2585 NMIClass *nc = NMI_CLASS(oc);
2586
2587 mc->desc = "IBM PowerNV (Non-Virtualized)";
2588 mc->init = pnv_init;
2589 mc->reset = pnv_reset;
2590 mc->max_cpus = MAX_CPUS;
2591 /* Pnv provides a AHCI device for storage */
2592 mc->block_default_type = IF_IDE;
2593 mc->no_parallel = 1;
2594 mc->default_boot_order = NULL;
2595 /*
2596 * RAM defaults to less than 2048 for 32-bit hosts, and large
2597 * enough to fit the maximum initrd size at it's load address
2598 */
2599 mc->default_ram_size = 1 * GiB;
2600 mc->default_ram_id = "pnv.ram";
2601 ispc->print_info = pnv_pic_print_info;
2602 nc->nmi_monitor_handler = pnv_nmi;
2603
2604 object_class_property_add_bool(oc, "hb-mode",
2605 pnv_machine_get_hb, pnv_machine_set_hb);
2606 object_class_property_set_description(oc, "hb-mode",
2607 "Use a hostboot like boot loader");
2608 }
2609
2610 #define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \
2611 { \
2612 .name = type, \
2613 .class_init = class_initfn, \
2614 .parent = TYPE_PNV8_CHIP, \
2615 }
2616
2617 #define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \
2618 { \
2619 .name = type, \
2620 .class_init = class_initfn, \
2621 .parent = TYPE_PNV9_CHIP, \
2622 }
2623
2624 #define DEFINE_PNV10_CHIP_TYPE(type, class_initfn) \
2625 { \
2626 .name = type, \
2627 .class_init = class_initfn, \
2628 .parent = TYPE_PNV10_CHIP, \
2629 }
2630
2631 static const TypeInfo types[] = {
2632 {
2633 .name = MACHINE_TYPE_NAME("powernv10-rainier"),
2634 .parent = MACHINE_TYPE_NAME("powernv10"),
2635 .class_init = pnv_machine_p10_rainier_class_init,
2636 },
2637 {
2638 .name = MACHINE_TYPE_NAME("powernv10"),
2639 .parent = TYPE_PNV_MACHINE,
2640 .class_init = pnv_machine_power10_class_init,
2641 .interfaces = (InterfaceInfo[]) {
2642 { TYPE_XIVE_FABRIC },
2643 { },
2644 },
2645 },
2646 {
2647 .name = MACHINE_TYPE_NAME("powernv9"),
2648 .parent = TYPE_PNV_MACHINE,
2649 .class_init = pnv_machine_power9_class_init,
2650 .interfaces = (InterfaceInfo[]) {
2651 { TYPE_XIVE_FABRIC },
2652 { },
2653 },
2654 },
2655 {
2656 .name = MACHINE_TYPE_NAME("powernv8"),
2657 .parent = TYPE_PNV_MACHINE,
2658 .class_init = pnv_machine_power8_class_init,
2659 .interfaces = (InterfaceInfo[]) {
2660 { TYPE_XICS_FABRIC },
2661 { },
2662 },
2663 },
2664 {
2665 .name = TYPE_PNV_MACHINE,
2666 .parent = TYPE_MACHINE,
2667 .abstract = true,
2668 .instance_size = sizeof(PnvMachineState),
2669 .class_init = pnv_machine_class_init,
2670 .class_size = sizeof(PnvMachineClass),
2671 .interfaces = (InterfaceInfo[]) {
2672 { TYPE_INTERRUPT_STATS_PROVIDER },
2673 { TYPE_NMI },
2674 { },
2675 },
2676 },
2677 {
2678 .name = TYPE_PNV_CHIP,
2679 .parent = TYPE_SYS_BUS_DEVICE,
2680 .class_init = pnv_chip_class_init,
2681 .instance_size = sizeof(PnvChip),
2682 .class_size = sizeof(PnvChipClass),
2683 .abstract = true,
2684 },
2685
2686 /*
2687 * P10 chip and variants
2688 */
2689 {
2690 .name = TYPE_PNV10_CHIP,
2691 .parent = TYPE_PNV_CHIP,
2692 .instance_init = pnv_chip_power10_instance_init,
2693 .instance_size = sizeof(Pnv10Chip),
2694 },
2695 DEFINE_PNV10_CHIP_TYPE(TYPE_PNV_CHIP_POWER10, pnv_chip_power10_class_init),
2696
2697 /*
2698 * P9 chip and variants
2699 */
2700 {
2701 .name = TYPE_PNV9_CHIP,
2702 .parent = TYPE_PNV_CHIP,
2703 .instance_init = pnv_chip_power9_instance_init,
2704 .instance_size = sizeof(Pnv9Chip),
2705 },
2706 DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init),
2707
2708 /*
2709 * P8 chip and variants
2710 */
2711 {
2712 .name = TYPE_PNV8_CHIP,
2713 .parent = TYPE_PNV_CHIP,
2714 .instance_init = pnv_chip_power8_instance_init,
2715 .instance_size = sizeof(Pnv8Chip),
2716 },
2717 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init),
2718 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_init),
2719 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL,
2720 pnv_chip_power8nvl_class_init),
2721 };
2722
2723 DEFINE_TYPES(types)
armbru's QEMU hackery