2 * QEMU IDE Emulation: PCI Bus support.
4 * Copyright (c) 2003 Fabrice Bellard
5 * Copyright (c) 2006 Openedhand Ltd.
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 #include "qemu/osdep.h"
28 #include "hw/pci/pci.h"
29 #include "migration/vmstate.h"
30 #include "sysemu/dma.h"
31 #include "qemu/error-report.h"
32 #include "qemu/module.h"
33 #include "hw/ide/pci.h"
36 #define BMDMA_PAGE_SIZE 4096
38 #define BM_MIGRATION_COMPAT_STATUS_BITS \
39 (IDE_RETRY_DMA | IDE_RETRY_PIO | \
40 IDE_RETRY_READ | IDE_RETRY_FLUSH)
42 static uint64_t pci_ide_status_read(void *opaque
, hwaddr addr
, unsigned size
)
46 if (addr
!= 2 || size
!= 1) {
47 return ((uint64_t)1 << (size
* 8)) - 1;
49 return ide_status_read(bus
, addr
+ 2);
52 static void pci_ide_ctrl_write(void *opaque
, hwaddr addr
,
53 uint64_t data
, unsigned size
)
57 if (addr
!= 2 || size
!= 1) {
60 ide_ctrl_write(bus
, addr
+ 2, data
);
63 const MemoryRegionOps pci_ide_cmd_le_ops
= {
64 .read
= pci_ide_status_read
,
65 .write
= pci_ide_ctrl_write
,
66 .endianness
= DEVICE_LITTLE_ENDIAN
,
69 static uint64_t pci_ide_data_read(void *opaque
, hwaddr addr
, unsigned size
)
74 return ide_ioport_read(bus
, addr
);
75 } else if (addr
== 0) {
77 return ide_data_readw(bus
, addr
);
79 return ide_data_readl(bus
, addr
);
82 return ((uint64_t)1 << (size
* 8)) - 1;
85 static void pci_ide_data_write(void *opaque
, hwaddr addr
,
86 uint64_t data
, unsigned size
)
91 ide_ioport_write(bus
, addr
, data
);
92 } else if (addr
== 0) {
94 ide_data_writew(bus
, addr
, data
);
96 ide_data_writel(bus
, addr
, data
);
101 const MemoryRegionOps pci_ide_data_le_ops
= {
102 .read
= pci_ide_data_read
,
103 .write
= pci_ide_data_write
,
104 .endianness
= DEVICE_LITTLE_ENDIAN
,
107 static IDEState
*bmdma_active_if(BMDMAState
*bmdma
)
109 assert(bmdma
->bus
->retry_unit
!= (uint8_t)-1);
110 return bmdma
->bus
->ifs
+ bmdma
->bus
->retry_unit
;
113 static void bmdma_start_dma(const IDEDMA
*dma
, IDEState
*s
,
114 BlockCompletionFunc
*dma_cb
)
116 BMDMAState
*bm
= DO_UPCAST(BMDMAState
, dma
, dma
);
119 bm
->cur_prd_last
= 0;
120 bm
->cur_prd_addr
= 0;
123 if (bm
->status
& BM_STATUS_DMAING
) {
124 bm
->dma_cb(bmdma_active_if(bm
), 0);
129 * Prepare an sglist based on available PRDs.
130 * @limit: How many bytes to prepare total.
132 * Returns the number of bytes prepared, -1 on error.
133 * IDEState.io_buffer_size will contain the number of bytes described
134 * by the PRDs, whether or not we added them to the sglist.
136 static int32_t bmdma_prepare_buf(const IDEDMA
*dma
, int32_t limit
)
138 BMDMAState
*bm
= DO_UPCAST(BMDMAState
, dma
, dma
);
139 IDEState
*s
= bmdma_active_if(bm
);
140 PCIDevice
*pci_dev
= PCI_DEVICE(bm
->pci_dev
);
147 pci_dma_sglist_init(&s
->sg
, pci_dev
,
148 s
->nsector
/ (BMDMA_PAGE_SIZE
/ BDRV_SECTOR_SIZE
) + 1);
149 s
->io_buffer_size
= 0;
151 if (bm
->cur_prd_len
== 0) {
152 /* end of table (with a fail safe of one page) */
153 if (bm
->cur_prd_last
||
154 (bm
->cur_addr
- bm
->addr
) >= BMDMA_PAGE_SIZE
) {
157 pci_dma_read(pci_dev
, bm
->cur_addr
, &prd
, 8);
159 prd
.addr
= le32_to_cpu(prd
.addr
);
160 prd
.size
= le32_to_cpu(prd
.size
);
161 len
= prd
.size
& 0xfffe;
164 bm
->cur_prd_len
= len
;
165 bm
->cur_prd_addr
= prd
.addr
;
166 bm
->cur_prd_last
= (prd
.size
& 0x80000000);
172 /* Don't add extra bytes to the SGList; consume any remaining
173 * PRDs from the guest, but ignore them. */
174 sg_len
= MIN(limit
- s
->sg
.size
, bm
->cur_prd_len
);
176 qemu_sglist_add(&s
->sg
, bm
->cur_prd_addr
, sg_len
);
179 bm
->cur_prd_addr
+= l
;
180 bm
->cur_prd_len
-= l
;
181 s
->io_buffer_size
+= l
;
185 qemu_sglist_destroy(&s
->sg
);
186 s
->io_buffer_size
= 0;
190 /* return 0 if buffer completed */
191 static int bmdma_rw_buf(const IDEDMA
*dma
, bool is_write
)
193 BMDMAState
*bm
= DO_UPCAST(BMDMAState
, dma
, dma
);
194 IDEState
*s
= bmdma_active_if(bm
);
195 PCIDevice
*pci_dev
= PCI_DEVICE(bm
->pci_dev
);
203 l
= s
->io_buffer_size
- s
->io_buffer_index
;
206 if (bm
->cur_prd_len
== 0) {
207 /* end of table (with a fail safe of one page) */
208 if (bm
->cur_prd_last
||
209 (bm
->cur_addr
- bm
->addr
) >= BMDMA_PAGE_SIZE
)
211 pci_dma_read(pci_dev
, bm
->cur_addr
, &prd
, 8);
213 prd
.addr
= le32_to_cpu(prd
.addr
);
214 prd
.size
= le32_to_cpu(prd
.size
);
215 len
= prd
.size
& 0xfffe;
218 bm
->cur_prd_len
= len
;
219 bm
->cur_prd_addr
= prd
.addr
;
220 bm
->cur_prd_last
= (prd
.size
& 0x80000000);
222 if (l
> bm
->cur_prd_len
)
226 pci_dma_write(pci_dev
, bm
->cur_prd_addr
,
227 s
->io_buffer
+ s
->io_buffer_index
, l
);
229 pci_dma_read(pci_dev
, bm
->cur_prd_addr
,
230 s
->io_buffer
+ s
->io_buffer_index
, l
);
232 bm
->cur_prd_addr
+= l
;
233 bm
->cur_prd_len
-= l
;
234 s
->io_buffer_index
+= l
;
240 static void bmdma_set_inactive(const IDEDMA
*dma
, bool more
)
242 BMDMAState
*bm
= DO_UPCAST(BMDMAState
, dma
, dma
);
246 bm
->status
|= BM_STATUS_DMAING
;
248 bm
->status
&= ~BM_STATUS_DMAING
;
252 static void bmdma_restart_dma(const IDEDMA
*dma
)
254 BMDMAState
*bm
= DO_UPCAST(BMDMAState
, dma
, dma
);
256 bm
->cur_addr
= bm
->addr
;
259 static void bmdma_cancel(BMDMAState
*bm
)
261 if (bm
->status
& BM_STATUS_DMAING
) {
262 /* cancel DMA request */
263 bmdma_set_inactive(&bm
->dma
, false);
267 static void bmdma_reset(const IDEDMA
*dma
)
269 BMDMAState
*bm
= DO_UPCAST(BMDMAState
, dma
, dma
);
277 bm
->cur_prd_last
= 0;
278 bm
->cur_prd_addr
= 0;
282 static void bmdma_irq(void *opaque
, int n
, int level
)
284 BMDMAState
*bm
= opaque
;
287 /* pass through lower */
288 qemu_set_irq(bm
->irq
, level
);
292 bm
->status
|= BM_STATUS_INT
;
294 /* trigger the real irq */
295 qemu_set_irq(bm
->irq
, level
);
298 void bmdma_cmd_writeb(BMDMAState
*bm
, uint32_t val
)
300 trace_bmdma_cmd_writeb(val
);
302 /* Ignore writes to SSBM if it keeps the old value */
303 if ((val
& BM_CMD_START
) != (bm
->cmd
& BM_CMD_START
)) {
304 if (!(val
& BM_CMD_START
)) {
305 ide_cancel_dma_sync(ide_bus_active_if(bm
->bus
));
306 bm
->status
&= ~BM_STATUS_DMAING
;
308 bm
->cur_addr
= bm
->addr
;
309 if (!(bm
->status
& BM_STATUS_DMAING
)) {
310 bm
->status
|= BM_STATUS_DMAING
;
311 /* start dma transfer if possible */
313 bm
->dma_cb(bmdma_active_if(bm
), 0);
318 bm
->cmd
= val
& 0x09;
321 static uint64_t bmdma_addr_read(void *opaque
, hwaddr addr
,
324 BMDMAState
*bm
= opaque
;
325 uint32_t mask
= (1ULL << (width
* 8)) - 1;
328 data
= (bm
->addr
>> (addr
* 8)) & mask
;
329 trace_bmdma_addr_read(data
);
333 static void bmdma_addr_write(void *opaque
, hwaddr addr
,
334 uint64_t data
, unsigned width
)
336 BMDMAState
*bm
= opaque
;
337 int shift
= addr
* 8;
338 uint32_t mask
= (1ULL << (width
* 8)) - 1;
340 trace_bmdma_addr_write(data
);
341 bm
->addr
&= ~(mask
<< shift
);
342 bm
->addr
|= ((data
& mask
) << shift
) & ~3;
345 MemoryRegionOps bmdma_addr_ioport_ops
= {
346 .read
= bmdma_addr_read
,
347 .write
= bmdma_addr_write
,
348 .endianness
= DEVICE_LITTLE_ENDIAN
,
351 static bool ide_bmdma_current_needed(void *opaque
)
353 BMDMAState
*bm
= opaque
;
355 return (bm
->cur_prd_len
!= 0);
358 static bool ide_bmdma_status_needed(void *opaque
)
360 BMDMAState
*bm
= opaque
;
362 /* Older versions abused some bits in the status register for internal
363 * error state. If any of these bits are set, we must add a subsection to
364 * transfer the real status register */
365 uint8_t abused_bits
= BM_MIGRATION_COMPAT_STATUS_BITS
;
367 return ((bm
->status
& abused_bits
) != 0);
370 static int ide_bmdma_pre_save(void *opaque
)
372 BMDMAState
*bm
= opaque
;
373 uint8_t abused_bits
= BM_MIGRATION_COMPAT_STATUS_BITS
;
375 if (!(bm
->status
& BM_STATUS_DMAING
) && bm
->dma_cb
) {
376 bm
->bus
->error_status
=
377 ide_dma_cmd_to_retry(bmdma_active_if(bm
)->dma_cmd
);
379 bm
->migration_retry_unit
= bm
->bus
->retry_unit
;
380 bm
->migration_retry_sector_num
= bm
->bus
->retry_sector_num
;
381 bm
->migration_retry_nsector
= bm
->bus
->retry_nsector
;
382 bm
->migration_compat_status
=
383 (bm
->status
& ~abused_bits
) | (bm
->bus
->error_status
& abused_bits
);
388 /* This function accesses bm->bus->error_status which is loaded only after
389 * BMDMA itself. This is why the function is called from ide_pci_post_load
390 * instead of being registered with VMState where it would run too early. */
391 static int ide_bmdma_post_load(void *opaque
, int version_id
)
393 BMDMAState
*bm
= opaque
;
394 uint8_t abused_bits
= BM_MIGRATION_COMPAT_STATUS_BITS
;
396 if (bm
->status
== 0) {
397 bm
->status
= bm
->migration_compat_status
& ~abused_bits
;
398 bm
->bus
->error_status
|= bm
->migration_compat_status
& abused_bits
;
400 if (bm
->bus
->error_status
) {
401 bm
->bus
->retry_sector_num
= bm
->migration_retry_sector_num
;
402 bm
->bus
->retry_nsector
= bm
->migration_retry_nsector
;
403 bm
->bus
->retry_unit
= bm
->migration_retry_unit
;
409 static const VMStateDescription vmstate_bmdma_current
= {
410 .name
= "ide bmdma_current",
412 .minimum_version_id
= 1,
413 .needed
= ide_bmdma_current_needed
,
414 .fields
= (VMStateField
[]) {
415 VMSTATE_UINT32(cur_addr
, BMDMAState
),
416 VMSTATE_UINT32(cur_prd_last
, BMDMAState
),
417 VMSTATE_UINT32(cur_prd_addr
, BMDMAState
),
418 VMSTATE_UINT32(cur_prd_len
, BMDMAState
),
419 VMSTATE_END_OF_LIST()
423 static const VMStateDescription vmstate_bmdma_status
= {
424 .name
="ide bmdma/status",
426 .minimum_version_id
= 1,
427 .needed
= ide_bmdma_status_needed
,
428 .fields
= (VMStateField
[]) {
429 VMSTATE_UINT8(status
, BMDMAState
),
430 VMSTATE_END_OF_LIST()
434 static const VMStateDescription vmstate_bmdma
= {
437 .minimum_version_id
= 0,
438 .pre_save
= ide_bmdma_pre_save
,
439 .fields
= (VMStateField
[]) {
440 VMSTATE_UINT8(cmd
, BMDMAState
),
441 VMSTATE_UINT8(migration_compat_status
, BMDMAState
),
442 VMSTATE_UINT32(addr
, BMDMAState
),
443 VMSTATE_INT64(migration_retry_sector_num
, BMDMAState
),
444 VMSTATE_UINT32(migration_retry_nsector
, BMDMAState
),
445 VMSTATE_UINT8(migration_retry_unit
, BMDMAState
),
446 VMSTATE_END_OF_LIST()
448 .subsections
= (const VMStateDescription
*[]) {
449 &vmstate_bmdma_current
,
450 &vmstate_bmdma_status
,
455 static int ide_pci_post_load(void *opaque
, int version_id
)
457 PCIIDEState
*d
= opaque
;
460 for(i
= 0; i
< 2; i
++) {
461 /* current versions always store 0/1, but older version
462 stored bigger values. We only need last bit */
463 d
->bmdma
[i
].migration_retry_unit
&= 1;
464 ide_bmdma_post_load(&d
->bmdma
[i
], -1);
470 const VMStateDescription vmstate_ide_pci
= {
473 .minimum_version_id
= 0,
474 .post_load
= ide_pci_post_load
,
475 .fields
= (VMStateField
[]) {
476 VMSTATE_PCI_DEVICE(parent_obj
, PCIIDEState
),
477 VMSTATE_STRUCT_ARRAY(bmdma
, PCIIDEState
, 2, 0,
478 vmstate_bmdma
, BMDMAState
),
479 VMSTATE_IDE_BUS_ARRAY(bus
, PCIIDEState
, 2),
480 VMSTATE_IDE_DRIVES(bus
[0].ifs
, PCIIDEState
),
481 VMSTATE_IDE_DRIVES(bus
[1].ifs
, PCIIDEState
),
482 VMSTATE_END_OF_LIST()
486 /* hd_table must contain 4 block drivers */
487 void pci_ide_create_devs(PCIDevice
*dev
)
489 PCIIDEState
*d
= PCI_IDE(dev
);
490 DriveInfo
*hd_table
[2 * MAX_IDE_DEVS
];
491 static const int bus
[4] = { 0, 0, 1, 1 };
492 static const int unit
[4] = { 0, 1, 0, 1 };
495 ide_drive_get(hd_table
, ARRAY_SIZE(hd_table
));
496 for (i
= 0; i
< 4; i
++) {
498 ide_bus_create_drive(d
->bus
+ bus
[i
], unit
[i
], hd_table
[i
]);
503 static const struct IDEDMAOps bmdma_ops
= {
504 .start_dma
= bmdma_start_dma
,
505 .prepare_buf
= bmdma_prepare_buf
,
506 .rw_buf
= bmdma_rw_buf
,
507 .restart_dma
= bmdma_restart_dma
,
508 .set_inactive
= bmdma_set_inactive
,
509 .reset
= bmdma_reset
,
512 void bmdma_init(IDEBus
*bus
, BMDMAState
*bm
, PCIIDEState
*d
)
514 if (bus
->dma
== &bm
->dma
) {
518 bm
->dma
.ops
= &bmdma_ops
;
521 bus
->irq
= qemu_allocate_irq(bmdma_irq
, bm
, 0);
525 static const TypeInfo pci_ide_type_info
= {
526 .name
= TYPE_PCI_IDE
,
527 .parent
= TYPE_PCI_DEVICE
,
528 .instance_size
= sizeof(PCIIDEState
),
530 .interfaces
= (InterfaceInfo
[]) {
531 { INTERFACE_CONVENTIONAL_PCI_DEVICE
},
536 static void pci_ide_register_types(void)
538 type_register_static(&pci_ide_type_info
);
541 type_init(pci_ide_register_types
)