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hw/sd/sdcard: Fix SET_BLOCK_COUNT command argument on eMMC (CMD23)
[qemu/armbru.git] / hw / arm / allwinner-r40.c
blobb8c72021334074e58a9abe8a3370a3f11a2eba37
1 /*
2 * Allwinner R40/A40i/T3 System on Chip emulation
3 *
4 * Copyright (C) 2023 qianfan Zhao <qianfanguijin@163.com>
5 *
6 * This program is free software: you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation, either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "qapi/error.h"
22 #include "qemu/error-report.h"
23 #include "qemu/bswap.h"
24 #include "qemu/module.h"
25 #include "qemu/units.h"
26 #include "hw/boards.h"
27 #include "hw/qdev-core.h"
28 #include "hw/sysbus.h"
29 #include "hw/char/serial.h"
30 #include "hw/misc/unimp.h"
31 #include "hw/usb/hcd-ehci.h"
32 #include "hw/loader.h"
33 #include "sysemu/sysemu.h"
34 #include "hw/arm/allwinner-r40.h"
35 #include "hw/misc/allwinner-r40-dramc.h"
36 #include "target/arm/cpu-qom.h"
37 #include "target/arm/gtimer.h"
38
39 /* Memory map */
40 const hwaddr allwinner_r40_memmap[] = {
41 [AW_R40_DEV_SRAM_A1] = 0x00000000,
42 [AW_R40_DEV_SRAM_A2] = 0x00004000,
43 [AW_R40_DEV_SRAM_A3] = 0x00008000,
44 [AW_R40_DEV_SRAM_A4] = 0x0000b400,
45 [AW_R40_DEV_SRAMC] = 0x01c00000,
46 [AW_R40_DEV_EMAC] = 0x01c0b000,
47 [AW_R40_DEV_MMC0] = 0x01c0f000,
48 [AW_R40_DEV_MMC1] = 0x01c10000,
49 [AW_R40_DEV_MMC2] = 0x01c11000,
50 [AW_R40_DEV_MMC3] = 0x01c12000,
51 [AW_R40_DEV_AHCI] = 0x01c18000,
52 [AW_R40_DEV_EHCI1] = 0x01c19000,
53 [AW_R40_DEV_OHCI1] = 0x01c19400,
54 [AW_R40_DEV_EHCI2] = 0x01c1c000,
55 [AW_R40_DEV_OHCI2] = 0x01c1c400,
56 [AW_R40_DEV_CCU] = 0x01c20000,
57 [AW_R40_DEV_PIT] = 0x01c20c00,
58 [AW_R40_DEV_WDT] = 0x01c20c90,
59 [AW_R40_DEV_UART0] = 0x01c28000,
60 [AW_R40_DEV_UART1] = 0x01c28400,
61 [AW_R40_DEV_UART2] = 0x01c28800,
62 [AW_R40_DEV_UART3] = 0x01c28c00,
63 [AW_R40_DEV_UART4] = 0x01c29000,
64 [AW_R40_DEV_UART5] = 0x01c29400,
65 [AW_R40_DEV_UART6] = 0x01c29800,
66 [AW_R40_DEV_UART7] = 0x01c29c00,
67 [AW_R40_DEV_TWI0] = 0x01c2ac00,
68 [AW_R40_DEV_GMAC] = 0x01c50000,
69 [AW_R40_DEV_DRAMCOM] = 0x01c62000,
70 [AW_R40_DEV_DRAMCTL] = 0x01c63000,
71 [AW_R40_DEV_DRAMPHY] = 0x01c65000,
72 [AW_R40_DEV_GIC_DIST] = 0x01c81000,
73 [AW_R40_DEV_GIC_CPU] = 0x01c82000,
74 [AW_R40_DEV_GIC_HYP] = 0x01c84000,
75 [AW_R40_DEV_GIC_VCPU] = 0x01c86000,
76 [AW_R40_DEV_SDRAM] = 0x40000000
77 };
78
79 /* List of unimplemented devices */
80 struct AwR40Unimplemented {
81 const char *device_name;
82 hwaddr base;
83 hwaddr size;
84 };
85
86 static struct AwR40Unimplemented r40_unimplemented[] = {
87 { "d-engine", 0x01000000, 4 * MiB },
88 { "d-inter", 0x01400000, 128 * KiB },
89 { "dma", 0x01c02000, 4 * KiB },
90 { "nfdc", 0x01c03000, 4 * KiB },
91 { "ts", 0x01c04000, 4 * KiB },
92 { "spi0", 0x01c05000, 4 * KiB },
93 { "spi1", 0x01c06000, 4 * KiB },
94 { "cs0", 0x01c09000, 4 * KiB },
95 { "keymem", 0x01c0a000, 4 * KiB },
96 { "usb0-otg", 0x01c13000, 4 * KiB },
97 { "usb0-host", 0x01c14000, 4 * KiB },
98 { "crypto", 0x01c15000, 4 * KiB },
99 { "spi2", 0x01c17000, 4 * KiB },
100 { "usb1-phy", 0x01c19800, 2 * KiB },
101 { "sid", 0x01c1b000, 4 * KiB },
102 { "usb2-phy", 0x01c1c800, 2 * KiB },
103 { "cs1", 0x01c1d000, 4 * KiB },
104 { "spi3", 0x01c1f000, 4 * KiB },
105 { "rtc", 0x01c20400, 1 * KiB },
106 { "pio", 0x01c20800, 1 * KiB },
107 { "owa", 0x01c21000, 1 * KiB },
108 { "ac97", 0x01c21400, 1 * KiB },
109 { "cir0", 0x01c21800, 1 * KiB },
110 { "cir1", 0x01c21c00, 1 * KiB },
111 { "pcm0", 0x01c22000, 1 * KiB },
112 { "pcm1", 0x01c22400, 1 * KiB },
113 { "pcm2", 0x01c22800, 1 * KiB },
114 { "audio", 0x01c22c00, 1 * KiB },
115 { "keypad", 0x01c23000, 1 * KiB },
116 { "pwm", 0x01c23400, 1 * KiB },
117 { "keyadc", 0x01c24400, 1 * KiB },
118 { "ths", 0x01c24c00, 1 * KiB },
119 { "rtp", 0x01c25000, 1 * KiB },
120 { "pmu", 0x01c25400, 1 * KiB },
121 { "cpu-cfg", 0x01c25c00, 1 * KiB },
122 { "uart0", 0x01c28000, 1 * KiB },
123 { "uart1", 0x01c28400, 1 * KiB },
124 { "uart2", 0x01c28800, 1 * KiB },
125 { "uart3", 0x01c28c00, 1 * KiB },
126 { "uart4", 0x01c29000, 1 * KiB },
127 { "uart5", 0x01c29400, 1 * KiB },
128 { "uart6", 0x01c29800, 1 * KiB },
129 { "uart7", 0x01c29c00, 1 * KiB },
130 { "ps20", 0x01c2a000, 1 * KiB },
131 { "ps21", 0x01c2a400, 1 * KiB },
132 { "twi1", 0x01c2b000, 1 * KiB },
133 { "twi2", 0x01c2b400, 1 * KiB },
134 { "twi3", 0x01c2b800, 1 * KiB },
135 { "twi4", 0x01c2c000, 1 * KiB },
136 { "scr", 0x01c2c400, 1 * KiB },
137 { "tvd-top", 0x01c30000, 4 * KiB },
138 { "tvd0", 0x01c31000, 4 * KiB },
139 { "tvd1", 0x01c32000, 4 * KiB },
140 { "tvd2", 0x01c33000, 4 * KiB },
141 { "tvd3", 0x01c34000, 4 * KiB },
142 { "gpu", 0x01c40000, 64 * KiB },
143 { "hstmr", 0x01c60000, 4 * KiB },
144 { "tcon-top", 0x01c70000, 4 * KiB },
145 { "lcd0", 0x01c71000, 4 * KiB },
146 { "lcd1", 0x01c72000, 4 * KiB },
147 { "tv0", 0x01c73000, 4 * KiB },
148 { "tv1", 0x01c74000, 4 * KiB },
149 { "tve-top", 0x01c90000, 16 * KiB },
150 { "tve0", 0x01c94000, 16 * KiB },
151 { "tve1", 0x01c98000, 16 * KiB },
152 { "mipi_dsi", 0x01ca0000, 4 * KiB },
153 { "mipi_dphy", 0x01ca1000, 4 * KiB },
154 { "ve", 0x01d00000, 1024 * KiB },
155 { "mp", 0x01e80000, 128 * KiB },
156 { "hdmi", 0x01ee0000, 128 * KiB },
157 { "prcm", 0x01f01400, 1 * KiB },
158 { "debug", 0x3f500000, 64 * KiB },
159 { "cpubist", 0x3f501000, 4 * KiB },
160 { "dcu", 0x3fff0000, 64 * KiB },
161 { "hstmr", 0x01c60000, 4 * KiB },
162 { "brom", 0xffff0000, 36 * KiB }
163 };
164
165 /* Per Processor Interrupts */
166 enum {
167 AW_R40_GIC_PPI_MAINT = 9,
168 AW_R40_GIC_PPI_HYPTIMER = 10,
169 AW_R40_GIC_PPI_VIRTTIMER = 11,
170 AW_R40_GIC_PPI_SECTIMER = 13,
171 AW_R40_GIC_PPI_PHYSTIMER = 14
172 };
173
174 /* Shared Processor Interrupts */
175 enum {
176 AW_R40_GIC_SPI_UART0 = 1,
177 AW_R40_GIC_SPI_UART1 = 2,
178 AW_R40_GIC_SPI_UART2 = 3,
179 AW_R40_GIC_SPI_UART3 = 4,
180 AW_R40_GIC_SPI_TWI0 = 7,
181 AW_R40_GIC_SPI_UART4 = 17,
182 AW_R40_GIC_SPI_UART5 = 18,
183 AW_R40_GIC_SPI_UART6 = 19,
184 AW_R40_GIC_SPI_UART7 = 20,
185 AW_R40_GIC_SPI_TIMER0 = 22,
186 AW_R40_GIC_SPI_TIMER1 = 23,
187 AW_R40_GIC_SPI_MMC0 = 32,
188 AW_R40_GIC_SPI_MMC1 = 33,
189 AW_R40_GIC_SPI_MMC2 = 34,
190 AW_R40_GIC_SPI_MMC3 = 35,
191 AW_R40_GIC_SPI_EMAC = 55,
192 AW_R40_GIC_SPI_AHCI = 56,
193 AW_R40_GIC_SPI_OHCI1 = 64,
194 AW_R40_GIC_SPI_OHCI2 = 65,
195 AW_R40_GIC_SPI_EHCI1 = 76,
196 AW_R40_GIC_SPI_EHCI2 = 78,
197 AW_R40_GIC_SPI_GMAC = 85,
198 };
199
200 /* Allwinner R40 general constants */
201 enum {
202 AW_R40_GIC_NUM_SPI = 128
203 };
204
205 #define BOOT0_MAGIC "eGON.BT0"
206
207 /* The low 8-bits of the 'boot_media' field in the SPL header */
208 #define SUNXI_BOOTED_FROM_MMC0 0
209 #define SUNXI_BOOTED_FROM_NAND 1
210 #define SUNXI_BOOTED_FROM_MMC2 2
211 #define SUNXI_BOOTED_FROM_SPI 3
212
213 struct boot_file_head {
214 uint32_t b_instruction;
215 uint8_t magic[8];
216 uint32_t check_sum;
217 uint32_t length;
218 uint32_t pub_head_size;
219 uint32_t fel_script_address;
220 uint32_t fel_uEnv_length;
221 uint32_t dt_name_offset;
222 uint32_t dram_size;
223 uint32_t boot_media;
224 uint32_t string_pool[13];
225 };
226
227 bool allwinner_r40_bootrom_setup(AwR40State *s, BlockBackend *blk, int unit)
228 {
229 const int64_t rom_size = 32 * KiB;
230 g_autofree uint8_t *buffer = g_new0(uint8_t, rom_size);
231 struct boot_file_head *head = (struct boot_file_head *)buffer;
232
233 if (blk_pread(blk, 8 * KiB, rom_size, buffer, 0) < 0) {
234 error_setg(&error_fatal, "%s: failed to read BlockBackend data",
235 __func__);
236 return false;
237 }
238
239 /* we only check the magic string here. */
240 if (memcmp(head->magic, BOOT0_MAGIC, sizeof(head->magic))) {
241 return false;
242 }
243
244 /*
245 * Simulate the behavior of the bootROM, it will change the boot_media
246 * flag to indicate where the chip is booting from. R40 can boot from
247 * mmc0 or mmc2, the default value of boot_media is zero
248 * (SUNXI_BOOTED_FROM_MMC0), let's fix this flag when it is booting from
249 * the others.
250 */
251 if (unit == 2) {
252 head->boot_media = cpu_to_le32(SUNXI_BOOTED_FROM_MMC2);
253 } else {
254 head->boot_media = cpu_to_le32(SUNXI_BOOTED_FROM_MMC0);
255 }
256
257 rom_add_blob("allwinner-r40.bootrom", buffer, rom_size,
258 rom_size, s->memmap[AW_R40_DEV_SRAM_A1],
259 NULL, NULL, NULL, NULL, false);
260 return true;
261 }
262
263 static void allwinner_r40_init(Object *obj)
264 {
265 static const char *mmc_names[AW_R40_NUM_MMCS] = {
266 "mmc0", "mmc1", "mmc2", "mmc3"
267 };
268 AwR40State *s = AW_R40(obj);
269
270 s->memmap = allwinner_r40_memmap;
271
272 for (int i = 0; i < AW_R40_NUM_CPUS; i++) {
273 object_initialize_child(obj, "cpu[*]", &s->cpus[i],
274 ARM_CPU_TYPE_NAME("cortex-a7"));
275 }
276
277 object_initialize_child(obj, "gic", &s->gic, TYPE_ARM_GIC);
278
279 object_initialize_child(obj, "timer", &s->timer, TYPE_AW_A10_PIT);
280 object_property_add_alias(obj, "clk0-freq", OBJECT(&s->timer),
281 "clk0-freq");
282 object_property_add_alias(obj, "clk1-freq", OBJECT(&s->timer),
283 "clk1-freq");
284
285 object_initialize_child(obj, "wdt", &s->wdt, TYPE_AW_WDT_SUN4I);
286
287 object_initialize_child(obj, "ccu", &s->ccu, TYPE_AW_R40_CCU);
288
289 for (int i = 0; i < AW_R40_NUM_MMCS; i++) {
290 object_initialize_child(obj, mmc_names[i], &s->mmc[i],
291 TYPE_AW_SDHOST_SUN50I_A64);
292 }
293
294 object_initialize_child(obj, "sata", &s->sata, TYPE_ALLWINNER_AHCI);
295
296 for (size_t i = 0; i < AW_R40_NUM_USB; i++) {
297 object_initialize_child(obj, "ehci[*]", &s->ehci[i],
298 TYPE_PLATFORM_EHCI);
299 object_initialize_child(obj, "ohci[*]", &s->ohci[i],
300 TYPE_SYSBUS_OHCI);
301 }
302
303 object_initialize_child(obj, "twi0", &s->i2c0, TYPE_AW_I2C_SUN6I);
304
305 object_initialize_child(obj, "emac", &s->emac, TYPE_AW_EMAC);
306 object_initialize_child(obj, "gmac", &s->gmac, TYPE_AW_SUN8I_EMAC);
307 object_property_add_alias(obj, "gmac-phy-addr",
308 OBJECT(&s->gmac), "phy-addr");
309
310 object_initialize_child(obj, "dramc", &s->dramc, TYPE_AW_R40_DRAMC);
311 object_property_add_alias(obj, "ram-addr", OBJECT(&s->dramc),
312 "ram-addr");
313 object_property_add_alias(obj, "ram-size", OBJECT(&s->dramc),
314 "ram-size");
315
316 object_initialize_child(obj, "sramc", &s->sramc, TYPE_AW_SRAMC_SUN8I_R40);
317 }
318
319 static void allwinner_r40_realize(DeviceState *dev, Error **errp)
320 {
321 AwR40State *s = AW_R40(dev);
322
323 /* CPUs */
324 for (unsigned i = 0; i < AW_R40_NUM_CPUS; i++) {
325
326 /*
327 * Disable secondary CPUs. Guest EL3 firmware will start
328 * them via CPU reset control registers.
329 */
330 qdev_prop_set_bit(DEVICE(&s->cpus[i]), "start-powered-off",
331 i > 0);
332
333 /* All exception levels required */
334 qdev_prop_set_bit(DEVICE(&s->cpus[i]), "has_el3", true);
335 qdev_prop_set_bit(DEVICE(&s->cpus[i]), "has_el2", true);
336
337 /* Mark realized */
338 qdev_realize(DEVICE(&s->cpus[i]), NULL, &error_fatal);
339 }
340
341 /* Generic Interrupt Controller */
342 qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", AW_R40_GIC_NUM_SPI +
343 GIC_INTERNAL);
344 qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2);
345 qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", AW_R40_NUM_CPUS);
346 qdev_prop_set_bit(DEVICE(&s->gic), "has-security-extensions", false);
347 qdev_prop_set_bit(DEVICE(&s->gic), "has-virtualization-extensions", true);
348 sysbus_realize(SYS_BUS_DEVICE(&s->gic), &error_fatal);
349
350 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 0, s->memmap[AW_R40_DEV_GIC_DIST]);
351 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 1, s->memmap[AW_R40_DEV_GIC_CPU]);
352 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 2, s->memmap[AW_R40_DEV_GIC_HYP]);
353 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 3, s->memmap[AW_R40_DEV_GIC_VCPU]);
354
355 /*
356 * Wire the outputs from each CPU's generic timer and the GICv2
357 * maintenance interrupt signal to the appropriate GIC PPI inputs,
358 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs.
359 */
360 for (unsigned i = 0; i < AW_R40_NUM_CPUS; i++) {
361 DeviceState *cpudev = DEVICE(&s->cpus[i]);
362 int ppibase = AW_R40_GIC_NUM_SPI + i * GIC_INTERNAL + GIC_NR_SGIS;
363 int irq;
364 /*
365 * Mapping from the output timer irq lines from the CPU to the
366 * GIC PPI inputs used for this board.
367 */
368 const int timer_irq[] = {
369 [GTIMER_PHYS] = AW_R40_GIC_PPI_PHYSTIMER,
370 [GTIMER_VIRT] = AW_R40_GIC_PPI_VIRTTIMER,
371 [GTIMER_HYP] = AW_R40_GIC_PPI_HYPTIMER,
372 [GTIMER_SEC] = AW_R40_GIC_PPI_SECTIMER,
373 };
374
375 /* Connect CPU timer outputs to GIC PPI inputs */
376 for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
377 qdev_connect_gpio_out(cpudev, irq,
378 qdev_get_gpio_in(DEVICE(&s->gic),
379 ppibase + timer_irq[irq]));
380 }
381
382 /* Connect GIC outputs to CPU interrupt inputs */
383 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i,
384 qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
385 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + AW_R40_NUM_CPUS,
386 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
387 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + (2 * AW_R40_NUM_CPUS),
388 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
389 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + (3 * AW_R40_NUM_CPUS),
390 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
391
392 /* GIC maintenance signal */
393 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + (4 * AW_R40_NUM_CPUS),
394 qdev_get_gpio_in(DEVICE(&s->gic),
395 ppibase + AW_R40_GIC_PPI_MAINT));
396 }
397
398 /* Timer */
399 sysbus_realize(SYS_BUS_DEVICE(&s->timer), &error_fatal);
400 sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer), 0, s->memmap[AW_R40_DEV_PIT]);
401 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer), 0,
402 qdev_get_gpio_in(DEVICE(&s->gic),
403 AW_R40_GIC_SPI_TIMER0));
404 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer), 1,
405 qdev_get_gpio_in(DEVICE(&s->gic),
406 AW_R40_GIC_SPI_TIMER1));
407
408 /* SRAM */
409 sysbus_realize(SYS_BUS_DEVICE(&s->sramc), &error_fatal);
410 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sramc), 0, s->memmap[AW_R40_DEV_SRAMC]);
411
412 memory_region_init_ram(&s->sram_a1, OBJECT(dev), "sram A1",
413 16 * KiB, &error_abort);
414 memory_region_init_ram(&s->sram_a2, OBJECT(dev), "sram A2",
415 16 * KiB, &error_abort);
416 memory_region_init_ram(&s->sram_a3, OBJECT(dev), "sram A3",
417 13 * KiB, &error_abort);
418 memory_region_init_ram(&s->sram_a4, OBJECT(dev), "sram A4",
419 3 * KiB, &error_abort);
420 memory_region_add_subregion(get_system_memory(),
421 s->memmap[AW_R40_DEV_SRAM_A1], &s->sram_a1);
422 memory_region_add_subregion(get_system_memory(),
423 s->memmap[AW_R40_DEV_SRAM_A2], &s->sram_a2);
424 memory_region_add_subregion(get_system_memory(),
425 s->memmap[AW_R40_DEV_SRAM_A3], &s->sram_a3);
426 memory_region_add_subregion(get_system_memory(),
427 s->memmap[AW_R40_DEV_SRAM_A4], &s->sram_a4);
428
429 /* Clock Control Unit */
430 sysbus_realize(SYS_BUS_DEVICE(&s->ccu), &error_fatal);
431 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccu), 0, s->memmap[AW_R40_DEV_CCU]);
432
433 /* SATA / AHCI */
434 sysbus_realize(SYS_BUS_DEVICE(&s->sata), &error_fatal);
435 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0,
436 allwinner_r40_memmap[AW_R40_DEV_AHCI]);
437 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0,
438 qdev_get_gpio_in(DEVICE(&s->gic), AW_R40_GIC_SPI_AHCI));
439
440 /* USB */
441 for (size_t i = 0; i < AW_R40_NUM_USB; i++) {
442 g_autofree char *bus = g_strdup_printf("usb-bus.%zu", i);
443
444 object_property_set_bool(OBJECT(&s->ehci[i]), "companion-enable", true,
445 &error_fatal);
446 sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), &error_fatal);
447 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci[i]), 0,
448 allwinner_r40_memmap[i ? AW_R40_DEV_EHCI2
449 : AW_R40_DEV_EHCI1]);
450 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0,
451 qdev_get_gpio_in(DEVICE(&s->gic),
452 i ? AW_R40_GIC_SPI_EHCI2
453 : AW_R40_GIC_SPI_EHCI1));
454
455 object_property_set_str(OBJECT(&s->ohci[i]), "masterbus", bus,
456 &error_fatal);
457 sysbus_realize(SYS_BUS_DEVICE(&s->ohci[i]), &error_fatal);
458 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ohci[i]), 0,
459 allwinner_r40_memmap[i ? AW_R40_DEV_OHCI2
460 : AW_R40_DEV_OHCI1]);
461 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ohci[i]), 0,
462 qdev_get_gpio_in(DEVICE(&s->gic),
463 i ? AW_R40_GIC_SPI_OHCI2
464 : AW_R40_GIC_SPI_OHCI1));
465 }
466
467 /* SD/MMC */
468 for (int i = 0; i < AW_R40_NUM_MMCS; i++) {
469 qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->gic),
470 AW_R40_GIC_SPI_MMC0 + i);
471 const hwaddr addr = s->memmap[AW_R40_DEV_MMC0 + i];
472
473 object_property_set_link(OBJECT(&s->mmc[i]), "dma-memory",
474 OBJECT(get_system_memory()), &error_fatal);
475 sysbus_realize(SYS_BUS_DEVICE(&s->mmc[i]), &error_fatal);
476 sysbus_mmio_map(SYS_BUS_DEVICE(&s->mmc[i]), 0, addr);
477 sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc[i]), 0, irq);
478 }
479
480 /* UART0. For future clocktree API: All UARTS are connected to APB2_CLK. */
481 for (int i = 0; i < AW_R40_NUM_UARTS; i++) {
482 static const int uart_irqs[AW_R40_NUM_UARTS] = {
483 AW_R40_GIC_SPI_UART0,
484 AW_R40_GIC_SPI_UART1,
485 AW_R40_GIC_SPI_UART2,
486 AW_R40_GIC_SPI_UART3,
487 AW_R40_GIC_SPI_UART4,
488 AW_R40_GIC_SPI_UART5,
489 AW_R40_GIC_SPI_UART6,
490 AW_R40_GIC_SPI_UART7,
491 };
492 const hwaddr addr = s->memmap[AW_R40_DEV_UART0 + i];
493
494 serial_mm_init(get_system_memory(), addr, 2,
495 qdev_get_gpio_in(DEVICE(&s->gic), uart_irqs[i]),
496 115200, serial_hd(i), DEVICE_NATIVE_ENDIAN);
497 }
498
499 /* I2C */
500 sysbus_realize(SYS_BUS_DEVICE(&s->i2c0), &error_fatal);
501 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c0), 0, s->memmap[AW_R40_DEV_TWI0]);
502 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c0), 0,
503 qdev_get_gpio_in(DEVICE(&s->gic), AW_R40_GIC_SPI_TWI0));
504
505 /* DRAMC */
506 sysbus_realize(SYS_BUS_DEVICE(&s->dramc), &error_fatal);
507 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 0,
508 s->memmap[AW_R40_DEV_DRAMCOM]);
509 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 1,
510 s->memmap[AW_R40_DEV_DRAMCTL]);
511 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 2,
512 s->memmap[AW_R40_DEV_DRAMPHY]);
513
514 /* GMAC */
515 qemu_configure_nic_device(DEVICE(&s->gmac), true, "gmac");
516 object_property_set_link(OBJECT(&s->gmac), "dma-memory",
517 OBJECT(get_system_memory()), &error_fatal);
518 sysbus_realize(SYS_BUS_DEVICE(&s->gmac), &error_fatal);
519 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gmac), 0, s->memmap[AW_R40_DEV_GMAC]);
520 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gmac), 0,
521 qdev_get_gpio_in(DEVICE(&s->gic), AW_R40_GIC_SPI_GMAC));
522
523 /* EMAC */
524 qemu_configure_nic_device(DEVICE(&s->emac), true, "emac");
525 sysbus_realize(SYS_BUS_DEVICE(&s->emac), &error_fatal);
526 sysbus_mmio_map(SYS_BUS_DEVICE(&s->emac), 0, s->memmap[AW_R40_DEV_EMAC]);
527 sysbus_connect_irq(SYS_BUS_DEVICE(&s->emac), 0,
528 qdev_get_gpio_in(DEVICE(&s->gic), AW_R40_GIC_SPI_EMAC));
529
530 /* WDT */
531 sysbus_realize(SYS_BUS_DEVICE(&s->wdt), &error_fatal);
532 sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->wdt), 0,
533 allwinner_r40_memmap[AW_R40_DEV_WDT], 1);
534
535 /* Unimplemented devices */
536 for (unsigned i = 0; i < ARRAY_SIZE(r40_unimplemented); i++) {
537 create_unimplemented_device(r40_unimplemented[i].device_name,
538 r40_unimplemented[i].base,
539 r40_unimplemented[i].size);
540 }
541 }
542
543 static void allwinner_r40_class_init(ObjectClass *oc, void *data)
544 {
545 DeviceClass *dc = DEVICE_CLASS(oc);
546
547 dc->realize = allwinner_r40_realize;
548 /* Reason: uses serial_hd() in realize function */
549 dc->user_creatable = false;
550 }
551
552 static const TypeInfo allwinner_r40_type_info = {
553 .name = TYPE_AW_R40,
554 .parent = TYPE_DEVICE,
555 .instance_size = sizeof(AwR40State),
556 .instance_init = allwinner_r40_init,
557 .class_init = allwinner_r40_class_init,
558 };
559
560 static void allwinner_r40_register_types(void)
561 {
562 type_register_static(&allwinner_r40_type_info);
563 }
564
565 type_init(allwinner_r40_register_types)
armbru's QEMU hackery