2 * RISC-V translation routines for the RV64M Standard Extension.
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
6 * Bastian Koppelmann, kbastian@mail.uni-paderborn.de
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2 or later, as published by the Free Software Foundation.
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License along with
18 * this program. If not, see <http://www.gnu.org/licenses/>.
21 #define REQUIRE_M_OR_ZMMUL(ctx) do { \
22 if (!ctx->cfg_ptr->ext_zmmul && !has_ext(ctx, RVM)) { \
27 static void gen_mulhu_i128(TCGv r2, TCGv r3, TCGv al, TCGv ah, TCGv bl, TCGv bh)
29 TCGv tmpl = tcg_temp_new();
30 TCGv tmph = tcg_temp_new();
31 TCGv r0 = tcg_temp_new();
32 TCGv r1 = tcg_temp_new();
33 TCGv zero = tcg_constant_tl(0);
35 tcg_gen_mulu2_tl(r0, r1, al, bl);
37 tcg_gen_mulu2_tl(tmpl, tmph, al, bh);
38 tcg_gen_add2_tl(r1, r2, r1, zero, tmpl, tmph);
39 tcg_gen_mulu2_tl(tmpl, tmph, ah, bl);
40 tcg_gen_add2_tl(r1, tmph, r1, r2, tmpl, tmph);
41 /* Overflow detection into r3 */
42 tcg_gen_setcond_tl(TCG_COND_LTU, r3, tmph, r2);
44 tcg_gen_mov_tl(r2, tmph);
46 tcg_gen_mulu2_tl(tmpl, tmph, ah, bh);
47 tcg_gen_add2_tl(r2, r3, r2, r3, tmpl, tmph);
50 static void gen_mul_i128(TCGv rl, TCGv rh,
51 TCGv rs1l, TCGv rs1h, TCGv rs2l, TCGv rs2h)
53 TCGv tmpl = tcg_temp_new();
54 TCGv tmph = tcg_temp_new();
55 TCGv tmpx = tcg_temp_new();
56 TCGv zero = tcg_constant_tl(0);
58 tcg_gen_mulu2_tl(rl, rh, rs1l, rs2l);
59 tcg_gen_mulu2_tl(tmpl, tmph, rs1l, rs2h);
60 tcg_gen_add2_tl(rh, tmpx, rh, zero, tmpl, tmph);
61 tcg_gen_mulu2_tl(tmpl, tmph, rs1h, rs2l);
62 tcg_gen_add2_tl(rh, tmph, rh, tmpx, tmpl, tmph);
65 static bool trans_mul(DisasContext *ctx, arg_mul *a)
67 REQUIRE_M_OR_ZMMUL(ctx);
68 return gen_arith(ctx, a, EXT_NONE, tcg_gen_mul_tl, gen_mul_i128);
71 static void gen_mulh_i128(TCGv rl, TCGv rh,
72 TCGv rs1l, TCGv rs1h, TCGv rs2l, TCGv rs2h)
74 TCGv t0l = tcg_temp_new();
75 TCGv t0h = tcg_temp_new();
76 TCGv t1l = tcg_temp_new();
77 TCGv t1h = tcg_temp_new();
79 gen_mulhu_i128(rl, rh, rs1l, rs1h, rs2l, rs2h);
80 tcg_gen_sari_tl(t0h, rs1h, 63);
81 tcg_gen_and_tl(t0l, t0h, rs2l);
82 tcg_gen_and_tl(t0h, t0h, rs2h);
83 tcg_gen_sari_tl(t1h, rs2h, 63);
84 tcg_gen_and_tl(t1l, t1h, rs1l);
85 tcg_gen_and_tl(t1h, t1h, rs1h);
86 tcg_gen_sub2_tl(t0l, t0h, rl, rh, t0l, t0h);
87 tcg_gen_sub2_tl(rl, rh, t0l, t0h, t1l, t1h);
90 static void gen_mulh(TCGv ret, TCGv s1, TCGv s2)
92 TCGv discard = tcg_temp_new();
94 tcg_gen_muls2_tl(discard, ret, s1, s2);
97 static void gen_mulh_w(TCGv ret, TCGv s1, TCGv s2)
99 tcg_gen_mul_tl(ret, s1, s2);
100 tcg_gen_sari_tl(ret, ret, 32);
103 static bool trans_mulh(DisasContext *ctx, arg_mulh *a)
105 REQUIRE_M_OR_ZMMUL(ctx);
106 return gen_arith_per_ol(ctx, a, EXT_SIGN, gen_mulh, gen_mulh_w,
110 static void gen_mulhsu_i128(TCGv rl, TCGv rh,
111 TCGv rs1l, TCGv rs1h, TCGv rs2l, TCGv rs2h)
114 TCGv t0l = tcg_temp_new();
115 TCGv t0h = tcg_temp_new();
117 gen_mulhu_i128(rl, rh, rs1l, rs1h, rs2l, rs2h);
118 tcg_gen_sari_tl(t0h, rs1h, 63);
119 tcg_gen_and_tl(t0l, t0h, rs2l);
120 tcg_gen_and_tl(t0h, t0h, rs2h);
121 tcg_gen_sub2_tl(rl, rh, rl, rh, t0l, t0h);
124 static void gen_mulhsu(TCGv ret, TCGv arg1, TCGv arg2)
126 TCGv rl = tcg_temp_new();
127 TCGv rh = tcg_temp_new();
129 tcg_gen_mulu2_tl(rl, rh, arg1, arg2);
130 /* fix up for one negative */
131 tcg_gen_sari_tl(rl, arg1, TARGET_LONG_BITS - 1);
132 tcg_gen_and_tl(rl, rl, arg2);
133 tcg_gen_sub_tl(ret, rh, rl);
136 static void gen_mulhsu_w(TCGv ret, TCGv arg1, TCGv arg2)
138 TCGv t1 = tcg_temp_new();
139 TCGv t2 = tcg_temp_new();
141 tcg_gen_ext32s_tl(t1, arg1);
142 tcg_gen_ext32u_tl(t2, arg2);
143 tcg_gen_mul_tl(ret, t1, t2);
144 tcg_gen_sari_tl(ret, ret, 32);
147 static bool trans_mulhsu(DisasContext *ctx, arg_mulhsu *a)
149 REQUIRE_M_OR_ZMMUL(ctx);
150 return gen_arith_per_ol(ctx, a, EXT_NONE, gen_mulhsu, gen_mulhsu_w,
154 static void gen_mulhu(TCGv ret, TCGv s1, TCGv s2)
156 TCGv discard = tcg_temp_new();
158 tcg_gen_mulu2_tl(discard, ret, s1, s2);
161 static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a)
163 REQUIRE_M_OR_ZMMUL(ctx);
164 /* gen_mulh_w works for either sign as input. */
165 return gen_arith_per_ol(ctx, a, EXT_ZERO, gen_mulhu, gen_mulh_w,
169 static void gen_div_i128(TCGv rdl, TCGv rdh,
170 TCGv rs1l, TCGv rs1h, TCGv rs2l, TCGv rs2h)
172 gen_helper_divs_i128(rdl, tcg_env, rs1l, rs1h, rs2l, rs2h);
173 tcg_gen_ld_tl(rdh, tcg_env, offsetof(CPURISCVState, retxh));
176 static void gen_div(TCGv ret, TCGv source1, TCGv source2)
178 TCGv temp1, temp2, zero, one, mone, min;
180 temp1 = tcg_temp_new();
181 temp2 = tcg_temp_new();
182 zero = tcg_constant_tl(0);
183 one = tcg_constant_tl(1);
184 mone = tcg_constant_tl(-1);
185 min = tcg_constant_tl(1ull << (TARGET_LONG_BITS - 1));
188 * If overflow, set temp2 to 1, else source2.
189 * This produces the required result of min.
191 tcg_gen_setcond_tl(TCG_COND_EQ, temp1, source1, min);
192 tcg_gen_setcond_tl(TCG_COND_EQ, temp2, source2, mone);
193 tcg_gen_and_tl(temp1, temp1, temp2);
194 tcg_gen_movcond_tl(TCG_COND_NE, temp2, temp1, zero, one, source2);
197 * If div by zero, set temp1 to -1 and temp2 to 1 to
198 * produce the required result of -1.
200 tcg_gen_movcond_tl(TCG_COND_EQ, temp1, source2, zero, mone, source1);
201 tcg_gen_movcond_tl(TCG_COND_EQ, temp2, source2, zero, one, temp2);
203 tcg_gen_div_tl(ret, temp1, temp2);
206 static bool trans_div(DisasContext *ctx, arg_div *a)
208 REQUIRE_EXT(ctx, RVM);
209 return gen_arith(ctx, a, EXT_SIGN, gen_div, gen_div_i128);
212 static void gen_divu_i128(TCGv rdl, TCGv rdh,
213 TCGv rs1l, TCGv rs1h, TCGv rs2l, TCGv rs2h)
215 gen_helper_divu_i128(rdl, tcg_env, rs1l, rs1h, rs2l, rs2h);
216 tcg_gen_ld_tl(rdh, tcg_env, offsetof(CPURISCVState, retxh));
219 static void gen_divu(TCGv ret, TCGv source1, TCGv source2)
221 TCGv temp1, temp2, zero, one, max;
223 temp1 = tcg_temp_new();
224 temp2 = tcg_temp_new();
225 zero = tcg_constant_tl(0);
226 one = tcg_constant_tl(1);
227 max = tcg_constant_tl(~0);
230 * If div by zero, set temp1 to max and temp2 to 1 to
231 * produce the required result of max.
233 tcg_gen_movcond_tl(TCG_COND_EQ, temp1, source2, zero, max, source1);
234 tcg_gen_movcond_tl(TCG_COND_EQ, temp2, source2, zero, one, source2);
235 tcg_gen_divu_tl(ret, temp1, temp2);
238 static bool trans_divu(DisasContext *ctx, arg_divu *a)
240 REQUIRE_EXT(ctx, RVM);
241 return gen_arith(ctx, a, EXT_ZERO, gen_divu, gen_divu_i128);
244 static void gen_rem_i128(TCGv rdl, TCGv rdh,
245 TCGv rs1l, TCGv rs1h, TCGv rs2l, TCGv rs2h)
247 gen_helper_rems_i128(rdl, tcg_env, rs1l, rs1h, rs2l, rs2h);
248 tcg_gen_ld_tl(rdh, tcg_env, offsetof(CPURISCVState, retxh));
251 static void gen_rem(TCGv ret, TCGv source1, TCGv source2)
253 TCGv temp1, temp2, zero, one, mone, min;
255 temp1 = tcg_temp_new();
256 temp2 = tcg_temp_new();
257 zero = tcg_constant_tl(0);
258 one = tcg_constant_tl(1);
259 mone = tcg_constant_tl(-1);
260 min = tcg_constant_tl(1ull << (TARGET_LONG_BITS - 1));
263 * If overflow, set temp1 to 0, else source1.
264 * This avoids a possible host trap, and produces the required result of 0.
266 tcg_gen_setcond_tl(TCG_COND_EQ, temp1, source1, min);
267 tcg_gen_setcond_tl(TCG_COND_EQ, temp2, source2, mone);
268 tcg_gen_and_tl(temp1, temp1, temp2);
269 tcg_gen_movcond_tl(TCG_COND_NE, temp1, temp1, zero, zero, source1);
272 * If div by zero, set temp2 to 1, else source2.
273 * This avoids a possible host trap, but produces an incorrect result.
275 tcg_gen_movcond_tl(TCG_COND_EQ, temp2, source2, zero, one, source2);
277 tcg_gen_rem_tl(temp1, temp1, temp2);
279 /* If div by zero, the required result is the original dividend. */
280 tcg_gen_movcond_tl(TCG_COND_EQ, ret, source2, zero, source1, temp1);
283 static bool trans_rem(DisasContext *ctx, arg_rem *a)
285 REQUIRE_EXT(ctx, RVM);
286 return gen_arith(ctx, a, EXT_SIGN, gen_rem, gen_rem_i128);
289 static void gen_remu_i128(TCGv rdl, TCGv rdh,
290 TCGv rs1l, TCGv rs1h, TCGv rs2l, TCGv rs2h)
292 gen_helper_remu_i128(rdl, tcg_env, rs1l, rs1h, rs2l, rs2h);
293 tcg_gen_ld_tl(rdh, tcg_env, offsetof(CPURISCVState, retxh));
296 static void gen_remu(TCGv ret, TCGv source1, TCGv source2)
298 TCGv temp, zero, one;
300 temp = tcg_temp_new();
301 zero = tcg_constant_tl(0);
302 one = tcg_constant_tl(1);
305 * If div by zero, set temp to 1, else source2.
306 * This avoids a possible host trap, but produces an incorrect result.
308 tcg_gen_movcond_tl(TCG_COND_EQ, temp, source2, zero, one, source2);
310 tcg_gen_remu_tl(temp, source1, temp);
312 /* If div by zero, the required result is the original dividend. */
313 tcg_gen_movcond_tl(TCG_COND_EQ, ret, source2, zero, source1, temp);
316 static bool trans_remu(DisasContext *ctx, arg_remu *a)
318 REQUIRE_EXT(ctx, RVM);
319 return gen_arith(ctx, a, EXT_ZERO, gen_remu, gen_remu_i128);
322 static bool trans_mulw(DisasContext *ctx, arg_mulw *a)
324 REQUIRE_64_OR_128BIT(ctx);
325 REQUIRE_M_OR_ZMMUL(ctx);
327 return gen_arith(ctx, a, EXT_NONE, tcg_gen_mul_tl, NULL);
330 static bool trans_divw(DisasContext *ctx, arg_divw *a)
332 REQUIRE_64_OR_128BIT(ctx);
333 REQUIRE_EXT(ctx, RVM);
335 return gen_arith(ctx, a, EXT_SIGN, gen_div, NULL);
338 static bool trans_divuw(DisasContext *ctx, arg_divuw *a)
340 REQUIRE_64_OR_128BIT(ctx);
341 REQUIRE_EXT(ctx, RVM);
343 return gen_arith(ctx, a, EXT_ZERO, gen_divu, NULL);
346 static bool trans_remw(DisasContext *ctx, arg_remw *a)
348 REQUIRE_64_OR_128BIT(ctx);
349 REQUIRE_EXT(ctx, RVM);
351 return gen_arith(ctx, a, EXT_SIGN, gen_rem, NULL);
354 static bool trans_remuw(DisasContext *ctx, arg_remuw *a)
356 REQUIRE_64_OR_128BIT(ctx);
357 REQUIRE_EXT(ctx, RVM);
359 return gen_arith(ctx, a, EXT_ZERO, gen_remu, NULL);
362 static bool trans_muld(DisasContext *ctx, arg_muld *a)
365 REQUIRE_M_OR_ZMMUL(ctx);
367 return gen_arith(ctx, a, EXT_SIGN, tcg_gen_mul_tl, NULL);
370 static bool trans_divd(DisasContext *ctx, arg_divd *a)
373 REQUIRE_EXT(ctx, RVM);
375 return gen_arith(ctx, a, EXT_SIGN, gen_div, NULL);
378 static bool trans_divud(DisasContext *ctx, arg_divud *a)
381 REQUIRE_EXT(ctx, RVM);
383 return gen_arith(ctx, a, EXT_ZERO, gen_divu, NULL);
386 static bool trans_remd(DisasContext *ctx, arg_remd *a)
389 REQUIRE_EXT(ctx, RVM);
391 return gen_arith(ctx, a, EXT_SIGN, gen_rem, NULL);
394 static bool trans_remud(DisasContext *ctx, arg_remud *a)
397 REQUIRE_EXT(ctx, RVM);
399 return gen_arith(ctx, a, EXT_ZERO, gen_remu, NULL);