2 * QEMU Malta board support
4 * Copyright (c) 2006 Aurelien Jarno
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "qemu/osdep.h"
26 #include "qemu/units.h"
27 #include "qemu/bitops.h"
28 #include "qemu-common.h"
29 #include "qemu/datadir.h"
32 #include "hw/southbridge/piix.h"
33 #include "hw/isa/superio.h"
34 #include "hw/char/serial.h"
36 #include "hw/boards.h"
37 #include "hw/i2c/smbus_eeprom.h"
38 #include "hw/block/flash.h"
39 #include "hw/mips/mips.h"
40 #include "hw/mips/cpudevs.h"
41 #include "hw/pci/pci.h"
42 #include "sysemu/sysemu.h"
43 #include "sysemu/arch_init.h"
45 #include "hw/mips/bios.h"
48 #include "hw/loader.h"
50 #include "exec/address-spaces.h"
51 #include "qom/object.h"
52 #include "hw/sysbus.h" /* SysBusDevice */
53 #include "qemu/host-utils.h"
54 #include "sysemu/qtest.h"
55 #include "sysemu/reset.h"
56 #include "sysemu/runstate.h"
57 #include "qapi/error.h"
58 #include "qemu/error-report.h"
59 #include "hw/misc/empty_slot.h"
60 #include "sysemu/kvm.h"
61 #include "hw/semihosting/semihost.h"
62 #include "hw/mips/cps.h"
63 #include "hw/qdev-clock.h"
65 #define ENVP_ADDR 0x80002000l
66 #define ENVP_NB_ENTRIES 16
67 #define ENVP_ENTRY_SIZE 256
69 /* Hardware addresses */
70 #define FLASH_ADDRESS 0x1e000000ULL
71 #define FPGA_ADDRESS 0x1f000000ULL
72 #define RESET_ADDRESS 0x1fc00000ULL
74 #define FLASH_SIZE 0x400000
80 MemoryRegion iomem_lo
; /* 0 - 0x900 */
81 MemoryRegion iomem_hi
; /* 0xa00 - 0x100000 */
95 #define TYPE_MIPS_MALTA "mips-malta"
96 OBJECT_DECLARE_SIMPLE_TYPE(MaltaState
, MIPS_MALTA
)
99 SysBusDevice parent_obj
;
103 qemu_irq i8259
[ISA_NUM_IRQS
];
106 static struct _loaderparams
{
107 int ram_size
, ram_low_size
;
108 const char *kernel_filename
;
109 const char *kernel_cmdline
;
110 const char *initrd_filename
;
114 static void malta_fpga_update_display(void *opaque
)
118 MaltaFPGAState
*s
= opaque
;
120 for (i
= 7 ; i
>= 0 ; i
--) {
121 if (s
->leds
& (1 << i
)) {
129 qemu_chr_fe_printf(&s
->display
, "\e[H\n\n|\e[32m%-8.8s\e[00m|\r\n",
131 qemu_chr_fe_printf(&s
->display
, "\n\n\n\n|\e[31m%-8.8s\e[00m|",
136 * EEPROM 24C01 / 24C02 emulation.
138 * Emulation for serial EEPROMs:
139 * 24C01 - 1024 bit (128 x 8)
140 * 24C02 - 2048 bit (256 x 8)
142 * Typical device names include Microchip 24C02SC or SGS Thomson ST24C02.
146 # define logout(fmt, ...) \
147 fprintf(stderr, "MALTA\t%-24s" fmt, __func__, ## __VA_ARGS__)
149 # define logout(fmt, ...) ((void)0)
152 struct _eeprom24c0x_t
{
161 uint8_t contents
[256];
164 typedef struct _eeprom24c0x_t eeprom24c0x_t
;
166 static eeprom24c0x_t spd_eeprom
= {
169 0x80, 0x08, 0xFF, 0x0D, 0x0A, 0xFF, 0x40, 0x00,
171 0x01, 0x75, 0x54, 0x00, 0x82, 0x08, 0x00, 0x01,
173 0x8F, 0x04, 0x02, 0x01, 0x01, 0x00, 0x00, 0x00,
175 0x00, 0x00, 0x00, 0x14, 0x0F, 0x14, 0x2D, 0xFF,
177 0x15, 0x08, 0x15, 0x08, 0x00, 0x00, 0x00, 0x00,
179 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
181 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
183 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x12, 0xD0,
185 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
187 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
189 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
191 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
193 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
195 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
197 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
199 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x64, 0xF4,
203 static void generate_eeprom_spd(uint8_t *eeprom
, ram_addr_t ram_size
)
205 enum { SDR
= 0x4, DDR2
= 0x8 } type
;
206 uint8_t *spd
= spd_eeprom
.contents
;
208 uint16_t density
= 0;
211 /* work in terms of MB */
214 while ((ram_size
>= 4) && (nbanks
<= 2)) {
215 int sz_log2
= MIN(31 - clz32(ram_size
), 14);
217 density
|= 1 << (sz_log2
- 2);
218 ram_size
-= 1 << sz_log2
;
221 /* split to 2 banks if possible */
222 if ((nbanks
== 1) && (density
> 1)) {
227 if (density
& 0xff00) {
228 density
= (density
& 0xe0) | ((density
>> 8) & 0x1f);
230 } else if (!(density
& 0x1f)) {
237 warn_report("SPD cannot represent final " RAM_ADDR_FMT
"MB"
238 " of SDRAM", ram_size
);
241 /* fill in SPD memory information */
248 for (i
= 0; i
< 63; i
++) {
253 memcpy(eeprom
, spd
, sizeof(spd_eeprom
.contents
));
256 static void generate_eeprom_serial(uint8_t *eeprom
)
259 uint8_t mac
[6] = { 0x00 };
260 uint8_t sn
[5] = { 0x01, 0x23, 0x45, 0x67, 0x89 };
263 eeprom
[pos
++] = 0x01;
266 eeprom
[pos
++] = 0x02;
269 eeprom
[pos
++] = 0x01; /* MAC */
270 eeprom
[pos
++] = 0x06; /* length */
271 memcpy(&eeprom
[pos
], mac
, sizeof(mac
));
275 eeprom
[pos
++] = 0x02; /* serial */
276 eeprom
[pos
++] = 0x05; /* length */
277 memcpy(&eeprom
[pos
], sn
, sizeof(sn
));
282 for (i
= 0; i
< pos
; i
++) {
283 eeprom
[pos
] += eeprom
[i
];
287 static uint8_t eeprom24c0x_read(eeprom24c0x_t
*eeprom
)
289 logout("%u: scl = %u, sda = %u, data = 0x%02x\n",
290 eeprom
->tick
, eeprom
->scl
, eeprom
->sda
, eeprom
->data
);
294 static void eeprom24c0x_write(eeprom24c0x_t
*eeprom
, int scl
, int sda
)
296 if (eeprom
->scl
&& scl
&& (eeprom
->sda
!= sda
)) {
297 logout("%u: scl = %u->%u, sda = %u->%u i2c %s\n",
298 eeprom
->tick
, eeprom
->scl
, scl
, eeprom
->sda
, sda
,
299 sda
? "stop" : "start");
304 } else if (eeprom
->tick
== 0 && !eeprom
->ack
) {
305 /* Waiting for start. */
306 logout("%u: scl = %u->%u, sda = %u->%u wait for i2c start\n",
307 eeprom
->tick
, eeprom
->scl
, scl
, eeprom
->sda
, sda
);
308 } else if (!eeprom
->scl
&& scl
) {
309 logout("%u: scl = %u->%u, sda = %u->%u trigger bit\n",
310 eeprom
->tick
, eeprom
->scl
, scl
, eeprom
->sda
, sda
);
312 logout("\ti2c ack bit = 0\n");
315 } else if (eeprom
->sda
== sda
) {
316 uint8_t bit
= (sda
!= 0);
317 logout("\ti2c bit = %d\n", bit
);
318 if (eeprom
->tick
< 9) {
319 eeprom
->command
<<= 1;
320 eeprom
->command
+= bit
;
322 if (eeprom
->tick
== 9) {
323 logout("\tcommand 0x%04x, %s\n", eeprom
->command
,
324 bit
? "read" : "write");
327 } else if (eeprom
->tick
< 17) {
328 if (eeprom
->command
& 1) {
329 sda
= ((eeprom
->data
& 0x80) != 0);
331 eeprom
->address
<<= 1;
332 eeprom
->address
+= bit
;
335 if (eeprom
->tick
== 17) {
336 eeprom
->data
= eeprom
->contents
[eeprom
->address
];
337 logout("\taddress 0x%04x, data 0x%02x\n",
338 eeprom
->address
, eeprom
->data
);
342 } else if (eeprom
->tick
>= 17) {
346 logout("\tsda changed with raising scl\n");
349 logout("%u: scl = %u->%u, sda = %u->%u\n", eeprom
->tick
, eeprom
->scl
,
350 scl
, eeprom
->sda
, sda
);
356 static uint64_t malta_fpga_read(void *opaque
, hwaddr addr
,
359 MaltaFPGAState
*s
= opaque
;
363 saddr
= (addr
& 0xfffff);
367 /* SWITCH Register */
372 /* STATUS Register */
374 #ifdef TARGET_WORDS_BIGENDIAN
386 /* LEDBAR Register */
391 /* BRKRES Register */
396 /* UART Registers are handled directly by the serial device */
403 /* XXX: implement a real I2C controller */
407 /* IN = OUT until a real I2C control is implemented */
415 /* I2CINP Register */
417 val
= ((s
->i2cin
& ~1) | eeprom24c0x_read(&spd_eeprom
));
425 /* I2COUT Register */
430 /* I2CSEL Register */
436 qemu_log_mask(LOG_GUEST_ERROR
,
437 "malta_fpga_read: Bad register addr 0x%"HWADDR_PRIX
"\n",
444 static void malta_fpga_write(void *opaque
, hwaddr addr
,
445 uint64_t val
, unsigned size
)
447 MaltaFPGAState
*s
= opaque
;
450 saddr
= (addr
& 0xfffff);
454 /* SWITCH Register */
462 /* LEDBAR Register */
464 s
->leds
= val
& 0xff;
465 malta_fpga_update_display(s
);
468 /* ASCIIWORD Register */
470 snprintf(s
->display_text
, 9, "%08X", (uint32_t)val
);
471 malta_fpga_update_display(s
);
474 /* ASCIIPOS0 to ASCIIPOS7 Registers */
483 s
->display_text
[(saddr
- 0x00418) >> 3] = (char) val
;
484 malta_fpga_update_display(s
);
487 /* SOFTRES Register */
490 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET
);
494 /* BRKRES Register */
499 /* UART Registers are handled directly by the serial device */
503 s
->gpout
= val
& 0xff;
508 s
->i2coe
= val
& 0x03;
511 /* I2COUT Register */
513 eeprom24c0x_write(&spd_eeprom
, val
& 0x02, val
& 0x01);
517 /* I2CSEL Register */
519 s
->i2csel
= val
& 0x01;
523 qemu_log_mask(LOG_GUEST_ERROR
,
524 "malta_fpga_write: Bad register addr 0x%"HWADDR_PRIX
"\n",
530 static const MemoryRegionOps malta_fpga_ops
= {
531 .read
= malta_fpga_read
,
532 .write
= malta_fpga_write
,
533 .endianness
= DEVICE_NATIVE_ENDIAN
,
536 static void malta_fpga_reset(void *opaque
)
538 MaltaFPGAState
*s
= opaque
;
548 s
->display_text
[8] = '\0';
549 snprintf(s
->display_text
, 9, " ");
552 static void malta_fgpa_display_event(void *opaque
, QEMUChrEvent event
)
554 MaltaFPGAState
*s
= opaque
;
556 if (event
== CHR_EVENT_OPENED
&& !s
->display_inited
) {
557 qemu_chr_fe_printf(&s
->display
, "\e[HMalta LEDBAR\r\n");
558 qemu_chr_fe_printf(&s
->display
, "+--------+\r\n");
559 qemu_chr_fe_printf(&s
->display
, "+ +\r\n");
560 qemu_chr_fe_printf(&s
->display
, "+--------+\r\n");
561 qemu_chr_fe_printf(&s
->display
, "\n");
562 qemu_chr_fe_printf(&s
->display
, "Malta ASCII\r\n");
563 qemu_chr_fe_printf(&s
->display
, "+--------+\r\n");
564 qemu_chr_fe_printf(&s
->display
, "+ +\r\n");
565 qemu_chr_fe_printf(&s
->display
, "+--------+\r\n");
566 s
->display_inited
= true;
570 static MaltaFPGAState
*malta_fpga_init(MemoryRegion
*address_space
,
571 hwaddr base
, qemu_irq uart_irq
, Chardev
*uart_chr
)
576 s
= g_new0(MaltaFPGAState
, 1);
578 memory_region_init_io(&s
->iomem
, NULL
, &malta_fpga_ops
, s
,
579 "malta-fpga", 0x100000);
580 memory_region_init_alias(&s
->iomem_lo
, NULL
, "malta-fpga",
581 &s
->iomem
, 0, 0x900);
582 memory_region_init_alias(&s
->iomem_hi
, NULL
, "malta-fpga",
583 &s
->iomem
, 0xa00, 0x100000 - 0xa00);
585 memory_region_add_subregion(address_space
, base
, &s
->iomem_lo
);
586 memory_region_add_subregion(address_space
, base
+ 0xa00, &s
->iomem_hi
);
588 chr
= qemu_chr_new("fpga", "vc:320x200", NULL
);
589 qemu_chr_fe_init(&s
->display
, chr
, NULL
);
590 qemu_chr_fe_set_handlers(&s
->display
, NULL
, NULL
,
591 malta_fgpa_display_event
, NULL
, s
, NULL
, true);
593 s
->uart
= serial_mm_init(address_space
, base
+ 0x900, 3, uart_irq
,
594 230400, uart_chr
, DEVICE_NATIVE_ENDIAN
);
597 qemu_register_reset(malta_fpga_reset
, s
);
602 /* Network support */
603 static void network_init(PCIBus
*pci_bus
)
607 for (i
= 0; i
< nb_nics
; i
++) {
608 NICInfo
*nd
= &nd_table
[i
];
609 const char *default_devaddr
= NULL
;
611 if (i
== 0 && (!nd
->model
|| strcmp(nd
->model
, "pcnet") == 0))
612 /* The malta board has a PCNet card using PCI SLOT 11 */
613 default_devaddr
= "0b";
615 pci_nic_init_nofail(nd
, pci_bus
, "pcnet", default_devaddr
);
619 static void write_bootloader_nanomips(uint8_t *base
, int64_t run_addr
,
620 int64_t kernel_entry
)
624 /* Small bootloader */
625 p
= (uint16_t *)base
;
627 #define NM_HI1(VAL) (((VAL) >> 16) & 0x1f)
628 #define NM_HI2(VAL) \
629 (((VAL) & 0xf000) | (((VAL) >> 19) & 0xffc) | (((VAL) >> 31) & 0x1))
630 #define NM_LO(VAL) ((VAL) & 0xfff)
632 stw_p(p
++, 0x2800); stw_p(p
++, 0x001c);
634 stw_p(p
++, 0x8000); stw_p(p
++, 0xc000);
636 stw_p(p
++, 0x8000); stw_p(p
++, 0xc000);
638 stw_p(p
++, 0x8000); stw_p(p
++, 0xc000);
640 stw_p(p
++, 0x8000); stw_p(p
++, 0xc000);
642 stw_p(p
++, 0x8000); stw_p(p
++, 0xc000);
644 stw_p(p
++, 0x8000); stw_p(p
++, 0xc000);
646 stw_p(p
++, 0x8000); stw_p(p
++, 0xc000);
650 if (semihosting_get_argc()) {
651 /* Preserve a0 content as arguments have been passed */
652 stw_p(p
++, 0x8000); stw_p(p
++, 0xc000);
655 stw_p(p
++, 0x0080); stw_p(p
++, 0x0002);
659 stw_p(p
++, 0xe3a0 | NM_HI1(ENVP_ADDR
- 64));
661 stw_p(p
++, NM_HI2(ENVP_ADDR
- 64));
662 /* lui sp,%hi(ENVP_ADDR - 64) */
664 stw_p(p
++, 0x83bd); stw_p(p
++, NM_LO(ENVP_ADDR
- 64));
665 /* ori sp,sp,%lo(ENVP_ADDR - 64) */
667 stw_p(p
++, 0xe0a0 | NM_HI1(ENVP_ADDR
));
669 stw_p(p
++, NM_HI2(ENVP_ADDR
));
670 /* lui a1,%hi(ENVP_ADDR) */
672 stw_p(p
++, 0x80a5); stw_p(p
++, NM_LO(ENVP_ADDR
));
673 /* ori a1,a1,%lo(ENVP_ADDR) */
675 stw_p(p
++, 0xe0c0 | NM_HI1(ENVP_ADDR
+ 8));
677 stw_p(p
++, NM_HI2(ENVP_ADDR
+ 8));
678 /* lui a2,%hi(ENVP_ADDR + 8) */
680 stw_p(p
++, 0x80c6); stw_p(p
++, NM_LO(ENVP_ADDR
+ 8));
681 /* ori a2,a2,%lo(ENVP_ADDR + 8) */
683 stw_p(p
++, 0xe0e0 | NM_HI1(loaderparams
.ram_low_size
));
685 stw_p(p
++, NM_HI2(loaderparams
.ram_low_size
));
686 /* lui a3,%hi(loaderparams.ram_low_size) */
688 stw_p(p
++, 0x80e7); stw_p(p
++, NM_LO(loaderparams
.ram_low_size
));
689 /* ori a3,a3,%lo(loaderparams.ram_low_size) */
692 * Load BAR registers as done by YAMON:
694 * - set up PCI0 I/O BARs from 0x18000000 to 0x181fffff
695 * - set up PCI0 MEM0 at 0x10000000, size 0x8000000
696 * - set up PCI0 MEM1 at 0x18200000, size 0xbe00000
699 stw_p(p
++, 0xe040); stw_p(p
++, 0x0681);
700 /* lui t1, %hi(0xb4000000) */
702 #ifdef TARGET_WORDS_BIGENDIAN
704 stw_p(p
++, 0xe020); stw_p(p
++, 0x0be1);
705 /* lui t0, %hi(0xdf000000) */
707 /* 0x68 corresponds to GT_ISD (from hw/mips/gt64xxx_pci.c) */
708 stw_p(p
++, 0x8422); stw_p(p
++, 0x9068);
709 /* sw t0, 0x68(t1) */
711 stw_p(p
++, 0xe040); stw_p(p
++, 0x077d);
712 /* lui t1, %hi(0xbbe00000) */
714 stw_p(p
++, 0xe020); stw_p(p
++, 0x0801);
715 /* lui t0, %hi(0xc0000000) */
717 /* 0x48 corresponds to GT_PCI0IOLD */
718 stw_p(p
++, 0x8422); stw_p(p
++, 0x9048);
719 /* sw t0, 0x48(t1) */
721 stw_p(p
++, 0xe020); stw_p(p
++, 0x0800);
722 /* lui t0, %hi(0x40000000) */
724 /* 0x50 corresponds to GT_PCI0IOHD */
725 stw_p(p
++, 0x8422); stw_p(p
++, 0x9050);
726 /* sw t0, 0x50(t1) */
728 stw_p(p
++, 0xe020); stw_p(p
++, 0x0001);
729 /* lui t0, %hi(0x80000000) */
731 /* 0x58 corresponds to GT_PCI0M0LD */
732 stw_p(p
++, 0x8422); stw_p(p
++, 0x9058);
733 /* sw t0, 0x58(t1) */
735 stw_p(p
++, 0xe020); stw_p(p
++, 0x07e0);
736 /* lui t0, %hi(0x3f000000) */
738 /* 0x60 corresponds to GT_PCI0M0HD */
739 stw_p(p
++, 0x8422); stw_p(p
++, 0x9060);
740 /* sw t0, 0x60(t1) */
742 stw_p(p
++, 0xe020); stw_p(p
++, 0x0821);
743 /* lui t0, %hi(0xc1000000) */
745 /* 0x80 corresponds to GT_PCI0M1LD */
746 stw_p(p
++, 0x8422); stw_p(p
++, 0x9080);
747 /* sw t0, 0x80(t1) */
749 stw_p(p
++, 0xe020); stw_p(p
++, 0x0bc0);
750 /* lui t0, %hi(0x5e000000) */
754 stw_p(p
++, 0x0020); stw_p(p
++, 0x00df);
755 /* addiu[32] t0, $0, 0xdf */
757 /* 0x68 corresponds to GT_ISD */
758 stw_p(p
++, 0x8422); stw_p(p
++, 0x9068);
759 /* sw t0, 0x68(t1) */
761 /* Use kseg2 remapped address 0x1be00000 */
762 stw_p(p
++, 0xe040); stw_p(p
++, 0x077d);
763 /* lui t1, %hi(0xbbe00000) */
765 stw_p(p
++, 0x0020); stw_p(p
++, 0x00c0);
766 /* addiu[32] t0, $0, 0xc0 */
768 /* 0x48 corresponds to GT_PCI0IOLD */
769 stw_p(p
++, 0x8422); stw_p(p
++, 0x9048);
770 /* sw t0, 0x48(t1) */
772 stw_p(p
++, 0x0020); stw_p(p
++, 0x0040);
773 /* addiu[32] t0, $0, 0x40 */
775 /* 0x50 corresponds to GT_PCI0IOHD */
776 stw_p(p
++, 0x8422); stw_p(p
++, 0x9050);
777 /* sw t0, 0x50(t1) */
779 stw_p(p
++, 0x0020); stw_p(p
++, 0x0080);
780 /* addiu[32] t0, $0, 0x80 */
782 /* 0x58 corresponds to GT_PCI0M0LD */
783 stw_p(p
++, 0x8422); stw_p(p
++, 0x9058);
784 /* sw t0, 0x58(t1) */
786 stw_p(p
++, 0x0020); stw_p(p
++, 0x003f);
787 /* addiu[32] t0, $0, 0x3f */
789 /* 0x60 corresponds to GT_PCI0M0HD */
790 stw_p(p
++, 0x8422); stw_p(p
++, 0x9060);
791 /* sw t0, 0x60(t1) */
793 stw_p(p
++, 0x0020); stw_p(p
++, 0x00c1);
794 /* addiu[32] t0, $0, 0xc1 */
796 /* 0x80 corresponds to GT_PCI0M1LD */
797 stw_p(p
++, 0x8422); stw_p(p
++, 0x9080);
798 /* sw t0, 0x80(t1) */
800 stw_p(p
++, 0x0020); stw_p(p
++, 0x005e);
801 /* addiu[32] t0, $0, 0x5e */
805 /* 0x88 corresponds to GT_PCI0M1HD */
806 stw_p(p
++, 0x8422); stw_p(p
++, 0x9088);
807 /* sw t0, 0x88(t1) */
809 stw_p(p
++, 0xe320 | NM_HI1(kernel_entry
));
811 stw_p(p
++, NM_HI2(kernel_entry
));
812 /* lui t9,%hi(kernel_entry) */
814 stw_p(p
++, 0x8339); stw_p(p
++, NM_LO(kernel_entry
));
815 /* ori t9,t9,%lo(kernel_entry) */
817 stw_p(p
++, 0x4bf9); stw_p(p
++, 0x0000);
822 * ROM and pseudo bootloader
824 * The following code implements a very very simple bootloader. It first
825 * loads the registers a0 to a3 to the values expected by the OS, and
826 * then jump at the kernel address.
828 * The bootloader should pass the locations of the kernel arguments and
829 * environment variables tables. Those tables contain the 32-bit address
830 * of NULL terminated strings. The environment variables table should be
831 * terminated by a NULL address.
833 * For a simpler implementation, the number of kernel arguments is fixed
834 * to two (the name of the kernel and the command line), and the two
835 * tables are actually the same one.
837 * The registers a0 to a3 should contain the following values:
838 * a0 - number of kernel arguments
839 * a1 - 32-bit address of the kernel arguments table
840 * a2 - 32-bit address of the environment variables table
841 * a3 - RAM size in bytes
843 static void write_bootloader(uint8_t *base
, int64_t run_addr
,
844 int64_t kernel_entry
)
848 /* Small bootloader */
849 p
= (uint32_t *)base
;
851 stl_p(p
++, 0x08000000 | /* j 0x1fc00580 */
852 ((run_addr
+ 0x580) & 0x0fffffff) >> 2);
853 stl_p(p
++, 0x00000000); /* nop */
855 /* YAMON service vector */
856 stl_p(base
+ 0x500, run_addr
+ 0x0580); /* start: */
857 stl_p(base
+ 0x504, run_addr
+ 0x083c); /* print_count: */
858 stl_p(base
+ 0x520, run_addr
+ 0x0580); /* start: */
859 stl_p(base
+ 0x52c, run_addr
+ 0x0800); /* flush_cache: */
860 stl_p(base
+ 0x534, run_addr
+ 0x0808); /* print: */
861 stl_p(base
+ 0x538, run_addr
+ 0x0800); /* reg_cpu_isr: */
862 stl_p(base
+ 0x53c, run_addr
+ 0x0800); /* unred_cpu_isr: */
863 stl_p(base
+ 0x540, run_addr
+ 0x0800); /* reg_ic_isr: */
864 stl_p(base
+ 0x544, run_addr
+ 0x0800); /* unred_ic_isr: */
865 stl_p(base
+ 0x548, run_addr
+ 0x0800); /* reg_esr: */
866 stl_p(base
+ 0x54c, run_addr
+ 0x0800); /* unreg_esr: */
867 stl_p(base
+ 0x550, run_addr
+ 0x0800); /* getchar: */
868 stl_p(base
+ 0x554, run_addr
+ 0x0800); /* syscon_read: */
871 /* Second part of the bootloader */
872 p
= (uint32_t *) (base
+ 0x580);
874 if (semihosting_get_argc()) {
875 /* Preserve a0 content as arguments have been passed */
876 stl_p(p
++, 0x00000000); /* nop */
878 stl_p(p
++, 0x24040002); /* addiu a0, zero, 2 */
881 /* lui sp, high(ENVP_ADDR) */
882 stl_p(p
++, 0x3c1d0000 | (((ENVP_ADDR
- 64) >> 16) & 0xffff));
883 /* ori sp, sp, low(ENVP_ADDR) */
884 stl_p(p
++, 0x37bd0000 | ((ENVP_ADDR
- 64) & 0xffff));
885 /* lui a1, high(ENVP_ADDR) */
886 stl_p(p
++, 0x3c050000 | ((ENVP_ADDR
>> 16) & 0xffff));
887 /* ori a1, a1, low(ENVP_ADDR) */
888 stl_p(p
++, 0x34a50000 | (ENVP_ADDR
& 0xffff));
889 /* lui a2, high(ENVP_ADDR + 8) */
890 stl_p(p
++, 0x3c060000 | (((ENVP_ADDR
+ 8) >> 16) & 0xffff));
891 /* ori a2, a2, low(ENVP_ADDR + 8) */
892 stl_p(p
++, 0x34c60000 | ((ENVP_ADDR
+ 8) & 0xffff));
893 /* lui a3, high(ram_low_size) */
894 stl_p(p
++, 0x3c070000 | (loaderparams
.ram_low_size
>> 16));
895 /* ori a3, a3, low(ram_low_size) */
896 stl_p(p
++, 0x34e70000 | (loaderparams
.ram_low_size
& 0xffff));
898 /* Load BAR registers as done by YAMON */
899 stl_p(p
++, 0x3c09b400); /* lui t1, 0xb400 */
901 #ifdef TARGET_WORDS_BIGENDIAN
902 stl_p(p
++, 0x3c08df00); /* lui t0, 0xdf00 */
904 stl_p(p
++, 0x340800df); /* ori t0, r0, 0x00df */
906 stl_p(p
++, 0xad280068); /* sw t0, 0x0068(t1) */
908 stl_p(p
++, 0x3c09bbe0); /* lui t1, 0xbbe0 */
910 #ifdef TARGET_WORDS_BIGENDIAN
911 stl_p(p
++, 0x3c08c000); /* lui t0, 0xc000 */
913 stl_p(p
++, 0x340800c0); /* ori t0, r0, 0x00c0 */
915 stl_p(p
++, 0xad280048); /* sw t0, 0x0048(t1) */
916 #ifdef TARGET_WORDS_BIGENDIAN
917 stl_p(p
++, 0x3c084000); /* lui t0, 0x4000 */
919 stl_p(p
++, 0x34080040); /* ori t0, r0, 0x0040 */
921 stl_p(p
++, 0xad280050); /* sw t0, 0x0050(t1) */
923 #ifdef TARGET_WORDS_BIGENDIAN
924 stl_p(p
++, 0x3c088000); /* lui t0, 0x8000 */
926 stl_p(p
++, 0x34080080); /* ori t0, r0, 0x0080 */
928 stl_p(p
++, 0xad280058); /* sw t0, 0x0058(t1) */
929 #ifdef TARGET_WORDS_BIGENDIAN
930 stl_p(p
++, 0x3c083f00); /* lui t0, 0x3f00 */
932 stl_p(p
++, 0x3408003f); /* ori t0, r0, 0x003f */
934 stl_p(p
++, 0xad280060); /* sw t0, 0x0060(t1) */
936 #ifdef TARGET_WORDS_BIGENDIAN
937 stl_p(p
++, 0x3c08c100); /* lui t0, 0xc100 */
939 stl_p(p
++, 0x340800c1); /* ori t0, r0, 0x00c1 */
941 stl_p(p
++, 0xad280080); /* sw t0, 0x0080(t1) */
942 #ifdef TARGET_WORDS_BIGENDIAN
943 stl_p(p
++, 0x3c085e00); /* lui t0, 0x5e00 */
945 stl_p(p
++, 0x3408005e); /* ori t0, r0, 0x005e */
947 stl_p(p
++, 0xad280088); /* sw t0, 0x0088(t1) */
949 /* Jump to kernel code */
950 stl_p(p
++, 0x3c1f0000 |
951 ((kernel_entry
>> 16) & 0xffff)); /* lui ra, high(kernel_entry) */
952 stl_p(p
++, 0x37ff0000 |
953 (kernel_entry
& 0xffff)); /* ori ra, ra, low(kernel_entry) */
954 stl_p(p
++, 0x03e00009); /* jalr ra */
955 stl_p(p
++, 0x00000000); /* nop */
957 /* YAMON subroutines */
958 p
= (uint32_t *) (base
+ 0x800);
959 stl_p(p
++, 0x03e00009); /* jalr ra */
960 stl_p(p
++, 0x24020000); /* li v0,0 */
961 /* 808 YAMON print */
962 stl_p(p
++, 0x03e06821); /* move t5,ra */
963 stl_p(p
++, 0x00805821); /* move t3,a0 */
964 stl_p(p
++, 0x00a05021); /* move t2,a1 */
965 stl_p(p
++, 0x91440000); /* lbu a0,0(t2) */
966 stl_p(p
++, 0x254a0001); /* addiu t2,t2,1 */
967 stl_p(p
++, 0x10800005); /* beqz a0,834 */
968 stl_p(p
++, 0x00000000); /* nop */
969 stl_p(p
++, 0x0ff0021c); /* jal 870 */
970 stl_p(p
++, 0x00000000); /* nop */
971 stl_p(p
++, 0x1000fff9); /* b 814 */
972 stl_p(p
++, 0x00000000); /* nop */
973 stl_p(p
++, 0x01a00009); /* jalr t5 */
974 stl_p(p
++, 0x01602021); /* move a0,t3 */
975 /* 0x83c YAMON print_count */
976 stl_p(p
++, 0x03e06821); /* move t5,ra */
977 stl_p(p
++, 0x00805821); /* move t3,a0 */
978 stl_p(p
++, 0x00a05021); /* move t2,a1 */
979 stl_p(p
++, 0x00c06021); /* move t4,a2 */
980 stl_p(p
++, 0x91440000); /* lbu a0,0(t2) */
981 stl_p(p
++, 0x0ff0021c); /* jal 870 */
982 stl_p(p
++, 0x00000000); /* nop */
983 stl_p(p
++, 0x254a0001); /* addiu t2,t2,1 */
984 stl_p(p
++, 0x258cffff); /* addiu t4,t4,-1 */
985 stl_p(p
++, 0x1580fffa); /* bnez t4,84c */
986 stl_p(p
++, 0x00000000); /* nop */
987 stl_p(p
++, 0x01a00009); /* jalr t5 */
988 stl_p(p
++, 0x01602021); /* move a0,t3 */
990 stl_p(p
++, 0x3c08b800); /* lui t0,0xb400 */
991 stl_p(p
++, 0x350803f8); /* ori t0,t0,0x3f8 */
992 stl_p(p
++, 0x91090005); /* lbu t1,5(t0) */
993 stl_p(p
++, 0x00000000); /* nop */
994 stl_p(p
++, 0x31290040); /* andi t1,t1,0x40 */
995 stl_p(p
++, 0x1120fffc); /* beqz t1,878 <outch+0x8> */
996 stl_p(p
++, 0x00000000); /* nop */
997 stl_p(p
++, 0x03e00009); /* jalr ra */
998 stl_p(p
++, 0xa1040000); /* sb a0,0(t0) */
1002 static void GCC_FMT_ATTR(3, 4) prom_set(uint32_t *prom_buf
, int index
,
1003 const char *string
, ...)
1008 if (index
>= ENVP_NB_ENTRIES
) {
1012 if (string
== NULL
) {
1013 prom_buf
[index
] = 0;
1017 table_addr
= sizeof(int32_t) * ENVP_NB_ENTRIES
+ index
* ENVP_ENTRY_SIZE
;
1018 prom_buf
[index
] = tswap32(ENVP_ADDR
+ table_addr
);
1020 va_start(ap
, string
);
1021 vsnprintf((char *)prom_buf
+ table_addr
, ENVP_ENTRY_SIZE
, string
, ap
);
1026 static int64_t load_kernel(void)
1028 int64_t kernel_entry
, kernel_high
, initrd_size
;
1030 ram_addr_t initrd_offset
;
1035 uint64_t (*xlate_to_kseg0
) (void *opaque
, uint64_t addr
);
1037 #ifdef TARGET_WORDS_BIGENDIAN
1043 kernel_size
= load_elf(loaderparams
.kernel_filename
, NULL
,
1044 cpu_mips_kseg0_to_phys
, NULL
,
1045 (uint64_t *)&kernel_entry
, NULL
,
1046 (uint64_t *)&kernel_high
, NULL
, big_endian
, EM_MIPS
,
1048 if (kernel_size
< 0) {
1049 error_report("could not load kernel '%s': %s",
1050 loaderparams
.kernel_filename
,
1051 load_elf_strerror(kernel_size
));
1055 /* Check where the kernel has been linked */
1056 if (kernel_entry
& 0x80000000ll
) {
1057 if (kvm_enabled()) {
1058 error_report("KVM guest kernels must be linked in useg. "
1059 "Did you forget to enable CONFIG_KVM_GUEST?");
1063 xlate_to_kseg0
= cpu_mips_phys_to_kseg0
;
1065 /* if kernel entry is in useg it is probably a KVM T&E kernel */
1066 mips_um_ksegs_enable();
1068 xlate_to_kseg0
= cpu_mips_kvm_um_phys_to_kseg0
;
1074 if (loaderparams
.initrd_filename
) {
1075 initrd_size
= get_image_size(loaderparams
.initrd_filename
);
1076 if (initrd_size
> 0) {
1078 * The kernel allocates the bootmap memory in the low memory after
1079 * the initrd. It takes at most 128kiB for 2GB RAM and 4kiB
1082 initrd_offset
= ROUND_UP(loaderparams
.ram_low_size
1083 - (initrd_size
+ 128 * KiB
),
1085 if (kernel_high
>= initrd_offset
) {
1086 error_report("memory too small for initial ram disk '%s'",
1087 loaderparams
.initrd_filename
);
1090 initrd_size
= load_image_targphys(loaderparams
.initrd_filename
,
1092 loaderparams
.ram_size
- initrd_offset
);
1094 if (initrd_size
== (target_ulong
) -1) {
1095 error_report("could not load initial ram disk '%s'",
1096 loaderparams
.initrd_filename
);
1101 /* Setup prom parameters. */
1102 prom_size
= ENVP_NB_ENTRIES
* (sizeof(int32_t) + ENVP_ENTRY_SIZE
);
1103 prom_buf
= g_malloc(prom_size
);
1105 prom_set(prom_buf
, prom_index
++, "%s", loaderparams
.kernel_filename
);
1106 if (initrd_size
> 0) {
1107 prom_set(prom_buf
, prom_index
++,
1108 "rd_start=0x%" PRIx64
" rd_size=%" PRId64
" %s",
1109 xlate_to_kseg0(NULL
, initrd_offset
),
1110 initrd_size
, loaderparams
.kernel_cmdline
);
1112 prom_set(prom_buf
, prom_index
++, "%s", loaderparams
.kernel_cmdline
);
1115 prom_set(prom_buf
, prom_index
++, "memsize");
1116 prom_set(prom_buf
, prom_index
++, "%u", loaderparams
.ram_low_size
);
1118 prom_set(prom_buf
, prom_index
++, "ememsize");
1119 prom_set(prom_buf
, prom_index
++, "%u", loaderparams
.ram_size
);
1121 prom_set(prom_buf
, prom_index
++, "modetty0");
1122 prom_set(prom_buf
, prom_index
++, "38400n8r");
1123 prom_set(prom_buf
, prom_index
++, NULL
);
1125 rom_add_blob_fixed("prom", prom_buf
, prom_size
,
1126 cpu_mips_kseg0_to_phys(NULL
, ENVP_ADDR
));
1129 return kernel_entry
;
1132 static void malta_mips_config(MIPSCPU
*cpu
)
1134 MachineState
*ms
= MACHINE(qdev_get_machine());
1135 unsigned int smp_cpus
= ms
->smp
.cpus
;
1136 CPUMIPSState
*env
= &cpu
->env
;
1137 CPUState
*cs
= CPU(cpu
);
1139 if (ase_mt_available(env
)) {
1140 env
->mvp
->CP0_MVPConf0
= deposit32(env
->mvp
->CP0_MVPConf0
,
1142 smp_cpus
* cs
->nr_threads
- 1);
1143 env
->mvp
->CP0_MVPConf0
= deposit32(env
->mvp
->CP0_MVPConf0
,
1144 CP0MVPC0_PVPE
, 4, smp_cpus
- 1);
1148 static void main_cpu_reset(void *opaque
)
1150 MIPSCPU
*cpu
= opaque
;
1151 CPUMIPSState
*env
= &cpu
->env
;
1153 cpu_reset(CPU(cpu
));
1156 * The bootloader does not need to be rewritten as it is located in a
1157 * read only location. The kernel location and the arguments table
1158 * location does not change.
1160 if (loaderparams
.kernel_filename
) {
1161 env
->CP0_Status
&= ~(1 << CP0St_ERL
);
1164 malta_mips_config(cpu
);
1166 if (kvm_enabled()) {
1167 /* Start running from the bootloader we wrote to end of RAM */
1168 env
->active_tc
.PC
= 0x40000000 + loaderparams
.ram_low_size
;
1172 static void create_cpu_without_cps(MachineState
*ms
, MaltaState
*s
,
1173 qemu_irq
*cbus_irq
, qemu_irq
*i8259_irq
)
1179 for (i
= 0; i
< ms
->smp
.cpus
; i
++) {
1180 cpu
= mips_cpu_create_with_clock(ms
->cpu_type
, s
->cpuclk
);
1182 /* Init internal devices */
1183 cpu_mips_irq_init_cpu(cpu
);
1184 cpu_mips_clock_init(cpu
);
1185 qemu_register_reset(main_cpu_reset
, cpu
);
1188 cpu
= MIPS_CPU(first_cpu
);
1190 *i8259_irq
= env
->irq
[2];
1191 *cbus_irq
= env
->irq
[4];
1194 static void create_cps(MachineState
*ms
, MaltaState
*s
,
1195 qemu_irq
*cbus_irq
, qemu_irq
*i8259_irq
)
1197 object_initialize_child(OBJECT(s
), "cps", &s
->cps
, TYPE_MIPS_CPS
);
1198 object_property_set_str(OBJECT(&s
->cps
), "cpu-type", ms
->cpu_type
,
1200 object_property_set_int(OBJECT(&s
->cps
), "num-vp", ms
->smp
.cpus
,
1202 qdev_connect_clock_in(DEVICE(&s
->cps
), "clk-in", s
->cpuclk
);
1203 sysbus_realize(SYS_BUS_DEVICE(&s
->cps
), &error_fatal
);
1205 sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s
->cps
), 0, 0, 1);
1207 *i8259_irq
= get_cps_irq(&s
->cps
, 3);
1211 static void mips_create_cpu(MachineState
*ms
, MaltaState
*s
,
1212 qemu_irq
*cbus_irq
, qemu_irq
*i8259_irq
)
1214 if ((ms
->smp
.cpus
> 1) && cpu_type_supports_cps_smp(ms
->cpu_type
)) {
1215 create_cps(ms
, s
, cbus_irq
, i8259_irq
);
1217 create_cpu_without_cps(ms
, s
, cbus_irq
, i8259_irq
);
1222 void mips_malta_init(MachineState
*machine
)
1224 ram_addr_t ram_size
= machine
->ram_size
;
1225 ram_addr_t ram_low_size
;
1226 const char *kernel_filename
= machine
->kernel_filename
;
1227 const char *kernel_cmdline
= machine
->kernel_cmdline
;
1228 const char *initrd_filename
= machine
->initrd_filename
;
1231 MemoryRegion
*system_memory
= get_system_memory();
1232 MemoryRegion
*ram_low_preio
= g_new(MemoryRegion
, 1);
1233 MemoryRegion
*ram_low_postio
;
1234 MemoryRegion
*bios
, *bios_copy
= g_new(MemoryRegion
, 1);
1235 const size_t smbus_eeprom_size
= 8 * 256;
1236 uint8_t *smbus_eeprom_buf
= g_malloc0(smbus_eeprom_size
);
1237 int64_t kernel_entry
, bootloader_run_addr
;
1240 qemu_irq cbus_irq
, i8259_irq
;
1248 s
= MIPS_MALTA(qdev_new(TYPE_MIPS_MALTA
));
1249 sysbus_realize_and_unref(SYS_BUS_DEVICE(s
), &error_fatal
);
1252 mips_create_cpu(machine
, s
, &cbus_irq
, &i8259_irq
);
1255 if (ram_size
> 2 * GiB
) {
1256 error_report("Too much memory for this machine: %" PRId64
"MB,"
1257 " maximum 2048MB", ram_size
/ MiB
);
1261 /* register RAM at high address where it is undisturbed by IO */
1262 memory_region_add_subregion(system_memory
, 0x80000000, machine
->ram
);
1264 /* alias for pre IO hole access */
1265 memory_region_init_alias(ram_low_preio
, NULL
, "mips_malta_low_preio.ram",
1266 machine
->ram
, 0, MIN(ram_size
, 256 * MiB
));
1267 memory_region_add_subregion(system_memory
, 0, ram_low_preio
);
1269 /* alias for post IO hole access, if there is enough RAM */
1270 if (ram_size
> 512 * MiB
) {
1271 ram_low_postio
= g_new(MemoryRegion
, 1);
1272 memory_region_init_alias(ram_low_postio
, NULL
,
1273 "mips_malta_low_postio.ram",
1274 machine
->ram
, 512 * MiB
,
1275 ram_size
- 512 * MiB
);
1276 memory_region_add_subregion(system_memory
, 512 * MiB
,
1280 #ifdef TARGET_WORDS_BIGENDIAN
1288 /* The CBUS UART is attached to the MIPS CPU INT2 pin, ie interrupt 4 */
1289 malta_fpga_init(system_memory
, FPGA_ADDRESS
, cbus_irq
, serial_hd(2));
1291 /* Load firmware in flash / BIOS. */
1292 dinfo
= drive_get(IF_PFLASH
, 0, fl_idx
);
1293 fl
= pflash_cfi01_register(FLASH_ADDRESS
, "mips_malta.bios",
1295 dinfo
? blk_by_legacy_dinfo(dinfo
) : NULL
,
1297 4, 0x0000, 0x0000, 0x0000, 0x0000, be
);
1298 bios
= pflash_cfi01_get_memory(fl
);
1300 if (kernel_filename
) {
1301 ram_low_size
= MIN(ram_size
, 256 * MiB
);
1302 /* For KVM we reserve 1MB of RAM for running bootloader */
1303 if (kvm_enabled()) {
1304 ram_low_size
-= 0x100000;
1305 bootloader_run_addr
= 0x40000000 + ram_low_size
;
1307 bootloader_run_addr
= 0xbfc00000;
1310 /* Write a small bootloader to the flash location. */
1311 loaderparams
.ram_size
= ram_size
;
1312 loaderparams
.ram_low_size
= ram_low_size
;
1313 loaderparams
.kernel_filename
= kernel_filename
;
1314 loaderparams
.kernel_cmdline
= kernel_cmdline
;
1315 loaderparams
.initrd_filename
= initrd_filename
;
1316 kernel_entry
= load_kernel();
1318 if (!cpu_type_supports_isa(machine
->cpu_type
, ISA_NANOMIPS32
)) {
1319 write_bootloader(memory_region_get_ram_ptr(bios
),
1320 bootloader_run_addr
, kernel_entry
);
1322 write_bootloader_nanomips(memory_region_get_ram_ptr(bios
),
1323 bootloader_run_addr
, kernel_entry
);
1325 if (kvm_enabled()) {
1326 /* Write the bootloader code @ the end of RAM, 1MB reserved */
1327 write_bootloader(memory_region_get_ram_ptr(ram_low_preio
) +
1329 bootloader_run_addr
, kernel_entry
);
1332 target_long bios_size
= FLASH_SIZE
;
1333 /* The flash region isn't executable from a KVM guest */
1334 if (kvm_enabled()) {
1335 error_report("KVM enabled but no -kernel argument was specified. "
1336 "Booting from flash is not supported with KVM.");
1339 /* Load firmware from flash. */
1341 /* Load a BIOS image. */
1342 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
,
1343 machine
->firmware
?: BIOS_FILENAME
);
1345 bios_size
= load_image_targphys(filename
, FLASH_ADDRESS
,
1351 if ((bios_size
< 0 || bios_size
> BIOS_SIZE
) &&
1352 machine
->firmware
&& !qtest_enabled()) {
1353 error_report("Could not load MIPS bios '%s'", machine
->firmware
);
1358 * In little endian mode the 32bit words in the bios are swapped,
1359 * a neat trick which allows bi-endian firmware.
1361 #ifndef TARGET_WORDS_BIGENDIAN
1363 uint32_t *end
, *addr
;
1364 const size_t swapsize
= MIN(bios_size
, 0x3e0000);
1365 addr
= rom_ptr(FLASH_ADDRESS
, swapsize
);
1367 addr
= memory_region_get_ram_ptr(bios
);
1369 end
= (void *)addr
+ swapsize
;
1370 while (addr
< end
) {
1379 * Map the BIOS at a 2nd physical location, as on the real board.
1380 * Copy it so that we can patch in the MIPS revision, which cannot be
1381 * handled by an overlapping region as the resulting ROM code subpage
1382 * regions are not executable.
1384 memory_region_init_ram(bios_copy
, NULL
, "bios.1fc", BIOS_SIZE
,
1386 if (!rom_copy(memory_region_get_ram_ptr(bios_copy
),
1387 FLASH_ADDRESS
, BIOS_SIZE
)) {
1388 memcpy(memory_region_get_ram_ptr(bios_copy
),
1389 memory_region_get_ram_ptr(bios
), BIOS_SIZE
);
1391 memory_region_set_readonly(bios_copy
, true);
1392 memory_region_add_subregion(system_memory
, RESET_ADDRESS
, bios_copy
);
1394 /* Board ID = 0x420 (Malta Board with CoreLV) */
1395 stl_p(memory_region_get_ram_ptr(bios_copy
) + 0x10, 0x00000420);
1398 pci_bus
= gt64120_register(s
->i8259
);
1400 * The whole address space decoded by the GT-64120A doesn't generate
1401 * exception when accessing invalid memory. Create an empty slot to
1402 * emulate this feature.
1404 empty_slot_init("GT64120", 0, 0x20000000);
1407 dev
= piix4_create(pci_bus
, &isa_bus
, &smbus
);
1409 /* Interrupt controller */
1410 qdev_connect_gpio_out_named(dev
, "intr", 0, i8259_irq
);
1411 for (int i
= 0; i
< ISA_NUM_IRQS
; i
++) {
1412 s
->i8259
[i
] = qdev_get_gpio_in_named(dev
, "isa", i
);
1415 /* generate SPD EEPROM data */
1416 generate_eeprom_spd(&smbus_eeprom_buf
[0 * 256], ram_size
);
1417 generate_eeprom_serial(&smbus_eeprom_buf
[6 * 256]);
1418 smbus_eeprom_init(smbus
, 8, smbus_eeprom_buf
, smbus_eeprom_size
);
1419 g_free(smbus_eeprom_buf
);
1421 /* Super I/O: SMS FDC37M817 */
1422 isa_create_simple(isa_bus
, TYPE_FDC37M81X_SUPERIO
);
1425 network_init(pci_bus
);
1427 /* Optional PCI video card */
1428 pci_vga_init(pci_bus
);
1431 static void mips_malta_instance_init(Object
*obj
)
1433 MaltaState
*s
= MIPS_MALTA(obj
);
1435 s
->cpuclk
= qdev_init_clock_out(DEVICE(obj
), "cpu-refclk");
1436 clock_set_hz(s
->cpuclk
, 320000000); /* 320 MHz */
1439 static const TypeInfo mips_malta_device
= {
1440 .name
= TYPE_MIPS_MALTA
,
1441 .parent
= TYPE_SYS_BUS_DEVICE
,
1442 .instance_size
= sizeof(MaltaState
),
1443 .instance_init
= mips_malta_instance_init
,
1446 static void mips_malta_machine_init(MachineClass
*mc
)
1448 mc
->desc
= "MIPS Malta Core LV";
1449 mc
->init
= mips_malta_init
;
1450 mc
->block_default_type
= IF_IDE
;
1452 mc
->is_default
= true;
1453 #ifdef TARGET_MIPS64
1454 mc
->default_cpu_type
= MIPS_CPU_TYPE_NAME("20Kc");
1456 mc
->default_cpu_type
= MIPS_CPU_TYPE_NAME("24Kf");
1458 mc
->default_ram_id
= "mips_malta.ram";
1461 DEFINE_MACHINE("malta", mips_malta_machine_init
)
1463 static void mips_malta_register_types(void)
1465 type_register_static(&mips_malta_device
);
1468 type_init(mips_malta_register_types
)