hw/core/machine.c

   1 /*
   2  * QEMU Machine
   3  *
   4  * Copyright (C) 2014 Red Hat Inc
   5  *
   6  * Authors:
   7  *   Marcel Apfelbaum <marcel.a@redhat.com>
   8  *
   9  * This work is licensed under the terms of the GNU GPL, version 2 or later.
  10  * See the COPYING file in the top-level directory.
  11  */
  12
  13 #include "qemu/osdep.h"
  14 #include "qemu/accel.h"
  15 #include "sysemu/replay.h"
  16 #include "hw/boards.h"
  17 #include "hw/loader.h"
  18 #include "qapi/error.h"
  19 #include "qapi/qapi-visit-machine.h"
  20 #include "qom/object_interfaces.h"
  21 #include "sysemu/cpus.h"
  22 #include "sysemu/sysemu.h"
  23 #include "sysemu/reset.h"
  24 #include "sysemu/runstate.h"
  25 #include "sysemu/xen.h"
  26 #include "sysemu/qtest.h"
  27 #include "hw/pci/pci_bridge.h"
  28 #include "hw/mem/nvdimm.h"
  29 #include "migration/global_state.h"
  30 #include "exec/confidential-guest-support.h"
  31 #include "hw/virtio/virtio-pci.h"
  32 #include "hw/virtio/virtio-net.h"
  33 #include "hw/virtio/virtio-iommu.h"
  34 #include "audio/audio.h"
  35
  36 GlobalProperty hw_compat_8_2[] = {
  37     { "migration", "zero-page-detection", "legacy"},
  38     { TYPE_VIRTIO_IOMMU_PCI, "granule", "4k" },
  39     { TYPE_VIRTIO_IOMMU_PCI, "aw-bits", "64" },
  40 };
  41 const size_t hw_compat_8_2_len = G_N_ELEMENTS(hw_compat_8_2);
  42
  43 GlobalProperty hw_compat_8_1[] = {
  44     { TYPE_PCI_BRIDGE, "x-pci-express-writeable-slt-bug", "true" },
  45     { "ramfb", "x-migrate", "off" },
  46     { "vfio-pci-nohotplug", "x-ramfb-migrate", "off" },
  47     { "igb", "x-pcie-flr-init", "off" },
  48 };
  49 const size_t hw_compat_8_1_len = G_N_ELEMENTS(hw_compat_8_1);
  50
  51 GlobalProperty hw_compat_8_0[] = {
  52     { "migration", "multifd-flush-after-each-section", "on"},
  53     { TYPE_PCI_DEVICE, "x-pcie-ari-nextfn-1", "on" },
  54     { TYPE_VIRTIO_NET, "host_uso", "off"},
  55     { TYPE_VIRTIO_NET, "guest_uso4", "off"},
  56     { TYPE_VIRTIO_NET, "guest_uso6", "off"},
  57 };
  58 const size_t hw_compat_8_0_len = G_N_ELEMENTS(hw_compat_8_0);
  59
  60 GlobalProperty hw_compat_7_2[] = {
  61     { "e1000e", "migrate-timadj", "off" },
  62     { "virtio-mem", "x-early-migration", "false" },
  63     { "migration", "x-preempt-pre-7-2", "true" },
  64     { TYPE_PCI_DEVICE, "x-pcie-err-unc-mask", "off" },
  65 };
  66 const size_t hw_compat_7_2_len = G_N_ELEMENTS(hw_compat_7_2);
  67
  68 GlobalProperty hw_compat_7_1[] = {
  69     { "virtio-device", "queue_reset", "false" },
  70     { "virtio-rng-pci", "vectors", "0" },
  71     { "virtio-rng-pci-transitional", "vectors", "0" },
  72     { "virtio-rng-pci-non-transitional", "vectors", "0" },
  73 };
  74 const size_t hw_compat_7_1_len = G_N_ELEMENTS(hw_compat_7_1);
  75
  76 GlobalProperty hw_compat_7_0[] = {
  77     { "arm-gicv3-common", "force-8-bit-prio", "on" },
  78     { "nvme-ns", "eui64-default", "on"},
  79 };
  80 const size_t hw_compat_7_0_len = G_N_ELEMENTS(hw_compat_7_0);
  81
  82 GlobalProperty hw_compat_6_2[] = {
  83     { "PIIX4_PM", "x-not-migrate-acpi-index", "on"},
  84 };
  85 const size_t hw_compat_6_2_len = G_N_ELEMENTS(hw_compat_6_2);
  86
  87 GlobalProperty hw_compat_6_1[] = {
  88     { "vhost-user-vsock-device", "seqpacket", "off" },
  89     { "nvme-ns", "shared", "off" },
  90 };
  91 const size_t hw_compat_6_1_len = G_N_ELEMENTS(hw_compat_6_1);
  92
  93 GlobalProperty hw_compat_6_0[] = {
  94     { "gpex-pcihost", "allow-unmapped-accesses", "false" },
  95     { "i8042", "extended-state", "false"},
  96     { "nvme-ns", "eui64-default", "off"},
  97     { "e1000", "init-vet", "off" },
  98     { "e1000e", "init-vet", "off" },
  99     { "vhost-vsock-device", "seqpacket", "off" },
 100 };
 101 const size_t hw_compat_6_0_len = G_N_ELEMENTS(hw_compat_6_0);
 102
 103 GlobalProperty hw_compat_5_2[] = {
 104     { "ICH9-LPC", "smm-compat", "on"},
 105     { "PIIX4_PM", "smm-compat", "on"},
 106     { "virtio-blk-device", "report-discard-granularity", "off" },
 107     { "virtio-net-pci-base", "vectors", "3"},
 108     { "nvme", "msix-exclusive-bar", "on"},
 109 };
 110 const size_t hw_compat_5_2_len = G_N_ELEMENTS(hw_compat_5_2);
 111
 112 GlobalProperty hw_compat_5_1[] = {
 113     { "vhost-scsi", "num_queues", "1"},
 114     { "vhost-user-blk", "num-queues", "1"},
 115     { "vhost-user-scsi", "num_queues", "1"},
 116     { "virtio-blk-device", "num-queues", "1"},
 117     { "virtio-scsi-device", "num_queues", "1"},
 118     { "nvme", "use-intel-id", "on"},
 119     { "pvpanic", "events", "1"}, /* PVPANIC_PANICKED */
 120     { "pl011", "migrate-clk", "off" },
 121     { "virtio-pci", "x-ats-page-aligned", "off"},
 122 };
 123 const size_t hw_compat_5_1_len = G_N_ELEMENTS(hw_compat_5_1);
 124
 125 GlobalProperty hw_compat_5_0[] = {
 126     { "pci-host-bridge", "x-config-reg-migration-enabled", "off" },
 127     { "virtio-balloon-device", "page-poison", "false" },
 128     { "vmport", "x-read-set-eax", "off" },
 129     { "vmport", "x-signal-unsupported-cmd", "off" },
 130     { "vmport", "x-report-vmx-type", "off" },
 131     { "vmport", "x-cmds-v2", "off" },
 132     { "virtio-device", "x-disable-legacy-check", "true" },
 133 };
 134 const size_t hw_compat_5_0_len = G_N_ELEMENTS(hw_compat_5_0);
 135
 136 GlobalProperty hw_compat_4_2[] = {
 137     { "virtio-blk-device", "queue-size", "128"},
 138     { "virtio-scsi-device", "virtqueue_size", "128"},
 139     { "virtio-blk-device", "x-enable-wce-if-config-wce", "off" },
 140     { "virtio-blk-device", "seg-max-adjust", "off"},
 141     { "virtio-scsi-device", "seg_max_adjust", "off"},
 142     { "vhost-blk-device", "seg_max_adjust", "off"},
 143     { "usb-host", "suppress-remote-wake", "off" },
 144     { "usb-redir", "suppress-remote-wake", "off" },
 145     { "qxl", "revision", "4" },
 146     { "qxl-vga", "revision", "4" },
 147     { "fw_cfg", "acpi-mr-restore", "false" },
 148     { "virtio-device", "use-disabled-flag", "false" },
 149 };
 150 const size_t hw_compat_4_2_len = G_N_ELEMENTS(hw_compat_4_2);
 151
 152 GlobalProperty hw_compat_4_1[] = {
 153     { "virtio-pci", "x-pcie-flr-init", "off" },
 154 };
 155 const size_t hw_compat_4_1_len = G_N_ELEMENTS(hw_compat_4_1);
 156
 157 GlobalProperty hw_compat_4_0[] = {
 158     { "VGA",            "edid", "false" },
 159     { "secondary-vga",  "edid", "false" },
 160     { "bochs-display",  "edid", "false" },
 161     { "virtio-vga",     "edid", "false" },
 162     { "virtio-gpu-device", "edid", "false" },
 163     { "virtio-device", "use-started", "false" },
 164     { "virtio-balloon-device", "qemu-4-0-config-size", "true" },
 165     { "pl031", "migrate-tick-offset", "false" },
 166 };
 167 const size_t hw_compat_4_0_len = G_N_ELEMENTS(hw_compat_4_0);
 168
 169 GlobalProperty hw_compat_3_1[] = {
 170     { "pcie-root-port", "x-speed", "2_5" },
 171     { "pcie-root-port", "x-width", "1" },
 172     { "memory-backend-file", "x-use-canonical-path-for-ramblock-id", "true" },
 173     { "memory-backend-memfd", "x-use-canonical-path-for-ramblock-id", "true" },
 174     { "tpm-crb", "ppi", "false" },
 175     { "tpm-tis", "ppi", "false" },
 176     { "usb-kbd", "serial", "42" },
 177     { "usb-mouse", "serial", "42" },
 178     { "usb-tablet", "serial", "42" },
 179     { "virtio-blk-device", "discard", "false" },
 180     { "virtio-blk-device", "write-zeroes", "false" },
 181     { "virtio-balloon-device", "qemu-4-0-config-size", "false" },
 182     { "pcie-root-port-base", "disable-acs", "true" }, /* Added in 4.1 */
 183 };
 184 const size_t hw_compat_3_1_len = G_N_ELEMENTS(hw_compat_3_1);
 185
 186 GlobalProperty hw_compat_3_0[] = {};
 187 const size_t hw_compat_3_0_len = G_N_ELEMENTS(hw_compat_3_0);
 188
 189 GlobalProperty hw_compat_2_12[] = {
 190     { "migration", "decompress-error-check", "off" },
 191     { "hda-audio", "use-timer", "false" },
 192     { "cirrus-vga", "global-vmstate", "true" },
 193     { "VGA", "global-vmstate", "true" },
 194     { "vmware-svga", "global-vmstate", "true" },
 195     { "qxl-vga", "global-vmstate", "true" },
 196 };
 197 const size_t hw_compat_2_12_len = G_N_ELEMENTS(hw_compat_2_12);
 198
 199 GlobalProperty hw_compat_2_11[] = {
 200     { "hpet", "hpet-offset-saved", "false" },
 201     { "virtio-blk-pci", "vectors", "2" },
 202     { "vhost-user-blk-pci", "vectors", "2" },
 203     { "e1000", "migrate_tso_props", "off" },
 204 };
 205 const size_t hw_compat_2_11_len = G_N_ELEMENTS(hw_compat_2_11);
 206
 207 GlobalProperty hw_compat_2_10[] = {
 208     { "virtio-mouse-device", "wheel-axis", "false" },
 209     { "virtio-tablet-device", "wheel-axis", "false" },
 210 };
 211 const size_t hw_compat_2_10_len = G_N_ELEMENTS(hw_compat_2_10);
 212
 213 GlobalProperty hw_compat_2_9[] = {
 214     { "pci-bridge", "shpc", "off" },
 215     { "intel-iommu", "pt", "off" },
 216     { "virtio-net-device", "x-mtu-bypass-backend", "off" },
 217     { "pcie-root-port", "x-migrate-msix", "false" },
 218 };
 219 const size_t hw_compat_2_9_len = G_N_ELEMENTS(hw_compat_2_9);
 220
 221 GlobalProperty hw_compat_2_8[] = {
 222     { "fw_cfg_mem", "x-file-slots", "0x10" },
 223     { "fw_cfg_io", "x-file-slots", "0x10" },
 224     { "pflash_cfi01", "old-multiple-chip-handling", "on" },
 225     { "pci-bridge", "shpc", "on" },
 226     { TYPE_PCI_DEVICE, "x-pcie-extcap-init", "off" },
 227     { "virtio-pci", "x-pcie-deverr-init", "off" },
 228     { "virtio-pci", "x-pcie-lnkctl-init", "off" },
 229     { "virtio-pci", "x-pcie-pm-init", "off" },
 230     { "cirrus-vga", "vgamem_mb", "8" },
 231     { "isa-cirrus-vga", "vgamem_mb", "8" },
 232 };
 233 const size_t hw_compat_2_8_len = G_N_ELEMENTS(hw_compat_2_8);
 234
 235 GlobalProperty hw_compat_2_7[] = {
 236     { "virtio-pci", "page-per-vq", "on" },
 237     { "virtio-serial-device", "emergency-write", "off" },
 238     { "ioapic", "version", "0x11" },
 239     { "intel-iommu", "x-buggy-eim", "true" },
 240     { "virtio-pci", "x-ignore-backend-features", "on" },
 241 };
 242 const size_t hw_compat_2_7_len = G_N_ELEMENTS(hw_compat_2_7);
 243
 244 GlobalProperty hw_compat_2_6[] = {
 245     { "virtio-mmio", "format_transport_address", "off" },
 246     /* Optional because not all virtio-pci devices support legacy mode */
 247     { "virtio-pci", "disable-modern", "on",  .optional = true },
 248     { "virtio-pci", "disable-legacy", "off", .optional = true },
 249 };
 250 const size_t hw_compat_2_6_len = G_N_ELEMENTS(hw_compat_2_6);
 251
 252 GlobalProperty hw_compat_2_5[] = {
 253     { "isa-fdc", "fallback", "144" },
 254     { "pvscsi", "x-old-pci-configuration", "on" },
 255     { "pvscsi", "x-disable-pcie", "on" },
 256     { "vmxnet3", "x-old-msi-offsets", "on" },
 257     { "vmxnet3", "x-disable-pcie", "on" },
 258 };
 259 const size_t hw_compat_2_5_len = G_N_ELEMENTS(hw_compat_2_5);
 260
 261 GlobalProperty hw_compat_2_4[] = {
 262     /* Optional because the 'scsi' property is Linux-only */
 263     { "virtio-blk-device", "scsi", "true", .optional = true },
 264     { "e1000", "extra_mac_registers", "off" },
 265     { "virtio-pci", "x-disable-pcie", "on" },
 266     { "virtio-pci", "migrate-extra", "off" },
 267     { "fw_cfg_mem", "dma_enabled", "off" },
 268     { "fw_cfg_io", "dma_enabled", "off" }
 269 };
 270 const size_t hw_compat_2_4_len = G_N_ELEMENTS(hw_compat_2_4);
 271
 272 GlobalProperty hw_compat_2_3[] = {
 273     { "virtio-blk-pci", "any_layout", "off" },
 274     { "virtio-balloon-pci", "any_layout", "off" },
 275     { "virtio-serial-pci", "any_layout", "off" },
 276     { "virtio-9p-pci", "any_layout", "off" },
 277     { "virtio-rng-pci", "any_layout", "off" },
 278     { TYPE_PCI_DEVICE, "x-pcie-lnksta-dllla", "off" },
 279     { "migration", "send-configuration", "off" },
 280     { "migration", "send-section-footer", "off" },
 281     { "migration", "store-global-state", "off" },
 282 };
 283 const size_t hw_compat_2_3_len = G_N_ELEMENTS(hw_compat_2_3);
 284
 285 GlobalProperty hw_compat_2_2[] = {};
 286 const size_t hw_compat_2_2_len = G_N_ELEMENTS(hw_compat_2_2);
 287
 288 GlobalProperty hw_compat_2_1[] = {
 289     { "intel-hda", "old_msi_addr", "on" },
 290     { "VGA", "qemu-extended-regs", "off" },
 291     { "secondary-vga", "qemu-extended-regs", "off" },
 292     { "virtio-scsi-pci", "any_layout", "off" },
 293     { "usb-mouse", "usb_version", "1" },
 294     { "usb-kbd", "usb_version", "1" },
 295     { "virtio-pci", "virtio-pci-bus-master-bug-migration", "on" },
 296 };
 297 const size_t hw_compat_2_1_len = G_N_ELEMENTS(hw_compat_2_1);
 298
 299 MachineState *current_machine;
 300
 301 static char *machine_get_kernel(Object *obj, Error **errp)
 302 {
 303     MachineState *ms = MACHINE(obj);
 304
 305     return g_strdup(ms->kernel_filename);
 306 }
 307
 308 static void machine_set_kernel(Object *obj, const char *value, Error **errp)
 309 {
 310     MachineState *ms = MACHINE(obj);
 311
 312     g_free(ms->kernel_filename);
 313     ms->kernel_filename = g_strdup(value);
 314 }
 315
 316 static char *machine_get_initrd(Object *obj, Error **errp)
 317 {
 318     MachineState *ms = MACHINE(obj);
 319
 320     return g_strdup(ms->initrd_filename);
 321 }
 322
 323 static void machine_set_initrd(Object *obj, const char *value, Error **errp)
 324 {
 325     MachineState *ms = MACHINE(obj);
 326
 327     g_free(ms->initrd_filename);
 328     ms->initrd_filename = g_strdup(value);
 329 }
 330
 331 static char *machine_get_append(Object *obj, Error **errp)
 332 {
 333     MachineState *ms = MACHINE(obj);
 334
 335     return g_strdup(ms->kernel_cmdline);
 336 }
 337
 338 static void machine_set_append(Object *obj, const char *value, Error **errp)
 339 {
 340     MachineState *ms = MACHINE(obj);
 341
 342     g_free(ms->kernel_cmdline);
 343     ms->kernel_cmdline = g_strdup(value);
 344 }
 345
 346 static char *machine_get_dtb(Object *obj, Error **errp)
 347 {
 348     MachineState *ms = MACHINE(obj);
 349
 350     return g_strdup(ms->dtb);
 351 }
 352
 353 static void machine_set_dtb(Object *obj, const char *value, Error **errp)
 354 {
 355     MachineState *ms = MACHINE(obj);
 356
 357     g_free(ms->dtb);
 358     ms->dtb = g_strdup(value);
 359 }
 360
 361 static char *machine_get_dumpdtb(Object *obj, Error **errp)
 362 {
 363     MachineState *ms = MACHINE(obj);
 364
 365     return g_strdup(ms->dumpdtb);
 366 }
 367
 368 static void machine_set_dumpdtb(Object *obj, const char *value, Error **errp)
 369 {
 370     MachineState *ms = MACHINE(obj);
 371
 372     g_free(ms->dumpdtb);
 373     ms->dumpdtb = g_strdup(value);
 374 }
 375
 376 static void machine_get_phandle_start(Object *obj, Visitor *v,
 377                                       const char *name, void *opaque,
 378                                       Error **errp)
 379 {
 380     MachineState *ms = MACHINE(obj);
 381     int64_t value = ms->phandle_start;
 382
 383     visit_type_int(v, name, &value, errp);
 384 }
 385
 386 static void machine_set_phandle_start(Object *obj, Visitor *v,
 387                                       const char *name, void *opaque,
 388                                       Error **errp)
 389 {
 390     MachineState *ms = MACHINE(obj);
 391     int64_t value;
 392
 393     if (!visit_type_int(v, name, &value, errp)) {
 394         return;
 395     }
 396
 397     ms->phandle_start = value;
 398 }
 399
 400 static char *machine_get_dt_compatible(Object *obj, Error **errp)
 401 {
 402     MachineState *ms = MACHINE(obj);
 403
 404     return g_strdup(ms->dt_compatible);
 405 }
 406
 407 static void machine_set_dt_compatible(Object *obj, const char *value, Error **errp)
 408 {
 409     MachineState *ms = MACHINE(obj);
 410
 411     g_free(ms->dt_compatible);
 412     ms->dt_compatible = g_strdup(value);
 413 }
 414
 415 static bool machine_get_dump_guest_core(Object *obj, Error **errp)
 416 {
 417     MachineState *ms = MACHINE(obj);
 418
 419     return ms->dump_guest_core;
 420 }
 421
 422 static void machine_set_dump_guest_core(Object *obj, bool value, Error **errp)
 423 {
 424     MachineState *ms = MACHINE(obj);
 425
 426     ms->dump_guest_core = value;
 427 }
 428
 429 static bool machine_get_mem_merge(Object *obj, Error **errp)
 430 {
 431     MachineState *ms = MACHINE(obj);
 432
 433     return ms->mem_merge;
 434 }
 435
 436 static void machine_set_mem_merge(Object *obj, bool value, Error **errp)
 437 {
 438     MachineState *ms = MACHINE(obj);
 439
 440     ms->mem_merge = value;
 441 }
 442
 443 static bool machine_get_usb(Object *obj, Error **errp)
 444 {
 445     MachineState *ms = MACHINE(obj);
 446
 447     return ms->usb;
 448 }
 449
 450 static void machine_set_usb(Object *obj, bool value, Error **errp)
 451 {
 452     MachineState *ms = MACHINE(obj);
 453
 454     ms->usb = value;
 455     ms->usb_disabled = !value;
 456 }
 457
 458 static bool machine_get_graphics(Object *obj, Error **errp)
 459 {
 460     MachineState *ms = MACHINE(obj);
 461
 462     return ms->enable_graphics;
 463 }
 464
 465 static void machine_set_graphics(Object *obj, bool value, Error **errp)
 466 {
 467     MachineState *ms = MACHINE(obj);
 468
 469     ms->enable_graphics = value;
 470 }
 471
 472 static char *machine_get_firmware(Object *obj, Error **errp)
 473 {
 474     MachineState *ms = MACHINE(obj);
 475
 476     return g_strdup(ms->firmware);
 477 }
 478
 479 static void machine_set_firmware(Object *obj, const char *value, Error **errp)
 480 {
 481     MachineState *ms = MACHINE(obj);
 482
 483     g_free(ms->firmware);
 484     ms->firmware = g_strdup(value);
 485 }
 486
 487 static void machine_set_suppress_vmdesc(Object *obj, bool value, Error **errp)
 488 {
 489     MachineState *ms = MACHINE(obj);
 490
 491     ms->suppress_vmdesc = value;
 492 }
 493
 494 static bool machine_get_suppress_vmdesc(Object *obj, Error **errp)
 495 {
 496     MachineState *ms = MACHINE(obj);
 497
 498     return ms->suppress_vmdesc;
 499 }
 500
 501 static char *machine_get_memory_encryption(Object *obj, Error **errp)
 502 {
 503     MachineState *ms = MACHINE(obj);
 504
 505     if (ms->cgs) {
 506         return g_strdup(object_get_canonical_path_component(OBJECT(ms->cgs)));
 507     }
 508
 509     return NULL;
 510 }
 511
 512 static void machine_set_memory_encryption(Object *obj, const char *value,
 513                                         Error **errp)
 514 {
 515     Object *cgs =
 516         object_resolve_path_component(object_get_objects_root(), value);
 517
 518     if (!cgs) {
 519         error_setg(errp, "No such memory encryption object '%s'", value);
 520         return;
 521     }
 522
 523     object_property_set_link(obj, "confidential-guest-support", cgs, errp);
 524 }
 525
 526 static void machine_check_confidential_guest_support(const Object *obj,
 527                                                      const char *name,
 528                                                      Object *new_target,
 529                                                      Error **errp)
 530 {
 531     /*
 532      * So far the only constraint is that the target has the
 533      * TYPE_CONFIDENTIAL_GUEST_SUPPORT interface, and that's checked
 534      * by the QOM core
 535      */
 536 }
 537
 538 static bool machine_get_nvdimm(Object *obj, Error **errp)
 539 {
 540     MachineState *ms = MACHINE(obj);
 541
 542     return ms->nvdimms_state->is_enabled;
 543 }
 544
 545 static void machine_set_nvdimm(Object *obj, bool value, Error **errp)
 546 {
 547     MachineState *ms = MACHINE(obj);
 548
 549     ms->nvdimms_state->is_enabled = value;
 550 }
 551
 552 static bool machine_get_hmat(Object *obj, Error **errp)
 553 {
 554     MachineState *ms = MACHINE(obj);
 555
 556     return ms->numa_state->hmat_enabled;
 557 }
 558
 559 static void machine_set_hmat(Object *obj, bool value, Error **errp)
 560 {
 561     MachineState *ms = MACHINE(obj);
 562
 563     ms->numa_state->hmat_enabled = value;
 564 }
 565
 566 static void machine_get_mem(Object *obj, Visitor *v, const char *name,
 567                             void *opaque, Error **errp)
 568 {
 569     MachineState *ms = MACHINE(obj);
 570     MemorySizeConfiguration mem = {
 571         .has_size = true,
 572         .size = ms->ram_size,
 573         .has_max_size = !!ms->ram_slots,
 574         .max_size = ms->maxram_size,
 575         .has_slots = !!ms->ram_slots,
 576         .slots = ms->ram_slots,
 577     };
 578     MemorySizeConfiguration *p_mem = &mem;
 579
 580     visit_type_MemorySizeConfiguration(v, name, &p_mem, &error_abort);
 581 }
 582
 583 static void machine_set_mem(Object *obj, Visitor *v, const char *name,
 584                             void *opaque, Error **errp)
 585 {
 586     ERRP_GUARD();
 587     MachineState *ms = MACHINE(obj);
 588     MachineClass *mc = MACHINE_GET_CLASS(obj);
 589     MemorySizeConfiguration *mem;
 590
 591     if (!visit_type_MemorySizeConfiguration(v, name, &mem, errp)) {
 592         return;
 593     }
 594
 595     if (!mem->has_size) {
 596         mem->has_size = true;
 597         mem->size = mc->default_ram_size;
 598     }
 599     mem->size = QEMU_ALIGN_UP(mem->size, 8192);
 600     if (mc->fixup_ram_size) {
 601         mem->size = mc->fixup_ram_size(mem->size);
 602     }
 603     if ((ram_addr_t)mem->size != mem->size) {
 604         error_setg(errp, "ram size too large");
 605         goto out_free;
 606     }
 607
 608     if (mem->has_max_size) {
 609         if (mem->max_size < mem->size) {
 610             error_setg(errp, "invalid value of maxmem: "
 611                        "maximum memory size (0x%" PRIx64 ") must be at least "
 612                        "the initial memory size (0x%" PRIx64 ")",
 613                        mem->max_size, mem->size);
 614             goto out_free;
 615         }
 616         if (mem->has_slots && mem->slots && mem->max_size == mem->size) {
 617             error_setg(errp, "invalid value of maxmem: "
 618                        "memory slots were specified but maximum memory size "
 619                        "(0x%" PRIx64 ") is equal to the initial memory size "
 620                        "(0x%" PRIx64 ")", mem->max_size, mem->size);
 621             goto out_free;
 622         }
 623         ms->maxram_size = mem->max_size;
 624     } else {
 625         if (mem->has_slots) {
 626             error_setg(errp, "slots specified but no max-size");
 627             goto out_free;
 628         }
 629         ms->maxram_size = mem->size;
 630     }
 631     ms->ram_size = mem->size;
 632     ms->ram_slots = mem->has_slots ? mem->slots : 0;
 633 out_free:
 634     qapi_free_MemorySizeConfiguration(mem);
 635 }
 636
 637 static char *machine_get_nvdimm_persistence(Object *obj, Error **errp)
 638 {
 639     MachineState *ms = MACHINE(obj);
 640
 641     return g_strdup(ms->nvdimms_state->persistence_string);
 642 }
 643
 644 static void machine_set_nvdimm_persistence(Object *obj, const char *value,
 645                                            Error **errp)
 646 {
 647     MachineState *ms = MACHINE(obj);
 648     NVDIMMState *nvdimms_state = ms->nvdimms_state;
 649
 650     if (strcmp(value, "cpu") == 0) {
 651         nvdimms_state->persistence = 3;
 652     } else if (strcmp(value, "mem-ctrl") == 0) {
 653         nvdimms_state->persistence = 2;
 654     } else {
 655         error_setg(errp, "-machine nvdimm-persistence=%s: unsupported option",
 656                    value);
 657         return;
 658     }
 659
 660     g_free(nvdimms_state->persistence_string);
 661     nvdimms_state->persistence_string = g_strdup(value);
 662 }
 663
 664 void machine_class_allow_dynamic_sysbus_dev(MachineClass *mc, const char *type)
 665 {
 666     QAPI_LIST_PREPEND(mc->allowed_dynamic_sysbus_devices, g_strdup(type));
 667 }
 668
 669 bool device_is_dynamic_sysbus(MachineClass *mc, DeviceState *dev)
 670 {
 671     Object *obj = OBJECT(dev);
 672
 673     if (!object_dynamic_cast(obj, TYPE_SYS_BUS_DEVICE)) {
 674         return false;
 675     }
 676
 677     return device_type_is_dynamic_sysbus(mc, object_get_typename(obj));
 678 }
 679
 680 bool device_type_is_dynamic_sysbus(MachineClass *mc, const char *type)
 681 {
 682     bool allowed = false;
 683     strList *wl;
 684     ObjectClass *klass = object_class_by_name(type);
 685
 686     for (wl = mc->allowed_dynamic_sysbus_devices;
 687          !allowed && wl;
 688          wl = wl->next) {
 689         allowed |= !!object_class_dynamic_cast(klass, wl->value);
 690     }
 691
 692     return allowed;
 693 }
 694
 695 static char *machine_get_audiodev(Object *obj, Error **errp)
 696 {
 697     MachineState *ms = MACHINE(obj);
 698
 699     return g_strdup(ms->audiodev);
 700 }
 701
 702 static void machine_set_audiodev(Object *obj, const char *value,
 703                                  Error **errp)
 704 {
 705     MachineState *ms = MACHINE(obj);
 706
 707     if (!audio_state_by_name(value, errp)) {
 708         return;
 709     }
 710
 711     g_free(ms->audiodev);
 712     ms->audiodev = g_strdup(value);
 713 }
 714
 715 HotpluggableCPUList *machine_query_hotpluggable_cpus(MachineState *machine)
 716 {
 717     int i;
 718     HotpluggableCPUList *head = NULL;
 719     MachineClass *mc = MACHINE_GET_CLASS(machine);
 720
 721     /* force board to initialize possible_cpus if it hasn't been done yet */
 722     mc->possible_cpu_arch_ids(machine);
 723
 724     for (i = 0; i < machine->possible_cpus->len; i++) {
 725         CPUState *cpu;
 726         HotpluggableCPU *cpu_item = g_new0(typeof(*cpu_item), 1);
 727
 728         cpu_item->type = g_strdup(machine->possible_cpus->cpus[i].type);
 729         cpu_item->vcpus_count = machine->possible_cpus->cpus[i].vcpus_count;
 730         cpu_item->props = g_memdup(&machine->possible_cpus->cpus[i].props,
 731                                    sizeof(*cpu_item->props));
 732
 733         cpu = machine->possible_cpus->cpus[i].cpu;
 734         if (cpu) {
 735             cpu_item->qom_path = object_get_canonical_path(OBJECT(cpu));
 736         }
 737         QAPI_LIST_PREPEND(head, cpu_item);
 738     }
 739     return head;
 740 }
 741
 742 /**
 743  * machine_set_cpu_numa_node:
 744  * @machine: machine object to modify
 745  * @props: specifies which cpu objects to assign to
 746  *         numa node specified by @props.node_id
 747  * @errp: if an error occurs, a pointer to an area to store the error
 748  *
 749  * Associate NUMA node specified by @props.node_id with cpu slots that
 750  * match socket/core/thread-ids specified by @props. It's recommended to use
 751  * query-hotpluggable-cpus.props values to specify affected cpu slots,
 752  * which would lead to exact 1:1 mapping of cpu slots to NUMA node.
 753  *
 754  * However for CLI convenience it's possible to pass in subset of properties,
 755  * which would affect all cpu slots that match it.
 756  * Ex for pc machine:
 757  *    -smp 4,cores=2,sockets=2 -numa node,nodeid=0 -numa node,nodeid=1 \
 758  *    -numa cpu,node-id=0,socket_id=0 \
 759  *    -numa cpu,node-id=1,socket_id=1
 760  * will assign all child cores of socket 0 to node 0 and
 761  * of socket 1 to node 1.
 762  *
 763  * On attempt of reassigning (already assigned) cpu slot to another NUMA node,
 764  * return error.
 765  * Empty subset is disallowed and function will return with error in this case.
 766  */
 767 void machine_set_cpu_numa_node(MachineState *machine,
 768                                const CpuInstanceProperties *props, Error **errp)
 769 {
 770     MachineClass *mc = MACHINE_GET_CLASS(machine);
 771     NodeInfo *numa_info = machine->numa_state->nodes;
 772     bool match = false;
 773     int i;
 774
 775     if (!mc->possible_cpu_arch_ids) {
 776         error_setg(errp, "mapping of CPUs to NUMA node is not supported");
 777         return;
 778     }
 779
 780     /* disabling node mapping is not supported, forbid it */
 781     assert(props->has_node_id);
 782
 783     /* force board to initialize possible_cpus if it hasn't been done yet */
 784     mc->possible_cpu_arch_ids(machine);
 785
 786     for (i = 0; i < machine->possible_cpus->len; i++) {
 787         CPUArchId *slot = &machine->possible_cpus->cpus[i];
 788
 789         /* reject unsupported by board properties */
 790         if (props->has_thread_id && !slot->props.has_thread_id) {
 791             error_setg(errp, "thread-id is not supported");
 792             return;
 793         }
 794
 795         if (props->has_core_id && !slot->props.has_core_id) {
 796             error_setg(errp, "core-id is not supported");
 797             return;
 798         }
 799
 800         if (props->has_cluster_id && !slot->props.has_cluster_id) {
 801             error_setg(errp, "cluster-id is not supported");
 802             return;
 803         }
 804
 805         if (props->has_socket_id && !slot->props.has_socket_id) {
 806             error_setg(errp, "socket-id is not supported");
 807             return;
 808         }
 809
 810         if (props->has_die_id && !slot->props.has_die_id) {
 811             error_setg(errp, "die-id is not supported");
 812             return;
 813         }
 814
 815         /* skip slots with explicit mismatch */
 816         if (props->has_thread_id && props->thread_id != slot->props.thread_id) {
 817                 continue;
 818         }
 819
 820         if (props->has_core_id && props->core_id != slot->props.core_id) {
 821                 continue;
 822         }
 823
 824         if (props->has_cluster_id &&
 825             props->cluster_id != slot->props.cluster_id) {
 826                 continue;
 827         }
 828
 829         if (props->has_die_id && props->die_id != slot->props.die_id) {
 830                 continue;
 831         }
 832
 833         if (props->has_socket_id && props->socket_id != slot->props.socket_id) {
 834                 continue;
 835         }
 836
 837         /* reject assignment if slot is already assigned, for compatibility
 838          * of legacy cpu_index mapping with SPAPR core based mapping do not
 839          * error out if cpu thread and matched core have the same node-id */
 840         if (slot->props.has_node_id &&
 841             slot->props.node_id != props->node_id) {
 842             error_setg(errp, "CPU is already assigned to node-id: %" PRId64,
 843                        slot->props.node_id);
 844             return;
 845         }
 846
 847         /* assign slot to node as it's matched '-numa cpu' key */
 848         match = true;
 849         slot->props.node_id = props->node_id;
 850         slot->props.has_node_id = props->has_node_id;
 851
 852         if (machine->numa_state->hmat_enabled) {
 853             if ((numa_info[props->node_id].initiator < MAX_NODES) &&
 854                 (props->node_id != numa_info[props->node_id].initiator)) {
 855                 error_setg(errp, "The initiator of CPU NUMA node %" PRId64
 856                            " should be itself (got %" PRIu16 ")",
 857                            props->node_id, numa_info[props->node_id].initiator);
 858                 return;
 859             }
 860             numa_info[props->node_id].has_cpu = true;
 861             numa_info[props->node_id].initiator = props->node_id;
 862         }
 863     }
 864
 865     if (!match) {
 866         error_setg(errp, "no match found");
 867     }
 868 }
 869
 870 static void machine_get_smp(Object *obj, Visitor *v, const char *name,
 871                             void *opaque, Error **errp)
 872 {
 873     MachineState *ms = MACHINE(obj);
 874     SMPConfiguration *config = &(SMPConfiguration){
 875         .has_cpus = true, .cpus = ms->smp.cpus,
 876         .has_drawers = true, .drawers = ms->smp.drawers,
 877         .has_books = true, .books = ms->smp.books,
 878         .has_sockets = true, .sockets = ms->smp.sockets,
 879         .has_dies = true, .dies = ms->smp.dies,
 880         .has_clusters = true, .clusters = ms->smp.clusters,
 881         .has_cores = true, .cores = ms->smp.cores,
 882         .has_threads = true, .threads = ms->smp.threads,
 883         .has_maxcpus = true, .maxcpus = ms->smp.max_cpus,
 884     };
 885
 886     if (!visit_type_SMPConfiguration(v, name, &config, &error_abort)) {
 887         return;
 888     }
 889 }
 890
 891 static void machine_set_smp(Object *obj, Visitor *v, const char *name,
 892                             void *opaque, Error **errp)
 893 {
 894     MachineState *ms = MACHINE(obj);
 895     g_autoptr(SMPConfiguration) config = NULL;
 896
 897     if (!visit_type_SMPConfiguration(v, name, &config, errp)) {
 898         return;
 899     }
 900
 901     machine_parse_smp_config(ms, config, errp);
 902 }
 903
 904 static void machine_get_boot(Object *obj, Visitor *v, const char *name,
 905                             void *opaque, Error **errp)
 906 {
 907     MachineState *ms = MACHINE(obj);
 908     BootConfiguration *config = &ms->boot_config;
 909     visit_type_BootConfiguration(v, name, &config, &error_abort);
 910 }
 911
 912 static void machine_free_boot_config(MachineState *ms)
 913 {
 914     g_free(ms->boot_config.order);
 915     g_free(ms->boot_config.once);
 916     g_free(ms->boot_config.splash);
 917 }
 918
 919 static void machine_copy_boot_config(MachineState *ms, BootConfiguration *config)
 920 {
 921     MachineClass *machine_class = MACHINE_GET_CLASS(ms);
 922
 923     machine_free_boot_config(ms);
 924     ms->boot_config = *config;
 925     if (!config->order) {
 926         ms->boot_config.order = g_strdup(machine_class->default_boot_order);
 927     }
 928 }
 929
 930 static void machine_set_boot(Object *obj, Visitor *v, const char *name,
 931                             void *opaque, Error **errp)
 932 {
 933     ERRP_GUARD();
 934     MachineState *ms = MACHINE(obj);
 935     BootConfiguration *config = NULL;
 936
 937     if (!visit_type_BootConfiguration(v, name, &config, errp)) {
 938         return;
 939     }
 940     if (config->order) {
 941         validate_bootdevices(config->order, errp);
 942         if (*errp) {
 943             goto out_free;
 944         }
 945     }
 946     if (config->once) {
 947         validate_bootdevices(config->once, errp);
 948         if (*errp) {
 949             goto out_free;
 950         }
 951     }
 952
 953     machine_copy_boot_config(ms, config);
 954     /* Strings live in ms->boot_config.  */
 955     free(config);
 956     return;
 957
 958 out_free:
 959     qapi_free_BootConfiguration(config);
 960 }
 961
 962 void machine_add_audiodev_property(MachineClass *mc)
 963 {
 964     ObjectClass *oc = OBJECT_CLASS(mc);
 965
 966     object_class_property_add_str(oc, "audiodev",
 967                                   machine_get_audiodev,
 968                                   machine_set_audiodev);
 969     object_class_property_set_description(oc, "audiodev",
 970                                           "Audiodev to use for default machine devices");
 971 }
 972
 973 static void machine_class_init(ObjectClass *oc, void *data)
 974 {
 975     MachineClass *mc = MACHINE_CLASS(oc);
 976
 977     /* Default 128 MB as guest ram size */
 978     mc->default_ram_size = 128 * MiB;
 979     mc->rom_file_has_mr = true;
 980
 981     /* numa node memory size aligned on 8MB by default.
 982      * On Linux, each node's border has to be 8MB aligned
 983      */
 984     mc->numa_mem_align_shift = 23;
 985
 986     object_class_property_add_str(oc, "kernel",
 987         machine_get_kernel, machine_set_kernel);
 988     object_class_property_set_description(oc, "kernel",
 989         "Linux kernel image file");
 990
 991     object_class_property_add_str(oc, "initrd",
 992         machine_get_initrd, machine_set_initrd);
 993     object_class_property_set_description(oc, "initrd",
 994         "Linux initial ramdisk file");
 995
 996     object_class_property_add_str(oc, "append",
 997         machine_get_append, machine_set_append);
 998     object_class_property_set_description(oc, "append",
 999         "Linux kernel command line");
1000
1001     object_class_property_add_str(oc, "dtb",
1002         machine_get_dtb, machine_set_dtb);
1003     object_class_property_set_description(oc, "dtb",
1004         "Linux kernel device tree file");
1005
1006     object_class_property_add_str(oc, "dumpdtb",
1007         machine_get_dumpdtb, machine_set_dumpdtb);
1008     object_class_property_set_description(oc, "dumpdtb",
1009         "Dump current dtb to a file and quit");
1010
1011     object_class_property_add(oc, "boot", "BootConfiguration",
1012         machine_get_boot, machine_set_boot,
1013         NULL, NULL);
1014     object_class_property_set_description(oc, "boot",
1015         "Boot configuration");
1016
1017     object_class_property_add(oc, "smp", "SMPConfiguration",
1018         machine_get_smp, machine_set_smp,
1019         NULL, NULL);
1020     object_class_property_set_description(oc, "smp",
1021         "CPU topology");
1022
1023     object_class_property_add(oc, "phandle-start", "int",
1024         machine_get_phandle_start, machine_set_phandle_start,
1025         NULL, NULL);
1026     object_class_property_set_description(oc, "phandle-start",
1027         "The first phandle ID we may generate dynamically");
1028
1029     object_class_property_add_str(oc, "dt-compatible",
1030         machine_get_dt_compatible, machine_set_dt_compatible);
1031     object_class_property_set_description(oc, "dt-compatible",
1032         "Overrides the \"compatible\" property of the dt root node");
1033
1034     object_class_property_add_bool(oc, "dump-guest-core",
1035         machine_get_dump_guest_core, machine_set_dump_guest_core);
1036     object_class_property_set_description(oc, "dump-guest-core",
1037         "Include guest memory in a core dump");
1038
1039     object_class_property_add_bool(oc, "mem-merge",
1040         machine_get_mem_merge, machine_set_mem_merge);
1041     object_class_property_set_description(oc, "mem-merge",
1042         "Enable/disable memory merge support");
1043
1044     object_class_property_add_bool(oc, "usb",
1045         machine_get_usb, machine_set_usb);
1046     object_class_property_set_description(oc, "usb",
1047         "Set on/off to enable/disable usb");
1048
1049     object_class_property_add_bool(oc, "graphics",
1050         machine_get_graphics, machine_set_graphics);
1051     object_class_property_set_description(oc, "graphics",
1052         "Set on/off to enable/disable graphics emulation");
1053
1054     object_class_property_add_str(oc, "firmware",
1055         machine_get_firmware, machine_set_firmware);
1056     object_class_property_set_description(oc, "firmware",
1057         "Firmware image");
1058
1059     object_class_property_add_bool(oc, "suppress-vmdesc",
1060         machine_get_suppress_vmdesc, machine_set_suppress_vmdesc);
1061     object_class_property_set_description(oc, "suppress-vmdesc",
1062         "Set on to disable self-describing migration");
1063
1064     object_class_property_add_link(oc, "confidential-guest-support",
1065                                    TYPE_CONFIDENTIAL_GUEST_SUPPORT,
1066                                    offsetof(MachineState, cgs),
1067                                    machine_check_confidential_guest_support,
1068                                    OBJ_PROP_LINK_STRONG);
1069     object_class_property_set_description(oc, "confidential-guest-support",
1070                                           "Set confidential guest scheme to support");
1071
1072     /* For compatibility */
1073     object_class_property_add_str(oc, "memory-encryption",
1074         machine_get_memory_encryption, machine_set_memory_encryption);
1075     object_class_property_set_description(oc, "memory-encryption",
1076         "Set memory encryption object to use");
1077
1078     object_class_property_add_link(oc, "memory-backend", TYPE_MEMORY_BACKEND,
1079                                    offsetof(MachineState, memdev), object_property_allow_set_link,
1080                                    OBJ_PROP_LINK_STRONG);
1081     object_class_property_set_description(oc, "memory-backend",
1082                                           "Set RAM backend"
1083                                           "Valid value is ID of hostmem based backend");
1084
1085     object_class_property_add(oc, "memory", "MemorySizeConfiguration",
1086         machine_get_mem, machine_set_mem,
1087         NULL, NULL);
1088     object_class_property_set_description(oc, "memory",
1089         "Memory size configuration");
1090 }
1091
1092 static void machine_class_base_init(ObjectClass *oc, void *data)
1093 {
1094     MachineClass *mc = MACHINE_CLASS(oc);
1095     mc->max_cpus = mc->max_cpus ?: 1;
1096     mc->min_cpus = mc->min_cpus ?: 1;
1097     mc->default_cpus = mc->default_cpus ?: 1;
1098
1099     if (!object_class_is_abstract(oc)) {
1100         const char *cname = object_class_get_name(oc);
1101         assert(g_str_has_suffix(cname, TYPE_MACHINE_SUFFIX));
1102         mc->name = g_strndup(cname,
1103                             strlen(cname) - strlen(TYPE_MACHINE_SUFFIX));
1104         mc->compat_props = g_ptr_array_new();
1105     }
1106 }
1107
1108 static void machine_initfn(Object *obj)
1109 {
1110     MachineState *ms = MACHINE(obj);
1111     MachineClass *mc = MACHINE_GET_CLASS(obj);
1112
1113     container_get(obj, "/peripheral");
1114     container_get(obj, "/peripheral-anon");
1115
1116     ms->dump_guest_core = true;
1117     ms->mem_merge = true;
1118     ms->enable_graphics = true;
1119     ms->kernel_cmdline = g_strdup("");
1120     ms->ram_size = mc->default_ram_size;
1121     ms->maxram_size = mc->default_ram_size;
1122
1123     if (mc->nvdimm_supported) {
1124         ms->nvdimms_state = g_new0(NVDIMMState, 1);
1125         object_property_add_bool(obj, "nvdimm",
1126                                  machine_get_nvdimm, machine_set_nvdimm);
1127         object_property_set_description(obj, "nvdimm",
1128                                         "Set on/off to enable/disable "
1129                                         "NVDIMM instantiation");
1130
1131         object_property_add_str(obj, "nvdimm-persistence",
1132                                 machine_get_nvdimm_persistence,
1133                                 machine_set_nvdimm_persistence);
1134         object_property_set_description(obj, "nvdimm-persistence",
1135                                         "Set NVDIMM persistence"
1136                                         "Valid values are cpu, mem-ctrl");
1137     }
1138
1139     if (mc->cpu_index_to_instance_props && mc->get_default_cpu_node_id) {
1140         ms->numa_state = g_new0(NumaState, 1);
1141         object_property_add_bool(obj, "hmat",
1142                                  machine_get_hmat, machine_set_hmat);
1143         object_property_set_description(obj, "hmat",
1144                                         "Set on/off to enable/disable "
1145                                         "ACPI Heterogeneous Memory Attribute "
1146                                         "Table (HMAT)");
1147     }
1148
1149     /* default to mc->default_cpus */
1150     ms->smp.cpus = mc->default_cpus;
1151     ms->smp.max_cpus = mc->default_cpus;
1152     ms->smp.drawers = 1;
1153     ms->smp.books = 1;
1154     ms->smp.sockets = 1;
1155     ms->smp.dies = 1;
1156     ms->smp.clusters = 1;
1157     ms->smp.cores = 1;
1158     ms->smp.threads = 1;
1159
1160     machine_copy_boot_config(ms, &(BootConfiguration){ 0 });
1161 }
1162
1163 static void machine_finalize(Object *obj)
1164 {
1165     MachineState *ms = MACHINE(obj);
1166
1167     machine_free_boot_config(ms);
1168     g_free(ms->kernel_filename);
1169     g_free(ms->initrd_filename);
1170     g_free(ms->kernel_cmdline);
1171     g_free(ms->dtb);
1172     g_free(ms->dumpdtb);
1173     g_free(ms->dt_compatible);
1174     g_free(ms->firmware);
1175     g_free(ms->device_memory);
1176     g_free(ms->nvdimms_state);
1177     g_free(ms->numa_state);
1178     g_free(ms->audiodev);
1179 }
1180
1181 bool machine_usb(MachineState *machine)
1182 {
1183     return machine->usb;
1184 }
1185
1186 int machine_phandle_start(MachineState *machine)
1187 {
1188     return machine->phandle_start;
1189 }
1190
1191 bool machine_dump_guest_core(MachineState *machine)
1192 {
1193     return machine->dump_guest_core;
1194 }
1195
1196 bool machine_mem_merge(MachineState *machine)
1197 {
1198     return machine->mem_merge;
1199 }
1200
1201 static char *cpu_slot_to_string(const CPUArchId *cpu)
1202 {
1203     GString *s = g_string_new(NULL);
1204     if (cpu->props.has_socket_id) {
1205         g_string_append_printf(s, "socket-id: %"PRId64, cpu->props.socket_id);
1206     }
1207     if (cpu->props.has_die_id) {
1208         if (s->len) {
1209             g_string_append_printf(s, ", ");
1210         }
1211         g_string_append_printf(s, "die-id: %"PRId64, cpu->props.die_id);
1212     }
1213     if (cpu->props.has_cluster_id) {
1214         if (s->len) {
1215             g_string_append_printf(s, ", ");
1216         }
1217         g_string_append_printf(s, "cluster-id: %"PRId64, cpu->props.cluster_id);
1218     }
1219     if (cpu->props.has_core_id) {
1220         if (s->len) {
1221             g_string_append_printf(s, ", ");
1222         }
1223         g_string_append_printf(s, "core-id: %"PRId64, cpu->props.core_id);
1224     }
1225     if (cpu->props.has_thread_id) {
1226         if (s->len) {
1227             g_string_append_printf(s, ", ");
1228         }
1229         g_string_append_printf(s, "thread-id: %"PRId64, cpu->props.thread_id);
1230     }
1231     return g_string_free(s, false);
1232 }
1233
1234 static void numa_validate_initiator(NumaState *numa_state)
1235 {
1236     int i;
1237     NodeInfo *numa_info = numa_state->nodes;
1238
1239     for (i = 0; i < numa_state->num_nodes; i++) {
1240         if (numa_info[i].initiator == MAX_NODES) {
1241             continue;
1242         }
1243
1244         if (!numa_info[numa_info[i].initiator].present) {
1245             error_report("NUMA node %" PRIu16 " is missing, use "
1246                          "'-numa node' option to declare it first",
1247                          numa_info[i].initiator);
1248             exit(1);
1249         }
1250
1251         if (!numa_info[numa_info[i].initiator].has_cpu) {
1252             error_report("The initiator of NUMA node %d is invalid", i);
1253             exit(1);
1254         }
1255     }
1256 }
1257
1258 static void machine_numa_finish_cpu_init(MachineState *machine)
1259 {
1260     int i;
1261     bool default_mapping;
1262     GString *s = g_string_new(NULL);
1263     MachineClass *mc = MACHINE_GET_CLASS(machine);
1264     const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(machine);
1265
1266     assert(machine->numa_state->num_nodes);
1267     for (i = 0; i < possible_cpus->len; i++) {
1268         if (possible_cpus->cpus[i].props.has_node_id) {
1269             break;
1270         }
1271     }
1272     default_mapping = (i == possible_cpus->len);
1273
1274     for (i = 0; i < possible_cpus->len; i++) {
1275         const CPUArchId *cpu_slot = &possible_cpus->cpus[i];
1276
1277         if (!cpu_slot->props.has_node_id) {
1278             /* fetch default mapping from board and enable it */
1279             CpuInstanceProperties props = cpu_slot->props;
1280
1281             props.node_id = mc->get_default_cpu_node_id(machine, i);
1282             if (!default_mapping) {
1283                 /* record slots with not set mapping,
1284                  * TODO: make it hard error in future */
1285                 char *cpu_str = cpu_slot_to_string(cpu_slot);
1286                 g_string_append_printf(s, "%sCPU %d [%s]",
1287                                        s->len ? ", " : "", i, cpu_str);
1288                 g_free(cpu_str);
1289
1290                 /* non mapped cpus used to fallback to node 0 */
1291                 props.node_id = 0;
1292             }
1293
1294             props.has_node_id = true;
1295             machine_set_cpu_numa_node(machine, &props, &error_fatal);
1296         }
1297     }
1298
1299     if (machine->numa_state->hmat_enabled) {
1300         numa_validate_initiator(machine->numa_state);
1301     }
1302
1303     if (s->len && !qtest_enabled()) {
1304         warn_report("CPU(s) not present in any NUMA nodes: %s",
1305                     s->str);
1306         warn_report("All CPU(s) up to maxcpus should be described "
1307                     "in NUMA config, ability to start up with partial NUMA "
1308                     "mappings is obsoleted and will be removed in future");
1309     }
1310     g_string_free(s, true);
1311 }
1312
1313 static void validate_cpu_cluster_to_numa_boundary(MachineState *ms)
1314 {
1315     MachineClass *mc = MACHINE_GET_CLASS(ms);
1316     NumaState *state = ms->numa_state;
1317     const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms);
1318     const CPUArchId *cpus = possible_cpus->cpus;
1319     int i, j;
1320
1321     if (qtest_enabled() || state->num_nodes <= 1 || possible_cpus->len <= 1) {
1322         return;
1323     }
1324
1325     /*
1326      * The Linux scheduling domain can't be parsed when the multiple CPUs
1327      * in one cluster have been associated with different NUMA nodes. However,
1328      * it's fine to associate one NUMA node with CPUs in different clusters.
1329      */
1330     for (i = 0; i < possible_cpus->len; i++) {
1331         for (j = i + 1; j < possible_cpus->len; j++) {
1332             if (cpus[i].props.has_socket_id &&
1333                 cpus[i].props.has_cluster_id &&
1334                 cpus[i].props.has_node_id &&
1335                 cpus[j].props.has_socket_id &&
1336                 cpus[j].props.has_cluster_id &&
1337                 cpus[j].props.has_node_id &&
1338                 cpus[i].props.socket_id == cpus[j].props.socket_id &&
1339                 cpus[i].props.cluster_id == cpus[j].props.cluster_id &&
1340                 cpus[i].props.node_id != cpus[j].props.node_id) {
1341                 warn_report("CPU-%d and CPU-%d in socket-%" PRId64 "-cluster-%" PRId64
1342                              " have been associated with node-%" PRId64 " and node-%" PRId64
1343                              " respectively. It can cause OSes like Linux to"
1344                              " misbehave", i, j, cpus[i].props.socket_id,
1345                              cpus[i].props.cluster_id, cpus[i].props.node_id,
1346                              cpus[j].props.node_id);
1347             }
1348         }
1349     }
1350 }
1351
1352 MemoryRegion *machine_consume_memdev(MachineState *machine,
1353                                      HostMemoryBackend *backend)
1354 {
1355     MemoryRegion *ret = host_memory_backend_get_memory(backend);
1356
1357     if (host_memory_backend_is_mapped(backend)) {
1358         error_report("memory backend %s can't be used multiple times.",
1359                      object_get_canonical_path_component(OBJECT(backend)));
1360         exit(EXIT_FAILURE);
1361     }
1362     host_memory_backend_set_mapped(backend, true);
1363     vmstate_register_ram_global(ret);
1364     return ret;
1365 }
1366
1367 static bool create_default_memdev(MachineState *ms, const char *path, Error **errp)
1368 {
1369     Object *obj;
1370     MachineClass *mc = MACHINE_GET_CLASS(ms);
1371     bool r = false;
1372
1373     obj = object_new(path ? TYPE_MEMORY_BACKEND_FILE : TYPE_MEMORY_BACKEND_RAM);
1374     if (path) {
1375         if (!object_property_set_str(obj, "mem-path", path, errp)) {
1376             goto out;
1377         }
1378     }
1379     if (!object_property_set_int(obj, "size", ms->ram_size, errp)) {
1380         goto out;
1381     }
1382     object_property_add_child(object_get_objects_root(), mc->default_ram_id,
1383                               obj);
1384     /* Ensure backend's memory region name is equal to mc->default_ram_id */
1385     if (!object_property_set_bool(obj, "x-use-canonical-path-for-ramblock-id",
1386                              false, errp)) {
1387         goto out;
1388     }
1389     if (!user_creatable_complete(USER_CREATABLE(obj), errp)) {
1390         goto out;
1391     }
1392     r = object_property_set_link(OBJECT(ms), "memory-backend", obj, errp);
1393
1394 out:
1395     object_unref(obj);
1396     return r;
1397 }
1398
1399 const char *machine_class_default_cpu_type(MachineClass *mc)
1400 {
1401     if (mc->valid_cpu_types && !mc->valid_cpu_types[1]) {
1402         /* Only a single CPU type allowed: use it as default. */
1403         return mc->valid_cpu_types[0];
1404     }
1405     return mc->default_cpu_type;
1406 }
1407
1408 static bool is_cpu_type_supported(const MachineState *machine, Error **errp)
1409 {
1410     MachineClass *mc = MACHINE_GET_CLASS(machine);
1411     ObjectClass *oc = object_class_by_name(machine->cpu_type);
1412     CPUClass *cc;
1413     int i;
1414
1415     /*
1416      * Check if the user specified CPU type is supported when the valid
1417      * CPU types have been determined. Note that the user specified CPU
1418      * type is provided through '-cpu' option.
1419      */
1420     if (mc->valid_cpu_types) {
1421         assert(mc->valid_cpu_types[0] != NULL);
1422         for (i = 0; mc->valid_cpu_types[i]; i++) {
1423             if (object_class_dynamic_cast(oc, mc->valid_cpu_types[i])) {
1424                 break;
1425             }
1426         }
1427
1428         /* The user specified CPU type isn't valid */
1429         if (!mc->valid_cpu_types[i]) {
1430             g_autofree char *requested = cpu_model_from_type(machine->cpu_type);
1431             error_setg(errp, "Invalid CPU model: %s", requested);
1432             if (!mc->valid_cpu_types[1]) {
1433                 g_autofree char *model = cpu_model_from_type(
1434                                                  mc->valid_cpu_types[0]);
1435                 error_append_hint(errp, "The only valid type is: %s\n", model);
1436             } else {
1437                 error_append_hint(errp, "The valid models are: ");
1438                 for (i = 0; mc->valid_cpu_types[i]; i++) {
1439                     g_autofree char *model = cpu_model_from_type(
1440                                                  mc->valid_cpu_types[i]);
1441                     error_append_hint(errp, "%s%s",
1442                                       model,
1443                                       mc->valid_cpu_types[i + 1] ? ", " : "");
1444                 }
1445                 error_append_hint(errp, "\n");
1446             }
1447
1448             return false;
1449         }
1450     }
1451
1452     /* Check if CPU type is deprecated and warn if so */
1453     cc = CPU_CLASS(oc);
1454     assert(cc != NULL);
1455     if (cc->deprecation_note) {
1456         warn_report("CPU model %s is deprecated -- %s",
1457                     machine->cpu_type, cc->deprecation_note);
1458     }
1459
1460     return true;
1461 }
1462
1463 void machine_run_board_init(MachineState *machine, const char *mem_path, Error **errp)
1464 {
1465     ERRP_GUARD();
1466     MachineClass *machine_class = MACHINE_GET_CLASS(machine);
1467
1468     /* This checkpoint is required by replay to separate prior clock
1469        reading from the other reads, because timer polling functions query
1470        clock values from the log. */
1471     replay_checkpoint(CHECKPOINT_INIT);
1472
1473     if (!xen_enabled()) {
1474         /* On 32-bit hosts, QEMU is limited by virtual address space */
1475         if (machine->ram_size > (2047 << 20) && HOST_LONG_BITS == 32) {
1476             error_setg(errp, "at most 2047 MB RAM can be simulated");
1477             return;
1478         }
1479     }
1480
1481     if (machine->memdev) {
1482         ram_addr_t backend_size = object_property_get_uint(OBJECT(machine->memdev),
1483                                                            "size",  &error_abort);
1484         if (backend_size != machine->ram_size) {
1485             error_setg(errp, "Machine memory size does not match the size of the memory backend");
1486             return;
1487         }
1488     } else if (machine_class->default_ram_id && machine->ram_size &&
1489                numa_uses_legacy_mem()) {
1490         if (object_property_find(object_get_objects_root(),
1491                                  machine_class->default_ram_id)) {
1492             error_setg(errp, "object's id '%s' is reserved for the default"
1493                 " RAM backend, it can't be used for any other purposes",
1494                 machine_class->default_ram_id);
1495             error_append_hint(errp,
1496                 "Change the object's 'id' to something else or disable"
1497                 " automatic creation of the default RAM backend by setting"
1498                 " 'memory-backend=%s' with '-machine'.\n",
1499                 machine_class->default_ram_id);
1500             return;
1501         }
1502         if (!create_default_memdev(current_machine, mem_path, errp)) {
1503             return;
1504         }
1505     }
1506
1507     if (machine->numa_state) {
1508         numa_complete_configuration(machine);
1509         if (machine->numa_state->num_nodes) {
1510             machine_numa_finish_cpu_init(machine);
1511             if (machine_class->cpu_cluster_has_numa_boundary) {
1512                 validate_cpu_cluster_to_numa_boundary(machine);
1513             }
1514         }
1515     }
1516
1517     if (!machine->ram && machine->memdev) {
1518         machine->ram = machine_consume_memdev(machine, machine->memdev);
1519     }
1520
1521     /* Check if the CPU type is supported */
1522     if (machine->cpu_type && !is_cpu_type_supported(machine, errp)) {
1523         return;
1524     }
1525
1526     if (machine->cgs) {
1527         /*
1528          * With confidential guests, the host can't see the real
1529          * contents of RAM, so there's no point in it trying to merge
1530          * areas.
1531          */
1532         machine_set_mem_merge(OBJECT(machine), false, &error_abort);
1533
1534         /*
1535          * Virtio devices can't count on directly accessing guest
1536          * memory, so they need iommu_platform=on to use normal DMA
1537          * mechanisms.  That requires also disabling legacy virtio
1538          * support for those virtio pci devices which allow it.
1539          */
1540         object_register_sugar_prop(TYPE_VIRTIO_PCI, "disable-legacy",
1541                                    "on", true);
1542         object_register_sugar_prop(TYPE_VIRTIO_DEVICE, "iommu_platform",
1543                                    "on", false);
1544     }
1545
1546     accel_init_interfaces(ACCEL_GET_CLASS(machine->accelerator));
1547     machine_class->init(machine);
1548     phase_advance(PHASE_MACHINE_INITIALIZED);
1549 }
1550
1551 static NotifierList machine_init_done_notifiers =
1552     NOTIFIER_LIST_INITIALIZER(machine_init_done_notifiers);
1553
1554 void qemu_add_machine_init_done_notifier(Notifier *notify)
1555 {
1556     notifier_list_add(&machine_init_done_notifiers, notify);
1557     if (phase_check(PHASE_MACHINE_READY)) {
1558         notify->notify(notify, NULL);
1559     }
1560 }
1561
1562 void qemu_remove_machine_init_done_notifier(Notifier *notify)
1563 {
1564     notifier_remove(notify);
1565 }
1566
1567 void qdev_machine_creation_done(void)
1568 {
1569     cpu_synchronize_all_post_init();
1570
1571     if (current_machine->boot_config.once) {
1572         qemu_boot_set(current_machine->boot_config.once, &error_fatal);
1573         qemu_register_reset(restore_boot_order, g_strdup(current_machine->boot_config.order));
1574     }
1575
1576     /*
1577      * ok, initial machine setup is done, starting from now we can
1578      * only create hotpluggable devices
1579      */
1580     phase_advance(PHASE_MACHINE_READY);
1581     qdev_assert_realized_properly();
1582
1583     /* TODO: once all bus devices are qdevified, this should be done
1584      * when bus is created by qdev.c */
1585     /*
1586      * This is where we arrange for the sysbus to be reset when the
1587      * whole simulation is reset. In turn, resetting the sysbus will cause
1588      * all devices hanging off it (and all their child buses, recursively)
1589      * to be reset. Note that this will *not* reset any Device objects
1590      * which are not attached to some part of the qbus tree!
1591      */
1592     qemu_register_resettable(OBJECT(sysbus_get_default()));
1593
1594     notifier_list_notify(&machine_init_done_notifiers, NULL);
1595
1596     if (rom_check_and_register_reset() != 0) {
1597         exit(1);
1598     }
1599
1600     replay_start();
1601
1602     /* This checkpoint is required by replay to separate prior clock
1603        reading from the other reads, because timer polling functions query
1604        clock values from the log. */
1605     replay_checkpoint(CHECKPOINT_RESET);
1606     qemu_system_reset(SHUTDOWN_CAUSE_NONE);
1607     register_global_state();
1608 }
1609
1610 static const TypeInfo machine_info = {
1611     .name = TYPE_MACHINE,
1612     .parent = TYPE_OBJECT,
1613     .abstract = true,
1614     .class_size = sizeof(MachineClass),
1615     .class_init    = machine_class_init,
1616     .class_base_init = machine_class_base_init,
1617     .instance_size = sizeof(MachineState),
1618     .instance_init = machine_initfn,
1619     .instance_finalize = machine_finalize,
1620 };
1621
1622 static void machine_register_types(void)
1623 {
1624     type_register_static(&machine_info);
1625 }
1626
1627 type_init(machine_register_types)