hw/core/machine.c

   1 /*
   2  * QEMU Machine
   3  *
   4  * Copyright (C) 2014 Red Hat Inc
   5  *
   6  * Authors:
   7  *   Marcel Apfelbaum <marcel.a@redhat.com>
   8  *
   9  * This work is licensed under the terms of the GNU GPL, version 2 or later.
  10  * See the COPYING file in the top-level directory.
  11  */
  12
  13 #include "qemu/osdep.h"
  14 #include "qemu/option.h"
  15 #include "qemu/accel.h"
  16 #include "sysemu/replay.h"
  17 #include "qemu/units.h"
  18 #include "hw/boards.h"
  19 #include "hw/loader.h"
  20 #include "qapi/error.h"
  21 #include "qapi/qapi-visit-common.h"
  22 #include "qapi/qapi-visit-machine.h"
  23 #include "qapi/visitor.h"
  24 #include "qom/object_interfaces.h"
  25 #include "hw/sysbus.h"
  26 #include "sysemu/cpus.h"
  27 #include "sysemu/sysemu.h"
  28 #include "sysemu/reset.h"
  29 #include "sysemu/runstate.h"
  30 #include "sysemu/numa.h"
  31 #include "sysemu/xen.h"
  32 #include "qemu/error-report.h"
  33 #include "sysemu/qtest.h"
  34 #include "hw/pci/pci.h"
  35 #include "hw/mem/nvdimm.h"
  36 #include "migration/global_state.h"
  37 #include "migration/vmstate.h"
  38 #include "exec/confidential-guest-support.h"
  39 #include "hw/virtio/virtio.h"
  40 #include "hw/virtio/virtio-pci.h"
  41
  42 GlobalProperty hw_compat_7_2[] = {
  43     { "virtio-mem", "x-early-migration", "false" },
  44 };
  45 const size_t hw_compat_7_2_len = G_N_ELEMENTS(hw_compat_7_2);
  46
  47 GlobalProperty hw_compat_7_1[] = {
  48     { "virtio-device", "queue_reset", "false" },
  49     { "virtio-rng-pci", "vectors", "0" },
  50 };
  51 const size_t hw_compat_7_1_len = G_N_ELEMENTS(hw_compat_7_1);
  52
  53 GlobalProperty hw_compat_7_0[] = {
  54     { "arm-gicv3-common", "force-8-bit-prio", "on" },
  55     { "nvme-ns", "eui64-default", "on"},
  56 };
  57 const size_t hw_compat_7_0_len = G_N_ELEMENTS(hw_compat_7_0);
  58
  59 GlobalProperty hw_compat_6_2[] = {
  60     { "PIIX4_PM", "x-not-migrate-acpi-index", "on"},
  61 };
  62 const size_t hw_compat_6_2_len = G_N_ELEMENTS(hw_compat_6_2);
  63
  64 GlobalProperty hw_compat_6_1[] = {
  65     { "vhost-user-vsock-device", "seqpacket", "off" },
  66     { "nvme-ns", "shared", "off" },
  67 };
  68 const size_t hw_compat_6_1_len = G_N_ELEMENTS(hw_compat_6_1);
  69
  70 GlobalProperty hw_compat_6_0[] = {
  71     { "gpex-pcihost", "allow-unmapped-accesses", "false" },
  72     { "i8042", "extended-state", "false"},
  73     { "nvme-ns", "eui64-default", "off"},
  74     { "e1000", "init-vet", "off" },
  75     { "e1000e", "init-vet", "off" },
  76     { "vhost-vsock-device", "seqpacket", "off" },
  77 };
  78 const size_t hw_compat_6_0_len = G_N_ELEMENTS(hw_compat_6_0);
  79
  80 GlobalProperty hw_compat_5_2[] = {
  81     { "ICH9-LPC", "smm-compat", "on"},
  82     { "PIIX4_PM", "smm-compat", "on"},
  83     { "virtio-blk-device", "report-discard-granularity", "off" },
  84     { "virtio-net-pci-base", "vectors", "3"},
  85 };
  86 const size_t hw_compat_5_2_len = G_N_ELEMENTS(hw_compat_5_2);
  87
  88 GlobalProperty hw_compat_5_1[] = {
  89     { "vhost-scsi", "num_queues", "1"},
  90     { "vhost-user-blk", "num-queues", "1"},
  91     { "vhost-user-scsi", "num_queues", "1"},
  92     { "virtio-blk-device", "num-queues", "1"},
  93     { "virtio-scsi-device", "num_queues", "1"},
  94     { "nvme", "use-intel-id", "on"},
  95     { "pvpanic", "events", "1"}, /* PVPANIC_PANICKED */
  96     { "pl011", "migrate-clk", "off" },
  97     { "virtio-pci", "x-ats-page-aligned", "off"},
  98 };
  99 const size_t hw_compat_5_1_len = G_N_ELEMENTS(hw_compat_5_1);
 100
 101 GlobalProperty hw_compat_5_0[] = {
 102     { "pci-host-bridge", "x-config-reg-migration-enabled", "off" },
 103     { "virtio-balloon-device", "page-poison", "false" },
 104     { "vmport", "x-read-set-eax", "off" },
 105     { "vmport", "x-signal-unsupported-cmd", "off" },
 106     { "vmport", "x-report-vmx-type", "off" },
 107     { "vmport", "x-cmds-v2", "off" },
 108     { "virtio-device", "x-disable-legacy-check", "true" },
 109 };
 110 const size_t hw_compat_5_0_len = G_N_ELEMENTS(hw_compat_5_0);
 111
 112 GlobalProperty hw_compat_4_2[] = {
 113     { "virtio-blk-device", "queue-size", "128"},
 114     { "virtio-scsi-device", "virtqueue_size", "128"},
 115     { "virtio-blk-device", "x-enable-wce-if-config-wce", "off" },
 116     { "virtio-blk-device", "seg-max-adjust", "off"},
 117     { "virtio-scsi-device", "seg_max_adjust", "off"},
 118     { "vhost-blk-device", "seg_max_adjust", "off"},
 119     { "usb-host", "suppress-remote-wake", "off" },
 120     { "usb-redir", "suppress-remote-wake", "off" },
 121     { "qxl", "revision", "4" },
 122     { "qxl-vga", "revision", "4" },
 123     { "fw_cfg", "acpi-mr-restore", "false" },
 124     { "virtio-device", "use-disabled-flag", "false" },
 125 };
 126 const size_t hw_compat_4_2_len = G_N_ELEMENTS(hw_compat_4_2);
 127
 128 GlobalProperty hw_compat_4_1[] = {
 129     { "virtio-pci", "x-pcie-flr-init", "off" },
 130 };
 131 const size_t hw_compat_4_1_len = G_N_ELEMENTS(hw_compat_4_1);
 132
 133 GlobalProperty hw_compat_4_0[] = {
 134     { "VGA",            "edid", "false" },
 135     { "secondary-vga",  "edid", "false" },
 136     { "bochs-display",  "edid", "false" },
 137     { "virtio-vga",     "edid", "false" },
 138     { "virtio-gpu-device", "edid", "false" },
 139     { "virtio-device", "use-started", "false" },
 140     { "virtio-balloon-device", "qemu-4-0-config-size", "true" },
 141     { "pl031", "migrate-tick-offset", "false" },
 142 };
 143 const size_t hw_compat_4_0_len = G_N_ELEMENTS(hw_compat_4_0);
 144
 145 GlobalProperty hw_compat_3_1[] = {
 146     { "pcie-root-port", "x-speed", "2_5" },
 147     { "pcie-root-port", "x-width", "1" },
 148     { "memory-backend-file", "x-use-canonical-path-for-ramblock-id", "true" },
 149     { "memory-backend-memfd", "x-use-canonical-path-for-ramblock-id", "true" },
 150     { "tpm-crb", "ppi", "false" },
 151     { "tpm-tis", "ppi", "false" },
 152     { "usb-kbd", "serial", "42" },
 153     { "usb-mouse", "serial", "42" },
 154     { "usb-tablet", "serial", "42" },
 155     { "virtio-blk-device", "discard", "false" },
 156     { "virtio-blk-device", "write-zeroes", "false" },
 157     { "virtio-balloon-device", "qemu-4-0-config-size", "false" },
 158     { "pcie-root-port-base", "disable-acs", "true" }, /* Added in 4.1 */
 159 };
 160 const size_t hw_compat_3_1_len = G_N_ELEMENTS(hw_compat_3_1);
 161
 162 GlobalProperty hw_compat_3_0[] = {};
 163 const size_t hw_compat_3_0_len = G_N_ELEMENTS(hw_compat_3_0);
 164
 165 GlobalProperty hw_compat_2_12[] = {
 166     { "migration", "decompress-error-check", "off" },
 167     { "hda-audio", "use-timer", "false" },
 168     { "cirrus-vga", "global-vmstate", "true" },
 169     { "VGA", "global-vmstate", "true" },
 170     { "vmware-svga", "global-vmstate", "true" },
 171     { "qxl-vga", "global-vmstate", "true" },
 172 };
 173 const size_t hw_compat_2_12_len = G_N_ELEMENTS(hw_compat_2_12);
 174
 175 GlobalProperty hw_compat_2_11[] = {
 176     { "hpet", "hpet-offset-saved", "false" },
 177     { "virtio-blk-pci", "vectors", "2" },
 178     { "vhost-user-blk-pci", "vectors", "2" },
 179     { "e1000", "migrate_tso_props", "off" },
 180 };
 181 const size_t hw_compat_2_11_len = G_N_ELEMENTS(hw_compat_2_11);
 182
 183 GlobalProperty hw_compat_2_10[] = {
 184     { "virtio-mouse-device", "wheel-axis", "false" },
 185     { "virtio-tablet-device", "wheel-axis", "false" },
 186 };
 187 const size_t hw_compat_2_10_len = G_N_ELEMENTS(hw_compat_2_10);
 188
 189 GlobalProperty hw_compat_2_9[] = {
 190     { "pci-bridge", "shpc", "off" },
 191     { "intel-iommu", "pt", "off" },
 192     { "virtio-net-device", "x-mtu-bypass-backend", "off" },
 193     { "pcie-root-port", "x-migrate-msix", "false" },
 194 };
 195 const size_t hw_compat_2_9_len = G_N_ELEMENTS(hw_compat_2_9);
 196
 197 GlobalProperty hw_compat_2_8[] = {
 198     { "fw_cfg_mem", "x-file-slots", "0x10" },
 199     { "fw_cfg_io", "x-file-slots", "0x10" },
 200     { "pflash_cfi01", "old-multiple-chip-handling", "on" },
 201     { "pci-bridge", "shpc", "on" },
 202     { TYPE_PCI_DEVICE, "x-pcie-extcap-init", "off" },
 203     { "virtio-pci", "x-pcie-deverr-init", "off" },
 204     { "virtio-pci", "x-pcie-lnkctl-init", "off" },
 205     { "virtio-pci", "x-pcie-pm-init", "off" },
 206     { "cirrus-vga", "vgamem_mb", "8" },
 207     { "isa-cirrus-vga", "vgamem_mb", "8" },
 208 };
 209 const size_t hw_compat_2_8_len = G_N_ELEMENTS(hw_compat_2_8);
 210
 211 GlobalProperty hw_compat_2_7[] = {
 212     { "virtio-pci", "page-per-vq", "on" },
 213     { "virtio-serial-device", "emergency-write", "off" },
 214     { "ioapic", "version", "0x11" },
 215     { "intel-iommu", "x-buggy-eim", "true" },
 216     { "virtio-pci", "x-ignore-backend-features", "on" },
 217 };
 218 const size_t hw_compat_2_7_len = G_N_ELEMENTS(hw_compat_2_7);
 219
 220 GlobalProperty hw_compat_2_6[] = {
 221     { "virtio-mmio", "format_transport_address", "off" },
 222     /* Optional because not all virtio-pci devices support legacy mode */
 223     { "virtio-pci", "disable-modern", "on",  .optional = true },
 224     { "virtio-pci", "disable-legacy", "off", .optional = true },
 225 };
 226 const size_t hw_compat_2_6_len = G_N_ELEMENTS(hw_compat_2_6);
 227
 228 GlobalProperty hw_compat_2_5[] = {
 229     { "isa-fdc", "fallback", "144" },
 230     { "pvscsi", "x-old-pci-configuration", "on" },
 231     { "pvscsi", "x-disable-pcie", "on" },
 232     { "vmxnet3", "x-old-msi-offsets", "on" },
 233     { "vmxnet3", "x-disable-pcie", "on" },
 234 };
 235 const size_t hw_compat_2_5_len = G_N_ELEMENTS(hw_compat_2_5);
 236
 237 GlobalProperty hw_compat_2_4[] = {
 238     /* Optional because the 'scsi' property is Linux-only */
 239     { "virtio-blk-device", "scsi", "true", .optional = true },
 240     { "e1000", "extra_mac_registers", "off" },
 241     { "virtio-pci", "x-disable-pcie", "on" },
 242     { "virtio-pci", "migrate-extra", "off" },
 243     { "fw_cfg_mem", "dma_enabled", "off" },
 244     { "fw_cfg_io", "dma_enabled", "off" }
 245 };
 246 const size_t hw_compat_2_4_len = G_N_ELEMENTS(hw_compat_2_4);
 247
 248 GlobalProperty hw_compat_2_3[] = {
 249     { "virtio-blk-pci", "any_layout", "off" },
 250     { "virtio-balloon-pci", "any_layout", "off" },
 251     { "virtio-serial-pci", "any_layout", "off" },
 252     { "virtio-9p-pci", "any_layout", "off" },
 253     { "virtio-rng-pci", "any_layout", "off" },
 254     { TYPE_PCI_DEVICE, "x-pcie-lnksta-dllla", "off" },
 255     { "migration", "send-configuration", "off" },
 256     { "migration", "send-section-footer", "off" },
 257     { "migration", "store-global-state", "off" },
 258 };
 259 const size_t hw_compat_2_3_len = G_N_ELEMENTS(hw_compat_2_3);
 260
 261 GlobalProperty hw_compat_2_2[] = {};
 262 const size_t hw_compat_2_2_len = G_N_ELEMENTS(hw_compat_2_2);
 263
 264 GlobalProperty hw_compat_2_1[] = {
 265     { "intel-hda", "old_msi_addr", "on" },
 266     { "VGA", "qemu-extended-regs", "off" },
 267     { "secondary-vga", "qemu-extended-regs", "off" },
 268     { "virtio-scsi-pci", "any_layout", "off" },
 269     { "usb-mouse", "usb_version", "1" },
 270     { "usb-kbd", "usb_version", "1" },
 271     { "virtio-pci", "virtio-pci-bus-master-bug-migration", "on" },
 272 };
 273 const size_t hw_compat_2_1_len = G_N_ELEMENTS(hw_compat_2_1);
 274
 275 MachineState *current_machine;
 276
 277 static char *machine_get_kernel(Object *obj, Error **errp)
 278 {
 279     MachineState *ms = MACHINE(obj);
 280
 281     return g_strdup(ms->kernel_filename);
 282 }
 283
 284 static void machine_set_kernel(Object *obj, const char *value, Error **errp)
 285 {
 286     MachineState *ms = MACHINE(obj);
 287
 288     g_free(ms->kernel_filename);
 289     ms->kernel_filename = g_strdup(value);
 290 }
 291
 292 static char *machine_get_initrd(Object *obj, Error **errp)
 293 {
 294     MachineState *ms = MACHINE(obj);
 295
 296     return g_strdup(ms->initrd_filename);
 297 }
 298
 299 static void machine_set_initrd(Object *obj, const char *value, Error **errp)
 300 {
 301     MachineState *ms = MACHINE(obj);
 302
 303     g_free(ms->initrd_filename);
 304     ms->initrd_filename = g_strdup(value);
 305 }
 306
 307 static char *machine_get_append(Object *obj, Error **errp)
 308 {
 309     MachineState *ms = MACHINE(obj);
 310
 311     return g_strdup(ms->kernel_cmdline);
 312 }
 313
 314 static void machine_set_append(Object *obj, const char *value, Error **errp)
 315 {
 316     MachineState *ms = MACHINE(obj);
 317
 318     g_free(ms->kernel_cmdline);
 319     ms->kernel_cmdline = g_strdup(value);
 320 }
 321
 322 static char *machine_get_dtb(Object *obj, Error **errp)
 323 {
 324     MachineState *ms = MACHINE(obj);
 325
 326     return g_strdup(ms->dtb);
 327 }
 328
 329 static void machine_set_dtb(Object *obj, const char *value, Error **errp)
 330 {
 331     MachineState *ms = MACHINE(obj);
 332
 333     g_free(ms->dtb);
 334     ms->dtb = g_strdup(value);
 335 }
 336
 337 static char *machine_get_dumpdtb(Object *obj, Error **errp)
 338 {
 339     MachineState *ms = MACHINE(obj);
 340
 341     return g_strdup(ms->dumpdtb);
 342 }
 343
 344 static void machine_set_dumpdtb(Object *obj, const char *value, Error **errp)
 345 {
 346     MachineState *ms = MACHINE(obj);
 347
 348     g_free(ms->dumpdtb);
 349     ms->dumpdtb = g_strdup(value);
 350 }
 351
 352 static void machine_get_phandle_start(Object *obj, Visitor *v,
 353                                       const char *name, void *opaque,
 354                                       Error **errp)
 355 {
 356     MachineState *ms = MACHINE(obj);
 357     int64_t value = ms->phandle_start;
 358
 359     visit_type_int(v, name, &value, errp);
 360 }
 361
 362 static void machine_set_phandle_start(Object *obj, Visitor *v,
 363                                       const char *name, void *opaque,
 364                                       Error **errp)
 365 {
 366     MachineState *ms = MACHINE(obj);
 367     int64_t value;
 368
 369     if (!visit_type_int(v, name, &value, errp)) {
 370         return;
 371     }
 372
 373     ms->phandle_start = value;
 374 }
 375
 376 static char *machine_get_dt_compatible(Object *obj, Error **errp)
 377 {
 378     MachineState *ms = MACHINE(obj);
 379
 380     return g_strdup(ms->dt_compatible);
 381 }
 382
 383 static void machine_set_dt_compatible(Object *obj, const char *value, Error **errp)
 384 {
 385     MachineState *ms = MACHINE(obj);
 386
 387     g_free(ms->dt_compatible);
 388     ms->dt_compatible = g_strdup(value);
 389 }
 390
 391 static bool machine_get_dump_guest_core(Object *obj, Error **errp)
 392 {
 393     MachineState *ms = MACHINE(obj);
 394
 395     return ms->dump_guest_core;
 396 }
 397
 398 static void machine_set_dump_guest_core(Object *obj, bool value, Error **errp)
 399 {
 400     MachineState *ms = MACHINE(obj);
 401
 402     ms->dump_guest_core = value;
 403 }
 404
 405 static bool machine_get_mem_merge(Object *obj, Error **errp)
 406 {
 407     MachineState *ms = MACHINE(obj);
 408
 409     return ms->mem_merge;
 410 }
 411
 412 static void machine_set_mem_merge(Object *obj, bool value, Error **errp)
 413 {
 414     MachineState *ms = MACHINE(obj);
 415
 416     ms->mem_merge = value;
 417 }
 418
 419 static bool machine_get_usb(Object *obj, Error **errp)
 420 {
 421     MachineState *ms = MACHINE(obj);
 422
 423     return ms->usb;
 424 }
 425
 426 static void machine_set_usb(Object *obj, bool value, Error **errp)
 427 {
 428     MachineState *ms = MACHINE(obj);
 429
 430     ms->usb = value;
 431     ms->usb_disabled = !value;
 432 }
 433
 434 static bool machine_get_graphics(Object *obj, Error **errp)
 435 {
 436     MachineState *ms = MACHINE(obj);
 437
 438     return ms->enable_graphics;
 439 }
 440
 441 static void machine_set_graphics(Object *obj, bool value, Error **errp)
 442 {
 443     MachineState *ms = MACHINE(obj);
 444
 445     ms->enable_graphics = value;
 446 }
 447
 448 static char *machine_get_firmware(Object *obj, Error **errp)
 449 {
 450     MachineState *ms = MACHINE(obj);
 451
 452     return g_strdup(ms->firmware);
 453 }
 454
 455 static void machine_set_firmware(Object *obj, const char *value, Error **errp)
 456 {
 457     MachineState *ms = MACHINE(obj);
 458
 459     g_free(ms->firmware);
 460     ms->firmware = g_strdup(value);
 461 }
 462
 463 static void machine_set_suppress_vmdesc(Object *obj, bool value, Error **errp)
 464 {
 465     MachineState *ms = MACHINE(obj);
 466
 467     ms->suppress_vmdesc = value;
 468 }
 469
 470 static bool machine_get_suppress_vmdesc(Object *obj, Error **errp)
 471 {
 472     MachineState *ms = MACHINE(obj);
 473
 474     return ms->suppress_vmdesc;
 475 }
 476
 477 static char *machine_get_memory_encryption(Object *obj, Error **errp)
 478 {
 479     MachineState *ms = MACHINE(obj);
 480
 481     if (ms->cgs) {
 482         return g_strdup(object_get_canonical_path_component(OBJECT(ms->cgs)));
 483     }
 484
 485     return NULL;
 486 }
 487
 488 static void machine_set_memory_encryption(Object *obj, const char *value,
 489                                         Error **errp)
 490 {
 491     Object *cgs =
 492         object_resolve_path_component(object_get_objects_root(), value);
 493
 494     if (!cgs) {
 495         error_setg(errp, "No such memory encryption object '%s'", value);
 496         return;
 497     }
 498
 499     object_property_set_link(obj, "confidential-guest-support", cgs, errp);
 500 }
 501
 502 static void machine_check_confidential_guest_support(const Object *obj,
 503                                                      const char *name,
 504                                                      Object *new_target,
 505                                                      Error **errp)
 506 {
 507     /*
 508      * So far the only constraint is that the target has the
 509      * TYPE_CONFIDENTIAL_GUEST_SUPPORT interface, and that's checked
 510      * by the QOM core
 511      */
 512 }
 513
 514 static bool machine_get_nvdimm(Object *obj, Error **errp)
 515 {
 516     MachineState *ms = MACHINE(obj);
 517
 518     return ms->nvdimms_state->is_enabled;
 519 }
 520
 521 static void machine_set_nvdimm(Object *obj, bool value, Error **errp)
 522 {
 523     MachineState *ms = MACHINE(obj);
 524
 525     ms->nvdimms_state->is_enabled = value;
 526 }
 527
 528 static bool machine_get_hmat(Object *obj, Error **errp)
 529 {
 530     MachineState *ms = MACHINE(obj);
 531
 532     return ms->numa_state->hmat_enabled;
 533 }
 534
 535 static void machine_set_hmat(Object *obj, bool value, Error **errp)
 536 {
 537     MachineState *ms = MACHINE(obj);
 538
 539     ms->numa_state->hmat_enabled = value;
 540 }
 541
 542 static void machine_get_mem(Object *obj, Visitor *v, const char *name,
 543                             void *opaque, Error **errp)
 544 {
 545     MachineState *ms = MACHINE(obj);
 546     MemorySizeConfiguration mem = {
 547         .has_size = true,
 548         .size = ms->ram_size,
 549         .has_max_size = !!ms->ram_slots,
 550         .max_size = ms->maxram_size,
 551         .has_slots = !!ms->ram_slots,
 552         .slots = ms->ram_slots,
 553     };
 554     MemorySizeConfiguration *p_mem = &mem;
 555
 556     visit_type_MemorySizeConfiguration(v, name, &p_mem, &error_abort);
 557 }
 558
 559 static void machine_set_mem(Object *obj, Visitor *v, const char *name,
 560                             void *opaque, Error **errp)
 561 {
 562     ERRP_GUARD();
 563     MachineState *ms = MACHINE(obj);
 564     MachineClass *mc = MACHINE_GET_CLASS(obj);
 565     MemorySizeConfiguration *mem;
 566
 567     if (!visit_type_MemorySizeConfiguration(v, name, &mem, errp)) {
 568         return;
 569     }
 570
 571     if (!mem->has_size) {
 572         mem->has_size = true;
 573         mem->size = mc->default_ram_size;
 574     }
 575     mem->size = QEMU_ALIGN_UP(mem->size, 8192);
 576     if (mc->fixup_ram_size) {
 577         mem->size = mc->fixup_ram_size(mem->size);
 578     }
 579     if ((ram_addr_t)mem->size != mem->size) {
 580         error_setg(errp, "ram size too large");
 581         goto out_free;
 582     }
 583
 584     if (mem->has_max_size) {
 585         if (mem->max_size < mem->size) {
 586             error_setg(errp, "invalid value of maxmem: "
 587                        "maximum memory size (0x%" PRIx64 ") must be at least "
 588                        "the initial memory size (0x%" PRIx64 ")",
 589                        mem->max_size, mem->size);
 590             goto out_free;
 591         }
 592         if (mem->has_slots && mem->slots && mem->max_size == mem->size) {
 593             error_setg(errp, "invalid value of maxmem: "
 594                        "memory slots were specified but maximum memory size "
 595                        "(0x%" PRIx64 ") is equal to the initial memory size "
 596                        "(0x%" PRIx64 ")", mem->max_size, mem->size);
 597             goto out_free;
 598         }
 599         ms->maxram_size = mem->max_size;
 600     } else {
 601         if (mem->has_slots) {
 602             error_setg(errp, "slots specified but no max-size");
 603             goto out_free;
 604         }
 605         ms->maxram_size = mem->size;
 606     }
 607     ms->ram_size = mem->size;
 608     ms->ram_slots = mem->has_slots ? mem->slots : 0;
 609 out_free:
 610     qapi_free_MemorySizeConfiguration(mem);
 611 }
 612
 613 static char *machine_get_nvdimm_persistence(Object *obj, Error **errp)
 614 {
 615     MachineState *ms = MACHINE(obj);
 616
 617     return g_strdup(ms->nvdimms_state->persistence_string);
 618 }
 619
 620 static void machine_set_nvdimm_persistence(Object *obj, const char *value,
 621                                            Error **errp)
 622 {
 623     MachineState *ms = MACHINE(obj);
 624     NVDIMMState *nvdimms_state = ms->nvdimms_state;
 625
 626     if (strcmp(value, "cpu") == 0) {
 627         nvdimms_state->persistence = 3;
 628     } else if (strcmp(value, "mem-ctrl") == 0) {
 629         nvdimms_state->persistence = 2;
 630     } else {
 631         error_setg(errp, "-machine nvdimm-persistence=%s: unsupported option",
 632                    value);
 633         return;
 634     }
 635
 636     g_free(nvdimms_state->persistence_string);
 637     nvdimms_state->persistence_string = g_strdup(value);
 638 }
 639
 640 void machine_class_allow_dynamic_sysbus_dev(MachineClass *mc, const char *type)
 641 {
 642     QAPI_LIST_PREPEND(mc->allowed_dynamic_sysbus_devices, g_strdup(type));
 643 }
 644
 645 bool device_is_dynamic_sysbus(MachineClass *mc, DeviceState *dev)
 646 {
 647     Object *obj = OBJECT(dev);
 648
 649     if (!object_dynamic_cast(obj, TYPE_SYS_BUS_DEVICE)) {
 650         return false;
 651     }
 652
 653     return device_type_is_dynamic_sysbus(mc, object_get_typename(obj));
 654 }
 655
 656 bool device_type_is_dynamic_sysbus(MachineClass *mc, const char *type)
 657 {
 658     bool allowed = false;
 659     strList *wl;
 660     ObjectClass *klass = object_class_by_name(type);
 661
 662     for (wl = mc->allowed_dynamic_sysbus_devices;
 663          !allowed && wl;
 664          wl = wl->next) {
 665         allowed |= !!object_class_dynamic_cast(klass, wl->value);
 666     }
 667
 668     return allowed;
 669 }
 670
 671 HotpluggableCPUList *machine_query_hotpluggable_cpus(MachineState *machine)
 672 {
 673     int i;
 674     HotpluggableCPUList *head = NULL;
 675     MachineClass *mc = MACHINE_GET_CLASS(machine);
 676
 677     /* force board to initialize possible_cpus if it hasn't been done yet */
 678     mc->possible_cpu_arch_ids(machine);
 679
 680     for (i = 0; i < machine->possible_cpus->len; i++) {
 681         Object *cpu;
 682         HotpluggableCPU *cpu_item = g_new0(typeof(*cpu_item), 1);
 683
 684         cpu_item->type = g_strdup(machine->possible_cpus->cpus[i].type);
 685         cpu_item->vcpus_count = machine->possible_cpus->cpus[i].vcpus_count;
 686         cpu_item->props = g_memdup(&machine->possible_cpus->cpus[i].props,
 687                                    sizeof(*cpu_item->props));
 688
 689         cpu = machine->possible_cpus->cpus[i].cpu;
 690         if (cpu) {
 691             cpu_item->qom_path = object_get_canonical_path(cpu);
 692         }
 693         QAPI_LIST_PREPEND(head, cpu_item);
 694     }
 695     return head;
 696 }
 697
 698 /**
 699  * machine_set_cpu_numa_node:
 700  * @machine: machine object to modify
 701  * @props: specifies which cpu objects to assign to
 702  *         numa node specified by @props.node_id
 703  * @errp: if an error occurs, a pointer to an area to store the error
 704  *
 705  * Associate NUMA node specified by @props.node_id with cpu slots that
 706  * match socket/core/thread-ids specified by @props. It's recommended to use
 707  * query-hotpluggable-cpus.props values to specify affected cpu slots,
 708  * which would lead to exact 1:1 mapping of cpu slots to NUMA node.
 709  *
 710  * However for CLI convenience it's possible to pass in subset of properties,
 711  * which would affect all cpu slots that match it.
 712  * Ex for pc machine:
 713  *    -smp 4,cores=2,sockets=2 -numa node,nodeid=0 -numa node,nodeid=1 \
 714  *    -numa cpu,node-id=0,socket_id=0 \
 715  *    -numa cpu,node-id=1,socket_id=1
 716  * will assign all child cores of socket 0 to node 0 and
 717  * of socket 1 to node 1.
 718  *
 719  * On attempt of reassigning (already assigned) cpu slot to another NUMA node,
 720  * return error.
 721  * Empty subset is disallowed and function will return with error in this case.
 722  */
 723 void machine_set_cpu_numa_node(MachineState *machine,
 724                                const CpuInstanceProperties *props, Error **errp)
 725 {
 726     MachineClass *mc = MACHINE_GET_CLASS(machine);
 727     NodeInfo *numa_info = machine->numa_state->nodes;
 728     bool match = false;
 729     int i;
 730
 731     if (!mc->possible_cpu_arch_ids) {
 732         error_setg(errp, "mapping of CPUs to NUMA node is not supported");
 733         return;
 734     }
 735
 736     /* disabling node mapping is not supported, forbid it */
 737     assert(props->has_node_id);
 738
 739     /* force board to initialize possible_cpus if it hasn't been done yet */
 740     mc->possible_cpu_arch_ids(machine);
 741
 742     for (i = 0; i < machine->possible_cpus->len; i++) {
 743         CPUArchId *slot = &machine->possible_cpus->cpus[i];
 744
 745         /* reject unsupported by board properties */
 746         if (props->has_thread_id && !slot->props.has_thread_id) {
 747             error_setg(errp, "thread-id is not supported");
 748             return;
 749         }
 750
 751         if (props->has_core_id && !slot->props.has_core_id) {
 752             error_setg(errp, "core-id is not supported");
 753             return;
 754         }
 755
 756         if (props->has_cluster_id && !slot->props.has_cluster_id) {
 757             error_setg(errp, "cluster-id is not supported");
 758             return;
 759         }
 760
 761         if (props->has_socket_id && !slot->props.has_socket_id) {
 762             error_setg(errp, "socket-id is not supported");
 763             return;
 764         }
 765
 766         if (props->has_die_id && !slot->props.has_die_id) {
 767             error_setg(errp, "die-id is not supported");
 768             return;
 769         }
 770
 771         /* skip slots with explicit mismatch */
 772         if (props->has_thread_id && props->thread_id != slot->props.thread_id) {
 773                 continue;
 774         }
 775
 776         if (props->has_core_id && props->core_id != slot->props.core_id) {
 777                 continue;
 778         }
 779
 780         if (props->has_cluster_id &&
 781             props->cluster_id != slot->props.cluster_id) {
 782                 continue;
 783         }
 784
 785         if (props->has_die_id && props->die_id != slot->props.die_id) {
 786                 continue;
 787         }
 788
 789         if (props->has_socket_id && props->socket_id != slot->props.socket_id) {
 790                 continue;
 791         }
 792
 793         /* reject assignment if slot is already assigned, for compatibility
 794          * of legacy cpu_index mapping with SPAPR core based mapping do not
 795          * error out if cpu thread and matched core have the same node-id */
 796         if (slot->props.has_node_id &&
 797             slot->props.node_id != props->node_id) {
 798             error_setg(errp, "CPU is already assigned to node-id: %" PRId64,
 799                        slot->props.node_id);
 800             return;
 801         }
 802
 803         /* assign slot to node as it's matched '-numa cpu' key */
 804         match = true;
 805         slot->props.node_id = props->node_id;
 806         slot->props.has_node_id = props->has_node_id;
 807
 808         if (machine->numa_state->hmat_enabled) {
 809             if ((numa_info[props->node_id].initiator < MAX_NODES) &&
 810                 (props->node_id != numa_info[props->node_id].initiator)) {
 811                 error_setg(errp, "The initiator of CPU NUMA node %" PRId64
 812                            " should be itself (got %" PRIu16 ")",
 813                            props->node_id, numa_info[props->node_id].initiator);
 814                 return;
 815             }
 816             numa_info[props->node_id].has_cpu = true;
 817             numa_info[props->node_id].initiator = props->node_id;
 818         }
 819     }
 820
 821     if (!match) {
 822         error_setg(errp, "no match found");
 823     }
 824 }
 825
 826 static void machine_get_smp(Object *obj, Visitor *v, const char *name,
 827                             void *opaque, Error **errp)
 828 {
 829     MachineState *ms = MACHINE(obj);
 830     SMPConfiguration *config = &(SMPConfiguration){
 831         .has_cpus = true, .cpus = ms->smp.cpus,
 832         .has_sockets = true, .sockets = ms->smp.sockets,
 833         .has_dies = true, .dies = ms->smp.dies,
 834         .has_clusters = true, .clusters = ms->smp.clusters,
 835         .has_cores = true, .cores = ms->smp.cores,
 836         .has_threads = true, .threads = ms->smp.threads,
 837         .has_maxcpus = true, .maxcpus = ms->smp.max_cpus,
 838     };
 839
 840     if (!visit_type_SMPConfiguration(v, name, &config, &error_abort)) {
 841         return;
 842     }
 843 }
 844
 845 static void machine_set_smp(Object *obj, Visitor *v, const char *name,
 846                             void *opaque, Error **errp)
 847 {
 848     MachineState *ms = MACHINE(obj);
 849     g_autoptr(SMPConfiguration) config = NULL;
 850
 851     if (!visit_type_SMPConfiguration(v, name, &config, errp)) {
 852         return;
 853     }
 854
 855     machine_parse_smp_config(ms, config, errp);
 856 }
 857
 858 static void machine_get_boot(Object *obj, Visitor *v, const char *name,
 859                             void *opaque, Error **errp)
 860 {
 861     MachineState *ms = MACHINE(obj);
 862     BootConfiguration *config = &ms->boot_config;
 863     visit_type_BootConfiguration(v, name, &config, &error_abort);
 864 }
 865
 866 static void machine_free_boot_config(MachineState *ms)
 867 {
 868     g_free(ms->boot_config.order);
 869     g_free(ms->boot_config.once);
 870     g_free(ms->boot_config.splash);
 871 }
 872
 873 static void machine_copy_boot_config(MachineState *ms, BootConfiguration *config)
 874 {
 875     MachineClass *machine_class = MACHINE_GET_CLASS(ms);
 876
 877     machine_free_boot_config(ms);
 878     ms->boot_config = *config;
 879     if (!config->order) {
 880         ms->boot_config.order = g_strdup(machine_class->default_boot_order);
 881     }
 882 }
 883
 884 static void machine_set_boot(Object *obj, Visitor *v, const char *name,
 885                             void *opaque, Error **errp)
 886 {
 887     ERRP_GUARD();
 888     MachineState *ms = MACHINE(obj);
 889     BootConfiguration *config = NULL;
 890
 891     if (!visit_type_BootConfiguration(v, name, &config, errp)) {
 892         return;
 893     }
 894     if (config->order) {
 895         validate_bootdevices(config->order, errp);
 896         if (*errp) {
 897             goto out_free;
 898         }
 899     }
 900     if (config->once) {
 901         validate_bootdevices(config->once, errp);
 902         if (*errp) {
 903             goto out_free;
 904         }
 905     }
 906
 907     machine_copy_boot_config(ms, config);
 908     /* Strings live in ms->boot_config.  */
 909     free(config);
 910     return;
 911
 912 out_free:
 913     qapi_free_BootConfiguration(config);
 914 }
 915
 916 static void machine_class_init(ObjectClass *oc, void *data)
 917 {
 918     MachineClass *mc = MACHINE_CLASS(oc);
 919
 920     /* Default 128 MB as guest ram size */
 921     mc->default_ram_size = 128 * MiB;
 922     mc->rom_file_has_mr = true;
 923
 924     /* numa node memory size aligned on 8MB by default.
 925      * On Linux, each node's border has to be 8MB aligned
 926      */
 927     mc->numa_mem_align_shift = 23;
 928
 929     object_class_property_add_str(oc, "kernel",
 930         machine_get_kernel, machine_set_kernel);
 931     object_class_property_set_description(oc, "kernel",
 932         "Linux kernel image file");
 933
 934     object_class_property_add_str(oc, "initrd",
 935         machine_get_initrd, machine_set_initrd);
 936     object_class_property_set_description(oc, "initrd",
 937         "Linux initial ramdisk file");
 938
 939     object_class_property_add_str(oc, "append",
 940         machine_get_append, machine_set_append);
 941     object_class_property_set_description(oc, "append",
 942         "Linux kernel command line");
 943
 944     object_class_property_add_str(oc, "dtb",
 945         machine_get_dtb, machine_set_dtb);
 946     object_class_property_set_description(oc, "dtb",
 947         "Linux kernel device tree file");
 948
 949     object_class_property_add_str(oc, "dumpdtb",
 950         machine_get_dumpdtb, machine_set_dumpdtb);
 951     object_class_property_set_description(oc, "dumpdtb",
 952         "Dump current dtb to a file and quit");
 953
 954     object_class_property_add(oc, "boot", "BootConfiguration",
 955         machine_get_boot, machine_set_boot,
 956         NULL, NULL);
 957     object_class_property_set_description(oc, "boot",
 958         "Boot configuration");
 959
 960     object_class_property_add(oc, "smp", "SMPConfiguration",
 961         machine_get_smp, machine_set_smp,
 962         NULL, NULL);
 963     object_class_property_set_description(oc, "smp",
 964         "CPU topology");
 965
 966     object_class_property_add(oc, "phandle-start", "int",
 967         machine_get_phandle_start, machine_set_phandle_start,
 968         NULL, NULL);
 969     object_class_property_set_description(oc, "phandle-start",
 970         "The first phandle ID we may generate dynamically");
 971
 972     object_class_property_add_str(oc, "dt-compatible",
 973         machine_get_dt_compatible, machine_set_dt_compatible);
 974     object_class_property_set_description(oc, "dt-compatible",
 975         "Overrides the \"compatible\" property of the dt root node");
 976
 977     object_class_property_add_bool(oc, "dump-guest-core",
 978         machine_get_dump_guest_core, machine_set_dump_guest_core);
 979     object_class_property_set_description(oc, "dump-guest-core",
 980         "Include guest memory in a core dump");
 981
 982     object_class_property_add_bool(oc, "mem-merge",
 983         machine_get_mem_merge, machine_set_mem_merge);
 984     object_class_property_set_description(oc, "mem-merge",
 985         "Enable/disable memory merge support");
 986
 987     object_class_property_add_bool(oc, "usb",
 988         machine_get_usb, machine_set_usb);
 989     object_class_property_set_description(oc, "usb",
 990         "Set on/off to enable/disable usb");
 991
 992     object_class_property_add_bool(oc, "graphics",
 993         machine_get_graphics, machine_set_graphics);
 994     object_class_property_set_description(oc, "graphics",
 995         "Set on/off to enable/disable graphics emulation");
 996
 997     object_class_property_add_str(oc, "firmware",
 998         machine_get_firmware, machine_set_firmware);
 999     object_class_property_set_description(oc, "firmware",
1000         "Firmware image");
1001
1002     object_class_property_add_bool(oc, "suppress-vmdesc",
1003         machine_get_suppress_vmdesc, machine_set_suppress_vmdesc);
1004     object_class_property_set_description(oc, "suppress-vmdesc",
1005         "Set on to disable self-describing migration");
1006
1007     object_class_property_add_link(oc, "confidential-guest-support",
1008                                    TYPE_CONFIDENTIAL_GUEST_SUPPORT,
1009                                    offsetof(MachineState, cgs),
1010                                    machine_check_confidential_guest_support,
1011                                    OBJ_PROP_LINK_STRONG);
1012     object_class_property_set_description(oc, "confidential-guest-support",
1013                                           "Set confidential guest scheme to support");
1014
1015     /* For compatibility */
1016     object_class_property_add_str(oc, "memory-encryption",
1017         machine_get_memory_encryption, machine_set_memory_encryption);
1018     object_class_property_set_description(oc, "memory-encryption",
1019         "Set memory encryption object to use");
1020
1021     object_class_property_add_link(oc, "memory-backend", TYPE_MEMORY_BACKEND,
1022                                    offsetof(MachineState, memdev), object_property_allow_set_link,
1023                                    OBJ_PROP_LINK_STRONG);
1024     object_class_property_set_description(oc, "memory-backend",
1025                                           "Set RAM backend"
1026                                           "Valid value is ID of hostmem based backend");
1027
1028     object_class_property_add(oc, "memory", "MemorySizeConfiguration",
1029         machine_get_mem, machine_set_mem,
1030         NULL, NULL);
1031     object_class_property_set_description(oc, "memory",
1032         "Memory size configuration");
1033 }
1034
1035 static void machine_class_base_init(ObjectClass *oc, void *data)
1036 {
1037     MachineClass *mc = MACHINE_CLASS(oc);
1038     mc->max_cpus = mc->max_cpus ?: 1;
1039     mc->min_cpus = mc->min_cpus ?: 1;
1040     mc->default_cpus = mc->default_cpus ?: 1;
1041
1042     if (!object_class_is_abstract(oc)) {
1043         const char *cname = object_class_get_name(oc);
1044         assert(g_str_has_suffix(cname, TYPE_MACHINE_SUFFIX));
1045         mc->name = g_strndup(cname,
1046                             strlen(cname) - strlen(TYPE_MACHINE_SUFFIX));
1047         mc->compat_props = g_ptr_array_new();
1048     }
1049 }
1050
1051 static void machine_initfn(Object *obj)
1052 {
1053     MachineState *ms = MACHINE(obj);
1054     MachineClass *mc = MACHINE_GET_CLASS(obj);
1055
1056     container_get(obj, "/peripheral");
1057     container_get(obj, "/peripheral-anon");
1058
1059     ms->dump_guest_core = true;
1060     ms->mem_merge = true;
1061     ms->enable_graphics = true;
1062     ms->kernel_cmdline = g_strdup("");
1063     ms->ram_size = mc->default_ram_size;
1064     ms->maxram_size = mc->default_ram_size;
1065
1066     if (mc->nvdimm_supported) {
1067         Object *obj = OBJECT(ms);
1068
1069         ms->nvdimms_state = g_new0(NVDIMMState, 1);
1070         object_property_add_bool(obj, "nvdimm",
1071                                  machine_get_nvdimm, machine_set_nvdimm);
1072         object_property_set_description(obj, "nvdimm",
1073                                         "Set on/off to enable/disable "
1074                                         "NVDIMM instantiation");
1075
1076         object_property_add_str(obj, "nvdimm-persistence",
1077                                 machine_get_nvdimm_persistence,
1078                                 machine_set_nvdimm_persistence);
1079         object_property_set_description(obj, "nvdimm-persistence",
1080                                         "Set NVDIMM persistence"
1081                                         "Valid values are cpu, mem-ctrl");
1082     }
1083
1084     if (mc->cpu_index_to_instance_props && mc->get_default_cpu_node_id) {
1085         ms->numa_state = g_new0(NumaState, 1);
1086         object_property_add_bool(obj, "hmat",
1087                                  machine_get_hmat, machine_set_hmat);
1088         object_property_set_description(obj, "hmat",
1089                                         "Set on/off to enable/disable "
1090                                         "ACPI Heterogeneous Memory Attribute "
1091                                         "Table (HMAT)");
1092     }
1093
1094     /* default to mc->default_cpus */
1095     ms->smp.cpus = mc->default_cpus;
1096     ms->smp.max_cpus = mc->default_cpus;
1097     ms->smp.sockets = 1;
1098     ms->smp.dies = 1;
1099     ms->smp.clusters = 1;
1100     ms->smp.cores = 1;
1101     ms->smp.threads = 1;
1102
1103     machine_copy_boot_config(ms, &(BootConfiguration){ 0 });
1104 }
1105
1106 static void machine_finalize(Object *obj)
1107 {
1108     MachineState *ms = MACHINE(obj);
1109
1110     machine_free_boot_config(ms);
1111     g_free(ms->kernel_filename);
1112     g_free(ms->initrd_filename);
1113     g_free(ms->kernel_cmdline);
1114     g_free(ms->dtb);
1115     g_free(ms->dumpdtb);
1116     g_free(ms->dt_compatible);
1117     g_free(ms->firmware);
1118     g_free(ms->device_memory);
1119     g_free(ms->nvdimms_state);
1120     g_free(ms->numa_state);
1121 }
1122
1123 bool machine_usb(MachineState *machine)
1124 {
1125     return machine->usb;
1126 }
1127
1128 int machine_phandle_start(MachineState *machine)
1129 {
1130     return machine->phandle_start;
1131 }
1132
1133 bool machine_dump_guest_core(MachineState *machine)
1134 {
1135     return machine->dump_guest_core;
1136 }
1137
1138 bool machine_mem_merge(MachineState *machine)
1139 {
1140     return machine->mem_merge;
1141 }
1142
1143 static char *cpu_slot_to_string(const CPUArchId *cpu)
1144 {
1145     GString *s = g_string_new(NULL);
1146     if (cpu->props.has_socket_id) {
1147         g_string_append_printf(s, "socket-id: %"PRId64, cpu->props.socket_id);
1148     }
1149     if (cpu->props.has_die_id) {
1150         if (s->len) {
1151             g_string_append_printf(s, ", ");
1152         }
1153         g_string_append_printf(s, "die-id: %"PRId64, cpu->props.die_id);
1154     }
1155     if (cpu->props.has_cluster_id) {
1156         if (s->len) {
1157             g_string_append_printf(s, ", ");
1158         }
1159         g_string_append_printf(s, "cluster-id: %"PRId64, cpu->props.cluster_id);
1160     }
1161     if (cpu->props.has_core_id) {
1162         if (s->len) {
1163             g_string_append_printf(s, ", ");
1164         }
1165         g_string_append_printf(s, "core-id: %"PRId64, cpu->props.core_id);
1166     }
1167     if (cpu->props.has_thread_id) {
1168         if (s->len) {
1169             g_string_append_printf(s, ", ");
1170         }
1171         g_string_append_printf(s, "thread-id: %"PRId64, cpu->props.thread_id);
1172     }
1173     return g_string_free(s, false);
1174 }
1175
1176 static void numa_validate_initiator(NumaState *numa_state)
1177 {
1178     int i;
1179     NodeInfo *numa_info = numa_state->nodes;
1180
1181     for (i = 0; i < numa_state->num_nodes; i++) {
1182         if (numa_info[i].initiator == MAX_NODES) {
1183             continue;
1184         }
1185
1186         if (!numa_info[numa_info[i].initiator].present) {
1187             error_report("NUMA node %" PRIu16 " is missing, use "
1188                          "'-numa node' option to declare it first",
1189                          numa_info[i].initiator);
1190             exit(1);
1191         }
1192
1193         if (!numa_info[numa_info[i].initiator].has_cpu) {
1194             error_report("The initiator of NUMA node %d is invalid", i);
1195             exit(1);
1196         }
1197     }
1198 }
1199
1200 static void machine_numa_finish_cpu_init(MachineState *machine)
1201 {
1202     int i;
1203     bool default_mapping;
1204     GString *s = g_string_new(NULL);
1205     MachineClass *mc = MACHINE_GET_CLASS(machine);
1206     const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(machine);
1207
1208     assert(machine->numa_state->num_nodes);
1209     for (i = 0; i < possible_cpus->len; i++) {
1210         if (possible_cpus->cpus[i].props.has_node_id) {
1211             break;
1212         }
1213     }
1214     default_mapping = (i == possible_cpus->len);
1215
1216     for (i = 0; i < possible_cpus->len; i++) {
1217         const CPUArchId *cpu_slot = &possible_cpus->cpus[i];
1218
1219         if (!cpu_slot->props.has_node_id) {
1220             /* fetch default mapping from board and enable it */
1221             CpuInstanceProperties props = cpu_slot->props;
1222
1223             props.node_id = mc->get_default_cpu_node_id(machine, i);
1224             if (!default_mapping) {
1225                 /* record slots with not set mapping,
1226                  * TODO: make it hard error in future */
1227                 char *cpu_str = cpu_slot_to_string(cpu_slot);
1228                 g_string_append_printf(s, "%sCPU %d [%s]",
1229                                        s->len ? ", " : "", i, cpu_str);
1230                 g_free(cpu_str);
1231
1232                 /* non mapped cpus used to fallback to node 0 */
1233                 props.node_id = 0;
1234             }
1235
1236             props.has_node_id = true;
1237             machine_set_cpu_numa_node(machine, &props, &error_fatal);
1238         }
1239     }
1240
1241     if (machine->numa_state->hmat_enabled) {
1242         numa_validate_initiator(machine->numa_state);
1243     }
1244
1245     if (s->len && !qtest_enabled()) {
1246         warn_report("CPU(s) not present in any NUMA nodes: %s",
1247                     s->str);
1248         warn_report("All CPU(s) up to maxcpus should be described "
1249                     "in NUMA config, ability to start up with partial NUMA "
1250                     "mappings is obsoleted and will be removed in future");
1251     }
1252     g_string_free(s, true);
1253 }
1254
1255 MemoryRegion *machine_consume_memdev(MachineState *machine,
1256                                      HostMemoryBackend *backend)
1257 {
1258     MemoryRegion *ret = host_memory_backend_get_memory(backend);
1259
1260     if (host_memory_backend_is_mapped(backend)) {
1261         error_report("memory backend %s can't be used multiple times.",
1262                      object_get_canonical_path_component(OBJECT(backend)));
1263         exit(EXIT_FAILURE);
1264     }
1265     host_memory_backend_set_mapped(backend, true);
1266     vmstate_register_ram_global(ret);
1267     return ret;
1268 }
1269
1270 static bool create_default_memdev(MachineState *ms, const char *path, Error **errp)
1271 {
1272     Object *obj;
1273     MachineClass *mc = MACHINE_GET_CLASS(ms);
1274     bool r = false;
1275
1276     obj = object_new(path ? TYPE_MEMORY_BACKEND_FILE : TYPE_MEMORY_BACKEND_RAM);
1277     if (path) {
1278         if (!object_property_set_str(obj, "mem-path", path, errp)) {
1279             goto out;
1280         }
1281     }
1282     if (!object_property_set_int(obj, "size", ms->ram_size, errp)) {
1283         goto out;
1284     }
1285     object_property_add_child(object_get_objects_root(), mc->default_ram_id,
1286                               obj);
1287     /* Ensure backend's memory region name is equal to mc->default_ram_id */
1288     if (!object_property_set_bool(obj, "x-use-canonical-path-for-ramblock-id",
1289                              false, errp)) {
1290         goto out;
1291     }
1292     if (!user_creatable_complete(USER_CREATABLE(obj), errp)) {
1293         goto out;
1294     }
1295     r = object_property_set_link(OBJECT(ms), "memory-backend", obj, errp);
1296
1297 out:
1298     object_unref(obj);
1299     return r;
1300 }
1301
1302
1303 void machine_run_board_init(MachineState *machine, const char *mem_path, Error **errp)
1304 {
1305     MachineClass *machine_class = MACHINE_GET_CLASS(machine);
1306     ObjectClass *oc = object_class_by_name(machine->cpu_type);
1307     CPUClass *cc;
1308
1309     /* This checkpoint is required by replay to separate prior clock
1310        reading from the other reads, because timer polling functions query
1311        clock values from the log. */
1312     replay_checkpoint(CHECKPOINT_INIT);
1313
1314     if (!xen_enabled()) {
1315         /* On 32-bit hosts, QEMU is limited by virtual address space */
1316         if (machine->ram_size > (2047 << 20) && HOST_LONG_BITS == 32) {
1317             error_setg(errp, "at most 2047 MB RAM can be simulated");
1318             return;
1319         }
1320     }
1321
1322     if (machine->memdev) {
1323         ram_addr_t backend_size = object_property_get_uint(OBJECT(machine->memdev),
1324                                                            "size",  &error_abort);
1325         if (backend_size != machine->ram_size) {
1326             error_setg(errp, "Machine memory size does not match the size of the memory backend");
1327             return;
1328         }
1329     } else if (machine_class->default_ram_id && machine->ram_size &&
1330                numa_uses_legacy_mem()) {
1331         if (!create_default_memdev(current_machine, mem_path, errp)) {
1332             return;
1333         }
1334     }
1335
1336     if (machine->numa_state) {
1337         numa_complete_configuration(machine);
1338         if (machine->numa_state->num_nodes) {
1339             machine_numa_finish_cpu_init(machine);
1340         }
1341     }
1342
1343     if (!machine->ram && machine->memdev) {
1344         machine->ram = machine_consume_memdev(machine, machine->memdev);
1345     }
1346
1347     /* If the machine supports the valid_cpu_types check and the user
1348      * specified a CPU with -cpu check here that the user CPU is supported.
1349      */
1350     if (machine_class->valid_cpu_types && machine->cpu_type) {
1351         int i;
1352
1353         for (i = 0; machine_class->valid_cpu_types[i]; i++) {
1354             if (object_class_dynamic_cast(oc,
1355                                           machine_class->valid_cpu_types[i])) {
1356                 /* The user specificed CPU is in the valid field, we are
1357                  * good to go.
1358                  */
1359                 break;
1360             }
1361         }
1362
1363         if (!machine_class->valid_cpu_types[i]) {
1364             /* The user specified CPU is not valid */
1365             error_report("Invalid CPU type: %s", machine->cpu_type);
1366             error_printf("The valid types are: %s",
1367                          machine_class->valid_cpu_types[0]);
1368             for (i = 1; machine_class->valid_cpu_types[i]; i++) {
1369                 error_printf(", %s", machine_class->valid_cpu_types[i]);
1370             }
1371             error_printf("\n");
1372
1373             exit(1);
1374         }
1375     }
1376
1377     /* Check if CPU type is deprecated and warn if so */
1378     cc = CPU_CLASS(oc);
1379     if (cc && cc->deprecation_note) {
1380         warn_report("CPU model %s is deprecated -- %s", machine->cpu_type,
1381                     cc->deprecation_note);
1382     }
1383
1384     if (machine->cgs) {
1385         /*
1386          * With confidential guests, the host can't see the real
1387          * contents of RAM, so there's no point in it trying to merge
1388          * areas.
1389          */
1390         machine_set_mem_merge(OBJECT(machine), false, &error_abort);
1391
1392         /*
1393          * Virtio devices can't count on directly accessing guest
1394          * memory, so they need iommu_platform=on to use normal DMA
1395          * mechanisms.  That requires also disabling legacy virtio
1396          * support for those virtio pci devices which allow it.
1397          */
1398         object_register_sugar_prop(TYPE_VIRTIO_PCI, "disable-legacy",
1399                                    "on", true);
1400         object_register_sugar_prop(TYPE_VIRTIO_DEVICE, "iommu_platform",
1401                                    "on", false);
1402     }
1403
1404     accel_init_interfaces(ACCEL_GET_CLASS(machine->accelerator));
1405     machine_class->init(machine);
1406     phase_advance(PHASE_MACHINE_INITIALIZED);
1407 }
1408
1409 static NotifierList machine_init_done_notifiers =
1410     NOTIFIER_LIST_INITIALIZER(machine_init_done_notifiers);
1411
1412 void qemu_add_machine_init_done_notifier(Notifier *notify)
1413 {
1414     notifier_list_add(&machine_init_done_notifiers, notify);
1415     if (phase_check(PHASE_MACHINE_READY)) {
1416         notify->notify(notify, NULL);
1417     }
1418 }
1419
1420 void qemu_remove_machine_init_done_notifier(Notifier *notify)
1421 {
1422     notifier_remove(notify);
1423 }
1424
1425 void qdev_machine_creation_done(void)
1426 {
1427     cpu_synchronize_all_post_init();
1428
1429     if (current_machine->boot_config.once) {
1430         qemu_boot_set(current_machine->boot_config.once, &error_fatal);
1431         qemu_register_reset(restore_boot_order, g_strdup(current_machine->boot_config.order));
1432     }
1433
1434     /*
1435      * ok, initial machine setup is done, starting from now we can
1436      * only create hotpluggable devices
1437      */
1438     phase_advance(PHASE_MACHINE_READY);
1439     qdev_assert_realized_properly();
1440
1441     /* TODO: once all bus devices are qdevified, this should be done
1442      * when bus is created by qdev.c */
1443     /*
1444      * TODO: If we had a main 'reset container' that the whole system
1445      * lived in, we could reset that using the multi-phase reset
1446      * APIs. For the moment, we just reset the sysbus, which will cause
1447      * all devices hanging off it (and all their child buses, recursively)
1448      * to be reset. Note that this will *not* reset any Device objects
1449      * which are not attached to some part of the qbus tree!
1450      */
1451     qemu_register_reset(resettable_cold_reset_fn, sysbus_get_default());
1452
1453     notifier_list_notify(&machine_init_done_notifiers, NULL);
1454
1455     if (rom_check_and_register_reset() != 0) {
1456         exit(1);
1457     }
1458
1459     replay_start();
1460
1461     /* This checkpoint is required by replay to separate prior clock
1462        reading from the other reads, because timer polling functions query
1463        clock values from the log. */
1464     replay_checkpoint(CHECKPOINT_RESET);
1465     qemu_system_reset(SHUTDOWN_CAUSE_NONE);
1466     register_global_state();
1467 }
1468
1469 static const TypeInfo machine_info = {
1470     .name = TYPE_MACHINE,
1471     .parent = TYPE_OBJECT,
1472     .abstract = true,
1473     .class_size = sizeof(MachineClass),
1474     .class_init    = machine_class_init,
1475     .class_base_init = machine_class_base_init,
1476     .instance_size = sizeof(MachineState),
1477     .instance_init = machine_initfn,
1478     .instance_finalize = machine_finalize,
1479 };
1480
1481 static void machine_register_types(void)
1482 {
1483     type_register_static(&machine_info);
1484 }
1485
1486 type_init(machine_register_types)