2 * ARM implementation of KVM hooks, 32 bit specific code.
4 * Copyright Christoffer Dall 2009-2010
6 * This work is licensed under the terms of the GNU GPL, version 2 or later.
7 * See the COPYING file in the top-level directory.
11 #include "qemu/osdep.h"
12 #include <sys/ioctl.h>
14 #include <linux/kvm.h>
16 #include "qemu-common.h"
18 #include "qemu/timer.h"
19 #include "sysemu/sysemu.h"
20 #include "sysemu/kvm.h"
22 #include "internals.h"
25 static inline void set_feature(uint64_t *features
, int feature
)
27 *features
|= 1ULL << feature
;
30 static int read_sys_reg32(int fd
, uint32_t *pret
, uint64_t id
)
32 struct kvm_one_reg idreg
= { .id
= id
, .addr
= (uintptr_t)pret
};
34 assert((id
& KVM_REG_SIZE_MASK
) == KVM_REG_SIZE_U32
);
35 return ioctl(fd
, KVM_GET_ONE_REG
, &idreg
);
38 bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures
*ahcf
)
40 /* Identify the feature bits corresponding to the host CPU, and
41 * fill out the ARMHostCPUClass fields accordingly. To do this
42 * we have to create a scratch VM, create a single CPU inside it,
43 * and then query that CPU for the relevant ID registers.
45 int err
= 0, fdarray
[3];
46 uint32_t midr
, id_pfr0
;
47 uint64_t features
= 0;
49 /* Old kernels may not know about the PREFERRED_TARGET ioctl: however
50 * we know these will only support creating one kind of guest CPU,
51 * which is its preferred CPU type.
53 static const uint32_t cpus_to_try
[] = {
54 QEMU_KVM_ARM_TARGET_CORTEX_A15
,
55 QEMU_KVM_ARM_TARGET_NONE
57 struct kvm_vcpu_init init
;
59 if (!kvm_arm_create_scratch_host_vcpu(cpus_to_try
, fdarray
, &init
)) {
63 ahcf
->target
= init
.target
;
65 /* This is not strictly blessed by the device tree binding docs yet,
66 * but in practice the kernel does not care about this string so
67 * there is no point maintaining an KVM_ARM_TARGET_* -> string table.
69 ahcf
->dtb_compatible
= "arm,arm-v7";
71 err
|= read_sys_reg32(fdarray
[2], &midr
, ARM_CP15_REG32(0, 0, 0, 0));
72 err
|= read_sys_reg32(fdarray
[2], &id_pfr0
, ARM_CP15_REG32(0, 0, 1, 0));
74 err
|= read_sys_reg32(fdarray
[2], &ahcf
->isar
.id_isar0
,
75 ARM_CP15_REG32(0, 0, 2, 0));
76 err
|= read_sys_reg32(fdarray
[2], &ahcf
->isar
.id_isar1
,
77 ARM_CP15_REG32(0, 0, 2, 1));
78 err
|= read_sys_reg32(fdarray
[2], &ahcf
->isar
.id_isar2
,
79 ARM_CP15_REG32(0, 0, 2, 2));
80 err
|= read_sys_reg32(fdarray
[2], &ahcf
->isar
.id_isar3
,
81 ARM_CP15_REG32(0, 0, 2, 3));
82 err
|= read_sys_reg32(fdarray
[2], &ahcf
->isar
.id_isar4
,
83 ARM_CP15_REG32(0, 0, 2, 4));
84 err
|= read_sys_reg32(fdarray
[2], &ahcf
->isar
.id_isar5
,
85 ARM_CP15_REG32(0, 0, 2, 5));
86 if (read_sys_reg32(fdarray
[2], &ahcf
->isar
.id_isar6
,
87 ARM_CP15_REG32(0, 0, 2, 7))) {
89 * Older kernels don't support reading ID_ISAR6. This register was
90 * only introduced in ARMv8, so we can assume that it is zero on a
91 * CPU that a kernel this old is running on.
93 ahcf
->isar
.id_isar6
= 0;
96 err
|= read_sys_reg32(fdarray
[2], &ahcf
->isar
.mvfr0
,
97 KVM_REG_ARM
| KVM_REG_SIZE_U32
|
98 KVM_REG_ARM_VFP
| KVM_REG_ARM_VFP_MVFR0
);
99 err
|= read_sys_reg32(fdarray
[2], &ahcf
->isar
.mvfr1
,
100 KVM_REG_ARM
| KVM_REG_SIZE_U32
|
101 KVM_REG_ARM_VFP
| KVM_REG_ARM_VFP_MVFR1
);
103 * FIXME: There is not yet a way to read MVFR2.
104 * Fortunately there is not yet anything in there that affects migration.
107 kvm_arm_destroy_scratch_host_vcpu(fdarray
);
113 /* Now we've retrieved all the register information we can
114 * set the feature bits based on the ID register fields.
115 * We can assume any KVM supporting CPU is at least a v7
116 * with VFPv3, virtualization extensions, and the generic
117 * timers; this in turn implies most of the other feature
118 * bits, but a few must be tested.
120 set_feature(&features
, ARM_FEATURE_V7VE
);
121 set_feature(&features
, ARM_FEATURE_VFP3
);
122 set_feature(&features
, ARM_FEATURE_GENERIC_TIMER
);
124 if (extract32(id_pfr0
, 12, 4) == 1) {
125 set_feature(&features
, ARM_FEATURE_THUMB2EE
);
127 if (extract32(ahcf
->isar
.mvfr1
, 12, 4) == 1) {
128 set_feature(&features
, ARM_FEATURE_NEON
);
130 if (extract32(ahcf
->isar
.mvfr1
, 28, 4) == 1) {
131 /* FMAC support implies VFPv4 */
132 set_feature(&features
, ARM_FEATURE_VFP4
);
135 ahcf
->features
= features
;
140 bool kvm_arm_reg_syncs_via_cpreg_list(uint64_t regidx
)
142 /* Return true if the regidx is a register we should synchronize
143 * via the cpreg_tuples array (ie is not a core reg we sync by
144 * hand in kvm_arch_get/put_registers())
146 switch (regidx
& KVM_REG_ARM_COPROC_MASK
) {
147 case KVM_REG_ARM_CORE
:
148 case KVM_REG_ARM_VFP
:
155 typedef struct CPRegStateLevel
{
160 /* All coprocessor registers not listed in the following table are assumed to
161 * be of the level KVM_PUT_RUNTIME_STATE. If a register should be written less
162 * often, you must add it to this table with a state of either
163 * KVM_PUT_RESET_STATE or KVM_PUT_FULL_STATE.
165 static const CPRegStateLevel non_runtime_cpregs
[] = {
166 { KVM_REG_ARM_TIMER_CNT
, KVM_PUT_FULL_STATE
},
169 int kvm_arm_cpreg_level(uint64_t regidx
)
173 for (i
= 0; i
< ARRAY_SIZE(non_runtime_cpregs
); i
++) {
174 const CPRegStateLevel
*l
= &non_runtime_cpregs
[i
];
175 if (l
->regidx
== regidx
) {
180 return KVM_PUT_RUNTIME_STATE
;
183 #define ARM_CPU_ID_MPIDR 0, 0, 0, 5
185 int kvm_arch_init_vcpu(CPUState
*cs
)
190 struct kvm_one_reg r
;
191 ARMCPU
*cpu
= ARM_CPU(cs
);
193 if (cpu
->kvm_target
== QEMU_KVM_ARM_TARGET_NONE
) {
194 fprintf(stderr
, "KVM is not supported for this guest CPU type\n");
198 /* Determine init features for this CPU */
199 memset(cpu
->kvm_init_features
, 0, sizeof(cpu
->kvm_init_features
));
200 if (cpu
->start_powered_off
) {
201 cpu
->kvm_init_features
[0] |= 1 << KVM_ARM_VCPU_POWER_OFF
;
203 if (kvm_check_extension(cs
->kvm_state
, KVM_CAP_ARM_PSCI_0_2
)) {
204 cpu
->psci_version
= 2;
205 cpu
->kvm_init_features
[0] |= 1 << KVM_ARM_VCPU_PSCI_0_2
;
208 /* Do KVM_ARM_VCPU_INIT ioctl */
209 ret
= kvm_arm_vcpu_init(cs
);
214 /* Query the kernel to make sure it supports 32 VFP
215 * registers: QEMU's "cortex-a15" CPU is always a
216 * VFP-D32 core. The simplest way to do this is just
217 * to attempt to read register d31.
219 r
.id
= KVM_REG_ARM
| KVM_REG_SIZE_U64
| KVM_REG_ARM_VFP
| 31;
220 r
.addr
= (uintptr_t)(&v
);
221 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_ONE_REG
, &r
);
222 if (ret
== -ENOENT
) {
227 * When KVM is in use, PSCI is emulated in-kernel and not by qemu.
228 * Currently KVM has its own idea about MPIDR assignment, so we
229 * override our defaults with what we get from KVM.
231 ret
= kvm_get_one_reg(cs
, ARM_CP15_REG32(ARM_CPU_ID_MPIDR
), &mpidr
);
235 cpu
->mp_affinity
= mpidr
& ARM32_AFFINITY_MASK
;
237 /* Check whether userspace can specify guest syndrome value */
238 kvm_arm_init_serror_injection(cs
);
240 return kvm_arm_init_cpreg_list(cpu
);
243 int kvm_arch_destroy_vcpu(CPUState
*cs
)
253 #define COREREG(KERNELNAME, QEMUFIELD) \
255 KVM_REG_ARM | KVM_REG_SIZE_U32 | \
256 KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(KERNELNAME), \
257 offsetof(CPUARMState, QEMUFIELD) \
260 #define VFPSYSREG(R) \
262 KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_VFP | \
263 KVM_REG_ARM_VFP_##R, \
264 offsetof(CPUARMState, vfp.xregs[ARM_VFP_##R]) \
267 /* Like COREREG, but handle fields which are in a uint64_t in CPUARMState. */
268 #define COREREG64(KERNELNAME, QEMUFIELD) \
270 KVM_REG_ARM | KVM_REG_SIZE_U32 | \
271 KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(KERNELNAME), \
272 offsetoflow32(CPUARMState, QEMUFIELD) \
275 static const Reg regs
[] = {
276 /* R0_usr .. R14_usr */
277 COREREG(usr_regs
.uregs
[0], regs
[0]),
278 COREREG(usr_regs
.uregs
[1], regs
[1]),
279 COREREG(usr_regs
.uregs
[2], regs
[2]),
280 COREREG(usr_regs
.uregs
[3], regs
[3]),
281 COREREG(usr_regs
.uregs
[4], regs
[4]),
282 COREREG(usr_regs
.uregs
[5], regs
[5]),
283 COREREG(usr_regs
.uregs
[6], regs
[6]),
284 COREREG(usr_regs
.uregs
[7], regs
[7]),
285 COREREG(usr_regs
.uregs
[8], usr_regs
[0]),
286 COREREG(usr_regs
.uregs
[9], usr_regs
[1]),
287 COREREG(usr_regs
.uregs
[10], usr_regs
[2]),
288 COREREG(usr_regs
.uregs
[11], usr_regs
[3]),
289 COREREG(usr_regs
.uregs
[12], usr_regs
[4]),
290 COREREG(usr_regs
.uregs
[13], banked_r13
[BANK_USRSYS
]),
291 COREREG(usr_regs
.uregs
[14], banked_r14
[BANK_USRSYS
]),
292 /* R13, R14, SPSR for SVC, ABT, UND, IRQ banks */
293 COREREG(svc_regs
[0], banked_r13
[BANK_SVC
]),
294 COREREG(svc_regs
[1], banked_r14
[BANK_SVC
]),
295 COREREG64(svc_regs
[2], banked_spsr
[BANK_SVC
]),
296 COREREG(abt_regs
[0], banked_r13
[BANK_ABT
]),
297 COREREG(abt_regs
[1], banked_r14
[BANK_ABT
]),
298 COREREG64(abt_regs
[2], banked_spsr
[BANK_ABT
]),
299 COREREG(und_regs
[0], banked_r13
[BANK_UND
]),
300 COREREG(und_regs
[1], banked_r14
[BANK_UND
]),
301 COREREG64(und_regs
[2], banked_spsr
[BANK_UND
]),
302 COREREG(irq_regs
[0], banked_r13
[BANK_IRQ
]),
303 COREREG(irq_regs
[1], banked_r14
[BANK_IRQ
]),
304 COREREG64(irq_regs
[2], banked_spsr
[BANK_IRQ
]),
305 /* R8_fiq .. R14_fiq and SPSR_fiq */
306 COREREG(fiq_regs
[0], fiq_regs
[0]),
307 COREREG(fiq_regs
[1], fiq_regs
[1]),
308 COREREG(fiq_regs
[2], fiq_regs
[2]),
309 COREREG(fiq_regs
[3], fiq_regs
[3]),
310 COREREG(fiq_regs
[4], fiq_regs
[4]),
311 COREREG(fiq_regs
[5], banked_r13
[BANK_FIQ
]),
312 COREREG(fiq_regs
[6], banked_r14
[BANK_FIQ
]),
313 COREREG64(fiq_regs
[7], banked_spsr
[BANK_FIQ
]),
315 COREREG(usr_regs
.uregs
[15], regs
[15]),
316 /* VFP system registers */
325 int kvm_arch_put_registers(CPUState
*cs
, int level
)
327 ARMCPU
*cpu
= ARM_CPU(cs
);
328 CPUARMState
*env
= &cpu
->env
;
329 struct kvm_one_reg r
;
332 uint32_t cpsr
, fpscr
;
334 /* Make sure the banked regs are properly set */
335 mode
= env
->uncached_cpsr
& CPSR_M
;
336 bn
= bank_number(mode
);
337 if (mode
== ARM_CPU_MODE_FIQ
) {
338 memcpy(env
->fiq_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
340 memcpy(env
->usr_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
342 env
->banked_r13
[bn
] = env
->regs
[13];
343 env
->banked_spsr
[bn
] = env
->spsr
;
344 env
->banked_r14
[r14_bank_number(mode
)] = env
->regs
[14];
346 /* Now we can safely copy stuff down to the kernel */
347 for (i
= 0; i
< ARRAY_SIZE(regs
); i
++) {
349 r
.addr
= (uintptr_t)(env
) + regs
[i
].offset
;
350 ret
= kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, &r
);
356 /* Special cases which aren't a single CPUARMState field */
357 cpsr
= cpsr_read(env
);
358 r
.id
= KVM_REG_ARM
| KVM_REG_SIZE_U32
|
359 KVM_REG_ARM_CORE
| KVM_REG_ARM_CORE_REG(usr_regs
.ARM_cpsr
);
360 r
.addr
= (uintptr_t)(&cpsr
);
361 ret
= kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, &r
);
367 r
.id
= KVM_REG_ARM
| KVM_REG_SIZE_U64
| KVM_REG_ARM_VFP
;
368 for (i
= 0; i
< 32; i
++) {
369 r
.addr
= (uintptr_t)aa32_vfp_dreg(env
, i
);
370 ret
= kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, &r
);
377 r
.id
= KVM_REG_ARM
| KVM_REG_SIZE_U32
| KVM_REG_ARM_VFP
|
378 KVM_REG_ARM_VFP_FPSCR
;
379 fpscr
= vfp_get_fpscr(env
);
380 r
.addr
= (uintptr_t)&fpscr
;
381 ret
= kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, &r
);
386 ret
= kvm_put_vcpu_events(cpu
);
391 write_cpustate_to_list(cpu
, true);
393 if (!write_list_to_kvmstate(cpu
, level
)) {
397 kvm_arm_sync_mpstate_to_kvm(cpu
);
402 int kvm_arch_get_registers(CPUState
*cs
)
404 ARMCPU
*cpu
= ARM_CPU(cs
);
405 CPUARMState
*env
= &cpu
->env
;
406 struct kvm_one_reg r
;
409 uint32_t cpsr
, fpscr
;
411 for (i
= 0; i
< ARRAY_SIZE(regs
); i
++) {
413 r
.addr
= (uintptr_t)(env
) + regs
[i
].offset
;
414 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_ONE_REG
, &r
);
420 /* Special cases which aren't a single CPUARMState field */
421 r
.id
= KVM_REG_ARM
| KVM_REG_SIZE_U32
|
422 KVM_REG_ARM_CORE
| KVM_REG_ARM_CORE_REG(usr_regs
.ARM_cpsr
);
423 r
.addr
= (uintptr_t)(&cpsr
);
424 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_ONE_REG
, &r
);
428 cpsr_write(env
, cpsr
, 0xffffffff, CPSRWriteRaw
);
430 /* Make sure the current mode regs are properly set */
431 mode
= env
->uncached_cpsr
& CPSR_M
;
432 bn
= bank_number(mode
);
433 if (mode
== ARM_CPU_MODE_FIQ
) {
434 memcpy(env
->regs
+ 8, env
->fiq_regs
, 5 * sizeof(uint32_t));
436 memcpy(env
->regs
+ 8, env
->usr_regs
, 5 * sizeof(uint32_t));
438 env
->regs
[13] = env
->banked_r13
[bn
];
439 env
->spsr
= env
->banked_spsr
[bn
];
440 env
->regs
[14] = env
->banked_r14
[r14_bank_number(mode
)];
443 r
.id
= KVM_REG_ARM
| KVM_REG_SIZE_U64
| KVM_REG_ARM_VFP
;
444 for (i
= 0; i
< 32; i
++) {
445 r
.addr
= (uintptr_t)aa32_vfp_dreg(env
, i
);
446 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_ONE_REG
, &r
);
453 r
.id
= KVM_REG_ARM
| KVM_REG_SIZE_U32
| KVM_REG_ARM_VFP
|
454 KVM_REG_ARM_VFP_FPSCR
;
455 r
.addr
= (uintptr_t)&fpscr
;
456 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_ONE_REG
, &r
);
460 vfp_set_fpscr(env
, fpscr
);
462 ret
= kvm_get_vcpu_events(cpu
);
467 if (!write_kvmstate_to_list(cpu
)) {
470 /* Note that it's OK to have registers which aren't in CPUState,
471 * so we can ignore a failure return here.
473 write_list_to_cpustate(cpu
);
475 kvm_arm_sync_mpstate_to_qemu(cpu
);
480 int kvm_arch_insert_sw_breakpoint(CPUState
*cs
, struct kvm_sw_breakpoint
*bp
)
482 qemu_log_mask(LOG_UNIMP
, "%s: guest debug not yet implemented\n", __func__
);
486 int kvm_arch_remove_sw_breakpoint(CPUState
*cs
, struct kvm_sw_breakpoint
*bp
)
488 qemu_log_mask(LOG_UNIMP
, "%s: guest debug not yet implemented\n", __func__
);
492 bool kvm_arm_handle_debug(CPUState
*cs
, struct kvm_debug_exit_arch
*debug_exit
)
494 qemu_log_mask(LOG_UNIMP
, "%s: guest debug not yet implemented\n", __func__
);
498 int kvm_arch_insert_hw_breakpoint(target_ulong addr
,
499 target_ulong len
, int type
)
501 qemu_log_mask(LOG_UNIMP
, "%s: not implemented\n", __func__
);
505 int kvm_arch_remove_hw_breakpoint(target_ulong addr
,
506 target_ulong len
, int type
)
508 qemu_log_mask(LOG_UNIMP
, "%s: not implemented\n", __func__
);
512 void kvm_arch_remove_all_hw_breakpoints(void)
514 qemu_log_mask(LOG_UNIMP
, "%s: not implemented\n", __func__
);
517 void kvm_arm_copy_hw_debug_data(struct kvm_guest_debug_arch
*ptr
)
519 qemu_log_mask(LOG_UNIMP
, "%s: not implemented\n", __func__
);
522 bool kvm_arm_hw_debug_active(CPUState
*cs
)
527 void kvm_arm_pmu_set_irq(CPUState
*cs
, int irq
)
529 qemu_log_mask(LOG_UNIMP
, "%s: not implemented\n", __func__
);
532 void kvm_arm_pmu_init(CPUState
*cs
)
534 qemu_log_mask(LOG_UNIMP
, "%s: not implemented\n", __func__
);