2 * QEMU PowerPC 440 embedded processors emulation
4 * Copyright (c) 2012 François Revol
5 * Copyright (c) 2016-2019 BALATON Zoltan
7 * This work is licensed under the GNU GPL license version 2 or later.
11 #include "qemu/osdep.h"
12 #include "qemu/units.h"
13 #include "qemu/error-report.h"
14 #include "qapi/error.h"
16 #include "qemu/module.h"
18 #include "exec/memory.h"
19 #include "hw/ppc/ppc4xx.h"
20 #include "hw/qdev-properties.h"
21 #include "hw/pci/pci.h"
22 #include "sysemu/block-backend.h"
23 #include "sysemu/reset.h"
25 #include "qom/object.h"
27 /*****************************************************************************/
28 /* L2 Cache as SRAM */
31 DCR_L2CACHE_BASE
= 0x30,
32 DCR_L2CACHE_CFG
= DCR_L2CACHE_BASE
,
40 DCR_L2CACHE_END
= DCR_L2CACHE_SNP1
,
43 /* base is 460ex-specific, cf. U-Boot, ppc4xx-isram.h */
45 DCR_ISRAM0_BASE
= 0x20,
46 DCR_ISRAM0_SB0CR
= DCR_ISRAM0_BASE
,
57 DCR_ISRAM0_END
= DCR_ISRAM0_DPC
61 DCR_ISRAM1_BASE
= 0xb0,
62 DCR_ISRAM1_SB0CR
= DCR_ISRAM1_BASE
,
64 DCR_ISRAM1_BEAR
= DCR_ISRAM1_BASE
+ 0x04,
71 DCR_ISRAM1_END
= DCR_ISRAM1_DPC
74 typedef struct ppc4xx_l2sram_t
{
81 static void l2sram_update_mappings(ppc4xx_l2sram_t
*l2sram
,
82 uint32_t isarc
, uint32_t isacntl
,
83 uint32_t dsarc
, uint32_t dsacntl
)
85 if (l2sram
->isarc
!= isarc
||
86 (l2sram
->isacntl
& 0x80000000) != (isacntl
& 0x80000000)) {
87 if (l2sram
->isacntl
& 0x80000000) {
88 /* Unmap previously assigned memory region */
89 memory_region_del_subregion(get_system_memory(),
92 if (isacntl
& 0x80000000) {
93 /* Map new instruction memory region */
94 memory_region_add_subregion(get_system_memory(), isarc
,
98 if (l2sram
->dsarc
!= dsarc
||
99 (l2sram
->dsacntl
& 0x80000000) != (dsacntl
& 0x80000000)) {
100 if (l2sram
->dsacntl
& 0x80000000) {
101 /* Beware not to unmap the region we just mapped */
102 if (!(isacntl
& 0x80000000) || l2sram
->dsarc
!= isarc
) {
103 /* Unmap previously assigned memory region */
104 memory_region_del_subregion(get_system_memory(),
108 if (dsacntl
& 0x80000000) {
109 /* Beware not to remap the region we just mapped */
110 if (!(isacntl
& 0x80000000) || dsarc
!= isarc
) {
111 /* Map new data memory region */
112 memory_region_add_subregion(get_system_memory(), dsarc
,
120 static uint32_t dcr_read_l2sram(void *opaque
, int dcrn
)
122 ppc4xx_l2sram_t
*l2sram
= opaque
;
126 case DCR_L2CACHE_CFG
:
127 case DCR_L2CACHE_CMD
:
128 case DCR_L2CACHE_ADDR
:
129 case DCR_L2CACHE_DATA
:
130 case DCR_L2CACHE_STAT
:
131 case DCR_L2CACHE_CVER
:
132 case DCR_L2CACHE_SNP0
:
133 case DCR_L2CACHE_SNP1
:
134 ret
= l2sram
->l2cache
[dcrn
- DCR_L2CACHE_BASE
];
137 case DCR_ISRAM0_SB0CR
:
138 case DCR_ISRAM0_SB1CR
:
139 case DCR_ISRAM0_SB2CR
:
140 case DCR_ISRAM0_SB3CR
:
141 case DCR_ISRAM0_BEAR
:
142 case DCR_ISRAM0_BESR0
:
143 case DCR_ISRAM0_BESR1
:
144 case DCR_ISRAM0_PMEG
:
146 case DCR_ISRAM0_REVID
:
148 ret
= l2sram
->isram0
[dcrn
- DCR_ISRAM0_BASE
];
158 static void dcr_write_l2sram(void *opaque
, int dcrn
, uint32_t val
)
160 /*ppc4xx_l2sram_t *l2sram = opaque;*/
161 /* FIXME: Actually handle L2 cache mapping */
164 case DCR_L2CACHE_CFG
:
165 case DCR_L2CACHE_CMD
:
166 case DCR_L2CACHE_ADDR
:
167 case DCR_L2CACHE_DATA
:
168 case DCR_L2CACHE_STAT
:
169 case DCR_L2CACHE_CVER
:
170 case DCR_L2CACHE_SNP0
:
171 case DCR_L2CACHE_SNP1
:
172 /*l2sram->l2cache[dcrn - DCR_L2CACHE_BASE] = val;*/
175 case DCR_ISRAM0_SB0CR
:
176 case DCR_ISRAM0_SB1CR
:
177 case DCR_ISRAM0_SB2CR
:
178 case DCR_ISRAM0_SB3CR
:
179 case DCR_ISRAM0_BEAR
:
180 case DCR_ISRAM0_BESR0
:
181 case DCR_ISRAM0_BESR1
:
182 case DCR_ISRAM0_PMEG
:
184 case DCR_ISRAM0_REVID
:
186 /*l2sram->isram0[dcrn - DCR_L2CACHE_BASE] = val;*/
189 case DCR_ISRAM1_SB0CR
:
190 case DCR_ISRAM1_BEAR
:
191 case DCR_ISRAM1_BESR0
:
192 case DCR_ISRAM1_BESR1
:
193 case DCR_ISRAM1_PMEG
:
195 case DCR_ISRAM1_REVID
:
197 /*l2sram->isram1[dcrn - DCR_L2CACHE_BASE] = val;*/
200 /*l2sram_update_mappings(l2sram, isarc, isacntl, dsarc, dsacntl);*/
203 static void l2sram_reset(void *opaque
)
205 ppc4xx_l2sram_t
*l2sram
= opaque
;
207 memset(l2sram
->l2cache
, 0, sizeof(l2sram
->l2cache
));
208 l2sram
->l2cache
[DCR_L2CACHE_STAT
- DCR_L2CACHE_BASE
] = 0x80000000;
209 memset(l2sram
->isram0
, 0, sizeof(l2sram
->isram0
));
210 /*l2sram_update_mappings(l2sram, isarc, isacntl, dsarc, dsacntl);*/
213 void ppc4xx_l2sram_init(CPUPPCState
*env
)
215 ppc4xx_l2sram_t
*l2sram
;
217 l2sram
= g_malloc0(sizeof(*l2sram
));
218 /* XXX: Size is 4*64kB for 460ex, cf. U-Boot, ppc4xx-isram.h */
219 memory_region_init_ram(&l2sram
->bank
[0], NULL
, "ppc4xx.l2sram_bank0",
220 64 * KiB
, &error_abort
);
221 memory_region_init_ram(&l2sram
->bank
[1], NULL
, "ppc4xx.l2sram_bank1",
222 64 * KiB
, &error_abort
);
223 memory_region_init_ram(&l2sram
->bank
[2], NULL
, "ppc4xx.l2sram_bank2",
224 64 * KiB
, &error_abort
);
225 memory_region_init_ram(&l2sram
->bank
[3], NULL
, "ppc4xx.l2sram_bank3",
226 64 * KiB
, &error_abort
);
227 qemu_register_reset(&l2sram_reset
, l2sram
);
228 ppc_dcr_register(env
, DCR_L2CACHE_CFG
,
229 l2sram
, &dcr_read_l2sram
, &dcr_write_l2sram
);
230 ppc_dcr_register(env
, DCR_L2CACHE_CMD
,
231 l2sram
, &dcr_read_l2sram
, &dcr_write_l2sram
);
232 ppc_dcr_register(env
, DCR_L2CACHE_ADDR
,
233 l2sram
, &dcr_read_l2sram
, &dcr_write_l2sram
);
234 ppc_dcr_register(env
, DCR_L2CACHE_DATA
,
235 l2sram
, &dcr_read_l2sram
, &dcr_write_l2sram
);
236 ppc_dcr_register(env
, DCR_L2CACHE_STAT
,
237 l2sram
, &dcr_read_l2sram
, &dcr_write_l2sram
);
238 ppc_dcr_register(env
, DCR_L2CACHE_CVER
,
239 l2sram
, &dcr_read_l2sram
, &dcr_write_l2sram
);
240 ppc_dcr_register(env
, DCR_L2CACHE_SNP0
,
241 l2sram
, &dcr_read_l2sram
, &dcr_write_l2sram
);
242 ppc_dcr_register(env
, DCR_L2CACHE_SNP1
,
243 l2sram
, &dcr_read_l2sram
, &dcr_write_l2sram
);
245 ppc_dcr_register(env
, DCR_ISRAM0_SB0CR
,
246 l2sram
, &dcr_read_l2sram
, &dcr_write_l2sram
);
247 ppc_dcr_register(env
, DCR_ISRAM0_SB1CR
,
248 l2sram
, &dcr_read_l2sram
, &dcr_write_l2sram
);
249 ppc_dcr_register(env
, DCR_ISRAM0_SB2CR
,
250 l2sram
, &dcr_read_l2sram
, &dcr_write_l2sram
);
251 ppc_dcr_register(env
, DCR_ISRAM0_SB3CR
,
252 l2sram
, &dcr_read_l2sram
, &dcr_write_l2sram
);
253 ppc_dcr_register(env
, DCR_ISRAM0_PMEG
,
254 l2sram
, &dcr_read_l2sram
, &dcr_write_l2sram
);
255 ppc_dcr_register(env
, DCR_ISRAM0_DPC
,
256 l2sram
, &dcr_read_l2sram
, &dcr_write_l2sram
);
258 ppc_dcr_register(env
, DCR_ISRAM1_SB0CR
,
259 l2sram
, &dcr_read_l2sram
, &dcr_write_l2sram
);
260 ppc_dcr_register(env
, DCR_ISRAM1_PMEG
,
261 l2sram
, &dcr_read_l2sram
, &dcr_write_l2sram
);
262 ppc_dcr_register(env
, DCR_ISRAM1_DPC
,
263 l2sram
, &dcr_read_l2sram
, &dcr_write_l2sram
);
266 /*****************************************************************************/
267 /* Clocking Power on Reset */
279 typedef struct ppc4xx_cpr_t
{
283 static uint32_t dcr_read_cpr(void *opaque
, int dcrn
)
285 ppc4xx_cpr_t
*cpr
= opaque
;
295 ret
= (0xb5 << 24) | (1 << 16) | (9 << 8);
318 static void dcr_write_cpr(void *opaque
, int dcrn
, uint32_t val
)
320 ppc4xx_cpr_t
*cpr
= opaque
;
333 static void ppc4xx_cpr_reset(void *opaque
)
335 ppc4xx_cpr_t
*cpr
= opaque
;
340 void ppc4xx_cpr_init(CPUPPCState
*env
)
344 cpr
= g_malloc0(sizeof(*cpr
));
345 ppc_dcr_register(env
, CPR0_CFGADDR
, cpr
, &dcr_read_cpr
, &dcr_write_cpr
);
346 ppc_dcr_register(env
, CPR0_CFGDATA
, cpr
, &dcr_read_cpr
, &dcr_write_cpr
);
347 qemu_register_reset(ppc4xx_cpr_reset
, cpr
);
350 /*****************************************************************************/
352 typedef struct ppc4xx_sdr_t ppc4xx_sdr_t
;
353 struct ppc4xx_sdr_t
{
358 SDR0_CFGADDR
= 0x00e,
374 PESDR0_RSTSTA
= 0x310,
378 PESDR1_RSTSTA
= 0x365,
381 #define SDR0_DDR0_DDRM_ENCODE(n) ((((unsigned long)(n)) & 0x03) << 29)
382 #define SDR0_DDR0_DDRM_DDR1 0x20000000
383 #define SDR0_DDR0_DDRM_DDR2 0x40000000
385 static uint32_t dcr_read_sdr(void *opaque
, int dcrn
)
387 ppc4xx_sdr_t
*sdr
= opaque
;
397 ret
= (0xb5 << 8) | (1 << 4) | 9;
400 ret
= (5 << 29) | (2 << 26) | (1 << 24);
403 ret
= 1 << 20; /* No Security/Kasumi support */
406 ret
= SDR0_DDR0_DDRM_ENCODE(1) | SDR0_DDR0_DDRM_DDR1
;
410 ret
= (1 << 24) | (1 << 16);
414 ret
= (1 << 16) | (1 << 12);
435 static void dcr_write_sdr(void *opaque
, int dcrn
, uint32_t val
)
437 ppc4xx_sdr_t
*sdr
= opaque
;
445 case 0x00: /* B0CR */
456 static void sdr_reset(void *opaque
)
458 ppc4xx_sdr_t
*sdr
= opaque
;
463 void ppc4xx_sdr_init(CPUPPCState
*env
)
467 sdr
= g_malloc0(sizeof(*sdr
));
468 qemu_register_reset(&sdr_reset
, sdr
);
469 ppc_dcr_register(env
, SDR0_CFGADDR
,
470 sdr
, &dcr_read_sdr
, &dcr_write_sdr
);
471 ppc_dcr_register(env
, SDR0_CFGDATA
,
472 sdr
, &dcr_read_sdr
, &dcr_write_sdr
);
473 ppc_dcr_register(env
, SDR0_102
,
474 sdr
, &dcr_read_sdr
, &dcr_write_sdr
);
475 ppc_dcr_register(env
, SDR0_103
,
476 sdr
, &dcr_read_sdr
, &dcr_write_sdr
);
477 ppc_dcr_register(env
, SDR0_128
,
478 sdr
, &dcr_read_sdr
, &dcr_write_sdr
);
479 ppc_dcr_register(env
, SDR0_USB0
,
480 sdr
, &dcr_read_sdr
, &dcr_write_sdr
);
483 /*****************************************************************************/
484 /* SDRAM controller */
485 typedef struct ppc440_sdram_t
{
488 Ppc4xxSdramBank bank
[4];
492 SDRAM0_CFGADDR
= 0x10,
498 SDRAM_CONF1HB
= 0x45,
499 SDRAM_PLBADDULL
= 0x4a,
500 SDRAM_CONF1LL
= 0x4b,
501 SDRAM_CONFPATHB
= 0x4f,
502 SDRAM_PLBADDUHB
= 0x50,
505 static uint32_t sdram_bcr(hwaddr ram_base
, hwaddr ram_size
)
541 error_report("invalid RAM size " TARGET_FMT_plx
, ram_size
);
544 bcr
|= ram_base
>> 2 & 0xffe00000;
550 static inline hwaddr
sdram_base(uint32_t bcr
)
552 return (bcr
& 0xffe00000) << 2;
555 static uint64_t sdram_size(uint32_t bcr
)
560 sh
= 1024 - ((bcr
>> 6) & 0x3ff);
566 static void sdram_set_bcr(ppc440_sdram_t
*sdram
, int i
,
567 uint32_t bcr
, int enabled
)
569 if (sdram
->bank
[i
].bcr
& 1) {
570 /* First unmap RAM if enabled */
571 memory_region_del_subregion(get_system_memory(),
572 &sdram
->bank
[i
].container
);
573 memory_region_del_subregion(&sdram
->bank
[i
].container
,
574 &sdram
->bank
[i
].ram
);
575 object_unparent(OBJECT(&sdram
->bank
[i
].container
));
577 sdram
->bank
[i
].bcr
= bcr
& 0xffe0ffc1;
578 if (enabled
&& (bcr
& 1)) {
579 memory_region_init(&sdram
->bank
[i
].container
, NULL
, "sdram-container",
581 memory_region_add_subregion(&sdram
->bank
[i
].container
, 0,
582 &sdram
->bank
[i
].ram
);
583 memory_region_add_subregion(get_system_memory(),
585 &sdram
->bank
[i
].container
);
589 static void sdram_map_bcr(ppc440_sdram_t
*sdram
)
593 for (i
= 0; i
< sdram
->nbanks
; i
++) {
594 if (sdram
->bank
[i
].size
!= 0) {
595 sdram_set_bcr(sdram
, i
, sdram_bcr(sdram
->bank
[i
].base
,
596 sdram
->bank
[i
].size
), 1);
598 sdram_set_bcr(sdram
, i
, 0, 0);
603 static uint32_t dcr_read_sdram(void *opaque
, int dcrn
)
605 ppc440_sdram_t
*sdram
= opaque
;
613 if (sdram
->bank
[dcrn
- SDRAM_R0BAS
].size
) {
614 ret
= sdram_bcr(sdram
->bank
[dcrn
- SDRAM_R0BAS
].base
,
615 sdram
->bank
[dcrn
- SDRAM_R0BAS
].size
);
620 case SDRAM_CONFPATHB
:
621 case SDRAM_PLBADDULL
:
622 case SDRAM_PLBADDUHB
:
628 switch (sdram
->addr
) {
629 case 0x14: /* SDRAM_MCSTAT (405EX) */
633 case 0x21: /* SDRAM_MCOPT2 */
636 case 0x40: /* SDRAM_MB0CF */
639 case 0x7A: /* SDRAM_DLCR */
642 case 0xE1: /* SDR0_DDR0 */
643 ret
= SDR0_DDR0_DDRM_ENCODE(1) | SDR0_DDR0_DDRM_DDR1
;
656 static void dcr_write_sdram(void *opaque
, int dcrn
, uint32_t val
)
658 ppc440_sdram_t
*sdram
= opaque
;
667 case SDRAM_CONFPATHB
:
668 case SDRAM_PLBADDULL
:
669 case SDRAM_PLBADDUHB
:
675 switch (sdram
->addr
) {
676 case 0x00: /* B0CR */
687 static void sdram_reset(void *opaque
)
689 ppc440_sdram_t
*sdram
= opaque
;
694 void ppc440_sdram_init(CPUPPCState
*env
, int nbanks
,
695 MemoryRegion
*ram_memories
,
696 hwaddr
*ram_bases
, hwaddr
*ram_sizes
,
699 ppc440_sdram_t
*sdram
;
702 sdram
= g_malloc0(sizeof(*sdram
));
703 sdram
->nbanks
= nbanks
;
704 for (i
= 0; i
< nbanks
; i
++) {
705 sdram
->bank
[i
].ram
= ram_memories
[i
];
706 sdram
->bank
[i
].base
= ram_bases
[i
];
707 sdram
->bank
[i
].size
= ram_sizes
[i
];
709 qemu_register_reset(&sdram_reset
, sdram
);
710 ppc_dcr_register(env
, SDRAM0_CFGADDR
,
711 sdram
, &dcr_read_sdram
, &dcr_write_sdram
);
712 ppc_dcr_register(env
, SDRAM0_CFGDATA
,
713 sdram
, &dcr_read_sdram
, &dcr_write_sdram
);
715 sdram_map_bcr(sdram
);
718 ppc_dcr_register(env
, SDRAM_R0BAS
,
719 sdram
, &dcr_read_sdram
, &dcr_write_sdram
);
720 ppc_dcr_register(env
, SDRAM_R1BAS
,
721 sdram
, &dcr_read_sdram
, &dcr_write_sdram
);
722 ppc_dcr_register(env
, SDRAM_R2BAS
,
723 sdram
, &dcr_read_sdram
, &dcr_write_sdram
);
724 ppc_dcr_register(env
, SDRAM_R3BAS
,
725 sdram
, &dcr_read_sdram
, &dcr_write_sdram
);
726 ppc_dcr_register(env
, SDRAM_CONF1HB
,
727 sdram
, &dcr_read_sdram
, &dcr_write_sdram
);
728 ppc_dcr_register(env
, SDRAM_PLBADDULL
,
729 sdram
, &dcr_read_sdram
, &dcr_write_sdram
);
730 ppc_dcr_register(env
, SDRAM_CONF1LL
,
731 sdram
, &dcr_read_sdram
, &dcr_write_sdram
);
732 ppc_dcr_register(env
, SDRAM_CONFPATHB
,
733 sdram
, &dcr_read_sdram
, &dcr_write_sdram
);
734 ppc_dcr_register(env
, SDRAM_PLBADDUHB
,
735 sdram
, &dcr_read_sdram
, &dcr_write_sdram
);
738 /*****************************************************************************/
739 /* PLB to AHB bridge */
745 typedef struct ppc4xx_ahb_t
{
750 static uint32_t dcr_read_ahb(void *opaque
, int dcrn
)
752 ppc4xx_ahb_t
*ahb
= opaque
;
769 static void dcr_write_ahb(void *opaque
, int dcrn
, uint32_t val
)
771 ppc4xx_ahb_t
*ahb
= opaque
;
783 static void ppc4xx_ahb_reset(void *opaque
)
785 ppc4xx_ahb_t
*ahb
= opaque
;
792 void ppc4xx_ahb_init(CPUPPCState
*env
)
796 ahb
= g_malloc0(sizeof(*ahb
));
797 ppc_dcr_register(env
, AHB_TOP
, ahb
, &dcr_read_ahb
, &dcr_write_ahb
);
798 ppc_dcr_register(env
, AHB_BOT
, ahb
, &dcr_read_ahb
, &dcr_write_ahb
);
799 qemu_register_reset(ppc4xx_ahb_reset
, ahb
);
802 /*****************************************************************************/
805 #define DMA0_CR_CE (1 << 31)
806 #define DMA0_CR_PW (1 << 26 | 1 << 25)
807 #define DMA0_CR_DAI (1 << 24)
808 #define DMA0_CR_SAI (1 << 23)
809 #define DMA0_CR_DEC (1 << 2)
841 static uint32_t dcr_read_dma(void *opaque
, int dcrn
)
843 PPC4xxDmaState
*dma
= opaque
;
845 int addr
= dcrn
- dma
->base
;
852 val
= dma
->ch
[chnl
].cr
;
855 val
= dma
->ch
[chnl
].ct
;
858 val
= dma
->ch
[chnl
].sa
>> 32;
861 val
= dma
->ch
[chnl
].sa
;
864 val
= dma
->ch
[chnl
].da
>> 32;
867 val
= dma
->ch
[chnl
].da
;
870 val
= dma
->ch
[chnl
].sg
>> 32;
873 val
= dma
->ch
[chnl
].sg
;
881 qemu_log_mask(LOG_UNIMP
, "%s: unimplemented register %x (%d, %x)\n",
882 __func__
, dcrn
, chnl
, addr
);
888 static void dcr_write_dma(void *opaque
, int dcrn
, uint32_t val
)
890 PPC4xxDmaState
*dma
= opaque
;
891 int addr
= dcrn
- dma
->base
;
898 dma
->ch
[chnl
].cr
= val
;
899 if (val
& DMA0_CR_CE
) {
900 int count
= dma
->ch
[chnl
].ct
& 0xffff;
903 int width
, i
, sidx
, didx
;
904 uint8_t *rptr
, *wptr
;
909 width
= 1 << ((val
& DMA0_CR_PW
) >> 25);
910 xferlen
= count
* width
;
911 wlen
= rlen
= xferlen
;
912 rptr
= cpu_physical_memory_map(dma
->ch
[chnl
].sa
, &rlen
,
914 wptr
= cpu_physical_memory_map(dma
->ch
[chnl
].da
, &wlen
,
916 if (rptr
&& rlen
== xferlen
&& wptr
&& wlen
== xferlen
) {
917 if (!(val
& DMA0_CR_DEC
) &&
918 val
& DMA0_CR_SAI
&& val
& DMA0_CR_DAI
) {
919 /* optimise common case */
920 memmove(wptr
, rptr
, count
* width
);
921 sidx
= didx
= count
* width
;
923 /* do it the slow way */
924 for (sidx
= didx
= i
= 0; i
< count
; i
++) {
925 uint64_t v
= ldn_le_p(rptr
+ sidx
, width
);
926 stn_le_p(wptr
+ didx
, width
, v
);
927 if (val
& DMA0_CR_SAI
) {
930 if (val
& DMA0_CR_DAI
) {
937 cpu_physical_memory_unmap(wptr
, wlen
, 1, didx
);
940 cpu_physical_memory_unmap(rptr
, rlen
, 0, sidx
);
946 dma
->ch
[chnl
].ct
= val
;
949 dma
->ch
[chnl
].sa
&= 0xffffffffULL
;
950 dma
->ch
[chnl
].sa
|= (uint64_t)val
<< 32;
953 dma
->ch
[chnl
].sa
&= 0xffffffff00000000ULL
;
954 dma
->ch
[chnl
].sa
|= val
;
957 dma
->ch
[chnl
].da
&= 0xffffffffULL
;
958 dma
->ch
[chnl
].da
|= (uint64_t)val
<< 32;
961 dma
->ch
[chnl
].da
&= 0xffffffff00000000ULL
;
962 dma
->ch
[chnl
].da
|= val
;
965 dma
->ch
[chnl
].sg
&= 0xffffffffULL
;
966 dma
->ch
[chnl
].sg
|= (uint64_t)val
<< 32;
969 dma
->ch
[chnl
].sg
&= 0xffffffff00000000ULL
;
970 dma
->ch
[chnl
].sg
|= val
;
978 qemu_log_mask(LOG_UNIMP
, "%s: unimplemented register %x (%d, %x)\n",
979 __func__
, dcrn
, chnl
, addr
);
983 static void ppc4xx_dma_reset(void *opaque
)
985 PPC4xxDmaState
*dma
= opaque
;
986 int dma_base
= dma
->base
;
988 memset(dma
, 0, sizeof(*dma
));
989 dma
->base
= dma_base
;
992 void ppc4xx_dma_init(CPUPPCState
*env
, int dcr_base
)
997 dma
= g_malloc0(sizeof(*dma
));
998 dma
->base
= dcr_base
;
999 qemu_register_reset(&ppc4xx_dma_reset
, dma
);
1000 for (i
= 0; i
< 4; i
++) {
1001 ppc_dcr_register(env
, dcr_base
+ i
* 8 + DMA0_CR
,
1002 dma
, &dcr_read_dma
, &dcr_write_dma
);
1003 ppc_dcr_register(env
, dcr_base
+ i
* 8 + DMA0_CT
,
1004 dma
, &dcr_read_dma
, &dcr_write_dma
);
1005 ppc_dcr_register(env
, dcr_base
+ i
* 8 + DMA0_SAH
,
1006 dma
, &dcr_read_dma
, &dcr_write_dma
);
1007 ppc_dcr_register(env
, dcr_base
+ i
* 8 + DMA0_SAL
,
1008 dma
, &dcr_read_dma
, &dcr_write_dma
);
1009 ppc_dcr_register(env
, dcr_base
+ i
* 8 + DMA0_DAH
,
1010 dma
, &dcr_read_dma
, &dcr_write_dma
);
1011 ppc_dcr_register(env
, dcr_base
+ i
* 8 + DMA0_DAL
,
1012 dma
, &dcr_read_dma
, &dcr_write_dma
);
1013 ppc_dcr_register(env
, dcr_base
+ i
* 8 + DMA0_SGH
,
1014 dma
, &dcr_read_dma
, &dcr_write_dma
);
1015 ppc_dcr_register(env
, dcr_base
+ i
* 8 + DMA0_SGL
,
1016 dma
, &dcr_read_dma
, &dcr_write_dma
);
1018 ppc_dcr_register(env
, dcr_base
+ DMA0_SR
,
1019 dma
, &dcr_read_dma
, &dcr_write_dma
);
1020 ppc_dcr_register(env
, dcr_base
+ DMA0_SGC
,
1021 dma
, &dcr_read_dma
, &dcr_write_dma
);
1022 ppc_dcr_register(env
, dcr_base
+ DMA0_SLP
,
1023 dma
, &dcr_read_dma
, &dcr_write_dma
);
1024 ppc_dcr_register(env
, dcr_base
+ DMA0_POL
,
1025 dma
, &dcr_read_dma
, &dcr_write_dma
);
1028 /*****************************************************************************/
1029 /* PCI Express controller */
1031 * FIXME: This is not complete and does not work, only implemented partially
1032 * to allow firmware and guests to find an empty bus. Cards should use PCI.
1034 #include "hw/pci/pcie_host.h"
1036 #define TYPE_PPC460EX_PCIE_HOST "ppc460ex-pcie-host"
1037 OBJECT_DECLARE_SIMPLE_TYPE(PPC460EXPCIEState
, PPC460EX_PCIE_HOST
)
1039 struct PPC460EXPCIEState
{
1040 PCIExpressHost host
;
1062 #define DCRN_PCIE0_BASE 0x100
1063 #define DCRN_PCIE1_BASE 0x120
1091 static uint32_t dcr_read_pcie(void *opaque
, int dcrn
)
1093 PPC460EXPCIEState
*state
= opaque
;
1096 switch (dcrn
- state
->dcrn_base
) {
1098 ret
= state
->cfg_base
>> 32;
1101 ret
= state
->cfg_base
;
1104 ret
= state
->cfg_mask
;
1107 ret
= state
->msg_base
>> 32;
1110 ret
= state
->msg_base
;
1113 ret
= state
->msg_mask
;
1116 ret
= state
->omr1_base
>> 32;
1119 ret
= state
->omr1_base
;
1121 case PEGPL_OMR1MSKH
:
1122 ret
= state
->omr1_mask
>> 32;
1124 case PEGPL_OMR1MSKL
:
1125 ret
= state
->omr1_mask
;
1128 ret
= state
->omr2_base
>> 32;
1131 ret
= state
->omr2_base
;
1133 case PEGPL_OMR2MSKH
:
1134 ret
= state
->omr2_mask
>> 32;
1136 case PEGPL_OMR2MSKL
:
1137 ret
= state
->omr3_mask
;
1140 ret
= state
->omr3_base
>> 32;
1143 ret
= state
->omr3_base
;
1145 case PEGPL_OMR3MSKH
:
1146 ret
= state
->omr3_mask
>> 32;
1148 case PEGPL_OMR3MSKL
:
1149 ret
= state
->omr3_mask
;
1152 ret
= state
->reg_base
>> 32;
1155 ret
= state
->reg_base
;
1158 ret
= state
->reg_mask
;
1161 ret
= state
->special
;
1171 static void dcr_write_pcie(void *opaque
, int dcrn
, uint32_t val
)
1173 PPC460EXPCIEState
*s
= opaque
;
1176 switch (dcrn
- s
->dcrn_base
) {
1178 s
->cfg_base
= ((uint64_t)val
<< 32) | (s
->cfg_base
& 0xffffffff);
1181 s
->cfg_base
= (s
->cfg_base
& 0xffffffff00000000ULL
) | val
;
1185 size
= ~(val
& 0xfffffffe) + 1;
1187 * Firmware sets this register to E0000001. Why we are not sure,
1188 * but the current guess is anything above PCIE_MMCFG_SIZE_MAX is
1191 if (size
> PCIE_MMCFG_SIZE_MAX
) {
1192 size
= PCIE_MMCFG_SIZE_MAX
;
1194 pcie_host_mmcfg_update(PCIE_HOST_BRIDGE(s
), val
& 1, s
->cfg_base
, size
);
1197 s
->msg_base
= ((uint64_t)val
<< 32) | (s
->msg_base
& 0xffffffff);
1200 s
->msg_base
= (s
->msg_base
& 0xffffffff00000000ULL
) | val
;
1206 s
->omr1_base
= ((uint64_t)val
<< 32) | (s
->omr1_base
& 0xffffffff);
1209 s
->omr1_base
= (s
->omr1_base
& 0xffffffff00000000ULL
) | val
;
1211 case PEGPL_OMR1MSKH
:
1212 s
->omr1_mask
= ((uint64_t)val
<< 32) | (s
->omr1_mask
& 0xffffffff);
1214 case PEGPL_OMR1MSKL
:
1215 s
->omr1_mask
= (s
->omr1_mask
& 0xffffffff00000000ULL
) | val
;
1218 s
->omr2_base
= ((uint64_t)val
<< 32) | (s
->omr2_base
& 0xffffffff);
1221 s
->omr2_base
= (s
->omr2_base
& 0xffffffff00000000ULL
) | val
;
1223 case PEGPL_OMR2MSKH
:
1224 s
->omr2_mask
= ((uint64_t)val
<< 32) | (s
->omr2_mask
& 0xffffffff);
1226 case PEGPL_OMR2MSKL
:
1227 s
->omr2_mask
= (s
->omr2_mask
& 0xffffffff00000000ULL
) | val
;
1230 s
->omr3_base
= ((uint64_t)val
<< 32) | (s
->omr3_base
& 0xffffffff);
1233 s
->omr3_base
= (s
->omr3_base
& 0xffffffff00000000ULL
) | val
;
1235 case PEGPL_OMR3MSKH
:
1236 s
->omr3_mask
= ((uint64_t)val
<< 32) | (s
->omr3_mask
& 0xffffffff);
1238 case PEGPL_OMR3MSKL
:
1239 s
->omr3_mask
= (s
->omr3_mask
& 0xffffffff00000000ULL
) | val
;
1242 s
->reg_base
= ((uint64_t)val
<< 32) | (s
->reg_base
& 0xffffffff);
1245 s
->reg_base
= (s
->reg_base
& 0xffffffff00000000ULL
) | val
;
1249 /* FIXME: how is size encoded? */
1250 size
= (val
== 0x7001 ? 4096 : ~(val
& 0xfffffffe) + 1);
1261 static void ppc460ex_set_irq(void *opaque
, int irq_num
, int level
)
1263 PPC460EXPCIEState
*s
= opaque
;
1264 qemu_set_irq(s
->irq
[irq_num
], level
);
1267 static void ppc460ex_pcie_realize(DeviceState
*dev
, Error
**errp
)
1269 PPC460EXPCIEState
*s
= PPC460EX_PCIE_HOST(dev
);
1270 PCIHostState
*pci
= PCI_HOST_BRIDGE(dev
);
1274 switch (s
->dcrn_base
) {
1275 case DCRN_PCIE0_BASE
:
1278 case DCRN_PCIE1_BASE
:
1282 error_setg(errp
, "invalid PCIe DCRN base");
1285 snprintf(buf
, sizeof(buf
), "pcie%d-io", id
);
1286 memory_region_init(&s
->iomem
, OBJECT(s
), buf
, UINT64_MAX
);
1287 for (i
= 0; i
< 4; i
++) {
1288 sysbus_init_irq(SYS_BUS_DEVICE(dev
), &s
->irq
[i
]);
1290 snprintf(buf
, sizeof(buf
), "pcie.%d", id
);
1291 pci
->bus
= pci_register_root_bus(DEVICE(s
), buf
, ppc460ex_set_irq
,
1292 pci_swizzle_map_irq_fn
, s
, &s
->iomem
,
1293 get_system_io(), 0, 4, TYPE_PCIE_BUS
);
1296 static Property ppc460ex_pcie_props
[] = {
1297 DEFINE_PROP_INT32("dcrn-base", PPC460EXPCIEState
, dcrn_base
, -1),
1298 DEFINE_PROP_END_OF_LIST(),
1301 static void ppc460ex_pcie_class_init(ObjectClass
*klass
, void *data
)
1303 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1305 set_bit(DEVICE_CATEGORY_BRIDGE
, dc
->categories
);
1306 dc
->realize
= ppc460ex_pcie_realize
;
1307 device_class_set_props(dc
, ppc460ex_pcie_props
);
1308 dc
->hotpluggable
= false;
1311 static const TypeInfo ppc460ex_pcie_host_info
= {
1312 .name
= TYPE_PPC460EX_PCIE_HOST
,
1313 .parent
= TYPE_PCIE_HOST_BRIDGE
,
1314 .instance_size
= sizeof(PPC460EXPCIEState
),
1315 .class_init
= ppc460ex_pcie_class_init
,
1318 static void ppc460ex_pcie_register(void)
1320 type_register_static(&ppc460ex_pcie_host_info
);
1323 type_init(ppc460ex_pcie_register
)
1325 static void ppc460ex_pcie_register_dcrs(PPC460EXPCIEState
*s
, CPUPPCState
*env
)
1327 ppc_dcr_register(env
, s
->dcrn_base
+ PEGPL_CFGBAH
, s
,
1328 &dcr_read_pcie
, &dcr_write_pcie
);
1329 ppc_dcr_register(env
, s
->dcrn_base
+ PEGPL_CFGBAL
, s
,
1330 &dcr_read_pcie
, &dcr_write_pcie
);
1331 ppc_dcr_register(env
, s
->dcrn_base
+ PEGPL_CFGMSK
, s
,
1332 &dcr_read_pcie
, &dcr_write_pcie
);
1333 ppc_dcr_register(env
, s
->dcrn_base
+ PEGPL_MSGBAH
, s
,
1334 &dcr_read_pcie
, &dcr_write_pcie
);
1335 ppc_dcr_register(env
, s
->dcrn_base
+ PEGPL_MSGBAL
, s
,
1336 &dcr_read_pcie
, &dcr_write_pcie
);
1337 ppc_dcr_register(env
, s
->dcrn_base
+ PEGPL_MSGMSK
, s
,
1338 &dcr_read_pcie
, &dcr_write_pcie
);
1339 ppc_dcr_register(env
, s
->dcrn_base
+ PEGPL_OMR1BAH
, s
,
1340 &dcr_read_pcie
, &dcr_write_pcie
);
1341 ppc_dcr_register(env
, s
->dcrn_base
+ PEGPL_OMR1BAL
, s
,
1342 &dcr_read_pcie
, &dcr_write_pcie
);
1343 ppc_dcr_register(env
, s
->dcrn_base
+ PEGPL_OMR1MSKH
, s
,
1344 &dcr_read_pcie
, &dcr_write_pcie
);
1345 ppc_dcr_register(env
, s
->dcrn_base
+ PEGPL_OMR1MSKL
, s
,
1346 &dcr_read_pcie
, &dcr_write_pcie
);
1347 ppc_dcr_register(env
, s
->dcrn_base
+ PEGPL_OMR2BAH
, s
,
1348 &dcr_read_pcie
, &dcr_write_pcie
);
1349 ppc_dcr_register(env
, s
->dcrn_base
+ PEGPL_OMR2BAL
, s
,
1350 &dcr_read_pcie
, &dcr_write_pcie
);
1351 ppc_dcr_register(env
, s
->dcrn_base
+ PEGPL_OMR2MSKH
, s
,
1352 &dcr_read_pcie
, &dcr_write_pcie
);
1353 ppc_dcr_register(env
, s
->dcrn_base
+ PEGPL_OMR2MSKL
, s
,
1354 &dcr_read_pcie
, &dcr_write_pcie
);
1355 ppc_dcr_register(env
, s
->dcrn_base
+ PEGPL_OMR3BAH
, s
,
1356 &dcr_read_pcie
, &dcr_write_pcie
);
1357 ppc_dcr_register(env
, s
->dcrn_base
+ PEGPL_OMR3BAL
, s
,
1358 &dcr_read_pcie
, &dcr_write_pcie
);
1359 ppc_dcr_register(env
, s
->dcrn_base
+ PEGPL_OMR3MSKH
, s
,
1360 &dcr_read_pcie
, &dcr_write_pcie
);
1361 ppc_dcr_register(env
, s
->dcrn_base
+ PEGPL_OMR3MSKL
, s
,
1362 &dcr_read_pcie
, &dcr_write_pcie
);
1363 ppc_dcr_register(env
, s
->dcrn_base
+ PEGPL_REGBAH
, s
,
1364 &dcr_read_pcie
, &dcr_write_pcie
);
1365 ppc_dcr_register(env
, s
->dcrn_base
+ PEGPL_REGBAL
, s
,
1366 &dcr_read_pcie
, &dcr_write_pcie
);
1367 ppc_dcr_register(env
, s
->dcrn_base
+ PEGPL_REGMSK
, s
,
1368 &dcr_read_pcie
, &dcr_write_pcie
);
1369 ppc_dcr_register(env
, s
->dcrn_base
+ PEGPL_SPECIAL
, s
,
1370 &dcr_read_pcie
, &dcr_write_pcie
);
1371 ppc_dcr_register(env
, s
->dcrn_base
+ PEGPL_CFG
, s
,
1372 &dcr_read_pcie
, &dcr_write_pcie
);
1375 void ppc460ex_pcie_init(CPUPPCState
*env
)
1379 dev
= qdev_new(TYPE_PPC460EX_PCIE_HOST
);
1380 qdev_prop_set_int32(dev
, "dcrn-base", DCRN_PCIE0_BASE
);
1381 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
1382 ppc460ex_pcie_register_dcrs(PPC460EX_PCIE_HOST(dev
), env
);
1384 dev
= qdev_new(TYPE_PPC460EX_PCIE_HOST
);
1385 qdev_prop_set_int32(dev
, "dcrn-base", DCRN_PCIE1_BASE
);
1386 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
1387 ppc460ex_pcie_register_dcrs(PPC460EX_PCIE_HOST(dev
), env
);