target/sparc/cpu-param.h

   1 /*
   2  * Sparc cpu parameters for qemu.
   3  *
   4  * SPDX-License-Identifier: LGPL-2.0+
   5  */
   6
   7 #ifndef SPARC_CPU_PARAM_H
   8 #define SPARC_CPU_PARAM_H
   9
  10 #ifdef TARGET_SPARC64
  11 # define TARGET_LONG_BITS 64
  12 # define TARGET_PAGE_BITS 13 /* 8k */
  13 # define TARGET_PHYS_ADDR_SPACE_BITS  41
  14 # ifdef TARGET_ABI32
  15 #  define TARGET_VIRT_ADDR_SPACE_BITS 32
  16 # else
  17 #  define TARGET_VIRT_ADDR_SPACE_BITS 44
  18 # endif
  19 #else
  20 # define TARGET_LONG_BITS 32
  21 # define TARGET_PAGE_BITS 12 /* 4k */
  22 # define TARGET_PHYS_ADDR_SPACE_BITS 36
  23 # define TARGET_VIRT_ADDR_SPACE_BITS 32
  24 #endif
  25
  26 /*
  27  * From Oracle SPARC Architecture 2015:
  28  *
  29  *   Compatibility notes: The PSO memory model described in SPARC V8 and
  30  *   SPARC V9 compatibility architecture specifications was never implemented
  31  *   in a SPARC V9 implementation and is not included in the Oracle SPARC
  32  *   Architecture specification.
  33  *
  34  *   The RMO memory model described in the SPARC V9 specification was
  35  *   implemented in some non-Sun SPARC V9 implementations, but is not
  36  *   directly supported in Oracle SPARC Architecture 2015 implementations.
  37  *
  38  * Therefore always use TSO in QEMU.
  39  *
  40  * D.5 Specification of Partial Store Order (PSO)
  41  *   ... [loads] are followed by an implied MEMBAR #LoadLoad | #LoadStore.
  42  *
  43  * D.6 Specification of Total Store Order (TSO)
  44  *   ... PSO with the additional requirement that all [stores] are followed
  45  *   by an implied MEMBAR #StoreStore.
  46  */
  47 #define TCG_GUEST_DEFAULT_MO  (TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_MO_ST_ST)
  48
  49 #endif