hw/hppa/lasi.c

   1 /*
   2  * HP-PARISC Lasi chipset emulation.
   3  *
   4  * (C) 2019 by Helge Deller <deller@gmx.de>
   5  *
   6  * This work is licensed under the GNU GPL license version 2 or later.
   7  *
   8  * Documentation available at:
   9  * https://parisc.wiki.kernel.org/images-parisc/7/79/Lasi_ers.pdf
  10  */
  11
  12 #include "qemu/osdep.h"
  13 #include "qemu/units.h"
  14 #include "qemu/log.h"
  15 #include "qapi/error.h"
  16 #include "trace.h"
  17 #include "hw/irq.h"
  18 #include "sysemu/sysemu.h"
  19 #include "sysemu/runstate.h"
  20 #include "hppa_sys.h"
  21 #include "hw/net/lasi_82596.h"
  22 #include "hw/char/parallel.h"
  23 #include "hw/char/serial.h"
  24 #include "hw/input/lasips2.h"
  25 #include "migration/vmstate.h"
  26 #include "qom/object.h"
  27
  28 #define TYPE_LASI_CHIP "lasi-chip"
  29
  30 #define LASI_IRR        0x00    /* RO */
  31 #define LASI_IMR        0x04
  32 #define LASI_IPR        0x08
  33 #define LASI_ICR        0x0c
  34 #define LASI_IAR        0x10
  35
  36 #define LASI_PCR        0x0C000 /* LASI Power Control register */
  37 #define LASI_ERRLOG     0x0C004 /* LASI Error Logging register */
  38 #define LASI_VER        0x0C008 /* LASI Version Control register */
  39 #define LASI_IORESET    0x0C00C /* LASI I/O Reset register */
  40 #define LASI_AMR        0x0C010 /* LASI Arbitration Mask register */
  41 #define LASI_IO_CONF    0x7FFFE /* LASI primary configuration register */
  42 #define LASI_IO_CONF2   0x7FFFF /* LASI secondary configuration register */
  43
  44 #define LASI_BIT(x)     (1ul << (x))
  45 #define LASI_IRQ_BITS   (LASI_BIT(5) | LASI_BIT(7) | LASI_BIT(8) | LASI_BIT(9) \
  46             | LASI_BIT(13) | LASI_BIT(14) | LASI_BIT(16) | LASI_BIT(17) \
  47             | LASI_BIT(18) | LASI_BIT(19) | LASI_BIT(20) | LASI_BIT(21) \
  48             | LASI_BIT(26))
  49
  50 #define ICR_BUS_ERROR_BIT  LASI_BIT(8)  /* bit 8 in ICR */
  51 #define ICR_TOC_BIT        LASI_BIT(1)  /* bit 1 in ICR */
  52
  53 OBJECT_DECLARE_SIMPLE_TYPE(LasiState, LASI_CHIP)
  54
  55 struct LasiState {
  56     PCIHostState parent_obj;
  57
  58     uint32_t irr;
  59     uint32_t imr;
  60     uint32_t ipr;
  61     uint32_t icr;
  62     uint32_t iar;
  63
  64     uint32_t errlog;
  65     uint32_t amr;
  66     uint32_t rtc;
  67     time_t rtc_ref;
  68
  69     MemoryRegion this_mem;
  70 };
  71
  72 static bool lasi_chip_mem_valid(void *opaque, hwaddr addr,
  73                                 unsigned size, bool is_write,
  74                                 MemTxAttrs attrs)
  75 {
  76     bool ret = false;
  77
  78     switch (addr) {
  79     case LASI_IRR:
  80     case LASI_IMR:
  81     case LASI_IPR:
  82     case LASI_ICR:
  83     case LASI_IAR:
  84
  85     case (LASI_LAN_HPA - LASI_HPA):
  86     case (LASI_LPT_HPA - LASI_HPA):
  87     case (LASI_UART_HPA - LASI_HPA):
  88     case (LASI_RTC_HPA - LASI_HPA):
  89
  90     case LASI_PCR ... LASI_AMR:
  91         ret = true;
  92     }
  93
  94     trace_lasi_chip_mem_valid(addr, ret);
  95     return ret;
  96 }
  97
  98 static MemTxResult lasi_chip_read_with_attrs(void *opaque, hwaddr addr,
  99                                              uint64_t *data, unsigned size,
 100                                              MemTxAttrs attrs)
 101 {
 102     LasiState *s = opaque;
 103     MemTxResult ret = MEMTX_OK;
 104     uint32_t val;
 105
 106     switch (addr) {
 107     case LASI_IRR:
 108         val = s->irr;
 109         break;
 110     case LASI_IMR:
 111         val = s->imr;
 112         break;
 113     case LASI_IPR:
 114         val = s->ipr;
 115         /* Any read to IPR clears the register.  */
 116         s->ipr = 0;
 117         break;
 118     case LASI_ICR:
 119         val = s->icr & ICR_BUS_ERROR_BIT; /* bus_error */
 120         break;
 121     case LASI_IAR:
 122         val = s->iar;
 123         break;
 124
 125     case (LASI_LAN_HPA - LASI_HPA):
 126     case (LASI_LPT_HPA - LASI_HPA):
 127     case (LASI_UART_HPA - LASI_HPA):
 128         val = 0;
 129         break;
 130     case (LASI_RTC_HPA - LASI_HPA):
 131         val = time(NULL);
 132         val += s->rtc_ref;
 133         break;
 134
 135     case LASI_PCR:
 136     case LASI_VER:      /* only version 0 existed. */
 137     case LASI_IORESET:
 138         val = 0;
 139         break;
 140     case LASI_ERRLOG:
 141         val = s->errlog;
 142         break;
 143     case LASI_AMR:
 144         val = s->amr;
 145         break;
 146
 147     default:
 148         /* Controlled by lasi_chip_mem_valid above. */
 149         g_assert_not_reached();
 150     }
 151
 152     trace_lasi_chip_read(addr, val);
 153
 154     *data = val;
 155     return ret;
 156 }
 157
 158 static MemTxResult lasi_chip_write_with_attrs(void *opaque, hwaddr addr,
 159                                               uint64_t val, unsigned size,
 160                                               MemTxAttrs attrs)
 161 {
 162     LasiState *s = opaque;
 163
 164     trace_lasi_chip_write(addr, val);
 165
 166     switch (addr) {
 167     case LASI_IRR:
 168         /* read-only.  */
 169         break;
 170     case LASI_IMR:
 171         s->imr = val;
 172         if (((val & LASI_IRQ_BITS) != val) && (val != 0xffffffff)) {
 173             qemu_log_mask(LOG_GUEST_ERROR,
 174                 "LASI: tried to set invalid %lx IMR value.\n",
 175                 (unsigned long) val);
 176         }
 177         break;
 178     case LASI_IPR:
 179         /* Any write to IPR clears the register. */
 180         s->ipr = 0;
 181         break;
 182     case LASI_ICR:
 183         s->icr = val;
 184         /* if (val & ICR_TOC_BIT) issue_toc(); */
 185         break;
 186     case LASI_IAR:
 187         s->iar = val;
 188         break;
 189
 190     case (LASI_LAN_HPA - LASI_HPA):
 191         /* XXX: reset LAN card */
 192         break;
 193     case (LASI_LPT_HPA - LASI_HPA):
 194         /* XXX: reset parallel port */
 195         break;
 196     case (LASI_UART_HPA - LASI_HPA):
 197         /* XXX: reset serial port */
 198         break;
 199     case (LASI_RTC_HPA - LASI_HPA):
 200         s->rtc_ref = val - time(NULL);
 201         break;
 202
 203     case LASI_PCR:
 204         if (val == 0x02) { /* immediately power off */
 205             qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
 206         }
 207         break;
 208     case LASI_ERRLOG:
 209         s->errlog = val;
 210         break;
 211     case LASI_VER:
 212         /* read-only.  */
 213         break;
 214     case LASI_IORESET:
 215         break;  /* XXX: TODO: Reset various devices. */
 216     case LASI_AMR:
 217         s->amr = val;
 218         break;
 219
 220     default:
 221         /* Controlled by lasi_chip_mem_valid above. */
 222         g_assert_not_reached();
 223     }
 224     return MEMTX_OK;
 225 }
 226
 227 static const MemoryRegionOps lasi_chip_ops = {
 228     .read_with_attrs = lasi_chip_read_with_attrs,
 229     .write_with_attrs = lasi_chip_write_with_attrs,
 230     .endianness = DEVICE_BIG_ENDIAN,
 231     .valid = {
 232         .min_access_size = 1,
 233         .max_access_size = 4,
 234         .accepts = lasi_chip_mem_valid,
 235     },
 236     .impl = {
 237         .min_access_size = 1,
 238         .max_access_size = 4,
 239     },
 240 };
 241
 242 static const VMStateDescription vmstate_lasi = {
 243     .name = "Lasi",
 244     .version_id = 1,
 245     .minimum_version_id = 1,
 246     .fields = (VMStateField[]) {
 247         VMSTATE_UINT32(irr, LasiState),
 248         VMSTATE_UINT32(imr, LasiState),
 249         VMSTATE_UINT32(ipr, LasiState),
 250         VMSTATE_UINT32(icr, LasiState),
 251         VMSTATE_UINT32(iar, LasiState),
 252         VMSTATE_UINT32(errlog, LasiState),
 253         VMSTATE_UINT32(amr, LasiState),
 254         VMSTATE_END_OF_LIST()
 255     }
 256 };
 257
 258
 259 static void lasi_set_irq(void *opaque, int irq, int level)
 260 {
 261     LasiState *s = opaque;
 262     uint32_t bit = 1u << irq;
 263
 264     if (level) {
 265         s->ipr |= bit;
 266         if (bit & s->imr) {
 267             uint32_t iar = s->iar;
 268             s->irr |= bit;
 269             if ((s->icr & ICR_BUS_ERROR_BIT) == 0) {
 270                 stl_be_phys(&address_space_memory, iar & -32, iar & 31);
 271             }
 272         }
 273     }
 274 }
 275
 276 static int lasi_get_irq(unsigned long hpa)
 277 {
 278     switch (hpa) {
 279     case LASI_HPA:
 280         return 14;
 281     case LASI_UART_HPA:
 282         return 5;
 283     case LASI_LPT_HPA:
 284         return 7;
 285     case LASI_LAN_HPA:
 286         return 8;
 287     case LASI_SCSI_HPA:
 288         return 9;
 289     case LASI_AUDIO_HPA:
 290         return 13;
 291     case LASI_PS2KBD_HPA:
 292     case LASI_PS2MOU_HPA:
 293         return 26;
 294     default:
 295         g_assert_not_reached();
 296     }
 297 }
 298
 299 DeviceState *lasi_init(MemoryRegion *address_space)
 300 {
 301     DeviceState *dev;
 302     LasiState *s;
 303
 304     dev = qdev_new(TYPE_LASI_CHIP);
 305     s = LASI_CHIP(dev);
 306     s->iar = CPU_HPA + 3;
 307
 308     /* Lasi access from main memory.  */
 309     memory_region_init_io(&s->this_mem, OBJECT(s), &lasi_chip_ops,
 310                           s, "lasi", 0x100000);
 311     memory_region_add_subregion(address_space, LASI_HPA, &s->this_mem);
 312
 313     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
 314
 315     /* LAN */
 316     if (enable_lasi_lan()) {
 317         qemu_irq lan_irq = qemu_allocate_irq(lasi_set_irq, s,
 318                 lasi_get_irq(LASI_LAN_HPA));
 319         lasi_82596_init(address_space, LASI_LAN_HPA, lan_irq);
 320     }
 321
 322     /* Parallel port */
 323     qemu_irq lpt_irq = qemu_allocate_irq(lasi_set_irq, s,
 324             lasi_get_irq(LASI_LPT_HPA));
 325     parallel_mm_init(address_space, LASI_LPT_HPA + 0x800, 0,
 326                      lpt_irq, parallel_hds[0]);
 327
 328     /* Real time clock (RTC), it's only one 32-bit counter @9000 */
 329
 330     s->rtc = time(NULL);
 331     s->rtc_ref = 0;
 332
 333     if (serial_hd(1)) {
 334         /* Serial port */
 335         qemu_irq serial_irq = qemu_allocate_irq(lasi_set_irq, s,
 336                 lasi_get_irq(LASI_UART_HPA));
 337         serial_mm_init(address_space, LASI_UART_HPA + 0x800, 0,
 338                 serial_irq, 8000000 / 16,
 339                 serial_hd(0), DEVICE_NATIVE_ENDIAN);
 340     }
 341
 342     /* PS/2 Keyboard/Mouse */
 343     qemu_irq ps2kbd_irq = qemu_allocate_irq(lasi_set_irq, s,
 344             lasi_get_irq(LASI_PS2KBD_HPA));
 345     lasips2_init(address_space, LASI_PS2KBD_HPA,  ps2kbd_irq);
 346
 347     return dev;
 348 }
 349
 350 static void lasi_class_init(ObjectClass *klass, void *data)
 351 {
 352     DeviceClass *dc = DEVICE_CLASS(klass);
 353
 354     dc->vmsd = &vmstate_lasi;
 355 }
 356
 357 static const TypeInfo lasi_pcihost_info = {
 358     .name          = TYPE_LASI_CHIP,
 359     .parent        = TYPE_SYS_BUS_DEVICE,
 360     .instance_size = sizeof(LasiState),
 361     .class_init    = lasi_class_init,
 362 };
 363
 364 static void lasi_register_types(void)
 365 {
 366     type_register_static(&lasi_pcihost_info);
 367 }
 368
 369 type_init(lasi_register_types)