2 * QEMU PowerPC e500-based platforms
4 * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
6 * Author: Yu Liu, <yu.liu@freescale.com>
8 * This file is derived from hw/ppc440_bamboo.c,
9 * the copyright for that material belongs to the original owners.
11 * This is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
17 #include "qemu/osdep.h"
18 #include "qemu/datadir.h"
19 #include "qemu/units.h"
20 #include "qapi/error.h"
22 #include "e500-ccsr.h"
24 #include "qemu/config-file.h"
25 #include "hw/char/serial.h"
26 #include "hw/pci/pci.h"
27 #include "sysemu/sysemu.h"
28 #include "sysemu/kvm.h"
29 #include "sysemu/reset.h"
30 #include "sysemu/runstate.h"
32 #include "sysemu/device_tree.h"
33 #include "hw/ppc/openpic.h"
34 #include "hw/ppc/openpic_kvm.h"
35 #include "hw/ppc/ppc.h"
36 #include "hw/qdev-properties.h"
37 #include "hw/loader.h"
39 #include "hw/sysbus.h"
40 #include "qemu/host-utils.h"
41 #include "qemu/option.h"
42 #include "hw/pci-host/ppce500.h"
43 #include "qemu/error-report.h"
44 #include "hw/platform-bus.h"
45 #include "hw/net/fsl_etsec/etsec.h"
46 #include "hw/i2c/i2c.h"
49 #define EPAPR_MAGIC (0x45504150)
50 #define DTC_LOAD_PAD 0x1800000
51 #define DTC_PAD_MASK 0xFFFFF
52 #define DTB_MAX_SIZE (8 * MiB)
53 #define INITRD_LOAD_PAD 0x2000000
54 #define INITRD_PAD_MASK 0xFFFFFF
56 #define RAM_SIZES_ALIGN (64 * MiB)
58 /* TODO: parameterize */
59 #define MPC8544_CCSRBAR_SIZE 0x00100000ULL
60 #define MPC8544_MPIC_REGS_OFFSET 0x40000ULL
61 #define MPC8544_MSI_REGS_OFFSET 0x41600ULL
62 #define MPC8544_SERIAL0_REGS_OFFSET 0x4500ULL
63 #define MPC8544_SERIAL1_REGS_OFFSET 0x4600ULL
64 #define MPC8544_PCI_REGS_OFFSET 0x8000ULL
65 #define MPC8544_PCI_REGS_SIZE 0x1000ULL
66 #define MPC8544_UTIL_OFFSET 0xe0000ULL
67 #define MPC8XXX_GPIO_OFFSET 0x000FF000ULL
68 #define MPC8544_I2C_REGS_OFFSET 0x3000ULL
69 #define MPC8XXX_GPIO_IRQ 47
70 #define MPC8544_I2C_IRQ 43
71 #define RTC_REGS_OFFSET 0x68
73 #define PLATFORM_CLK_FREQ_HZ (400 * 1000 * 1000)
82 static uint32_t *pci_map_create(void *fdt
, uint32_t mpic
, int first_slot
,
83 int nr_slots
, int *len
)
89 int last_slot
= first_slot
+ nr_slots
;
92 *len
= nr_slots
* 4 * 7 * sizeof(uint32_t);
93 pci_map
= g_malloc(*len
);
95 for (slot
= first_slot
; slot
< last_slot
; slot
++) {
96 for (pci_irq
= 0; pci_irq
< 4; pci_irq
++) {
97 pci_map
[i
++] = cpu_to_be32(slot
<< 11);
98 pci_map
[i
++] = cpu_to_be32(0x0);
99 pci_map
[i
++] = cpu_to_be32(0x0);
100 pci_map
[i
++] = cpu_to_be32(pci_irq
+ 1);
101 pci_map
[i
++] = cpu_to_be32(mpic
);
102 host_irq
= ppce500_pci_map_irq_slot(slot
, pci_irq
);
103 pci_map
[i
++] = cpu_to_be32(host_irq
+ 1);
104 pci_map
[i
++] = cpu_to_be32(0x1);
108 assert((i
* sizeof(uint32_t)) == *len
);
113 static void dt_serial_create(void *fdt
, unsigned long long offset
,
114 const char *soc
, const char *mpic
,
115 const char *alias
, int idx
, bool defcon
)
119 ser
= g_strdup_printf("%s/serial@%llx", soc
, offset
);
120 qemu_fdt_add_subnode(fdt
, ser
);
121 qemu_fdt_setprop_string(fdt
, ser
, "device_type", "serial");
122 qemu_fdt_setprop_string(fdt
, ser
, "compatible", "ns16550");
123 qemu_fdt_setprop_cells(fdt
, ser
, "reg", offset
, 0x100);
124 qemu_fdt_setprop_cell(fdt
, ser
, "cell-index", idx
);
125 qemu_fdt_setprop_cell(fdt
, ser
, "clock-frequency", PLATFORM_CLK_FREQ_HZ
);
126 qemu_fdt_setprop_cells(fdt
, ser
, "interrupts", 42, 2);
127 qemu_fdt_setprop_phandle(fdt
, ser
, "interrupt-parent", mpic
);
128 qemu_fdt_setprop_string(fdt
, "/aliases", alias
, ser
);
132 * "linux,stdout-path" and "stdout" properties are deprecated by linux
133 * kernel. New platforms should only use the "stdout-path" property. Set
134 * the new property and continue using older property to remain
135 * compatible with the existing firmware.
137 qemu_fdt_setprop_string(fdt
, "/chosen", "linux,stdout-path", ser
);
138 qemu_fdt_setprop_string(fdt
, "/chosen", "stdout-path", ser
);
143 static void create_dt_mpc8xxx_gpio(void *fdt
, const char *soc
, const char *mpic
)
145 hwaddr mmio0
= MPC8XXX_GPIO_OFFSET
;
146 int irq0
= MPC8XXX_GPIO_IRQ
;
147 gchar
*node
= g_strdup_printf("%s/gpio@%"PRIx64
, soc
, mmio0
);
148 gchar
*poweroff
= g_strdup_printf("%s/power-off", soc
);
151 qemu_fdt_add_subnode(fdt
, node
);
152 qemu_fdt_setprop_string(fdt
, node
, "compatible", "fsl,qoriq-gpio");
153 qemu_fdt_setprop_cells(fdt
, node
, "reg", mmio0
, 0x1000);
154 qemu_fdt_setprop_cells(fdt
, node
, "interrupts", irq0
, 0x2);
155 qemu_fdt_setprop_phandle(fdt
, node
, "interrupt-parent", mpic
);
156 qemu_fdt_setprop_cells(fdt
, node
, "#gpio-cells", 2);
157 qemu_fdt_setprop(fdt
, node
, "gpio-controller", NULL
, 0);
158 gpio_ph
= qemu_fdt_alloc_phandle(fdt
);
159 qemu_fdt_setprop_cell(fdt
, node
, "phandle", gpio_ph
);
160 qemu_fdt_setprop_cell(fdt
, node
, "linux,phandle", gpio_ph
);
163 qemu_fdt_add_subnode(fdt
, poweroff
);
164 qemu_fdt_setprop_string(fdt
, poweroff
, "compatible", "gpio-poweroff");
165 qemu_fdt_setprop_cells(fdt
, poweroff
, "gpios", gpio_ph
, 0, 0);
171 static void dt_rtc_create(void *fdt
, const char *i2c
, const char *alias
)
173 int offset
= RTC_REGS_OFFSET
;
175 gchar
*rtc
= g_strdup_printf("%s/rtc@%"PRIx32
, i2c
, offset
);
176 qemu_fdt_add_subnode(fdt
, rtc
);
177 qemu_fdt_setprop_string(fdt
, rtc
, "compatible", "pericom,pt7c4338");
178 qemu_fdt_setprop_cells(fdt
, rtc
, "reg", offset
);
179 qemu_fdt_setprop_string(fdt
, "/aliases", alias
, rtc
);
184 static void dt_i2c_create(void *fdt
, const char *soc
, const char *mpic
,
187 hwaddr mmio0
= MPC8544_I2C_REGS_OFFSET
;
188 int irq0
= MPC8544_I2C_IRQ
;
190 gchar
*i2c
= g_strdup_printf("%s/i2c@%"PRIx64
, soc
, mmio0
);
191 qemu_fdt_add_subnode(fdt
, i2c
);
192 qemu_fdt_setprop_string(fdt
, i2c
, "device_type", "i2c");
193 qemu_fdt_setprop_string(fdt
, i2c
, "compatible", "fsl-i2c");
194 qemu_fdt_setprop_cells(fdt
, i2c
, "reg", mmio0
, 0x14);
195 qemu_fdt_setprop_cells(fdt
, i2c
, "cell-index", 0);
196 qemu_fdt_setprop_cells(fdt
, i2c
, "interrupts", irq0
, 0x2);
197 qemu_fdt_setprop_phandle(fdt
, i2c
, "interrupt-parent", mpic
);
198 qemu_fdt_setprop_string(fdt
, "/aliases", alias
, i2c
);
204 typedef struct PlatformDevtreeData
{
209 PlatformBusDevice
*pbus
;
210 } PlatformDevtreeData
;
212 static int create_devtree_etsec(SysBusDevice
*sbdev
, PlatformDevtreeData
*data
)
214 eTSEC
*etsec
= ETSEC_COMMON(sbdev
);
215 PlatformBusDevice
*pbus
= data
->pbus
;
216 hwaddr mmio0
= platform_bus_get_mmio_addr(pbus
, sbdev
, 0);
217 int irq0
= platform_bus_get_irqn(pbus
, sbdev
, 0);
218 int irq1
= platform_bus_get_irqn(pbus
, sbdev
, 1);
219 int irq2
= platform_bus_get_irqn(pbus
, sbdev
, 2);
220 gchar
*node
= g_strdup_printf("/platform/ethernet@%"PRIx64
, mmio0
);
221 gchar
*group
= g_strdup_printf("%s/queue-group", node
);
222 void *fdt
= data
->fdt
;
224 assert((int64_t)mmio0
>= 0);
229 qemu_fdt_add_subnode(fdt
, node
);
230 qemu_fdt_setprop(fdt
, node
, "ranges", NULL
, 0);
231 qemu_fdt_setprop_string(fdt
, node
, "device_type", "network");
232 qemu_fdt_setprop_string(fdt
, node
, "compatible", "fsl,etsec2");
233 qemu_fdt_setprop_string(fdt
, node
, "model", "eTSEC");
234 qemu_fdt_setprop(fdt
, node
, "local-mac-address", etsec
->conf
.macaddr
.a
, 6);
235 qemu_fdt_setprop_cells(fdt
, node
, "fixed-link", 0, 1, 1000, 0, 0);
236 qemu_fdt_setprop_cells(fdt
, node
, "#size-cells", 1);
237 qemu_fdt_setprop_cells(fdt
, node
, "#address-cells", 1);
239 qemu_fdt_add_subnode(fdt
, group
);
240 qemu_fdt_setprop_cells(fdt
, group
, "reg", mmio0
, 0x1000);
241 qemu_fdt_setprop_cells(fdt
, group
, "interrupts",
242 data
->irq_start
+ irq0
, 0x2,
243 data
->irq_start
+ irq1
, 0x2,
244 data
->irq_start
+ irq2
, 0x2);
252 static void sysbus_device_create_devtree(SysBusDevice
*sbdev
, void *opaque
)
254 PlatformDevtreeData
*data
= opaque
;
255 bool matched
= false;
257 if (object_dynamic_cast(OBJECT(sbdev
), TYPE_ETSEC_COMMON
)) {
258 create_devtree_etsec(sbdev
, data
);
263 error_report("Device %s is not supported by this machine yet.",
264 qdev_fw_name(DEVICE(sbdev
)));
269 static void platform_bus_create_devtree(PPCE500MachineState
*pms
,
270 void *fdt
, const char *mpic
)
272 const PPCE500MachineClass
*pmc
= PPCE500_MACHINE_GET_CLASS(pms
);
273 gchar
*node
= g_strdup_printf("/platform@%"PRIx64
, pmc
->platform_bus_base
);
274 const char platcomp
[] = "qemu,platform\0simple-bus";
275 uint64_t addr
= pmc
->platform_bus_base
;
276 uint64_t size
= pmc
->platform_bus_size
;
277 int irq_start
= pmc
->platform_bus_first_irq
;
279 /* Create a /platform node that we can put all devices into */
281 qemu_fdt_add_subnode(fdt
, node
);
282 qemu_fdt_setprop(fdt
, node
, "compatible", platcomp
, sizeof(platcomp
));
284 /* Our platform bus region is less than 32bit big, so 1 cell is enough for
286 qemu_fdt_setprop_cells(fdt
, node
, "#size-cells", 1);
287 qemu_fdt_setprop_cells(fdt
, node
, "#address-cells", 1);
288 qemu_fdt_setprop_cells(fdt
, node
, "ranges", 0, addr
>> 32, addr
, size
);
290 qemu_fdt_setprop_phandle(fdt
, node
, "interrupt-parent", mpic
);
292 /* Create dt nodes for dynamic devices */
293 PlatformDevtreeData data
= {
296 .irq_start
= irq_start
,
298 .pbus
= pms
->pbus_dev
,
301 /* Loop through all dynamic sysbus devices and create nodes for them */
302 foreach_dynamic_sysbus_device(sysbus_device_create_devtree
, &data
);
307 static int ppce500_load_device_tree(PPCE500MachineState
*pms
,
315 MachineState
*machine
= MACHINE(pms
);
316 unsigned int smp_cpus
= machine
->smp
.cpus
;
317 const PPCE500MachineClass
*pmc
= PPCE500_MACHINE_GET_CLASS(pms
);
318 CPUPPCState
*env
= first_cpu
->env_ptr
;
320 uint64_t mem_reg_property
[] = { 0, cpu_to_be64(machine
->ram_size
) };
323 uint8_t hypercall
[16];
324 uint32_t clock_freq
= PLATFORM_CLK_FREQ_HZ
;
325 uint32_t tb_freq
= PLATFORM_CLK_FREQ_HZ
;
327 char compatible_sb
[] = "fsl,mpc8544-immr\0simple-bus";
335 uint32_t *pci_map
= NULL
;
337 uint32_t pci_ranges
[14] =
339 0x2000000, 0x0, pmc
->pci_mmio_bus_base
,
340 pmc
->pci_mmio_base
>> 32, pmc
->pci_mmio_base
,
344 pmc
->pci_pio_base
>> 32, pmc
->pci_pio_base
,
347 const char *dtb_file
= machine
->dtb
;
348 const char *toplevel_compat
= machine
->dt_compatible
;
352 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, dtb_file
);
357 fdt
= load_device_tree(filename
, &fdt_size
);
365 fdt
= create_device_tree(&fdt_size
);
370 /* Manipulate device tree in memory. */
371 qemu_fdt_setprop_cell(fdt
, "/", "#address-cells", 2);
372 qemu_fdt_setprop_cell(fdt
, "/", "#size-cells", 2);
374 qemu_fdt_add_subnode(fdt
, "/memory");
375 qemu_fdt_setprop_string(fdt
, "/memory", "device_type", "memory");
376 qemu_fdt_setprop(fdt
, "/memory", "reg", mem_reg_property
,
377 sizeof(mem_reg_property
));
379 qemu_fdt_add_subnode(fdt
, "/chosen");
381 ret
= qemu_fdt_setprop_cell(fdt
, "/chosen", "linux,initrd-start",
384 fprintf(stderr
, "couldn't set /chosen/linux,initrd-start\n");
387 ret
= qemu_fdt_setprop_cell(fdt
, "/chosen", "linux,initrd-end",
388 (initrd_base
+ initrd_size
));
390 fprintf(stderr
, "couldn't set /chosen/linux,initrd-end\n");
395 if (kernel_base
!= -1ULL) {
396 qemu_fdt_setprop_cells(fdt
, "/chosen", "qemu,boot-kernel",
397 kernel_base
>> 32, kernel_base
,
398 kernel_size
>> 32, kernel_size
);
401 ret
= qemu_fdt_setprop_string(fdt
, "/chosen", "bootargs",
402 machine
->kernel_cmdline
);
404 fprintf(stderr
, "couldn't set /chosen/bootargs\n");
407 /* Read out host's frequencies */
408 clock_freq
= kvmppc_get_clockfreq();
409 tb_freq
= kvmppc_get_tbfreq();
411 /* indicate KVM hypercall interface */
412 qemu_fdt_add_subnode(fdt
, "/hypervisor");
413 qemu_fdt_setprop_string(fdt
, "/hypervisor", "compatible",
415 kvmppc_get_hypercall(env
, hypercall
, sizeof(hypercall
));
416 qemu_fdt_setprop(fdt
, "/hypervisor", "hcall-instructions",
417 hypercall
, sizeof(hypercall
));
418 /* if KVM supports the idle hcall, set property indicating this */
419 if (kvmppc_get_hasidle(env
)) {
420 qemu_fdt_setprop(fdt
, "/hypervisor", "has-idle", NULL
, 0);
424 /* Create CPU nodes */
425 qemu_fdt_add_subnode(fdt
, "/cpus");
426 qemu_fdt_setprop_cell(fdt
, "/cpus", "#address-cells", 1);
427 qemu_fdt_setprop_cell(fdt
, "/cpus", "#size-cells", 0);
429 /* We need to generate the cpu nodes in reverse order, so Linux can pick
430 the first node as boot node and be happy */
431 for (i
= smp_cpus
- 1; i
>= 0; i
--) {
434 uint64_t cpu_release_addr
= pmc
->spin_base
+ (i
* 0x20);
436 cpu
= qemu_get_cpu(i
);
442 cpu_name
= g_strdup_printf("/cpus/PowerPC,8544@%x", i
);
443 qemu_fdt_add_subnode(fdt
, cpu_name
);
444 qemu_fdt_setprop_cell(fdt
, cpu_name
, "clock-frequency", clock_freq
);
445 qemu_fdt_setprop_cell(fdt
, cpu_name
, "timebase-frequency", tb_freq
);
446 qemu_fdt_setprop_string(fdt
, cpu_name
, "device_type", "cpu");
447 qemu_fdt_setprop_cell(fdt
, cpu_name
, "reg", i
);
448 qemu_fdt_setprop_cell(fdt
, cpu_name
, "d-cache-line-size",
449 env
->dcache_line_size
);
450 qemu_fdt_setprop_cell(fdt
, cpu_name
, "i-cache-line-size",
451 env
->icache_line_size
);
452 qemu_fdt_setprop_cell(fdt
, cpu_name
, "d-cache-size", 0x8000);
453 qemu_fdt_setprop_cell(fdt
, cpu_name
, "i-cache-size", 0x8000);
454 qemu_fdt_setprop_cell(fdt
, cpu_name
, "bus-frequency", 0);
455 if (cpu
->cpu_index
) {
456 qemu_fdt_setprop_string(fdt
, cpu_name
, "status", "disabled");
457 qemu_fdt_setprop_string(fdt
, cpu_name
, "enable-method",
459 qemu_fdt_setprop_u64(fdt
, cpu_name
, "cpu-release-addr",
462 qemu_fdt_setprop_string(fdt
, cpu_name
, "status", "okay");
467 qemu_fdt_add_subnode(fdt
, "/aliases");
468 /* XXX These should go into their respective devices' code */
469 soc
= g_strdup_printf("/soc@%"PRIx64
, pmc
->ccsrbar_base
);
470 qemu_fdt_add_subnode(fdt
, soc
);
471 qemu_fdt_setprop_string(fdt
, soc
, "device_type", "soc");
472 qemu_fdt_setprop(fdt
, soc
, "compatible", compatible_sb
,
473 sizeof(compatible_sb
));
474 qemu_fdt_setprop_cell(fdt
, soc
, "#address-cells", 1);
475 qemu_fdt_setprop_cell(fdt
, soc
, "#size-cells", 1);
476 qemu_fdt_setprop_cells(fdt
, soc
, "ranges", 0x0,
477 pmc
->ccsrbar_base
>> 32, pmc
->ccsrbar_base
,
478 MPC8544_CCSRBAR_SIZE
);
479 /* XXX should contain a reasonable value */
480 qemu_fdt_setprop_cell(fdt
, soc
, "bus-frequency", 0);
482 mpic
= g_strdup_printf("%s/pic@%llx", soc
, MPC8544_MPIC_REGS_OFFSET
);
483 qemu_fdt_add_subnode(fdt
, mpic
);
484 qemu_fdt_setprop_string(fdt
, mpic
, "device_type", "open-pic");
485 qemu_fdt_setprop_string(fdt
, mpic
, "compatible", "fsl,mpic");
486 qemu_fdt_setprop_cells(fdt
, mpic
, "reg", MPC8544_MPIC_REGS_OFFSET
,
488 qemu_fdt_setprop_cell(fdt
, mpic
, "#address-cells", 0);
489 qemu_fdt_setprop_cell(fdt
, mpic
, "#interrupt-cells", 2);
490 mpic_ph
= qemu_fdt_alloc_phandle(fdt
);
491 qemu_fdt_setprop_cell(fdt
, mpic
, "phandle", mpic_ph
);
492 qemu_fdt_setprop_cell(fdt
, mpic
, "linux,phandle", mpic_ph
);
493 qemu_fdt_setprop(fdt
, mpic
, "interrupt-controller", NULL
, 0);
496 * We have to generate ser1 first, because Linux takes the first
497 * device it finds in the dt as serial output device. And we generate
498 * devices in reverse order to the dt.
501 dt_serial_create(fdt
, MPC8544_SERIAL1_REGS_OFFSET
,
502 soc
, mpic
, "serial1", 1, false);
506 dt_serial_create(fdt
, MPC8544_SERIAL0_REGS_OFFSET
,
507 soc
, mpic
, "serial0", 0, true);
511 dt_i2c_create(fdt
, soc
, mpic
, "i2c");
513 dt_rtc_create(fdt
, "i2c", "rtc");
516 gutil
= g_strdup_printf("%s/global-utilities@%llx", soc
,
517 MPC8544_UTIL_OFFSET
);
518 qemu_fdt_add_subnode(fdt
, gutil
);
519 qemu_fdt_setprop_string(fdt
, gutil
, "compatible", "fsl,mpc8544-guts");
520 qemu_fdt_setprop_cells(fdt
, gutil
, "reg", MPC8544_UTIL_OFFSET
, 0x1000);
521 qemu_fdt_setprop(fdt
, gutil
, "fsl,has-rstcr", NULL
, 0);
524 msi
= g_strdup_printf("/%s/msi@%llx", soc
, MPC8544_MSI_REGS_OFFSET
);
525 qemu_fdt_add_subnode(fdt
, msi
);
526 qemu_fdt_setprop_string(fdt
, msi
, "compatible", "fsl,mpic-msi");
527 qemu_fdt_setprop_cells(fdt
, msi
, "reg", MPC8544_MSI_REGS_OFFSET
, 0x200);
528 msi_ph
= qemu_fdt_alloc_phandle(fdt
);
529 qemu_fdt_setprop_cells(fdt
, msi
, "msi-available-ranges", 0x0, 0x100);
530 qemu_fdt_setprop_phandle(fdt
, msi
, "interrupt-parent", mpic
);
531 qemu_fdt_setprop_cells(fdt
, msi
, "interrupts",
540 qemu_fdt_setprop_cell(fdt
, msi
, "phandle", msi_ph
);
541 qemu_fdt_setprop_cell(fdt
, msi
, "linux,phandle", msi_ph
);
544 pci
= g_strdup_printf("/pci@%llx",
545 pmc
->ccsrbar_base
+ MPC8544_PCI_REGS_OFFSET
);
546 qemu_fdt_add_subnode(fdt
, pci
);
547 qemu_fdt_setprop_cell(fdt
, pci
, "cell-index", 0);
548 qemu_fdt_setprop_string(fdt
, pci
, "compatible", "fsl,mpc8540-pci");
549 qemu_fdt_setprop_string(fdt
, pci
, "device_type", "pci");
550 qemu_fdt_setprop_cells(fdt
, pci
, "interrupt-map-mask", 0xf800, 0x0,
552 pci_map
= pci_map_create(fdt
, qemu_fdt_get_phandle(fdt
, mpic
),
553 pmc
->pci_first_slot
, pmc
->pci_nr_slots
,
555 qemu_fdt_setprop(fdt
, pci
, "interrupt-map", pci_map
, len
);
556 qemu_fdt_setprop_phandle(fdt
, pci
, "interrupt-parent", mpic
);
557 qemu_fdt_setprop_cells(fdt
, pci
, "interrupts", 24, 2);
558 qemu_fdt_setprop_cells(fdt
, pci
, "bus-range", 0, 255);
559 for (i
= 0; i
< 14; i
++) {
560 pci_ranges
[i
] = cpu_to_be32(pci_ranges
[i
]);
562 qemu_fdt_setprop_cell(fdt
, pci
, "fsl,msi", msi_ph
);
563 qemu_fdt_setprop(fdt
, pci
, "ranges", pci_ranges
, sizeof(pci_ranges
));
564 qemu_fdt_setprop_cells(fdt
, pci
, "reg",
565 (pmc
->ccsrbar_base
+ MPC8544_PCI_REGS_OFFSET
) >> 32,
566 (pmc
->ccsrbar_base
+ MPC8544_PCI_REGS_OFFSET
),
568 qemu_fdt_setprop_cell(fdt
, pci
, "clock-frequency", 66666666);
569 qemu_fdt_setprop_cell(fdt
, pci
, "#interrupt-cells", 1);
570 qemu_fdt_setprop_cell(fdt
, pci
, "#size-cells", 2);
571 qemu_fdt_setprop_cell(fdt
, pci
, "#address-cells", 3);
572 qemu_fdt_setprop_string(fdt
, "/aliases", "pci0", pci
);
575 if (pmc
->has_mpc8xxx_gpio
) {
576 create_dt_mpc8xxx_gpio(fdt
, soc
, mpic
);
581 platform_bus_create_devtree(pms
, fdt
, mpic
);
585 pmc
->fixup_devtree(fdt
);
587 if (toplevel_compat
) {
588 qemu_fdt_setprop(fdt
, "/", "compatible", toplevel_compat
,
589 strlen(toplevel_compat
) + 1);
594 qemu_fdt_dumpdtb(fdt
, fdt_size
);
595 cpu_physical_memory_write(addr
, fdt
, fdt_size
);
606 typedef struct DeviceTreeParams
{
607 PPCE500MachineState
*machine
;
616 static void ppce500_reset_device_tree(void *opaque
)
618 DeviceTreeParams
*p
= opaque
;
619 ppce500_load_device_tree(p
->machine
, p
->addr
, p
->initrd_base
,
620 p
->initrd_size
, p
->kernel_base
, p
->kernel_size
,
624 static void ppce500_init_notify(Notifier
*notifier
, void *data
)
626 DeviceTreeParams
*p
= container_of(notifier
, DeviceTreeParams
, notifier
);
627 ppce500_reset_device_tree(p
);
630 static int ppce500_prep_device_tree(PPCE500MachineState
*machine
,
637 DeviceTreeParams
*p
= g_new(DeviceTreeParams
, 1);
638 p
->machine
= machine
;
640 p
->initrd_base
= initrd_base
;
641 p
->initrd_size
= initrd_size
;
642 p
->kernel_base
= kernel_base
;
643 p
->kernel_size
= kernel_size
;
645 qemu_register_reset(ppce500_reset_device_tree
, p
);
646 p
->notifier
.notify
= ppce500_init_notify
;
647 qemu_add_machine_init_done_notifier(&p
->notifier
);
649 /* Issue the device tree loader once, so that we get the size of the blob */
650 return ppce500_load_device_tree(machine
, addr
, initrd_base
, initrd_size
,
651 kernel_base
, kernel_size
, true);
654 /* Create -kernel TLB entries for BookE. */
655 hwaddr
booke206_page_size_to_tlb(uint64_t size
)
657 return 63 - clz64(size
/ KiB
);
660 static int booke206_initial_map_tsize(CPUPPCState
*env
)
662 struct boot_info
*bi
= env
->load_info
;
666 /* Our initial TLB entry needs to cover everything from 0 to
667 the device tree top */
668 dt_end
= bi
->dt_base
+ bi
->dt_size
;
669 ps
= booke206_page_size_to_tlb(dt_end
) + 1;
671 /* e500v2 can only do even TLB size bits */
677 static uint64_t mmubooke_initial_mapsize(CPUPPCState
*env
)
681 tsize
= booke206_initial_map_tsize(env
);
682 return (1ULL << 10 << tsize
);
685 static void mmubooke_create_initial_mapping(CPUPPCState
*env
)
687 ppcmas_tlb_t
*tlb
= booke206_get_tlbm(env
, 1, 0, 0);
691 ps
= booke206_initial_map_tsize(env
);
692 size
= (ps
<< MAS1_TSIZE_SHIFT
);
693 tlb
->mas1
= MAS1_VALID
| size
;
696 tlb
->mas7_3
|= MAS3_UR
| MAS3_UW
| MAS3_UX
| MAS3_SR
| MAS3_SW
| MAS3_SX
;
698 env
->tlb_dirty
= true;
701 static void ppce500_cpu_reset_sec(void *opaque
)
703 PowerPCCPU
*cpu
= opaque
;
704 CPUState
*cs
= CPU(cpu
);
708 cs
->exception_index
= EXCP_HLT
;
711 static void ppce500_cpu_reset(void *opaque
)
713 PowerPCCPU
*cpu
= opaque
;
714 CPUState
*cs
= CPU(cpu
);
715 CPUPPCState
*env
= &cpu
->env
;
716 struct boot_info
*bi
= env
->load_info
;
720 /* Set initial guest state. */
722 env
->gpr
[1] = (16 * MiB
) - 8;
723 env
->gpr
[3] = bi
->dt_base
;
726 env
->gpr
[6] = EPAPR_MAGIC
;
727 env
->gpr
[7] = mmubooke_initial_mapsize(env
);
730 env
->nip
= bi
->entry
;
731 mmubooke_create_initial_mapping(env
);
734 static DeviceState
*ppce500_init_mpic_qemu(PPCE500MachineState
*pms
,
740 MachineState
*machine
= MACHINE(pms
);
741 unsigned int smp_cpus
= machine
->smp
.cpus
;
742 const PPCE500MachineClass
*pmc
= PPCE500_MACHINE_GET_CLASS(pms
);
744 dev
= qdev_new(TYPE_OPENPIC
);
745 object_property_add_child(OBJECT(machine
), "pic", OBJECT(dev
));
746 qdev_prop_set_uint32(dev
, "model", pmc
->mpic_version
);
747 qdev_prop_set_uint32(dev
, "nb_cpus", smp_cpus
);
749 s
= SYS_BUS_DEVICE(dev
);
750 sysbus_realize_and_unref(s
, &error_fatal
);
753 for (i
= 0; i
< smp_cpus
; i
++) {
754 for (j
= 0; j
< OPENPIC_OUTPUT_NB
; j
++) {
755 sysbus_connect_irq(s
, k
++, irqs
[i
].irq
[j
]);
762 static DeviceState
*ppce500_init_mpic_kvm(const PPCE500MachineClass
*pmc
,
763 IrqLines
*irqs
, Error
**errp
)
768 dev
= qdev_new(TYPE_KVM_OPENPIC
);
769 qdev_prop_set_uint32(dev
, "model", pmc
->mpic_version
);
771 if (!sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), errp
)) {
772 object_unparent(OBJECT(dev
));
777 if (kvm_openpic_connect_vcpu(dev
, cs
)) {
778 fprintf(stderr
, "%s: failed to connect vcpu to irqchip\n",
787 static DeviceState
*ppce500_init_mpic(PPCE500MachineState
*pms
,
791 const PPCE500MachineClass
*pmc
= PPCE500_MACHINE_GET_CLASS(pms
);
792 DeviceState
*dev
= NULL
;
798 if (kvm_kernel_irqchip_allowed()) {
799 dev
= ppce500_init_mpic_kvm(pmc
, irqs
, &err
);
801 if (kvm_kernel_irqchip_required() && !dev
) {
802 error_reportf_err(err
,
803 "kernel_irqchip requested but unavailable: ");
809 dev
= ppce500_init_mpic_qemu(pms
, irqs
);
812 s
= SYS_BUS_DEVICE(dev
);
813 memory_region_add_subregion(ccsr
, MPC8544_MPIC_REGS_OFFSET
,
819 static void ppce500_power_off(void *opaque
, int line
, int on
)
822 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN
);
826 void ppce500_init(MachineState
*machine
)
828 MemoryRegion
*address_space_mem
= get_system_memory();
829 PPCE500MachineState
*pms
= PPCE500_MACHINE(machine
);
830 const PPCE500MachineClass
*pmc
= PPCE500_MACHINE_GET_CLASS(machine
);
832 CPUPPCState
*env
= NULL
;
834 hwaddr kernel_base
= -1LL;
837 hwaddr initrd_base
= 0;
841 const char *payload_name
;
842 bool kernel_as_payload
;
843 hwaddr bios_entry
= 0;
844 target_long payload_size
;
845 struct boot_info
*boot_info
;
848 unsigned int smp_cpus
= machine
->smp
.cpus
;
849 /* irq num for pin INTA, INTB, INTC and INTD is 1, 2, 3 and
851 unsigned int pci_irq_nrs
[PCI_NUM_PINS
] = {1, 2, 3, 4};
853 DeviceState
*dev
, *mpicdev
;
854 CPUPPCState
*firstenv
= NULL
;
855 MemoryRegion
*ccsr_addr_space
;
857 PPCE500CCSRState
*ccsr
;
860 irqs
= g_new0(IrqLines
, smp_cpus
);
861 for (i
= 0; i
< smp_cpus
; i
++) {
865 cpu
= POWERPC_CPU(object_new(machine
->cpu_type
));
869 if (env
->mmu_model
!= POWERPC_MMU_BOOKE206
) {
870 error_report("MMU model %i not supported by this machine",
876 * Secondary CPU starts in halted state for now. Needs to change
877 * when implementing non-kernel boot.
879 object_property_set_bool(OBJECT(cs
), "start-powered-off", i
!= 0,
881 qdev_realize_and_unref(DEVICE(cs
), NULL
, &error_fatal
);
887 irqs
[i
].irq
[OPENPIC_OUTPUT_INT
] =
888 qdev_get_gpio_in(DEVICE(cpu
), PPCE500_INPUT_INT
);
889 irqs
[i
].irq
[OPENPIC_OUTPUT_CINT
] =
890 qdev_get_gpio_in(DEVICE(cpu
), PPCE500_INPUT_CINT
);
891 env
->spr_cb
[SPR_BOOKE_PIR
].default_value
= cs
->cpu_index
= i
;
892 env
->mpic_iack
= pmc
->ccsrbar_base
+ MPC8544_MPIC_REGS_OFFSET
+ 0xa0;
894 ppc_booke_timers_init(cpu
, PLATFORM_CLK_FREQ_HZ
, PPC_TIMER_E500
);
896 /* Register reset handler */
899 struct boot_info
*boot_info
;
900 boot_info
= g_new0(struct boot_info
, 1);
901 qemu_register_reset(ppce500_cpu_reset
, cpu
);
902 env
->load_info
= boot_info
;
905 qemu_register_reset(ppce500_cpu_reset_sec
, cpu
);
911 if (!QEMU_IS_ALIGNED(machine
->ram_size
, RAM_SIZES_ALIGN
)) {
912 error_report("RAM size must be multiple of %" PRIu64
, RAM_SIZES_ALIGN
);
916 /* Register Memory */
917 memory_region_add_subregion(address_space_mem
, 0, machine
->ram
);
919 dev
= qdev_new("e500-ccsr");
920 object_property_add_child(qdev_get_machine(), "e500-ccsr",
922 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
924 ccsr_addr_space
= &ccsr
->ccsr_space
;
925 memory_region_add_subregion(address_space_mem
, pmc
->ccsrbar_base
,
928 mpicdev
= ppce500_init_mpic(pms
, ccsr_addr_space
, irqs
);
933 serial_mm_init(ccsr_addr_space
, MPC8544_SERIAL0_REGS_OFFSET
,
934 0, qdev_get_gpio_in(mpicdev
, 42), 399193,
935 serial_hd(0), DEVICE_BIG_ENDIAN
);
939 serial_mm_init(ccsr_addr_space
, MPC8544_SERIAL1_REGS_OFFSET
,
940 0, qdev_get_gpio_in(mpicdev
, 42), 399193,
941 serial_hd(1), DEVICE_BIG_ENDIAN
);
944 dev
= qdev_new("mpc-i2c");
945 s
= SYS_BUS_DEVICE(dev
);
946 sysbus_realize_and_unref(s
, &error_fatal
);
947 sysbus_connect_irq(s
, 0, qdev_get_gpio_in(mpicdev
, MPC8544_I2C_IRQ
));
948 memory_region_add_subregion(ccsr_addr_space
, MPC8544_I2C_REGS_OFFSET
,
949 sysbus_mmio_get_region(s
, 0));
950 i2c
= (I2CBus
*)qdev_get_child_bus(dev
, "i2c");
951 i2c_slave_create_simple(i2c
, "ds1338", RTC_REGS_OFFSET
);
954 /* General Utility device */
955 dev
= qdev_new("mpc8544-guts");
956 s
= SYS_BUS_DEVICE(dev
);
957 sysbus_realize_and_unref(s
, &error_fatal
);
958 memory_region_add_subregion(ccsr_addr_space
, MPC8544_UTIL_OFFSET
,
959 sysbus_mmio_get_region(s
, 0));
962 dev
= qdev_new("e500-pcihost");
963 object_property_add_child(qdev_get_machine(), "pci-host", OBJECT(dev
));
964 qdev_prop_set_uint32(dev
, "first_slot", pmc
->pci_first_slot
);
965 qdev_prop_set_uint32(dev
, "first_pin_irq", pci_irq_nrs
[0]);
966 s
= SYS_BUS_DEVICE(dev
);
967 sysbus_realize_and_unref(s
, &error_fatal
);
968 for (i
= 0; i
< PCI_NUM_PINS
; i
++) {
969 sysbus_connect_irq(s
, i
, qdev_get_gpio_in(mpicdev
, pci_irq_nrs
[i
]));
972 memory_region_add_subregion(ccsr_addr_space
, MPC8544_PCI_REGS_OFFSET
,
973 sysbus_mmio_get_region(s
, 0));
975 pci_bus
= (PCIBus
*)qdev_get_child_bus(dev
, "pci.0");
977 printf("couldn't create PCI controller!\n");
980 /* Register network interfaces. */
981 for (i
= 0; i
< nb_nics
; i
++) {
982 pci_nic_init_nofail(&nd_table
[i
], pci_bus
, "virtio-net-pci", NULL
);
986 /* Register spinning region */
987 sysbus_create_simple("e500-spin", pmc
->spin_base
, NULL
);
989 if (pmc
->has_mpc8xxx_gpio
) {
990 qemu_irq poweroff_irq
;
992 dev
= qdev_new("mpc8xxx_gpio");
993 s
= SYS_BUS_DEVICE(dev
);
994 sysbus_realize_and_unref(s
, &error_fatal
);
995 sysbus_connect_irq(s
, 0, qdev_get_gpio_in(mpicdev
, MPC8XXX_GPIO_IRQ
));
996 memory_region_add_subregion(ccsr_addr_space
, MPC8XXX_GPIO_OFFSET
,
997 sysbus_mmio_get_region(s
, 0));
999 /* Power Off GPIO at Pin 0 */
1000 poweroff_irq
= qemu_allocate_irq(ppce500_power_off
, NULL
, 0);
1001 qdev_connect_gpio_out(dev
, 0, poweroff_irq
);
1004 /* Platform Bus Device */
1005 if (pmc
->has_platform_bus
) {
1006 dev
= qdev_new(TYPE_PLATFORM_BUS_DEVICE
);
1007 dev
->id
= g_strdup(TYPE_PLATFORM_BUS_DEVICE
);
1008 qdev_prop_set_uint32(dev
, "num_irqs", pmc
->platform_bus_num_irqs
);
1009 qdev_prop_set_uint32(dev
, "mmio_size", pmc
->platform_bus_size
);
1010 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
1011 pms
->pbus_dev
= PLATFORM_BUS_DEVICE(dev
);
1013 s
= SYS_BUS_DEVICE(pms
->pbus_dev
);
1014 for (i
= 0; i
< pmc
->platform_bus_num_irqs
; i
++) {
1015 int irqn
= pmc
->platform_bus_first_irq
+ i
;
1016 sysbus_connect_irq(s
, i
, qdev_get_gpio_in(mpicdev
, irqn
));
1019 memory_region_add_subregion(address_space_mem
,
1020 pmc
->platform_bus_base
,
1021 sysbus_mmio_get_region(s
, 0));
1025 * Smart firmware defaults ahead!
1027 * We follow the following table to select which payload we execute.
1029 * -kernel | -bios | payload
1030 * ---------+-------+---------
1036 * This ensures backwards compatibility with how we used to expose
1037 * -kernel to users but allows them to run through u-boot as well.
1039 kernel_as_payload
= false;
1040 if (machine
->firmware
== NULL
) {
1041 if (machine
->kernel_filename
) {
1042 payload_name
= machine
->kernel_filename
;
1043 kernel_as_payload
= true;
1045 payload_name
= "u-boot.e500";
1048 payload_name
= machine
->firmware
;
1051 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, payload_name
);
1053 error_report("could not find firmware/kernel file '%s'", payload_name
);
1057 payload_size
= load_elf(filename
, NULL
, NULL
, NULL
,
1058 &bios_entry
, &loadaddr
, NULL
, NULL
,
1059 1, PPC_ELF_MACHINE
, 0, 0);
1060 if (payload_size
< 0) {
1062 * Hrm. No ELF image? Try a uImage, maybe someone is giving us an
1063 * ePAPR compliant kernel
1065 loadaddr
= LOAD_UIMAGE_LOADADDR_INVALID
;
1066 payload_size
= load_uimage(filename
, &bios_entry
, &loadaddr
, NULL
,
1068 if (payload_size
< 0) {
1069 error_report("could not load firmware '%s'", filename
);
1076 if (kernel_as_payload
) {
1077 kernel_base
= loadaddr
;
1078 kernel_size
= payload_size
;
1081 cur_base
= loadaddr
+ payload_size
;
1082 if (cur_base
< 32 * MiB
) {
1083 /* u-boot occupies memory up to 32MB, so load blobs above */
1084 cur_base
= 32 * MiB
;
1087 /* Load bare kernel only if no bios/u-boot has been provided */
1088 if (machine
->kernel_filename
&& !kernel_as_payload
) {
1089 kernel_base
= cur_base
;
1090 kernel_size
= load_image_targphys(machine
->kernel_filename
,
1092 machine
->ram_size
- cur_base
);
1093 if (kernel_size
< 0) {
1094 error_report("could not load kernel '%s'",
1095 machine
->kernel_filename
);
1099 cur_base
+= kernel_size
;
1103 if (machine
->initrd_filename
) {
1104 initrd_base
= (cur_base
+ INITRD_LOAD_PAD
) & ~INITRD_PAD_MASK
;
1105 initrd_size
= load_image_targphys(machine
->initrd_filename
, initrd_base
,
1106 machine
->ram_size
- initrd_base
);
1108 if (initrd_size
< 0) {
1109 error_report("could not load initial ram disk '%s'",
1110 machine
->initrd_filename
);
1114 cur_base
= initrd_base
+ initrd_size
;
1118 * Reserve space for dtb behind the kernel image because Linux has a bug
1119 * where it can only handle the dtb if it's within the first 64MB of where
1120 * <kernel> starts. dtb cannot not reach initrd_base because INITRD_LOAD_PAD
1121 * ensures enough space between kernel and initrd.
1123 dt_base
= (loadaddr
+ payload_size
+ DTC_LOAD_PAD
) & ~DTC_PAD_MASK
;
1124 if (dt_base
+ DTB_MAX_SIZE
> machine
->ram_size
) {
1125 error_report("not enough memory for device tree");
1129 dt_size
= ppce500_prep_device_tree(pms
, dt_base
,
1130 initrd_base
, initrd_size
,
1131 kernel_base
, kernel_size
);
1133 error_report("couldn't load device tree");
1136 assert(dt_size
< DTB_MAX_SIZE
);
1138 boot_info
= env
->load_info
;
1139 boot_info
->entry
= bios_entry
;
1140 boot_info
->dt_base
= dt_base
;
1141 boot_info
->dt_size
= dt_size
;
1144 static void e500_ccsr_initfn(Object
*obj
)
1146 PPCE500CCSRState
*ccsr
= CCSR(obj
);
1147 memory_region_init(&ccsr
->ccsr_space
, obj
, "e500-ccsr",
1148 MPC8544_CCSRBAR_SIZE
);
1151 static const TypeInfo e500_ccsr_info
= {
1153 .parent
= TYPE_SYS_BUS_DEVICE
,
1154 .instance_size
= sizeof(PPCE500CCSRState
),
1155 .instance_init
= e500_ccsr_initfn
,
1158 static const TypeInfo ppce500_info
= {
1159 .name
= TYPE_PPCE500_MACHINE
,
1160 .parent
= TYPE_MACHINE
,
1162 .instance_size
= sizeof(PPCE500MachineState
),
1163 .class_size
= sizeof(PPCE500MachineClass
),
1166 static void e500_register_types(void)
1168 type_register_static(&e500_ccsr_info
);
1169 type_register_static(&ppce500_info
);
1172 type_init(e500_register_types
)