2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
4 * Copyright (c) 2004-2007 Fabrice Bellard
5 * Copyright (c) 2007 Jocelyn Mayer
6 * Copyright (c) 2010 David Gibson, IBM Corporation.
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
27 #include "qemu/osdep.h"
28 #include "qemu-common.h"
29 #include "qapi/error.h"
30 #include "qapi/visitor.h"
31 #include "sysemu/sysemu.h"
32 #include "sysemu/hostmem.h"
33 #include "sysemu/numa.h"
34 #include "sysemu/qtest.h"
35 #include "sysemu/reset.h"
36 #include "sysemu/runstate.h"
38 #include "hw/fw-path-provider.h"
41 #include "sysemu/device_tree.h"
42 #include "sysemu/cpus.h"
43 #include "sysemu/hw_accel.h"
45 #include "migration/misc.h"
46 #include "migration/qemu-file-types.h"
47 #include "migration/global_state.h"
48 #include "migration/register.h"
49 #include "mmu-hash64.h"
50 #include "mmu-book3s-v3.h"
51 #include "cpu-models.h"
52 #include "hw/core/cpu.h"
54 #include "hw/boards.h"
55 #include "hw/ppc/ppc.h"
56 #include "hw/loader.h"
58 #include "hw/ppc/fdt.h"
59 #include "hw/ppc/spapr.h"
60 #include "hw/ppc/spapr_vio.h"
61 #include "hw/qdev-properties.h"
62 #include "hw/pci-host/spapr.h"
63 #include "hw/pci/msi.h"
65 #include "hw/pci/pci.h"
66 #include "hw/scsi/scsi.h"
67 #include "hw/virtio/virtio-scsi.h"
68 #include "hw/virtio/vhost-scsi-common.h"
70 #include "exec/address-spaces.h"
71 #include "exec/ram_addr.h"
73 #include "qemu/config-file.h"
74 #include "qemu/error-report.h"
77 #include "hw/intc/intc.h"
79 #include "qemu/cutils.h"
80 #include "hw/ppc/spapr_cpu_core.h"
81 #include "hw/mem/memory-device.h"
82 #include "hw/ppc/spapr_tpm_proxy.h"
84 #include "monitor/monitor.h"
88 /* SLOF memory layout:
90 * SLOF raw image loaded at 0, copies its romfs right below the flat
91 * device-tree, then position SLOF itself 31M below that
93 * So we set FW_OVERHEAD to 40MB which should account for all of that
96 * We load our kernel at 4M, leaving space for SLOF initial image
98 #define FDT_MAX_SIZE 0x100000
99 #define RTAS_MAX_SIZE 0x10000
100 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */
101 #define FW_MAX_SIZE 0x400000
102 #define FW_FILE_NAME "slof.bin"
103 #define FW_OVERHEAD 0x2800000
104 #define KERNEL_LOAD_ADDR FW_MAX_SIZE
106 #define MIN_RMA_SLOF 128UL
108 #define PHANDLE_INTC 0x00001111
110 /* These two functions implement the VCPU id numbering: one to compute them
111 * all and one to identify thread 0 of a VCORE. Any change to the first one
112 * is likely to have an impact on the second one, so let's keep them close.
114 static int spapr_vcpu_id(SpaprMachineState
*spapr
, int cpu_index
)
116 MachineState
*ms
= MACHINE(spapr
);
117 unsigned int smp_threads
= ms
->smp
.threads
;
121 (cpu_index
/ smp_threads
) * spapr
->vsmt
+ cpu_index
% smp_threads
;
123 static bool spapr_is_thread0_in_vcore(SpaprMachineState
*spapr
,
127 return spapr_get_vcpu_id(cpu
) % spapr
->vsmt
== 0;
130 static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque
)
132 /* Dummy entries correspond to unused ICPState objects in older QEMUs,
133 * and newer QEMUs don't even have them. In both cases, we don't want
134 * to send anything on the wire.
139 static const VMStateDescription pre_2_10_vmstate_dummy_icp
= {
140 .name
= "icp/server",
142 .minimum_version_id
= 1,
143 .needed
= pre_2_10_vmstate_dummy_icp_needed
,
144 .fields
= (VMStateField
[]) {
145 VMSTATE_UNUSED(4), /* uint32_t xirr */
146 VMSTATE_UNUSED(1), /* uint8_t pending_priority */
147 VMSTATE_UNUSED(1), /* uint8_t mfrr */
148 VMSTATE_END_OF_LIST()
152 static void pre_2_10_vmstate_register_dummy_icp(int i
)
154 vmstate_register(NULL
, i
, &pre_2_10_vmstate_dummy_icp
,
155 (void *)(uintptr_t) i
);
158 static void pre_2_10_vmstate_unregister_dummy_icp(int i
)
160 vmstate_unregister(NULL
, &pre_2_10_vmstate_dummy_icp
,
161 (void *)(uintptr_t) i
);
164 int spapr_max_server_number(SpaprMachineState
*spapr
)
166 MachineState
*ms
= MACHINE(spapr
);
169 return DIV_ROUND_UP(ms
->smp
.max_cpus
* spapr
->vsmt
, ms
->smp
.threads
);
172 static int spapr_fixup_cpu_smt_dt(void *fdt
, int offset
, PowerPCCPU
*cpu
,
176 uint32_t servers_prop
[smt_threads
];
177 uint32_t gservers_prop
[smt_threads
* 2];
178 int index
= spapr_get_vcpu_id(cpu
);
180 if (cpu
->compat_pvr
) {
181 ret
= fdt_setprop_cell(fdt
, offset
, "cpu-version", cpu
->compat_pvr
);
187 /* Build interrupt servers and gservers properties */
188 for (i
= 0; i
< smt_threads
; i
++) {
189 servers_prop
[i
] = cpu_to_be32(index
+ i
);
190 /* Hack, direct the group queues back to cpu 0 */
191 gservers_prop
[i
*2] = cpu_to_be32(index
+ i
);
192 gservers_prop
[i
*2 + 1] = 0;
194 ret
= fdt_setprop(fdt
, offset
, "ibm,ppc-interrupt-server#s",
195 servers_prop
, sizeof(servers_prop
));
199 ret
= fdt_setprop(fdt
, offset
, "ibm,ppc-interrupt-gserver#s",
200 gservers_prop
, sizeof(gservers_prop
));
205 static int spapr_fixup_cpu_numa_dt(void *fdt
, int offset
, PowerPCCPU
*cpu
)
207 int index
= spapr_get_vcpu_id(cpu
);
208 uint32_t associativity
[] = {cpu_to_be32(0x5),
212 cpu_to_be32(cpu
->node_id
),
215 /* Advertise NUMA via ibm,associativity */
216 return fdt_setprop(fdt
, offset
, "ibm,associativity", associativity
,
217 sizeof(associativity
));
220 /* Populate the "ibm,pa-features" property */
221 static void spapr_populate_pa_features(SpaprMachineState
*spapr
,
223 void *fdt
, int offset
)
225 uint8_t pa_features_206
[] = { 6, 0,
226 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 };
227 uint8_t pa_features_207
[] = { 24, 0,
228 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0,
229 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
230 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
231 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 };
232 uint8_t pa_features_300
[] = { 66, 0,
233 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */
234 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */
235 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */
237 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */
239 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */
240 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */
241 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */
242 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */
243 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */
244 /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */
245 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */
246 /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */
247 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */
248 /* 42: PM, 44: PC RA, 46: SC vec'd */
249 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */
250 /* 48: SIMD, 50: QP BFP, 52: String */
251 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */
252 /* 54: DecFP, 56: DecI, 58: SHA */
253 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */
254 /* 60: NM atomic, 62: RNG */
255 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */
257 uint8_t *pa_features
= NULL
;
260 if (ppc_check_compat(cpu
, CPU_POWERPC_LOGICAL_2_06
, 0, cpu
->compat_pvr
)) {
261 pa_features
= pa_features_206
;
262 pa_size
= sizeof(pa_features_206
);
264 if (ppc_check_compat(cpu
, CPU_POWERPC_LOGICAL_2_07
, 0, cpu
->compat_pvr
)) {
265 pa_features
= pa_features_207
;
266 pa_size
= sizeof(pa_features_207
);
268 if (ppc_check_compat(cpu
, CPU_POWERPC_LOGICAL_3_00
, 0, cpu
->compat_pvr
)) {
269 pa_features
= pa_features_300
;
270 pa_size
= sizeof(pa_features_300
);
276 if (ppc_hash64_has(cpu
, PPC_HASH64_CI_LARGEPAGE
)) {
278 * Note: we keep CI large pages off by default because a 64K capable
279 * guest provisioned with large pages might otherwise try to map a qemu
280 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages
281 * even if that qemu runs on a 4k host.
282 * We dd this bit back here if we are confident this is not an issue
284 pa_features
[3] |= 0x20;
286 if ((spapr_get_cap(spapr
, SPAPR_CAP_HTM
) != 0) && pa_size
> 24) {
287 pa_features
[24] |= 0x80; /* Transactional memory support */
289 if (spapr
->cas_pre_isa3_guest
&& pa_size
> 40) {
290 /* Workaround for broken kernels that attempt (guest) radix
291 * mode when they can't handle it, if they see the radix bit set
292 * in pa-features. So hide it from them. */
293 pa_features
[40 + 2] &= ~0x80; /* Radix MMU */
296 _FDT((fdt_setprop(fdt
, offset
, "ibm,pa-features", pa_features
, pa_size
)));
299 static int spapr_fixup_cpu_dt(void *fdt
, SpaprMachineState
*spapr
)
301 MachineState
*ms
= MACHINE(spapr
);
302 int ret
= 0, offset
, cpus_offset
;
305 uint32_t pft_size_prop
[] = {0, cpu_to_be32(spapr
->htab_shift
)};
308 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
309 DeviceClass
*dc
= DEVICE_GET_CLASS(cs
);
310 int index
= spapr_get_vcpu_id(cpu
);
311 int compat_smt
= MIN(ms
->smp
.threads
, ppc_compat_max_vthreads(cpu
));
313 if (!spapr_is_thread0_in_vcore(spapr
, cpu
)) {
317 snprintf(cpu_model
, 32, "%s@%x", dc
->fw_name
, index
);
319 cpus_offset
= fdt_path_offset(fdt
, "/cpus");
320 if (cpus_offset
< 0) {
321 cpus_offset
= fdt_add_subnode(fdt
, 0, "cpus");
322 if (cpus_offset
< 0) {
326 offset
= fdt_subnode_offset(fdt
, cpus_offset
, cpu_model
);
328 offset
= fdt_add_subnode(fdt
, cpus_offset
, cpu_model
);
334 ret
= fdt_setprop(fdt
, offset
, "ibm,pft-size",
335 pft_size_prop
, sizeof(pft_size_prop
));
340 if (ms
->numa_state
->num_nodes
> 1) {
341 ret
= spapr_fixup_cpu_numa_dt(fdt
, offset
, cpu
);
347 ret
= spapr_fixup_cpu_smt_dt(fdt
, offset
, cpu
, compat_smt
);
352 spapr_populate_pa_features(spapr
, cpu
, fdt
, offset
);
357 static hwaddr
spapr_node0_size(MachineState
*machine
)
359 if (machine
->numa_state
->num_nodes
) {
361 for (i
= 0; i
< machine
->numa_state
->num_nodes
; ++i
) {
362 if (machine
->numa_state
->nodes
[i
].node_mem
) {
363 return MIN(pow2floor(machine
->numa_state
->nodes
[i
].node_mem
),
368 return machine
->ram_size
;
371 static void add_str(GString
*s
, const gchar
*s1
)
373 g_string_append_len(s
, s1
, strlen(s1
) + 1);
376 static int spapr_populate_memory_node(void *fdt
, int nodeid
, hwaddr start
,
379 uint32_t associativity
[] = {
380 cpu_to_be32(0x4), /* length */
381 cpu_to_be32(0x0), cpu_to_be32(0x0),
382 cpu_to_be32(0x0), cpu_to_be32(nodeid
)
385 uint64_t mem_reg_property
[2];
388 mem_reg_property
[0] = cpu_to_be64(start
);
389 mem_reg_property
[1] = cpu_to_be64(size
);
391 sprintf(mem_name
, "memory@%" HWADDR_PRIx
, start
);
392 off
= fdt_add_subnode(fdt
, 0, mem_name
);
394 _FDT((fdt_setprop_string(fdt
, off
, "device_type", "memory")));
395 _FDT((fdt_setprop(fdt
, off
, "reg", mem_reg_property
,
396 sizeof(mem_reg_property
))));
397 _FDT((fdt_setprop(fdt
, off
, "ibm,associativity", associativity
,
398 sizeof(associativity
))));
402 static int spapr_populate_memory(SpaprMachineState
*spapr
, void *fdt
)
404 MachineState
*machine
= MACHINE(spapr
);
405 hwaddr mem_start
, node_size
;
406 int i
, nb_nodes
= machine
->numa_state
->num_nodes
;
407 NodeInfo
*nodes
= machine
->numa_state
->nodes
;
410 /* No NUMA nodes, assume there is just one node with whole RAM */
413 ramnode
.node_mem
= machine
->ram_size
;
417 for (i
= 0, mem_start
= 0; i
< nb_nodes
; ++i
) {
418 if (!nodes
[i
].node_mem
) {
421 if (mem_start
>= machine
->ram_size
) {
424 node_size
= nodes
[i
].node_mem
;
425 if (node_size
> machine
->ram_size
- mem_start
) {
426 node_size
= machine
->ram_size
- mem_start
;
430 /* spapr_machine_init() checks for rma_size <= node0_size
432 spapr_populate_memory_node(fdt
, i
, 0, spapr
->rma_size
);
433 mem_start
+= spapr
->rma_size
;
434 node_size
-= spapr
->rma_size
;
436 for ( ; node_size
; ) {
437 hwaddr sizetmp
= pow2floor(node_size
);
439 /* mem_start != 0 here */
440 if (ctzl(mem_start
) < ctzl(sizetmp
)) {
441 sizetmp
= 1ULL << ctzl(mem_start
);
444 spapr_populate_memory_node(fdt
, i
, mem_start
, sizetmp
);
445 node_size
-= sizetmp
;
446 mem_start
+= sizetmp
;
453 static void spapr_populate_cpu_dt(CPUState
*cs
, void *fdt
, int offset
,
454 SpaprMachineState
*spapr
)
456 MachineState
*ms
= MACHINE(spapr
);
457 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
458 CPUPPCState
*env
= &cpu
->env
;
459 PowerPCCPUClass
*pcc
= POWERPC_CPU_GET_CLASS(cs
);
460 int index
= spapr_get_vcpu_id(cpu
);
461 uint32_t segs
[] = {cpu_to_be32(28), cpu_to_be32(40),
462 0xffffffff, 0xffffffff};
463 uint32_t tbfreq
= kvm_enabled() ? kvmppc_get_tbfreq()
464 : SPAPR_TIMEBASE_FREQ
;
465 uint32_t cpufreq
= kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000;
466 uint32_t page_sizes_prop
[64];
467 size_t page_sizes_prop_size
;
468 unsigned int smp_threads
= ms
->smp
.threads
;
469 uint32_t vcpus_per_socket
= smp_threads
* ms
->smp
.cores
;
470 uint32_t pft_size_prop
[] = {0, cpu_to_be32(spapr
->htab_shift
)};
471 int compat_smt
= MIN(smp_threads
, ppc_compat_max_vthreads(cpu
));
474 uint32_t radix_AP_encodings
[PPC_PAGE_SIZES_MAX_SZ
];
477 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_CPU
, index
);
479 drc_index
= spapr_drc_index(drc
);
480 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,my-drc-index", drc_index
)));
483 _FDT((fdt_setprop_cell(fdt
, offset
, "reg", index
)));
484 _FDT((fdt_setprop_string(fdt
, offset
, "device_type", "cpu")));
486 _FDT((fdt_setprop_cell(fdt
, offset
, "cpu-version", env
->spr
[SPR_PVR
])));
487 _FDT((fdt_setprop_cell(fdt
, offset
, "d-cache-block-size",
488 env
->dcache_line_size
)));
489 _FDT((fdt_setprop_cell(fdt
, offset
, "d-cache-line-size",
490 env
->dcache_line_size
)));
491 _FDT((fdt_setprop_cell(fdt
, offset
, "i-cache-block-size",
492 env
->icache_line_size
)));
493 _FDT((fdt_setprop_cell(fdt
, offset
, "i-cache-line-size",
494 env
->icache_line_size
)));
496 if (pcc
->l1_dcache_size
) {
497 _FDT((fdt_setprop_cell(fdt
, offset
, "d-cache-size",
498 pcc
->l1_dcache_size
)));
500 warn_report("Unknown L1 dcache size for cpu");
502 if (pcc
->l1_icache_size
) {
503 _FDT((fdt_setprop_cell(fdt
, offset
, "i-cache-size",
504 pcc
->l1_icache_size
)));
506 warn_report("Unknown L1 icache size for cpu");
509 _FDT((fdt_setprop_cell(fdt
, offset
, "timebase-frequency", tbfreq
)));
510 _FDT((fdt_setprop_cell(fdt
, offset
, "clock-frequency", cpufreq
)));
511 _FDT((fdt_setprop_cell(fdt
, offset
, "slb-size", cpu
->hash64_opts
->slb_size
)));
512 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,slb-size", cpu
->hash64_opts
->slb_size
)));
513 _FDT((fdt_setprop_string(fdt
, offset
, "status", "okay")));
514 _FDT((fdt_setprop(fdt
, offset
, "64-bit", NULL
, 0)));
516 if (env
->spr_cb
[SPR_PURR
].oea_read
) {
517 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,purr", 1)));
519 if (env
->spr_cb
[SPR_SPURR
].oea_read
) {
520 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,spurr", 1)));
523 if (ppc_hash64_has(cpu
, PPC_HASH64_1TSEG
)) {
524 _FDT((fdt_setprop(fdt
, offset
, "ibm,processor-segment-sizes",
525 segs
, sizeof(segs
))));
528 /* Advertise VSX (vector extensions) if available
529 * 1 == VMX / Altivec available
532 * Only CPUs for which we create core types in spapr_cpu_core.c
533 * are possible, and all of those have VMX */
534 if (spapr_get_cap(spapr
, SPAPR_CAP_VSX
) != 0) {
535 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,vmx", 2)));
537 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,vmx", 1)));
540 /* Advertise DFP (Decimal Floating Point) if available
541 * 0 / no property == no DFP
542 * 1 == DFP available */
543 if (spapr_get_cap(spapr
, SPAPR_CAP_DFP
) != 0) {
544 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,dfp", 1)));
547 page_sizes_prop_size
= ppc_create_page_sizes_prop(cpu
, page_sizes_prop
,
548 sizeof(page_sizes_prop
));
549 if (page_sizes_prop_size
) {
550 _FDT((fdt_setprop(fdt
, offset
, "ibm,segment-page-sizes",
551 page_sizes_prop
, page_sizes_prop_size
)));
554 spapr_populate_pa_features(spapr
, cpu
, fdt
, offset
);
556 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,chip-id",
557 cs
->cpu_index
/ vcpus_per_socket
)));
559 _FDT((fdt_setprop(fdt
, offset
, "ibm,pft-size",
560 pft_size_prop
, sizeof(pft_size_prop
))));
562 if (ms
->numa_state
->num_nodes
> 1) {
563 _FDT(spapr_fixup_cpu_numa_dt(fdt
, offset
, cpu
));
566 _FDT(spapr_fixup_cpu_smt_dt(fdt
, offset
, cpu
, compat_smt
));
568 if (pcc
->radix_page_info
) {
569 for (i
= 0; i
< pcc
->radix_page_info
->count
; i
++) {
570 radix_AP_encodings
[i
] =
571 cpu_to_be32(pcc
->radix_page_info
->entries
[i
]);
573 _FDT((fdt_setprop(fdt
, offset
, "ibm,processor-radix-AP-encodings",
575 pcc
->radix_page_info
->count
*
576 sizeof(radix_AP_encodings
[0]))));
580 * We set this property to let the guest know that it can use the large
581 * decrementer and its width in bits.
583 if (spapr_get_cap(spapr
, SPAPR_CAP_LARGE_DECREMENTER
) != SPAPR_CAP_OFF
)
584 _FDT((fdt_setprop_u32(fdt
, offset
, "ibm,dec-bits",
585 pcc
->lrg_decr_bits
)));
588 static void spapr_populate_cpus_dt_node(void *fdt
, SpaprMachineState
*spapr
)
597 cpus_offset
= fdt_add_subnode(fdt
, 0, "cpus");
599 _FDT((fdt_setprop_cell(fdt
, cpus_offset
, "#address-cells", 0x1)));
600 _FDT((fdt_setprop_cell(fdt
, cpus_offset
, "#size-cells", 0x0)));
603 * We walk the CPUs in reverse order to ensure that CPU DT nodes
604 * created by fdt_add_subnode() end up in the right order in FDT
605 * for the guest kernel the enumerate the CPUs correctly.
607 * The CPU list cannot be traversed in reverse order, so we need
613 rev
= g_renew(CPUState
*, rev
, n_cpus
+ 1);
617 for (i
= n_cpus
- 1; i
>= 0; i
--) {
618 CPUState
*cs
= rev
[i
];
619 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
620 int index
= spapr_get_vcpu_id(cpu
);
621 DeviceClass
*dc
= DEVICE_GET_CLASS(cs
);
624 if (!spapr_is_thread0_in_vcore(spapr
, cpu
)) {
628 nodename
= g_strdup_printf("%s@%x", dc
->fw_name
, index
);
629 offset
= fdt_add_subnode(fdt
, cpus_offset
, nodename
);
632 spapr_populate_cpu_dt(cs
, fdt
, offset
, spapr
);
638 static int spapr_rng_populate_dt(void *fdt
)
643 node
= qemu_fdt_add_subnode(fdt
, "/ibm,platform-facilities");
647 ret
= fdt_setprop_string(fdt
, node
, "device_type",
648 "ibm,platform-facilities");
649 ret
|= fdt_setprop_cell(fdt
, node
, "#address-cells", 0x1);
650 ret
|= fdt_setprop_cell(fdt
, node
, "#size-cells", 0x0);
652 node
= fdt_add_subnode(fdt
, node
, "ibm,random-v1");
656 ret
|= fdt_setprop_string(fdt
, node
, "compatible", "ibm,random");
661 static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList
*list
, ram_addr_t addr
)
663 MemoryDeviceInfoList
*info
;
665 for (info
= list
; info
; info
= info
->next
) {
666 MemoryDeviceInfo
*value
= info
->value
;
668 if (value
&& value
->type
== MEMORY_DEVICE_INFO_KIND_DIMM
) {
669 PCDIMMDeviceInfo
*pcdimm_info
= value
->u
.dimm
.data
;
671 if (addr
>= pcdimm_info
->addr
&&
672 addr
< (pcdimm_info
->addr
+ pcdimm_info
->size
)) {
673 return pcdimm_info
->node
;
681 struct sPAPRDrconfCellV2
{
689 typedef struct DrconfCellQueue
{
690 struct sPAPRDrconfCellV2 cell
;
691 QSIMPLEQ_ENTRY(DrconfCellQueue
) entry
;
694 static DrconfCellQueue
*
695 spapr_get_drconf_cell(uint32_t seq_lmbs
, uint64_t base_addr
,
696 uint32_t drc_index
, uint32_t aa_index
,
699 DrconfCellQueue
*elem
;
701 elem
= g_malloc0(sizeof(*elem
));
702 elem
->cell
.seq_lmbs
= cpu_to_be32(seq_lmbs
);
703 elem
->cell
.base_addr
= cpu_to_be64(base_addr
);
704 elem
->cell
.drc_index
= cpu_to_be32(drc_index
);
705 elem
->cell
.aa_index
= cpu_to_be32(aa_index
);
706 elem
->cell
.flags
= cpu_to_be32(flags
);
711 /* ibm,dynamic-memory-v2 */
712 static int spapr_populate_drmem_v2(SpaprMachineState
*spapr
, void *fdt
,
713 int offset
, MemoryDeviceInfoList
*dimms
)
715 MachineState
*machine
= MACHINE(spapr
);
716 uint8_t *int_buf
, *cur_index
;
718 uint64_t lmb_size
= SPAPR_MEMORY_BLOCK_SIZE
;
719 uint64_t addr
, cur_addr
, size
;
720 uint32_t nr_boot_lmbs
= (machine
->device_memory
->base
/ lmb_size
);
721 uint64_t mem_end
= machine
->device_memory
->base
+
722 memory_region_size(&machine
->device_memory
->mr
);
723 uint32_t node
, buf_len
, nr_entries
= 0;
725 DrconfCellQueue
*elem
, *next
;
726 MemoryDeviceInfoList
*info
;
727 QSIMPLEQ_HEAD(, DrconfCellQueue
) drconf_queue
728 = QSIMPLEQ_HEAD_INITIALIZER(drconf_queue
);
730 /* Entry to cover RAM and the gap area */
731 elem
= spapr_get_drconf_cell(nr_boot_lmbs
, 0, 0, -1,
732 SPAPR_LMB_FLAGS_RESERVED
|
733 SPAPR_LMB_FLAGS_DRC_INVALID
);
734 QSIMPLEQ_INSERT_TAIL(&drconf_queue
, elem
, entry
);
737 cur_addr
= machine
->device_memory
->base
;
738 for (info
= dimms
; info
; info
= info
->next
) {
739 PCDIMMDeviceInfo
*di
= info
->value
->u
.dimm
.data
;
745 /* Entry for hot-pluggable area */
746 if (cur_addr
< addr
) {
747 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
, cur_addr
/ lmb_size
);
749 elem
= spapr_get_drconf_cell((addr
- cur_addr
) / lmb_size
,
750 cur_addr
, spapr_drc_index(drc
), -1, 0);
751 QSIMPLEQ_INSERT_TAIL(&drconf_queue
, elem
, entry
);
756 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
, addr
/ lmb_size
);
758 elem
= spapr_get_drconf_cell(size
/ lmb_size
, addr
,
759 spapr_drc_index(drc
), node
,
760 SPAPR_LMB_FLAGS_ASSIGNED
);
761 QSIMPLEQ_INSERT_TAIL(&drconf_queue
, elem
, entry
);
763 cur_addr
= addr
+ size
;
766 /* Entry for remaining hotpluggable area */
767 if (cur_addr
< mem_end
) {
768 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
, cur_addr
/ lmb_size
);
770 elem
= spapr_get_drconf_cell((mem_end
- cur_addr
) / lmb_size
,
771 cur_addr
, spapr_drc_index(drc
), -1, 0);
772 QSIMPLEQ_INSERT_TAIL(&drconf_queue
, elem
, entry
);
776 buf_len
= nr_entries
* sizeof(struct sPAPRDrconfCellV2
) + sizeof(uint32_t);
777 int_buf
= cur_index
= g_malloc0(buf_len
);
778 *(uint32_t *)int_buf
= cpu_to_be32(nr_entries
);
779 cur_index
+= sizeof(nr_entries
);
781 QSIMPLEQ_FOREACH_SAFE(elem
, &drconf_queue
, entry
, next
) {
782 memcpy(cur_index
, &elem
->cell
, sizeof(elem
->cell
));
783 cur_index
+= sizeof(elem
->cell
);
784 QSIMPLEQ_REMOVE(&drconf_queue
, elem
, DrconfCellQueue
, entry
);
788 ret
= fdt_setprop(fdt
, offset
, "ibm,dynamic-memory-v2", int_buf
, buf_len
);
796 /* ibm,dynamic-memory */
797 static int spapr_populate_drmem_v1(SpaprMachineState
*spapr
, void *fdt
,
798 int offset
, MemoryDeviceInfoList
*dimms
)
800 MachineState
*machine
= MACHINE(spapr
);
802 uint64_t lmb_size
= SPAPR_MEMORY_BLOCK_SIZE
;
803 uint32_t device_lmb_start
= machine
->device_memory
->base
/ lmb_size
;
804 uint32_t nr_lmbs
= (machine
->device_memory
->base
+
805 memory_region_size(&machine
->device_memory
->mr
)) /
807 uint32_t *int_buf
, *cur_index
, buf_len
;
810 * Allocate enough buffer size to fit in ibm,dynamic-memory
812 buf_len
= (nr_lmbs
* SPAPR_DR_LMB_LIST_ENTRY_SIZE
+ 1) * sizeof(uint32_t);
813 cur_index
= int_buf
= g_malloc0(buf_len
);
814 int_buf
[0] = cpu_to_be32(nr_lmbs
);
816 for (i
= 0; i
< nr_lmbs
; i
++) {
817 uint64_t addr
= i
* lmb_size
;
818 uint32_t *dynamic_memory
= cur_index
;
820 if (i
>= device_lmb_start
) {
823 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
, i
);
826 dynamic_memory
[0] = cpu_to_be32(addr
>> 32);
827 dynamic_memory
[1] = cpu_to_be32(addr
& 0xffffffff);
828 dynamic_memory
[2] = cpu_to_be32(spapr_drc_index(drc
));
829 dynamic_memory
[3] = cpu_to_be32(0); /* reserved */
830 dynamic_memory
[4] = cpu_to_be32(spapr_pc_dimm_node(dimms
, addr
));
831 if (memory_region_present(get_system_memory(), addr
)) {
832 dynamic_memory
[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED
);
834 dynamic_memory
[5] = cpu_to_be32(0);
838 * LMB information for RMA, boot time RAM and gap b/n RAM and
839 * device memory region -- all these are marked as reserved
840 * and as having no valid DRC.
842 dynamic_memory
[0] = cpu_to_be32(addr
>> 32);
843 dynamic_memory
[1] = cpu_to_be32(addr
& 0xffffffff);
844 dynamic_memory
[2] = cpu_to_be32(0);
845 dynamic_memory
[3] = cpu_to_be32(0); /* reserved */
846 dynamic_memory
[4] = cpu_to_be32(-1);
847 dynamic_memory
[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED
|
848 SPAPR_LMB_FLAGS_DRC_INVALID
);
851 cur_index
+= SPAPR_DR_LMB_LIST_ENTRY_SIZE
;
853 ret
= fdt_setprop(fdt
, offset
, "ibm,dynamic-memory", int_buf
, buf_len
);
862 * Adds ibm,dynamic-reconfiguration-memory node.
863 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation
864 * of this device tree node.
866 static int spapr_populate_drconf_memory(SpaprMachineState
*spapr
, void *fdt
)
868 MachineState
*machine
= MACHINE(spapr
);
869 int nb_numa_nodes
= machine
->numa_state
->num_nodes
;
871 uint64_t lmb_size
= SPAPR_MEMORY_BLOCK_SIZE
;
872 uint32_t prop_lmb_size
[] = {0, cpu_to_be32(lmb_size
)};
873 uint32_t *int_buf
, *cur_index
, buf_len
;
874 int nr_nodes
= nb_numa_nodes
? nb_numa_nodes
: 1;
875 MemoryDeviceInfoList
*dimms
= NULL
;
878 * Don't create the node if there is no device memory
880 if (machine
->ram_size
== machine
->maxram_size
) {
884 offset
= fdt_add_subnode(fdt
, 0, "ibm,dynamic-reconfiguration-memory");
886 ret
= fdt_setprop(fdt
, offset
, "ibm,lmb-size", prop_lmb_size
,
887 sizeof(prop_lmb_size
));
892 ret
= fdt_setprop_cell(fdt
, offset
, "ibm,memory-flags-mask", 0xff);
897 ret
= fdt_setprop_cell(fdt
, offset
, "ibm,memory-preservation-time", 0x0);
902 /* ibm,dynamic-memory or ibm,dynamic-memory-v2 */
903 dimms
= qmp_memory_device_list();
904 if (spapr_ovec_test(spapr
->ov5_cas
, OV5_DRMEM_V2
)) {
905 ret
= spapr_populate_drmem_v2(spapr
, fdt
, offset
, dimms
);
907 ret
= spapr_populate_drmem_v1(spapr
, fdt
, offset
, dimms
);
909 qapi_free_MemoryDeviceInfoList(dimms
);
915 /* ibm,associativity-lookup-arrays */
916 buf_len
= (nr_nodes
* 4 + 2) * sizeof(uint32_t);
917 cur_index
= int_buf
= g_malloc0(buf_len
);
918 int_buf
[0] = cpu_to_be32(nr_nodes
);
919 int_buf
[1] = cpu_to_be32(4); /* Number of entries per associativity list */
921 for (i
= 0; i
< nr_nodes
; i
++) {
922 uint32_t associativity
[] = {
928 memcpy(cur_index
, associativity
, sizeof(associativity
));
931 ret
= fdt_setprop(fdt
, offset
, "ibm,associativity-lookup-arrays", int_buf
,
932 (cur_index
- int_buf
) * sizeof(uint32_t));
938 static int spapr_dt_cas_updates(SpaprMachineState
*spapr
, void *fdt
,
939 SpaprOptionVector
*ov5_updates
)
941 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(spapr
);
944 /* Generate ibm,dynamic-reconfiguration-memory node if required */
945 if (spapr_ovec_test(ov5_updates
, OV5_DRCONF_MEMORY
)) {
946 g_assert(smc
->dr_lmb_enabled
);
947 ret
= spapr_populate_drconf_memory(spapr
, fdt
);
953 offset
= fdt_path_offset(fdt
, "/chosen");
955 offset
= fdt_add_subnode(fdt
, 0, "chosen");
960 ret
= spapr_ovec_populate_dt(fdt
, offset
, spapr
->ov5_cas
,
961 "ibm,architecture-vec-5");
967 static bool spapr_hotplugged_dev_before_cas(void)
969 Object
*drc_container
, *obj
;
970 ObjectProperty
*prop
;
971 ObjectPropertyIterator iter
;
973 drc_container
= container_get(object_get_root(), "/dr-connector");
974 object_property_iter_init(&iter
, drc_container
);
975 while ((prop
= object_property_iter_next(&iter
))) {
976 if (!strstart(prop
->type
, "link<", NULL
)) {
979 obj
= object_property_get_link(drc_container
, prop
->name
, NULL
);
980 if (spapr_drc_needed(obj
)) {
987 int spapr_h_cas_compose_response(SpaprMachineState
*spapr
,
988 target_ulong addr
, target_ulong size
,
989 SpaprOptionVector
*ov5_updates
)
991 void *fdt
, *fdt_skel
;
992 SpaprDeviceTreeUpdateHeader hdr
= { .version_id
= 1 };
994 if (spapr_hotplugged_dev_before_cas()) {
998 if (size
< sizeof(hdr
) || size
> FW_MAX_SIZE
) {
999 error_report("SLOF provided an unexpected CAS buffer size "
1000 TARGET_FMT_lu
" (min: %zu, max: %u)",
1001 size
, sizeof(hdr
), FW_MAX_SIZE
);
1005 size
-= sizeof(hdr
);
1007 /* Create skeleton */
1008 fdt_skel
= g_malloc0(size
);
1009 _FDT((fdt_create(fdt_skel
, size
)));
1010 _FDT((fdt_finish_reservemap(fdt_skel
)));
1011 _FDT((fdt_begin_node(fdt_skel
, "")));
1012 _FDT((fdt_end_node(fdt_skel
)));
1013 _FDT((fdt_finish(fdt_skel
)));
1014 fdt
= g_malloc0(size
);
1015 _FDT((fdt_open_into(fdt_skel
, fdt
, size
)));
1018 /* Fixup cpu nodes */
1019 _FDT((spapr_fixup_cpu_dt(fdt
, spapr
)));
1021 if (spapr_dt_cas_updates(spapr
, fdt
, ov5_updates
)) {
1025 /* Pack resulting tree */
1026 _FDT((fdt_pack(fdt
)));
1028 if (fdt_totalsize(fdt
) + sizeof(hdr
) > size
) {
1030 trace_spapr_cas_failed(size
);
1034 cpu_physical_memory_write(addr
, &hdr
, sizeof(hdr
));
1035 cpu_physical_memory_write(addr
+ sizeof(hdr
), fdt
, fdt_totalsize(fdt
));
1036 trace_spapr_cas_continue(fdt_totalsize(fdt
) + sizeof(hdr
));
1042 static void spapr_dt_rtas(SpaprMachineState
*spapr
, void *fdt
)
1044 MachineState
*ms
= MACHINE(spapr
);
1046 GString
*hypertas
= g_string_sized_new(256);
1047 GString
*qemu_hypertas
= g_string_sized_new(256);
1048 uint32_t refpoints
[] = { cpu_to_be32(0x4), cpu_to_be32(0x4) };
1049 uint64_t max_device_addr
= MACHINE(spapr
)->device_memory
->base
+
1050 memory_region_size(&MACHINE(spapr
)->device_memory
->mr
);
1051 uint32_t lrdr_capacity
[] = {
1052 cpu_to_be32(max_device_addr
>> 32),
1053 cpu_to_be32(max_device_addr
& 0xffffffff),
1054 0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE
),
1055 cpu_to_be32(ms
->smp
.max_cpus
/ ms
->smp
.threads
),
1057 uint32_t maxdomain
= cpu_to_be32(spapr
->gpu_numa_id
> 1 ? 1 : 0);
1058 uint32_t maxdomains
[] = {
1063 cpu_to_be32(spapr
->gpu_numa_id
),
1066 _FDT(rtas
= fdt_add_subnode(fdt
, 0, "rtas"));
1069 add_str(hypertas
, "hcall-pft");
1070 add_str(hypertas
, "hcall-term");
1071 add_str(hypertas
, "hcall-dabr");
1072 add_str(hypertas
, "hcall-interrupt");
1073 add_str(hypertas
, "hcall-tce");
1074 add_str(hypertas
, "hcall-vio");
1075 add_str(hypertas
, "hcall-splpar");
1076 add_str(hypertas
, "hcall-join");
1077 add_str(hypertas
, "hcall-bulk");
1078 add_str(hypertas
, "hcall-set-mode");
1079 add_str(hypertas
, "hcall-sprg0");
1080 add_str(hypertas
, "hcall-copy");
1081 add_str(hypertas
, "hcall-debug");
1082 add_str(hypertas
, "hcall-vphn");
1083 add_str(qemu_hypertas
, "hcall-memop1");
1085 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) {
1086 add_str(hypertas
, "hcall-multi-tce");
1089 if (spapr
->resize_hpt
!= SPAPR_RESIZE_HPT_DISABLED
) {
1090 add_str(hypertas
, "hcall-hpt-resize");
1093 _FDT(fdt_setprop(fdt
, rtas
, "ibm,hypertas-functions",
1094 hypertas
->str
, hypertas
->len
));
1095 g_string_free(hypertas
, TRUE
);
1096 _FDT(fdt_setprop(fdt
, rtas
, "qemu,hypertas-functions",
1097 qemu_hypertas
->str
, qemu_hypertas
->len
));
1098 g_string_free(qemu_hypertas
, TRUE
);
1100 _FDT(fdt_setprop(fdt
, rtas
, "ibm,associativity-reference-points",
1101 refpoints
, sizeof(refpoints
)));
1103 _FDT(fdt_setprop(fdt
, rtas
, "ibm,max-associativity-domains",
1104 maxdomains
, sizeof(maxdomains
)));
1106 _FDT(fdt_setprop_cell(fdt
, rtas
, "rtas-error-log-max",
1107 RTAS_ERROR_LOG_MAX
));
1108 _FDT(fdt_setprop_cell(fdt
, rtas
, "rtas-event-scan-rate",
1109 RTAS_EVENT_SCAN_RATE
));
1111 g_assert(msi_nonbroken
);
1112 _FDT(fdt_setprop(fdt
, rtas
, "ibm,change-msix-capable", NULL
, 0));
1115 * According to PAPR, rtas ibm,os-term does not guarantee a return
1116 * back to the guest cpu.
1118 * While an additional ibm,extended-os-term property indicates
1119 * that rtas call return will always occur. Set this property.
1121 _FDT(fdt_setprop(fdt
, rtas
, "ibm,extended-os-term", NULL
, 0));
1123 _FDT(fdt_setprop(fdt
, rtas
, "ibm,lrdr-capacity",
1124 lrdr_capacity
, sizeof(lrdr_capacity
)));
1126 spapr_dt_rtas_tokens(fdt
, rtas
);
1130 * Prepare ibm,arch-vec-5-platform-support, which indicates the MMU
1131 * and the XIVE features that the guest may request and thus the valid
1132 * values for bytes 23..26 of option vector 5:
1134 static void spapr_dt_ov5_platform_support(SpaprMachineState
*spapr
, void *fdt
,
1137 PowerPCCPU
*first_ppc_cpu
= POWERPC_CPU(first_cpu
);
1140 23, spapr
->irq
->ov5
, /* Xive mode. */
1141 24, 0x00, /* Hash/Radix, filled in below. */
1142 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */
1143 26, 0x40, /* Radix options: GTSE == yes. */
1146 if (!ppc_check_compat(first_ppc_cpu
, CPU_POWERPC_LOGICAL_3_00
, 0,
1147 first_ppc_cpu
->compat_pvr
)) {
1149 * If we're in a pre POWER9 compat mode then the guest should
1150 * do hash and use the legacy interrupt mode
1152 val
[1] = 0x00; /* XICS */
1153 val
[3] = 0x00; /* Hash */
1154 } else if (kvm_enabled()) {
1155 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) {
1156 val
[3] = 0x80; /* OV5_MMU_BOTH */
1157 } else if (kvmppc_has_cap_mmu_radix()) {
1158 val
[3] = 0x40; /* OV5_MMU_RADIX_300 */
1160 val
[3] = 0x00; /* Hash */
1163 /* V3 MMU supports both hash and radix in tcg (with dynamic switching) */
1166 _FDT(fdt_setprop(fdt
, chosen
, "ibm,arch-vec-5-platform-support",
1170 static void spapr_dt_chosen(SpaprMachineState
*spapr
, void *fdt
)
1172 MachineState
*machine
= MACHINE(spapr
);
1173 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(machine
);
1175 const char *boot_device
= machine
->boot_order
;
1176 char *stdout_path
= spapr_vio_stdout_path(spapr
->vio_bus
);
1178 char *bootlist
= get_boot_devices_list(&cb
);
1180 _FDT(chosen
= fdt_add_subnode(fdt
, 0, "chosen"));
1182 if (machine
->kernel_cmdline
&& machine
->kernel_cmdline
[0]) {
1183 _FDT(fdt_setprop_string(fdt
, chosen
, "bootargs",
1184 machine
->kernel_cmdline
));
1186 if (spapr
->initrd_size
) {
1187 _FDT(fdt_setprop_cell(fdt
, chosen
, "linux,initrd-start",
1188 spapr
->initrd_base
));
1189 _FDT(fdt_setprop_cell(fdt
, chosen
, "linux,initrd-end",
1190 spapr
->initrd_base
+ spapr
->initrd_size
));
1193 if (spapr
->kernel_size
) {
1194 uint64_t kprop
[2] = { cpu_to_be64(KERNEL_LOAD_ADDR
),
1195 cpu_to_be64(spapr
->kernel_size
) };
1197 _FDT(fdt_setprop(fdt
, chosen
, "qemu,boot-kernel",
1198 &kprop
, sizeof(kprop
)));
1199 if (spapr
->kernel_le
) {
1200 _FDT(fdt_setprop(fdt
, chosen
, "qemu,boot-kernel-le", NULL
, 0));
1204 _FDT((fdt_setprop_cell(fdt
, chosen
, "qemu,boot-menu", boot_menu
)));
1206 _FDT(fdt_setprop_cell(fdt
, chosen
, "qemu,graphic-width", graphic_width
));
1207 _FDT(fdt_setprop_cell(fdt
, chosen
, "qemu,graphic-height", graphic_height
));
1208 _FDT(fdt_setprop_cell(fdt
, chosen
, "qemu,graphic-depth", graphic_depth
));
1210 if (cb
&& bootlist
) {
1213 for (i
= 0; i
< cb
; i
++) {
1214 if (bootlist
[i
] == '\n') {
1218 _FDT(fdt_setprop_string(fdt
, chosen
, "qemu,boot-list", bootlist
));
1221 if (boot_device
&& strlen(boot_device
)) {
1222 _FDT(fdt_setprop_string(fdt
, chosen
, "qemu,boot-device", boot_device
));
1225 if (!spapr
->has_graphics
&& stdout_path
) {
1227 * "linux,stdout-path" and "stdout" properties are deprecated by linux
1228 * kernel. New platforms should only use the "stdout-path" property. Set
1229 * the new property and continue using older property to remain
1230 * compatible with the existing firmware.
1232 _FDT(fdt_setprop_string(fdt
, chosen
, "linux,stdout-path", stdout_path
));
1233 _FDT(fdt_setprop_string(fdt
, chosen
, "stdout-path", stdout_path
));
1236 /* We can deal with BAR reallocation just fine, advertise it to the guest */
1237 if (smc
->linux_pci_probe
) {
1238 _FDT(fdt_setprop_cell(fdt
, chosen
, "linux,pci-probe-only", 0));
1241 spapr_dt_ov5_platform_support(spapr
, fdt
, chosen
);
1243 g_free(stdout_path
);
1247 static void spapr_dt_hypervisor(SpaprMachineState
*spapr
, void *fdt
)
1249 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR
1250 * KVM to work under pHyp with some guest co-operation */
1252 uint8_t hypercall
[16];
1254 _FDT(hypervisor
= fdt_add_subnode(fdt
, 0, "hypervisor"));
1255 /* indicate KVM hypercall interface */
1256 _FDT(fdt_setprop_string(fdt
, hypervisor
, "compatible", "linux,kvm"));
1257 if (kvmppc_has_cap_fixup_hcalls()) {
1259 * Older KVM versions with older guest kernels were broken
1260 * with the magic page, don't allow the guest to map it.
1262 if (!kvmppc_get_hypercall(first_cpu
->env_ptr
, hypercall
,
1263 sizeof(hypercall
))) {
1264 _FDT(fdt_setprop(fdt
, hypervisor
, "hcall-instructions",
1265 hypercall
, sizeof(hypercall
)));
1270 static void *spapr_build_fdt(SpaprMachineState
*spapr
)
1272 MachineState
*machine
= MACHINE(spapr
);
1273 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
1274 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(machine
);
1280 fdt
= g_malloc0(FDT_MAX_SIZE
);
1281 _FDT((fdt_create_empty_tree(fdt
, FDT_MAX_SIZE
)));
1284 _FDT(fdt_setprop_string(fdt
, 0, "device_type", "chrp"));
1285 _FDT(fdt_setprop_string(fdt
, 0, "model", "IBM pSeries (emulated by qemu)"));
1286 _FDT(fdt_setprop_string(fdt
, 0, "compatible", "qemu,pseries"));
1288 /* Guest UUID & Name*/
1289 buf
= qemu_uuid_unparse_strdup(&qemu_uuid
);
1290 _FDT(fdt_setprop_string(fdt
, 0, "vm,uuid", buf
));
1291 if (qemu_uuid_set
) {
1292 _FDT(fdt_setprop_string(fdt
, 0, "system-id", buf
));
1296 if (qemu_get_vm_name()) {
1297 _FDT(fdt_setprop_string(fdt
, 0, "ibm,partition-name",
1298 qemu_get_vm_name()));
1301 /* Host Model & Serial Number */
1302 if (spapr
->host_model
) {
1303 _FDT(fdt_setprop_string(fdt
, 0, "host-model", spapr
->host_model
));
1304 } else if (smc
->broken_host_serial_model
&& kvmppc_get_host_model(&buf
)) {
1305 _FDT(fdt_setprop_string(fdt
, 0, "host-model", buf
));
1309 if (spapr
->host_serial
) {
1310 _FDT(fdt_setprop_string(fdt
, 0, "host-serial", spapr
->host_serial
));
1311 } else if (smc
->broken_host_serial_model
&& kvmppc_get_host_serial(&buf
)) {
1312 _FDT(fdt_setprop_string(fdt
, 0, "host-serial", buf
));
1316 _FDT(fdt_setprop_cell(fdt
, 0, "#address-cells", 2));
1317 _FDT(fdt_setprop_cell(fdt
, 0, "#size-cells", 2));
1319 /* /interrupt controller */
1320 spapr
->irq
->dt_populate(spapr
, spapr_max_server_number(spapr
), fdt
,
1323 ret
= spapr_populate_memory(spapr
, fdt
);
1325 error_report("couldn't setup memory nodes in fdt");
1330 spapr_dt_vdevice(spapr
->vio_bus
, fdt
);
1332 if (object_resolve_path_type("", TYPE_SPAPR_RNG
, NULL
)) {
1333 ret
= spapr_rng_populate_dt(fdt
);
1335 error_report("could not set up rng device in the fdt");
1340 QLIST_FOREACH(phb
, &spapr
->phbs
, list
) {
1341 ret
= spapr_dt_phb(phb
, PHANDLE_INTC
, fdt
, spapr
->irq
->nr_msis
, NULL
);
1343 error_report("couldn't setup PCI devices in fdt");
1349 spapr_populate_cpus_dt_node(fdt
, spapr
);
1351 if (smc
->dr_lmb_enabled
) {
1352 _FDT(spapr_dt_drc(fdt
, 0, NULL
, SPAPR_DR_CONNECTOR_TYPE_LMB
));
1355 if (mc
->has_hotpluggable_cpus
) {
1356 int offset
= fdt_path_offset(fdt
, "/cpus");
1357 ret
= spapr_dt_drc(fdt
, offset
, NULL
, SPAPR_DR_CONNECTOR_TYPE_CPU
);
1359 error_report("Couldn't set up CPU DR device tree properties");
1364 /* /event-sources */
1365 spapr_dt_events(spapr
, fdt
);
1368 spapr_dt_rtas(spapr
, fdt
);
1371 spapr_dt_chosen(spapr
, fdt
);
1374 if (kvm_enabled()) {
1375 spapr_dt_hypervisor(spapr
, fdt
);
1378 /* Build memory reserve map */
1379 if (spapr
->kernel_size
) {
1380 _FDT((fdt_add_mem_rsv(fdt
, KERNEL_LOAD_ADDR
, spapr
->kernel_size
)));
1382 if (spapr
->initrd_size
) {
1383 _FDT((fdt_add_mem_rsv(fdt
, spapr
->initrd_base
, spapr
->initrd_size
)));
1386 /* ibm,client-architecture-support updates */
1387 ret
= spapr_dt_cas_updates(spapr
, fdt
, spapr
->ov5_cas
);
1389 error_report("couldn't setup CAS properties fdt");
1393 if (smc
->dr_phb_enabled
) {
1394 ret
= spapr_dt_drc(fdt
, 0, NULL
, SPAPR_DR_CONNECTOR_TYPE_PHB
);
1396 error_report("Couldn't set up PHB DR device tree properties");
1404 static uint64_t translate_kernel_address(void *opaque
, uint64_t addr
)
1406 return (addr
& 0x0fffffff) + KERNEL_LOAD_ADDR
;
1409 static void emulate_spapr_hypercall(PPCVirtualHypervisor
*vhyp
,
1412 CPUPPCState
*env
= &cpu
->env
;
1414 /* The TCG path should also be holding the BQL at this point */
1415 g_assert(qemu_mutex_iothread_locked());
1418 hcall_dprintf("Hypercall made with MSR[PR]=1\n");
1419 env
->gpr
[3] = H_PRIVILEGE
;
1421 env
->gpr
[3] = spapr_hypercall(cpu
, env
->gpr
[3], &env
->gpr
[4]);
1425 struct LPCRSyncState
{
1430 static void do_lpcr_sync(CPUState
*cs
, run_on_cpu_data arg
)
1432 struct LPCRSyncState
*s
= arg
.host_ptr
;
1433 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
1434 CPUPPCState
*env
= &cpu
->env
;
1437 cpu_synchronize_state(cs
);
1438 lpcr
= env
->spr
[SPR_LPCR
];
1441 ppc_store_lpcr(cpu
, lpcr
);
1444 void spapr_set_all_lpcrs(target_ulong value
, target_ulong mask
)
1447 struct LPCRSyncState s
= {
1452 run_on_cpu(cs
, do_lpcr_sync
, RUN_ON_CPU_HOST_PTR(&s
));
1456 static void spapr_get_pate(PPCVirtualHypervisor
*vhyp
, ppc_v3_pate_t
*entry
)
1458 SpaprMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1460 /* Copy PATE1:GR into PATE0:HR */
1461 entry
->dw0
= spapr
->patb_entry
& PATE0_HR
;
1462 entry
->dw1
= spapr
->patb_entry
;
1465 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2))
1466 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID)
1467 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY)
1468 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY))
1469 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY))
1472 * Get the fd to access the kernel htab, re-opening it if necessary
1474 static int get_htab_fd(SpaprMachineState
*spapr
)
1476 Error
*local_err
= NULL
;
1478 if (spapr
->htab_fd
>= 0) {
1479 return spapr
->htab_fd
;
1482 spapr
->htab_fd
= kvmppc_get_htab_fd(false, 0, &local_err
);
1483 if (spapr
->htab_fd
< 0) {
1484 error_report_err(local_err
);
1487 return spapr
->htab_fd
;
1490 void close_htab_fd(SpaprMachineState
*spapr
)
1492 if (spapr
->htab_fd
>= 0) {
1493 close(spapr
->htab_fd
);
1495 spapr
->htab_fd
= -1;
1498 static hwaddr
spapr_hpt_mask(PPCVirtualHypervisor
*vhyp
)
1500 SpaprMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1502 return HTAB_SIZE(spapr
) / HASH_PTEG_SIZE_64
- 1;
1505 static target_ulong
spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor
*vhyp
)
1507 SpaprMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1509 assert(kvm_enabled());
1515 return (target_ulong
)(uintptr_t)spapr
->htab
| (spapr
->htab_shift
- 18);
1518 static const ppc_hash_pte64_t
*spapr_map_hptes(PPCVirtualHypervisor
*vhyp
,
1521 SpaprMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1522 hwaddr pte_offset
= ptex
* HASH_PTE_SIZE_64
;
1526 * HTAB is controlled by KVM. Fetch into temporary buffer
1528 ppc_hash_pte64_t
*hptes
= g_malloc(n
* HASH_PTE_SIZE_64
);
1529 kvmppc_read_hptes(hptes
, ptex
, n
);
1534 * HTAB is controlled by QEMU. Just point to the internally
1537 return (const ppc_hash_pte64_t
*)(spapr
->htab
+ pte_offset
);
1540 static void spapr_unmap_hptes(PPCVirtualHypervisor
*vhyp
,
1541 const ppc_hash_pte64_t
*hptes
,
1544 SpaprMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1547 g_free((void *)hptes
);
1550 /* Nothing to do for qemu managed HPT */
1553 void spapr_store_hpte(PowerPCCPU
*cpu
, hwaddr ptex
,
1554 uint64_t pte0
, uint64_t pte1
)
1556 SpaprMachineState
*spapr
= SPAPR_MACHINE(cpu
->vhyp
);
1557 hwaddr offset
= ptex
* HASH_PTE_SIZE_64
;
1560 kvmppc_write_hpte(ptex
, pte0
, pte1
);
1562 if (pte0
& HPTE64_V_VALID
) {
1563 stq_p(spapr
->htab
+ offset
+ HASH_PTE_SIZE_64
/ 2, pte1
);
1565 * When setting valid, we write PTE1 first. This ensures
1566 * proper synchronization with the reading code in
1567 * ppc_hash64_pteg_search()
1570 stq_p(spapr
->htab
+ offset
, pte0
);
1572 stq_p(spapr
->htab
+ offset
, pte0
);
1574 * When clearing it we set PTE0 first. This ensures proper
1575 * synchronization with the reading code in
1576 * ppc_hash64_pteg_search()
1579 stq_p(spapr
->htab
+ offset
+ HASH_PTE_SIZE_64
/ 2, pte1
);
1584 static void spapr_hpte_set_c(PPCVirtualHypervisor
*vhyp
, hwaddr ptex
,
1587 hwaddr offset
= ptex
* HASH_PTE_SIZE_64
+ 15;
1588 SpaprMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1591 /* There should always be a hash table when this is called */
1592 error_report("spapr_hpte_set_c called with no hash table !");
1596 /* The HW performs a non-atomic byte update */
1597 stb_p(spapr
->htab
+ offset
, (pte1
& 0xff) | 0x80);
1600 static void spapr_hpte_set_r(PPCVirtualHypervisor
*vhyp
, hwaddr ptex
,
1603 hwaddr offset
= ptex
* HASH_PTE_SIZE_64
+ 14;
1604 SpaprMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1607 /* There should always be a hash table when this is called */
1608 error_report("spapr_hpte_set_r called with no hash table !");
1612 /* The HW performs a non-atomic byte update */
1613 stb_p(spapr
->htab
+ offset
, ((pte1
>> 8) & 0xff) | 0x01);
1616 int spapr_hpt_shift_for_ramsize(uint64_t ramsize
)
1620 /* We aim for a hash table of size 1/128 the size of RAM (rounded
1621 * up). The PAPR recommendation is actually 1/64 of RAM size, but
1622 * that's much more than is needed for Linux guests */
1623 shift
= ctz64(pow2ceil(ramsize
)) - 7;
1624 shift
= MAX(shift
, 18); /* Minimum architected size */
1625 shift
= MIN(shift
, 46); /* Maximum architected size */
1629 void spapr_free_hpt(SpaprMachineState
*spapr
)
1631 g_free(spapr
->htab
);
1633 spapr
->htab_shift
= 0;
1634 close_htab_fd(spapr
);
1637 void spapr_reallocate_hpt(SpaprMachineState
*spapr
, int shift
,
1642 /* Clean up any HPT info from a previous boot */
1643 spapr_free_hpt(spapr
);
1645 rc
= kvmppc_reset_htab(shift
);
1647 /* kernel-side HPT needed, but couldn't allocate one */
1648 error_setg_errno(errp
, errno
,
1649 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)",
1651 /* This is almost certainly fatal, but if the caller really
1652 * wants to carry on with shift == 0, it's welcome to try */
1653 } else if (rc
> 0) {
1654 /* kernel-side HPT allocated */
1657 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)",
1661 spapr
->htab_shift
= shift
;
1664 /* kernel-side HPT not needed, allocate in userspace instead */
1665 size_t size
= 1ULL << shift
;
1668 spapr
->htab
= qemu_memalign(size
, size
);
1670 error_setg_errno(errp
, errno
,
1671 "Could not allocate HPT of order %d", shift
);
1675 memset(spapr
->htab
, 0, size
);
1676 spapr
->htab_shift
= shift
;
1678 for (i
= 0; i
< size
/ HASH_PTE_SIZE_64
; i
++) {
1679 DIRTY_HPTE(HPTE(spapr
->htab
, i
));
1682 /* We're setting up a hash table, so that means we're not radix */
1683 spapr
->patb_entry
= 0;
1684 spapr_set_all_lpcrs(0, LPCR_HR
| LPCR_UPRT
);
1687 void spapr_setup_hpt_and_vrma(SpaprMachineState
*spapr
)
1691 if ((spapr
->resize_hpt
== SPAPR_RESIZE_HPT_DISABLED
)
1692 || (spapr
->cas_reboot
1693 && !spapr_ovec_test(spapr
->ov5_cas
, OV5_HPT_RESIZE
))) {
1694 hpt_shift
= spapr_hpt_shift_for_ramsize(MACHINE(spapr
)->maxram_size
);
1696 uint64_t current_ram_size
;
1698 current_ram_size
= MACHINE(spapr
)->ram_size
+ get_plugged_memory_size();
1699 hpt_shift
= spapr_hpt_shift_for_ramsize(current_ram_size
);
1701 spapr_reallocate_hpt(spapr
, hpt_shift
, &error_fatal
);
1703 if (spapr
->vrma_adjust
) {
1704 spapr
->rma_size
= kvmppc_rma_size(spapr_node0_size(MACHINE(spapr
)),
1709 static int spapr_reset_drcs(Object
*child
, void *opaque
)
1712 (SpaprDrc
*) object_dynamic_cast(child
,
1713 TYPE_SPAPR_DR_CONNECTOR
);
1716 spapr_drc_reset(drc
);
1722 static void spapr_machine_reset(MachineState
*machine
)
1724 SpaprMachineState
*spapr
= SPAPR_MACHINE(machine
);
1725 PowerPCCPU
*first_ppc_cpu
;
1726 uint32_t rtas_limit
;
1727 hwaddr rtas_addr
, fdt_addr
;
1731 spapr_caps_apply(spapr
);
1733 first_ppc_cpu
= POWERPC_CPU(first_cpu
);
1734 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() &&
1735 ppc_type_check_compat(machine
->cpu_type
, CPU_POWERPC_LOGICAL_3_00
, 0,
1736 spapr
->max_compat_pvr
)) {
1738 * If using KVM with radix mode available, VCPUs can be started
1739 * without a HPT because KVM will start them in radix mode.
1740 * Set the GR bit in PATE so that we know there is no HPT.
1742 spapr
->patb_entry
= PATE1_GR
;
1743 spapr_set_all_lpcrs(LPCR_HR
| LPCR_UPRT
, LPCR_HR
| LPCR_UPRT
);
1745 spapr_setup_hpt_and_vrma(spapr
);
1748 qemu_devices_reset();
1751 * If this reset wasn't generated by CAS, we should reset our
1752 * negotiated options and start from scratch
1754 if (!spapr
->cas_reboot
) {
1755 spapr_ovec_cleanup(spapr
->ov5_cas
);
1756 spapr
->ov5_cas
= spapr_ovec_new();
1758 ppc_set_compat_all(spapr
->max_compat_pvr
, &error_fatal
);
1762 * This is fixing some of the default configuration of the XIVE
1763 * devices. To be called after the reset of the machine devices.
1765 spapr_irq_reset(spapr
, &error_fatal
);
1768 * There is no CAS under qtest. Simulate one to please the code that
1769 * depends on spapr->ov5_cas. This is especially needed to test device
1770 * unplug, so we do that before resetting the DRCs.
1772 if (qtest_enabled()) {
1773 spapr_ovec_cleanup(spapr
->ov5_cas
);
1774 spapr
->ov5_cas
= spapr_ovec_clone(spapr
->ov5
);
1777 /* DRC reset may cause a device to be unplugged. This will cause troubles
1778 * if this device is used by another device (eg, a running vhost backend
1779 * will crash QEMU if the DIMM holding the vring goes away). To avoid such
1780 * situations, we reset DRCs after all devices have been reset.
1782 object_child_foreach_recursive(object_get_root(), spapr_reset_drcs
, NULL
);
1784 spapr_clear_pending_events(spapr
);
1787 * We place the device tree and RTAS just below either the top of the RMA,
1788 * or just below 2GB, whichever is lower, so that it can be
1789 * processed with 32-bit real mode code if necessary
1791 rtas_limit
= MIN(spapr
->rma_size
, RTAS_MAX_ADDR
);
1792 rtas_addr
= rtas_limit
- RTAS_MAX_SIZE
;
1793 fdt_addr
= rtas_addr
- FDT_MAX_SIZE
;
1795 fdt
= spapr_build_fdt(spapr
);
1797 spapr_load_rtas(spapr
, fdt
, rtas_addr
);
1801 /* Should only fail if we've built a corrupted tree */
1804 if (fdt_totalsize(fdt
) > FDT_MAX_SIZE
) {
1805 error_report("FDT too big ! 0x%x bytes (max is 0x%x)",
1806 fdt_totalsize(fdt
), FDT_MAX_SIZE
);
1811 qemu_fdt_dumpdtb(fdt
, fdt_totalsize(fdt
));
1812 cpu_physical_memory_write(fdt_addr
, fdt
, fdt_totalsize(fdt
));
1813 g_free(spapr
->fdt_blob
);
1814 spapr
->fdt_size
= fdt_totalsize(fdt
);
1815 spapr
->fdt_initial_size
= spapr
->fdt_size
;
1816 spapr
->fdt_blob
= fdt
;
1818 /* Set up the entry state */
1819 spapr_cpu_set_entry_state(first_ppc_cpu
, SPAPR_ENTRY_POINT
, fdt_addr
);
1820 first_ppc_cpu
->env
.gpr
[5] = 0;
1822 spapr
->cas_reboot
= false;
1825 static void spapr_create_nvram(SpaprMachineState
*spapr
)
1827 DeviceState
*dev
= qdev_create(&spapr
->vio_bus
->bus
, "spapr-nvram");
1828 DriveInfo
*dinfo
= drive_get(IF_PFLASH
, 0, 0);
1831 qdev_prop_set_drive(dev
, "drive", blk_by_legacy_dinfo(dinfo
),
1835 qdev_init_nofail(dev
);
1837 spapr
->nvram
= (struct SpaprNvram
*)dev
;
1840 static void spapr_rtc_create(SpaprMachineState
*spapr
)
1842 object_initialize_child(OBJECT(spapr
), "rtc",
1843 &spapr
->rtc
, sizeof(spapr
->rtc
), TYPE_SPAPR_RTC
,
1844 &error_fatal
, NULL
);
1845 object_property_set_bool(OBJECT(&spapr
->rtc
), true, "realized",
1847 object_property_add_alias(OBJECT(spapr
), "rtc-time", OBJECT(&spapr
->rtc
),
1848 "date", &error_fatal
);
1851 /* Returns whether we want to use VGA or not */
1852 static bool spapr_vga_init(PCIBus
*pci_bus
, Error
**errp
)
1854 switch (vga_interface_type
) {
1862 return pci_vga_init(pci_bus
) != NULL
;
1865 "Unsupported VGA mode, only -vga std or -vga virtio is supported");
1870 static int spapr_pre_load(void *opaque
)
1874 rc
= spapr_caps_pre_load(opaque
);
1882 static int spapr_post_load(void *opaque
, int version_id
)
1884 SpaprMachineState
*spapr
= (SpaprMachineState
*)opaque
;
1887 err
= spapr_caps_post_migration(spapr
);
1893 * In earlier versions, there was no separate qdev for the PAPR
1894 * RTC, so the RTC offset was stored directly in sPAPREnvironment.
1895 * So when migrating from those versions, poke the incoming offset
1896 * value into the RTC device
1898 if (version_id
< 3) {
1899 err
= spapr_rtc_import_offset(&spapr
->rtc
, spapr
->rtc_offset
);
1905 if (kvm_enabled() && spapr
->patb_entry
) {
1906 PowerPCCPU
*cpu
= POWERPC_CPU(first_cpu
);
1907 bool radix
= !!(spapr
->patb_entry
& PATE1_GR
);
1908 bool gtse
= !!(cpu
->env
.spr
[SPR_LPCR
] & LPCR_GTSE
);
1911 * Update LPCR:HR and UPRT as they may not be set properly in
1914 spapr_set_all_lpcrs(radix
? (LPCR_HR
| LPCR_UPRT
) : 0,
1915 LPCR_HR
| LPCR_UPRT
);
1917 err
= kvmppc_configure_v3_mmu(cpu
, radix
, gtse
, spapr
->patb_entry
);
1919 error_report("Process table config unsupported by the host");
1924 err
= spapr_irq_post_load(spapr
, version_id
);
1932 static int spapr_pre_save(void *opaque
)
1936 rc
= spapr_caps_pre_save(opaque
);
1944 static bool version_before_3(void *opaque
, int version_id
)
1946 return version_id
< 3;
1949 static bool spapr_pending_events_needed(void *opaque
)
1951 SpaprMachineState
*spapr
= (SpaprMachineState
*)opaque
;
1952 return !QTAILQ_EMPTY(&spapr
->pending_events
);
1955 static const VMStateDescription vmstate_spapr_event_entry
= {
1956 .name
= "spapr_event_log_entry",
1958 .minimum_version_id
= 1,
1959 .fields
= (VMStateField
[]) {
1960 VMSTATE_UINT32(summary
, SpaprEventLogEntry
),
1961 VMSTATE_UINT32(extended_length
, SpaprEventLogEntry
),
1962 VMSTATE_VBUFFER_ALLOC_UINT32(extended_log
, SpaprEventLogEntry
, 0,
1963 NULL
, extended_length
),
1964 VMSTATE_END_OF_LIST()
1968 static const VMStateDescription vmstate_spapr_pending_events
= {
1969 .name
= "spapr_pending_events",
1971 .minimum_version_id
= 1,
1972 .needed
= spapr_pending_events_needed
,
1973 .fields
= (VMStateField
[]) {
1974 VMSTATE_QTAILQ_V(pending_events
, SpaprMachineState
, 1,
1975 vmstate_spapr_event_entry
, SpaprEventLogEntry
, next
),
1976 VMSTATE_END_OF_LIST()
1980 static bool spapr_ov5_cas_needed(void *opaque
)
1982 SpaprMachineState
*spapr
= opaque
;
1983 SpaprOptionVector
*ov5_mask
= spapr_ovec_new();
1984 SpaprOptionVector
*ov5_legacy
= spapr_ovec_new();
1985 SpaprOptionVector
*ov5_removed
= spapr_ovec_new();
1988 /* Prior to the introduction of SpaprOptionVector, we had two option
1989 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY.
1990 * Both of these options encode machine topology into the device-tree
1991 * in such a way that the now-booted OS should still be able to interact
1992 * appropriately with QEMU regardless of what options were actually
1993 * negotiatied on the source side.
1995 * As such, we can avoid migrating the CAS-negotiated options if these
1996 * are the only options available on the current machine/platform.
1997 * Since these are the only options available for pseries-2.7 and
1998 * earlier, this allows us to maintain old->new/new->old migration
2001 * For QEMU 2.8+, there are additional CAS-negotiatable options available
2002 * via default pseries-2.8 machines and explicit command-line parameters.
2003 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware
2004 * of the actual CAS-negotiated values to continue working properly. For
2005 * example, availability of memory unplug depends on knowing whether
2006 * OV5_HP_EVT was negotiated via CAS.
2008 * Thus, for any cases where the set of available CAS-negotiatable
2009 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we
2010 * include the CAS-negotiated options in the migration stream, unless
2011 * if they affect boot time behaviour only.
2013 spapr_ovec_set(ov5_mask
, OV5_FORM1_AFFINITY
);
2014 spapr_ovec_set(ov5_mask
, OV5_DRCONF_MEMORY
);
2015 spapr_ovec_set(ov5_mask
, OV5_DRMEM_V2
);
2017 /* spapr_ovec_diff returns true if bits were removed. we avoid using
2018 * the mask itself since in the future it's possible "legacy" bits may be
2019 * removed via machine options, which could generate a false positive
2020 * that breaks migration.
2022 spapr_ovec_intersect(ov5_legacy
, spapr
->ov5
, ov5_mask
);
2023 cas_needed
= spapr_ovec_diff(ov5_removed
, spapr
->ov5
, ov5_legacy
);
2025 spapr_ovec_cleanup(ov5_mask
);
2026 spapr_ovec_cleanup(ov5_legacy
);
2027 spapr_ovec_cleanup(ov5_removed
);
2032 static const VMStateDescription vmstate_spapr_ov5_cas
= {
2033 .name
= "spapr_option_vector_ov5_cas",
2035 .minimum_version_id
= 1,
2036 .needed
= spapr_ov5_cas_needed
,
2037 .fields
= (VMStateField
[]) {
2038 VMSTATE_STRUCT_POINTER_V(ov5_cas
, SpaprMachineState
, 1,
2039 vmstate_spapr_ovec
, SpaprOptionVector
),
2040 VMSTATE_END_OF_LIST()
2044 static bool spapr_patb_entry_needed(void *opaque
)
2046 SpaprMachineState
*spapr
= opaque
;
2048 return !!spapr
->patb_entry
;
2051 static const VMStateDescription vmstate_spapr_patb_entry
= {
2052 .name
= "spapr_patb_entry",
2054 .minimum_version_id
= 1,
2055 .needed
= spapr_patb_entry_needed
,
2056 .fields
= (VMStateField
[]) {
2057 VMSTATE_UINT64(patb_entry
, SpaprMachineState
),
2058 VMSTATE_END_OF_LIST()
2062 static bool spapr_irq_map_needed(void *opaque
)
2064 SpaprMachineState
*spapr
= opaque
;
2066 return spapr
->irq_map
&& !bitmap_empty(spapr
->irq_map
, spapr
->irq_map_nr
);
2069 static const VMStateDescription vmstate_spapr_irq_map
= {
2070 .name
= "spapr_irq_map",
2072 .minimum_version_id
= 1,
2073 .needed
= spapr_irq_map_needed
,
2074 .fields
= (VMStateField
[]) {
2075 VMSTATE_BITMAP(irq_map
, SpaprMachineState
, 0, irq_map_nr
),
2076 VMSTATE_END_OF_LIST()
2080 static bool spapr_dtb_needed(void *opaque
)
2082 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(opaque
);
2084 return smc
->update_dt_enabled
;
2087 static int spapr_dtb_pre_load(void *opaque
)
2089 SpaprMachineState
*spapr
= (SpaprMachineState
*)opaque
;
2091 g_free(spapr
->fdt_blob
);
2092 spapr
->fdt_blob
= NULL
;
2093 spapr
->fdt_size
= 0;
2098 static const VMStateDescription vmstate_spapr_dtb
= {
2099 .name
= "spapr_dtb",
2101 .minimum_version_id
= 1,
2102 .needed
= spapr_dtb_needed
,
2103 .pre_load
= spapr_dtb_pre_load
,
2104 .fields
= (VMStateField
[]) {
2105 VMSTATE_UINT32(fdt_initial_size
, SpaprMachineState
),
2106 VMSTATE_UINT32(fdt_size
, SpaprMachineState
),
2107 VMSTATE_VBUFFER_ALLOC_UINT32(fdt_blob
, SpaprMachineState
, 0, NULL
,
2109 VMSTATE_END_OF_LIST()
2113 static const VMStateDescription vmstate_spapr
= {
2116 .minimum_version_id
= 1,
2117 .pre_load
= spapr_pre_load
,
2118 .post_load
= spapr_post_load
,
2119 .pre_save
= spapr_pre_save
,
2120 .fields
= (VMStateField
[]) {
2121 /* used to be @next_irq */
2122 VMSTATE_UNUSED_BUFFER(version_before_3
, 0, 4),
2125 VMSTATE_UINT64_TEST(rtc_offset
, SpaprMachineState
, version_before_3
),
2127 VMSTATE_PPC_TIMEBASE_V(tb
, SpaprMachineState
, 2),
2128 VMSTATE_END_OF_LIST()
2130 .subsections
= (const VMStateDescription
*[]) {
2131 &vmstate_spapr_ov5_cas
,
2132 &vmstate_spapr_patb_entry
,
2133 &vmstate_spapr_pending_events
,
2134 &vmstate_spapr_cap_htm
,
2135 &vmstate_spapr_cap_vsx
,
2136 &vmstate_spapr_cap_dfp
,
2137 &vmstate_spapr_cap_cfpc
,
2138 &vmstate_spapr_cap_sbbc
,
2139 &vmstate_spapr_cap_ibs
,
2140 &vmstate_spapr_cap_hpt_maxpagesize
,
2141 &vmstate_spapr_irq_map
,
2142 &vmstate_spapr_cap_nested_kvm_hv
,
2144 &vmstate_spapr_cap_large_decr
,
2145 &vmstate_spapr_cap_ccf_assist
,
2150 static int htab_save_setup(QEMUFile
*f
, void *opaque
)
2152 SpaprMachineState
*spapr
= opaque
;
2154 /* "Iteration" header */
2155 if (!spapr
->htab_shift
) {
2156 qemu_put_be32(f
, -1);
2158 qemu_put_be32(f
, spapr
->htab_shift
);
2162 spapr
->htab_save_index
= 0;
2163 spapr
->htab_first_pass
= true;
2165 if (spapr
->htab_shift
) {
2166 assert(kvm_enabled());
2174 static void htab_save_chunk(QEMUFile
*f
, SpaprMachineState
*spapr
,
2175 int chunkstart
, int n_valid
, int n_invalid
)
2177 qemu_put_be32(f
, chunkstart
);
2178 qemu_put_be16(f
, n_valid
);
2179 qemu_put_be16(f
, n_invalid
);
2180 qemu_put_buffer(f
, HPTE(spapr
->htab
, chunkstart
),
2181 HASH_PTE_SIZE_64
* n_valid
);
2184 static void htab_save_end_marker(QEMUFile
*f
)
2186 qemu_put_be32(f
, 0);
2187 qemu_put_be16(f
, 0);
2188 qemu_put_be16(f
, 0);
2191 static void htab_save_first_pass(QEMUFile
*f
, SpaprMachineState
*spapr
,
2194 bool has_timeout
= max_ns
!= -1;
2195 int htabslots
= HTAB_SIZE(spapr
) / HASH_PTE_SIZE_64
;
2196 int index
= spapr
->htab_save_index
;
2197 int64_t starttime
= qemu_clock_get_ns(QEMU_CLOCK_REALTIME
);
2199 assert(spapr
->htab_first_pass
);
2204 /* Consume invalid HPTEs */
2205 while ((index
< htabslots
)
2206 && !HPTE_VALID(HPTE(spapr
->htab
, index
))) {
2207 CLEAN_HPTE(HPTE(spapr
->htab
, index
));
2211 /* Consume valid HPTEs */
2213 while ((index
< htabslots
) && (index
- chunkstart
< USHRT_MAX
)
2214 && HPTE_VALID(HPTE(spapr
->htab
, index
))) {
2215 CLEAN_HPTE(HPTE(spapr
->htab
, index
));
2219 if (index
> chunkstart
) {
2220 int n_valid
= index
- chunkstart
;
2222 htab_save_chunk(f
, spapr
, chunkstart
, n_valid
, 0);
2225 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME
) - starttime
) > max_ns
) {
2229 } while ((index
< htabslots
) && !qemu_file_rate_limit(f
));
2231 if (index
>= htabslots
) {
2232 assert(index
== htabslots
);
2234 spapr
->htab_first_pass
= false;
2236 spapr
->htab_save_index
= index
;
2239 static int htab_save_later_pass(QEMUFile
*f
, SpaprMachineState
*spapr
,
2242 bool final
= max_ns
< 0;
2243 int htabslots
= HTAB_SIZE(spapr
) / HASH_PTE_SIZE_64
;
2244 int examined
= 0, sent
= 0;
2245 int index
= spapr
->htab_save_index
;
2246 int64_t starttime
= qemu_clock_get_ns(QEMU_CLOCK_REALTIME
);
2248 assert(!spapr
->htab_first_pass
);
2251 int chunkstart
, invalidstart
;
2253 /* Consume non-dirty HPTEs */
2254 while ((index
< htabslots
)
2255 && !HPTE_DIRTY(HPTE(spapr
->htab
, index
))) {
2261 /* Consume valid dirty HPTEs */
2262 while ((index
< htabslots
) && (index
- chunkstart
< USHRT_MAX
)
2263 && HPTE_DIRTY(HPTE(spapr
->htab
, index
))
2264 && HPTE_VALID(HPTE(spapr
->htab
, index
))) {
2265 CLEAN_HPTE(HPTE(spapr
->htab
, index
));
2270 invalidstart
= index
;
2271 /* Consume invalid dirty HPTEs */
2272 while ((index
< htabslots
) && (index
- invalidstart
< USHRT_MAX
)
2273 && HPTE_DIRTY(HPTE(spapr
->htab
, index
))
2274 && !HPTE_VALID(HPTE(spapr
->htab
, index
))) {
2275 CLEAN_HPTE(HPTE(spapr
->htab
, index
));
2280 if (index
> chunkstart
) {
2281 int n_valid
= invalidstart
- chunkstart
;
2282 int n_invalid
= index
- invalidstart
;
2284 htab_save_chunk(f
, spapr
, chunkstart
, n_valid
, n_invalid
);
2285 sent
+= index
- chunkstart
;
2287 if (!final
&& (qemu_clock_get_ns(QEMU_CLOCK_REALTIME
) - starttime
) > max_ns
) {
2292 if (examined
>= htabslots
) {
2296 if (index
>= htabslots
) {
2297 assert(index
== htabslots
);
2300 } while ((examined
< htabslots
) && (!qemu_file_rate_limit(f
) || final
));
2302 if (index
>= htabslots
) {
2303 assert(index
== htabslots
);
2307 spapr
->htab_save_index
= index
;
2309 return (examined
>= htabslots
) && (sent
== 0) ? 1 : 0;
2312 #define MAX_ITERATION_NS 5000000 /* 5 ms */
2313 #define MAX_KVM_BUF_SIZE 2048
2315 static int htab_save_iterate(QEMUFile
*f
, void *opaque
)
2317 SpaprMachineState
*spapr
= opaque
;
2321 /* Iteration header */
2322 if (!spapr
->htab_shift
) {
2323 qemu_put_be32(f
, -1);
2326 qemu_put_be32(f
, 0);
2330 assert(kvm_enabled());
2332 fd
= get_htab_fd(spapr
);
2337 rc
= kvmppc_save_htab(f
, fd
, MAX_KVM_BUF_SIZE
, MAX_ITERATION_NS
);
2341 } else if (spapr
->htab_first_pass
) {
2342 htab_save_first_pass(f
, spapr
, MAX_ITERATION_NS
);
2344 rc
= htab_save_later_pass(f
, spapr
, MAX_ITERATION_NS
);
2347 htab_save_end_marker(f
);
2352 static int htab_save_complete(QEMUFile
*f
, void *opaque
)
2354 SpaprMachineState
*spapr
= opaque
;
2357 /* Iteration header */
2358 if (!spapr
->htab_shift
) {
2359 qemu_put_be32(f
, -1);
2362 qemu_put_be32(f
, 0);
2368 assert(kvm_enabled());
2370 fd
= get_htab_fd(spapr
);
2375 rc
= kvmppc_save_htab(f
, fd
, MAX_KVM_BUF_SIZE
, -1);
2380 if (spapr
->htab_first_pass
) {
2381 htab_save_first_pass(f
, spapr
, -1);
2383 htab_save_later_pass(f
, spapr
, -1);
2387 htab_save_end_marker(f
);
2392 static int htab_load(QEMUFile
*f
, void *opaque
, int version_id
)
2394 SpaprMachineState
*spapr
= opaque
;
2395 uint32_t section_hdr
;
2397 Error
*local_err
= NULL
;
2399 if (version_id
< 1 || version_id
> 1) {
2400 error_report("htab_load() bad version");
2404 section_hdr
= qemu_get_be32(f
);
2406 if (section_hdr
== -1) {
2407 spapr_free_hpt(spapr
);
2412 /* First section gives the htab size */
2413 spapr_reallocate_hpt(spapr
, section_hdr
, &local_err
);
2415 error_report_err(local_err
);
2422 assert(kvm_enabled());
2424 fd
= kvmppc_get_htab_fd(true, 0, &local_err
);
2426 error_report_err(local_err
);
2433 uint16_t n_valid
, n_invalid
;
2435 index
= qemu_get_be32(f
);
2436 n_valid
= qemu_get_be16(f
);
2437 n_invalid
= qemu_get_be16(f
);
2439 if ((index
== 0) && (n_valid
== 0) && (n_invalid
== 0)) {
2444 if ((index
+ n_valid
+ n_invalid
) >
2445 (HTAB_SIZE(spapr
) / HASH_PTE_SIZE_64
)) {
2446 /* Bad index in stream */
2448 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)",
2449 index
, n_valid
, n_invalid
, spapr
->htab_shift
);
2455 qemu_get_buffer(f
, HPTE(spapr
->htab
, index
),
2456 HASH_PTE_SIZE_64
* n_valid
);
2459 memset(HPTE(spapr
->htab
, index
+ n_valid
), 0,
2460 HASH_PTE_SIZE_64
* n_invalid
);
2467 rc
= kvmppc_load_htab_chunk(f
, fd
, index
, n_valid
, n_invalid
);
2482 static void htab_save_cleanup(void *opaque
)
2484 SpaprMachineState
*spapr
= opaque
;
2486 close_htab_fd(spapr
);
2489 static SaveVMHandlers savevm_htab_handlers
= {
2490 .save_setup
= htab_save_setup
,
2491 .save_live_iterate
= htab_save_iterate
,
2492 .save_live_complete_precopy
= htab_save_complete
,
2493 .save_cleanup
= htab_save_cleanup
,
2494 .load_state
= htab_load
,
2497 static void spapr_boot_set(void *opaque
, const char *boot_device
,
2500 MachineState
*machine
= MACHINE(opaque
);
2501 machine
->boot_order
= g_strdup(boot_device
);
2504 static void spapr_create_lmb_dr_connectors(SpaprMachineState
*spapr
)
2506 MachineState
*machine
= MACHINE(spapr
);
2507 uint64_t lmb_size
= SPAPR_MEMORY_BLOCK_SIZE
;
2508 uint32_t nr_lmbs
= (machine
->maxram_size
- machine
->ram_size
)/lmb_size
;
2511 for (i
= 0; i
< nr_lmbs
; i
++) {
2514 addr
= i
* lmb_size
+ machine
->device_memory
->base
;
2515 spapr_dr_connector_new(OBJECT(spapr
), TYPE_SPAPR_DRC_LMB
,
2521 * If RAM size, maxmem size and individual node mem sizes aren't aligned
2522 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest
2523 * since we can't support such unaligned sizes with DRCONF_MEMORY.
2525 static void spapr_validate_node_memory(MachineState
*machine
, Error
**errp
)
2529 if (machine
->ram_size
% SPAPR_MEMORY_BLOCK_SIZE
) {
2530 error_setg(errp
, "Memory size 0x" RAM_ADDR_FMT
2531 " is not aligned to %" PRIu64
" MiB",
2533 SPAPR_MEMORY_BLOCK_SIZE
/ MiB
);
2537 if (machine
->maxram_size
% SPAPR_MEMORY_BLOCK_SIZE
) {
2538 error_setg(errp
, "Maximum memory size 0x" RAM_ADDR_FMT
2539 " is not aligned to %" PRIu64
" MiB",
2541 SPAPR_MEMORY_BLOCK_SIZE
/ MiB
);
2545 for (i
= 0; i
< machine
->numa_state
->num_nodes
; i
++) {
2546 if (machine
->numa_state
->nodes
[i
].node_mem
% SPAPR_MEMORY_BLOCK_SIZE
) {
2548 "Node %d memory size 0x%" PRIx64
2549 " is not aligned to %" PRIu64
" MiB",
2550 i
, machine
->numa_state
->nodes
[i
].node_mem
,
2551 SPAPR_MEMORY_BLOCK_SIZE
/ MiB
);
2557 /* find cpu slot in machine->possible_cpus by core_id */
2558 static CPUArchId
*spapr_find_cpu_slot(MachineState
*ms
, uint32_t id
, int *idx
)
2560 int index
= id
/ ms
->smp
.threads
;
2562 if (index
>= ms
->possible_cpus
->len
) {
2568 return &ms
->possible_cpus
->cpus
[index
];
2571 static void spapr_set_vsmt_mode(SpaprMachineState
*spapr
, Error
**errp
)
2573 MachineState
*ms
= MACHINE(spapr
);
2574 Error
*local_err
= NULL
;
2575 bool vsmt_user
= !!spapr
->vsmt
;
2576 int kvm_smt
= kvmppc_smt_threads();
2578 unsigned int smp_threads
= ms
->smp
.threads
;
2580 if (!kvm_enabled() && (smp_threads
> 1)) {
2581 error_setg(&local_err
, "TCG cannot support more than 1 thread/core "
2582 "on a pseries machine");
2585 if (!is_power_of_2(smp_threads
)) {
2586 error_setg(&local_err
, "Cannot support %d threads/core on a pseries "
2587 "machine because it must be a power of 2", smp_threads
);
2591 /* Detemine the VSMT mode to use: */
2593 if (spapr
->vsmt
< smp_threads
) {
2594 error_setg(&local_err
, "Cannot support VSMT mode %d"
2595 " because it must be >= threads/core (%d)",
2596 spapr
->vsmt
, smp_threads
);
2599 /* In this case, spapr->vsmt has been set by the command line */
2602 * Default VSMT value is tricky, because we need it to be as
2603 * consistent as possible (for migration), but this requires
2604 * changing it for at least some existing cases. We pick 8 as
2605 * the value that we'd get with KVM on POWER8, the
2606 * overwhelmingly common case in production systems.
2608 spapr
->vsmt
= MAX(8, smp_threads
);
2611 /* KVM: If necessary, set the SMT mode: */
2612 if (kvm_enabled() && (spapr
->vsmt
!= kvm_smt
)) {
2613 ret
= kvmppc_set_smt_threads(spapr
->vsmt
);
2615 /* Looks like KVM isn't able to change VSMT mode */
2616 error_setg(&local_err
,
2617 "Failed to set KVM's VSMT mode to %d (errno %d)",
2619 /* We can live with that if the default one is big enough
2620 * for the number of threads, and a submultiple of the one
2621 * we want. In this case we'll waste some vcpu ids, but
2622 * behaviour will be correct */
2623 if ((kvm_smt
>= smp_threads
) && ((spapr
->vsmt
% kvm_smt
) == 0)) {
2624 warn_report_err(local_err
);
2629 error_append_hint(&local_err
,
2630 "On PPC, a VM with %d threads/core"
2631 " on a host with %d threads/core"
2632 " requires the use of VSMT mode %d.\n",
2633 smp_threads
, kvm_smt
, spapr
->vsmt
);
2635 kvmppc_hint_smt_possible(&local_err
);
2640 /* else TCG: nothing to do currently */
2642 error_propagate(errp
, local_err
);
2645 static void spapr_init_cpus(SpaprMachineState
*spapr
)
2647 MachineState
*machine
= MACHINE(spapr
);
2648 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
2649 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(machine
);
2650 const char *type
= spapr_get_cpu_core_type(machine
->cpu_type
);
2651 const CPUArchIdList
*possible_cpus
;
2652 unsigned int smp_cpus
= machine
->smp
.cpus
;
2653 unsigned int smp_threads
= machine
->smp
.threads
;
2654 unsigned int max_cpus
= machine
->smp
.max_cpus
;
2655 int boot_cores_nr
= smp_cpus
/ smp_threads
;
2658 possible_cpus
= mc
->possible_cpu_arch_ids(machine
);
2659 if (mc
->has_hotpluggable_cpus
) {
2660 if (smp_cpus
% smp_threads
) {
2661 error_report("smp_cpus (%u) must be multiple of threads (%u)",
2662 smp_cpus
, smp_threads
);
2665 if (max_cpus
% smp_threads
) {
2666 error_report("max_cpus (%u) must be multiple of threads (%u)",
2667 max_cpus
, smp_threads
);
2671 if (max_cpus
!= smp_cpus
) {
2672 error_report("This machine version does not support CPU hotplug");
2675 boot_cores_nr
= possible_cpus
->len
;
2678 if (smc
->pre_2_10_has_unused_icps
) {
2681 for (i
= 0; i
< spapr_max_server_number(spapr
); i
++) {
2682 /* Dummy entries get deregistered when real ICPState objects
2683 * are registered during CPU core hotplug.
2685 pre_2_10_vmstate_register_dummy_icp(i
);
2689 for (i
= 0; i
< possible_cpus
->len
; i
++) {
2690 int core_id
= i
* smp_threads
;
2692 if (mc
->has_hotpluggable_cpus
) {
2693 spapr_dr_connector_new(OBJECT(spapr
), TYPE_SPAPR_DRC_CPU
,
2694 spapr_vcpu_id(spapr
, core_id
));
2697 if (i
< boot_cores_nr
) {
2698 Object
*core
= object_new(type
);
2699 int nr_threads
= smp_threads
;
2701 /* Handle the partially filled core for older machine types */
2702 if ((i
+ 1) * smp_threads
>= smp_cpus
) {
2703 nr_threads
= smp_cpus
- i
* smp_threads
;
2706 object_property_set_int(core
, nr_threads
, "nr-threads",
2708 object_property_set_int(core
, core_id
, CPU_CORE_PROP_CORE_ID
,
2710 object_property_set_bool(core
, true, "realized", &error_fatal
);
2717 static PCIHostState
*spapr_create_default_phb(void)
2721 dev
= qdev_create(NULL
, TYPE_SPAPR_PCI_HOST_BRIDGE
);
2722 qdev_prop_set_uint32(dev
, "index", 0);
2723 qdev_init_nofail(dev
);
2725 return PCI_HOST_BRIDGE(dev
);
2728 /* pSeries LPAR / sPAPR hardware init */
2729 static void spapr_machine_init(MachineState
*machine
)
2731 SpaprMachineState
*spapr
= SPAPR_MACHINE(machine
);
2732 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(machine
);
2733 const char *kernel_filename
= machine
->kernel_filename
;
2734 const char *initrd_filename
= machine
->initrd_filename
;
2737 MemoryRegion
*sysmem
= get_system_memory();
2738 MemoryRegion
*ram
= g_new(MemoryRegion
, 1);
2739 hwaddr node0_size
= spapr_node0_size(machine
);
2740 long load_limit
, fw_size
;
2742 Error
*resize_hpt_err
= NULL
;
2744 msi_nonbroken
= true;
2746 QLIST_INIT(&spapr
->phbs
);
2747 QTAILQ_INIT(&spapr
->pending_dimm_unplugs
);
2749 /* Determine capabilities to run with */
2750 spapr_caps_init(spapr
);
2752 kvmppc_check_papr_resize_hpt(&resize_hpt_err
);
2753 if (spapr
->resize_hpt
== SPAPR_RESIZE_HPT_DEFAULT
) {
2755 * If the user explicitly requested a mode we should either
2756 * supply it, or fail completely (which we do below). But if
2757 * it's not set explicitly, we reset our mode to something
2760 if (resize_hpt_err
) {
2761 spapr
->resize_hpt
= SPAPR_RESIZE_HPT_DISABLED
;
2762 error_free(resize_hpt_err
);
2763 resize_hpt_err
= NULL
;
2765 spapr
->resize_hpt
= smc
->resize_hpt_default
;
2769 assert(spapr
->resize_hpt
!= SPAPR_RESIZE_HPT_DEFAULT
);
2771 if ((spapr
->resize_hpt
!= SPAPR_RESIZE_HPT_DISABLED
) && resize_hpt_err
) {
2773 * User requested HPT resize, but this host can't supply it. Bail out
2775 error_report_err(resize_hpt_err
);
2779 spapr
->rma_size
= node0_size
;
2781 /* With KVM, we don't actually know whether KVM supports an
2782 * unbounded RMA (PR KVM) or is limited by the hash table size
2783 * (HV KVM using VRMA), so we always assume the latter
2785 * In that case, we also limit the initial allocations for RTAS
2786 * etc... to 256M since we have no way to know what the VRMA size
2787 * is going to be as it depends on the size of the hash table
2788 * which isn't determined yet.
2790 if (kvm_enabled()) {
2791 spapr
->vrma_adjust
= 1;
2792 spapr
->rma_size
= MIN(spapr
->rma_size
, 0x10000000);
2795 /* Actually we don't support unbounded RMA anymore since we added
2796 * proper emulation of HV mode. The max we can get is 16G which
2797 * also happens to be what we configure for PAPR mode so make sure
2798 * we don't do anything bigger than that
2800 spapr
->rma_size
= MIN(spapr
->rma_size
, 0x400000000ull
);
2802 if (spapr
->rma_size
> node0_size
) {
2803 error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx
")",
2808 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */
2809 load_limit
= MIN(spapr
->rma_size
, RTAS_MAX_ADDR
) - FW_OVERHEAD
;
2812 * VSMT must be set in order to be able to compute VCPU ids, ie to
2813 * call spapr_max_server_number() or spapr_vcpu_id().
2815 spapr_set_vsmt_mode(spapr
, &error_fatal
);
2817 /* Set up Interrupt Controller before we create the VCPUs */
2818 spapr_irq_init(spapr
, &error_fatal
);
2820 /* Set up containers for ibm,client-architecture-support negotiated options
2822 spapr
->ov5
= spapr_ovec_new();
2823 spapr
->ov5_cas
= spapr_ovec_new();
2825 if (smc
->dr_lmb_enabled
) {
2826 spapr_ovec_set(spapr
->ov5
, OV5_DRCONF_MEMORY
);
2827 spapr_validate_node_memory(machine
, &error_fatal
);
2830 spapr_ovec_set(spapr
->ov5
, OV5_FORM1_AFFINITY
);
2832 /* advertise support for dedicated HP event source to guests */
2833 if (spapr
->use_hotplug_event_source
) {
2834 spapr_ovec_set(spapr
->ov5
, OV5_HP_EVT
);
2837 /* advertise support for HPT resizing */
2838 if (spapr
->resize_hpt
!= SPAPR_RESIZE_HPT_DISABLED
) {
2839 spapr_ovec_set(spapr
->ov5
, OV5_HPT_RESIZE
);
2842 /* advertise support for ibm,dyamic-memory-v2 */
2843 spapr_ovec_set(spapr
->ov5
, OV5_DRMEM_V2
);
2845 /* advertise XIVE on POWER9 machines */
2846 if (spapr
->irq
->ov5
& (SPAPR_OV5_XIVE_EXPLOIT
| SPAPR_OV5_XIVE_BOTH
)) {
2847 spapr_ovec_set(spapr
->ov5
, OV5_XIVE_EXPLOIT
);
2851 spapr_init_cpus(spapr
);
2854 * check we don't have a memory-less/cpu-less NUMA node
2855 * Firmware relies on the existing memory/cpu topology to provide the
2856 * NUMA topology to the kernel.
2857 * And the linux kernel needs to know the NUMA topology at start
2858 * to be able to hotplug CPUs later.
2860 if (machine
->numa_state
->num_nodes
) {
2861 for (i
= 0; i
< machine
->numa_state
->num_nodes
; ++i
) {
2862 /* check for memory-less node */
2863 if (machine
->numa_state
->nodes
[i
].node_mem
== 0) {
2866 /* check for cpu-less node */
2868 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
2869 if (cpu
->node_id
== i
) {
2874 /* memory-less and cpu-less node */
2877 "Memory-less/cpu-less nodes are not supported (node %d)",
2887 * NVLink2-connected GPU RAM needs to be placed on a separate NUMA node.
2888 * We assign a new numa ID per GPU in spapr_pci_collect_nvgpu() which is
2889 * called from vPHB reset handler so we initialize the counter here.
2890 * If no NUMA is configured from the QEMU side, we start from 1 as GPU RAM
2891 * must be equally distant from any other node.
2892 * The final value of spapr->gpu_numa_id is going to be written to
2893 * max-associativity-domains in spapr_build_fdt().
2895 spapr
->gpu_numa_id
= MAX(1, machine
->numa_state
->num_nodes
);
2897 if ((!kvm_enabled() || kvmppc_has_cap_mmu_radix()) &&
2898 ppc_type_check_compat(machine
->cpu_type
, CPU_POWERPC_LOGICAL_3_00
, 0,
2899 spapr
->max_compat_pvr
)) {
2900 /* KVM and TCG always allow GTSE with radix... */
2901 spapr_ovec_set(spapr
->ov5
, OV5_MMU_RADIX_GTSE
);
2903 /* ... but not with hash (currently). */
2905 if (kvm_enabled()) {
2906 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */
2907 kvmppc_enable_logical_ci_hcalls();
2908 kvmppc_enable_set_mode_hcall();
2910 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */
2911 kvmppc_enable_clear_ref_mod_hcalls();
2913 /* Enable H_PAGE_INIT */
2914 kvmppc_enable_h_page_init();
2918 memory_region_allocate_system_memory(ram
, NULL
, "ppc_spapr.ram",
2920 memory_region_add_subregion(sysmem
, 0, ram
);
2922 /* always allocate the device memory information */
2923 machine
->device_memory
= g_malloc0(sizeof(*machine
->device_memory
));
2925 /* initialize hotplug memory address space */
2926 if (machine
->ram_size
< machine
->maxram_size
) {
2927 ram_addr_t device_mem_size
= machine
->maxram_size
- machine
->ram_size
;
2929 * Limit the number of hotpluggable memory slots to half the number
2930 * slots that KVM supports, leaving the other half for PCI and other
2931 * devices. However ensure that number of slots doesn't drop below 32.
2933 int max_memslots
= kvm_enabled() ? kvm_get_max_memslots() / 2 :
2934 SPAPR_MAX_RAM_SLOTS
;
2936 if (max_memslots
< SPAPR_MAX_RAM_SLOTS
) {
2937 max_memslots
= SPAPR_MAX_RAM_SLOTS
;
2939 if (machine
->ram_slots
> max_memslots
) {
2940 error_report("Specified number of memory slots %"
2941 PRIu64
" exceeds max supported %d",
2942 machine
->ram_slots
, max_memslots
);
2946 machine
->device_memory
->base
= ROUND_UP(machine
->ram_size
,
2947 SPAPR_DEVICE_MEM_ALIGN
);
2948 memory_region_init(&machine
->device_memory
->mr
, OBJECT(spapr
),
2949 "device-memory", device_mem_size
);
2950 memory_region_add_subregion(sysmem
, machine
->device_memory
->base
,
2951 &machine
->device_memory
->mr
);
2954 if (smc
->dr_lmb_enabled
) {
2955 spapr_create_lmb_dr_connectors(spapr
);
2958 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, "spapr-rtas.bin");
2960 error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin");
2963 spapr
->rtas_size
= get_image_size(filename
);
2964 if (spapr
->rtas_size
< 0) {
2965 error_report("Could not get size of LPAR rtas '%s'", filename
);
2968 spapr
->rtas_blob
= g_malloc(spapr
->rtas_size
);
2969 if (load_image_size(filename
, spapr
->rtas_blob
, spapr
->rtas_size
) < 0) {
2970 error_report("Could not load LPAR rtas '%s'", filename
);
2973 if (spapr
->rtas_size
> RTAS_MAX_SIZE
) {
2974 error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)",
2975 (size_t)spapr
->rtas_size
, RTAS_MAX_SIZE
);
2980 /* Set up RTAS event infrastructure */
2981 spapr_events_init(spapr
);
2983 /* Set up the RTC RTAS interfaces */
2984 spapr_rtc_create(spapr
);
2986 /* Set up VIO bus */
2987 spapr
->vio_bus
= spapr_vio_bus_init();
2989 for (i
= 0; i
< serial_max_hds(); i
++) {
2991 spapr_vty_create(spapr
->vio_bus
, serial_hd(i
));
2995 /* We always have at least the nvram device on VIO */
2996 spapr_create_nvram(spapr
);
2999 * Setup hotplug / dynamic-reconfiguration connectors. top-level
3000 * connectors (described in root DT node's "ibm,drc-types" property)
3001 * are pre-initialized here. additional child connectors (such as
3002 * connectors for a PHBs PCI slots) are added as needed during their
3003 * parent's realization.
3005 if (smc
->dr_phb_enabled
) {
3006 for (i
= 0; i
< SPAPR_MAX_PHBS
; i
++) {
3007 spapr_dr_connector_new(OBJECT(machine
), TYPE_SPAPR_DRC_PHB
, i
);
3012 spapr_pci_rtas_init();
3014 phb
= spapr_create_default_phb();
3016 for (i
= 0; i
< nb_nics
; i
++) {
3017 NICInfo
*nd
= &nd_table
[i
];
3020 nd
->model
= g_strdup("spapr-vlan");
3023 if (g_str_equal(nd
->model
, "spapr-vlan") ||
3024 g_str_equal(nd
->model
, "ibmveth")) {
3025 spapr_vlan_create(spapr
->vio_bus
, nd
);
3027 pci_nic_init_nofail(&nd_table
[i
], phb
->bus
, nd
->model
, NULL
);
3031 for (i
= 0; i
<= drive_get_max_bus(IF_SCSI
); i
++) {
3032 spapr_vscsi_create(spapr
->vio_bus
);
3036 if (spapr_vga_init(phb
->bus
, &error_fatal
)) {
3037 spapr
->has_graphics
= true;
3038 machine
->usb
|= defaults_enabled() && !machine
->usb_disabled
;
3042 if (smc
->use_ohci_by_default
) {
3043 pci_create_simple(phb
->bus
, -1, "pci-ohci");
3045 pci_create_simple(phb
->bus
, -1, "nec-usb-xhci");
3048 if (spapr
->has_graphics
) {
3049 USBBus
*usb_bus
= usb_bus_find(-1);
3051 usb_create_simple(usb_bus
, "usb-kbd");
3052 usb_create_simple(usb_bus
, "usb-mouse");
3056 if (spapr
->rma_size
< (MIN_RMA_SLOF
* MiB
)) {
3058 "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)",
3063 if (kernel_filename
) {
3064 uint64_t lowaddr
= 0;
3066 spapr
->kernel_size
= load_elf(kernel_filename
, NULL
,
3067 translate_kernel_address
, NULL
,
3068 NULL
, &lowaddr
, NULL
, 1,
3069 PPC_ELF_MACHINE
, 0, 0);
3070 if (spapr
->kernel_size
== ELF_LOAD_WRONG_ENDIAN
) {
3071 spapr
->kernel_size
= load_elf(kernel_filename
, NULL
,
3072 translate_kernel_address
, NULL
, NULL
,
3073 &lowaddr
, NULL
, 0, PPC_ELF_MACHINE
,
3075 spapr
->kernel_le
= spapr
->kernel_size
> 0;
3077 if (spapr
->kernel_size
< 0) {
3078 error_report("error loading %s: %s", kernel_filename
,
3079 load_elf_strerror(spapr
->kernel_size
));
3084 if (initrd_filename
) {
3085 /* Try to locate the initrd in the gap between the kernel
3086 * and the firmware. Add a bit of space just in case
3088 spapr
->initrd_base
= (KERNEL_LOAD_ADDR
+ spapr
->kernel_size
3089 + 0x1ffff) & ~0xffff;
3090 spapr
->initrd_size
= load_image_targphys(initrd_filename
,
3093 - spapr
->initrd_base
);
3094 if (spapr
->initrd_size
< 0) {
3095 error_report("could not load initial ram disk '%s'",
3102 if (bios_name
== NULL
) {
3103 bios_name
= FW_FILE_NAME
;
3105 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, bios_name
);
3107 error_report("Could not find LPAR firmware '%s'", bios_name
);
3110 fw_size
= load_image_targphys(filename
, 0, FW_MAX_SIZE
);
3112 error_report("Could not load LPAR firmware '%s'", filename
);
3117 /* FIXME: Should register things through the MachineState's qdev
3118 * interface, this is a legacy from the sPAPREnvironment structure
3119 * which predated MachineState but had a similar function */
3120 vmstate_register(NULL
, 0, &vmstate_spapr
, spapr
);
3121 register_savevm_live("spapr/htab", -1, 1,
3122 &savevm_htab_handlers
, spapr
);
3124 qbus_set_hotplug_handler(sysbus_get_default(), OBJECT(machine
),
3127 qemu_register_boot_set(spapr_boot_set
, spapr
);
3130 * Nothing needs to be done to resume a suspended guest because
3131 * suspending does not change the machine state, so no need for
3132 * a ->wakeup method.
3134 qemu_register_wakeup_support();
3136 if (kvm_enabled()) {
3137 /* to stop and start vmclock */
3138 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change
,
3141 kvmppc_spapr_enable_inkernel_multitce();
3145 static int spapr_kvm_type(MachineState
*machine
, const char *vm_type
)
3151 if (!strcmp(vm_type
, "HV")) {
3155 if (!strcmp(vm_type
, "PR")) {
3159 error_report("Unknown kvm-type specified '%s'", vm_type
);
3164 * Implementation of an interface to adjust firmware path
3165 * for the bootindex property handling.
3167 static char *spapr_get_fw_dev_path(FWPathProvider
*p
, BusState
*bus
,
3170 #define CAST(type, obj, name) \
3171 ((type *)object_dynamic_cast(OBJECT(obj), (name)))
3172 SCSIDevice
*d
= CAST(SCSIDevice
, dev
, TYPE_SCSI_DEVICE
);
3173 SpaprPhbState
*phb
= CAST(SpaprPhbState
, dev
, TYPE_SPAPR_PCI_HOST_BRIDGE
);
3174 VHostSCSICommon
*vsc
= CAST(VHostSCSICommon
, dev
, TYPE_VHOST_SCSI_COMMON
);
3177 void *spapr
= CAST(void, bus
->parent
, "spapr-vscsi");
3178 VirtIOSCSI
*virtio
= CAST(VirtIOSCSI
, bus
->parent
, TYPE_VIRTIO_SCSI
);
3179 USBDevice
*usb
= CAST(USBDevice
, bus
->parent
, TYPE_USB_DEVICE
);
3183 * Replace "channel@0/disk@0,0" with "disk@8000000000000000":
3184 * In the top 16 bits of the 64-bit LUN, we use SRP luns of the form
3185 * 0x8000 | (target << 8) | (bus << 5) | lun
3186 * (see the "Logical unit addressing format" table in SAM5)
3188 unsigned id
= 0x8000 | (d
->id
<< 8) | (d
->channel
<< 5) | d
->lun
;
3189 return g_strdup_printf("%s@%"PRIX64
, qdev_fw_name(dev
),
3190 (uint64_t)id
<< 48);
3191 } else if (virtio
) {
3193 * We use SRP luns of the form 01000000 | (target << 8) | lun
3194 * in the top 32 bits of the 64-bit LUN
3195 * Note: the quote above is from SLOF and it is wrong,
3196 * the actual binding is:
3197 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun )
3199 unsigned id
= 0x1000000 | (d
->id
<< 16) | d
->lun
;
3200 if (d
->lun
>= 256) {
3201 /* Use the LUN "flat space addressing method" */
3204 return g_strdup_printf("%s@%"PRIX64
, qdev_fw_name(dev
),
3205 (uint64_t)id
<< 32);
3208 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun
3209 * in the top 32 bits of the 64-bit LUN
3211 unsigned usb_port
= atoi(usb
->port
->path
);
3212 unsigned id
= 0x1000000 | (usb_port
<< 16) | d
->lun
;
3213 return g_strdup_printf("%s@%"PRIX64
, qdev_fw_name(dev
),
3214 (uint64_t)id
<< 32);
3219 * SLOF probes the USB devices, and if it recognizes that the device is a
3220 * storage device, it changes its name to "storage" instead of "usb-host",
3221 * and additionally adds a child node for the SCSI LUN, so the correct
3222 * boot path in SLOF is something like .../storage@1/disk@xxx" instead.
3224 if (strcmp("usb-host", qdev_fw_name(dev
)) == 0) {
3225 USBDevice
*usbdev
= CAST(USBDevice
, dev
, TYPE_USB_DEVICE
);
3226 if (usb_host_dev_is_scsi_storage(usbdev
)) {
3227 return g_strdup_printf("storage@%s/disk", usbdev
->port
->path
);
3232 /* Replace "pci" with "pci@800000020000000" */
3233 return g_strdup_printf("pci@%"PRIX64
, phb
->buid
);
3237 /* Same logic as virtio above */
3238 unsigned id
= 0x1000000 | (vsc
->target
<< 16) | vsc
->lun
;
3239 return g_strdup_printf("disk@%"PRIX64
, (uint64_t)id
<< 32);
3242 if (g_str_equal("pci-bridge", qdev_fw_name(dev
))) {
3243 /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */
3244 PCIDevice
*pcidev
= CAST(PCIDevice
, dev
, TYPE_PCI_DEVICE
);
3245 return g_strdup_printf("pci@%x", PCI_SLOT(pcidev
->devfn
));
3251 static char *spapr_get_kvm_type(Object
*obj
, Error
**errp
)
3253 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3255 return g_strdup(spapr
->kvm_type
);
3258 static void spapr_set_kvm_type(Object
*obj
, const char *value
, Error
**errp
)
3260 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3262 g_free(spapr
->kvm_type
);
3263 spapr
->kvm_type
= g_strdup(value
);
3266 static bool spapr_get_modern_hotplug_events(Object
*obj
, Error
**errp
)
3268 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3270 return spapr
->use_hotplug_event_source
;
3273 static void spapr_set_modern_hotplug_events(Object
*obj
, bool value
,
3276 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3278 spapr
->use_hotplug_event_source
= value
;
3281 static bool spapr_get_msix_emulation(Object
*obj
, Error
**errp
)
3286 static char *spapr_get_resize_hpt(Object
*obj
, Error
**errp
)
3288 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3290 switch (spapr
->resize_hpt
) {
3291 case SPAPR_RESIZE_HPT_DEFAULT
:
3292 return g_strdup("default");
3293 case SPAPR_RESIZE_HPT_DISABLED
:
3294 return g_strdup("disabled");
3295 case SPAPR_RESIZE_HPT_ENABLED
:
3296 return g_strdup("enabled");
3297 case SPAPR_RESIZE_HPT_REQUIRED
:
3298 return g_strdup("required");
3300 g_assert_not_reached();
3303 static void spapr_set_resize_hpt(Object
*obj
, const char *value
, Error
**errp
)
3305 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3307 if (strcmp(value
, "default") == 0) {
3308 spapr
->resize_hpt
= SPAPR_RESIZE_HPT_DEFAULT
;
3309 } else if (strcmp(value
, "disabled") == 0) {
3310 spapr
->resize_hpt
= SPAPR_RESIZE_HPT_DISABLED
;
3311 } else if (strcmp(value
, "enabled") == 0) {
3312 spapr
->resize_hpt
= SPAPR_RESIZE_HPT_ENABLED
;
3313 } else if (strcmp(value
, "required") == 0) {
3314 spapr
->resize_hpt
= SPAPR_RESIZE_HPT_REQUIRED
;
3316 error_setg(errp
, "Bad value for \"resize-hpt\" property");
3320 static void spapr_get_vsmt(Object
*obj
, Visitor
*v
, const char *name
,
3321 void *opaque
, Error
**errp
)
3323 visit_type_uint32(v
, name
, (uint32_t *)opaque
, errp
);
3326 static void spapr_set_vsmt(Object
*obj
, Visitor
*v
, const char *name
,
3327 void *opaque
, Error
**errp
)
3329 visit_type_uint32(v
, name
, (uint32_t *)opaque
, errp
);
3332 static char *spapr_get_ic_mode(Object
*obj
, Error
**errp
)
3334 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3336 if (spapr
->irq
== &spapr_irq_xics_legacy
) {
3337 return g_strdup("legacy");
3338 } else if (spapr
->irq
== &spapr_irq_xics
) {
3339 return g_strdup("xics");
3340 } else if (spapr
->irq
== &spapr_irq_xive
) {
3341 return g_strdup("xive");
3342 } else if (spapr
->irq
== &spapr_irq_dual
) {
3343 return g_strdup("dual");
3345 g_assert_not_reached();
3348 static void spapr_set_ic_mode(Object
*obj
, const char *value
, Error
**errp
)
3350 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3352 if (SPAPR_MACHINE_GET_CLASS(spapr
)->legacy_irq_allocation
) {
3353 error_setg(errp
, "This machine only uses the legacy XICS backend, don't pass ic-mode");
3357 /* The legacy IRQ backend can not be set */
3358 if (strcmp(value
, "xics") == 0) {
3359 spapr
->irq
= &spapr_irq_xics
;
3360 } else if (strcmp(value
, "xive") == 0) {
3361 spapr
->irq
= &spapr_irq_xive
;
3362 } else if (strcmp(value
, "dual") == 0) {
3363 spapr
->irq
= &spapr_irq_dual
;
3365 error_setg(errp
, "Bad value for \"ic-mode\" property");
3369 static char *spapr_get_host_model(Object
*obj
, Error
**errp
)
3371 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3373 return g_strdup(spapr
->host_model
);
3376 static void spapr_set_host_model(Object
*obj
, const char *value
, Error
**errp
)
3378 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3380 g_free(spapr
->host_model
);
3381 spapr
->host_model
= g_strdup(value
);
3384 static char *spapr_get_host_serial(Object
*obj
, Error
**errp
)
3386 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3388 return g_strdup(spapr
->host_serial
);
3391 static void spapr_set_host_serial(Object
*obj
, const char *value
, Error
**errp
)
3393 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3395 g_free(spapr
->host_serial
);
3396 spapr
->host_serial
= g_strdup(value
);
3399 static void spapr_instance_init(Object
*obj
)
3401 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3402 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(spapr
);
3404 spapr
->htab_fd
= -1;
3405 spapr
->use_hotplug_event_source
= true;
3406 object_property_add_str(obj
, "kvm-type",
3407 spapr_get_kvm_type
, spapr_set_kvm_type
, NULL
);
3408 object_property_set_description(obj
, "kvm-type",
3409 "Specifies the KVM virtualization mode (HV, PR)",
3411 object_property_add_bool(obj
, "modern-hotplug-events",
3412 spapr_get_modern_hotplug_events
,
3413 spapr_set_modern_hotplug_events
,
3415 object_property_set_description(obj
, "modern-hotplug-events",
3416 "Use dedicated hotplug event mechanism in"
3417 " place of standard EPOW events when possible"
3418 " (required for memory hot-unplug support)",
3420 ppc_compat_add_property(obj
, "max-cpu-compat", &spapr
->max_compat_pvr
,
3421 "Maximum permitted CPU compatibility mode",
3424 object_property_add_str(obj
, "resize-hpt",
3425 spapr_get_resize_hpt
, spapr_set_resize_hpt
, NULL
);
3426 object_property_set_description(obj
, "resize-hpt",
3427 "Resizing of the Hash Page Table (enabled, disabled, required)",
3429 object_property_add(obj
, "vsmt", "uint32", spapr_get_vsmt
,
3430 spapr_set_vsmt
, NULL
, &spapr
->vsmt
, &error_abort
);
3431 object_property_set_description(obj
, "vsmt",
3432 "Virtual SMT: KVM behaves as if this were"
3433 " the host's SMT mode", &error_abort
);
3434 object_property_add_bool(obj
, "vfio-no-msix-emulation",
3435 spapr_get_msix_emulation
, NULL
, NULL
);
3437 /* The machine class defines the default interrupt controller mode */
3438 spapr
->irq
= smc
->irq
;
3439 object_property_add_str(obj
, "ic-mode", spapr_get_ic_mode
,
3440 spapr_set_ic_mode
, NULL
);
3441 object_property_set_description(obj
, "ic-mode",
3442 "Specifies the interrupt controller mode (xics, xive, dual)",
3445 object_property_add_str(obj
, "host-model",
3446 spapr_get_host_model
, spapr_set_host_model
,
3448 object_property_set_description(obj
, "host-model",
3449 "Host model to advertise in guest device tree", &error_abort
);
3450 object_property_add_str(obj
, "host-serial",
3451 spapr_get_host_serial
, spapr_set_host_serial
,
3453 object_property_set_description(obj
, "host-serial",
3454 "Host serial number to advertise in guest device tree", &error_abort
);
3457 static void spapr_machine_finalizefn(Object
*obj
)
3459 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3461 g_free(spapr
->kvm_type
);
3464 void spapr_do_system_reset_on_cpu(CPUState
*cs
, run_on_cpu_data arg
)
3466 cpu_synchronize_state(cs
);
3467 ppc_cpu_do_system_reset(cs
);
3470 static void spapr_nmi(NMIState
*n
, int cpu_index
, Error
**errp
)
3475 async_run_on_cpu(cs
, spapr_do_system_reset_on_cpu
, RUN_ON_CPU_NULL
);
3479 int spapr_lmb_dt_populate(SpaprDrc
*drc
, SpaprMachineState
*spapr
,
3480 void *fdt
, int *fdt_start_offset
, Error
**errp
)
3485 addr
= spapr_drc_index(drc
) * SPAPR_MEMORY_BLOCK_SIZE
;
3486 node
= object_property_get_uint(OBJECT(drc
->dev
), PC_DIMM_NODE_PROP
,
3488 *fdt_start_offset
= spapr_populate_memory_node(fdt
, node
, addr
,
3489 SPAPR_MEMORY_BLOCK_SIZE
);
3493 static void spapr_add_lmbs(DeviceState
*dev
, uint64_t addr_start
, uint64_t size
,
3494 bool dedicated_hp_event_source
, Error
**errp
)
3497 uint32_t nr_lmbs
= size
/SPAPR_MEMORY_BLOCK_SIZE
;
3499 uint64_t addr
= addr_start
;
3500 bool hotplugged
= spapr_drc_hotplugged(dev
);
3501 Error
*local_err
= NULL
;
3503 for (i
= 0; i
< nr_lmbs
; i
++) {
3504 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
,
3505 addr
/ SPAPR_MEMORY_BLOCK_SIZE
);
3508 spapr_drc_attach(drc
, dev
, &local_err
);
3510 while (addr
> addr_start
) {
3511 addr
-= SPAPR_MEMORY_BLOCK_SIZE
;
3512 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
,
3513 addr
/ SPAPR_MEMORY_BLOCK_SIZE
);
3514 spapr_drc_detach(drc
);
3516 error_propagate(errp
, local_err
);
3520 spapr_drc_reset(drc
);
3522 addr
+= SPAPR_MEMORY_BLOCK_SIZE
;
3524 /* send hotplug notification to the
3525 * guest only in case of hotplugged memory
3528 if (dedicated_hp_event_source
) {
3529 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
,
3530 addr_start
/ SPAPR_MEMORY_BLOCK_SIZE
);
3531 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB
,
3533 spapr_drc_index(drc
));
3535 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB
,
3541 static void spapr_memory_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
3544 Error
*local_err
= NULL
;
3545 SpaprMachineState
*ms
= SPAPR_MACHINE(hotplug_dev
);
3546 PCDIMMDevice
*dimm
= PC_DIMM(dev
);
3547 uint64_t size
, addr
;
3549 size
= memory_device_get_region_size(MEMORY_DEVICE(dev
), &error_abort
);
3551 pc_dimm_plug(dimm
, MACHINE(ms
), &local_err
);
3556 addr
= object_property_get_uint(OBJECT(dimm
),
3557 PC_DIMM_ADDR_PROP
, &local_err
);
3562 spapr_add_lmbs(dev
, addr
, size
, spapr_ovec_test(ms
->ov5_cas
, OV5_HP_EVT
),
3571 pc_dimm_unplug(dimm
, MACHINE(ms
));
3573 error_propagate(errp
, local_err
);
3576 static void spapr_memory_pre_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
3579 const SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(hotplug_dev
);
3580 SpaprMachineState
*spapr
= SPAPR_MACHINE(hotplug_dev
);
3581 PCDIMMDevice
*dimm
= PC_DIMM(dev
);
3582 Error
*local_err
= NULL
;
3587 if (!smc
->dr_lmb_enabled
) {
3588 error_setg(errp
, "Memory hotplug not supported for this machine");
3592 size
= memory_device_get_region_size(MEMORY_DEVICE(dimm
), &local_err
);
3594 error_propagate(errp
, local_err
);
3598 if (size
% SPAPR_MEMORY_BLOCK_SIZE
) {
3599 error_setg(errp
, "Hotplugged memory size must be a multiple of "
3600 "%" PRIu64
" MB", SPAPR_MEMORY_BLOCK_SIZE
/ MiB
);
3604 memdev
= object_property_get_link(OBJECT(dimm
), PC_DIMM_MEMDEV_PROP
,
3606 pagesize
= host_memory_backend_pagesize(MEMORY_BACKEND(memdev
));
3607 spapr_check_pagesize(spapr
, pagesize
, &local_err
);
3609 error_propagate(errp
, local_err
);
3613 pc_dimm_pre_plug(dimm
, MACHINE(hotplug_dev
), NULL
, errp
);
3616 struct SpaprDimmState
{
3619 QTAILQ_ENTRY(SpaprDimmState
) next
;
3622 static SpaprDimmState
*spapr_pending_dimm_unplugs_find(SpaprMachineState
*s
,
3625 SpaprDimmState
*dimm_state
= NULL
;
3627 QTAILQ_FOREACH(dimm_state
, &s
->pending_dimm_unplugs
, next
) {
3628 if (dimm_state
->dimm
== dimm
) {
3635 static SpaprDimmState
*spapr_pending_dimm_unplugs_add(SpaprMachineState
*spapr
,
3639 SpaprDimmState
*ds
= NULL
;
3642 * If this request is for a DIMM whose removal had failed earlier
3643 * (due to guest's refusal to remove the LMBs), we would have this
3644 * dimm already in the pending_dimm_unplugs list. In that
3645 * case don't add again.
3647 ds
= spapr_pending_dimm_unplugs_find(spapr
, dimm
);
3649 ds
= g_malloc0(sizeof(SpaprDimmState
));
3650 ds
->nr_lmbs
= nr_lmbs
;
3652 QTAILQ_INSERT_HEAD(&spapr
->pending_dimm_unplugs
, ds
, next
);
3657 static void spapr_pending_dimm_unplugs_remove(SpaprMachineState
*spapr
,
3658 SpaprDimmState
*dimm_state
)
3660 QTAILQ_REMOVE(&spapr
->pending_dimm_unplugs
, dimm_state
, next
);
3664 static SpaprDimmState
*spapr_recover_pending_dimm_state(SpaprMachineState
*ms
,
3668 uint64_t size
= memory_device_get_region_size(MEMORY_DEVICE(dimm
),
3670 uint32_t nr_lmbs
= size
/ SPAPR_MEMORY_BLOCK_SIZE
;
3671 uint32_t avail_lmbs
= 0;
3672 uint64_t addr_start
, addr
;
3675 addr_start
= object_property_get_int(OBJECT(dimm
), PC_DIMM_ADDR_PROP
,
3679 for (i
= 0; i
< nr_lmbs
; i
++) {
3680 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
,
3681 addr
/ SPAPR_MEMORY_BLOCK_SIZE
);
3686 addr
+= SPAPR_MEMORY_BLOCK_SIZE
;
3689 return spapr_pending_dimm_unplugs_add(ms
, avail_lmbs
, dimm
);
3692 /* Callback to be called during DRC release. */
3693 void spapr_lmb_release(DeviceState
*dev
)
3695 HotplugHandler
*hotplug_ctrl
= qdev_get_hotplug_handler(dev
);
3696 SpaprMachineState
*spapr
= SPAPR_MACHINE(hotplug_ctrl
);
3697 SpaprDimmState
*ds
= spapr_pending_dimm_unplugs_find(spapr
, PC_DIMM(dev
));
3699 /* This information will get lost if a migration occurs
3700 * during the unplug process. In this case recover it. */
3702 ds
= spapr_recover_pending_dimm_state(spapr
, PC_DIMM(dev
));
3704 /* The DRC being examined by the caller at least must be counted */
3705 g_assert(ds
->nr_lmbs
);
3708 if (--ds
->nr_lmbs
) {
3713 * Now that all the LMBs have been removed by the guest, call the
3714 * unplug handler chain. This can never fail.
3716 hotplug_handler_unplug(hotplug_ctrl
, dev
, &error_abort
);
3717 object_unparent(OBJECT(dev
));
3720 static void spapr_memory_unplug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
)
3722 SpaprMachineState
*spapr
= SPAPR_MACHINE(hotplug_dev
);
3723 SpaprDimmState
*ds
= spapr_pending_dimm_unplugs_find(spapr
, PC_DIMM(dev
));
3725 pc_dimm_unplug(PC_DIMM(dev
), MACHINE(hotplug_dev
));
3726 object_property_set_bool(OBJECT(dev
), false, "realized", NULL
);
3727 spapr_pending_dimm_unplugs_remove(spapr
, ds
);
3730 static void spapr_memory_unplug_request(HotplugHandler
*hotplug_dev
,
3731 DeviceState
*dev
, Error
**errp
)
3733 SpaprMachineState
*spapr
= SPAPR_MACHINE(hotplug_dev
);
3734 Error
*local_err
= NULL
;
3735 PCDIMMDevice
*dimm
= PC_DIMM(dev
);
3737 uint64_t size
, addr_start
, addr
;
3741 size
= memory_device_get_region_size(MEMORY_DEVICE(dimm
), &error_abort
);
3742 nr_lmbs
= size
/ SPAPR_MEMORY_BLOCK_SIZE
;
3744 addr_start
= object_property_get_uint(OBJECT(dimm
), PC_DIMM_ADDR_PROP
,
3751 * An existing pending dimm state for this DIMM means that there is an
3752 * unplug operation in progress, waiting for the spapr_lmb_release
3753 * callback to complete the job (BQL can't cover that far). In this case,
3754 * bail out to avoid detaching DRCs that were already released.
3756 if (spapr_pending_dimm_unplugs_find(spapr
, dimm
)) {
3757 error_setg(&local_err
,
3758 "Memory unplug already in progress for device %s",
3763 spapr_pending_dimm_unplugs_add(spapr
, nr_lmbs
, dimm
);
3766 for (i
= 0; i
< nr_lmbs
; i
++) {
3767 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
,
3768 addr
/ SPAPR_MEMORY_BLOCK_SIZE
);
3771 spapr_drc_detach(drc
);
3772 addr
+= SPAPR_MEMORY_BLOCK_SIZE
;
3775 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
,
3776 addr_start
/ SPAPR_MEMORY_BLOCK_SIZE
);
3777 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB
,
3778 nr_lmbs
, spapr_drc_index(drc
));
3780 error_propagate(errp
, local_err
);
3783 /* Callback to be called during DRC release. */
3784 void spapr_core_release(DeviceState
*dev
)
3786 HotplugHandler
*hotplug_ctrl
= qdev_get_hotplug_handler(dev
);
3788 /* Call the unplug handler chain. This can never fail. */
3789 hotplug_handler_unplug(hotplug_ctrl
, dev
, &error_abort
);
3790 object_unparent(OBJECT(dev
));
3793 static void spapr_core_unplug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
)
3795 MachineState
*ms
= MACHINE(hotplug_dev
);
3796 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(ms
);
3797 CPUCore
*cc
= CPU_CORE(dev
);
3798 CPUArchId
*core_slot
= spapr_find_cpu_slot(ms
, cc
->core_id
, NULL
);
3800 if (smc
->pre_2_10_has_unused_icps
) {
3801 SpaprCpuCore
*sc
= SPAPR_CPU_CORE(OBJECT(dev
));
3804 for (i
= 0; i
< cc
->nr_threads
; i
++) {
3805 CPUState
*cs
= CPU(sc
->threads
[i
]);
3807 pre_2_10_vmstate_register_dummy_icp(cs
->cpu_index
);
3812 core_slot
->cpu
= NULL
;
3813 object_property_set_bool(OBJECT(dev
), false, "realized", NULL
);
3817 void spapr_core_unplug_request(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
3820 SpaprMachineState
*spapr
= SPAPR_MACHINE(OBJECT(hotplug_dev
));
3823 CPUCore
*cc
= CPU_CORE(dev
);
3825 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev
), cc
->core_id
, &index
)) {
3826 error_setg(errp
, "Unable to find CPU core with core-id: %d",
3831 error_setg(errp
, "Boot CPU core may not be unplugged");
3835 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_CPU
,
3836 spapr_vcpu_id(spapr
, cc
->core_id
));
3839 spapr_drc_detach(drc
);
3841 spapr_hotplug_req_remove_by_index(drc
);
3844 int spapr_core_dt_populate(SpaprDrc
*drc
, SpaprMachineState
*spapr
,
3845 void *fdt
, int *fdt_start_offset
, Error
**errp
)
3847 SpaprCpuCore
*core
= SPAPR_CPU_CORE(drc
->dev
);
3848 CPUState
*cs
= CPU(core
->threads
[0]);
3849 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
3850 DeviceClass
*dc
= DEVICE_GET_CLASS(cs
);
3851 int id
= spapr_get_vcpu_id(cpu
);
3855 nodename
= g_strdup_printf("%s@%x", dc
->fw_name
, id
);
3856 offset
= fdt_add_subnode(fdt
, 0, nodename
);
3859 spapr_populate_cpu_dt(cs
, fdt
, offset
, spapr
);
3861 *fdt_start_offset
= offset
;
3865 static void spapr_core_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
3868 SpaprMachineState
*spapr
= SPAPR_MACHINE(OBJECT(hotplug_dev
));
3869 MachineClass
*mc
= MACHINE_GET_CLASS(spapr
);
3870 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
3871 SpaprCpuCore
*core
= SPAPR_CPU_CORE(OBJECT(dev
));
3872 CPUCore
*cc
= CPU_CORE(dev
);
3875 Error
*local_err
= NULL
;
3876 CPUArchId
*core_slot
;
3878 bool hotplugged
= spapr_drc_hotplugged(dev
);
3881 core_slot
= spapr_find_cpu_slot(MACHINE(hotplug_dev
), cc
->core_id
, &index
);
3883 error_setg(errp
, "Unable to find CPU core with core-id: %d",
3887 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_CPU
,
3888 spapr_vcpu_id(spapr
, cc
->core_id
));
3890 g_assert(drc
|| !mc
->has_hotpluggable_cpus
);
3893 spapr_drc_attach(drc
, dev
, &local_err
);
3895 error_propagate(errp
, local_err
);
3901 * Send hotplug notification interrupt to the guest only
3902 * in case of hotplugged CPUs.
3904 spapr_hotplug_req_add_by_index(drc
);
3906 spapr_drc_reset(drc
);
3910 core_slot
->cpu
= OBJECT(dev
);
3912 if (smc
->pre_2_10_has_unused_icps
) {
3913 for (i
= 0; i
< cc
->nr_threads
; i
++) {
3914 cs
= CPU(core
->threads
[i
]);
3915 pre_2_10_vmstate_unregister_dummy_icp(cs
->cpu_index
);
3920 * Set compatibility mode to match the boot CPU, which was either set
3921 * by the machine reset code or by CAS.
3924 for (i
= 0; i
< cc
->nr_threads
; i
++) {
3925 ppc_set_compat(core
->threads
[i
], POWERPC_CPU(first_cpu
)->compat_pvr
,
3928 error_propagate(errp
, local_err
);
3935 static void spapr_core_pre_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
3938 MachineState
*machine
= MACHINE(OBJECT(hotplug_dev
));
3939 MachineClass
*mc
= MACHINE_GET_CLASS(hotplug_dev
);
3940 Error
*local_err
= NULL
;
3941 CPUCore
*cc
= CPU_CORE(dev
);
3942 const char *base_core_type
= spapr_get_cpu_core_type(machine
->cpu_type
);
3943 const char *type
= object_get_typename(OBJECT(dev
));
3944 CPUArchId
*core_slot
;
3946 unsigned int smp_threads
= machine
->smp
.threads
;
3948 if (dev
->hotplugged
&& !mc
->has_hotpluggable_cpus
) {
3949 error_setg(&local_err
, "CPU hotplug not supported for this machine");
3953 if (strcmp(base_core_type
, type
)) {
3954 error_setg(&local_err
, "CPU core type should be %s", base_core_type
);
3958 if (cc
->core_id
% smp_threads
) {
3959 error_setg(&local_err
, "invalid core id %d", cc
->core_id
);
3964 * In general we should have homogeneous threads-per-core, but old
3965 * (pre hotplug support) machine types allow the last core to have
3966 * reduced threads as a compatibility hack for when we allowed
3967 * total vcpus not a multiple of threads-per-core.
3969 if (mc
->has_hotpluggable_cpus
&& (cc
->nr_threads
!= smp_threads
)) {
3970 error_setg(&local_err
, "invalid nr-threads %d, must be %d",
3971 cc
->nr_threads
, smp_threads
);
3975 core_slot
= spapr_find_cpu_slot(MACHINE(hotplug_dev
), cc
->core_id
, &index
);
3977 error_setg(&local_err
, "core id %d out of range", cc
->core_id
);
3981 if (core_slot
->cpu
) {
3982 error_setg(&local_err
, "core %d already populated", cc
->core_id
);
3986 numa_cpu_pre_plug(core_slot
, dev
, &local_err
);
3989 error_propagate(errp
, local_err
);
3992 int spapr_phb_dt_populate(SpaprDrc
*drc
, SpaprMachineState
*spapr
,
3993 void *fdt
, int *fdt_start_offset
, Error
**errp
)
3995 SpaprPhbState
*sphb
= SPAPR_PCI_HOST_BRIDGE(drc
->dev
);
3998 intc_phandle
= spapr_irq_get_phandle(spapr
, spapr
->fdt_blob
, errp
);
3999 if (intc_phandle
<= 0) {
4003 if (spapr_dt_phb(sphb
, intc_phandle
, fdt
, spapr
->irq
->nr_msis
,
4004 fdt_start_offset
)) {
4005 error_setg(errp
, "unable to create FDT node for PHB %d", sphb
->index
);
4009 /* generally SLOF creates these, for hotplug it's up to QEMU */
4010 _FDT(fdt_setprop_string(fdt
, *fdt_start_offset
, "name", "pci"));
4015 static void spapr_phb_pre_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
4018 SpaprMachineState
*spapr
= SPAPR_MACHINE(OBJECT(hotplug_dev
));
4019 SpaprPhbState
*sphb
= SPAPR_PCI_HOST_BRIDGE(dev
);
4020 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(spapr
);
4021 const unsigned windows_supported
= spapr_phb_windows_supported(sphb
);
4023 if (dev
->hotplugged
&& !smc
->dr_phb_enabled
) {
4024 error_setg(errp
, "PHB hotplug not supported for this machine");
4028 if (sphb
->index
== (uint32_t)-1) {
4029 error_setg(errp
, "\"index\" for PAPR PHB is mandatory");
4034 * This will check that sphb->index doesn't exceed the maximum number of
4035 * PHBs for the current machine type.
4037 smc
->phb_placement(spapr
, sphb
->index
,
4038 &sphb
->buid
, &sphb
->io_win_addr
,
4039 &sphb
->mem_win_addr
, &sphb
->mem64_win_addr
,
4040 windows_supported
, sphb
->dma_liobn
,
4041 &sphb
->nv2_gpa_win_addr
, &sphb
->nv2_atsd_win_addr
,
4045 static void spapr_phb_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
4048 SpaprMachineState
*spapr
= SPAPR_MACHINE(OBJECT(hotplug_dev
));
4049 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(spapr
);
4050 SpaprPhbState
*sphb
= SPAPR_PCI_HOST_BRIDGE(dev
);
4052 bool hotplugged
= spapr_drc_hotplugged(dev
);
4053 Error
*local_err
= NULL
;
4055 if (!smc
->dr_phb_enabled
) {
4059 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_PHB
, sphb
->index
);
4060 /* hotplug hooks should check it's enabled before getting this far */
4063 spapr_drc_attach(drc
, DEVICE(dev
), &local_err
);
4065 error_propagate(errp
, local_err
);
4070 spapr_hotplug_req_add_by_index(drc
);
4072 spapr_drc_reset(drc
);
4076 void spapr_phb_release(DeviceState
*dev
)
4078 HotplugHandler
*hotplug_ctrl
= qdev_get_hotplug_handler(dev
);
4080 hotplug_handler_unplug(hotplug_ctrl
, dev
, &error_abort
);
4081 object_unparent(OBJECT(dev
));
4084 static void spapr_phb_unplug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
)
4086 object_property_set_bool(OBJECT(dev
), false, "realized", NULL
);
4089 static void spapr_phb_unplug_request(HotplugHandler
*hotplug_dev
,
4090 DeviceState
*dev
, Error
**errp
)
4092 SpaprPhbState
*sphb
= SPAPR_PCI_HOST_BRIDGE(dev
);
4095 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_PHB
, sphb
->index
);
4098 if (!spapr_drc_unplug_requested(drc
)) {
4099 spapr_drc_detach(drc
);
4100 spapr_hotplug_req_remove_by_index(drc
);
4104 static void spapr_tpm_proxy_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
4107 SpaprMachineState
*spapr
= SPAPR_MACHINE(OBJECT(hotplug_dev
));
4108 SpaprTpmProxy
*tpm_proxy
= SPAPR_TPM_PROXY(dev
);
4110 if (spapr
->tpm_proxy
!= NULL
) {
4111 error_setg(errp
, "Only one TPM proxy can be specified for this machine");
4115 spapr
->tpm_proxy
= tpm_proxy
;
4118 static void spapr_tpm_proxy_unplug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
)
4120 SpaprMachineState
*spapr
= SPAPR_MACHINE(OBJECT(hotplug_dev
));
4122 object_property_set_bool(OBJECT(dev
), false, "realized", NULL
);
4123 object_unparent(OBJECT(dev
));
4124 spapr
->tpm_proxy
= NULL
;
4127 static void spapr_machine_device_plug(HotplugHandler
*hotplug_dev
,
4128 DeviceState
*dev
, Error
**errp
)
4130 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
4131 spapr_memory_plug(hotplug_dev
, dev
, errp
);
4132 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_CPU_CORE
)) {
4133 spapr_core_plug(hotplug_dev
, dev
, errp
);
4134 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_PCI_HOST_BRIDGE
)) {
4135 spapr_phb_plug(hotplug_dev
, dev
, errp
);
4136 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_TPM_PROXY
)) {
4137 spapr_tpm_proxy_plug(hotplug_dev
, dev
, errp
);
4141 static void spapr_machine_device_unplug(HotplugHandler
*hotplug_dev
,
4142 DeviceState
*dev
, Error
**errp
)
4144 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
4145 spapr_memory_unplug(hotplug_dev
, dev
);
4146 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_CPU_CORE
)) {
4147 spapr_core_unplug(hotplug_dev
, dev
);
4148 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_PCI_HOST_BRIDGE
)) {
4149 spapr_phb_unplug(hotplug_dev
, dev
);
4150 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_TPM_PROXY
)) {
4151 spapr_tpm_proxy_unplug(hotplug_dev
, dev
);
4155 static void spapr_machine_device_unplug_request(HotplugHandler
*hotplug_dev
,
4156 DeviceState
*dev
, Error
**errp
)
4158 SpaprMachineState
*sms
= SPAPR_MACHINE(OBJECT(hotplug_dev
));
4159 MachineClass
*mc
= MACHINE_GET_CLASS(sms
);
4160 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4162 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
4163 if (spapr_ovec_test(sms
->ov5_cas
, OV5_HP_EVT
)) {
4164 spapr_memory_unplug_request(hotplug_dev
, dev
, errp
);
4166 /* NOTE: this means there is a window after guest reset, prior to
4167 * CAS negotiation, where unplug requests will fail due to the
4168 * capability not being detected yet. This is a bit different than
4169 * the case with PCI unplug, where the events will be queued and
4170 * eventually handled by the guest after boot
4172 error_setg(errp
, "Memory hot unplug not supported for this guest");
4174 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_CPU_CORE
)) {
4175 if (!mc
->has_hotpluggable_cpus
) {
4176 error_setg(errp
, "CPU hot unplug not supported on this machine");
4179 spapr_core_unplug_request(hotplug_dev
, dev
, errp
);
4180 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_PCI_HOST_BRIDGE
)) {
4181 if (!smc
->dr_phb_enabled
) {
4182 error_setg(errp
, "PHB hot unplug not supported on this machine");
4185 spapr_phb_unplug_request(hotplug_dev
, dev
, errp
);
4186 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_TPM_PROXY
)) {
4187 spapr_tpm_proxy_unplug(hotplug_dev
, dev
);
4191 static void spapr_machine_device_pre_plug(HotplugHandler
*hotplug_dev
,
4192 DeviceState
*dev
, Error
**errp
)
4194 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
4195 spapr_memory_pre_plug(hotplug_dev
, dev
, errp
);
4196 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_CPU_CORE
)) {
4197 spapr_core_pre_plug(hotplug_dev
, dev
, errp
);
4198 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_PCI_HOST_BRIDGE
)) {
4199 spapr_phb_pre_plug(hotplug_dev
, dev
, errp
);
4203 static HotplugHandler
*spapr_get_hotplug_handler(MachineState
*machine
,
4206 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
) ||
4207 object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_CPU_CORE
) ||
4208 object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_PCI_HOST_BRIDGE
) ||
4209 object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_TPM_PROXY
)) {
4210 return HOTPLUG_HANDLER(machine
);
4212 if (object_dynamic_cast(OBJECT(dev
), TYPE_PCI_DEVICE
)) {
4213 PCIDevice
*pcidev
= PCI_DEVICE(dev
);
4214 PCIBus
*root
= pci_device_root_bus(pcidev
);
4215 SpaprPhbState
*phb
=
4216 (SpaprPhbState
*)object_dynamic_cast(OBJECT(BUS(root
)->parent
),
4217 TYPE_SPAPR_PCI_HOST_BRIDGE
);
4220 return HOTPLUG_HANDLER(phb
);
4226 static CpuInstanceProperties
4227 spapr_cpu_index_to_props(MachineState
*machine
, unsigned cpu_index
)
4229 CPUArchId
*core_slot
;
4230 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
4232 /* make sure possible_cpu are intialized */
4233 mc
->possible_cpu_arch_ids(machine
);
4234 /* get CPU core slot containing thread that matches cpu_index */
4235 core_slot
= spapr_find_cpu_slot(machine
, cpu_index
, NULL
);
4237 return core_slot
->props
;
4240 static int64_t spapr_get_default_cpu_node_id(const MachineState
*ms
, int idx
)
4242 return idx
/ ms
->smp
.cores
% ms
->numa_state
->num_nodes
;
4245 static const CPUArchIdList
*spapr_possible_cpu_arch_ids(MachineState
*machine
)
4248 unsigned int smp_threads
= machine
->smp
.threads
;
4249 unsigned int smp_cpus
= machine
->smp
.cpus
;
4250 const char *core_type
;
4251 int spapr_max_cores
= machine
->smp
.max_cpus
/ smp_threads
;
4252 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
4254 if (!mc
->has_hotpluggable_cpus
) {
4255 spapr_max_cores
= QEMU_ALIGN_UP(smp_cpus
, smp_threads
) / smp_threads
;
4257 if (machine
->possible_cpus
) {
4258 assert(machine
->possible_cpus
->len
== spapr_max_cores
);
4259 return machine
->possible_cpus
;
4262 core_type
= spapr_get_cpu_core_type(machine
->cpu_type
);
4264 error_report("Unable to find sPAPR CPU Core definition");
4268 machine
->possible_cpus
= g_malloc0(sizeof(CPUArchIdList
) +
4269 sizeof(CPUArchId
) * spapr_max_cores
);
4270 machine
->possible_cpus
->len
= spapr_max_cores
;
4271 for (i
= 0; i
< machine
->possible_cpus
->len
; i
++) {
4272 int core_id
= i
* smp_threads
;
4274 machine
->possible_cpus
->cpus
[i
].type
= core_type
;
4275 machine
->possible_cpus
->cpus
[i
].vcpus_count
= smp_threads
;
4276 machine
->possible_cpus
->cpus
[i
].arch_id
= core_id
;
4277 machine
->possible_cpus
->cpus
[i
].props
.has_core_id
= true;
4278 machine
->possible_cpus
->cpus
[i
].props
.core_id
= core_id
;
4280 return machine
->possible_cpus
;
4283 static void spapr_phb_placement(SpaprMachineState
*spapr
, uint32_t index
,
4284 uint64_t *buid
, hwaddr
*pio
,
4285 hwaddr
*mmio32
, hwaddr
*mmio64
,
4286 unsigned n_dma
, uint32_t *liobns
,
4287 hwaddr
*nv2gpa
, hwaddr
*nv2atsd
, Error
**errp
)
4290 * New-style PHB window placement.
4292 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window
4293 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO
4296 * Some guest kernels can't work with MMIO windows above 1<<46
4297 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB
4299 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each
4300 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the
4301 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the
4302 * 1TiB 64-bit MMIO windows for each PHB.
4304 const uint64_t base_buid
= 0x800000020000000ULL
;
4307 /* Sanity check natural alignments */
4308 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE
% SPAPR_PCI_MEM64_WIN_SIZE
) != 0);
4309 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT
% SPAPR_PCI_MEM64_WIN_SIZE
) != 0);
4310 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE
% SPAPR_PCI_MEM32_WIN_SIZE
) != 0);
4311 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE
% SPAPR_PCI_IO_WIN_SIZE
) != 0);
4312 /* Sanity check bounds */
4313 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS
* SPAPR_PCI_IO_WIN_SIZE
) >
4314 SPAPR_PCI_MEM32_WIN_SIZE
);
4315 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS
* SPAPR_PCI_MEM32_WIN_SIZE
) >
4316 SPAPR_PCI_MEM64_WIN_SIZE
);
4318 if (index
>= SPAPR_MAX_PHBS
) {
4319 error_setg(errp
, "\"index\" for PAPR PHB is too large (max %llu)",
4320 SPAPR_MAX_PHBS
- 1);
4324 *buid
= base_buid
+ index
;
4325 for (i
= 0; i
< n_dma
; ++i
) {
4326 liobns
[i
] = SPAPR_PCI_LIOBN(index
, i
);
4329 *pio
= SPAPR_PCI_BASE
+ index
* SPAPR_PCI_IO_WIN_SIZE
;
4330 *mmio32
= SPAPR_PCI_BASE
+ (index
+ 1) * SPAPR_PCI_MEM32_WIN_SIZE
;
4331 *mmio64
= SPAPR_PCI_BASE
+ (index
+ 1) * SPAPR_PCI_MEM64_WIN_SIZE
;
4333 *nv2gpa
= SPAPR_PCI_NV2RAM64_WIN_BASE
+ index
* SPAPR_PCI_NV2RAM64_WIN_SIZE
;
4334 *nv2atsd
= SPAPR_PCI_NV2ATSD_WIN_BASE
+ index
* SPAPR_PCI_NV2ATSD_WIN_SIZE
;
4337 static ICSState
*spapr_ics_get(XICSFabric
*dev
, int irq
)
4339 SpaprMachineState
*spapr
= SPAPR_MACHINE(dev
);
4341 return ics_valid_irq(spapr
->ics
, irq
) ? spapr
->ics
: NULL
;
4344 static void spapr_ics_resend(XICSFabric
*dev
)
4346 SpaprMachineState
*spapr
= SPAPR_MACHINE(dev
);
4348 ics_resend(spapr
->ics
);
4351 static ICPState
*spapr_icp_get(XICSFabric
*xi
, int vcpu_id
)
4353 PowerPCCPU
*cpu
= spapr_find_cpu(vcpu_id
);
4355 return cpu
? spapr_cpu_state(cpu
)->icp
: NULL
;
4358 static void spapr_pic_print_info(InterruptStatsProvider
*obj
,
4361 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
4363 spapr
->irq
->print_info(spapr
, mon
);
4364 monitor_printf(mon
, "irqchip: %s\n",
4365 kvm_irqchip_in_kernel() ? "in-kernel" : "emulated");
4368 int spapr_get_vcpu_id(PowerPCCPU
*cpu
)
4370 return cpu
->vcpu_id
;
4373 void spapr_set_vcpu_id(PowerPCCPU
*cpu
, int cpu_index
, Error
**errp
)
4375 SpaprMachineState
*spapr
= SPAPR_MACHINE(qdev_get_machine());
4376 MachineState
*ms
= MACHINE(spapr
);
4379 vcpu_id
= spapr_vcpu_id(spapr
, cpu_index
);
4381 if (kvm_enabled() && !kvm_vcpu_id_is_valid(vcpu_id
)) {
4382 error_setg(errp
, "Can't create CPU with id %d in KVM", vcpu_id
);
4383 error_append_hint(errp
, "Adjust the number of cpus to %d "
4384 "or try to raise the number of threads per core\n",
4385 vcpu_id
* ms
->smp
.threads
/ spapr
->vsmt
);
4389 cpu
->vcpu_id
= vcpu_id
;
4392 PowerPCCPU
*spapr_find_cpu(int vcpu_id
)
4397 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
4399 if (spapr_get_vcpu_id(cpu
) == vcpu_id
) {
4407 static void spapr_cpu_exec_enter(PPCVirtualHypervisor
*vhyp
, PowerPCCPU
*cpu
)
4409 SpaprCpuState
*spapr_cpu
= spapr_cpu_state(cpu
);
4411 /* These are only called by TCG, KVM maintains dispatch state */
4413 spapr_cpu
->prod
= false;
4414 if (spapr_cpu
->vpa_addr
) {
4415 CPUState
*cs
= CPU(cpu
);
4418 dispatch
= ldl_be_phys(cs
->as
,
4419 spapr_cpu
->vpa_addr
+ VPA_DISPATCH_COUNTER
);
4421 if ((dispatch
& 1) != 0) {
4422 qemu_log_mask(LOG_GUEST_ERROR
,
4423 "VPA: incorrect dispatch counter value for "
4424 "dispatched partition %u, correcting.\n", dispatch
);
4428 spapr_cpu
->vpa_addr
+ VPA_DISPATCH_COUNTER
, dispatch
);
4432 static void spapr_cpu_exec_exit(PPCVirtualHypervisor
*vhyp
, PowerPCCPU
*cpu
)
4434 SpaprCpuState
*spapr_cpu
= spapr_cpu_state(cpu
);
4436 if (spapr_cpu
->vpa_addr
) {
4437 CPUState
*cs
= CPU(cpu
);
4440 dispatch
= ldl_be_phys(cs
->as
,
4441 spapr_cpu
->vpa_addr
+ VPA_DISPATCH_COUNTER
);
4443 if ((dispatch
& 1) != 1) {
4444 qemu_log_mask(LOG_GUEST_ERROR
,
4445 "VPA: incorrect dispatch counter value for "
4446 "preempted partition %u, correcting.\n", dispatch
);
4450 spapr_cpu
->vpa_addr
+ VPA_DISPATCH_COUNTER
, dispatch
);
4454 static void spapr_machine_class_init(ObjectClass
*oc
, void *data
)
4456 MachineClass
*mc
= MACHINE_CLASS(oc
);
4457 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(oc
);
4458 FWPathProviderClass
*fwc
= FW_PATH_PROVIDER_CLASS(oc
);
4459 NMIClass
*nc
= NMI_CLASS(oc
);
4460 HotplugHandlerClass
*hc
= HOTPLUG_HANDLER_CLASS(oc
);
4461 PPCVirtualHypervisorClass
*vhc
= PPC_VIRTUAL_HYPERVISOR_CLASS(oc
);
4462 XICSFabricClass
*xic
= XICS_FABRIC_CLASS(oc
);
4463 InterruptStatsProviderClass
*ispc
= INTERRUPT_STATS_PROVIDER_CLASS(oc
);
4465 mc
->desc
= "pSeries Logical Partition (PAPR compliant)";
4466 mc
->ignore_boot_device_suffixes
= true;
4469 * We set up the default / latest behaviour here. The class_init
4470 * functions for the specific versioned machine types can override
4471 * these details for backwards compatibility
4473 mc
->init
= spapr_machine_init
;
4474 mc
->reset
= spapr_machine_reset
;
4475 mc
->block_default_type
= IF_SCSI
;
4476 mc
->max_cpus
= 1024;
4477 mc
->no_parallel
= 1;
4478 mc
->default_boot_order
= "";
4479 mc
->default_ram_size
= 512 * MiB
;
4480 mc
->default_display
= "std";
4481 mc
->kvm_type
= spapr_kvm_type
;
4482 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_SPAPR_PCI_HOST_BRIDGE
);
4483 mc
->pci_allow_0_address
= true;
4484 assert(!mc
->get_hotplug_handler
);
4485 mc
->get_hotplug_handler
= spapr_get_hotplug_handler
;
4486 hc
->pre_plug
= spapr_machine_device_pre_plug
;
4487 hc
->plug
= spapr_machine_device_plug
;
4488 mc
->cpu_index_to_instance_props
= spapr_cpu_index_to_props
;
4489 mc
->get_default_cpu_node_id
= spapr_get_default_cpu_node_id
;
4490 mc
->possible_cpu_arch_ids
= spapr_possible_cpu_arch_ids
;
4491 hc
->unplug_request
= spapr_machine_device_unplug_request
;
4492 hc
->unplug
= spapr_machine_device_unplug
;
4494 smc
->dr_lmb_enabled
= true;
4495 smc
->update_dt_enabled
= true;
4496 mc
->default_cpu_type
= POWERPC_CPU_TYPE_NAME("power9_v2.0");
4497 mc
->has_hotpluggable_cpus
= true;
4498 smc
->resize_hpt_default
= SPAPR_RESIZE_HPT_ENABLED
;
4499 fwc
->get_dev_path
= spapr_get_fw_dev_path
;
4500 nc
->nmi_monitor_handler
= spapr_nmi
;
4501 smc
->phb_placement
= spapr_phb_placement
;
4502 vhc
->hypercall
= emulate_spapr_hypercall
;
4503 vhc
->hpt_mask
= spapr_hpt_mask
;
4504 vhc
->map_hptes
= spapr_map_hptes
;
4505 vhc
->unmap_hptes
= spapr_unmap_hptes
;
4506 vhc
->hpte_set_c
= spapr_hpte_set_c
;
4507 vhc
->hpte_set_r
= spapr_hpte_set_r
;
4508 vhc
->get_pate
= spapr_get_pate
;
4509 vhc
->encode_hpt_for_kvm_pr
= spapr_encode_hpt_for_kvm_pr
;
4510 vhc
->cpu_exec_enter
= spapr_cpu_exec_enter
;
4511 vhc
->cpu_exec_exit
= spapr_cpu_exec_exit
;
4512 xic
->ics_get
= spapr_ics_get
;
4513 xic
->ics_resend
= spapr_ics_resend
;
4514 xic
->icp_get
= spapr_icp_get
;
4515 ispc
->print_info
= spapr_pic_print_info
;
4516 /* Force NUMA node memory size to be a multiple of
4517 * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity
4518 * in which LMBs are represented and hot-added
4520 mc
->numa_mem_align_shift
= 28;
4521 mc
->numa_mem_supported
= true;
4523 smc
->default_caps
.caps
[SPAPR_CAP_HTM
] = SPAPR_CAP_OFF
;
4524 smc
->default_caps
.caps
[SPAPR_CAP_VSX
] = SPAPR_CAP_ON
;
4525 smc
->default_caps
.caps
[SPAPR_CAP_DFP
] = SPAPR_CAP_ON
;
4526 smc
->default_caps
.caps
[SPAPR_CAP_CFPC
] = SPAPR_CAP_WORKAROUND
;
4527 smc
->default_caps
.caps
[SPAPR_CAP_SBBC
] = SPAPR_CAP_WORKAROUND
;
4528 smc
->default_caps
.caps
[SPAPR_CAP_IBS
] = SPAPR_CAP_WORKAROUND
;
4529 smc
->default_caps
.caps
[SPAPR_CAP_HPT_MAXPAGESIZE
] = 16; /* 64kiB */
4530 smc
->default_caps
.caps
[SPAPR_CAP_NESTED_KVM_HV
] = SPAPR_CAP_OFF
;
4531 smc
->default_caps
.caps
[SPAPR_CAP_LARGE_DECREMENTER
] = SPAPR_CAP_ON
;
4532 smc
->default_caps
.caps
[SPAPR_CAP_CCF_ASSIST
] = SPAPR_CAP_OFF
;
4533 spapr_caps_add_properties(smc
, &error_abort
);
4534 smc
->irq
= &spapr_irq_dual
;
4535 smc
->dr_phb_enabled
= true;
4536 smc
->linux_pci_probe
= true;
4539 static const TypeInfo spapr_machine_info
= {
4540 .name
= TYPE_SPAPR_MACHINE
,
4541 .parent
= TYPE_MACHINE
,
4543 .instance_size
= sizeof(SpaprMachineState
),
4544 .instance_init
= spapr_instance_init
,
4545 .instance_finalize
= spapr_machine_finalizefn
,
4546 .class_size
= sizeof(SpaprMachineClass
),
4547 .class_init
= spapr_machine_class_init
,
4548 .interfaces
= (InterfaceInfo
[]) {
4549 { TYPE_FW_PATH_PROVIDER
},
4551 { TYPE_HOTPLUG_HANDLER
},
4552 { TYPE_PPC_VIRTUAL_HYPERVISOR
},
4553 { TYPE_XICS_FABRIC
},
4554 { TYPE_INTERRUPT_STATS_PROVIDER
},
4559 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \
4560 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \
4563 MachineClass *mc = MACHINE_CLASS(oc); \
4564 spapr_machine_##suffix##_class_options(mc); \
4566 mc->alias = "pseries"; \
4567 mc->is_default = 1; \
4570 static const TypeInfo spapr_machine_##suffix##_info = { \
4571 .name = MACHINE_TYPE_NAME("pseries-" verstr), \
4572 .parent = TYPE_SPAPR_MACHINE, \
4573 .class_init = spapr_machine_##suffix##_class_init, \
4575 static void spapr_machine_register_##suffix(void) \
4577 type_register(&spapr_machine_##suffix##_info); \
4579 type_init(spapr_machine_register_##suffix)
4584 static void spapr_machine_4_2_class_options(MachineClass
*mc
)
4586 /* Defaults for the latest behaviour inherited from the base class */
4589 DEFINE_SPAPR_MACHINE(4_2
, "4.2", true);
4594 static void spapr_machine_4_1_class_options(MachineClass
*mc
)
4596 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4597 static GlobalProperty compat
[] = {
4598 /* Only allow 4kiB and 64kiB IOMMU pagesizes */
4599 { TYPE_SPAPR_PCI_HOST_BRIDGE
, "pgsz", "0x11000" },
4602 spapr_machine_4_2_class_options(mc
);
4603 smc
->linux_pci_probe
= false;
4604 compat_props_add(mc
->compat_props
, hw_compat_4_1
, hw_compat_4_1_len
);
4605 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
4608 DEFINE_SPAPR_MACHINE(4_1
, "4.1", false);
4613 static void phb_placement_4_0(SpaprMachineState
*spapr
, uint32_t index
,
4614 uint64_t *buid
, hwaddr
*pio
,
4615 hwaddr
*mmio32
, hwaddr
*mmio64
,
4616 unsigned n_dma
, uint32_t *liobns
,
4617 hwaddr
*nv2gpa
, hwaddr
*nv2atsd
, Error
**errp
)
4619 spapr_phb_placement(spapr
, index
, buid
, pio
, mmio32
, mmio64
, n_dma
, liobns
,
4620 nv2gpa
, nv2atsd
, errp
);
4625 static void spapr_machine_4_0_class_options(MachineClass
*mc
)
4627 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4629 spapr_machine_4_1_class_options(mc
);
4630 compat_props_add(mc
->compat_props
, hw_compat_4_0
, hw_compat_4_0_len
);
4631 smc
->phb_placement
= phb_placement_4_0
;
4632 smc
->irq
= &spapr_irq_xics
;
4633 smc
->pre_4_1_migration
= true;
4636 DEFINE_SPAPR_MACHINE(4_0
, "4.0", false);
4641 static void spapr_machine_3_1_class_options(MachineClass
*mc
)
4643 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4645 spapr_machine_4_0_class_options(mc
);
4646 compat_props_add(mc
->compat_props
, hw_compat_3_1
, hw_compat_3_1_len
);
4648 mc
->default_cpu_type
= POWERPC_CPU_TYPE_NAME("power8_v2.0");
4649 smc
->update_dt_enabled
= false;
4650 smc
->dr_phb_enabled
= false;
4651 smc
->broken_host_serial_model
= true;
4652 smc
->default_caps
.caps
[SPAPR_CAP_CFPC
] = SPAPR_CAP_BROKEN
;
4653 smc
->default_caps
.caps
[SPAPR_CAP_SBBC
] = SPAPR_CAP_BROKEN
;
4654 smc
->default_caps
.caps
[SPAPR_CAP_IBS
] = SPAPR_CAP_BROKEN
;
4655 smc
->default_caps
.caps
[SPAPR_CAP_LARGE_DECREMENTER
] = SPAPR_CAP_OFF
;
4658 DEFINE_SPAPR_MACHINE(3_1
, "3.1", false);
4664 static void spapr_machine_3_0_class_options(MachineClass
*mc
)
4666 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4668 spapr_machine_3_1_class_options(mc
);
4669 compat_props_add(mc
->compat_props
, hw_compat_3_0
, hw_compat_3_0_len
);
4671 smc
->legacy_irq_allocation
= true;
4672 smc
->irq
= &spapr_irq_xics_legacy
;
4675 DEFINE_SPAPR_MACHINE(3_0
, "3.0", false);
4680 static void spapr_machine_2_12_class_options(MachineClass
*mc
)
4682 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4683 static GlobalProperty compat
[] = {
4684 { TYPE_POWERPC_CPU
, "pre-3.0-migration", "on" },
4685 { TYPE_SPAPR_CPU_CORE
, "pre-3.0-migration", "on" },
4688 spapr_machine_3_0_class_options(mc
);
4689 compat_props_add(mc
->compat_props
, hw_compat_2_12
, hw_compat_2_12_len
);
4690 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
4692 /* We depend on kvm_enabled() to choose a default value for the
4693 * hpt-max-page-size capability. Of course we can't do it here
4694 * because this is too early and the HW accelerator isn't initialzed
4695 * yet. Postpone this to machine init (see default_caps_with_cpu()).
4697 smc
->default_caps
.caps
[SPAPR_CAP_HPT_MAXPAGESIZE
] = 0;
4700 DEFINE_SPAPR_MACHINE(2_12
, "2.12", false);
4702 static void spapr_machine_2_12_sxxm_class_options(MachineClass
*mc
)
4704 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4706 spapr_machine_2_12_class_options(mc
);
4707 smc
->default_caps
.caps
[SPAPR_CAP_CFPC
] = SPAPR_CAP_WORKAROUND
;
4708 smc
->default_caps
.caps
[SPAPR_CAP_SBBC
] = SPAPR_CAP_WORKAROUND
;
4709 smc
->default_caps
.caps
[SPAPR_CAP_IBS
] = SPAPR_CAP_FIXED_CCD
;
4712 DEFINE_SPAPR_MACHINE(2_12_sxxm
, "2.12-sxxm", false);
4718 static void spapr_machine_2_11_class_options(MachineClass
*mc
)
4720 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4722 spapr_machine_2_12_class_options(mc
);
4723 smc
->default_caps
.caps
[SPAPR_CAP_HTM
] = SPAPR_CAP_ON
;
4724 compat_props_add(mc
->compat_props
, hw_compat_2_11
, hw_compat_2_11_len
);
4727 DEFINE_SPAPR_MACHINE(2_11
, "2.11", false);
4733 static void spapr_machine_2_10_class_options(MachineClass
*mc
)
4735 spapr_machine_2_11_class_options(mc
);
4736 compat_props_add(mc
->compat_props
, hw_compat_2_10
, hw_compat_2_10_len
);
4739 DEFINE_SPAPR_MACHINE(2_10
, "2.10", false);
4745 static void spapr_machine_2_9_class_options(MachineClass
*mc
)
4747 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4748 static GlobalProperty compat
[] = {
4749 { TYPE_POWERPC_CPU
, "pre-2.10-migration", "on" },
4752 spapr_machine_2_10_class_options(mc
);
4753 compat_props_add(mc
->compat_props
, hw_compat_2_9
, hw_compat_2_9_len
);
4754 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
4755 mc
->numa_auto_assign_ram
= numa_legacy_auto_assign_ram
;
4756 smc
->pre_2_10_has_unused_icps
= true;
4757 smc
->resize_hpt_default
= SPAPR_RESIZE_HPT_DISABLED
;
4760 DEFINE_SPAPR_MACHINE(2_9
, "2.9", false);
4766 static void spapr_machine_2_8_class_options(MachineClass
*mc
)
4768 static GlobalProperty compat
[] = {
4769 { TYPE_SPAPR_PCI_HOST_BRIDGE
, "pcie-extended-configuration-space", "off" },
4772 spapr_machine_2_9_class_options(mc
);
4773 compat_props_add(mc
->compat_props
, hw_compat_2_8
, hw_compat_2_8_len
);
4774 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
4775 mc
->numa_mem_align_shift
= 23;
4778 DEFINE_SPAPR_MACHINE(2_8
, "2.8", false);
4784 static void phb_placement_2_7(SpaprMachineState
*spapr
, uint32_t index
,
4785 uint64_t *buid
, hwaddr
*pio
,
4786 hwaddr
*mmio32
, hwaddr
*mmio64
,
4787 unsigned n_dma
, uint32_t *liobns
,
4788 hwaddr
*nv2gpa
, hwaddr
*nv2atsd
, Error
**errp
)
4790 /* Legacy PHB placement for pseries-2.7 and earlier machine types */
4791 const uint64_t base_buid
= 0x800000020000000ULL
;
4792 const hwaddr phb_spacing
= 0x1000000000ULL
; /* 64 GiB */
4793 const hwaddr mmio_offset
= 0xa0000000; /* 2 GiB + 512 MiB */
4794 const hwaddr pio_offset
= 0x80000000; /* 2 GiB */
4795 const uint32_t max_index
= 255;
4796 const hwaddr phb0_alignment
= 0x10000000000ULL
; /* 1 TiB */
4798 uint64_t ram_top
= MACHINE(spapr
)->ram_size
;
4799 hwaddr phb0_base
, phb_base
;
4802 /* Do we have device memory? */
4803 if (MACHINE(spapr
)->maxram_size
> ram_top
) {
4804 /* Can't just use maxram_size, because there may be an
4805 * alignment gap between normal and device memory regions
4807 ram_top
= MACHINE(spapr
)->device_memory
->base
+
4808 memory_region_size(&MACHINE(spapr
)->device_memory
->mr
);
4811 phb0_base
= QEMU_ALIGN_UP(ram_top
, phb0_alignment
);
4813 if (index
> max_index
) {
4814 error_setg(errp
, "\"index\" for PAPR PHB is too large (max %u)",
4819 *buid
= base_buid
+ index
;
4820 for (i
= 0; i
< n_dma
; ++i
) {
4821 liobns
[i
] = SPAPR_PCI_LIOBN(index
, i
);
4824 phb_base
= phb0_base
+ index
* phb_spacing
;
4825 *pio
= phb_base
+ pio_offset
;
4826 *mmio32
= phb_base
+ mmio_offset
;
4828 * We don't set the 64-bit MMIO window, relying on the PHB's
4829 * fallback behaviour of automatically splitting a large "32-bit"
4830 * window into contiguous 32-bit and 64-bit windows
4837 static void spapr_machine_2_7_class_options(MachineClass
*mc
)
4839 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4840 static GlobalProperty compat
[] = {
4841 { TYPE_SPAPR_PCI_HOST_BRIDGE
, "mem_win_size", "0xf80000000", },
4842 { TYPE_SPAPR_PCI_HOST_BRIDGE
, "mem64_win_size", "0", },
4843 { TYPE_POWERPC_CPU
, "pre-2.8-migration", "on", },
4844 { TYPE_SPAPR_PCI_HOST_BRIDGE
, "pre-2.8-migration", "on", },
4847 spapr_machine_2_8_class_options(mc
);
4848 mc
->default_cpu_type
= POWERPC_CPU_TYPE_NAME("power7_v2.3");
4849 mc
->default_machine_opts
= "modern-hotplug-events=off";
4850 compat_props_add(mc
->compat_props
, hw_compat_2_7
, hw_compat_2_7_len
);
4851 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
4852 smc
->phb_placement
= phb_placement_2_7
;
4855 DEFINE_SPAPR_MACHINE(2_7
, "2.7", false);
4861 static void spapr_machine_2_6_class_options(MachineClass
*mc
)
4863 static GlobalProperty compat
[] = {
4864 { TYPE_SPAPR_PCI_HOST_BRIDGE
, "ddw", "off" },
4867 spapr_machine_2_7_class_options(mc
);
4868 mc
->has_hotpluggable_cpus
= false;
4869 compat_props_add(mc
->compat_props
, hw_compat_2_6
, hw_compat_2_6_len
);
4870 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
4873 DEFINE_SPAPR_MACHINE(2_6
, "2.6", false);
4879 static void spapr_machine_2_5_class_options(MachineClass
*mc
)
4881 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4882 static GlobalProperty compat
[] = {
4883 { "spapr-vlan", "use-rx-buffer-pools", "off" },
4886 spapr_machine_2_6_class_options(mc
);
4887 smc
->use_ohci_by_default
= true;
4888 compat_props_add(mc
->compat_props
, hw_compat_2_5
, hw_compat_2_5_len
);
4889 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
4892 DEFINE_SPAPR_MACHINE(2_5
, "2.5", false);
4898 static void spapr_machine_2_4_class_options(MachineClass
*mc
)
4900 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4902 spapr_machine_2_5_class_options(mc
);
4903 smc
->dr_lmb_enabled
= false;
4904 compat_props_add(mc
->compat_props
, hw_compat_2_4
, hw_compat_2_4_len
);
4907 DEFINE_SPAPR_MACHINE(2_4
, "2.4", false);
4913 static void spapr_machine_2_3_class_options(MachineClass
*mc
)
4915 static GlobalProperty compat
[] = {
4916 { "spapr-pci-host-bridge", "dynamic-reconfiguration", "off" },
4918 spapr_machine_2_4_class_options(mc
);
4919 compat_props_add(mc
->compat_props
, hw_compat_2_3
, hw_compat_2_3_len
);
4920 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
4922 DEFINE_SPAPR_MACHINE(2_3
, "2.3", false);
4928 static void spapr_machine_2_2_class_options(MachineClass
*mc
)
4930 static GlobalProperty compat
[] = {
4931 { TYPE_SPAPR_PCI_HOST_BRIDGE
, "mem_win_size", "0x20000000" },
4934 spapr_machine_2_3_class_options(mc
);
4935 compat_props_add(mc
->compat_props
, hw_compat_2_2
, hw_compat_2_2_len
);
4936 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
4937 mc
->default_machine_opts
= "modern-hotplug-events=off,suppress-vmdesc=on";
4939 DEFINE_SPAPR_MACHINE(2_2
, "2.2", false);
4945 static void spapr_machine_2_1_class_options(MachineClass
*mc
)
4947 spapr_machine_2_2_class_options(mc
);
4948 compat_props_add(mc
->compat_props
, hw_compat_2_1
, hw_compat_2_1_len
);
4950 DEFINE_SPAPR_MACHINE(2_1
, "2.1", false);
4952 static void spapr_machine_register_types(void)
4954 type_register_static(&spapr_machine_info
);
4957 type_init(spapr_machine_register_types
)