target/tricore/cpu.c

   1 /*
   2  *  TriCore emulation for qemu: main translation routines.
   3  *
   4  *  Copyright (c) 2012-2014 Bastian Koppelmann C-Lab/University Paderborn
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "qapi/error.h"
  22 #include "cpu.h"
  23 #include "exec/exec-all.h"
  24 #include "qemu/error-report.h"
  25 #include "tcg/debug-assert.h"
  26
  27 static inline void set_feature(CPUTriCoreState *env, int feature)
  28 {
  29     env->features |= 1ULL << feature;
  30 }
  31
  32 static const gchar *tricore_gdb_arch_name(CPUState *cs)
  33 {
  34     return "tricore";
  35 }
  36
  37 static void tricore_cpu_set_pc(CPUState *cs, vaddr value)
  38 {
  39     TriCoreCPU *cpu = TRICORE_CPU(cs);
  40     CPUTriCoreState *env = &cpu->env;
  41
  42     env->PC = value & ~(target_ulong)1;
  43 }
  44
  45 static vaddr tricore_cpu_get_pc(CPUState *cs)
  46 {
  47     TriCoreCPU *cpu = TRICORE_CPU(cs);
  48     CPUTriCoreState *env = &cpu->env;
  49
  50     return env->PC;
  51 }
  52
  53 static void tricore_cpu_synchronize_from_tb(CPUState *cs,
  54                                             const TranslationBlock *tb)
  55 {
  56     TriCoreCPU *cpu = TRICORE_CPU(cs);
  57     CPUTriCoreState *env = &cpu->env;
  58
  59     tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));
  60     env->PC = tb->pc;
  61 }
  62
  63 static void tricore_restore_state_to_opc(CPUState *cs,
  64                                          const TranslationBlock *tb,
  65                                          const uint64_t *data)
  66 {
  67     TriCoreCPU *cpu = TRICORE_CPU(cs);
  68     CPUTriCoreState *env = &cpu->env;
  69
  70     env->PC = data[0];
  71 }
  72
  73 static void tricore_cpu_reset_hold(Object *obj)
  74 {
  75     CPUState *s = CPU(obj);
  76     TriCoreCPU *cpu = TRICORE_CPU(s);
  77     TriCoreCPUClass *tcc = TRICORE_CPU_GET_CLASS(cpu);
  78     CPUTriCoreState *env = &cpu->env;
  79
  80     if (tcc->parent_phases.hold) {
  81         tcc->parent_phases.hold(obj);
  82     }
  83
  84     cpu_state_reset(env);
  85 }
  86
  87 static bool tricore_cpu_has_work(CPUState *cs)
  88 {
  89     return true;
  90 }
  91
  92 static int tricore_cpu_mmu_index(CPUState *cs, bool ifetch)
  93 {
  94     return 0;
  95 }
  96
  97 static void tricore_cpu_realizefn(DeviceState *dev, Error **errp)
  98 {
  99     CPUState *cs = CPU(dev);
 100     TriCoreCPU *cpu = TRICORE_CPU(dev);
 101     TriCoreCPUClass *tcc = TRICORE_CPU_GET_CLASS(dev);
 102     CPUTriCoreState *env = &cpu->env;
 103     Error *local_err = NULL;
 104
 105     cpu_exec_realizefn(cs, &local_err);
 106     if (local_err != NULL) {
 107         error_propagate(errp, local_err);
 108         return;
 109     }
 110
 111     /* Some features automatically imply others */
 112     if (tricore_has_feature(env, TRICORE_FEATURE_162)) {
 113         set_feature(env, TRICORE_FEATURE_161);
 114     }
 115
 116     if (tricore_has_feature(env, TRICORE_FEATURE_161)) {
 117         set_feature(env, TRICORE_FEATURE_16);
 118     }
 119
 120     if (tricore_has_feature(env, TRICORE_FEATURE_16)) {
 121         set_feature(env, TRICORE_FEATURE_131);
 122     }
 123     if (tricore_has_feature(env, TRICORE_FEATURE_131)) {
 124         set_feature(env, TRICORE_FEATURE_13);
 125     }
 126     cpu_reset(cs);
 127     qemu_init_vcpu(cs);
 128
 129     tcc->parent_realize(dev, errp);
 130 }
 131
 132 static ObjectClass *tricore_cpu_class_by_name(const char *cpu_model)
 133 {
 134     ObjectClass *oc;
 135     char *typename;
 136
 137     typename = g_strdup_printf(TRICORE_CPU_TYPE_NAME("%s"), cpu_model);
 138     oc = object_class_by_name(typename);
 139     g_free(typename);
 140
 141     return oc;
 142 }
 143
 144 static void tc1796_initfn(Object *obj)
 145 {
 146     TriCoreCPU *cpu = TRICORE_CPU(obj);
 147
 148     set_feature(&cpu->env, TRICORE_FEATURE_13);
 149 }
 150
 151 static void tc1797_initfn(Object *obj)
 152 {
 153     TriCoreCPU *cpu = TRICORE_CPU(obj);
 154
 155     set_feature(&cpu->env, TRICORE_FEATURE_131);
 156 }
 157
 158 static void tc27x_initfn(Object *obj)
 159 {
 160     TriCoreCPU *cpu = TRICORE_CPU(obj);
 161
 162     set_feature(&cpu->env, TRICORE_FEATURE_161);
 163 }
 164
 165 static void tc37x_initfn(Object *obj)
 166 {
 167     TriCoreCPU *cpu = TRICORE_CPU(obj);
 168
 169     set_feature(&cpu->env, TRICORE_FEATURE_162);
 170 }
 171
 172
 173 #include "hw/core/sysemu-cpu-ops.h"
 174
 175 static const struct SysemuCPUOps tricore_sysemu_ops = {
 176     .get_phys_page_debug = tricore_cpu_get_phys_page_debug,
 177 };
 178
 179 #include "hw/core/tcg-cpu-ops.h"
 180
 181 static const TCGCPUOps tricore_tcg_ops = {
 182     .initialize = tricore_tcg_init,
 183     .synchronize_from_tb = tricore_cpu_synchronize_from_tb,
 184     .restore_state_to_opc = tricore_restore_state_to_opc,
 185     .tlb_fill = tricore_cpu_tlb_fill,
 186 };
 187
 188 static void tricore_cpu_class_init(ObjectClass *c, void *data)
 189 {
 190     TriCoreCPUClass *mcc = TRICORE_CPU_CLASS(c);
 191     CPUClass *cc = CPU_CLASS(c);
 192     DeviceClass *dc = DEVICE_CLASS(c);
 193     ResettableClass *rc = RESETTABLE_CLASS(c);
 194
 195     device_class_set_parent_realize(dc, tricore_cpu_realizefn,
 196                                     &mcc->parent_realize);
 197
 198     resettable_class_set_parent_phases(rc, NULL, tricore_cpu_reset_hold, NULL,
 199                                        &mcc->parent_phases);
 200     cc->class_by_name = tricore_cpu_class_by_name;
 201     cc->has_work = tricore_cpu_has_work;
 202     cc->mmu_index = tricore_cpu_mmu_index;
 203
 204     cc->gdb_read_register = tricore_cpu_gdb_read_register;
 205     cc->gdb_write_register = tricore_cpu_gdb_write_register;
 206     cc->gdb_num_core_regs = 44;
 207     cc->gdb_arch_name = tricore_gdb_arch_name;
 208
 209     cc->dump_state = tricore_cpu_dump_state;
 210     cc->set_pc = tricore_cpu_set_pc;
 211     cc->get_pc = tricore_cpu_get_pc;
 212     cc->sysemu_ops = &tricore_sysemu_ops;
 213     cc->tcg_ops = &tricore_tcg_ops;
 214 }
 215
 216 #define DEFINE_TRICORE_CPU_TYPE(cpu_model, initfn) \
 217     {                                              \
 218         .parent = TYPE_TRICORE_CPU,                \
 219         .instance_init = initfn,                   \
 220         .name = TRICORE_CPU_TYPE_NAME(cpu_model),  \
 221     }
 222
 223 static const TypeInfo tricore_cpu_type_infos[] = {
 224     {
 225         .name = TYPE_TRICORE_CPU,
 226         .parent = TYPE_CPU,
 227         .instance_size = sizeof(TriCoreCPU),
 228         .instance_align = __alignof(TriCoreCPU),
 229         .abstract = true,
 230         .class_size = sizeof(TriCoreCPUClass),
 231         .class_init = tricore_cpu_class_init,
 232     },
 233     DEFINE_TRICORE_CPU_TYPE("tc1796", tc1796_initfn),
 234     DEFINE_TRICORE_CPU_TYPE("tc1797", tc1797_initfn),
 235     DEFINE_TRICORE_CPU_TYPE("tc27x", tc27x_initfn),
 236     DEFINE_TRICORE_CPU_TYPE("tc37x", tc37x_initfn),
 237 };
 238
 239 DEFINE_TYPES(tricore_cpu_type_infos)