hw/char/sh_serial.c

   1 /*
   2  * QEMU SCI/SCIF serial port emulation
   3  *
   4  * Copyright (c) 2007 Magnus Damm
   5  *
   6  * Based on serial.c - QEMU 16450 UART emulation
   7  * Copyright (c) 2003-2004 Fabrice Bellard
   8  *
   9  * Permission is hereby granted, free of charge, to any person obtaining a copy
  10  * of this software and associated documentation files (the "Software"), to deal
  11  * in the Software without restriction, including without limitation the rights
  12  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  13  * copies of the Software, and to permit persons to whom the Software is
  14  * furnished to do so, subject to the following conditions:
  15  *
  16  * The above copyright notice and this permission notice shall be included in
  17  * all copies or substantial portions of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  24  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  25  * THE SOFTWARE.
  26  */
  27
  28 #include "qemu/osdep.h"
  29 #include "hw/irq.h"
  30 #include "hw/sh4/sh.h"
  31 #include "chardev/char-fe.h"
  32 #include "qapi/error.h"
  33 #include "qemu/timer.h"
  34 #include "qemu/log.h"
  35 #include "trace.h"
  36
  37 #define SH_SERIAL_FLAG_TEND (1 << 0)
  38 #define SH_SERIAL_FLAG_TDE  (1 << 1)
  39 #define SH_SERIAL_FLAG_RDF  (1 << 2)
  40 #define SH_SERIAL_FLAG_BRK  (1 << 3)
  41 #define SH_SERIAL_FLAG_DR   (1 << 4)
  42
  43 #define SH_RX_FIFO_LENGTH (16)
  44
  45 typedef struct {
  46     MemoryRegion iomem;
  47     MemoryRegion iomem_p4;
  48     MemoryRegion iomem_a7;
  49     uint8_t smr;
  50     uint8_t brr;
  51     uint8_t scr;
  52     uint8_t dr; /* ftdr / tdr */
  53     uint8_t sr; /* fsr / ssr */
  54     uint16_t fcr;
  55     uint8_t sptr;
  56
  57     uint8_t rx_fifo[SH_RX_FIFO_LENGTH]; /* frdr / rdr */
  58     uint8_t rx_cnt;
  59     uint8_t rx_tail;
  60     uint8_t rx_head;
  61
  62     int freq;
  63     int feat;
  64     int flags;
  65     int rtrg;
  66
  67     CharBackend chr;
  68     QEMUTimer fifo_timeout_timer;
  69     uint64_t etu; /* Elementary Time Unit (ns) */
  70
  71     qemu_irq eri;
  72     qemu_irq rxi;
  73     qemu_irq txi;
  74     qemu_irq tei;
  75     qemu_irq bri;
  76 } SHSerialState;
  77
  78 static void sh_serial_clear_fifo(SHSerialState *s)
  79 {
  80     memset(s->rx_fifo, 0, SH_RX_FIFO_LENGTH);
  81     s->rx_cnt = 0;
  82     s->rx_head = 0;
  83     s->rx_tail = 0;
  84 }
  85
  86 static void sh_serial_write(void *opaque, hwaddr offs,
  87                             uint64_t val, unsigned size)
  88 {
  89     SHSerialState *s = opaque;
  90     unsigned char ch;
  91
  92     trace_sh_serial_write(size, offs, val);
  93     switch (offs) {
  94     case 0x00: /* SMR */
  95         s->smr = val & ((s->feat & SH_SERIAL_FEAT_SCIF) ? 0x7b : 0xff);
  96         return;
  97     case 0x04: /* BRR */
  98         s->brr = val;
  99         return;
 100     case 0x08: /* SCR */
 101         /* TODO : For SH7751, SCIF mask should be 0xfb. */
 102         s->scr = val & ((s->feat & SH_SERIAL_FEAT_SCIF) ? 0xfa : 0xff);
 103         if (!(val & (1 << 5))) {
 104             s->flags |= SH_SERIAL_FLAG_TEND;
 105         }
 106         if ((s->feat & SH_SERIAL_FEAT_SCIF) && s->txi) {
 107             qemu_set_irq(s->txi, val & (1 << 7));
 108         }
 109         if (!(val & (1 << 6))) {
 110             qemu_set_irq(s->rxi, 0);
 111         }
 112         return;
 113     case 0x0c: /* FTDR / TDR */
 114         if (qemu_chr_fe_backend_connected(&s->chr)) {
 115             ch = val;
 116             /*
 117              * XXX this blocks entire thread. Rewrite to use
 118              * qemu_chr_fe_write and background I/O callbacks
 119              */
 120             qemu_chr_fe_write_all(&s->chr, &ch, 1);
 121         }
 122         s->dr = val;
 123         s->flags &= ~SH_SERIAL_FLAG_TDE;
 124         return;
 125 #if 0
 126     case 0x14: /* FRDR / RDR */
 127         ret = 0;
 128         break;
 129 #endif
 130     }
 131     if (s->feat & SH_SERIAL_FEAT_SCIF) {
 132         switch (offs) {
 133         case 0x10: /* FSR */
 134             if (!(val & (1 << 6))) {
 135                 s->flags &= ~SH_SERIAL_FLAG_TEND;
 136             }
 137             if (!(val & (1 << 5))) {
 138                 s->flags &= ~SH_SERIAL_FLAG_TDE;
 139             }
 140             if (!(val & (1 << 4))) {
 141                 s->flags &= ~SH_SERIAL_FLAG_BRK;
 142             }
 143             if (!(val & (1 << 1))) {
 144                 s->flags &= ~SH_SERIAL_FLAG_RDF;
 145             }
 146             if (!(val & (1 << 0))) {
 147                 s->flags &= ~SH_SERIAL_FLAG_DR;
 148             }
 149
 150             if (!(val & (1 << 1)) || !(val & (1 << 0))) {
 151                 if (s->rxi) {
 152                     qemu_set_irq(s->rxi, 0);
 153                 }
 154             }
 155             return;
 156         case 0x18: /* FCR */
 157             s->fcr = val;
 158             switch ((val >> 6) & 3) {
 159             case 0:
 160                 s->rtrg = 1;
 161                 break;
 162             case 1:
 163                 s->rtrg = 4;
 164                 break;
 165             case 2:
 166                 s->rtrg = 8;
 167                 break;
 168             case 3:
 169                 s->rtrg = 14;
 170                 break;
 171             }
 172             if (val & (1 << 1)) {
 173                 sh_serial_clear_fifo(s);
 174                 s->sr &= ~(1 << 1);
 175             }
 176
 177             return;
 178         case 0x20: /* SPTR */
 179             s->sptr = val & 0xf3;
 180             return;
 181         case 0x24: /* LSR */
 182             return;
 183         }
 184     } else {
 185         switch (offs) {
 186 #if 0
 187         case 0x0c:
 188             ret = s->dr;
 189             break;
 190         case 0x10:
 191             ret = 0;
 192             break;
 193 #endif
 194         case 0x1c:
 195             s->sptr = val & 0x8f;
 196             return;
 197         }
 198     }
 199     qemu_log_mask(LOG_GUEST_ERROR,
 200                   "%s: unsupported write to 0x%02" HWADDR_PRIx "\n",
 201                   __func__, offs);
 202 }
 203
 204 static uint64_t sh_serial_read(void *opaque, hwaddr offs,
 205                                unsigned size)
 206 {
 207     SHSerialState *s = opaque;
 208     uint32_t ret = UINT32_MAX;
 209
 210 #if 0
 211     switch (offs) {
 212     case 0x00:
 213         ret = s->smr;
 214         break;
 215     case 0x04:
 216         ret = s->brr;
 217         break;
 218     case 0x08:
 219         ret = s->scr;
 220         break;
 221     case 0x14:
 222         ret = 0;
 223         break;
 224     }
 225 #endif
 226     if (s->feat & SH_SERIAL_FEAT_SCIF) {
 227         switch (offs) {
 228         case 0x00: /* SMR */
 229             ret = s->smr;
 230             break;
 231         case 0x08: /* SCR */
 232             ret = s->scr;
 233             break;
 234         case 0x10: /* FSR */
 235             ret = 0;
 236             if (s->flags & SH_SERIAL_FLAG_TEND) {
 237                 ret |= (1 << 6);
 238             }
 239             if (s->flags & SH_SERIAL_FLAG_TDE) {
 240                 ret |= (1 << 5);
 241             }
 242             if (s->flags & SH_SERIAL_FLAG_BRK) {
 243                 ret |= (1 << 4);
 244             }
 245             if (s->flags & SH_SERIAL_FLAG_RDF) {
 246                 ret |= (1 << 1);
 247             }
 248             if (s->flags & SH_SERIAL_FLAG_DR) {
 249                 ret |= (1 << 0);
 250             }
 251
 252             if (s->scr & (1 << 5)) {
 253                 s->flags |= SH_SERIAL_FLAG_TDE | SH_SERIAL_FLAG_TEND;
 254             }
 255
 256             break;
 257         case 0x14:
 258             if (s->rx_cnt > 0) {
 259                 ret = s->rx_fifo[s->rx_tail++];
 260                 s->rx_cnt--;
 261                 if (s->rx_tail == SH_RX_FIFO_LENGTH) {
 262                     s->rx_tail = 0;
 263                 }
 264                 if (s->rx_cnt < s->rtrg) {
 265                     s->flags &= ~SH_SERIAL_FLAG_RDF;
 266                 }
 267             }
 268             break;
 269         case 0x18:
 270             ret = s->fcr;
 271             break;
 272         case 0x1c:
 273             ret = s->rx_cnt;
 274             break;
 275         case 0x20:
 276             ret = s->sptr;
 277             break;
 278         case 0x24:
 279             ret = 0;
 280             break;
 281         }
 282     } else {
 283         switch (offs) {
 284 #if 0
 285         case 0x0c:
 286             ret = s->dr;
 287             break;
 288         case 0x10:
 289             ret = 0;
 290             break;
 291         case 0x14:
 292             ret = s->rx_fifo[0];
 293             break;
 294 #endif
 295         case 0x1c:
 296             ret = s->sptr;
 297             break;
 298         }
 299     }
 300     trace_sh_serial_read(size, offs, ret);
 301
 302     if (ret > UINT16_MAX) {
 303         qemu_log_mask(LOG_GUEST_ERROR,
 304                       "%s: unsupported read from 0x%02" HWADDR_PRIx "\n",
 305                       __func__, offs);
 306         ret = 0;
 307     }
 308
 309     return ret;
 310 }
 311
 312 static int sh_serial_can_receive(SHSerialState *s)
 313 {
 314     return s->scr & (1 << 4);
 315 }
 316
 317 static void sh_serial_receive_break(SHSerialState *s)
 318 {
 319     if (s->feat & SH_SERIAL_FEAT_SCIF) {
 320         s->sr |= (1 << 4);
 321     }
 322 }
 323
 324 static int sh_serial_can_receive1(void *opaque)
 325 {
 326     SHSerialState *s = opaque;
 327     return sh_serial_can_receive(s);
 328 }
 329
 330 static void sh_serial_timeout_int(void *opaque)
 331 {
 332     SHSerialState *s = opaque;
 333
 334     s->flags |= SH_SERIAL_FLAG_RDF;
 335     if (s->scr & (1 << 6) && s->rxi) {
 336         qemu_set_irq(s->rxi, 1);
 337     }
 338 }
 339
 340 static void sh_serial_receive1(void *opaque, const uint8_t *buf, int size)
 341 {
 342     SHSerialState *s = opaque;
 343
 344     if (s->feat & SH_SERIAL_FEAT_SCIF) {
 345         int i;
 346         for (i = 0; i < size; i++) {
 347             if (s->rx_cnt < SH_RX_FIFO_LENGTH) {
 348                 s->rx_fifo[s->rx_head++] = buf[i];
 349                 if (s->rx_head == SH_RX_FIFO_LENGTH) {
 350                     s->rx_head = 0;
 351                 }
 352                 s->rx_cnt++;
 353                 if (s->rx_cnt >= s->rtrg) {
 354                     s->flags |= SH_SERIAL_FLAG_RDF;
 355                     if (s->scr & (1 << 6) && s->rxi) {
 356                         timer_del(&s->fifo_timeout_timer);
 357                         qemu_set_irq(s->rxi, 1);
 358                     }
 359                 } else {
 360                     timer_mod(&s->fifo_timeout_timer,
 361                         qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 15 * s->etu);
 362                 }
 363             }
 364         }
 365     } else {
 366         s->rx_fifo[0] = buf[0];
 367     }
 368 }
 369
 370 static void sh_serial_event(void *opaque, QEMUChrEvent event)
 371 {
 372     SHSerialState *s = opaque;
 373     if (event == CHR_EVENT_BREAK) {
 374         sh_serial_receive_break(s);
 375     }
 376 }
 377
 378 static const MemoryRegionOps sh_serial_ops = {
 379     .read = sh_serial_read,
 380     .write = sh_serial_write,
 381     .endianness = DEVICE_NATIVE_ENDIAN,
 382 };
 383
 384 void sh_serial_init(MemoryRegion *sysmem,
 385                     hwaddr base, int feat,
 386                     uint32_t freq, Chardev *chr,
 387                     qemu_irq eri_source,
 388                     qemu_irq rxi_source,
 389                     qemu_irq txi_source,
 390                     qemu_irq tei_source,
 391                     qemu_irq bri_source)
 392 {
 393     SHSerialState *s = g_malloc0(sizeof(*s));
 394
 395     s->feat = feat;
 396     s->flags = SH_SERIAL_FLAG_TEND | SH_SERIAL_FLAG_TDE;
 397     s->rtrg = 1;
 398
 399     s->smr = 0;
 400     s->brr = 0xff;
 401     s->scr = 1 << 5; /* pretend that TX is enabled so early printk works */
 402     s->sptr = 0;
 403
 404     if (feat & SH_SERIAL_FEAT_SCIF) {
 405         s->fcr = 0;
 406     } else {
 407         s->dr = 0xff;
 408     }
 409
 410     sh_serial_clear_fifo(s);
 411
 412     memory_region_init_io(&s->iomem, NULL, &sh_serial_ops, s,
 413                           "serial", 0x100000000ULL);
 414
 415     memory_region_init_alias(&s->iomem_p4, NULL, "serial-p4", &s->iomem,
 416                              0, 0x28);
 417     memory_region_add_subregion(sysmem, P4ADDR(base), &s->iomem_p4);
 418
 419     memory_region_init_alias(&s->iomem_a7, NULL, "serial-a7", &s->iomem,
 420                              0, 0x28);
 421     memory_region_add_subregion(sysmem, A7ADDR(base), &s->iomem_a7);
 422
 423     if (chr) {
 424         qemu_chr_fe_init(&s->chr, chr, &error_abort);
 425         qemu_chr_fe_set_handlers(&s->chr, sh_serial_can_receive1,
 426                                  sh_serial_receive1,
 427                                  sh_serial_event, NULL, s, NULL, true);
 428     }
 429
 430     timer_init_ns(&s->fifo_timeout_timer, QEMU_CLOCK_VIRTUAL,
 431                   sh_serial_timeout_int, s);
 432     s->etu = NANOSECONDS_PER_SECOND / 9600;
 433     s->eri = eri_source;
 434     s->rxi = rxi_source;
 435     s->txi = txi_source;
 436     s->tei = tei_source;
 437     s->bri = bri_source;
 438 }