?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Merge tag 'pull-ppc-for-9.0-2-20240313' of https://gitlab.com/npiggin/qemu into staging
[qemu/armbru.git] / target / ppc / cpu_init.c
blob7e65f08147f154fc68c5187bf6d34749df5a4248
1 /*
2 * PowerPC CPU initialization for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2.1 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "disas/dis-asm.h"
23 #include "gdbstub/helpers.h"
24 #include "sysemu/cpus.h"
25 #include "sysemu/hw_accel.h"
26 #include "sysemu/tcg.h"
27 #include "cpu-models.h"
28 #include "mmu-hash32.h"
29 #include "mmu-hash64.h"
30 #include "qemu/error-report.h"
31 #include "qemu/module.h"
32 #include "qemu/qemu-print.h"
33 #include "qapi/error.h"
34 #include "qapi/qmp/qnull.h"
35 #include "qapi/visitor.h"
36 #include "hw/qdev-properties.h"
37 #include "hw/ppc/ppc.h"
38 #include "mmu-book3s-v3.h"
39 #include "qemu/cutils.h"
40 #include "disas/capstone.h"
41 #include "fpu/softfloat.h"
42
43 #include "helper_regs.h"
44 #include "internal.h"
45 #include "spr_common.h"
46 #include "power8-pmu.h"
47
48 #ifndef CONFIG_USER_ONLY
49 #include "hw/boards.h"
50 #include "hw/intc/intc.h"
51 #include "kvm_ppc.h"
52 #endif
53
54 /* #define PPC_DEBUG_SPR */
55 /* #define USE_APPLE_GDB */
56
57 static inline void vscr_init(CPUPPCState *env, uint32_t val)
58 {
59 /* Altivec always uses round-to-nearest */
60 set_float_rounding_mode(float_round_nearest_even, &env->vec_status);
61 ppc_store_vscr(env, val);
62 }
63
64 static void register_745_sprs(CPUPPCState *env)
65 {
66 /* SGPRs */
67 spr_register(env, SPR_SPRG4, "SPRG4",
68 SPR_NOACCESS, SPR_NOACCESS,
69 &spr_read_generic, &spr_write_generic,
70 0x00000000);
71 spr_register(env, SPR_SPRG5, "SPRG5",
72 SPR_NOACCESS, SPR_NOACCESS,
73 &spr_read_generic, &spr_write_generic,
74 0x00000000);
75 spr_register(env, SPR_SPRG6, "SPRG6",
76 SPR_NOACCESS, SPR_NOACCESS,
77 &spr_read_generic, &spr_write_generic,
78 0x00000000);
79 spr_register(env, SPR_SPRG7, "SPRG7",
80 SPR_NOACCESS, SPR_NOACCESS,
81 &spr_read_generic, &spr_write_generic,
82 0x00000000);
83
84 /* Hardware implementation registers */
85 spr_register(env, SPR_HID0, "HID0",
86 SPR_NOACCESS, SPR_NOACCESS,
87 &spr_read_generic, &spr_write_generic,
88 0x00000000);
89
90 spr_register(env, SPR_HID1, "HID1",
91 SPR_NOACCESS, SPR_NOACCESS,
92 &spr_read_generic, &spr_write_generic,
93 0x00000000);
94
95 spr_register(env, SPR_HID2, "HID2",
96 SPR_NOACCESS, SPR_NOACCESS,
97 &spr_read_generic, &spr_write_generic,
98 0x00000000);
99 }
100
101 static void register_755_sprs(CPUPPCState *env)
102 {
103 /* L2 cache control */
104 spr_register(env, SPR_L2CR, "L2CR",
105 SPR_NOACCESS, SPR_NOACCESS,
106 &spr_read_generic, spr_access_nop,
107 0x00000000);
108
109 spr_register(env, SPR_L2PMCR, "L2PMCR",
110 SPR_NOACCESS, SPR_NOACCESS,
111 &spr_read_generic, &spr_write_generic,
112 0x00000000);
113 }
114
115 /* SPR common to all 7xx PowerPC implementations */
116 static void register_7xx_sprs(CPUPPCState *env)
117 {
118 /* Breakpoints */
119 spr_register_kvm(env, SPR_DABR, "DABR",
120 SPR_NOACCESS, SPR_NOACCESS,
121 &spr_read_generic, &spr_write_generic,
122 KVM_REG_PPC_DABR, 0x00000000);
123
124 spr_register(env, SPR_IABR, "IABR",
125 SPR_NOACCESS, SPR_NOACCESS,
126 &spr_read_generic, &spr_write_generic,
127 0x00000000);
128 /* Cache management */
129 spr_register(env, SPR_ICTC, "ICTC",
130 SPR_NOACCESS, SPR_NOACCESS,
131 &spr_read_generic, &spr_write_generic,
132 0x00000000);
133 /* Performance monitors */
134 spr_register(env, SPR_7XX_MMCR0, "MMCR0",
135 SPR_NOACCESS, SPR_NOACCESS,
136 &spr_read_generic, &spr_write_generic,
137 0x00000000);
138
139 spr_register(env, SPR_7XX_MMCR1, "MMCR1",
140 SPR_NOACCESS, SPR_NOACCESS,
141 &spr_read_generic, &spr_write_generic,
142 0x00000000);
143
144 spr_register(env, SPR_7XX_PMC1, "PMC1",
145 SPR_NOACCESS, SPR_NOACCESS,
146 &spr_read_generic, &spr_write_generic,
147 0x00000000);
148
149 spr_register(env, SPR_7XX_PMC2, "PMC2",
150 SPR_NOACCESS, SPR_NOACCESS,
151 &spr_read_generic, &spr_write_generic,
152 0x00000000);
153
154 spr_register(env, SPR_7XX_PMC3, "PMC3",
155 SPR_NOACCESS, SPR_NOACCESS,
156 &spr_read_generic, &spr_write_generic,
157 0x00000000);
158
159 spr_register(env, SPR_7XX_PMC4, "PMC4",
160 SPR_NOACCESS, SPR_NOACCESS,
161 &spr_read_generic, &spr_write_generic,
162 0x00000000);
163
164 spr_register(env, SPR_7XX_SIAR, "SIAR",
165 SPR_NOACCESS, SPR_NOACCESS,
166 &spr_read_generic, SPR_NOACCESS,
167 0x00000000);
168
169 spr_register(env, SPR_7XX_UMMCR0, "UMMCR0",
170 &spr_read_ureg, SPR_NOACCESS,
171 &spr_read_ureg, SPR_NOACCESS,
172 0x00000000);
173
174 spr_register(env, SPR_7XX_UMMCR1, "UMMCR1",
175 &spr_read_ureg, SPR_NOACCESS,
176 &spr_read_ureg, SPR_NOACCESS,
177 0x00000000);
178
179 spr_register(env, SPR_7XX_UPMC1, "UPMC1",
180 &spr_read_ureg, SPR_NOACCESS,
181 &spr_read_ureg, SPR_NOACCESS,
182 0x00000000);
183
184 spr_register(env, SPR_7XX_UPMC2, "UPMC2",
185 &spr_read_ureg, SPR_NOACCESS,
186 &spr_read_ureg, SPR_NOACCESS,
187 0x00000000);
188
189 spr_register(env, SPR_7XX_UPMC3, "UPMC3",
190 &spr_read_ureg, SPR_NOACCESS,
191 &spr_read_ureg, SPR_NOACCESS,
192 0x00000000);
193
194 spr_register(env, SPR_7XX_UPMC4, "UPMC4",
195 &spr_read_ureg, SPR_NOACCESS,
196 &spr_read_ureg, SPR_NOACCESS,
197 0x00000000);
198
199 spr_register(env, SPR_7XX_USIAR, "USIAR",
200 &spr_read_ureg, SPR_NOACCESS,
201 &spr_read_ureg, SPR_NOACCESS,
202 0x00000000);
203 /* External access control */
204 spr_register(env, SPR_EAR, "EAR",
205 SPR_NOACCESS, SPR_NOACCESS,
206 &spr_read_generic, &spr_write_generic,
207 0x00000000);
208
209 /* Hardware implementation registers */
210 spr_register(env, SPR_HID0, "HID0",
211 SPR_NOACCESS, SPR_NOACCESS,
212 &spr_read_generic, &spr_write_generic,
213 0x00000000);
214
215 spr_register(env, SPR_HID1, "HID1",
216 SPR_NOACCESS, SPR_NOACCESS,
217 &spr_read_generic, &spr_write_generic,
218 0x00000000);
219 }
220
221 #ifdef TARGET_PPC64
222 static void register_amr_sprs(CPUPPCState *env)
223 {
224 #ifndef CONFIG_USER_ONLY
225 /*
226 * Virtual Page Class Key protection
227 *
228 * The AMR is accessible either via SPR 13 or SPR 29. 13 is
229 * userspace accessible, 29 is privileged. So we only need to set
230 * the kvm ONE_REG id on one of them, we use 29
231 */
232 spr_register(env, SPR_UAMR, "UAMR",
233 &spr_read_generic, &spr_write_amr,
234 &spr_read_generic, &spr_write_amr,
235 0);
236 spr_register_kvm_hv(env, SPR_AMR, "AMR",
237 SPR_NOACCESS, SPR_NOACCESS,
238 &spr_read_generic, &spr_write_amr,
239 &spr_read_generic, &spr_write_generic,
240 KVM_REG_PPC_AMR, 0);
241 spr_register_kvm_hv(env, SPR_UAMOR, "UAMOR",
242 SPR_NOACCESS, SPR_NOACCESS,
243 &spr_read_generic, &spr_write_uamor,
244 &spr_read_generic, &spr_write_generic,
245 KVM_REG_PPC_UAMOR, 0);
246 spr_register_hv(env, SPR_AMOR, "AMOR",
247 SPR_NOACCESS, SPR_NOACCESS,
248 SPR_NOACCESS, SPR_NOACCESS,
249 &spr_read_generic, &spr_write_generic,
250 0);
251 #endif /* !CONFIG_USER_ONLY */
252 }
253
254 static void register_iamr_sprs(CPUPPCState *env)
255 {
256 #ifndef CONFIG_USER_ONLY
257 spr_register_kvm_hv(env, SPR_IAMR, "IAMR",
258 SPR_NOACCESS, SPR_NOACCESS,
259 &spr_read_generic, &spr_write_iamr,
260 &spr_read_generic, &spr_write_generic,
261 KVM_REG_PPC_IAMR, 0);
262 #endif /* !CONFIG_USER_ONLY */
263 }
264 #endif /* TARGET_PPC64 */
265
266 /* SPR specific to PowerPC 604 implementation */
267 static void register_604_sprs(CPUPPCState *env)
268 {
269 /* Processor identification */
270 spr_register(env, SPR_PIR, "PIR",
271 SPR_NOACCESS, SPR_NOACCESS,
272 &spr_read_generic, &spr_write_pir,
273 0x00000000);
274 /* Breakpoints */
275 spr_register(env, SPR_IABR, "IABR",
276 SPR_NOACCESS, SPR_NOACCESS,
277 &spr_read_generic, &spr_write_generic,
278 0x00000000);
279
280 spr_register_kvm(env, SPR_DABR, "DABR",
281 SPR_NOACCESS, SPR_NOACCESS,
282 &spr_read_generic, &spr_write_generic,
283 KVM_REG_PPC_DABR, 0x00000000);
284 /* Performance counters */
285 spr_register(env, SPR_7XX_MMCR0, "MMCR0",
286 SPR_NOACCESS, SPR_NOACCESS,
287 &spr_read_generic, &spr_write_generic,
288 0x00000000);
289
290 spr_register(env, SPR_7XX_PMC1, "PMC1",
291 SPR_NOACCESS, SPR_NOACCESS,
292 &spr_read_generic, &spr_write_generic,
293 0x00000000);
294
295 spr_register(env, SPR_7XX_PMC2, "PMC2",
296 SPR_NOACCESS, SPR_NOACCESS,
297 &spr_read_generic, &spr_write_generic,
298 0x00000000);
299
300 spr_register(env, SPR_7XX_SIAR, "SIAR",
301 SPR_NOACCESS, SPR_NOACCESS,
302 &spr_read_generic, SPR_NOACCESS,
303 0x00000000);
304
305 spr_register(env, SPR_SDA, "SDA",
306 SPR_NOACCESS, SPR_NOACCESS,
307 &spr_read_generic, SPR_NOACCESS,
308 0x00000000);
309 /* External access control */
310 spr_register(env, SPR_EAR, "EAR",
311 SPR_NOACCESS, SPR_NOACCESS,
312 &spr_read_generic, &spr_write_generic,
313 0x00000000);
314
315 /* Hardware implementation registers */
316 spr_register(env, SPR_HID0, "HID0",
317 SPR_NOACCESS, SPR_NOACCESS,
318 &spr_read_generic, &spr_write_generic,
319 0x00000000);
320 }
321
322 static void register_604e_sprs(CPUPPCState *env)
323 {
324 spr_register(env, SPR_7XX_MMCR1, "MMCR1",
325 SPR_NOACCESS, SPR_NOACCESS,
326 &spr_read_generic, &spr_write_generic,
327 0x00000000);
328
329 spr_register(env, SPR_7XX_PMC3, "PMC3",
330 SPR_NOACCESS, SPR_NOACCESS,
331 &spr_read_generic, &spr_write_generic,
332 0x00000000);
333
334 spr_register(env, SPR_7XX_PMC4, "PMC4",
335 SPR_NOACCESS, SPR_NOACCESS,
336 &spr_read_generic, &spr_write_generic,
337 0x00000000);
338 /* Hardware implementation registers */
339 spr_register(env, SPR_HID1, "HID1",
340 SPR_NOACCESS, SPR_NOACCESS,
341 &spr_read_generic, &spr_write_generic,
342 0x00000000);
343 }
344
345 /* SPR specific to PowerPC 603 implementation */
346 static void register_603_sprs(CPUPPCState *env)
347 {
348 /* External access control */
349 spr_register(env, SPR_EAR, "EAR",
350 SPR_NOACCESS, SPR_NOACCESS,
351 &spr_read_generic, &spr_write_generic,
352 0x00000000);
353 /* Breakpoints */
354 spr_register(env, SPR_IABR, "IABR",
355 SPR_NOACCESS, SPR_NOACCESS,
356 &spr_read_generic, &spr_write_generic,
357 0x00000000);
358
359 spr_register(env, SPR_HID0, "HID0",
360 SPR_NOACCESS, SPR_NOACCESS,
361 &spr_read_generic, &spr_write_generic,
362 0x00000000);
363
364 spr_register(env, SPR_HID1, "HID1",
365 SPR_NOACCESS, SPR_NOACCESS,
366 &spr_read_generic, &spr_write_generic,
367 0x00000000);
368 }
369
370 static void register_e300_sprs(CPUPPCState *env)
371 {
372 /* hardware implementation registers */
373 spr_register(env, SPR_HID2, "HID2",
374 SPR_NOACCESS, SPR_NOACCESS,
375 &spr_read_generic, &spr_write_generic,
376 0x00000000);
377 /* Breakpoints */
378 spr_register(env, SPR_DABR, "DABR",
379 SPR_NOACCESS, SPR_NOACCESS,
380 &spr_read_generic, &spr_write_generic,
381 0x00000000);
382
383 spr_register(env, SPR_DABR2, "DABR2",
384 SPR_NOACCESS, SPR_NOACCESS,
385 &spr_read_generic, &spr_write_generic,
386 0x00000000);
387
388 spr_register(env, SPR_IABR2, "IABR2",
389 SPR_NOACCESS, SPR_NOACCESS,
390 &spr_read_generic, &spr_write_generic,
391 0x00000000);
392
393 spr_register(env, SPR_IBCR, "IBCR",
394 SPR_NOACCESS, SPR_NOACCESS,
395 &spr_read_generic, &spr_write_generic,
396 0x00000000);
397
398 spr_register(env, SPR_DBCR, "DBCR",
399 SPR_NOACCESS, SPR_NOACCESS,
400 &spr_read_generic, &spr_write_generic,
401 0x00000000);
402 }
403
404 /* SPR specific to PowerPC G2 implementation */
405 static void register_G2_sprs(CPUPPCState *env)
406 {
407 /* Memory base address */
408 /* MBAR */
409 spr_register(env, SPR_MBAR, "MBAR",
410 SPR_NOACCESS, SPR_NOACCESS,
411 &spr_read_generic, &spr_write_generic,
412 0x00000000);
413 /* Exception processing */
414 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
415 SPR_NOACCESS, SPR_NOACCESS,
416 &spr_read_generic, &spr_write_generic,
417 0x00000000);
418 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
419 SPR_NOACCESS, SPR_NOACCESS,
420 &spr_read_generic, &spr_write_generic,
421 0x00000000);
422 /* Breakpoints */
423 spr_register(env, SPR_DABR, "DABR",
424 SPR_NOACCESS, SPR_NOACCESS,
425 &spr_read_generic, &spr_write_generic,
426 0x00000000);
427
428 spr_register(env, SPR_DABR2, "DABR2",
429 SPR_NOACCESS, SPR_NOACCESS,
430 &spr_read_generic, &spr_write_generic,
431 0x00000000);
432
433 spr_register(env, SPR_IABR, "IABR",
434 SPR_NOACCESS, SPR_NOACCESS,
435 &spr_read_generic, &spr_write_generic,
436 0x00000000);
437
438 spr_register(env, SPR_IABR2, "IABR2",
439 SPR_NOACCESS, SPR_NOACCESS,
440 &spr_read_generic, &spr_write_generic,
441 0x00000000);
442
443 spr_register(env, SPR_IBCR, "IBCR",
444 SPR_NOACCESS, SPR_NOACCESS,
445 &spr_read_generic, &spr_write_generic,
446 0x00000000);
447
448 spr_register(env, SPR_DBCR, "DBCR",
449 SPR_NOACCESS, SPR_NOACCESS,
450 &spr_read_generic, &spr_write_generic,
451 0x00000000);
452
453 /* External access control */
454 spr_register(env, SPR_EAR, "EAR",
455 SPR_NOACCESS, SPR_NOACCESS,
456 &spr_read_generic, &spr_write_generic,
457 0x00000000);
458 /* Hardware implementation register */
459 spr_register(env, SPR_HID0, "HID0",
460 SPR_NOACCESS, SPR_NOACCESS,
461 &spr_read_generic, &spr_write_generic,
462 0x00000000);
463
464 spr_register(env, SPR_HID1, "HID1",
465 SPR_NOACCESS, SPR_NOACCESS,
466 &spr_read_generic, &spr_write_generic,
467 0x00000000);
468
469 spr_register(env, SPR_HID2, "HID2",
470 SPR_NOACCESS, SPR_NOACCESS,
471 &spr_read_generic, &spr_write_generic,
472 0x00000000);
473
474 /* SGPRs */
475 spr_register(env, SPR_SPRG4, "SPRG4",
476 SPR_NOACCESS, SPR_NOACCESS,
477 &spr_read_generic, &spr_write_generic,
478 0x00000000);
479 spr_register(env, SPR_SPRG5, "SPRG5",
480 SPR_NOACCESS, SPR_NOACCESS,
481 &spr_read_generic, &spr_write_generic,
482 0x00000000);
483 spr_register(env, SPR_SPRG6, "SPRG6",
484 SPR_NOACCESS, SPR_NOACCESS,
485 &spr_read_generic, &spr_write_generic,
486 0x00000000);
487 spr_register(env, SPR_SPRG7, "SPRG7",
488 SPR_NOACCESS, SPR_NOACCESS,
489 &spr_read_generic, &spr_write_generic,
490 0x00000000);
491 }
492
493 static void register_74xx_sprs(CPUPPCState *env)
494 {
495 /* Breakpoints */
496 spr_register_kvm(env, SPR_DABR, "DABR",
497 SPR_NOACCESS, SPR_NOACCESS,
498 &spr_read_generic, &spr_write_generic,
499 KVM_REG_PPC_DABR, 0x00000000);
500
501 spr_register(env, SPR_IABR, "IABR",
502 SPR_NOACCESS, SPR_NOACCESS,
503 &spr_read_generic, &spr_write_generic,
504 0x00000000);
505 /* Cache management */
506 spr_register(env, SPR_ICTC, "ICTC",
507 SPR_NOACCESS, SPR_NOACCESS,
508 &spr_read_generic, &spr_write_generic,
509 0x00000000);
510 /* Performance monitors */
511 spr_register(env, SPR_7XX_MMCR0, "MMCR0",
512 SPR_NOACCESS, SPR_NOACCESS,
513 &spr_read_generic, &spr_write_generic,
514 0x00000000);
515
516 spr_register(env, SPR_7XX_MMCR1, "MMCR1",
517 SPR_NOACCESS, SPR_NOACCESS,
518 &spr_read_generic, &spr_write_generic,
519 0x00000000);
520
521 spr_register(env, SPR_7XX_PMC1, "PMC1",
522 SPR_NOACCESS, SPR_NOACCESS,
523 &spr_read_generic, &spr_write_generic,
524 0x00000000);
525
526 spr_register(env, SPR_7XX_PMC2, "PMC2",
527 SPR_NOACCESS, SPR_NOACCESS,
528 &spr_read_generic, &spr_write_generic,
529 0x00000000);
530
531 spr_register(env, SPR_7XX_PMC3, "PMC3",
532 SPR_NOACCESS, SPR_NOACCESS,
533 &spr_read_generic, &spr_write_generic,
534 0x00000000);
535
536 spr_register(env, SPR_7XX_PMC4, "PMC4",
537 SPR_NOACCESS, SPR_NOACCESS,
538 &spr_read_generic, &spr_write_generic,
539 0x00000000);
540
541 spr_register(env, SPR_7XX_SIAR, "SIAR",
542 SPR_NOACCESS, SPR_NOACCESS,
543 &spr_read_generic, SPR_NOACCESS,
544 0x00000000);
545
546 spr_register(env, SPR_7XX_UMMCR0, "UMMCR0",
547 &spr_read_ureg, SPR_NOACCESS,
548 &spr_read_ureg, SPR_NOACCESS,
549 0x00000000);
550
551 spr_register(env, SPR_7XX_UMMCR1, "UMMCR1",
552 &spr_read_ureg, SPR_NOACCESS,
553 &spr_read_ureg, SPR_NOACCESS,
554 0x00000000);
555
556 spr_register(env, SPR_7XX_UPMC1, "UPMC1",
557 &spr_read_ureg, SPR_NOACCESS,
558 &spr_read_ureg, SPR_NOACCESS,
559 0x00000000);
560
561 spr_register(env, SPR_7XX_UPMC2, "UPMC2",
562 &spr_read_ureg, SPR_NOACCESS,
563 &spr_read_ureg, SPR_NOACCESS,
564 0x00000000);
565
566 spr_register(env, SPR_7XX_UPMC3, "UPMC3",
567 &spr_read_ureg, SPR_NOACCESS,
568 &spr_read_ureg, SPR_NOACCESS,
569 0x00000000);
570
571 spr_register(env, SPR_7XX_UPMC4, "UPMC4",
572 &spr_read_ureg, SPR_NOACCESS,
573 &spr_read_ureg, SPR_NOACCESS,
574 0x00000000);
575
576 spr_register(env, SPR_7XX_USIAR, "USIAR",
577 &spr_read_ureg, SPR_NOACCESS,
578 &spr_read_ureg, SPR_NOACCESS,
579 0x00000000);
580 /* External access control */
581 spr_register(env, SPR_EAR, "EAR",
582 SPR_NOACCESS, SPR_NOACCESS,
583 &spr_read_generic, &spr_write_generic,
584 0x00000000);
585
586 /* Processor identification */
587 spr_register(env, SPR_PIR, "PIR",
588 SPR_NOACCESS, SPR_NOACCESS,
589 &spr_read_generic, &spr_write_pir,
590 0x00000000);
591
592 spr_register(env, SPR_74XX_MMCR2, "MMCR2",
593 SPR_NOACCESS, SPR_NOACCESS,
594 &spr_read_generic, &spr_write_generic,
595 0x00000000);
596
597 spr_register(env, SPR_74XX_UMMCR2, "UMMCR2",
598 &spr_read_ureg, SPR_NOACCESS,
599 &spr_read_ureg, SPR_NOACCESS,
600 0x00000000);
601
602 spr_register(env, SPR_BAMR, "BAMR",
603 SPR_NOACCESS, SPR_NOACCESS,
604 &spr_read_generic, &spr_write_generic,
605 0x00000000);
606
607 spr_register(env, SPR_MSSCR0, "MSSCR0",
608 SPR_NOACCESS, SPR_NOACCESS,
609 &spr_read_generic, &spr_write_generic,
610 0x00000000);
611 /* Hardware implementation registers */
612 spr_register(env, SPR_HID0, "HID0",
613 SPR_NOACCESS, SPR_NOACCESS,
614 &spr_read_generic, &spr_write_generic,
615 0x00000000);
616
617 spr_register(env, SPR_HID1, "HID1",
618 SPR_NOACCESS, SPR_NOACCESS,
619 &spr_read_generic, &spr_write_generic,
620 0x00000000);
621 /* Altivec */
622 spr_register(env, SPR_VRSAVE, "VRSAVE",
623 &spr_read_generic, &spr_write_generic,
624 &spr_read_generic, &spr_write_generic,
625 0x00000000);
626
627 spr_register(env, SPR_L2CR, "L2CR",
628 SPR_NOACCESS, SPR_NOACCESS,
629 &spr_read_generic, spr_access_nop,
630 0x00000000);
631 }
632
633 static void register_l3_ctrl(CPUPPCState *env)
634 {
635 /* L3CR */
636 spr_register(env, SPR_L3CR, "L3CR",
637 SPR_NOACCESS, SPR_NOACCESS,
638 &spr_read_generic, &spr_write_generic,
639 0x00000000);
640 /* L3ITCR0 */
641 spr_register(env, SPR_L3ITCR0, "L3ITCR0",
642 SPR_NOACCESS, SPR_NOACCESS,
643 &spr_read_generic, &spr_write_generic,
644 0x00000000);
645 /* L3PM */
646 spr_register(env, SPR_L3PM, "L3PM",
647 SPR_NOACCESS, SPR_NOACCESS,
648 &spr_read_generic, &spr_write_generic,
649 0x00000000);
650 }
651
652 /* PowerPC BookE SPR */
653 static void register_BookE_sprs(CPUPPCState *env, uint64_t ivor_mask)
654 {
655 const char *ivor_names[64] = {
656 "IVOR0", "IVOR1", "IVOR2", "IVOR3",
657 "IVOR4", "IVOR5", "IVOR6", "IVOR7",
658 "IVOR8", "IVOR9", "IVOR10", "IVOR11",
659 "IVOR12", "IVOR13", "IVOR14", "IVOR15",
660 "IVOR16", "IVOR17", "IVOR18", "IVOR19",
661 "IVOR20", "IVOR21", "IVOR22", "IVOR23",
662 "IVOR24", "IVOR25", "IVOR26", "IVOR27",
663 "IVOR28", "IVOR29", "IVOR30", "IVOR31",
664 "IVOR32", "IVOR33", "IVOR34", "IVOR35",
665 "IVOR36", "IVOR37", "IVOR38", "IVOR39",
666 "IVOR40", "IVOR41", "IVOR42", "IVOR43",
667 "IVOR44", "IVOR45", "IVOR46", "IVOR47",
668 "IVOR48", "IVOR49", "IVOR50", "IVOR51",
669 "IVOR52", "IVOR53", "IVOR54", "IVOR55",
670 "IVOR56", "IVOR57", "IVOR58", "IVOR59",
671 "IVOR60", "IVOR61", "IVOR62", "IVOR63",
672 };
673 #define SPR_BOOKE_IVORxx (-1)
674 int ivor_sprn[64] = {
675 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3,
676 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7,
677 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11,
678 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15,
679 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
680 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
681 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
682 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
683 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35,
684 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVOR38, SPR_BOOKE_IVOR39,
685 SPR_BOOKE_IVOR40, SPR_BOOKE_IVOR41, SPR_BOOKE_IVOR42, SPR_BOOKE_IVORxx,
686 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
687 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
688 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
689 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
690 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
691 };
692 int i;
693
694 /* Interrupt processing */
695 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
696 SPR_NOACCESS, SPR_NOACCESS,
697 &spr_read_generic, &spr_write_generic,
698 0x00000000);
699 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
700 SPR_NOACCESS, SPR_NOACCESS,
701 &spr_read_generic, &spr_write_generic,
702 0x00000000);
703 /* Debug */
704 spr_register(env, SPR_BOOKE_IAC1, "IAC1",
705 SPR_NOACCESS, SPR_NOACCESS,
706 &spr_read_generic, &spr_write_generic,
707 0x00000000);
708
709 spr_register(env, SPR_BOOKE_IAC2, "IAC2",
710 SPR_NOACCESS, SPR_NOACCESS,
711 &spr_read_generic, &spr_write_generic,
712 0x00000000);
713
714 spr_register(env, SPR_BOOKE_DAC1, "DAC1",
715 SPR_NOACCESS, SPR_NOACCESS,
716 &spr_read_generic, &spr_write_generic,
717 0x00000000);
718
719 spr_register(env, SPR_BOOKE_DAC2, "DAC2",
720 SPR_NOACCESS, SPR_NOACCESS,
721 &spr_read_generic, &spr_write_generic,
722 0x00000000);
723
724 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
725 SPR_NOACCESS, SPR_NOACCESS,
726 &spr_read_generic, &spr_write_40x_dbcr0,
727 0x00000000);
728
729 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
730 SPR_NOACCESS, SPR_NOACCESS,
731 &spr_read_generic, &spr_write_generic,
732 0x00000000);
733
734 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
735 SPR_NOACCESS, SPR_NOACCESS,
736 &spr_read_generic, &spr_write_generic,
737 0x00000000);
738 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
739 SPR_NOACCESS, SPR_NOACCESS,
740 &spr_read_generic, &spr_write_generic,
741 0x00000000);
742 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
743 SPR_NOACCESS, SPR_NOACCESS,
744 &spr_read_generic, &spr_write_generic,
745 0x00000000);
746
747 spr_register(env, SPR_BOOKE_DBSR, "DBSR",
748 SPR_NOACCESS, SPR_NOACCESS,
749 &spr_read_generic, &spr_write_clear,
750 0x00000000);
751 spr_register(env, SPR_BOOKE_DEAR, "DEAR",
752 SPR_NOACCESS, SPR_NOACCESS,
753 &spr_read_generic, &spr_write_generic,
754 0x00000000);
755 spr_register(env, SPR_BOOKE_ESR, "ESR",
756 SPR_NOACCESS, SPR_NOACCESS,
757 &spr_read_generic, &spr_write_generic,
758 0x00000000);
759 spr_register(env, SPR_BOOKE_IVPR, "IVPR",
760 SPR_NOACCESS, SPR_NOACCESS,
761 &spr_read_generic, &spr_write_excp_prefix,
762 0x00000000);
763 /* Exception vectors */
764 for (i = 0; i < 64; i++) {
765 if (ivor_mask & (1ULL << i)) {
766 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) {
767 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i);
768 exit(1);
769 }
770 spr_register(env, ivor_sprn[i], ivor_names[i],
771 SPR_NOACCESS, SPR_NOACCESS,
772 &spr_read_generic, &spr_write_excp_vector,
773 0x00000000);
774 }
775 }
776 spr_register(env, SPR_BOOKE_PID, "PID",
777 SPR_NOACCESS, SPR_NOACCESS,
778 &spr_read_generic, &spr_write_booke_pid,
779 0x00000000);
780 spr_register(env, SPR_BOOKE_TCR, "TCR",
781 SPR_NOACCESS, SPR_NOACCESS,
782 &spr_read_generic, &spr_write_booke_tcr,
783 0x00000000);
784 spr_register(env, SPR_BOOKE_TSR, "TSR",
785 SPR_NOACCESS, SPR_NOACCESS,
786 &spr_read_generic, &spr_write_booke_tsr,
787 0x00000000);
788 /* Timer */
789 spr_register(env, SPR_DECR, "DECR",
790 SPR_NOACCESS, SPR_NOACCESS,
791 &spr_read_decr, &spr_write_decr,
792 0x00000000);
793 spr_register(env, SPR_BOOKE_DECAR, "DECAR",
794 SPR_NOACCESS, SPR_NOACCESS,
795 SPR_NOACCESS, &spr_write_generic,
796 0x00000000);
797 /* SPRGs */
798 spr_register(env, SPR_USPRG0, "USPRG0",
799 &spr_read_generic, &spr_write_generic,
800 &spr_read_generic, &spr_write_generic,
801 0x00000000);
802 spr_register(env, SPR_SPRG4, "SPRG4",
803 SPR_NOACCESS, SPR_NOACCESS,
804 &spr_read_generic, &spr_write_generic,
805 0x00000000);
806 spr_register(env, SPR_SPRG5, "SPRG5",
807 SPR_NOACCESS, SPR_NOACCESS,
808 &spr_read_generic, &spr_write_generic,
809 0x00000000);
810 spr_register(env, SPR_SPRG6, "SPRG6",
811 SPR_NOACCESS, SPR_NOACCESS,
812 &spr_read_generic, &spr_write_generic,
813 0x00000000);
814 spr_register(env, SPR_SPRG7, "SPRG7",
815 SPR_NOACCESS, SPR_NOACCESS,
816 &spr_read_generic, &spr_write_generic,
817 0x00000000);
818 spr_register(env, SPR_BOOKE_SPRG8, "SPRG8",
819 SPR_NOACCESS, SPR_NOACCESS,
820 &spr_read_generic, &spr_write_generic,
821 0x00000000);
822 spr_register(env, SPR_BOOKE_SPRG9, "SPRG9",
823 SPR_NOACCESS, SPR_NOACCESS,
824 &spr_read_generic, &spr_write_generic,
825 0x00000000);
826 }
827
828 #if !defined(CONFIG_USER_ONLY)
829 static inline uint32_t register_tlbncfg(uint32_t assoc, uint32_t minsize,
830 uint32_t maxsize, uint32_t flags,
831 uint32_t nentries)
832 {
833 return (assoc << TLBnCFG_ASSOC_SHIFT) |
834 (minsize << TLBnCFG_MINSIZE_SHIFT) |
835 (maxsize << TLBnCFG_MAXSIZE_SHIFT) |
836 flags | nentries;
837 }
838 #endif /* !CONFIG_USER_ONLY */
839
840 /* BookE 2.06 storage control registers */
841 static void register_BookE206_sprs(CPUPPCState *env, uint32_t mas_mask,
842 uint32_t *tlbncfg, uint32_t mmucfg)
843 {
844 #if !defined(CONFIG_USER_ONLY)
845 const char *mas_names[8] = {
846 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
847 };
848 int mas_sprn[8] = {
849 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3,
850 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7,
851 };
852 int i;
853
854 /* TLB assist registers */
855 for (i = 0; i < 8; i++) {
856 if (mas_mask & (1 << i)) {
857 spr_register(env, mas_sprn[i], mas_names[i],
858 SPR_NOACCESS, SPR_NOACCESS,
859 &spr_read_generic,
860 (i == 2 && (env->insns_flags & PPC_64B))
861 ? &spr_write_generic : &spr_write_generic32,
862 0x00000000);
863 }
864 }
865 if (env->nb_pids > 1) {
866 spr_register(env, SPR_BOOKE_PID1, "PID1",
867 SPR_NOACCESS, SPR_NOACCESS,
868 &spr_read_generic, &spr_write_booke_pid,
869 0x00000000);
870 }
871 if (env->nb_pids > 2) {
872 spr_register(env, SPR_BOOKE_PID2, "PID2",
873 SPR_NOACCESS, SPR_NOACCESS,
874 &spr_read_generic, &spr_write_booke_pid,
875 0x00000000);
876 }
877
878 spr_register(env, SPR_BOOKE_EPLC, "EPLC",
879 SPR_NOACCESS, SPR_NOACCESS,
880 &spr_read_generic, &spr_write_eplc,
881 0x00000000);
882 spr_register(env, SPR_BOOKE_EPSC, "EPSC",
883 SPR_NOACCESS, SPR_NOACCESS,
884 &spr_read_generic, &spr_write_epsc,
885 0x00000000);
886
887 spr_register(env, SPR_MMUCFG, "MMUCFG",
888 SPR_NOACCESS, SPR_NOACCESS,
889 &spr_read_generic, SPR_NOACCESS,
890 mmucfg);
891 switch (env->nb_ways) {
892 case 4:
893 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
894 SPR_NOACCESS, SPR_NOACCESS,
895 &spr_read_generic, SPR_NOACCESS,
896 tlbncfg[3]);
897 /* Fallthru */
898 case 3:
899 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
900 SPR_NOACCESS, SPR_NOACCESS,
901 &spr_read_generic, SPR_NOACCESS,
902 tlbncfg[2]);
903 /* Fallthru */
904 case 2:
905 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
906 SPR_NOACCESS, SPR_NOACCESS,
907 &spr_read_generic, SPR_NOACCESS,
908 tlbncfg[1]);
909 /* Fallthru */
910 case 1:
911 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
912 SPR_NOACCESS, SPR_NOACCESS,
913 &spr_read_generic, SPR_NOACCESS,
914 tlbncfg[0]);
915 /* Fallthru */
916 case 0:
917 default:
918 break;
919 }
920 #endif
921 }
922
923 /* SPR specific to PowerPC 440 implementation */
924 static void register_440_sprs(CPUPPCState *env)
925 {
926 /* Cache control */
927 spr_register(env, SPR_440_DNV0, "DNV0",
928 SPR_NOACCESS, SPR_NOACCESS,
929 &spr_read_generic, &spr_write_generic,
930 0x00000000);
931
932 spr_register(env, SPR_440_DNV1, "DNV1",
933 SPR_NOACCESS, SPR_NOACCESS,
934 &spr_read_generic, &spr_write_generic,
935 0x00000000);
936
937 spr_register(env, SPR_440_DNV2, "DNV2",
938 SPR_NOACCESS, SPR_NOACCESS,
939 &spr_read_generic, &spr_write_generic,
940 0x00000000);
941
942 spr_register(env, SPR_440_DNV3, "DNV3",
943 SPR_NOACCESS, SPR_NOACCESS,
944 &spr_read_generic, &spr_write_generic,
945 0x00000000);
946
947 spr_register(env, SPR_440_DTV0, "DTV0",
948 SPR_NOACCESS, SPR_NOACCESS,
949 &spr_read_generic, &spr_write_generic,
950 0x00000000);
951
952 spr_register(env, SPR_440_DTV1, "DTV1",
953 SPR_NOACCESS, SPR_NOACCESS,
954 &spr_read_generic, &spr_write_generic,
955 0x00000000);
956
957 spr_register(env, SPR_440_DTV2, "DTV2",
958 SPR_NOACCESS, SPR_NOACCESS,
959 &spr_read_generic, &spr_write_generic,
960 0x00000000);
961
962 spr_register(env, SPR_440_DTV3, "DTV3",
963 SPR_NOACCESS, SPR_NOACCESS,
964 &spr_read_generic, &spr_write_generic,
965 0x00000000);
966
967 spr_register(env, SPR_440_DVLIM, "DVLIM",
968 SPR_NOACCESS, SPR_NOACCESS,
969 &spr_read_generic, &spr_write_generic,
970 0x00000000);
971
972 spr_register(env, SPR_440_INV0, "INV0",
973 SPR_NOACCESS, SPR_NOACCESS,
974 &spr_read_generic, &spr_write_generic,
975 0x00000000);
976
977 spr_register(env, SPR_440_INV1, "INV1",
978 SPR_NOACCESS, SPR_NOACCESS,
979 &spr_read_generic, &spr_write_generic,
980 0x00000000);
981
982 spr_register(env, SPR_440_INV2, "INV2",
983 SPR_NOACCESS, SPR_NOACCESS,
984 &spr_read_generic, &spr_write_generic,
985 0x00000000);
986
987 spr_register(env, SPR_440_INV3, "INV3",
988 SPR_NOACCESS, SPR_NOACCESS,
989 &spr_read_generic, &spr_write_generic,
990 0x00000000);
991
992 spr_register(env, SPR_440_ITV0, "ITV0",
993 SPR_NOACCESS, SPR_NOACCESS,
994 &spr_read_generic, &spr_write_generic,
995 0x00000000);
996
997 spr_register(env, SPR_440_ITV1, "ITV1",
998 SPR_NOACCESS, SPR_NOACCESS,
999 &spr_read_generic, &spr_write_generic,
1000 0x00000000);
1001
1002 spr_register(env, SPR_440_ITV2, "ITV2",
1003 SPR_NOACCESS, SPR_NOACCESS,
1004 &spr_read_generic, &spr_write_generic,
1005 0x00000000);
1006
1007 spr_register(env, SPR_440_ITV3, "ITV3",
1008 SPR_NOACCESS, SPR_NOACCESS,
1009 &spr_read_generic, &spr_write_generic,
1010 0x00000000);
1011
1012 spr_register(env, SPR_440_IVLIM, "IVLIM",
1013 SPR_NOACCESS, SPR_NOACCESS,
1014 &spr_read_generic, &spr_write_generic,
1015 0x00000000);
1016 /* Cache debug */
1017 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
1018 SPR_NOACCESS, SPR_NOACCESS,
1019 &spr_read_generic, SPR_NOACCESS,
1020 0x00000000);
1021
1022 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
1023 SPR_NOACCESS, SPR_NOACCESS,
1024 &spr_read_generic, SPR_NOACCESS,
1025 0x00000000);
1026
1027 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1028 SPR_NOACCESS, SPR_NOACCESS,
1029 &spr_read_generic, SPR_NOACCESS,
1030 0x00000000);
1031
1032 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
1033 SPR_NOACCESS, SPR_NOACCESS,
1034 &spr_read_generic, SPR_NOACCESS,
1035 0x00000000);
1036
1037 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
1038 SPR_NOACCESS, SPR_NOACCESS,
1039 &spr_read_generic, SPR_NOACCESS,
1040 0x00000000);
1041
1042 spr_register(env, SPR_440_DBDR, "DBDR",
1043 SPR_NOACCESS, SPR_NOACCESS,
1044 &spr_read_generic, &spr_write_generic,
1045 0x00000000);
1046 /* Processor control */
1047 spr_register(env, SPR_4xx_CCR0, "CCR0",
1048 SPR_NOACCESS, SPR_NOACCESS,
1049 &spr_read_generic, &spr_write_generic,
1050 0x00000000);
1051 spr_register(env, SPR_440_RSTCFG, "RSTCFG",
1052 SPR_NOACCESS, SPR_NOACCESS,
1053 &spr_read_generic, SPR_NOACCESS,
1054 0x00000000);
1055 /* Storage control */
1056 spr_register(env, SPR_440_MMUCR, "MMUCR",
1057 SPR_NOACCESS, SPR_NOACCESS,
1058 &spr_read_generic, &spr_write_generic,
1059 0x00000000);
1060
1061 /* Processor identification */
1062 spr_register(env, SPR_BOOKE_PIR, "PIR",
1063 SPR_NOACCESS, SPR_NOACCESS,
1064 &spr_read_generic, &spr_write_pir,
1065 0x00000000);
1066
1067 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
1068 SPR_NOACCESS, SPR_NOACCESS,
1069 &spr_read_generic, &spr_write_generic,
1070 0x00000000);
1071
1072 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
1073 SPR_NOACCESS, SPR_NOACCESS,
1074 &spr_read_generic, &spr_write_generic,
1075 0x00000000);
1076
1077 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
1078 SPR_NOACCESS, SPR_NOACCESS,
1079 &spr_read_generic, &spr_write_generic,
1080 0x00000000);
1081
1082 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
1083 SPR_NOACCESS, SPR_NOACCESS,
1084 &spr_read_generic, &spr_write_generic,
1085 0x00000000);
1086 }
1087
1088 /* SPR shared between PowerPC 40x implementations */
1089 static void register_40x_sprs(CPUPPCState *env)
1090 {
1091 /* Cache */
1092 /* not emulated, as QEMU do not emulate caches */
1093 spr_register(env, SPR_40x_DCCR, "DCCR",
1094 SPR_NOACCESS, SPR_NOACCESS,
1095 &spr_read_generic, &spr_write_generic,
1096 0x00000000);
1097 /* not emulated, as QEMU do not emulate caches */
1098 spr_register(env, SPR_40x_ICCR, "ICCR",
1099 SPR_NOACCESS, SPR_NOACCESS,
1100 &spr_read_generic, &spr_write_generic,
1101 0x00000000);
1102 /* not emulated, as QEMU do not emulate caches */
1103 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1104 SPR_NOACCESS, SPR_NOACCESS,
1105 &spr_read_generic, SPR_NOACCESS,
1106 0x00000000);
1107 /* Exception */
1108 spr_register(env, SPR_40x_DEAR, "DEAR",
1109 SPR_NOACCESS, SPR_NOACCESS,
1110 &spr_read_generic, &spr_write_generic,
1111 0x00000000);
1112 spr_register(env, SPR_40x_ESR, "ESR",
1113 SPR_NOACCESS, SPR_NOACCESS,
1114 &spr_read_generic, &spr_write_generic,
1115 0x00000000);
1116 spr_register(env, SPR_40x_EVPR, "EVPR",
1117 SPR_NOACCESS, SPR_NOACCESS,
1118 &spr_read_generic, &spr_write_excp_prefix,
1119 0x00000000);
1120 spr_register(env, SPR_40x_SRR2, "SRR2",
1121 &spr_read_generic, &spr_write_generic,
1122 &spr_read_generic, &spr_write_generic,
1123 0x00000000);
1124 spr_register(env, SPR_40x_SRR3, "SRR3",
1125 &spr_read_generic, &spr_write_generic,
1126 &spr_read_generic, &spr_write_generic,
1127 0x00000000);
1128 /* Timers */
1129 spr_register(env, SPR_40x_PIT, "PIT",
1130 SPR_NOACCESS, SPR_NOACCESS,
1131 &spr_read_40x_pit, &spr_write_40x_pit,
1132 0x00000000);
1133 spr_register(env, SPR_40x_TCR, "TCR",
1134 SPR_NOACCESS, SPR_NOACCESS,
1135 &spr_read_generic, &spr_write_40x_tcr,
1136 0x00000000);
1137 spr_register(env, SPR_40x_TSR, "TSR",
1138 SPR_NOACCESS, SPR_NOACCESS,
1139 &spr_read_generic, &spr_write_40x_tsr,
1140 0x00000000);
1141 }
1142
1143 /* SPR specific to PowerPC 405 implementation */
1144 static void register_405_sprs(CPUPPCState *env)
1145 {
1146 /* MMU */
1147 spr_register(env, SPR_40x_PID, "PID",
1148 SPR_NOACCESS, SPR_NOACCESS,
1149 &spr_read_generic, &spr_write_40x_pid,
1150 0x00000000);
1151 spr_register(env, SPR_4xx_CCR0, "CCR0",
1152 SPR_NOACCESS, SPR_NOACCESS,
1153 &spr_read_generic, &spr_write_generic,
1154 0x00700000);
1155 /* Debug interface */
1156 spr_register(env, SPR_40x_DBCR0, "DBCR0",
1157 SPR_NOACCESS, SPR_NOACCESS,
1158 &spr_read_generic, &spr_write_40x_dbcr0,
1159 0x00000000);
1160
1161 spr_register(env, SPR_405_DBCR1, "DBCR1",
1162 SPR_NOACCESS, SPR_NOACCESS,
1163 &spr_read_generic, &spr_write_generic,
1164 0x00000000);
1165
1166 spr_register(env, SPR_40x_DBSR, "DBSR",
1167 SPR_NOACCESS, SPR_NOACCESS,
1168 &spr_read_generic, &spr_write_clear,
1169 /* Last reset was system reset */
1170 0x00000300);
1171
1172 spr_register(env, SPR_40x_DAC1, "DAC1",
1173 SPR_NOACCESS, SPR_NOACCESS,
1174 &spr_read_generic, &spr_write_generic,
1175 0x00000000);
1176 spr_register(env, SPR_40x_DAC2, "DAC2",
1177 SPR_NOACCESS, SPR_NOACCESS,
1178 &spr_read_generic, &spr_write_generic,
1179 0x00000000);
1180
1181 spr_register(env, SPR_405_DVC1, "DVC1",
1182 SPR_NOACCESS, SPR_NOACCESS,
1183 &spr_read_generic, &spr_write_generic,
1184 0x00000000);
1185
1186 spr_register(env, SPR_405_DVC2, "DVC2",
1187 SPR_NOACCESS, SPR_NOACCESS,
1188 &spr_read_generic, &spr_write_generic,
1189 0x00000000);
1190
1191 spr_register(env, SPR_40x_IAC1, "IAC1",
1192 SPR_NOACCESS, SPR_NOACCESS,
1193 &spr_read_generic, &spr_write_generic,
1194 0x00000000);
1195 spr_register(env, SPR_40x_IAC2, "IAC2",
1196 SPR_NOACCESS, SPR_NOACCESS,
1197 &spr_read_generic, &spr_write_generic,
1198 0x00000000);
1199
1200 spr_register(env, SPR_405_IAC3, "IAC3",
1201 SPR_NOACCESS, SPR_NOACCESS,
1202 &spr_read_generic, &spr_write_generic,
1203 0x00000000);
1204
1205 spr_register(env, SPR_405_IAC4, "IAC4",
1206 SPR_NOACCESS, SPR_NOACCESS,
1207 &spr_read_generic, &spr_write_generic,
1208 0x00000000);
1209 /* Storage control */
1210 spr_register(env, SPR_405_SLER, "SLER",
1211 SPR_NOACCESS, SPR_NOACCESS,
1212 &spr_read_generic, &spr_write_40x_sler,
1213 0x00000000);
1214 spr_register(env, SPR_40x_ZPR, "ZPR",
1215 SPR_NOACCESS, SPR_NOACCESS,
1216 &spr_read_generic, &spr_write_generic,
1217 0x00000000);
1218
1219 spr_register(env, SPR_405_SU0R, "SU0R",
1220 SPR_NOACCESS, SPR_NOACCESS,
1221 &spr_read_generic, &spr_write_generic,
1222 0x00000000);
1223 /* SPRG */
1224 spr_register(env, SPR_USPRG0, "USPRG0",
1225 &spr_read_ureg, SPR_NOACCESS,
1226 &spr_read_ureg, SPR_NOACCESS,
1227 0x00000000);
1228 spr_register(env, SPR_SPRG4, "SPRG4",
1229 SPR_NOACCESS, SPR_NOACCESS,
1230 &spr_read_generic, &spr_write_generic,
1231 0x00000000);
1232 spr_register(env, SPR_SPRG5, "SPRG5",
1233 SPR_NOACCESS, SPR_NOACCESS,
1234 spr_read_generic, &spr_write_generic,
1235 0x00000000);
1236 spr_register(env, SPR_SPRG6, "SPRG6",
1237 SPR_NOACCESS, SPR_NOACCESS,
1238 spr_read_generic, &spr_write_generic,
1239 0x00000000);
1240 spr_register(env, SPR_SPRG7, "SPRG7",
1241 SPR_NOACCESS, SPR_NOACCESS,
1242 spr_read_generic, &spr_write_generic,
1243 0x00000000);
1244
1245 /* Bus access control */
1246 /* not emulated, as QEMU never does speculative access */
1247 spr_register(env, SPR_40x_SGR, "SGR",
1248 SPR_NOACCESS, SPR_NOACCESS,
1249 &spr_read_generic, &spr_write_generic,
1250 0xFFFFFFFF);
1251 /* not emulated, as QEMU do not emulate caches */
1252 spr_register(env, SPR_40x_DCWR, "DCWR",
1253 SPR_NOACCESS, SPR_NOACCESS,
1254 &spr_read_generic, &spr_write_generic,
1255 0x00000000);
1256 }
1257
1258
1259 static void register_5xx_8xx_sprs(CPUPPCState *env)
1260 {
1261 /* Exception processing */
1262 spr_register_kvm(env, SPR_DSISR, "DSISR",
1263 SPR_NOACCESS, SPR_NOACCESS,
1264 &spr_read_generic, &spr_write_generic,
1265 KVM_REG_PPC_DSISR, 0x00000000);
1266 spr_register_kvm(env, SPR_DAR, "DAR",
1267 SPR_NOACCESS, SPR_NOACCESS,
1268 &spr_read_generic, &spr_write_generic,
1269 KVM_REG_PPC_DAR, 0x00000000);
1270 /* Timer */
1271 spr_register(env, SPR_DECR, "DECR",
1272 SPR_NOACCESS, SPR_NOACCESS,
1273 &spr_read_decr, &spr_write_decr,
1274 0x00000000);
1275
1276 spr_register(env, SPR_MPC_EIE, "EIE",
1277 SPR_NOACCESS, SPR_NOACCESS,
1278 &spr_read_generic, &spr_write_generic,
1279 0x00000000);
1280
1281 spr_register(env, SPR_MPC_EID, "EID",
1282 SPR_NOACCESS, SPR_NOACCESS,
1283 &spr_read_generic, &spr_write_generic,
1284 0x00000000);
1285
1286 spr_register(env, SPR_MPC_NRI, "NRI",
1287 SPR_NOACCESS, SPR_NOACCESS,
1288 &spr_read_generic, &spr_write_generic,
1289 0x00000000);
1290
1291 spr_register(env, SPR_MPC_CMPA, "CMPA",
1292 SPR_NOACCESS, SPR_NOACCESS,
1293 &spr_read_generic, &spr_write_generic,
1294 0x00000000);
1295
1296 spr_register(env, SPR_MPC_CMPB, "CMPB",
1297 SPR_NOACCESS, SPR_NOACCESS,
1298 &spr_read_generic, &spr_write_generic,
1299 0x00000000);
1300
1301 spr_register(env, SPR_MPC_CMPC, "CMPC",
1302 SPR_NOACCESS, SPR_NOACCESS,
1303 &spr_read_generic, &spr_write_generic,
1304 0x00000000);
1305
1306 spr_register(env, SPR_MPC_CMPD, "CMPD",
1307 SPR_NOACCESS, SPR_NOACCESS,
1308 &spr_read_generic, &spr_write_generic,
1309 0x00000000);
1310
1311 spr_register(env, SPR_MPC_ECR, "ECR",
1312 SPR_NOACCESS, SPR_NOACCESS,
1313 &spr_read_generic, &spr_write_generic,
1314 0x00000000);
1315
1316 spr_register(env, SPR_MPC_DER, "DER",
1317 SPR_NOACCESS, SPR_NOACCESS,
1318 &spr_read_generic, &spr_write_generic,
1319 0x00000000);
1320
1321 spr_register(env, SPR_MPC_COUNTA, "COUNTA",
1322 SPR_NOACCESS, SPR_NOACCESS,
1323 &spr_read_generic, &spr_write_generic,
1324 0x00000000);
1325
1326 spr_register(env, SPR_MPC_COUNTB, "COUNTB",
1327 SPR_NOACCESS, SPR_NOACCESS,
1328 &spr_read_generic, &spr_write_generic,
1329 0x00000000);
1330
1331 spr_register(env, SPR_MPC_CMPE, "CMPE",
1332 SPR_NOACCESS, SPR_NOACCESS,
1333 &spr_read_generic, &spr_write_generic,
1334 0x00000000);
1335
1336 spr_register(env, SPR_MPC_CMPF, "CMPF",
1337 SPR_NOACCESS, SPR_NOACCESS,
1338 &spr_read_generic, &spr_write_generic,
1339 0x00000000);
1340
1341 spr_register(env, SPR_MPC_CMPG, "CMPG",
1342 SPR_NOACCESS, SPR_NOACCESS,
1343 &spr_read_generic, &spr_write_generic,
1344 0x00000000);
1345
1346 spr_register(env, SPR_MPC_CMPH, "CMPH",
1347 SPR_NOACCESS, SPR_NOACCESS,
1348 &spr_read_generic, &spr_write_generic,
1349 0x00000000);
1350
1351 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1",
1352 SPR_NOACCESS, SPR_NOACCESS,
1353 &spr_read_generic, &spr_write_generic,
1354 0x00000000);
1355
1356 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2",
1357 SPR_NOACCESS, SPR_NOACCESS,
1358 &spr_read_generic, &spr_write_generic,
1359 0x00000000);
1360
1361 spr_register(env, SPR_MPC_BAR, "BAR",
1362 SPR_NOACCESS, SPR_NOACCESS,
1363 &spr_read_generic, &spr_write_generic,
1364 0x00000000);
1365
1366 spr_register(env, SPR_MPC_DPDR, "DPDR",
1367 SPR_NOACCESS, SPR_NOACCESS,
1368 &spr_read_generic, &spr_write_generic,
1369 0x00000000);
1370
1371 spr_register(env, SPR_MPC_IMMR, "IMMR",
1372 SPR_NOACCESS, SPR_NOACCESS,
1373 &spr_read_generic, &spr_write_generic,
1374 0x00000000);
1375 }
1376
1377 static void register_5xx_sprs(CPUPPCState *env)
1378 {
1379 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
1380 SPR_NOACCESS, SPR_NOACCESS,
1381 &spr_read_generic, &spr_write_generic,
1382 0x00000000);
1383
1384 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA",
1385 SPR_NOACCESS, SPR_NOACCESS,
1386 &spr_read_generic, &spr_write_generic,
1387 0x00000000);
1388
1389 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR",
1390 SPR_NOACCESS, SPR_NOACCESS,
1391 &spr_read_generic, &spr_write_generic,
1392 0x00000000);
1393
1394 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR",
1395 SPR_NOACCESS, SPR_NOACCESS,
1396 &spr_read_generic, &spr_write_generic,
1397 0x00000000);
1398
1399 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0",
1400 SPR_NOACCESS, SPR_NOACCESS,
1401 &spr_read_generic, &spr_write_generic,
1402 0x00000000);
1403
1404 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1",
1405 SPR_NOACCESS, SPR_NOACCESS,
1406 &spr_read_generic, &spr_write_generic,
1407 0x00000000);
1408
1409 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2",
1410 SPR_NOACCESS, SPR_NOACCESS,
1411 &spr_read_generic, &spr_write_generic,
1412 0x00000000);
1413
1414 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3",
1415 SPR_NOACCESS, SPR_NOACCESS,
1416 &spr_read_generic, &spr_write_generic,
1417 0x00000000);
1418
1419 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0",
1420 SPR_NOACCESS, SPR_NOACCESS,
1421 &spr_read_generic, &spr_write_generic,
1422 0x00000000);
1423
1424 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1",
1425 SPR_NOACCESS, SPR_NOACCESS,
1426 &spr_read_generic, &spr_write_generic,
1427 0x00000000);
1428
1429 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2",
1430 SPR_NOACCESS, SPR_NOACCESS,
1431 &spr_read_generic, &spr_write_generic,
1432 0x00000000);
1433
1434 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3",
1435 SPR_NOACCESS, SPR_NOACCESS,
1436 &spr_read_generic, &spr_write_generic,
1437 0x00000000);
1438
1439 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0",
1440 SPR_NOACCESS, SPR_NOACCESS,
1441 &spr_read_generic, &spr_write_generic,
1442 0x00000000);
1443
1444 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1",
1445 SPR_NOACCESS, SPR_NOACCESS,
1446 &spr_read_generic, &spr_write_generic,
1447 0x00000000);
1448
1449 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2",
1450 SPR_NOACCESS, SPR_NOACCESS,
1451 &spr_read_generic, &spr_write_generic,
1452 0x00000000);
1453
1454 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3",
1455 SPR_NOACCESS, SPR_NOACCESS,
1456 &spr_read_generic, &spr_write_generic,
1457 0x00000000);
1458
1459 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0",
1460 SPR_NOACCESS, SPR_NOACCESS,
1461 &spr_read_generic, &spr_write_generic,
1462 0x00000000);
1463
1464 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1",
1465 SPR_NOACCESS, SPR_NOACCESS,
1466 &spr_read_generic, &spr_write_generic,
1467 0x00000000);
1468
1469 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2",
1470 SPR_NOACCESS, SPR_NOACCESS,
1471 &spr_read_generic, &spr_write_generic,
1472 0x00000000);
1473
1474 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3",
1475 SPR_NOACCESS, SPR_NOACCESS,
1476 &spr_read_generic, &spr_write_generic,
1477 0x00000000);
1478
1479 spr_register(env, SPR_RCPU_FPECR, "FPECR",
1480 SPR_NOACCESS, SPR_NOACCESS,
1481 &spr_read_generic, &spr_write_generic,
1482 0x00000000);
1483 }
1484
1485 static void register_8xx_sprs(CPUPPCState *env)
1486 {
1487
1488 spr_register(env, SPR_MPC_IC_CST, "IC_CST",
1489 SPR_NOACCESS, SPR_NOACCESS,
1490 &spr_read_generic, &spr_write_generic,
1491 0x00000000);
1492
1493 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR",
1494 SPR_NOACCESS, SPR_NOACCESS,
1495 &spr_read_generic, &spr_write_generic,
1496 0x00000000);
1497
1498 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT",
1499 SPR_NOACCESS, SPR_NOACCESS,
1500 &spr_read_generic, &spr_write_generic,
1501 0x00000000);
1502
1503 spr_register(env, SPR_MPC_DC_CST, "DC_CST",
1504 SPR_NOACCESS, SPR_NOACCESS,
1505 &spr_read_generic, &spr_write_generic,
1506 0x00000000);
1507
1508 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR",
1509 SPR_NOACCESS, SPR_NOACCESS,
1510 &spr_read_generic, &spr_write_generic,
1511 0x00000000);
1512
1513 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT",
1514 SPR_NOACCESS, SPR_NOACCESS,
1515 &spr_read_generic, &spr_write_generic,
1516 0x00000000);
1517
1518 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR",
1519 SPR_NOACCESS, SPR_NOACCESS,
1520 &spr_read_generic, &spr_write_generic,
1521 0x00000000);
1522
1523 spr_register(env, SPR_MPC_MI_AP, "MI_AP",
1524 SPR_NOACCESS, SPR_NOACCESS,
1525 &spr_read_generic, &spr_write_generic,
1526 0x00000000);
1527
1528 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN",
1529 SPR_NOACCESS, SPR_NOACCESS,
1530 &spr_read_generic, &spr_write_generic,
1531 0x00000000);
1532
1533 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC",
1534 SPR_NOACCESS, SPR_NOACCESS,
1535 &spr_read_generic, &spr_write_generic,
1536 0x00000000);
1537
1538 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN",
1539 SPR_NOACCESS, SPR_NOACCESS,
1540 &spr_read_generic, &spr_write_generic,
1541 0x00000000);
1542
1543 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM",
1544 SPR_NOACCESS, SPR_NOACCESS,
1545 &spr_read_generic, &spr_write_generic,
1546 0x00000000);
1547
1548 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0",
1549 SPR_NOACCESS, SPR_NOACCESS,
1550 &spr_read_generic, &spr_write_generic,
1551 0x00000000);
1552
1553 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1",
1554 SPR_NOACCESS, SPR_NOACCESS,
1555 &spr_read_generic, &spr_write_generic,
1556 0x00000000);
1557
1558 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR",
1559 SPR_NOACCESS, SPR_NOACCESS,
1560 &spr_read_generic, &spr_write_generic,
1561 0x00000000);
1562
1563 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID",
1564 SPR_NOACCESS, SPR_NOACCESS,
1565 &spr_read_generic, &spr_write_generic,
1566 0x00000000);
1567
1568 spr_register(env, SPR_MPC_MD_AP, "MD_AP",
1569 SPR_NOACCESS, SPR_NOACCESS,
1570 &spr_read_generic, &spr_write_generic,
1571 0x00000000);
1572
1573 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN",
1574 SPR_NOACCESS, SPR_NOACCESS,
1575 &spr_read_generic, &spr_write_generic,
1576 0x00000000);
1577
1578 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB",
1579 SPR_NOACCESS, SPR_NOACCESS,
1580 &spr_read_generic, &spr_write_generic,
1581 0x00000000);
1582
1583 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC",
1584 SPR_NOACCESS, SPR_NOACCESS,
1585 &spr_read_generic, &spr_write_generic,
1586 0x00000000);
1587
1588 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN",
1589 SPR_NOACCESS, SPR_NOACCESS,
1590 &spr_read_generic, &spr_write_generic,
1591 0x00000000);
1592
1593 spr_register(env, SPR_MPC_MD_TW, "MD_TW",
1594 SPR_NOACCESS, SPR_NOACCESS,
1595 &spr_read_generic, &spr_write_generic,
1596 0x00000000);
1597
1598 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM",
1599 SPR_NOACCESS, SPR_NOACCESS,
1600 &spr_read_generic, &spr_write_generic,
1601 0x00000000);
1602
1603 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0",
1604 SPR_NOACCESS, SPR_NOACCESS,
1605 &spr_read_generic, &spr_write_generic,
1606 0x00000000);
1607
1608 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1",
1609 SPR_NOACCESS, SPR_NOACCESS,
1610 &spr_read_generic, &spr_write_generic,
1611 0x00000000);
1612 }
1613
1614 /*
1615 * AMR => SPR 29 (Power 2.04)
1616 * CTRL => SPR 136 (Power 2.04)
1617 * CTRL => SPR 152 (Power 2.04)
1618 * SCOMC => SPR 276 (64 bits ?)
1619 * SCOMD => SPR 277 (64 bits ?)
1620 * TBU40 => SPR 286 (Power 2.04 hypv)
1621 * HSPRG0 => SPR 304 (Power 2.04 hypv)
1622 * HSPRG1 => SPR 305 (Power 2.04 hypv)
1623 * HDSISR => SPR 306 (Power 2.04 hypv)
1624 * HDAR => SPR 307 (Power 2.04 hypv)
1625 * PURR => SPR 309 (Power 2.04 hypv)
1626 * HDEC => SPR 310 (Power 2.04 hypv)
1627 * HIOR => SPR 311 (hypv)
1628 * RMOR => SPR 312 (970)
1629 * HRMOR => SPR 313 (Power 2.04 hypv)
1630 * HSRR0 => SPR 314 (Power 2.04 hypv)
1631 * HSRR1 => SPR 315 (Power 2.04 hypv)
1632 * LPIDR => SPR 317 (970)
1633 * HEIR => SPR 339 (Power 2.05 hypv) (64-bit reg from 3.1)
1634 * EPR => SPR 702 (Power 2.04 emb)
1635 * perf => 768-783 (Power 2.04)
1636 * perf => 784-799 (Power 2.04)
1637 * PPR => SPR 896 (Power 2.04)
1638 * DABRX => 1015 (Power 2.04 hypv)
1639 * FPECR => SPR 1022 (?)
1640 * ... and more (thermal management, performance counters, ...)
1641 */
1642
1643 /*****************************************************************************/
1644 /* Exception vectors models */
1645 static void init_excp_4xx_softmmu(CPUPPCState *env)
1646 {
1647 #if !defined(CONFIG_USER_ONLY)
1648 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
1649 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1650 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1651 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1652 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1653 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1654 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1655 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1656 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
1657 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
1658 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
1659 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100;
1660 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200;
1661 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
1662 env->ivor_mask = 0x0000FFF0UL;
1663 env->ivpr_mask = 0xFFFF0000UL;
1664 /* Hardware reset vector */
1665 env->hreset_vector = 0xFFFFFFFCUL;
1666 #endif
1667 }
1668
1669 static void init_excp_MPC5xx(CPUPPCState *env)
1670 {
1671 #if !defined(CONFIG_USER_ONLY)
1672 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1673 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1674 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1675 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1676 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1677 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1678 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1679 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1680 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1681 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
1682 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
1683 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
1684 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
1685 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
1686 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
1687 env->ivor_mask = 0x0000FFF0UL;
1688 env->ivpr_mask = 0xFFFF0000UL;
1689 /* Hardware reset vector */
1690 env->hreset_vector = 0x00000100UL;
1691 #endif
1692 }
1693
1694 static void init_excp_MPC8xx(CPUPPCState *env)
1695 {
1696 #if !defined(CONFIG_USER_ONLY)
1697 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1698 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1699 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1700 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1701 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1702 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1703 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1704 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1705 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1706 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1707 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1708 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
1709 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
1710 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100;
1711 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200;
1712 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300;
1713 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400;
1714 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
1715 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
1716 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
1717 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
1718 env->ivor_mask = 0x0000FFF0UL;
1719 env->ivpr_mask = 0xFFFF0000UL;
1720 /* Hardware reset vector */
1721 env->hreset_vector = 0x00000100UL;
1722 #endif
1723 }
1724
1725 static void init_excp_G2(CPUPPCState *env)
1726 {
1727 #if !defined(CONFIG_USER_ONLY)
1728 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1729 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1730 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1731 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1732 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1733 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1734 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1735 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1736 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1737 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
1738 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1739 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1740 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
1741 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
1742 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
1743 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
1744 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
1745 /* Hardware reset vector */
1746 env->hreset_vector = 0x00000100UL;
1747 #endif
1748 }
1749
1750 static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask)
1751 {
1752 #if !defined(CONFIG_USER_ONLY)
1753 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC;
1754 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
1755 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
1756 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
1757 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
1758 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
1759 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
1760 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
1761 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
1762 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
1763 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
1764 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
1765 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
1766 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
1767 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
1768 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
1769 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
1770 /*
1771 * These two are the same IVOR as POWERPC_EXCP_VPU and
1772 * POWERPC_EXCP_VPUA. We deal with that when dispatching at
1773 * powerpc_excp().
1774 */
1775 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000;
1776 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000;
1777
1778 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000;
1779 env->ivor_mask = 0x0000FFF7UL;
1780 env->ivpr_mask = ivpr_mask;
1781 /* Hardware reset vector */
1782 env->hreset_vector = 0xFFFFFFFCUL;
1783 #endif
1784 }
1785
1786 static void init_excp_BookE(CPUPPCState *env)
1787 {
1788 #if !defined(CONFIG_USER_ONLY)
1789 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
1790 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
1791 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
1792 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
1793 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
1794 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
1795 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
1796 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
1797 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
1798 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
1799 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
1800 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
1801 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
1802 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
1803 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
1804 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
1805 env->ivor_mask = 0x0000FFF0UL;
1806 env->ivpr_mask = 0xFFFF0000UL;
1807 /* Hardware reset vector */
1808 env->hreset_vector = 0xFFFFFFFCUL;
1809 #endif
1810 }
1811
1812 static void init_excp_603(CPUPPCState *env)
1813 {
1814 #if !defined(CONFIG_USER_ONLY)
1815 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1816 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1817 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1818 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1819 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1820 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1821 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1822 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1823 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1824 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1825 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1826 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
1827 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
1828 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
1829 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
1830 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
1831 /* Hardware reset vector */
1832 env->hreset_vector = 0x00000100UL;
1833 #endif
1834 }
1835
1836 static void init_excp_604(CPUPPCState *env)
1837 {
1838 #if !defined(CONFIG_USER_ONLY)
1839 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1840 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1841 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1842 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1843 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1844 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1845 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1846 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1847 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1848 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1849 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1850 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
1851 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
1852 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
1853 /* Hardware reset vector */
1854 env->hreset_vector = 0x00000100UL;
1855 #endif
1856 }
1857
1858 static void init_excp_7x0(CPUPPCState *env)
1859 {
1860 #if !defined(CONFIG_USER_ONLY)
1861 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1862 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1863 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1864 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1865 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1866 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1867 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1868 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1869 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1870 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1871 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1872 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
1873 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
1874 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
1875 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
1876 /* Hardware reset vector */
1877 env->hreset_vector = 0x00000100UL;
1878 #endif
1879 }
1880
1881 static void init_excp_750cl(CPUPPCState *env)
1882 {
1883 #if !defined(CONFIG_USER_ONLY)
1884 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1885 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1886 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1887 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1888 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1889 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1890 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1891 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1892 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1893 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1894 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1895 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
1896 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
1897 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
1898 /* Hardware reset vector */
1899 env->hreset_vector = 0x00000100UL;
1900 #endif
1901 }
1902
1903 static void init_excp_750cx(CPUPPCState *env)
1904 {
1905 #if !defined(CONFIG_USER_ONLY)
1906 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1907 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1908 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1909 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1910 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1911 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1912 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1913 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1914 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1915 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1916 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1917 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
1918 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
1919 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
1920 /* Hardware reset vector */
1921 env->hreset_vector = 0x00000100UL;
1922 #endif
1923 }
1924
1925 /* XXX: Check if this is correct */
1926 static void init_excp_7x5(CPUPPCState *env)
1927 {
1928 #if !defined(CONFIG_USER_ONLY)
1929 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1930 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1931 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1932 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1933 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1934 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1935 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1936 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1937 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1938 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1939 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1940 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
1941 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
1942 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
1943 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
1944 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
1945 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
1946 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
1947 /* Hardware reset vector */
1948 env->hreset_vector = 0x00000100UL;
1949 #endif
1950 }
1951
1952 static void init_excp_7400(CPUPPCState *env)
1953 {
1954 #if !defined(CONFIG_USER_ONLY)
1955 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1956 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1957 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1958 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1959 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1960 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1961 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1962 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1963 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1964 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1965 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1966 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
1967 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
1968 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
1969 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
1970 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
1971 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
1972 /* Hardware reset vector */
1973 env->hreset_vector = 0x00000100UL;
1974 #endif
1975 }
1976
1977 static void init_excp_7450(CPUPPCState *env)
1978 {
1979 #if !defined(CONFIG_USER_ONLY)
1980 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1981 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1982 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1983 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1984 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1985 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1986 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1987 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1988 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1989 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1990 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1991 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
1992 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
1993 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
1994 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
1995 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
1996 /* Hardware reset vector */
1997 env->hreset_vector = 0x00000100UL;
1998 #endif
1999 }
2000
2001 #if defined(TARGET_PPC64)
2002 static void init_excp_970(CPUPPCState *env)
2003 {
2004 #if !defined(CONFIG_USER_ONLY)
2005 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2006 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2007 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2008 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
2009 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2010 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
2011 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2012 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2013 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2014 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2015 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2016 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
2017 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2018 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2019 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2020 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2021 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2022 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
2023 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
2024 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
2025 /* Hardware reset vector */
2026 env->hreset_vector = 0x0000000000000100ULL;
2027 #endif
2028 }
2029
2030 static void init_excp_POWER7(CPUPPCState *env)
2031 {
2032 #if !defined(CONFIG_USER_ONLY)
2033 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2034 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2035 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2036 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
2037 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2038 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
2039 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2040 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2041 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2042 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2043 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2044 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
2045 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2046 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2047 env->excp_vectors[POWERPC_EXCP_HDSI] = 0x00000E00;
2048 env->excp_vectors[POWERPC_EXCP_HISI] = 0x00000E20;
2049 env->excp_vectors[POWERPC_EXCP_HV_EMU] = 0x00000E40;
2050 env->excp_vectors[POWERPC_EXCP_HV_MAINT] = 0x00000E60;
2051 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2052 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2053 env->excp_vectors[POWERPC_EXCP_VSXU] = 0x00000F40;
2054 /* Hardware reset vector */
2055 env->hreset_vector = 0x0000000000000100ULL;
2056 #endif
2057 }
2058
2059 static void init_excp_POWER8(CPUPPCState *env)
2060 {
2061 init_excp_POWER7(env);
2062
2063 #if !defined(CONFIG_USER_ONLY)
2064 env->excp_vectors[POWERPC_EXCP_SDOOR] = 0x00000A00;
2065 env->excp_vectors[POWERPC_EXCP_FU] = 0x00000F60;
2066 env->excp_vectors[POWERPC_EXCP_HV_FU] = 0x00000F80;
2067 env->excp_vectors[POWERPC_EXCP_SDOOR_HV] = 0x00000E80;
2068
2069 /* Userland exceptions without vector value in PowerISA v3.1 */
2070 env->excp_vectors[POWERPC_EXCP_PERFM_EBB] = 0x0;
2071 env->excp_vectors[POWERPC_EXCP_EXTERNAL_EBB] = 0x0;
2072 #endif
2073 }
2074
2075 static void init_excp_POWER9(CPUPPCState *env)
2076 {
2077 init_excp_POWER8(env);
2078
2079 #if !defined(CONFIG_USER_ONLY)
2080 env->excp_vectors[POWERPC_EXCP_HVIRT] = 0x00000EA0;
2081 env->excp_vectors[POWERPC_EXCP_SYSCALL_VECTORED] = 0x00017000;
2082 #endif
2083 }
2084
2085 static void init_excp_POWER10(CPUPPCState *env)
2086 {
2087 init_excp_POWER9(env);
2088 }
2089
2090 #endif
2091
2092 static int check_pow_hid0(CPUPPCState *env)
2093 {
2094 if (env->spr[SPR_HID0] & 0x00E00000) {
2095 return 1;
2096 }
2097
2098 return 0;
2099 }
2100
2101 static int check_pow_hid0_74xx(CPUPPCState *env)
2102 {
2103 if (env->spr[SPR_HID0] & 0x00600000) {
2104 return 1;
2105 }
2106
2107 return 0;
2108 }
2109
2110 static void init_proc_405(CPUPPCState *env)
2111 {
2112 register_40x_sprs(env);
2113 register_405_sprs(env);
2114 register_usprgh_sprs(env);
2115
2116 /* Memory management */
2117 #if !defined(CONFIG_USER_ONLY)
2118 env->nb_tlb = 64;
2119 env->nb_ways = 1;
2120 env->id_tlbs = 0;
2121 env->tlb_type = TLB_EMB;
2122 #endif
2123 init_excp_4xx_softmmu(env);
2124 env->dcache_line_size = 32;
2125 env->icache_line_size = 32;
2126 /* Allocate hardware IRQ controller */
2127 ppc40x_irq_init(env_archcpu(env));
2128
2129 SET_FIT_PERIOD(8, 12, 16, 20);
2130 SET_WDT_PERIOD(16, 20, 24, 28);
2131 }
2132
2133 POWERPC_FAMILY(405)(ObjectClass *oc, void *data)
2134 {
2135 DeviceClass *dc = DEVICE_CLASS(oc);
2136 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2137
2138 dc->desc = "PowerPC 405";
2139 pcc->init_proc = init_proc_405;
2140 pcc->check_pow = check_pow_nocheck;
2141 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
2142 PPC_DCR | PPC_WRTEE |
2143 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
2144 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2145 PPC_MEM_SYNC | PPC_MEM_EIEIO |
2146 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
2147 PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP;
2148 pcc->msr_mask = (1ull << MSR_WE) |
2149 (1ull << MSR_CE) |
2150 (1ull << MSR_EE) |
2151 (1ull << MSR_PR) |
2152 (1ull << MSR_FP) |
2153 (1ull << MSR_ME) |
2154 (1ull << MSR_DWE) |
2155 (1ull << MSR_DE) |
2156 (1ull << MSR_IR) |
2157 (1ull << MSR_DR);
2158 pcc->mmu_model = POWERPC_MMU_SOFT_4xx;
2159 pcc->excp_model = POWERPC_EXCP_40x;
2160 pcc->bus_model = PPC_FLAGS_INPUT_405;
2161 pcc->bfd_mach = bfd_mach_ppc_403;
2162 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
2163 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
2164 }
2165
2166 static void init_proc_440EP(CPUPPCState *env)
2167 {
2168 register_BookE_sprs(env, 0x000000000000FFFFULL);
2169 register_440_sprs(env);
2170 register_usprgh_sprs(env);
2171
2172 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
2173 SPR_NOACCESS, SPR_NOACCESS,
2174 &spr_read_generic, &spr_write_generic,
2175 0x00000000);
2176 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
2177 SPR_NOACCESS, SPR_NOACCESS,
2178 &spr_read_generic, &spr_write_generic,
2179 0x00000000);
2180 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
2181 SPR_NOACCESS, SPR_NOACCESS,
2182 &spr_read_generic, &spr_write_generic,
2183 0x00000000);
2184
2185 spr_register(env, SPR_440_CCR1, "CCR1",
2186 SPR_NOACCESS, SPR_NOACCESS,
2187 &spr_read_generic, &spr_write_generic,
2188 0x00000000);
2189 /* Memory management */
2190 #if !defined(CONFIG_USER_ONLY)
2191 env->nb_tlb = 64;
2192 env->nb_ways = 1;
2193 env->id_tlbs = 0;
2194 env->tlb_type = TLB_EMB;
2195 #endif
2196 init_excp_BookE(env);
2197 env->dcache_line_size = 32;
2198 env->icache_line_size = 32;
2199 ppc40x_irq_init(env_archcpu(env));
2200
2201 SET_FIT_PERIOD(12, 16, 20, 24);
2202 SET_WDT_PERIOD(20, 24, 28, 32);
2203 }
2204
2205 POWERPC_FAMILY(440EP)(ObjectClass *oc, void *data)
2206 {
2207 DeviceClass *dc = DEVICE_CLASS(oc);
2208 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2209
2210 dc->desc = "PowerPC 440 EP";
2211 pcc->init_proc = init_proc_440EP;
2212 pcc->check_pow = check_pow_nocheck;
2213 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2214 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
2215 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
2216 PPC_FLOAT_STFIWX |
2217 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
2218 PPC_CACHE | PPC_CACHE_ICBI |
2219 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2220 PPC_MEM_TLBSYNC | PPC_MFTB |
2221 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
2222 PPC_440_SPEC;
2223 pcc->msr_mask = (1ull << MSR_POW) |
2224 (1ull << MSR_CE) |
2225 (1ull << MSR_EE) |
2226 (1ull << MSR_PR) |
2227 (1ull << MSR_FP) |
2228 (1ull << MSR_ME) |
2229 (1ull << MSR_FE0) |
2230 (1ull << MSR_DWE) |
2231 (1ull << MSR_DE) |
2232 (1ull << MSR_FE1) |
2233 (1ull << MSR_IR) |
2234 (1ull << MSR_DR);
2235 pcc->mmu_model = POWERPC_MMU_BOOKE;
2236 pcc->excp_model = POWERPC_EXCP_BOOKE;
2237 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
2238 pcc->bfd_mach = bfd_mach_ppc_403;
2239 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
2240 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
2241 }
2242
2243 POWERPC_FAMILY(460EX)(ObjectClass *oc, void *data)
2244 {
2245 DeviceClass *dc = DEVICE_CLASS(oc);
2246 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2247
2248 dc->desc = "PowerPC 460 EX";
2249 pcc->init_proc = init_proc_440EP;
2250 pcc->check_pow = check_pow_nocheck;
2251 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2252 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
2253 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
2254 PPC_FLOAT_STFIWX |
2255 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_RFMCI |
2256 PPC_CACHE | PPC_CACHE_ICBI |
2257 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2258 PPC_MEM_TLBSYNC | PPC_MFTB |
2259 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
2260 PPC_440_SPEC;
2261 pcc->msr_mask = (1ull << MSR_POW) |
2262 (1ull << MSR_CE) |
2263 (1ull << MSR_EE) |
2264 (1ull << MSR_PR) |
2265 (1ull << MSR_FP) |
2266 (1ull << MSR_ME) |
2267 (1ull << MSR_FE0) |
2268 (1ull << MSR_DWE) |
2269 (1ull << MSR_DE) |
2270 (1ull << MSR_FE1) |
2271 (1ull << MSR_IR) |
2272 (1ull << MSR_DR);
2273 pcc->mmu_model = POWERPC_MMU_BOOKE;
2274 pcc->excp_model = POWERPC_EXCP_BOOKE;
2275 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
2276 pcc->bfd_mach = bfd_mach_ppc_403;
2277 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
2278 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
2279 }
2280
2281 static void init_proc_440GP(CPUPPCState *env)
2282 {
2283 register_BookE_sprs(env, 0x000000000000FFFFULL);
2284 register_440_sprs(env);
2285 register_usprgh_sprs(env);
2286
2287 /* Memory management */
2288 #if !defined(CONFIG_USER_ONLY)
2289 env->nb_tlb = 64;
2290 env->nb_ways = 1;
2291 env->id_tlbs = 0;
2292 env->tlb_type = TLB_EMB;
2293 #endif
2294 init_excp_BookE(env);
2295 env->dcache_line_size = 32;
2296 env->icache_line_size = 32;
2297 /* XXX: TODO: allocate internal IRQ controller */
2298
2299 SET_FIT_PERIOD(12, 16, 20, 24);
2300 SET_WDT_PERIOD(20, 24, 28, 32);
2301 }
2302
2303 POWERPC_FAMILY(440GP)(ObjectClass *oc, void *data)
2304 {
2305 DeviceClass *dc = DEVICE_CLASS(oc);
2306 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2307
2308 dc->desc = "PowerPC 440 GP";
2309 pcc->init_proc = init_proc_440GP;
2310 pcc->check_pow = check_pow_nocheck;
2311 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2312 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI |
2313 PPC_CACHE | PPC_CACHE_ICBI |
2314 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2315 PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB |
2316 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
2317 PPC_440_SPEC;
2318 pcc->msr_mask = (1ull << MSR_POW) |
2319 (1ull << MSR_CE) |
2320 (1ull << MSR_EE) |
2321 (1ull << MSR_PR) |
2322 (1ull << MSR_FP) |
2323 (1ull << MSR_ME) |
2324 (1ull << MSR_FE0) |
2325 (1ull << MSR_DWE) |
2326 (1ull << MSR_DE) |
2327 (1ull << MSR_FE1) |
2328 (1ull << MSR_IR) |
2329 (1ull << MSR_DR);
2330 pcc->mmu_model = POWERPC_MMU_BOOKE;
2331 pcc->excp_model = POWERPC_EXCP_BOOKE;
2332 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
2333 pcc->bfd_mach = bfd_mach_ppc_403;
2334 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
2335 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
2336 }
2337
2338 static void init_proc_440x5(CPUPPCState *env)
2339 {
2340 register_BookE_sprs(env, 0x000000000000FFFFULL);
2341 register_440_sprs(env);
2342 register_usprgh_sprs(env);
2343
2344 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
2345 SPR_NOACCESS, SPR_NOACCESS,
2346 &spr_read_generic, &spr_write_generic,
2347 0x00000000);
2348 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
2349 SPR_NOACCESS, SPR_NOACCESS,
2350 &spr_read_generic, &spr_write_generic,
2351 0x00000000);
2352 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
2353 SPR_NOACCESS, SPR_NOACCESS,
2354 &spr_read_generic, &spr_write_generic,
2355 0x00000000);
2356
2357 spr_register(env, SPR_440_CCR1, "CCR1",
2358 SPR_NOACCESS, SPR_NOACCESS,
2359 &spr_read_generic, &spr_write_generic,
2360 0x00000000);
2361 /* Memory management */
2362 #if !defined(CONFIG_USER_ONLY)
2363 env->nb_tlb = 64;
2364 env->nb_ways = 1;
2365 env->id_tlbs = 0;
2366 env->tlb_type = TLB_EMB;
2367 #endif
2368 init_excp_BookE(env);
2369 env->dcache_line_size = 32;
2370 env->icache_line_size = 32;
2371 ppc40x_irq_init(env_archcpu(env));
2372
2373 SET_FIT_PERIOD(12, 16, 20, 24);
2374 SET_WDT_PERIOD(20, 24, 28, 32);
2375 }
2376
2377 POWERPC_FAMILY(440x5)(ObjectClass *oc, void *data)
2378 {
2379 DeviceClass *dc = DEVICE_CLASS(oc);
2380 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2381
2382 dc->desc = "PowerPC 440x5";
2383 pcc->init_proc = init_proc_440x5;
2384 pcc->check_pow = check_pow_nocheck;
2385 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2386 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
2387 PPC_CACHE | PPC_CACHE_ICBI |
2388 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2389 PPC_MEM_TLBSYNC | PPC_MFTB |
2390 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
2391 PPC_440_SPEC;
2392 pcc->msr_mask = (1ull << MSR_POW) |
2393 (1ull << MSR_CE) |
2394 (1ull << MSR_EE) |
2395 (1ull << MSR_PR) |
2396 (1ull << MSR_FP) |
2397 (1ull << MSR_ME) |
2398 (1ull << MSR_FE0) |
2399 (1ull << MSR_DWE) |
2400 (1ull << MSR_DE) |
2401 (1ull << MSR_FE1) |
2402 (1ull << MSR_IR) |
2403 (1ull << MSR_DR);
2404 pcc->mmu_model = POWERPC_MMU_BOOKE;
2405 pcc->excp_model = POWERPC_EXCP_BOOKE;
2406 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
2407 pcc->bfd_mach = bfd_mach_ppc_403;
2408 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
2409 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
2410 }
2411
2412 POWERPC_FAMILY(440x5wDFPU)(ObjectClass *oc, void *data)
2413 {
2414 DeviceClass *dc = DEVICE_CLASS(oc);
2415 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2416
2417 dc->desc = "PowerPC 440x5 with double precision FPU";
2418 pcc->init_proc = init_proc_440x5;
2419 pcc->check_pow = check_pow_nocheck;
2420 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2421 PPC_FLOAT | PPC_FLOAT_FSQRT |
2422 PPC_FLOAT_STFIWX |
2423 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
2424 PPC_CACHE | PPC_CACHE_ICBI |
2425 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2426 PPC_MEM_TLBSYNC | PPC_MFTB |
2427 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
2428 PPC_440_SPEC;
2429 pcc->insns_flags2 = PPC2_FP_CVT_S64;
2430 pcc->msr_mask = (1ull << MSR_POW) |
2431 (1ull << MSR_CE) |
2432 (1ull << MSR_EE) |
2433 (1ull << MSR_PR) |
2434 (1ull << MSR_FP) |
2435 (1ull << MSR_ME) |
2436 (1ull << MSR_FE0) |
2437 (1ull << MSR_DWE) |
2438 (1ull << MSR_DE) |
2439 (1ull << MSR_FE1) |
2440 (1ull << MSR_IR) |
2441 (1ull << MSR_DR);
2442 pcc->mmu_model = POWERPC_MMU_BOOKE;
2443 pcc->excp_model = POWERPC_EXCP_BOOKE;
2444 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
2445 pcc->bfd_mach = bfd_mach_ppc_403;
2446 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
2447 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
2448 }
2449
2450 static void init_proc_MPC5xx(CPUPPCState *env)
2451 {
2452 register_5xx_8xx_sprs(env);
2453 register_5xx_sprs(env);
2454 init_excp_MPC5xx(env);
2455 env->dcache_line_size = 32;
2456 env->icache_line_size = 32;
2457 /* XXX: TODO: allocate internal IRQ controller */
2458 }
2459
2460 POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, void *data)
2461 {
2462 DeviceClass *dc = DEVICE_CLASS(oc);
2463 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2464
2465 dc->desc = "Freescale 5xx cores (aka RCPU)";
2466 pcc->init_proc = init_proc_MPC5xx;
2467 pcc->check_pow = check_pow_none;
2468 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2469 PPC_MEM_EIEIO | PPC_MEM_SYNC |
2470 PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX |
2471 PPC_MFTB;
2472 pcc->msr_mask = (1ull << MSR_ILE) |
2473 (1ull << MSR_EE) |
2474 (1ull << MSR_PR) |
2475 (1ull << MSR_FP) |
2476 (1ull << MSR_ME) |
2477 (1ull << MSR_FE0) |
2478 (1ull << MSR_SE) |
2479 (1ull << MSR_DE) |
2480 (1ull << MSR_FE1) |
2481 (1ull << MSR_EP) |
2482 (1ull << MSR_RI) |
2483 (1ull << MSR_LE);
2484 pcc->mmu_model = POWERPC_MMU_REAL;
2485 pcc->excp_model = POWERPC_EXCP_6xx;
2486 pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
2487 pcc->bfd_mach = bfd_mach_ppc_505;
2488 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
2489 POWERPC_FLAG_BUS_CLK;
2490 }
2491
2492 static void init_proc_MPC8xx(CPUPPCState *env)
2493 {
2494 register_5xx_8xx_sprs(env);
2495 register_8xx_sprs(env);
2496 init_excp_MPC8xx(env);
2497 env->dcache_line_size = 32;
2498 env->icache_line_size = 32;
2499 /* XXX: TODO: allocate internal IRQ controller */
2500 }
2501
2502 POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, void *data)
2503 {
2504 DeviceClass *dc = DEVICE_CLASS(oc);
2505 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2506
2507 dc->desc = "Freescale 8xx cores (aka PowerQUICC)";
2508 pcc->init_proc = init_proc_MPC8xx;
2509 pcc->check_pow = check_pow_none;
2510 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2511 PPC_MEM_EIEIO | PPC_MEM_SYNC |
2512 PPC_CACHE_ICBI | PPC_MFTB;
2513 pcc->msr_mask = (1ull << MSR_ILE) |
2514 (1ull << MSR_EE) |
2515 (1ull << MSR_PR) |
2516 (1ull << MSR_FP) |
2517 (1ull << MSR_ME) |
2518 (1ull << MSR_SE) |
2519 (1ull << MSR_DE) |
2520 (1ull << MSR_EP) |
2521 (1ull << MSR_IR) |
2522 (1ull << MSR_DR) |
2523 (1ull << MSR_RI) |
2524 (1ull << MSR_LE);
2525 pcc->mmu_model = POWERPC_MMU_MPC8xx;
2526 pcc->excp_model = POWERPC_EXCP_6xx;
2527 pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
2528 pcc->bfd_mach = bfd_mach_ppc_860;
2529 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
2530 POWERPC_FLAG_BUS_CLK;
2531 }
2532
2533 /* Freescale 82xx cores (aka PowerQUICC-II) */
2534
2535 static void init_proc_G2(CPUPPCState *env)
2536 {
2537 register_non_embedded_sprs(env);
2538 register_sdr1_sprs(env);
2539 register_G2_sprs(env);
2540
2541 /* Memory management */
2542 register_low_BATs(env);
2543 register_high_BATs(env);
2544 register_6xx_7xx_soft_tlb(env, 64, 2);
2545 init_excp_G2(env);
2546 env->dcache_line_size = 32;
2547 env->icache_line_size = 32;
2548 /* Allocate hardware IRQ controller */
2549 ppc6xx_irq_init(env_archcpu(env));
2550 }
2551
2552 POWERPC_FAMILY(G2)(ObjectClass *oc, void *data)
2553 {
2554 DeviceClass *dc = DEVICE_CLASS(oc);
2555 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2556
2557 dc->desc = "PowerPC G2";
2558 pcc->init_proc = init_proc_G2;
2559 pcc->check_pow = check_pow_hid0;
2560 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
2561 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
2562 PPC_FLOAT_STFIWX |
2563 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
2564 PPC_MEM_SYNC | PPC_MEM_EIEIO |
2565 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
2566 PPC_SEGMENT | PPC_EXTERN;
2567 pcc->msr_mask = (1ull << MSR_POW) |
2568 (1ull << MSR_TGPR) |
2569 (1ull << MSR_EE) |
2570 (1ull << MSR_PR) |
2571 (1ull << MSR_FP) |
2572 (1ull << MSR_ME) |
2573 (1ull << MSR_FE0) |
2574 (1ull << MSR_SE) |
2575 (1ull << MSR_DE) |
2576 (1ull << MSR_FE1) |
2577 (1ull << MSR_AL) |
2578 (1ull << MSR_EP) |
2579 (1ull << MSR_IR) |
2580 (1ull << MSR_DR) |
2581 (1ull << MSR_RI);
2582 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
2583 pcc->excp_model = POWERPC_EXCP_6xx;
2584 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
2585 pcc->bfd_mach = bfd_mach_ppc_ec603e;
2586 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
2587 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
2588 }
2589
2590 POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data)
2591 {
2592 DeviceClass *dc = DEVICE_CLASS(oc);
2593 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2594
2595 dc->desc = "PowerPC G2LE";
2596 pcc->init_proc = init_proc_G2;
2597 pcc->check_pow = check_pow_hid0;
2598 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
2599 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
2600 PPC_FLOAT_STFIWX |
2601 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
2602 PPC_MEM_SYNC | PPC_MEM_EIEIO |
2603 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
2604 PPC_SEGMENT | PPC_EXTERN;
2605 pcc->msr_mask = (1ull << MSR_POW) |
2606 (1ull << MSR_TGPR) |
2607 (1ull << MSR_ILE) |
2608 (1ull << MSR_EE) |
2609 (1ull << MSR_PR) |
2610 (1ull << MSR_FP) |
2611 (1ull << MSR_ME) |
2612 (1ull << MSR_FE0) |
2613 (1ull << MSR_SE) |
2614 (1ull << MSR_DE) |
2615 (1ull << MSR_FE1) |
2616 (1ull << MSR_AL) |
2617 (1ull << MSR_EP) |
2618 (1ull << MSR_IR) |
2619 (1ull << MSR_DR) |
2620 (1ull << MSR_RI) |
2621 (1ull << MSR_LE);
2622 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
2623 pcc->excp_model = POWERPC_EXCP_6xx;
2624 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
2625 pcc->bfd_mach = bfd_mach_ppc_ec603e;
2626 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
2627 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
2628 }
2629
2630 static void init_proc_e200(CPUPPCState *env)
2631 {
2632 register_BookE_sprs(env, 0x000000070000FFFFULL);
2633
2634 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
2635 &spr_read_spefscr, &spr_write_spefscr,
2636 &spr_read_spefscr, &spr_write_spefscr,
2637 0x00000000);
2638 /* Memory management */
2639 register_BookE206_sprs(env, 0x0000005D, NULL, 0);
2640 register_usprgh_sprs(env);
2641
2642 spr_register(env, SPR_HID0, "HID0",
2643 SPR_NOACCESS, SPR_NOACCESS,
2644 &spr_read_generic, &spr_write_generic,
2645 0x00000000);
2646
2647 spr_register(env, SPR_HID1, "HID1",
2648 SPR_NOACCESS, SPR_NOACCESS,
2649 &spr_read_generic, &spr_write_generic,
2650 0x00000000);
2651
2652 spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR",
2653 SPR_NOACCESS, SPR_NOACCESS,
2654 &spr_read_generic, &spr_write_generic,
2655 0x00000000);
2656
2657 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
2658 SPR_NOACCESS, SPR_NOACCESS,
2659 &spr_read_generic, &spr_write_generic,
2660 0x00000000);
2661
2662 spr_register(env, SPR_Exxx_CTXCR, "CTXCR",
2663 SPR_NOACCESS, SPR_NOACCESS,
2664 &spr_read_generic, &spr_write_generic,
2665 0x00000000);
2666
2667 spr_register(env, SPR_Exxx_DBCNT, "DBCNT",
2668 SPR_NOACCESS, SPR_NOACCESS,
2669 &spr_read_generic, &spr_write_generic,
2670 0x00000000);
2671
2672 spr_register(env, SPR_Exxx_DBCR3, "DBCR3",
2673 SPR_NOACCESS, SPR_NOACCESS,
2674 &spr_read_generic, &spr_write_generic,
2675 0x00000000);
2676
2677 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
2678 &spr_read_generic, SPR_NOACCESS,
2679 &spr_read_generic, SPR_NOACCESS,
2680 0x00000000);
2681
2682 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
2683 SPR_NOACCESS, SPR_NOACCESS,
2684 &spr_read_generic, &spr_write_generic,
2685 0x00000000);
2686
2687 spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0",
2688 SPR_NOACCESS, SPR_NOACCESS,
2689 &spr_read_generic, &spr_write_generic,
2690 0x00000000);
2691
2692 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
2693 SPR_NOACCESS, SPR_NOACCESS,
2694 &spr_read_generic, &spr_write_generic,
2695 0x00000000);
2696
2697 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
2698 SPR_NOACCESS, SPR_NOACCESS,
2699 &spr_read_generic, &spr_write_generic,
2700 0x00000000);
2701
2702 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
2703 SPR_NOACCESS, SPR_NOACCESS,
2704 &spr_read_generic, &spr_write_generic,
2705 0x00000000);
2706
2707 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
2708 SPR_NOACCESS, SPR_NOACCESS,
2709 &spr_read_generic, &spr_write_generic,
2710 0x00000000);
2711
2712 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
2713 SPR_NOACCESS, SPR_NOACCESS,
2714 &spr_read_generic, &spr_write_generic,
2715 0x00000000); /* TOFIX */
2716 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
2717 SPR_NOACCESS, SPR_NOACCESS,
2718 &spr_read_generic, &spr_write_generic,
2719 0x00000000);
2720 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
2721 SPR_NOACCESS, SPR_NOACCESS,
2722 &spr_read_generic, &spr_write_generic,
2723 0x00000000);
2724 #if !defined(CONFIG_USER_ONLY)
2725 env->nb_tlb = 64;
2726 env->nb_ways = 1;
2727 env->id_tlbs = 0;
2728 env->tlb_type = TLB_EMB;
2729 #endif
2730 init_excp_e200(env, 0xFFFF0000UL);
2731 env->dcache_line_size = 32;
2732 env->icache_line_size = 32;
2733 /* XXX: TODO: allocate internal IRQ controller */
2734 }
2735
2736 POWERPC_FAMILY(e200)(ObjectClass *oc, void *data)
2737 {
2738 DeviceClass *dc = DEVICE_CLASS(oc);
2739 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2740
2741 dc->desc = "e200 core";
2742 pcc->init_proc = init_proc_e200;
2743 pcc->check_pow = check_pow_hid0;
2744 /*
2745 * XXX: unimplemented instructions:
2746 * dcblc
2747 * dcbtlst
2748 * dcbtstls
2749 * icblc
2750 * icbtls
2751 * tlbivax
2752 * all SPE multiply-accumulate instructions
2753 */
2754 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
2755 PPC_SPE | PPC_SPE_SINGLE |
2756 PPC_WRTEE | PPC_RFDI |
2757 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
2758 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2759 PPC_MEM_TLBSYNC | PPC_TLBIVAX |
2760 PPC_BOOKE;
2761 pcc->msr_mask = (1ull << MSR_UCLE) |
2762 (1ull << MSR_SPE) |
2763 (1ull << MSR_POW) |
2764 (1ull << MSR_CE) |
2765 (1ull << MSR_EE) |
2766 (1ull << MSR_PR) |
2767 (1ull << MSR_FP) |
2768 (1ull << MSR_ME) |
2769 (1ull << MSR_FE0) |
2770 (1ull << MSR_DWE) |
2771 (1ull << MSR_DE) |
2772 (1ull << MSR_FE1) |
2773 (1ull << MSR_IR) |
2774 (1ull << MSR_DR);
2775 pcc->mmu_model = POWERPC_MMU_BOOKE206;
2776 pcc->excp_model = POWERPC_EXCP_BOOKE;
2777 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
2778 pcc->bfd_mach = bfd_mach_ppc_860;
2779 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
2780 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
2781 POWERPC_FLAG_BUS_CLK;
2782 }
2783
2784 enum fsl_e500_version {
2785 fsl_e500v1,
2786 fsl_e500v2,
2787 fsl_e500mc,
2788 fsl_e5500,
2789 fsl_e6500,
2790 };
2791
2792 static void init_proc_e500(CPUPPCState *env, int version)
2793 {
2794 uint32_t tlbncfg[2];
2795 uint64_t ivor_mask;
2796 uint64_t ivpr_mask = 0xFFFF0000ULL;
2797 uint32_t l1cfg0 = 0x3800 /* 8 ways */
2798 | 0x0020; /* 32 kb */
2799 uint32_t l1cfg1 = 0x3800 /* 8 ways */
2800 | 0x0020; /* 32 kb */
2801 uint32_t mmucfg = 0;
2802 #if !defined(CONFIG_USER_ONLY)
2803 int i;
2804 #endif
2805
2806 /*
2807 * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't
2808 * complain when accessing them.
2809 * register_BookE_sprs(env, 0x0000000F0000FD7FULL);
2810 */
2811 switch (version) {
2812 case fsl_e500v1:
2813 case fsl_e500v2:
2814 default:
2815 ivor_mask = 0x0000000F0000FFFFULL;
2816 break;
2817 case fsl_e500mc:
2818 case fsl_e5500:
2819 ivor_mask = 0x000003FE0000FFFFULL;
2820 break;
2821 case fsl_e6500:
2822 ivor_mask = 0x000003FF0000FFFFULL;
2823 break;
2824 }
2825 register_BookE_sprs(env, ivor_mask);
2826
2827 spr_register(env, SPR_USPRG3, "USPRG3",
2828 &spr_read_ureg, SPR_NOACCESS,
2829 &spr_read_ureg, SPR_NOACCESS,
2830 0x00000000);
2831
2832 /* Processor identification */
2833 spr_register(env, SPR_BOOKE_PIR, "PIR",
2834 SPR_NOACCESS, SPR_NOACCESS,
2835 &spr_read_generic, &spr_write_pir,
2836 0x00000000);
2837
2838 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
2839 &spr_read_spefscr, &spr_write_spefscr,
2840 &spr_read_spefscr, &spr_write_spefscr,
2841 0x00000000);
2842 #if !defined(CONFIG_USER_ONLY)
2843 /* Memory management */
2844 env->nb_pids = 3;
2845 env->nb_ways = 2;
2846 env->id_tlbs = 0;
2847 switch (version) {
2848 case fsl_e500v1:
2849 tlbncfg[0] = register_tlbncfg(2, 1, 1, 0, 256);
2850 tlbncfg[1] = register_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
2851 break;
2852 case fsl_e500v2:
2853 tlbncfg[0] = register_tlbncfg(4, 1, 1, 0, 512);
2854 tlbncfg[1] = register_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
2855 break;
2856 case fsl_e500mc:
2857 case fsl_e5500:
2858 tlbncfg[0] = register_tlbncfg(4, 1, 1, 0, 512);
2859 tlbncfg[1] = register_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64);
2860 break;
2861 case fsl_e6500:
2862 mmucfg = 0x6510B45;
2863 env->nb_pids = 1;
2864 tlbncfg[0] = 0x08052400;
2865 tlbncfg[1] = 0x40028040;
2866 break;
2867 default:
2868 cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n",
2869 env->spr[SPR_PVR]);
2870 }
2871 #endif
2872 /* Cache sizes */
2873 switch (version) {
2874 case fsl_e500v1:
2875 case fsl_e500v2:
2876 env->dcache_line_size = 32;
2877 env->icache_line_size = 32;
2878 break;
2879 case fsl_e500mc:
2880 case fsl_e5500:
2881 env->dcache_line_size = 64;
2882 env->icache_line_size = 64;
2883 l1cfg0 |= 0x1000000; /* 64 byte cache block size */
2884 l1cfg1 |= 0x1000000; /* 64 byte cache block size */
2885 break;
2886 case fsl_e6500:
2887 env->dcache_line_size = 32;
2888 env->icache_line_size = 32;
2889 l1cfg0 |= 0x0F83820;
2890 l1cfg1 |= 0x0B83820;
2891 break;
2892 default:
2893 cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n",
2894 env->spr[SPR_PVR]);
2895 }
2896 register_BookE206_sprs(env, 0x000000DF, tlbncfg, mmucfg);
2897 register_usprgh_sprs(env);
2898
2899 spr_register(env, SPR_HID0, "HID0",
2900 SPR_NOACCESS, SPR_NOACCESS,
2901 &spr_read_generic, &spr_write_generic,
2902 0x00000000);
2903
2904 spr_register(env, SPR_HID1, "HID1",
2905 SPR_NOACCESS, SPR_NOACCESS,
2906 &spr_read_generic, &spr_write_generic,
2907 0x00000000);
2908
2909 spr_register(env, SPR_Exxx_BBEAR, "BBEAR",
2910 SPR_NOACCESS, SPR_NOACCESS,
2911 &spr_read_generic, &spr_write_generic,
2912 0x00000000);
2913
2914 spr_register(env, SPR_Exxx_BBTAR, "BBTAR",
2915 SPR_NOACCESS, SPR_NOACCESS,
2916 &spr_read_generic, &spr_write_generic,
2917 0x00000000);
2918
2919 spr_register(env, SPR_Exxx_MCAR, "MCAR",
2920 SPR_NOACCESS, SPR_NOACCESS,
2921 &spr_read_generic, &spr_write_generic,
2922 0x00000000);
2923
2924 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
2925 SPR_NOACCESS, SPR_NOACCESS,
2926 &spr_read_generic, &spr_write_generic,
2927 0x00000000);
2928
2929 spr_register(env, SPR_Exxx_NPIDR, "NPIDR",
2930 SPR_NOACCESS, SPR_NOACCESS,
2931 &spr_read_generic, &spr_write_generic,
2932 0x00000000);
2933
2934 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
2935 SPR_NOACCESS, SPR_NOACCESS,
2936 &spr_read_generic, &spr_write_generic,
2937 0x00000000);
2938
2939 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
2940 &spr_read_generic, SPR_NOACCESS,
2941 &spr_read_generic, SPR_NOACCESS,
2942 l1cfg0);
2943 spr_register(env, SPR_Exxx_L1CFG1, "L1CFG1",
2944 &spr_read_generic, SPR_NOACCESS,
2945 &spr_read_generic, SPR_NOACCESS,
2946 l1cfg1);
2947 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
2948 SPR_NOACCESS, SPR_NOACCESS,
2949 &spr_read_generic, &spr_write_e500_l1csr0,
2950 0x00000000);
2951 spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1",
2952 SPR_NOACCESS, SPR_NOACCESS,
2953 &spr_read_generic, &spr_write_e500_l1csr1,
2954 0x00000000);
2955 if (version != fsl_e500v1 && version != fsl_e500v2) {
2956 spr_register(env, SPR_Exxx_L2CSR0, "L2CSR0",
2957 SPR_NOACCESS, SPR_NOACCESS,
2958 &spr_read_generic, &spr_write_e500_l2csr0,
2959 0x00000000);
2960 }
2961 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
2962 SPR_NOACCESS, SPR_NOACCESS,
2963 &spr_read_generic, &spr_write_generic,
2964 0x00000000);
2965 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
2966 SPR_NOACCESS, SPR_NOACCESS,
2967 &spr_read_generic, &spr_write_generic,
2968 0x00000000);
2969 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
2970 SPR_NOACCESS, SPR_NOACCESS,
2971 &spr_read_generic, &spr_write_booke206_mmucsr0,
2972 0x00000000);
2973 spr_register(env, SPR_BOOKE_EPR, "EPR",
2974 SPR_NOACCESS, SPR_NOACCESS,
2975 &spr_read_generic, SPR_NOACCESS,
2976 0x00000000);
2977 /* XXX better abstract into Emb.xxx features */
2978 if ((version == fsl_e5500) || (version == fsl_e6500)) {
2979 spr_register(env, SPR_BOOKE_EPCR, "EPCR",
2980 SPR_NOACCESS, SPR_NOACCESS,
2981 &spr_read_generic, &spr_write_generic,
2982 0x00000000);
2983 spr_register(env, SPR_BOOKE_MAS7_MAS3, "MAS7_MAS3",
2984 SPR_NOACCESS, SPR_NOACCESS,
2985 &spr_read_mas73, &spr_write_mas73,
2986 0x00000000);
2987 ivpr_mask = (target_ulong)~0xFFFFULL;
2988 }
2989
2990 if (version == fsl_e6500) {
2991 /* Thread identification */
2992 spr_register(env, SPR_TIR, "TIR",
2993 SPR_NOACCESS, SPR_NOACCESS,
2994 &spr_read_generic, SPR_NOACCESS,
2995 0x00000000);
2996 spr_register(env, SPR_BOOKE_TLB0PS, "TLB0PS",
2997 SPR_NOACCESS, SPR_NOACCESS,
2998 &spr_read_generic, SPR_NOACCESS,
2999 0x00000004);
3000 spr_register(env, SPR_BOOKE_TLB1PS, "TLB1PS",
3001 SPR_NOACCESS, SPR_NOACCESS,
3002 &spr_read_generic, SPR_NOACCESS,
3003 0x7FFFFFFC);
3004 }
3005
3006 #if !defined(CONFIG_USER_ONLY)
3007 env->nb_tlb = 0;
3008 env->tlb_type = TLB_MAS;
3009 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
3010 env->nb_tlb += booke206_tlb_size(env, i);
3011 }
3012 #endif
3013
3014 init_excp_e200(env, ivpr_mask);
3015 /* Allocate hardware IRQ controller */
3016 ppce500_irq_init(env_archcpu(env));
3017 }
3018
3019 static void init_proc_e500v1(CPUPPCState *env)
3020 {
3021 init_proc_e500(env, fsl_e500v1);
3022 }
3023
3024 POWERPC_FAMILY(e500v1)(ObjectClass *oc, void *data)
3025 {
3026 DeviceClass *dc = DEVICE_CLASS(oc);
3027 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3028
3029 dc->desc = "e500v1 core";
3030 pcc->init_proc = init_proc_e500v1;
3031 pcc->check_pow = check_pow_hid0;
3032 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
3033 PPC_SPE | PPC_SPE_SINGLE |
3034 PPC_WRTEE | PPC_RFDI |
3035 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
3036 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3037 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
3038 pcc->insns_flags2 = PPC2_BOOKE206;
3039 pcc->msr_mask = (1ull << MSR_UCLE) |
3040 (1ull << MSR_SPE) |
3041 (1ull << MSR_POW) |
3042 (1ull << MSR_CE) |
3043 (1ull << MSR_EE) |
3044 (1ull << MSR_PR) |
3045 (1ull << MSR_FP) |
3046 (1ull << MSR_ME) |
3047 (1ull << MSR_FE0) |
3048 (1ull << MSR_DWE) |
3049 (1ull << MSR_DE) |
3050 (1ull << MSR_FE1) |
3051 (1ull << MSR_IR) |
3052 (1ull << MSR_DR);
3053 pcc->mmu_model = POWERPC_MMU_BOOKE206;
3054 pcc->excp_model = POWERPC_EXCP_BOOKE;
3055 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3056 pcc->bfd_mach = bfd_mach_ppc_860;
3057 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
3058 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
3059 POWERPC_FLAG_BUS_CLK;
3060 }
3061
3062 static void init_proc_e500v2(CPUPPCState *env)
3063 {
3064 init_proc_e500(env, fsl_e500v2);
3065 }
3066
3067 POWERPC_FAMILY(e500v2)(ObjectClass *oc, void *data)
3068 {
3069 DeviceClass *dc = DEVICE_CLASS(oc);
3070 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3071
3072 dc->desc = "e500v2 core";
3073 pcc->init_proc = init_proc_e500v2;
3074 pcc->check_pow = check_pow_hid0;
3075 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
3076 PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE |
3077 PPC_WRTEE | PPC_RFDI |
3078 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
3079 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3080 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
3081 pcc->insns_flags2 = PPC2_BOOKE206;
3082 pcc->msr_mask = (1ull << MSR_UCLE) |
3083 (1ull << MSR_SPE) |
3084 (1ull << MSR_POW) |
3085 (1ull << MSR_CE) |
3086 (1ull << MSR_EE) |
3087 (1ull << MSR_PR) |
3088 (1ull << MSR_FP) |
3089 (1ull << MSR_ME) |
3090 (1ull << MSR_FE0) |
3091 (1ull << MSR_DWE) |
3092 (1ull << MSR_DE) |
3093 (1ull << MSR_FE1) |
3094 (1ull << MSR_IR) |
3095 (1ull << MSR_DR);
3096 pcc->mmu_model = POWERPC_MMU_BOOKE206;
3097 pcc->excp_model = POWERPC_EXCP_BOOKE;
3098 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3099 pcc->bfd_mach = bfd_mach_ppc_860;
3100 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
3101 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
3102 POWERPC_FLAG_BUS_CLK;
3103 }
3104
3105 static void init_proc_e500mc(CPUPPCState *env)
3106 {
3107 init_proc_e500(env, fsl_e500mc);
3108 }
3109
3110 POWERPC_FAMILY(e500mc)(ObjectClass *oc, void *data)
3111 {
3112 DeviceClass *dc = DEVICE_CLASS(oc);
3113 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3114
3115 dc->desc = "e500mc core";
3116 pcc->init_proc = init_proc_e500mc;
3117 pcc->check_pow = check_pow_none;
3118 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB |
3119 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
3120 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
3121 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3122 PPC_FLOAT | PPC_FLOAT_FRES |
3123 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
3124 PPC_FLOAT_STFIWX | PPC_WAIT |
3125 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
3126 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL;
3127 pcc->msr_mask = (1ull << MSR_GS) |
3128 (1ull << MSR_UCLE) |
3129 (1ull << MSR_CE) |
3130 (1ull << MSR_EE) |
3131 (1ull << MSR_PR) |
3132 (1ull << MSR_FP) |
3133 (1ull << MSR_ME) |
3134 (1ull << MSR_FE0) |
3135 (1ull << MSR_DE) |
3136 (1ull << MSR_FE1) |
3137 (1ull << MSR_IR) |
3138 (1ull << MSR_DR) |
3139 (1ull << MSR_PX) |
3140 (1ull << MSR_RI);
3141 pcc->mmu_model = POWERPC_MMU_BOOKE206;
3142 pcc->excp_model = POWERPC_EXCP_BOOKE;
3143 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3144 /* FIXME: figure out the correct flag for e500mc */
3145 pcc->bfd_mach = bfd_mach_ppc_e500;
3146 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3147 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3148 }
3149
3150 #ifdef TARGET_PPC64
3151 static void init_proc_e5500(CPUPPCState *env)
3152 {
3153 init_proc_e500(env, fsl_e5500);
3154 }
3155
3156 POWERPC_FAMILY(e5500)(ObjectClass *oc, void *data)
3157 {
3158 DeviceClass *dc = DEVICE_CLASS(oc);
3159 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3160
3161 dc->desc = "e5500 core";
3162 pcc->init_proc = init_proc_e5500;
3163 pcc->check_pow = check_pow_none;
3164 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB |
3165 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
3166 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
3167 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3168 PPC_FLOAT | PPC_FLOAT_FRES |
3169 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
3170 PPC_FLOAT_STFIWX | PPC_WAIT |
3171 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC |
3172 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD;
3173 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 |
3174 PPC2_FP_CVT_S64;
3175 pcc->msr_mask = (1ull << MSR_CM) |
3176 (1ull << MSR_GS) |
3177 (1ull << MSR_UCLE) |
3178 (1ull << MSR_CE) |
3179 (1ull << MSR_EE) |
3180 (1ull << MSR_PR) |
3181 (1ull << MSR_FP) |
3182 (1ull << MSR_ME) |
3183 (1ull << MSR_FE0) |
3184 (1ull << MSR_DE) |
3185 (1ull << MSR_FE1) |
3186 (1ull << MSR_IR) |
3187 (1ull << MSR_DR) |
3188 (1ull << MSR_PX) |
3189 (1ull << MSR_RI);
3190 pcc->mmu_model = POWERPC_MMU_BOOKE206;
3191 pcc->excp_model = POWERPC_EXCP_BOOKE;
3192 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3193 /* FIXME: figure out the correct flag for e5500 */
3194 pcc->bfd_mach = bfd_mach_ppc_e500;
3195 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3196 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3197 }
3198
3199 static void init_proc_e6500(CPUPPCState *env)
3200 {
3201 init_proc_e500(env, fsl_e6500);
3202 }
3203
3204 POWERPC_FAMILY(e6500)(ObjectClass *oc, void *data)
3205 {
3206 DeviceClass *dc = DEVICE_CLASS(oc);
3207 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3208
3209 dc->desc = "e6500 core";
3210 pcc->init_proc = init_proc_e6500;
3211 pcc->check_pow = check_pow_none;
3212 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB |
3213 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
3214 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
3215 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3216 PPC_FLOAT | PPC_FLOAT_FRES |
3217 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
3218 PPC_FLOAT_STFIWX | PPC_WAIT |
3219 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC |
3220 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD | PPC_ALTIVEC;
3221 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 |
3222 PPC2_FP_CVT_S64 | PPC2_ATOMIC_ISA206;
3223 pcc->msr_mask = (1ull << MSR_CM) |
3224 (1ull << MSR_GS) |
3225 (1ull << MSR_UCLE) |
3226 (1ull << MSR_CE) |
3227 (1ull << MSR_EE) |
3228 (1ull << MSR_PR) |
3229 (1ull << MSR_FP) |
3230 (1ull << MSR_ME) |
3231 (1ull << MSR_FE0) |
3232 (1ull << MSR_DE) |
3233 (1ull << MSR_FE1) |
3234 (1ull << MSR_IS) |
3235 (1ull << MSR_DS) |
3236 (1ull << MSR_PX) |
3237 (1ull << MSR_RI) |
3238 (1ull << MSR_VR);
3239 pcc->mmu_model = POWERPC_MMU_BOOKE206;
3240 pcc->excp_model = POWERPC_EXCP_BOOKE;
3241 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3242 pcc->bfd_mach = bfd_mach_ppc_e500;
3243 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3244 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_VRE;
3245 }
3246
3247 #endif
3248
3249 /* Non-embedded PowerPC */
3250 static void init_proc_603(CPUPPCState *env)
3251 {
3252 register_non_embedded_sprs(env);
3253 register_sdr1_sprs(env);
3254 register_603_sprs(env);
3255
3256 /* Memory management */
3257 register_low_BATs(env);
3258 register_6xx_7xx_soft_tlb(env, 64, 2);
3259 init_excp_603(env);
3260 env->dcache_line_size = 32;
3261 env->icache_line_size = 32;
3262 /* Allocate hardware IRQ controller */
3263 ppc6xx_irq_init(env_archcpu(env));
3264 }
3265
3266 POWERPC_FAMILY(603)(ObjectClass *oc, void *data)
3267 {
3268 DeviceClass *dc = DEVICE_CLASS(oc);
3269 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3270
3271 dc->desc = "PowerPC 603";
3272 pcc->init_proc = init_proc_603;
3273 pcc->check_pow = check_pow_hid0;
3274 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3275 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3276 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3277 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3278 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3279 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
3280 PPC_SEGMENT | PPC_EXTERN;
3281 pcc->msr_mask = (1ull << MSR_POW) |
3282 (1ull << MSR_TGPR) |
3283 (1ull << MSR_ILE) |
3284 (1ull << MSR_EE) |
3285 (1ull << MSR_PR) |
3286 (1ull << MSR_FP) |
3287 (1ull << MSR_ME) |
3288 (1ull << MSR_FE0) |
3289 (1ull << MSR_SE) |
3290 (1ull << MSR_DE) |
3291 (1ull << MSR_FE1) |
3292 (1ull << MSR_EP) |
3293 (1ull << MSR_IR) |
3294 (1ull << MSR_DR) |
3295 (1ull << MSR_RI) |
3296 (1ull << MSR_LE);
3297 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
3298 pcc->excp_model = POWERPC_EXCP_6xx;
3299 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3300 pcc->bfd_mach = bfd_mach_ppc_603;
3301 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
3302 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
3303 }
3304
3305 POWERPC_FAMILY(603E)(ObjectClass *oc, void *data)
3306 {
3307 DeviceClass *dc = DEVICE_CLASS(oc);
3308 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3309
3310 dc->desc = "PowerPC 603e";
3311 pcc->init_proc = init_proc_603;
3312 pcc->check_pow = check_pow_hid0;
3313 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3314 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3315 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3316 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3317 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3318 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
3319 PPC_SEGMENT | PPC_EXTERN;
3320 pcc->msr_mask = (1ull << MSR_POW) |
3321 (1ull << MSR_TGPR) |
3322 (1ull << MSR_ILE) |
3323 (1ull << MSR_EE) |
3324 (1ull << MSR_PR) |
3325 (1ull << MSR_FP) |
3326 (1ull << MSR_ME) |
3327 (1ull << MSR_FE0) |
3328 (1ull << MSR_SE) |
3329 (1ull << MSR_DE) |
3330 (1ull << MSR_FE1) |
3331 (1ull << MSR_EP) |
3332 (1ull << MSR_IR) |
3333 (1ull << MSR_DR) |
3334 (1ull << MSR_RI) |
3335 (1ull << MSR_LE);
3336 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
3337 pcc->excp_model = POWERPC_EXCP_6xx;
3338 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3339 pcc->bfd_mach = bfd_mach_ppc_ec603e;
3340 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
3341 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
3342 }
3343
3344 static void init_proc_e300(CPUPPCState *env)
3345 {
3346 init_proc_603(env);
3347 register_e300_sprs(env);
3348 }
3349
3350 POWERPC_FAMILY(e300)(ObjectClass *oc, void *data)
3351 {
3352 DeviceClass *dc = DEVICE_CLASS(oc);
3353 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3354
3355 dc->desc = "e300 core";
3356 pcc->init_proc = init_proc_e300;
3357 pcc->check_pow = check_pow_hid0;
3358 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3359 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3360 PPC_FLOAT_STFIWX |
3361 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3362 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3363 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
3364 PPC_SEGMENT | PPC_EXTERN;
3365 pcc->msr_mask = (1ull << MSR_POW) |
3366 (1ull << MSR_TGPR) |
3367 (1ull << MSR_ILE) |
3368 (1ull << MSR_EE) |
3369 (1ull << MSR_PR) |
3370 (1ull << MSR_FP) |
3371 (1ull << MSR_ME) |
3372 (1ull << MSR_FE0) |
3373 (1ull << MSR_SE) |
3374 (1ull << MSR_DE) |
3375 (1ull << MSR_FE1) |
3376 (1ull << MSR_AL) |
3377 (1ull << MSR_EP) |
3378 (1ull << MSR_IR) |
3379 (1ull << MSR_DR) |
3380 (1ull << MSR_RI) |
3381 (1ull << MSR_LE);
3382 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
3383 pcc->excp_model = POWERPC_EXCP_6xx;
3384 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3385 pcc->bfd_mach = bfd_mach_ppc_603;
3386 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
3387 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
3388 }
3389
3390 static void init_proc_604(CPUPPCState *env)
3391 {
3392 register_non_embedded_sprs(env);
3393 register_sdr1_sprs(env);
3394 register_604_sprs(env);
3395
3396 /* Memory management */
3397 register_low_BATs(env);
3398 init_excp_604(env);
3399 env->dcache_line_size = 32;
3400 env->icache_line_size = 32;
3401 /* Allocate hardware IRQ controller */
3402 ppc6xx_irq_init(env_archcpu(env));
3403 }
3404
3405 POWERPC_FAMILY(604)(ObjectClass *oc, void *data)
3406 {
3407 DeviceClass *dc = DEVICE_CLASS(oc);
3408 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3409
3410 dc->desc = "PowerPC 604";
3411 pcc->init_proc = init_proc_604;
3412 pcc->check_pow = check_pow_nocheck;
3413 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3414 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3415 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3416 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3417 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3418 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
3419 PPC_SEGMENT | PPC_EXTERN;
3420 pcc->msr_mask = (1ull << MSR_POW) |
3421 (1ull << MSR_ILE) |
3422 (1ull << MSR_EE) |
3423 (1ull << MSR_PR) |
3424 (1ull << MSR_FP) |
3425 (1ull << MSR_ME) |
3426 (1ull << MSR_FE0) |
3427 (1ull << MSR_SE) |
3428 (1ull << MSR_DE) |
3429 (1ull << MSR_FE1) |
3430 (1ull << MSR_EP) |
3431 (1ull << MSR_IR) |
3432 (1ull << MSR_DR) |
3433 (1ull << MSR_PMM) |
3434 (1ull << MSR_RI) |
3435 (1ull << MSR_LE);
3436 pcc->mmu_model = POWERPC_MMU_32B;
3437 pcc->excp_model = POWERPC_EXCP_6xx;
3438 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3439 pcc->bfd_mach = bfd_mach_ppc_604;
3440 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
3441 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3442 }
3443
3444 static void init_proc_604E(CPUPPCState *env)
3445 {
3446 init_proc_604(env);
3447 register_604e_sprs(env);
3448 }
3449
3450 POWERPC_FAMILY(604E)(ObjectClass *oc, void *data)
3451 {
3452 DeviceClass *dc = DEVICE_CLASS(oc);
3453 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3454
3455 dc->desc = "PowerPC 604E";
3456 pcc->init_proc = init_proc_604E;
3457 pcc->check_pow = check_pow_nocheck;
3458 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3459 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3460 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3461 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3462 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3463 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
3464 PPC_SEGMENT | PPC_EXTERN;
3465 pcc->msr_mask = (1ull << MSR_POW) |
3466 (1ull << MSR_ILE) |
3467 (1ull << MSR_EE) |
3468 (1ull << MSR_PR) |
3469 (1ull << MSR_FP) |
3470 (1ull << MSR_ME) |
3471 (1ull << MSR_FE0) |
3472 (1ull << MSR_SE) |
3473 (1ull << MSR_DE) |
3474 (1ull << MSR_FE1) |
3475 (1ull << MSR_EP) |
3476 (1ull << MSR_IR) |
3477 (1ull << MSR_DR) |
3478 (1ull << MSR_PMM) |
3479 (1ull << MSR_RI) |
3480 (1ull << MSR_LE);
3481 pcc->mmu_model = POWERPC_MMU_32B;
3482 pcc->excp_model = POWERPC_EXCP_6xx;
3483 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3484 pcc->bfd_mach = bfd_mach_ppc_604;
3485 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
3486 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3487 }
3488
3489 static void init_proc_740(CPUPPCState *env)
3490 {
3491 register_non_embedded_sprs(env);
3492 register_sdr1_sprs(env);
3493 register_7xx_sprs(env);
3494 /* Thermal management */
3495 register_thrm_sprs(env);
3496
3497 /* Memory management */
3498 register_low_BATs(env);
3499 init_excp_7x0(env);
3500 env->dcache_line_size = 32;
3501 env->icache_line_size = 32;
3502 /* Allocate hardware IRQ controller */
3503 ppc6xx_irq_init(env_archcpu(env));
3504 }
3505
3506 POWERPC_FAMILY(740)(ObjectClass *oc, void *data)
3507 {
3508 DeviceClass *dc = DEVICE_CLASS(oc);
3509 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3510
3511 dc->desc = "PowerPC 740";
3512 pcc->init_proc = init_proc_740;
3513 pcc->check_pow = check_pow_hid0;
3514 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3515 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3516 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3517 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3518 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3519 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
3520 PPC_SEGMENT | PPC_EXTERN;
3521 pcc->msr_mask = (1ull << MSR_POW) |
3522 (1ull << MSR_ILE) |
3523 (1ull << MSR_EE) |
3524 (1ull << MSR_PR) |
3525 (1ull << MSR_FP) |
3526 (1ull << MSR_ME) |
3527 (1ull << MSR_FE0) |
3528 (1ull << MSR_SE) |
3529 (1ull << MSR_DE) |
3530 (1ull << MSR_FE1) |
3531 (1ull << MSR_EP) |
3532 (1ull << MSR_IR) |
3533 (1ull << MSR_DR) |
3534 (1ull << MSR_PMM) |
3535 (1ull << MSR_RI) |
3536 (1ull << MSR_LE);
3537 pcc->mmu_model = POWERPC_MMU_32B;
3538 pcc->excp_model = POWERPC_EXCP_7xx;
3539 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3540 pcc->bfd_mach = bfd_mach_ppc_750;
3541 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
3542 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3543 }
3544
3545 static void init_proc_750(CPUPPCState *env)
3546 {
3547 register_non_embedded_sprs(env);
3548 register_sdr1_sprs(env);
3549 register_7xx_sprs(env);
3550
3551 spr_register(env, SPR_L2CR, "L2CR",
3552 SPR_NOACCESS, SPR_NOACCESS,
3553 &spr_read_generic, spr_access_nop,
3554 0x00000000);
3555 /* Thermal management */
3556 register_thrm_sprs(env);
3557
3558 /* Memory management */
3559 register_low_BATs(env);
3560 /*
3561 * XXX: high BATs are also present but are known to be bugged on
3562 * die version 1.x
3563 */
3564 init_excp_7x0(env);
3565 env->dcache_line_size = 32;
3566 env->icache_line_size = 32;
3567 /* Allocate hardware IRQ controller */
3568 ppc6xx_irq_init(env_archcpu(env));
3569 }
3570
3571 POWERPC_FAMILY(750)(ObjectClass *oc, void *data)
3572 {
3573 DeviceClass *dc = DEVICE_CLASS(oc);
3574 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3575
3576 dc->desc = "PowerPC 750";
3577 pcc->init_proc = init_proc_750;
3578 pcc->check_pow = check_pow_hid0;
3579 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3580 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3581 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3582 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3583 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3584 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
3585 PPC_SEGMENT | PPC_EXTERN;
3586 pcc->msr_mask = (1ull << MSR_POW) |
3587 (1ull << MSR_ILE) |
3588 (1ull << MSR_EE) |
3589 (1ull << MSR_PR) |
3590 (1ull << MSR_FP) |
3591 (1ull << MSR_ME) |
3592 (1ull << MSR_FE0) |
3593 (1ull << MSR_SE) |
3594 (1ull << MSR_DE) |
3595 (1ull << MSR_FE1) |
3596 (1ull << MSR_EP) |
3597 (1ull << MSR_IR) |
3598 (1ull << MSR_DR) |
3599 (1ull << MSR_PMM) |
3600 (1ull << MSR_RI) |
3601 (1ull << MSR_LE);
3602 pcc->mmu_model = POWERPC_MMU_32B;
3603 pcc->excp_model = POWERPC_EXCP_7xx;
3604 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3605 pcc->bfd_mach = bfd_mach_ppc_750;
3606 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
3607 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3608 }
3609
3610 static void init_proc_750cl(CPUPPCState *env)
3611 {
3612 register_non_embedded_sprs(env);
3613 register_sdr1_sprs(env);
3614 register_7xx_sprs(env);
3615
3616 spr_register(env, SPR_L2CR, "L2CR",
3617 SPR_NOACCESS, SPR_NOACCESS,
3618 &spr_read_generic, spr_access_nop,
3619 0x00000000);
3620 /* Thermal management */
3621 /* Those registers are fake on 750CL */
3622 spr_register(env, SPR_THRM1, "THRM1",
3623 SPR_NOACCESS, SPR_NOACCESS,
3624 &spr_read_generic, &spr_write_generic,
3625 0x00000000);
3626 spr_register(env, SPR_THRM2, "THRM2",
3627 SPR_NOACCESS, SPR_NOACCESS,
3628 &spr_read_generic, &spr_write_generic,
3629 0x00000000);
3630 spr_register(env, SPR_THRM3, "THRM3",
3631 SPR_NOACCESS, SPR_NOACCESS,
3632 &spr_read_generic, &spr_write_generic,
3633 0x00000000);
3634
3635 spr_register(env, SPR_750_TDCL, "TDCL",
3636 SPR_NOACCESS, SPR_NOACCESS,
3637 &spr_read_generic, &spr_write_generic,
3638 0x00000000);
3639 spr_register(env, SPR_750_TDCH, "TDCH",
3640 SPR_NOACCESS, SPR_NOACCESS,
3641 &spr_read_generic, &spr_write_generic,
3642 0x00000000);
3643 /* DMA */
3644 spr_register(env, SPR_750_WPAR, "WPAR",
3645 SPR_NOACCESS, SPR_NOACCESS,
3646 &spr_read_generic, &spr_write_generic,
3647 0x00000000);
3648 spr_register(env, SPR_750_DMAL, "DMAL",
3649 SPR_NOACCESS, SPR_NOACCESS,
3650 &spr_read_generic, &spr_write_generic,
3651 0x00000000);
3652 spr_register(env, SPR_750_DMAU, "DMAU",
3653 SPR_NOACCESS, SPR_NOACCESS,
3654 &spr_read_generic, &spr_write_generic,
3655 0x00000000);
3656 /* Hardware implementation registers */
3657 spr_register(env, SPR_750CL_HID2, "HID2",
3658 SPR_NOACCESS, SPR_NOACCESS,
3659 &spr_read_generic, &spr_write_generic,
3660 0x00000000);
3661
3662 spr_register(env, SPR_750CL_HID4, "HID4",
3663 SPR_NOACCESS, SPR_NOACCESS,
3664 &spr_read_generic, &spr_write_generic,
3665 0x00000000);
3666 /* Quantization registers */
3667 spr_register(env, SPR_750_GQR0, "GQR0",
3668 SPR_NOACCESS, SPR_NOACCESS,
3669 &spr_read_generic, &spr_write_generic,
3670 0x00000000);
3671
3672 spr_register(env, SPR_750_GQR1, "GQR1",
3673 SPR_NOACCESS, SPR_NOACCESS,
3674 &spr_read_generic, &spr_write_generic,
3675 0x00000000);
3676
3677 spr_register(env, SPR_750_GQR2, "GQR2",
3678 SPR_NOACCESS, SPR_NOACCESS,
3679 &spr_read_generic, &spr_write_generic,
3680 0x00000000);
3681
3682 spr_register(env, SPR_750_GQR3, "GQR3",
3683 SPR_NOACCESS, SPR_NOACCESS,
3684 &spr_read_generic, &spr_write_generic,
3685 0x00000000);
3686
3687 spr_register(env, SPR_750_GQR4, "GQR4",
3688 SPR_NOACCESS, SPR_NOACCESS,
3689 &spr_read_generic, &spr_write_generic,
3690 0x00000000);
3691
3692 spr_register(env, SPR_750_GQR5, "GQR5",
3693 SPR_NOACCESS, SPR_NOACCESS,
3694 &spr_read_generic, &spr_write_generic,
3695 0x00000000);
3696
3697 spr_register(env, SPR_750_GQR6, "GQR6",
3698 SPR_NOACCESS, SPR_NOACCESS,
3699 &spr_read_generic, &spr_write_generic,
3700 0x00000000);
3701
3702 spr_register(env, SPR_750_GQR7, "GQR7",
3703 SPR_NOACCESS, SPR_NOACCESS,
3704 &spr_read_generic, &spr_write_generic,
3705 0x00000000);
3706 /* Memory management */
3707 register_low_BATs(env);
3708 /* PowerPC 750cl has 8 DBATs and 8 IBATs */
3709 register_high_BATs(env);
3710 init_excp_750cl(env);
3711 env->dcache_line_size = 32;
3712 env->icache_line_size = 32;
3713 /* Allocate hardware IRQ controller */
3714 ppc6xx_irq_init(env_archcpu(env));
3715 }
3716
3717 POWERPC_FAMILY(750cl)(ObjectClass *oc, void *data)
3718 {
3719 DeviceClass *dc = DEVICE_CLASS(oc);
3720 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3721
3722 dc->desc = "PowerPC 750 CL";
3723 pcc->init_proc = init_proc_750cl;
3724 pcc->check_pow = check_pow_hid0;
3725 /*
3726 * XXX: not implemented:
3727 * cache lock instructions:
3728 * dcbz_l
3729 * floating point paired instructions
3730 * psq_lux
3731 * psq_lx
3732 * psq_stux
3733 * psq_stx
3734 * ps_abs
3735 * ps_add
3736 * ps_cmpo0
3737 * ps_cmpo1
3738 * ps_cmpu0
3739 * ps_cmpu1
3740 * ps_div
3741 * ps_madd
3742 * ps_madds0
3743 * ps_madds1
3744 * ps_merge00
3745 * ps_merge01
3746 * ps_merge10
3747 * ps_merge11
3748 * ps_mr
3749 * ps_msub
3750 * ps_mul
3751 * ps_muls0
3752 * ps_muls1
3753 * ps_nabs
3754 * ps_neg
3755 * ps_nmadd
3756 * ps_nmsub
3757 * ps_res
3758 * ps_rsqrte
3759 * ps_sel
3760 * ps_sub
3761 * ps_sum0
3762 * ps_sum1
3763 */
3764 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3765 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3766 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3767 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3768 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3769 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
3770 PPC_SEGMENT | PPC_EXTERN;
3771 pcc->msr_mask = (1ull << MSR_POW) |
3772 (1ull << MSR_ILE) |
3773 (1ull << MSR_EE) |
3774 (1ull << MSR_PR) |
3775 (1ull << MSR_FP) |
3776 (1ull << MSR_ME) |
3777 (1ull << MSR_FE0) |
3778 (1ull << MSR_SE) |
3779 (1ull << MSR_DE) |
3780 (1ull << MSR_FE1) |
3781 (1ull << MSR_EP) |
3782 (1ull << MSR_IR) |
3783 (1ull << MSR_DR) |
3784 (1ull << MSR_PMM) |
3785 (1ull << MSR_RI) |
3786 (1ull << MSR_LE);
3787 pcc->mmu_model = POWERPC_MMU_32B;
3788 pcc->excp_model = POWERPC_EXCP_7xx;
3789 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3790 pcc->bfd_mach = bfd_mach_ppc_750;
3791 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
3792 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3793 }
3794
3795 static void init_proc_750cx(CPUPPCState *env)
3796 {
3797 register_non_embedded_sprs(env);
3798 register_sdr1_sprs(env);
3799 register_7xx_sprs(env);
3800
3801 spr_register(env, SPR_L2CR, "L2CR",
3802 SPR_NOACCESS, SPR_NOACCESS,
3803 &spr_read_generic, spr_access_nop,
3804 0x00000000);
3805 /* Thermal management */
3806 register_thrm_sprs(env);
3807
3808 spr_register(env, SPR_SDA, "SDA",
3809 SPR_NOACCESS, SPR_NOACCESS,
3810 &spr_read_generic, &spr_write_generic,
3811 0x00000000);
3812
3813 /* Memory management */
3814 register_low_BATs(env);
3815 /* PowerPC 750cx has 8 DBATs and 8 IBATs */
3816 register_high_BATs(env);
3817 init_excp_750cx(env);
3818 env->dcache_line_size = 32;
3819 env->icache_line_size = 32;
3820 /* Allocate hardware IRQ controller */
3821 ppc6xx_irq_init(env_archcpu(env));
3822 }
3823
3824 POWERPC_FAMILY(750cx)(ObjectClass *oc, void *data)
3825 {
3826 DeviceClass *dc = DEVICE_CLASS(oc);
3827 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3828
3829 dc->desc = "PowerPC 750CX";
3830 pcc->init_proc = init_proc_750cx;
3831 pcc->check_pow = check_pow_hid0;
3832 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3833 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3834 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3835 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3836 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3837 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
3838 PPC_SEGMENT | PPC_EXTERN;
3839 pcc->msr_mask = (1ull << MSR_POW) |
3840 (1ull << MSR_ILE) |
3841 (1ull << MSR_EE) |
3842 (1ull << MSR_PR) |
3843 (1ull << MSR_FP) |
3844 (1ull << MSR_ME) |
3845 (1ull << MSR_FE0) |
3846 (1ull << MSR_SE) |
3847 (1ull << MSR_DE) |
3848 (1ull << MSR_FE1) |
3849 (1ull << MSR_EP) |
3850 (1ull << MSR_IR) |
3851 (1ull << MSR_DR) |
3852 (1ull << MSR_PMM) |
3853 (1ull << MSR_RI) |
3854 (1ull << MSR_LE);
3855 pcc->mmu_model = POWERPC_MMU_32B;
3856 pcc->excp_model = POWERPC_EXCP_7xx;
3857 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3858 pcc->bfd_mach = bfd_mach_ppc_750;
3859 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
3860 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3861 }
3862
3863 static void init_proc_750fx(CPUPPCState *env)
3864 {
3865 register_non_embedded_sprs(env);
3866 register_sdr1_sprs(env);
3867 register_7xx_sprs(env);
3868
3869 spr_register(env, SPR_L2CR, "L2CR",
3870 SPR_NOACCESS, SPR_NOACCESS,
3871 &spr_read_generic, spr_access_nop,
3872 0x00000000);
3873 /* Thermal management */
3874 register_thrm_sprs(env);
3875
3876 spr_register(env, SPR_750_THRM4, "THRM4",
3877 SPR_NOACCESS, SPR_NOACCESS,
3878 &spr_read_generic, &spr_write_generic,
3879 0x00000000);
3880 /* Hardware implementation registers */
3881 spr_register(env, SPR_750FX_HID2, "HID2",
3882 SPR_NOACCESS, SPR_NOACCESS,
3883 &spr_read_generic, &spr_write_generic,
3884 0x00000000);
3885 /* Memory management */
3886 register_low_BATs(env);
3887 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
3888 register_high_BATs(env);
3889 init_excp_7x0(env);
3890 env->dcache_line_size = 32;
3891 env->icache_line_size = 32;
3892 /* Allocate hardware IRQ controller */
3893 ppc6xx_irq_init(env_archcpu(env));
3894 }
3895
3896 POWERPC_FAMILY(750fx)(ObjectClass *oc, void *data)
3897 {
3898 DeviceClass *dc = DEVICE_CLASS(oc);
3899 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3900
3901 dc->desc = "PowerPC 750FX";
3902 pcc->init_proc = init_proc_750fx;
3903 pcc->check_pow = check_pow_hid0;
3904 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3905 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3906 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3907 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3908 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3909 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
3910 PPC_SEGMENT | PPC_EXTERN;
3911 pcc->msr_mask = (1ull << MSR_POW) |
3912 (1ull << MSR_ILE) |
3913 (1ull << MSR_EE) |
3914 (1ull << MSR_PR) |
3915 (1ull << MSR_FP) |
3916 (1ull << MSR_ME) |
3917 (1ull << MSR_FE0) |
3918 (1ull << MSR_SE) |
3919 (1ull << MSR_DE) |
3920 (1ull << MSR_FE1) |
3921 (1ull << MSR_EP) |
3922 (1ull << MSR_IR) |
3923 (1ull << MSR_DR) |
3924 (1ull << MSR_PMM) |
3925 (1ull << MSR_RI) |
3926 (1ull << MSR_LE);
3927 pcc->mmu_model = POWERPC_MMU_32B;
3928 pcc->excp_model = POWERPC_EXCP_7xx;
3929 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3930 pcc->bfd_mach = bfd_mach_ppc_750;
3931 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
3932 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3933 }
3934
3935 static void init_proc_750gx(CPUPPCState *env)
3936 {
3937 register_non_embedded_sprs(env);
3938 register_sdr1_sprs(env);
3939 register_7xx_sprs(env);
3940
3941 spr_register(env, SPR_L2CR, "L2CR",
3942 SPR_NOACCESS, SPR_NOACCESS,
3943 &spr_read_generic, spr_access_nop,
3944 0x00000000);
3945 /* Thermal management */
3946 register_thrm_sprs(env);
3947
3948 spr_register(env, SPR_750_THRM4, "THRM4",
3949 SPR_NOACCESS, SPR_NOACCESS,
3950 &spr_read_generic, &spr_write_generic,
3951 0x00000000);
3952 /* Hardware implementation registers */
3953 spr_register(env, SPR_750FX_HID2, "HID2",
3954 SPR_NOACCESS, SPR_NOACCESS,
3955 &spr_read_generic, &spr_write_generic,
3956 0x00000000);
3957 /* Memory management */
3958 register_low_BATs(env);
3959 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
3960 register_high_BATs(env);
3961 init_excp_7x0(env);
3962 env->dcache_line_size = 32;
3963 env->icache_line_size = 32;
3964 /* Allocate hardware IRQ controller */
3965 ppc6xx_irq_init(env_archcpu(env));
3966 }
3967
3968 POWERPC_FAMILY(750gx)(ObjectClass *oc, void *data)
3969 {
3970 DeviceClass *dc = DEVICE_CLASS(oc);
3971 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3972
3973 dc->desc = "PowerPC 750GX";
3974 pcc->init_proc = init_proc_750gx;
3975 pcc->check_pow = check_pow_hid0;
3976 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3977 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3978 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3979 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3980 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3981 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
3982 PPC_SEGMENT | PPC_EXTERN;
3983 pcc->msr_mask = (1ull << MSR_POW) |
3984 (1ull << MSR_ILE) |
3985 (1ull << MSR_EE) |
3986 (1ull << MSR_PR) |
3987 (1ull << MSR_FP) |
3988 (1ull << MSR_ME) |
3989 (1ull << MSR_FE0) |
3990 (1ull << MSR_SE) |
3991 (1ull << MSR_DE) |
3992 (1ull << MSR_FE1) |
3993 (1ull << MSR_EP) |
3994 (1ull << MSR_IR) |
3995 (1ull << MSR_DR) |
3996 (1ull << MSR_PMM) |
3997 (1ull << MSR_RI) |
3998 (1ull << MSR_LE);
3999 pcc->mmu_model = POWERPC_MMU_32B;
4000 pcc->excp_model = POWERPC_EXCP_7xx;
4001 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4002 pcc->bfd_mach = bfd_mach_ppc_750;
4003 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4004 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4005 }
4006
4007 static void init_proc_745(CPUPPCState *env)
4008 {
4009 register_non_embedded_sprs(env);
4010 register_sdr1_sprs(env);
4011 register_7xx_sprs(env);
4012 register_745_sprs(env);
4013 /* Thermal management */
4014 register_thrm_sprs(env);
4015
4016 /* Memory management */
4017 register_low_BATs(env);
4018 register_high_BATs(env);
4019 register_6xx_7xx_soft_tlb(env, 64, 2);
4020 init_excp_7x5(env);
4021 env->dcache_line_size = 32;
4022 env->icache_line_size = 32;
4023 /* Allocate hardware IRQ controller */
4024 ppc6xx_irq_init(env_archcpu(env));
4025 }
4026
4027 POWERPC_FAMILY(745)(ObjectClass *oc, void *data)
4028 {
4029 DeviceClass *dc = DEVICE_CLASS(oc);
4030 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4031
4032 dc->desc = "PowerPC 745";
4033 pcc->init_proc = init_proc_745;
4034 pcc->check_pow = check_pow_hid0;
4035 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4036 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4037 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4038 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4039 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4040 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4041 PPC_SEGMENT | PPC_EXTERN;
4042 pcc->msr_mask = (1ull << MSR_POW) |
4043 (1ull << MSR_ILE) |
4044 (1ull << MSR_EE) |
4045 (1ull << MSR_PR) |
4046 (1ull << MSR_FP) |
4047 (1ull << MSR_ME) |
4048 (1ull << MSR_FE0) |
4049 (1ull << MSR_SE) |
4050 (1ull << MSR_DE) |
4051 (1ull << MSR_FE1) |
4052 (1ull << MSR_EP) |
4053 (1ull << MSR_IR) |
4054 (1ull << MSR_DR) |
4055 (1ull << MSR_PMM) |
4056 (1ull << MSR_RI) |
4057 (1ull << MSR_LE);
4058 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4059 pcc->excp_model = POWERPC_EXCP_7xx;
4060 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4061 pcc->bfd_mach = bfd_mach_ppc_750;
4062 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4063 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4064 }
4065
4066 static void init_proc_755(CPUPPCState *env)
4067 {
4068 init_proc_745(env);
4069 register_755_sprs(env);
4070 }
4071
4072 POWERPC_FAMILY(755)(ObjectClass *oc, void *data)
4073 {
4074 DeviceClass *dc = DEVICE_CLASS(oc);
4075 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4076
4077 dc->desc = "PowerPC 755";
4078 pcc->init_proc = init_proc_755;
4079 pcc->check_pow = check_pow_hid0;
4080 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4081 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4082 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4083 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4084 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4085 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4086 PPC_SEGMENT | PPC_EXTERN;
4087 pcc->msr_mask = (1ull << MSR_POW) |
4088 (1ull << MSR_ILE) |
4089 (1ull << MSR_EE) |
4090 (1ull << MSR_PR) |
4091 (1ull << MSR_FP) |
4092 (1ull << MSR_ME) |
4093 (1ull << MSR_FE0) |
4094 (1ull << MSR_SE) |
4095 (1ull << MSR_DE) |
4096 (1ull << MSR_FE1) |
4097 (1ull << MSR_EP) |
4098 (1ull << MSR_IR) |
4099 (1ull << MSR_DR) |
4100 (1ull << MSR_PMM) |
4101 (1ull << MSR_RI) |
4102 (1ull << MSR_LE);
4103 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4104 pcc->excp_model = POWERPC_EXCP_7xx;
4105 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4106 pcc->bfd_mach = bfd_mach_ppc_750;
4107 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4108 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4109 }
4110
4111 static void init_proc_7400(CPUPPCState *env)
4112 {
4113 register_non_embedded_sprs(env);
4114 register_sdr1_sprs(env);
4115 register_74xx_sprs(env);
4116 vscr_init(env, 0x00010000);
4117
4118 spr_register(env, SPR_UBAMR, "UBAMR",
4119 &spr_read_ureg, SPR_NOACCESS,
4120 &spr_read_ureg, SPR_NOACCESS,
4121 0x00000000);
4122
4123 spr_register(env, SPR_MSSCR1, "MSSCR1",
4124 SPR_NOACCESS, SPR_NOACCESS,
4125 &spr_read_generic, &spr_write_generic,
4126 0x00000000);
4127 /* Thermal management */
4128 register_thrm_sprs(env);
4129 /* Memory management */
4130 register_low_BATs(env);
4131 init_excp_7400(env);
4132 env->dcache_line_size = 32;
4133 env->icache_line_size = 32;
4134 /* Allocate hardware IRQ controller */
4135 ppc6xx_irq_init(env_archcpu(env));
4136 }
4137
4138 POWERPC_FAMILY(7400)(ObjectClass *oc, void *data)
4139 {
4140 DeviceClass *dc = DEVICE_CLASS(oc);
4141 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4142
4143 dc->desc = "PowerPC 7400 (aka G4)";
4144 pcc->init_proc = init_proc_7400;
4145 pcc->check_pow = check_pow_hid0;
4146 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4147 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4148 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4149 PPC_FLOAT_STFIWX |
4150 PPC_CACHE | PPC_CACHE_ICBI |
4151 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
4152 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4153 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4154 PPC_MEM_TLBIA |
4155 PPC_SEGMENT | PPC_EXTERN |
4156 PPC_ALTIVEC;
4157 pcc->msr_mask = (1ull << MSR_VR) |
4158 (1ull << MSR_POW) |
4159 (1ull << MSR_ILE) |
4160 (1ull << MSR_EE) |
4161 (1ull << MSR_PR) |
4162 (1ull << MSR_FP) |
4163 (1ull << MSR_ME) |
4164 (1ull << MSR_FE0) |
4165 (1ull << MSR_SE) |
4166 (1ull << MSR_DE) |
4167 (1ull << MSR_FE1) |
4168 (1ull << MSR_EP) |
4169 (1ull << MSR_IR) |
4170 (1ull << MSR_DR) |
4171 (1ull << MSR_PMM) |
4172 (1ull << MSR_RI) |
4173 (1ull << MSR_LE);
4174 pcc->mmu_model = POWERPC_MMU_32B;
4175 pcc->excp_model = POWERPC_EXCP_74xx;
4176 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4177 pcc->bfd_mach = bfd_mach_ppc_7400;
4178 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
4179 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
4180 POWERPC_FLAG_BUS_CLK;
4181 }
4182
4183 static void init_proc_7410(CPUPPCState *env)
4184 {
4185 register_non_embedded_sprs(env);
4186 register_sdr1_sprs(env);
4187 register_74xx_sprs(env);
4188 vscr_init(env, 0x00010000);
4189
4190 spr_register(env, SPR_UBAMR, "UBAMR",
4191 &spr_read_ureg, SPR_NOACCESS,
4192 &spr_read_ureg, SPR_NOACCESS,
4193 0x00000000);
4194 /* Thermal management */
4195 register_thrm_sprs(env);
4196 /* L2PMCR */
4197
4198 spr_register(env, SPR_L2PMCR, "L2PMCR",
4199 SPR_NOACCESS, SPR_NOACCESS,
4200 &spr_read_generic, &spr_write_generic,
4201 0x00000000);
4202 /* LDSTDB */
4203
4204 spr_register(env, SPR_LDSTDB, "LDSTDB",
4205 SPR_NOACCESS, SPR_NOACCESS,
4206 &spr_read_generic, &spr_write_generic,
4207 0x00000000);
4208 /* Memory management */
4209 register_low_BATs(env);
4210 init_excp_7400(env);
4211 env->dcache_line_size = 32;
4212 env->icache_line_size = 32;
4213 /* Allocate hardware IRQ controller */
4214 ppc6xx_irq_init(env_archcpu(env));
4215 }
4216
4217 POWERPC_FAMILY(7410)(ObjectClass *oc, void *data)
4218 {
4219 DeviceClass *dc = DEVICE_CLASS(oc);
4220 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4221
4222 dc->desc = "PowerPC 7410 (aka G4)";
4223 pcc->init_proc = init_proc_7410;
4224 pcc->check_pow = check_pow_hid0;
4225 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4226 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4227 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4228 PPC_FLOAT_STFIWX |
4229 PPC_CACHE | PPC_CACHE_ICBI |
4230 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
4231 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4232 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4233 PPC_MEM_TLBIA |
4234 PPC_SEGMENT | PPC_EXTERN |
4235 PPC_ALTIVEC;
4236 pcc->msr_mask = (1ull << MSR_VR) |
4237 (1ull << MSR_POW) |
4238 (1ull << MSR_ILE) |
4239 (1ull << MSR_EE) |
4240 (1ull << MSR_PR) |
4241 (1ull << MSR_FP) |
4242 (1ull << MSR_ME) |
4243 (1ull << MSR_FE0) |
4244 (1ull << MSR_SE) |
4245 (1ull << MSR_DE) |
4246 (1ull << MSR_FE1) |
4247 (1ull << MSR_EP) |
4248 (1ull << MSR_IR) |
4249 (1ull << MSR_DR) |
4250 (1ull << MSR_PMM) |
4251 (1ull << MSR_RI) |
4252 (1ull << MSR_LE);
4253 pcc->mmu_model = POWERPC_MMU_32B;
4254 pcc->excp_model = POWERPC_EXCP_74xx;
4255 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4256 pcc->bfd_mach = bfd_mach_ppc_7400;
4257 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
4258 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
4259 POWERPC_FLAG_BUS_CLK;
4260 }
4261
4262 static void init_proc_7440(CPUPPCState *env)
4263 {
4264 register_non_embedded_sprs(env);
4265 register_sdr1_sprs(env);
4266 register_74xx_sprs(env);
4267 vscr_init(env, 0x00010000);
4268
4269 spr_register(env, SPR_UBAMR, "UBAMR",
4270 &spr_read_ureg, SPR_NOACCESS,
4271 &spr_read_ureg, SPR_NOACCESS,
4272 0x00000000);
4273 /* LDSTCR */
4274 spr_register(env, SPR_LDSTCR, "LDSTCR",
4275 SPR_NOACCESS, SPR_NOACCESS,
4276 &spr_read_generic, &spr_write_generic,
4277 0x00000000);
4278 /* ICTRL */
4279 spr_register(env, SPR_ICTRL, "ICTRL",
4280 SPR_NOACCESS, SPR_NOACCESS,
4281 &spr_read_generic, &spr_write_generic,
4282 0x00000000);
4283 /* MSSSR0 */
4284 spr_register(env, SPR_MSSSR0, "MSSSR0",
4285 SPR_NOACCESS, SPR_NOACCESS,
4286 &spr_read_generic, &spr_write_generic,
4287 0x00000000);
4288 /* PMC */
4289 spr_register(env, SPR_7XX_PMC5, "PMC5",
4290 SPR_NOACCESS, SPR_NOACCESS,
4291 &spr_read_generic, &spr_write_generic,
4292 0x00000000);
4293
4294 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
4295 &spr_read_ureg, SPR_NOACCESS,
4296 &spr_read_ureg, SPR_NOACCESS,
4297 0x00000000);
4298
4299 spr_register(env, SPR_7XX_PMC6, "PMC6",
4300 SPR_NOACCESS, SPR_NOACCESS,
4301 &spr_read_generic, &spr_write_generic,
4302 0x00000000);
4303
4304 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
4305 &spr_read_ureg, SPR_NOACCESS,
4306 &spr_read_ureg, SPR_NOACCESS,
4307 0x00000000);
4308 /* Memory management */
4309 register_low_BATs(env);
4310 init_excp_7450(env);
4311 env->dcache_line_size = 32;
4312 env->icache_line_size = 32;
4313 /* Allocate hardware IRQ controller */
4314 ppc6xx_irq_init(env_archcpu(env));
4315 }
4316
4317 POWERPC_FAMILY(7440)(ObjectClass *oc, void *data)
4318 {
4319 DeviceClass *dc = DEVICE_CLASS(oc);
4320 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4321
4322 dc->desc = "PowerPC 7440 (aka G4)";
4323 pcc->init_proc = init_proc_7440;
4324 pcc->check_pow = check_pow_hid0_74xx;
4325 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4326 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4327 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4328 PPC_FLOAT_STFIWX |
4329 PPC_CACHE | PPC_CACHE_ICBI |
4330 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
4331 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4332 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4333 PPC_MEM_TLBIA |
4334 PPC_SEGMENT | PPC_EXTERN |
4335 PPC_ALTIVEC;
4336 pcc->msr_mask = (1ull << MSR_VR) |
4337 (1ull << MSR_POW) |
4338 (1ull << MSR_ILE) |
4339 (1ull << MSR_EE) |
4340 (1ull << MSR_PR) |
4341 (1ull << MSR_FP) |
4342 (1ull << MSR_ME) |
4343 (1ull << MSR_FE0) |
4344 (1ull << MSR_SE) |
4345 (1ull << MSR_DE) |
4346 (1ull << MSR_FE1) |
4347 (1ull << MSR_EP) |
4348 (1ull << MSR_IR) |
4349 (1ull << MSR_DR) |
4350 (1ull << MSR_PMM) |
4351 (1ull << MSR_RI) |
4352 (1ull << MSR_LE);
4353 pcc->mmu_model = POWERPC_MMU_32B;
4354 pcc->excp_model = POWERPC_EXCP_74xx;
4355 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4356 pcc->bfd_mach = bfd_mach_ppc_7400;
4357 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
4358 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
4359 POWERPC_FLAG_BUS_CLK;
4360 }
4361
4362 static void init_proc_7450(CPUPPCState *env)
4363 {
4364 register_non_embedded_sprs(env);
4365 register_sdr1_sprs(env);
4366 register_74xx_sprs(env);
4367 vscr_init(env, 0x00010000);
4368 /* Level 3 cache control */
4369 register_l3_ctrl(env);
4370 /* L3ITCR1 */
4371 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
4372 SPR_NOACCESS, SPR_NOACCESS,
4373 &spr_read_generic, &spr_write_generic,
4374 0x00000000);
4375 /* L3ITCR2 */
4376 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
4377 SPR_NOACCESS, SPR_NOACCESS,
4378 &spr_read_generic, &spr_write_generic,
4379 0x00000000);
4380 /* L3ITCR3 */
4381 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
4382 SPR_NOACCESS, SPR_NOACCESS,
4383 &spr_read_generic, &spr_write_generic,
4384 0x00000000);
4385 /* L3OHCR */
4386 spr_register(env, SPR_L3OHCR, "L3OHCR",
4387 SPR_NOACCESS, SPR_NOACCESS,
4388 &spr_read_generic, &spr_write_generic,
4389 0x00000000);
4390
4391 spr_register(env, SPR_UBAMR, "UBAMR",
4392 &spr_read_ureg, SPR_NOACCESS,
4393 &spr_read_ureg, SPR_NOACCESS,
4394 0x00000000);
4395 /* LDSTCR */
4396 spr_register(env, SPR_LDSTCR, "LDSTCR",
4397 SPR_NOACCESS, SPR_NOACCESS,
4398 &spr_read_generic, &spr_write_generic,
4399 0x00000000);
4400 /* ICTRL */
4401 spr_register(env, SPR_ICTRL, "ICTRL",
4402 SPR_NOACCESS, SPR_NOACCESS,
4403 &spr_read_generic, &spr_write_generic,
4404 0x00000000);
4405 /* MSSSR0 */
4406 spr_register(env, SPR_MSSSR0, "MSSSR0",
4407 SPR_NOACCESS, SPR_NOACCESS,
4408 &spr_read_generic, &spr_write_generic,
4409 0x00000000);
4410 /* PMC */
4411 spr_register(env, SPR_7XX_PMC5, "PMC5",
4412 SPR_NOACCESS, SPR_NOACCESS,
4413 &spr_read_generic, &spr_write_generic,
4414 0x00000000);
4415
4416 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
4417 &spr_read_ureg, SPR_NOACCESS,
4418 &spr_read_ureg, SPR_NOACCESS,
4419 0x00000000);
4420
4421 spr_register(env, SPR_7XX_PMC6, "PMC6",
4422 SPR_NOACCESS, SPR_NOACCESS,
4423 &spr_read_generic, &spr_write_generic,
4424 0x00000000);
4425
4426 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
4427 &spr_read_ureg, SPR_NOACCESS,
4428 &spr_read_ureg, SPR_NOACCESS,
4429 0x00000000);
4430 /* Memory management */
4431 register_low_BATs(env);
4432 init_excp_7450(env);
4433 env->dcache_line_size = 32;
4434 env->icache_line_size = 32;
4435 /* Allocate hardware IRQ controller */
4436 ppc6xx_irq_init(env_archcpu(env));
4437 }
4438
4439 POWERPC_FAMILY(7450)(ObjectClass *oc, void *data)
4440 {
4441 DeviceClass *dc = DEVICE_CLASS(oc);
4442 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4443
4444 dc->desc = "PowerPC 7450 (aka G4)";
4445 pcc->init_proc = init_proc_7450;
4446 pcc->check_pow = check_pow_hid0_74xx;
4447 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4448 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4449 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4450 PPC_FLOAT_STFIWX |
4451 PPC_CACHE | PPC_CACHE_ICBI |
4452 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
4453 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4454 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4455 PPC_MEM_TLBIA |
4456 PPC_SEGMENT | PPC_EXTERN |
4457 PPC_ALTIVEC;
4458 pcc->msr_mask = (1ull << MSR_VR) |
4459 (1ull << MSR_POW) |
4460 (1ull << MSR_ILE) |
4461 (1ull << MSR_EE) |
4462 (1ull << MSR_PR) |
4463 (1ull << MSR_FP) |
4464 (1ull << MSR_ME) |
4465 (1ull << MSR_FE0) |
4466 (1ull << MSR_SE) |
4467 (1ull << MSR_DE) |
4468 (1ull << MSR_FE1) |
4469 (1ull << MSR_EP) |
4470 (1ull << MSR_IR) |
4471 (1ull << MSR_DR) |
4472 (1ull << MSR_PMM) |
4473 (1ull << MSR_RI) |
4474 (1ull << MSR_LE);
4475 pcc->mmu_model = POWERPC_MMU_32B;
4476 pcc->excp_model = POWERPC_EXCP_74xx;
4477 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4478 pcc->bfd_mach = bfd_mach_ppc_7400;
4479 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
4480 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
4481 POWERPC_FLAG_BUS_CLK;
4482 }
4483
4484 static void init_proc_7445(CPUPPCState *env)
4485 {
4486 register_non_embedded_sprs(env);
4487 register_sdr1_sprs(env);
4488 register_74xx_sprs(env);
4489 vscr_init(env, 0x00010000);
4490 /* LDSTCR */
4491 spr_register(env, SPR_LDSTCR, "LDSTCR",
4492 SPR_NOACCESS, SPR_NOACCESS,
4493 &spr_read_generic, &spr_write_generic,
4494 0x00000000);
4495 /* ICTRL */
4496 spr_register(env, SPR_ICTRL, "ICTRL",
4497 SPR_NOACCESS, SPR_NOACCESS,
4498 &spr_read_generic, &spr_write_generic,
4499 0x00000000);
4500 /* MSSSR0 */
4501 spr_register(env, SPR_MSSSR0, "MSSSR0",
4502 SPR_NOACCESS, SPR_NOACCESS,
4503 &spr_read_generic, &spr_write_generic,
4504 0x00000000);
4505 /* PMC */
4506 spr_register(env, SPR_7XX_PMC5, "PMC5",
4507 SPR_NOACCESS, SPR_NOACCESS,
4508 &spr_read_generic, &spr_write_generic,
4509 0x00000000);
4510
4511 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
4512 &spr_read_ureg, SPR_NOACCESS,
4513 &spr_read_ureg, SPR_NOACCESS,
4514 0x00000000);
4515
4516 spr_register(env, SPR_7XX_PMC6, "PMC6",
4517 SPR_NOACCESS, SPR_NOACCESS,
4518 &spr_read_generic, &spr_write_generic,
4519 0x00000000);
4520
4521 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
4522 &spr_read_ureg, SPR_NOACCESS,
4523 &spr_read_ureg, SPR_NOACCESS,
4524 0x00000000);
4525 /* SPRGs */
4526 spr_register(env, SPR_SPRG4, "SPRG4",
4527 SPR_NOACCESS, SPR_NOACCESS,
4528 &spr_read_generic, &spr_write_generic,
4529 0x00000000);
4530 spr_register(env, SPR_USPRG4, "USPRG4",
4531 &spr_read_ureg, SPR_NOACCESS,
4532 &spr_read_ureg, SPR_NOACCESS,
4533 0x00000000);
4534 spr_register(env, SPR_SPRG5, "SPRG5",
4535 SPR_NOACCESS, SPR_NOACCESS,
4536 &spr_read_generic, &spr_write_generic,
4537 0x00000000);
4538 spr_register(env, SPR_USPRG5, "USPRG5",
4539 &spr_read_ureg, SPR_NOACCESS,
4540 &spr_read_ureg, SPR_NOACCESS,
4541 0x00000000);
4542 spr_register(env, SPR_SPRG6, "SPRG6",
4543 SPR_NOACCESS, SPR_NOACCESS,
4544 &spr_read_generic, &spr_write_generic,
4545 0x00000000);
4546 spr_register(env, SPR_USPRG6, "USPRG6",
4547 &spr_read_ureg, SPR_NOACCESS,
4548 &spr_read_ureg, SPR_NOACCESS,
4549 0x00000000);
4550 spr_register(env, SPR_SPRG7, "SPRG7",
4551 SPR_NOACCESS, SPR_NOACCESS,
4552 &spr_read_generic, &spr_write_generic,
4553 0x00000000);
4554 spr_register(env, SPR_USPRG7, "USPRG7",
4555 &spr_read_ureg, SPR_NOACCESS,
4556 &spr_read_ureg, SPR_NOACCESS,
4557 0x00000000);
4558 /* Memory management */
4559 register_low_BATs(env);
4560 register_high_BATs(env);
4561 init_excp_7450(env);
4562 env->dcache_line_size = 32;
4563 env->icache_line_size = 32;
4564 /* Allocate hardware IRQ controller */
4565 ppc6xx_irq_init(env_archcpu(env));
4566 }
4567
4568 POWERPC_FAMILY(7445)(ObjectClass *oc, void *data)
4569 {
4570 DeviceClass *dc = DEVICE_CLASS(oc);
4571 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4572
4573 dc->desc = "PowerPC 7445 (aka G4)";
4574 pcc->init_proc = init_proc_7445;
4575 pcc->check_pow = check_pow_hid0_74xx;
4576 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4577 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4578 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4579 PPC_FLOAT_STFIWX |
4580 PPC_CACHE | PPC_CACHE_ICBI |
4581 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
4582 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4583 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4584 PPC_MEM_TLBIA |
4585 PPC_SEGMENT | PPC_EXTERN |
4586 PPC_ALTIVEC;
4587 pcc->msr_mask = (1ull << MSR_VR) |
4588 (1ull << MSR_POW) |
4589 (1ull << MSR_ILE) |
4590 (1ull << MSR_EE) |
4591 (1ull << MSR_PR) |
4592 (1ull << MSR_FP) |
4593 (1ull << MSR_ME) |
4594 (1ull << MSR_FE0) |
4595 (1ull << MSR_SE) |
4596 (1ull << MSR_DE) |
4597 (1ull << MSR_FE1) |
4598 (1ull << MSR_EP) |
4599 (1ull << MSR_IR) |
4600 (1ull << MSR_DR) |
4601 (1ull << MSR_PMM) |
4602 (1ull << MSR_RI) |
4603 (1ull << MSR_LE);
4604 pcc->mmu_model = POWERPC_MMU_32B;
4605 pcc->excp_model = POWERPC_EXCP_74xx;
4606 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4607 pcc->bfd_mach = bfd_mach_ppc_7400;
4608 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
4609 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
4610 POWERPC_FLAG_BUS_CLK;
4611 }
4612
4613 static void init_proc_7455(CPUPPCState *env)
4614 {
4615 register_non_embedded_sprs(env);
4616 register_sdr1_sprs(env);
4617 register_74xx_sprs(env);
4618 vscr_init(env, 0x00010000);
4619 /* Level 3 cache control */
4620 register_l3_ctrl(env);
4621 /* LDSTCR */
4622 spr_register(env, SPR_LDSTCR, "LDSTCR",
4623 SPR_NOACCESS, SPR_NOACCESS,
4624 &spr_read_generic, &spr_write_generic,
4625 0x00000000);
4626 /* ICTRL */
4627 spr_register(env, SPR_ICTRL, "ICTRL",
4628 SPR_NOACCESS, SPR_NOACCESS,
4629 &spr_read_generic, &spr_write_generic,
4630 0x00000000);
4631 /* MSSSR0 */
4632 spr_register(env, SPR_MSSSR0, "MSSSR0",
4633 SPR_NOACCESS, SPR_NOACCESS,
4634 &spr_read_generic, &spr_write_generic,
4635 0x00000000);
4636 /* PMC */
4637 spr_register(env, SPR_7XX_PMC5, "PMC5",
4638 SPR_NOACCESS, SPR_NOACCESS,
4639 &spr_read_generic, &spr_write_generic,
4640 0x00000000);
4641
4642 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
4643 &spr_read_ureg, SPR_NOACCESS,
4644 &spr_read_ureg, SPR_NOACCESS,
4645 0x00000000);
4646
4647 spr_register(env, SPR_7XX_PMC6, "PMC6",
4648 SPR_NOACCESS, SPR_NOACCESS,
4649 &spr_read_generic, &spr_write_generic,
4650 0x00000000);
4651
4652 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
4653 &spr_read_ureg, SPR_NOACCESS,
4654 &spr_read_ureg, SPR_NOACCESS,
4655 0x00000000);
4656 /* SPRGs */
4657 spr_register(env, SPR_SPRG4, "SPRG4",
4658 SPR_NOACCESS, SPR_NOACCESS,
4659 &spr_read_generic, &spr_write_generic,
4660 0x00000000);
4661 spr_register(env, SPR_USPRG4, "USPRG4",
4662 &spr_read_ureg, SPR_NOACCESS,
4663 &spr_read_ureg, SPR_NOACCESS,
4664 0x00000000);
4665 spr_register(env, SPR_SPRG5, "SPRG5",
4666 SPR_NOACCESS, SPR_NOACCESS,
4667 &spr_read_generic, &spr_write_generic,
4668 0x00000000);
4669 spr_register(env, SPR_USPRG5, "USPRG5",
4670 &spr_read_ureg, SPR_NOACCESS,
4671 &spr_read_ureg, SPR_NOACCESS,
4672 0x00000000);
4673 spr_register(env, SPR_SPRG6, "SPRG6",
4674 SPR_NOACCESS, SPR_NOACCESS,
4675 &spr_read_generic, &spr_write_generic,
4676 0x00000000);
4677 spr_register(env, SPR_USPRG6, "USPRG6",
4678 &spr_read_ureg, SPR_NOACCESS,
4679 &spr_read_ureg, SPR_NOACCESS,
4680 0x00000000);
4681 spr_register(env, SPR_SPRG7, "SPRG7",
4682 SPR_NOACCESS, SPR_NOACCESS,
4683 &spr_read_generic, &spr_write_generic,
4684 0x00000000);
4685 spr_register(env, SPR_USPRG7, "USPRG7",
4686 &spr_read_ureg, SPR_NOACCESS,
4687 &spr_read_ureg, SPR_NOACCESS,
4688 0x00000000);
4689 /* Memory management */
4690 register_low_BATs(env);
4691 register_high_BATs(env);
4692 init_excp_7450(env);
4693 env->dcache_line_size = 32;
4694 env->icache_line_size = 32;
4695 /* Allocate hardware IRQ controller */
4696 ppc6xx_irq_init(env_archcpu(env));
4697 }
4698
4699 POWERPC_FAMILY(7455)(ObjectClass *oc, void *data)
4700 {
4701 DeviceClass *dc = DEVICE_CLASS(oc);
4702 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4703
4704 dc->desc = "PowerPC 7455 (aka G4)";
4705 pcc->init_proc = init_proc_7455;
4706 pcc->check_pow = check_pow_hid0_74xx;
4707 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4708 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4709 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4710 PPC_FLOAT_STFIWX |
4711 PPC_CACHE | PPC_CACHE_ICBI |
4712 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
4713 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4714 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4715 PPC_MEM_TLBIA |
4716 PPC_SEGMENT | PPC_EXTERN |
4717 PPC_ALTIVEC;
4718 pcc->msr_mask = (1ull << MSR_VR) |
4719 (1ull << MSR_POW) |
4720 (1ull << MSR_ILE) |
4721 (1ull << MSR_EE) |
4722 (1ull << MSR_PR) |
4723 (1ull << MSR_FP) |
4724 (1ull << MSR_ME) |
4725 (1ull << MSR_FE0) |
4726 (1ull << MSR_SE) |
4727 (1ull << MSR_DE) |
4728 (1ull << MSR_FE1) |
4729 (1ull << MSR_EP) |
4730 (1ull << MSR_IR) |
4731 (1ull << MSR_DR) |
4732 (1ull << MSR_PMM) |
4733 (1ull << MSR_RI) |
4734 (1ull << MSR_LE);
4735 pcc->mmu_model = POWERPC_MMU_32B;
4736 pcc->excp_model = POWERPC_EXCP_74xx;
4737 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4738 pcc->bfd_mach = bfd_mach_ppc_7400;
4739 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
4740 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
4741 POWERPC_FLAG_BUS_CLK;
4742 }
4743
4744 static void init_proc_7457(CPUPPCState *env)
4745 {
4746 register_non_embedded_sprs(env);
4747 register_sdr1_sprs(env);
4748 register_74xx_sprs(env);
4749 vscr_init(env, 0x00010000);
4750 /* Level 3 cache control */
4751 register_l3_ctrl(env);
4752 /* L3ITCR1 */
4753 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
4754 SPR_NOACCESS, SPR_NOACCESS,
4755 &spr_read_generic, &spr_write_generic,
4756 0x00000000);
4757 /* L3ITCR2 */
4758 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
4759 SPR_NOACCESS, SPR_NOACCESS,
4760 &spr_read_generic, &spr_write_generic,
4761 0x00000000);
4762 /* L3ITCR3 */
4763 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
4764 SPR_NOACCESS, SPR_NOACCESS,
4765 &spr_read_generic, &spr_write_generic,
4766 0x00000000);
4767 /* L3OHCR */
4768 spr_register(env, SPR_L3OHCR, "L3OHCR",
4769 SPR_NOACCESS, SPR_NOACCESS,
4770 &spr_read_generic, &spr_write_generic,
4771 0x00000000);
4772 /* LDSTCR */
4773 spr_register(env, SPR_LDSTCR, "LDSTCR",
4774 SPR_NOACCESS, SPR_NOACCESS,
4775 &spr_read_generic, &spr_write_generic,
4776 0x00000000);
4777 /* ICTRL */
4778 spr_register(env, SPR_ICTRL, "ICTRL",
4779 SPR_NOACCESS, SPR_NOACCESS,
4780 &spr_read_generic, &spr_write_generic,
4781 0x00000000);
4782 /* MSSSR0 */
4783 spr_register(env, SPR_MSSSR0, "MSSSR0",
4784 SPR_NOACCESS, SPR_NOACCESS,
4785 &spr_read_generic, &spr_write_generic,
4786 0x00000000);
4787 /* PMC */
4788 spr_register(env, SPR_7XX_PMC5, "PMC5",
4789 SPR_NOACCESS, SPR_NOACCESS,
4790 &spr_read_generic, &spr_write_generic,
4791 0x00000000);
4792
4793 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
4794 &spr_read_ureg, SPR_NOACCESS,
4795 &spr_read_ureg, SPR_NOACCESS,
4796 0x00000000);
4797
4798 spr_register(env, SPR_7XX_PMC6, "PMC6",
4799 SPR_NOACCESS, SPR_NOACCESS,
4800 &spr_read_generic, &spr_write_generic,
4801 0x00000000);
4802
4803 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
4804 &spr_read_ureg, SPR_NOACCESS,
4805 &spr_read_ureg, SPR_NOACCESS,
4806 0x00000000);
4807 /* SPRGs */
4808 spr_register(env, SPR_SPRG4, "SPRG4",
4809 SPR_NOACCESS, SPR_NOACCESS,
4810 &spr_read_generic, &spr_write_generic,
4811 0x00000000);
4812 spr_register(env, SPR_USPRG4, "USPRG4",
4813 &spr_read_ureg, SPR_NOACCESS,
4814 &spr_read_ureg, SPR_NOACCESS,
4815 0x00000000);
4816 spr_register(env, SPR_SPRG5, "SPRG5",
4817 SPR_NOACCESS, SPR_NOACCESS,
4818 &spr_read_generic, &spr_write_generic,
4819 0x00000000);
4820 spr_register(env, SPR_USPRG5, "USPRG5",
4821 &spr_read_ureg, SPR_NOACCESS,
4822 &spr_read_ureg, SPR_NOACCESS,
4823 0x00000000);
4824 spr_register(env, SPR_SPRG6, "SPRG6",
4825 SPR_NOACCESS, SPR_NOACCESS,
4826 &spr_read_generic, &spr_write_generic,
4827 0x00000000);
4828 spr_register(env, SPR_USPRG6, "USPRG6",
4829 &spr_read_ureg, SPR_NOACCESS,
4830 &spr_read_ureg, SPR_NOACCESS,
4831 0x00000000);
4832 spr_register(env, SPR_SPRG7, "SPRG7",
4833 SPR_NOACCESS, SPR_NOACCESS,
4834 &spr_read_generic, &spr_write_generic,
4835 0x00000000);
4836 spr_register(env, SPR_USPRG7, "USPRG7",
4837 &spr_read_ureg, SPR_NOACCESS,
4838 &spr_read_ureg, SPR_NOACCESS,
4839 0x00000000);
4840 /* Memory management */
4841 register_low_BATs(env);
4842 register_high_BATs(env);
4843 init_excp_7450(env);
4844 env->dcache_line_size = 32;
4845 env->icache_line_size = 32;
4846 /* Allocate hardware IRQ controller */
4847 ppc6xx_irq_init(env_archcpu(env));
4848 }
4849
4850 POWERPC_FAMILY(7457)(ObjectClass *oc, void *data)
4851 {
4852 DeviceClass *dc = DEVICE_CLASS(oc);
4853 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4854
4855 dc->desc = "PowerPC 7457 (aka G4)";
4856 pcc->init_proc = init_proc_7457;
4857 pcc->check_pow = check_pow_hid0_74xx;
4858 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4859 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4860 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4861 PPC_FLOAT_STFIWX |
4862 PPC_CACHE | PPC_CACHE_ICBI |
4863 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
4864 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4865 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4866 PPC_MEM_TLBIA |
4867 PPC_SEGMENT | PPC_EXTERN |
4868 PPC_ALTIVEC;
4869 pcc->msr_mask = (1ull << MSR_VR) |
4870 (1ull << MSR_POW) |
4871 (1ull << MSR_ILE) |
4872 (1ull << MSR_EE) |
4873 (1ull << MSR_PR) |
4874 (1ull << MSR_FP) |
4875 (1ull << MSR_ME) |
4876 (1ull << MSR_FE0) |
4877 (1ull << MSR_SE) |
4878 (1ull << MSR_DE) |
4879 (1ull << MSR_FE1) |
4880 (1ull << MSR_EP) |
4881 (1ull << MSR_IR) |
4882 (1ull << MSR_DR) |
4883 (1ull << MSR_PMM) |
4884 (1ull << MSR_RI) |
4885 (1ull << MSR_LE);
4886 pcc->mmu_model = POWERPC_MMU_32B;
4887 pcc->excp_model = POWERPC_EXCP_74xx;
4888 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4889 pcc->bfd_mach = bfd_mach_ppc_7400;
4890 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
4891 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
4892 POWERPC_FLAG_BUS_CLK;
4893 }
4894
4895 static void init_proc_e600(CPUPPCState *env)
4896 {
4897 register_non_embedded_sprs(env);
4898 register_sdr1_sprs(env);
4899 register_74xx_sprs(env);
4900 vscr_init(env, 0x00010000);
4901
4902 spr_register(env, SPR_UBAMR, "UBAMR",
4903 &spr_read_ureg, SPR_NOACCESS,
4904 &spr_read_ureg, SPR_NOACCESS,
4905 0x00000000);
4906
4907 spr_register(env, SPR_LDSTCR, "LDSTCR",
4908 SPR_NOACCESS, SPR_NOACCESS,
4909 &spr_read_generic, &spr_write_generic,
4910 0x00000000);
4911
4912 spr_register(env, SPR_ICTRL, "ICTRL",
4913 SPR_NOACCESS, SPR_NOACCESS,
4914 &spr_read_generic, &spr_write_generic,
4915 0x00000000);
4916
4917 spr_register(env, SPR_MSSSR0, "MSSSR0",
4918 SPR_NOACCESS, SPR_NOACCESS,
4919 &spr_read_generic, &spr_write_generic,
4920 0x00000000);
4921
4922 spr_register(env, SPR_7XX_PMC5, "PMC5",
4923 SPR_NOACCESS, SPR_NOACCESS,
4924 &spr_read_generic, &spr_write_generic,
4925 0x00000000);
4926
4927 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
4928 &spr_read_ureg, SPR_NOACCESS,
4929 &spr_read_ureg, SPR_NOACCESS,
4930 0x00000000);
4931
4932 spr_register(env, SPR_7XX_PMC6, "PMC6",
4933 SPR_NOACCESS, SPR_NOACCESS,
4934 &spr_read_generic, &spr_write_generic,
4935 0x00000000);
4936
4937 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
4938 &spr_read_ureg, SPR_NOACCESS,
4939 &spr_read_ureg, SPR_NOACCESS,
4940 0x00000000);
4941 /* SPRGs */
4942 spr_register(env, SPR_SPRG4, "SPRG4",
4943 SPR_NOACCESS, SPR_NOACCESS,
4944 &spr_read_generic, &spr_write_generic,
4945 0x00000000);
4946 spr_register(env, SPR_USPRG4, "USPRG4",
4947 &spr_read_ureg, SPR_NOACCESS,
4948 &spr_read_ureg, SPR_NOACCESS,
4949 0x00000000);
4950 spr_register(env, SPR_SPRG5, "SPRG5",
4951 SPR_NOACCESS, SPR_NOACCESS,
4952 &spr_read_generic, &spr_write_generic,
4953 0x00000000);
4954 spr_register(env, SPR_USPRG5, "USPRG5",
4955 &spr_read_ureg, SPR_NOACCESS,
4956 &spr_read_ureg, SPR_NOACCESS,
4957 0x00000000);
4958 spr_register(env, SPR_SPRG6, "SPRG6",
4959 SPR_NOACCESS, SPR_NOACCESS,
4960 &spr_read_generic, &spr_write_generic,
4961 0x00000000);
4962 spr_register(env, SPR_USPRG6, "USPRG6",
4963 &spr_read_ureg, SPR_NOACCESS,
4964 &spr_read_ureg, SPR_NOACCESS,
4965 0x00000000);
4966 spr_register(env, SPR_SPRG7, "SPRG7",
4967 SPR_NOACCESS, SPR_NOACCESS,
4968 &spr_read_generic, &spr_write_generic,
4969 0x00000000);
4970 spr_register(env, SPR_USPRG7, "USPRG7",
4971 &spr_read_ureg, SPR_NOACCESS,
4972 &spr_read_ureg, SPR_NOACCESS,
4973 0x00000000);
4974 /* Memory management */
4975 register_low_BATs(env);
4976 register_high_BATs(env);
4977 init_excp_7450(env);
4978 env->dcache_line_size = 32;
4979 env->icache_line_size = 32;
4980 /* Allocate hardware IRQ controller */
4981 ppc6xx_irq_init(env_archcpu(env));
4982 }
4983
4984 POWERPC_FAMILY(e600)(ObjectClass *oc, void *data)
4985 {
4986 DeviceClass *dc = DEVICE_CLASS(oc);
4987 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4988
4989 dc->desc = "PowerPC e600";
4990 pcc->init_proc = init_proc_e600;
4991 pcc->check_pow = check_pow_hid0_74xx;
4992 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4993 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4994 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4995 PPC_FLOAT_STFIWX |
4996 PPC_CACHE | PPC_CACHE_ICBI |
4997 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
4998 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4999 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5000 PPC_MEM_TLBIA |
5001 PPC_SEGMENT | PPC_EXTERN |
5002 PPC_ALTIVEC;
5003 pcc->insns_flags2 = PPC_NONE;
5004 pcc->msr_mask = (1ull << MSR_VR) |
5005 (1ull << MSR_POW) |
5006 (1ull << MSR_ILE) |
5007 (1ull << MSR_EE) |
5008 (1ull << MSR_PR) |
5009 (1ull << MSR_FP) |
5010 (1ull << MSR_ME) |
5011 (1ull << MSR_FE0) |
5012 (1ull << MSR_SE) |
5013 (1ull << MSR_DE) |
5014 (1ull << MSR_FE1) |
5015 (1ull << MSR_EP) |
5016 (1ull << MSR_IR) |
5017 (1ull << MSR_DR) |
5018 (1ull << MSR_PMM) |
5019 (1ull << MSR_RI) |
5020 (1ull << MSR_LE);
5021 pcc->mmu_model = POWERPC_MMU_32B;
5022 pcc->excp_model = POWERPC_EXCP_74xx;
5023 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5024 pcc->bfd_mach = bfd_mach_ppc_7400;
5025 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
5026 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
5027 POWERPC_FLAG_BUS_CLK;
5028 }
5029
5030 #if defined(TARGET_PPC64)
5031 #if defined(CONFIG_USER_ONLY)
5032 #define POWERPC970_HID5_INIT 0x00000080
5033 #else
5034 #define POWERPC970_HID5_INIT 0x00000000
5035 #endif
5036
5037 static int check_pow_970(CPUPPCState *env)
5038 {
5039 if (env->spr[SPR_HID0] & (HID0_DEEPNAP | HID0_DOZE | HID0_NAP)) {
5040 return 1;
5041 }
5042
5043 return 0;
5044 }
5045
5046 static void register_970_hid_sprs(CPUPPCState *env)
5047 {
5048 /* Hardware implementation registers */
5049 spr_register(env, SPR_HID0, "HID0",
5050 SPR_NOACCESS, SPR_NOACCESS,
5051 &spr_read_generic, &spr_write_clear,
5052 0x60000000);
5053 spr_register(env, SPR_HID1, "HID1",
5054 SPR_NOACCESS, SPR_NOACCESS,
5055 &spr_read_generic, &spr_write_generic,
5056 0x00000000);
5057 spr_register(env, SPR_970_HID5, "HID5",
5058 SPR_NOACCESS, SPR_NOACCESS,
5059 &spr_read_generic, &spr_write_generic,
5060 POWERPC970_HID5_INIT);
5061 }
5062
5063 static void register_970_hior_sprs(CPUPPCState *env)
5064 {
5065 spr_register(env, SPR_HIOR, "HIOR",
5066 SPR_NOACCESS, SPR_NOACCESS,
5067 &spr_read_hior, &spr_write_hior,
5068 0x00000000);
5069 }
5070
5071 static void register_book3s_ctrl_sprs(CPUPPCState *env)
5072 {
5073 spr_register(env, SPR_CTRL, "CTRL",
5074 SPR_NOACCESS, SPR_NOACCESS,
5075 SPR_NOACCESS, &spr_write_CTRL,
5076 0x00000000);
5077 spr_register(env, SPR_UCTRL, "UCTRL",
5078 &spr_read_ureg, SPR_NOACCESS,
5079 &spr_read_ureg, SPR_NOACCESS,
5080 0x00000000);
5081 }
5082
5083 static void register_book3s_altivec_sprs(CPUPPCState *env)
5084 {
5085 if (!(env->insns_flags & PPC_ALTIVEC)) {
5086 return;
5087 }
5088
5089 spr_register_kvm(env, SPR_VRSAVE, "VRSAVE",
5090 &spr_read_generic, &spr_write_generic32,
5091 &spr_read_generic, &spr_write_generic32,
5092 KVM_REG_PPC_VRSAVE, 0x00000000);
5093
5094 }
5095
5096 static void register_book3s_dbg_sprs(CPUPPCState *env)
5097 {
5098 /*
5099 * TODO: different specs define different scopes for these,
5100 * will have to address this:
5101 * 970: super/write and super/read
5102 * powerisa 2.03..2.04: hypv/write and super/read.
5103 * powerisa 2.05 and newer: hypv/write and hypv/read.
5104 */
5105 spr_register_kvm(env, SPR_DABR, "DABR",
5106 SPR_NOACCESS, SPR_NOACCESS,
5107 &spr_read_generic, &spr_write_generic,
5108 KVM_REG_PPC_DABR, 0x00000000);
5109 spr_register_kvm(env, SPR_DABRX, "DABRX",
5110 SPR_NOACCESS, SPR_NOACCESS,
5111 &spr_read_generic, &spr_write_generic,
5112 KVM_REG_PPC_DABRX, 0x00000000);
5113 }
5114
5115 static void register_book3s_207_dbg_sprs(CPUPPCState *env)
5116 {
5117 spr_register_kvm_hv(env, SPR_DAWR0, "DAWR0",
5118 SPR_NOACCESS, SPR_NOACCESS,
5119 SPR_NOACCESS, SPR_NOACCESS,
5120 &spr_read_generic, &spr_write_dawr0,
5121 KVM_REG_PPC_DAWR, 0x00000000);
5122 spr_register_kvm_hv(env, SPR_DAWRX0, "DAWRX0",
5123 SPR_NOACCESS, SPR_NOACCESS,
5124 SPR_NOACCESS, SPR_NOACCESS,
5125 &spr_read_generic, &spr_write_dawrx0,
5126 KVM_REG_PPC_DAWRX, 0x00000000);
5127 spr_register_kvm_hv(env, SPR_CIABR, "CIABR",
5128 SPR_NOACCESS, SPR_NOACCESS,
5129 SPR_NOACCESS, SPR_NOACCESS,
5130 &spr_read_generic, &spr_write_ciabr,
5131 KVM_REG_PPC_CIABR, 0x00000000);
5132 }
5133
5134 static void register_970_dbg_sprs(CPUPPCState *env)
5135 {
5136 /* Breakpoints */
5137 spr_register(env, SPR_IABR, "IABR",
5138 SPR_NOACCESS, SPR_NOACCESS,
5139 &spr_read_generic, &spr_write_generic,
5140 0x00000000);
5141 }
5142
5143 static void register_book3s_pmu_sup_sprs(CPUPPCState *env)
5144 {
5145 spr_register_kvm(env, SPR_POWER_MMCR0, "MMCR0",
5146 SPR_NOACCESS, SPR_NOACCESS,
5147 &spr_read_generic, &spr_write_MMCR0,
5148 KVM_REG_PPC_MMCR0, 0x80000000);
5149 spr_register_kvm(env, SPR_POWER_MMCR1, "MMCR1",
5150 SPR_NOACCESS, SPR_NOACCESS,
5151 &spr_read_generic, &spr_write_MMCR1,
5152 KVM_REG_PPC_MMCR1, 0x00000000);
5153 spr_register_kvm(env, SPR_POWER_MMCRA, "MMCRA",
5154 SPR_NOACCESS, SPR_NOACCESS,
5155 &spr_read_generic, &spr_write_generic,
5156 KVM_REG_PPC_MMCRA, 0x00000000);
5157 spr_register_kvm(env, SPR_POWER_PMC1, "PMC1",
5158 SPR_NOACCESS, SPR_NOACCESS,
5159 &spr_read_PMC, &spr_write_PMC,
5160 KVM_REG_PPC_PMC1, 0x00000000);
5161 spr_register_kvm(env, SPR_POWER_PMC2, "PMC2",
5162 SPR_NOACCESS, SPR_NOACCESS,
5163 &spr_read_PMC, &spr_write_PMC,
5164 KVM_REG_PPC_PMC2, 0x00000000);
5165 spr_register_kvm(env, SPR_POWER_PMC3, "PMC3",
5166 SPR_NOACCESS, SPR_NOACCESS,
5167 &spr_read_PMC, &spr_write_PMC,
5168 KVM_REG_PPC_PMC3, 0x00000000);
5169 spr_register_kvm(env, SPR_POWER_PMC4, "PMC4",
5170 SPR_NOACCESS, SPR_NOACCESS,
5171 &spr_read_PMC, &spr_write_PMC,
5172 KVM_REG_PPC_PMC4, 0x00000000);
5173 spr_register_kvm(env, SPR_POWER_PMC5, "PMC5",
5174 SPR_NOACCESS, SPR_NOACCESS,
5175 &spr_read_PMC, &spr_write_PMC,
5176 KVM_REG_PPC_PMC5, 0x00000000);
5177 spr_register_kvm(env, SPR_POWER_PMC6, "PMC6",
5178 SPR_NOACCESS, SPR_NOACCESS,
5179 &spr_read_PMC, &spr_write_PMC,
5180 KVM_REG_PPC_PMC6, 0x00000000);
5181 spr_register_kvm(env, SPR_POWER_SIAR, "SIAR",
5182 SPR_NOACCESS, SPR_NOACCESS,
5183 &spr_read_generic, &spr_write_generic,
5184 KVM_REG_PPC_SIAR, 0x00000000);
5185 spr_register_kvm(env, SPR_POWER_SDAR, "SDAR",
5186 SPR_NOACCESS, SPR_NOACCESS,
5187 &spr_read_generic, &spr_write_generic,
5188 KVM_REG_PPC_SDAR, 0x00000000);
5189 }
5190
5191 static void register_book3s_pmu_user_sprs(CPUPPCState *env)
5192 {
5193 spr_register(env, SPR_POWER_UMMCR0, "UMMCR0",
5194 &spr_read_MMCR0_ureg, &spr_write_MMCR0_ureg,
5195 &spr_read_ureg, &spr_write_ureg,
5196 0x80000000);
5197 spr_register(env, SPR_POWER_UMMCR1, "UMMCR1",
5198 &spr_read_ureg, SPR_NOACCESS,
5199 &spr_read_ureg, &spr_write_ureg,
5200 0x00000000);
5201 spr_register(env, SPR_POWER_UMMCRA, "UMMCRA",
5202 &spr_read_ureg, SPR_NOACCESS,
5203 &spr_read_ureg, &spr_write_ureg,
5204 0x00000000);
5205 spr_register(env, SPR_POWER_UPMC1, "UPMC1",
5206 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg,
5207 &spr_read_ureg, &spr_write_ureg,
5208 0x00000000);
5209 spr_register(env, SPR_POWER_UPMC2, "UPMC2",
5210 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg,
5211 &spr_read_ureg, &spr_write_ureg,
5212 0x00000000);
5213 spr_register(env, SPR_POWER_UPMC3, "UPMC3",
5214 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg,
5215 &spr_read_ureg, &spr_write_ureg,
5216 0x00000000);
5217 spr_register(env, SPR_POWER_UPMC4, "UPMC4",
5218 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg,
5219 &spr_read_ureg, &spr_write_ureg,
5220 0x00000000);
5221 spr_register(env, SPR_POWER_UPMC5, "UPMC5",
5222 &spr_read_PMC56_ureg, &spr_write_PMC56_ureg,
5223 &spr_read_ureg, &spr_write_ureg,
5224 0x00000000);
5225 spr_register(env, SPR_POWER_UPMC6, "UPMC6",
5226 &spr_read_PMC56_ureg, &spr_write_PMC56_ureg,
5227 &spr_read_ureg, &spr_write_ureg,
5228 0x00000000);
5229 spr_register(env, SPR_POWER_USIAR, "USIAR",
5230 &spr_read_ureg, SPR_NOACCESS,
5231 &spr_read_ureg, &spr_write_ureg,
5232 0x00000000);
5233 spr_register(env, SPR_POWER_USDAR, "USDAR",
5234 &spr_read_ureg, SPR_NOACCESS,
5235 &spr_read_ureg, &spr_write_ureg,
5236 0x00000000);
5237 }
5238
5239 static void register_970_pmu_sup_sprs(CPUPPCState *env)
5240 {
5241 spr_register_kvm(env, SPR_970_PMC7, "PMC7",
5242 SPR_NOACCESS, SPR_NOACCESS,
5243 &spr_read_generic, &spr_write_generic,
5244 KVM_REG_PPC_PMC7, 0x00000000);
5245 spr_register_kvm(env, SPR_970_PMC8, "PMC8",
5246 SPR_NOACCESS, SPR_NOACCESS,
5247 &spr_read_generic, &spr_write_generic,
5248 KVM_REG_PPC_PMC8, 0x00000000);
5249 }
5250
5251 static void register_970_pmu_user_sprs(CPUPPCState *env)
5252 {
5253 spr_register(env, SPR_970_UPMC7, "UPMC7",
5254 &spr_read_ureg, SPR_NOACCESS,
5255 &spr_read_ureg, &spr_write_ureg,
5256 0x00000000);
5257 spr_register(env, SPR_970_UPMC8, "UPMC8",
5258 &spr_read_ureg, SPR_NOACCESS,
5259 &spr_read_ureg, &spr_write_ureg,
5260 0x00000000);
5261 }
5262
5263 static void register_power8_pmu_sup_sprs(CPUPPCState *env)
5264 {
5265 spr_register_kvm(env, SPR_POWER_MMCR2, "MMCR2",
5266 SPR_NOACCESS, SPR_NOACCESS,
5267 &spr_read_generic, &spr_write_generic,
5268 KVM_REG_PPC_MMCR2, 0x00000000);
5269 spr_register_kvm(env, SPR_POWER_MMCRS, "MMCRS",
5270 SPR_NOACCESS, SPR_NOACCESS,
5271 &spr_read_generic, &spr_write_generic,
5272 KVM_REG_PPC_MMCRS, 0x00000000);
5273 spr_register_kvm(env, SPR_POWER_SIER, "SIER",
5274 SPR_NOACCESS, SPR_NOACCESS,
5275 &spr_read_generic, &spr_write_generic,
5276 KVM_REG_PPC_SIER, 0x00000000);
5277 spr_register_kvm(env, SPR_POWER_SPMC1, "SPMC1",
5278 SPR_NOACCESS, SPR_NOACCESS,
5279 &spr_read_generic, &spr_write_generic,
5280 KVM_REG_PPC_SPMC1, 0x00000000);
5281 spr_register_kvm(env, SPR_POWER_SPMC2, "SPMC2",
5282 SPR_NOACCESS, SPR_NOACCESS,
5283 &spr_read_generic, &spr_write_generic,
5284 KVM_REG_PPC_SPMC2, 0x00000000);
5285 spr_register_kvm(env, SPR_TACR, "TACR",
5286 SPR_NOACCESS, SPR_NOACCESS,
5287 &spr_read_generic, &spr_write_generic,
5288 KVM_REG_PPC_TACR, 0x00000000);
5289 spr_register_kvm(env, SPR_TCSCR, "TCSCR",
5290 SPR_NOACCESS, SPR_NOACCESS,
5291 &spr_read_generic, &spr_write_generic,
5292 KVM_REG_PPC_TCSCR, 0x00000000);
5293 spr_register_kvm(env, SPR_CSIGR, "CSIGR",
5294 SPR_NOACCESS, SPR_NOACCESS,
5295 &spr_read_generic, &spr_write_generic,
5296 KVM_REG_PPC_CSIGR, 0x00000000);
5297 }
5298
5299 static void register_power8_pmu_user_sprs(CPUPPCState *env)
5300 {
5301 spr_register(env, SPR_POWER_UMMCR2, "UMMCR2",
5302 &spr_read_MMCR2_ureg, &spr_write_MMCR2_ureg,
5303 &spr_read_ureg, &spr_write_ureg,
5304 0x00000000);
5305 spr_register(env, SPR_POWER_USIER, "USIER",
5306 &spr_read_generic, SPR_NOACCESS,
5307 &spr_read_generic, &spr_write_generic,
5308 0x00000000);
5309 }
5310
5311 static void register_power10_pmu_sup_sprs(CPUPPCState *env)
5312 {
5313 spr_register_kvm(env, SPR_POWER_MMCR3, "MMCR3",
5314 SPR_NOACCESS, SPR_NOACCESS,
5315 &spr_read_generic, &spr_write_generic,
5316 KVM_REG_PPC_MMCR3, 0x00000000);
5317 spr_register_kvm(env, SPR_POWER_SIER2, "SIER2",
5318 SPR_NOACCESS, SPR_NOACCESS,
5319 &spr_read_generic, &spr_write_generic,
5320 KVM_REG_PPC_SIER2, 0x00000000);
5321 spr_register_kvm(env, SPR_POWER_SIER3, "SIER3",
5322 SPR_NOACCESS, SPR_NOACCESS,
5323 &spr_read_generic, &spr_write_generic,
5324 KVM_REG_PPC_SIER3, 0x00000000);
5325 }
5326
5327 static void register_power10_pmu_user_sprs(CPUPPCState *env)
5328 {
5329 spr_register(env, SPR_POWER_UMMCR3, "UMMCR3",
5330 &spr_read_generic, &spr_write_generic,
5331 &spr_read_generic, &spr_write_generic,
5332 0x00000000);
5333 spr_register(env, SPR_POWER_USIER2, "USIER2",
5334 &spr_read_generic, SPR_NOACCESS,
5335 &spr_read_generic, &spr_write_generic,
5336 0x00000000);
5337 spr_register(env, SPR_POWER_USIER3, "USIER3",
5338 &spr_read_generic, SPR_NOACCESS,
5339 &spr_read_generic, &spr_write_generic,
5340 0x00000000);
5341 }
5342
5343 static void register_power5p_ear_sprs(CPUPPCState *env)
5344 {
5345 /* External access control */
5346 spr_register(env, SPR_EAR, "EAR",
5347 SPR_NOACCESS, SPR_NOACCESS,
5348 &spr_read_generic, &spr_write_generic,
5349 0x00000000);
5350 }
5351
5352 static void register_power5p_tb_sprs(CPUPPCState *env)
5353 {
5354 /* TBU40 (High 40 bits of the Timebase register */
5355 spr_register_hv(env, SPR_TBU40, "TBU40",
5356 SPR_NOACCESS, SPR_NOACCESS,
5357 SPR_NOACCESS, SPR_NOACCESS,
5358 SPR_NOACCESS, &spr_write_tbu40,
5359 0x00000000);
5360 }
5361
5362 static void register_970_lpar_sprs(CPUPPCState *env)
5363 {
5364 #if !defined(CONFIG_USER_ONLY)
5365 /*
5366 * PPC970: HID4 covers things later controlled by the LPCR and
5367 * RMOR in later CPUs, but with a different encoding. We only
5368 * support the 970 in "Apple mode" which has all hypervisor
5369 * facilities disabled by strapping, so we can basically just
5370 * ignore it
5371 */
5372 spr_register(env, SPR_970_HID4, "HID4",
5373 SPR_NOACCESS, SPR_NOACCESS,
5374 &spr_read_generic, &spr_write_generic,
5375 0x00000000);
5376 #endif
5377 }
5378
5379 static void register_power5p_lpar_sprs(CPUPPCState *env)
5380 {
5381 #if !defined(CONFIG_USER_ONLY)
5382 /* Logical partitioning */
5383 spr_register_kvm_hv(env, SPR_LPCR, "LPCR",
5384 SPR_NOACCESS, SPR_NOACCESS,
5385 SPR_NOACCESS, SPR_NOACCESS,
5386 &spr_read_generic, &spr_write_lpcr,
5387 KVM_REG_PPC_LPCR, LPCR_LPES0 | LPCR_LPES1);
5388 spr_register_hv(env, SPR_HDEC, "HDEC",
5389 SPR_NOACCESS, SPR_NOACCESS,
5390 SPR_NOACCESS, SPR_NOACCESS,
5391 &spr_read_hdecr, &spr_write_hdecr, 0);
5392 #endif
5393 }
5394
5395 static void register_book3s_ids_sprs(CPUPPCState *env)
5396 {
5397 /* FIXME: Will need to deal with thread vs core only SPRs */
5398
5399 /* Processor identification */
5400 spr_register_hv(env, SPR_PIR, "PIR",
5401 SPR_NOACCESS, SPR_NOACCESS,
5402 &spr_read_generic, SPR_NOACCESS,
5403 &spr_read_generic, NULL,
5404 0x00000000);
5405 spr_register_hv(env, SPR_LPIDR, "LPIDR",
5406 SPR_NOACCESS, SPR_NOACCESS,
5407 SPR_NOACCESS, SPR_NOACCESS,
5408 &spr_read_generic, &spr_write_lpidr,
5409 0x00000000);
5410 spr_register_hv(env, SPR_HFSCR, "HFSCR",
5411 SPR_NOACCESS, SPR_NOACCESS,
5412 SPR_NOACCESS, SPR_NOACCESS,
5413 &spr_read_generic, &spr_write_generic,
5414 0x00000000);
5415 spr_register_hv(env, SPR_MMCRC, "MMCRC",
5416 SPR_NOACCESS, SPR_NOACCESS,
5417 SPR_NOACCESS, SPR_NOACCESS,
5418 &spr_read_generic, &spr_write_generic32,
5419 0x00000000);
5420 spr_register_hv(env, SPR_MMCRH, "MMCRH",
5421 SPR_NOACCESS, SPR_NOACCESS,
5422 SPR_NOACCESS, SPR_NOACCESS,
5423 &spr_read_generic, &spr_write_generic,
5424 0x00000000);
5425 spr_register_hv(env, SPR_HSPRG0, "HSPRG0",
5426 SPR_NOACCESS, SPR_NOACCESS,
5427 SPR_NOACCESS, SPR_NOACCESS,
5428 &spr_read_generic, &spr_write_generic,
5429 0x00000000);
5430 spr_register_hv(env, SPR_HSPRG1, "HSPRG1",
5431 SPR_NOACCESS, SPR_NOACCESS,
5432 SPR_NOACCESS, SPR_NOACCESS,
5433 &spr_read_generic, &spr_write_generic,
5434 0x00000000);
5435 spr_register_hv(env, SPR_HSRR0, "HSRR0",
5436 SPR_NOACCESS, SPR_NOACCESS,
5437 SPR_NOACCESS, SPR_NOACCESS,
5438 &spr_read_generic, &spr_write_generic,
5439 0x00000000);
5440 spr_register_hv(env, SPR_HSRR1, "HSRR1",
5441 SPR_NOACCESS, SPR_NOACCESS,
5442 SPR_NOACCESS, SPR_NOACCESS,
5443 &spr_read_generic, &spr_write_generic,
5444 0x00000000);
5445 spr_register_hv(env, SPR_HDAR, "HDAR",
5446 SPR_NOACCESS, SPR_NOACCESS,
5447 SPR_NOACCESS, SPR_NOACCESS,
5448 &spr_read_generic, &spr_write_generic,
5449 0x00000000);
5450 spr_register_hv(env, SPR_HDSISR, "HDSISR",
5451 SPR_NOACCESS, SPR_NOACCESS,
5452 SPR_NOACCESS, SPR_NOACCESS,
5453 &spr_read_generic, &spr_write_generic32,
5454 0x00000000);
5455 spr_register_hv(env, SPR_HRMOR, "HRMOR",
5456 SPR_NOACCESS, SPR_NOACCESS,
5457 SPR_NOACCESS, SPR_NOACCESS,
5458 &spr_read_generic, &spr_write_generic,
5459 0x00000000);
5460 }
5461
5462 static void register_rmor_sprs(CPUPPCState *env)
5463 {
5464 spr_register_hv(env, SPR_RMOR, "RMOR",
5465 SPR_NOACCESS, SPR_NOACCESS,
5466 SPR_NOACCESS, SPR_NOACCESS,
5467 &spr_read_generic, &spr_write_generic,
5468 0x00000000);
5469 }
5470
5471 static void register_power8_ids_sprs(CPUPPCState *env)
5472 {
5473 /* Thread identification */
5474 spr_register(env, SPR_TIR, "TIR",
5475 SPR_NOACCESS, SPR_NOACCESS,
5476 &spr_read_generic, SPR_NOACCESS,
5477 0x00000000);
5478 }
5479
5480 static void register_book3s_purr_sprs(CPUPPCState *env)
5481 {
5482 #if !defined(CONFIG_USER_ONLY)
5483 /* PURR & SPURR: Hack - treat these as aliases for the TB for now */
5484 spr_register_kvm_hv(env, SPR_PURR, "PURR",
5485 &spr_read_purr, SPR_NOACCESS,
5486 &spr_read_purr, SPR_NOACCESS,
5487 &spr_read_purr, &spr_write_purr,
5488 KVM_REG_PPC_PURR, 0x00000000);
5489 spr_register_kvm_hv(env, SPR_SPURR, "SPURR",
5490 &spr_read_purr, SPR_NOACCESS,
5491 &spr_read_purr, SPR_NOACCESS,
5492 &spr_read_purr, &spr_write_purr,
5493 KVM_REG_PPC_SPURR, 0x00000000);
5494 #endif
5495 }
5496
5497 static void register_power6_dbg_sprs(CPUPPCState *env)
5498 {
5499 #if !defined(CONFIG_USER_ONLY)
5500 spr_register(env, SPR_CFAR, "CFAR",
5501 SPR_NOACCESS, SPR_NOACCESS,
5502 &spr_read_cfar, &spr_write_cfar,
5503 0x00000000);
5504 #endif
5505 }
5506
5507 static void register_power5p_common_sprs(CPUPPCState *env)
5508 {
5509 spr_register_kvm(env, SPR_PPR, "PPR",
5510 &spr_read_generic, &spr_write_generic,
5511 &spr_read_generic, &spr_write_generic,
5512 KVM_REG_PPC_PPR, 0x00000000);
5513 }
5514
5515 static void register_power6_common_sprs(CPUPPCState *env)
5516 {
5517 #if !defined(CONFIG_USER_ONLY)
5518 spr_register_kvm(env, SPR_DSCR, "DSCR",
5519 SPR_NOACCESS, SPR_NOACCESS,
5520 &spr_read_generic, &spr_write_generic,
5521 KVM_REG_PPC_DSCR, 0x00000000);
5522 #endif
5523 /*
5524 * Register PCR to report POWERPC_EXCP_PRIV_REG instead of
5525 * POWERPC_EXCP_INVAL_SPR in userspace. Permit hypervisor access.
5526 */
5527 spr_register_hv(env, SPR_PCR, "PCR",
5528 SPR_NOACCESS, SPR_NOACCESS,
5529 SPR_NOACCESS, SPR_NOACCESS,
5530 &spr_read_generic, &spr_write_pcr,
5531 0x00000000);
5532 }
5533
5534 static void register_HEIR32_spr(CPUPPCState *env)
5535 {
5536 spr_register_hv(env, SPR_HEIR, "HEIR",
5537 SPR_NOACCESS, SPR_NOACCESS,
5538 SPR_NOACCESS, SPR_NOACCESS,
5539 &spr_read_generic, &spr_write_generic32,
5540 0x00000000);
5541 }
5542
5543 static void register_HEIR64_spr(CPUPPCState *env)
5544 {
5545 spr_register_hv(env, SPR_HEIR, "HEIR",
5546 SPR_NOACCESS, SPR_NOACCESS,
5547 SPR_NOACCESS, SPR_NOACCESS,
5548 &spr_read_generic, &spr_write_generic,
5549 0x00000000);
5550 }
5551
5552 static void register_power8_tce_address_control_sprs(CPUPPCState *env)
5553 {
5554 spr_register_kvm(env, SPR_TAR, "TAR",
5555 &spr_read_tar, &spr_write_tar,
5556 &spr_read_generic, &spr_write_generic,
5557 KVM_REG_PPC_TAR, 0x00000000);
5558 }
5559
5560 static void register_power8_tm_sprs(CPUPPCState *env)
5561 {
5562 spr_register_kvm(env, SPR_TFHAR, "TFHAR",
5563 &spr_read_tm, &spr_write_tm,
5564 &spr_read_tm, &spr_write_tm,
5565 KVM_REG_PPC_TFHAR, 0x00000000);
5566 spr_register_kvm(env, SPR_TFIAR, "TFIAR",
5567 &spr_read_tm, &spr_write_tm,
5568 &spr_read_tm, &spr_write_tm,
5569 KVM_REG_PPC_TFIAR, 0x00000000);
5570 spr_register_kvm(env, SPR_TEXASR, "TEXASR",
5571 &spr_read_tm, &spr_write_tm,
5572 &spr_read_tm, &spr_write_tm,
5573 KVM_REG_PPC_TEXASR, 0x00000000);
5574 spr_register(env, SPR_TEXASRU, "TEXASRU",
5575 &spr_read_tm_upper32, &spr_write_tm_upper32,
5576 &spr_read_tm_upper32, &spr_write_tm_upper32,
5577 0x00000000);
5578 }
5579
5580 static void register_power8_ebb_sprs(CPUPPCState *env)
5581 {
5582 spr_register(env, SPR_BESCRS, "BESCRS",
5583 &spr_read_ebb, &spr_write_ebb,
5584 &spr_read_generic, &spr_write_generic,
5585 0x00000000);
5586 spr_register(env, SPR_BESCRSU, "BESCRSU",
5587 &spr_read_ebb_upper32, &spr_write_ebb_upper32,
5588 &spr_read_prev_upper32, &spr_write_prev_upper32,
5589 0x00000000);
5590 spr_register(env, SPR_BESCRR, "BESCRR",
5591 &spr_read_ebb, &spr_write_ebb,
5592 &spr_read_generic, &spr_write_generic,
5593 0x00000000);
5594 spr_register(env, SPR_BESCRRU, "BESCRRU",
5595 &spr_read_ebb_upper32, &spr_write_ebb_upper32,
5596 &spr_read_prev_upper32, &spr_write_prev_upper32,
5597 0x00000000);
5598 spr_register_kvm(env, SPR_EBBHR, "EBBHR",
5599 &spr_read_ebb, &spr_write_ebb,
5600 &spr_read_generic, &spr_write_generic,
5601 KVM_REG_PPC_EBBHR, 0x00000000);
5602 spr_register_kvm(env, SPR_EBBRR, "EBBRR",
5603 &spr_read_ebb, &spr_write_ebb,
5604 &spr_read_generic, &spr_write_generic,
5605 KVM_REG_PPC_EBBRR, 0x00000000);
5606 spr_register_kvm(env, SPR_BESCR, "BESCR",
5607 &spr_read_ebb, &spr_write_ebb,
5608 &spr_read_generic, &spr_write_generic,
5609 KVM_REG_PPC_BESCR, 0x00000000);
5610 }
5611
5612 /* Virtual Time Base */
5613 static void register_vtb_sprs(CPUPPCState *env)
5614 {
5615 spr_register_kvm_hv(env, SPR_VTB, "VTB",
5616 SPR_NOACCESS, SPR_NOACCESS,
5617 &spr_read_vtb, SPR_NOACCESS,
5618 &spr_read_vtb, &spr_write_vtb,
5619 KVM_REG_PPC_VTB, 0x00000000);
5620 }
5621
5622 static void register_power8_fscr_sprs(CPUPPCState *env)
5623 {
5624 #if defined(CONFIG_USER_ONLY)
5625 target_ulong initval = 1ULL << FSCR_TAR;
5626 #else
5627 target_ulong initval = 0;
5628 #endif
5629 spr_register_kvm(env, SPR_FSCR, "FSCR",
5630 SPR_NOACCESS, SPR_NOACCESS,
5631 &spr_read_generic, &spr_write_generic,
5632 KVM_REG_PPC_FSCR, initval);
5633 }
5634
5635 static void register_power8_pspb_sprs(CPUPPCState *env)
5636 {
5637 spr_register_kvm(env, SPR_PSPB, "PSPB",
5638 SPR_NOACCESS, SPR_NOACCESS,
5639 &spr_read_generic, &spr_write_generic32,
5640 KVM_REG_PPC_PSPB, 0);
5641 }
5642
5643 static void register_power8_dpdes_sprs(CPUPPCState *env)
5644 {
5645 #if !defined(CONFIG_USER_ONLY)
5646 /* Directed Privileged Door-bell Exception State, used for IPI */
5647 spr_register_kvm_hv(env, SPR_DPDES, "DPDES",
5648 SPR_NOACCESS, SPR_NOACCESS,
5649 &spr_read_dpdes, SPR_NOACCESS,
5650 &spr_read_dpdes, &spr_write_dpdes,
5651 KVM_REG_PPC_DPDES, 0x00000000);
5652 #endif
5653 }
5654
5655 static void register_power8_ic_sprs(CPUPPCState *env)
5656 {
5657 #if !defined(CONFIG_USER_ONLY)
5658 spr_register_hv(env, SPR_IC, "IC",
5659 SPR_NOACCESS, SPR_NOACCESS,
5660 &spr_read_generic, SPR_NOACCESS,
5661 &spr_read_generic, &spr_write_generic,
5662 0);
5663 #endif
5664 }
5665
5666 /* SPRs specific to IBM POWER CPUs */
5667 static void register_power_common_book4_sprs(CPUPPCState *env)
5668 {
5669 #if !defined(CONFIG_USER_ONLY)
5670 spr_register_hv(env, SPR_HID0, "HID0",
5671 SPR_NOACCESS, SPR_NOACCESS,
5672 SPR_NOACCESS, SPR_NOACCESS,
5673 &spr_read_generic, &spr_core_write_generic,
5674 0x00000000);
5675 spr_register_hv(env, SPR_TSCR, "TSCR",
5676 SPR_NOACCESS, SPR_NOACCESS,
5677 SPR_NOACCESS, SPR_NOACCESS,
5678 &spr_read_generic, &spr_write_generic32,
5679 0x00000000);
5680 spr_register_hv(env, SPR_HMER, "HMER",
5681 SPR_NOACCESS, SPR_NOACCESS,
5682 SPR_NOACCESS, SPR_NOACCESS,
5683 &spr_read_generic, &spr_write_hmer,
5684 0x00000000);
5685 spr_register_hv(env, SPR_HMEER, "HMEER",
5686 SPR_NOACCESS, SPR_NOACCESS,
5687 SPR_NOACCESS, SPR_NOACCESS,
5688 &spr_read_generic, &spr_write_generic,
5689 0x00000000);
5690 spr_register_hv(env, SPR_TFMR, "TFMR",
5691 SPR_NOACCESS, SPR_NOACCESS,
5692 SPR_NOACCESS, SPR_NOACCESS,
5693 &spr_read_tfmr, &spr_write_tfmr,
5694 0x00000000);
5695 spr_register_hv(env, SPR_TRIG1, "TRIG1",
5696 SPR_NOACCESS, SPR_NOACCESS,
5697 &spr_access_nop, &spr_write_generic,
5698 &spr_access_nop, &spr_write_generic,
5699 0x00000000);
5700 spr_register_hv(env, SPR_TRIG2, "TRIG2",
5701 SPR_NOACCESS, SPR_NOACCESS,
5702 &spr_access_nop, &spr_write_generic,
5703 &spr_access_nop, &spr_write_generic,
5704 0x00000000);
5705 #endif
5706 }
5707
5708 static void register_power9_book4_sprs(CPUPPCState *env)
5709 {
5710 /* Add a number of P9 book4 registers */
5711 register_power_common_book4_sprs(env);
5712 #if !defined(CONFIG_USER_ONLY)
5713 spr_register_kvm(env, SPR_WORT, "WORT",
5714 SPR_NOACCESS, SPR_NOACCESS,
5715 &spr_read_generic, &spr_write_generic,
5716 KVM_REG_PPC_WORT, 0);
5717 #endif
5718 }
5719
5720 static void register_power8_book4_sprs(CPUPPCState *env)
5721 {
5722 /* Add a number of P8 book4 registers */
5723 register_power_common_book4_sprs(env);
5724 #if !defined(CONFIG_USER_ONLY)
5725 spr_register_kvm(env, SPR_ACOP, "ACOP",
5726 SPR_NOACCESS, SPR_NOACCESS,
5727 &spr_read_generic, &spr_write_generic,
5728 KVM_REG_PPC_ACOP, 0);
5729 /* PID is only in BookE in ISA v2.07 */
5730 spr_register_kvm(env, SPR_BOOKS_PID, "PIDR",
5731 SPR_NOACCESS, SPR_NOACCESS,
5732 &spr_read_generic, &spr_write_pidr,
5733 KVM_REG_PPC_PID, 0);
5734 spr_register_kvm(env, SPR_WORT, "WORT",
5735 SPR_NOACCESS, SPR_NOACCESS,
5736 &spr_read_generic, &spr_write_generic,
5737 KVM_REG_PPC_WORT, 0);
5738 #endif
5739 }
5740
5741 static void register_power7_book4_sprs(CPUPPCState *env)
5742 {
5743 /* Add a number of P7 book4 registers */
5744 #if !defined(CONFIG_USER_ONLY)
5745 register_power_common_book4_sprs(env);
5746 spr_register_kvm(env, SPR_ACOP, "ACOP",
5747 SPR_NOACCESS, SPR_NOACCESS,
5748 &spr_read_generic, &spr_write_generic,
5749 KVM_REG_PPC_ACOP, 0);
5750 /* PID is only in BookE in ISA v2.06 */
5751 spr_register_kvm(env, SPR_BOOKS_PID, "PIDR",
5752 SPR_NOACCESS, SPR_NOACCESS,
5753 &spr_read_generic, &spr_write_generic32,
5754 KVM_REG_PPC_PID, 0);
5755 #endif
5756 }
5757
5758 static void register_power8_rpr_sprs(CPUPPCState *env)
5759 {
5760 #if !defined(CONFIG_USER_ONLY)
5761 spr_register_hv(env, SPR_RPR, "RPR",
5762 SPR_NOACCESS, SPR_NOACCESS,
5763 SPR_NOACCESS, SPR_NOACCESS,
5764 &spr_read_generic, &spr_write_generic,
5765 0x00000103070F1F3F);
5766 #endif
5767 }
5768
5769 static void register_power9_mmu_sprs(CPUPPCState *env)
5770 {
5771 #if !defined(CONFIG_USER_ONLY)
5772 /* Partition Table Control */
5773 spr_register_kvm_hv(env, SPR_PTCR, "PTCR",
5774 SPR_NOACCESS, SPR_NOACCESS,
5775 SPR_NOACCESS, SPR_NOACCESS,
5776 &spr_read_generic, &spr_write_ptcr,
5777 KVM_REG_PPC_PTCR, 0x00000000);
5778 /* Address Segment Descriptor Register */
5779 spr_register_hv(env, SPR_ASDR, "ASDR",
5780 SPR_NOACCESS, SPR_NOACCESS,
5781 SPR_NOACCESS, SPR_NOACCESS,
5782 &spr_read_generic, &spr_write_generic,
5783 0x0000000000000000);
5784 /* PID is part of the BookS ISA from v3.0 */
5785 spr_register_kvm(env, SPR_BOOKS_PID, "PIDR",
5786 SPR_NOACCESS, SPR_NOACCESS,
5787 &spr_read_generic, &spr_write_pidr,
5788 KVM_REG_PPC_PID, 0);
5789 #endif
5790 }
5791
5792 static void register_power10_hash_sprs(CPUPPCState *env)
5793 {
5794 /*
5795 * it's the OS responsibility to generate a random value for the registers
5796 * in each process' context. So, initialize it with 0 here.
5797 */
5798 uint64_t hashkeyr_initial_value = 0, hashpkeyr_initial_value = 0;
5799 #if defined(CONFIG_USER_ONLY)
5800 /* in linux-user, setup the hash register with a random value */
5801 GRand *rand = g_rand_new();
5802 hashkeyr_initial_value =
5803 ((uint64_t)g_rand_int(rand) << 32) | (uint64_t)g_rand_int(rand);
5804 hashpkeyr_initial_value =
5805 ((uint64_t)g_rand_int(rand) << 32) | (uint64_t)g_rand_int(rand);
5806 g_rand_free(rand);
5807 #endif
5808 spr_register(env, SPR_HASHKEYR, "HASHKEYR",
5809 SPR_NOACCESS, SPR_NOACCESS,
5810 &spr_read_generic, &spr_write_generic,
5811 hashkeyr_initial_value);
5812 spr_register_hv(env, SPR_HASHPKEYR, "HASHPKEYR",
5813 SPR_NOACCESS, SPR_NOACCESS,
5814 SPR_NOACCESS, SPR_NOACCESS,
5815 &spr_read_generic, &spr_write_generic,
5816 hashpkeyr_initial_value);
5817 }
5818
5819 static void register_power10_dexcr_sprs(CPUPPCState *env)
5820 {
5821 spr_register(env, SPR_DEXCR, "DEXCR",
5822 SPR_NOACCESS, SPR_NOACCESS,
5823 &spr_read_generic, &spr_write_generic32,
5824 0);
5825
5826 spr_register(env, SPR_UDEXCR, "UDEXCR",
5827 &spr_read_dexcr_ureg, SPR_NOACCESS,
5828 &spr_read_dexcr_ureg, SPR_NOACCESS,
5829 0);
5830
5831 spr_register_hv(env, SPR_HDEXCR, "HDEXCR",
5832 SPR_NOACCESS, SPR_NOACCESS,
5833 SPR_NOACCESS, SPR_NOACCESS,
5834 &spr_read_generic, &spr_write_generic32,
5835 0);
5836
5837 spr_register(env, SPR_UHDEXCR, "UHDEXCR",
5838 &spr_read_dexcr_ureg, SPR_NOACCESS,
5839 &spr_read_dexcr_ureg, SPR_NOACCESS,
5840 0);
5841 }
5842
5843 /*
5844 * Initialize PMU counter overflow timers for Power8 and
5845 * newer Power chips when using TCG.
5846 */
5847 static void init_tcg_pmu_power8(CPUPPCState *env)
5848 {
5849 /* Init PMU overflow timers */
5850 if (tcg_enabled()) {
5851 cpu_ppc_pmu_init(env);
5852 }
5853 }
5854
5855 static void init_proc_book3s_common(CPUPPCState *env)
5856 {
5857 register_non_embedded_sprs(env);
5858 register_book3s_altivec_sprs(env);
5859 register_book3s_pmu_sup_sprs(env);
5860 register_book3s_pmu_user_sprs(env);
5861 register_book3s_ctrl_sprs(env);
5862 /*
5863 * Can't find information on what this should be on reset. This
5864 * value is the one used by 74xx processors.
5865 */
5866 vscr_init(env, 0x00010000);
5867
5868 spr_register(env, SPR_USPRG3, "USPRG3",
5869 &spr_read_ureg, SPR_NOACCESS,
5870 &spr_read_ureg, SPR_NOACCESS,
5871 0x00000000);
5872 }
5873
5874 static void init_proc_970(CPUPPCState *env)
5875 {
5876 /* Common Registers */
5877 init_proc_book3s_common(env);
5878 register_sdr1_sprs(env);
5879 register_book3s_dbg_sprs(env);
5880
5881 /* 970 Specific Registers */
5882 register_970_hid_sprs(env);
5883 register_970_hior_sprs(env);
5884 register_low_BATs(env);
5885 register_970_pmu_sup_sprs(env);
5886 register_970_pmu_user_sprs(env);
5887 register_970_lpar_sprs(env);
5888 register_970_dbg_sprs(env);
5889
5890 /* env variables */
5891 env->dcache_line_size = 128;
5892 env->icache_line_size = 128;
5893
5894 /* Allocate hardware IRQ controller */
5895 init_excp_970(env);
5896 ppc970_irq_init(env_archcpu(env));
5897 }
5898
5899 POWERPC_FAMILY(970)(ObjectClass *oc, void *data)
5900 {
5901 DeviceClass *dc = DEVICE_CLASS(oc);
5902 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5903
5904 dc->desc = "PowerPC 970";
5905 pcc->init_proc = init_proc_970;
5906 pcc->check_pow = check_pow_970;
5907 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5908 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5909 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
5910 PPC_FLOAT_STFIWX |
5911 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5912 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5913 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5914 PPC_64B | PPC_ALTIVEC |
5915 PPC_SEGMENT_64B | PPC_SLBI;
5916 pcc->insns_flags2 = PPC2_FP_CVT_S64 | PPC2_MEM_LWSYNC;
5917 pcc->msr_mask = (1ull << MSR_SF) |
5918 (1ull << MSR_VR) |
5919 (1ull << MSR_POW) |
5920 (1ull << MSR_EE) |
5921 (1ull << MSR_PR) |
5922 (1ull << MSR_FP) |
5923 (1ull << MSR_ME) |
5924 (1ull << MSR_FE0) |
5925 (1ull << MSR_SE) |
5926 (1ull << MSR_DE) |
5927 (1ull << MSR_FE1) |
5928 (1ull << MSR_IR) |
5929 (1ull << MSR_DR) |
5930 (1ull << MSR_PMM) |
5931 (1ull << MSR_RI);
5932 pcc->mmu_model = POWERPC_MMU_64B;
5933 #if !defined(CONFIG_USER_ONLY)
5934 pcc->hash64_opts = &ppc_hash64_opts_basic;
5935 #endif
5936 pcc->excp_model = POWERPC_EXCP_970;
5937 pcc->bus_model = PPC_FLAGS_INPUT_970;
5938 pcc->bfd_mach = bfd_mach_ppc64;
5939 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
5940 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
5941 POWERPC_FLAG_BUS_CLK;
5942 pcc->l1_dcache_size = 0x8000;
5943 pcc->l1_icache_size = 0x10000;
5944 }
5945
5946 static void init_proc_power5plus(CPUPPCState *env)
5947 {
5948 /* Common Registers */
5949 init_proc_book3s_common(env);
5950 register_sdr1_sprs(env);
5951 register_book3s_dbg_sprs(env);
5952
5953 /* POWER5+ Specific Registers */
5954 register_970_hid_sprs(env);
5955 register_970_hior_sprs(env);
5956 register_low_BATs(env);
5957 register_970_pmu_sup_sprs(env);
5958 register_970_pmu_user_sprs(env);
5959 register_power5p_common_sprs(env);
5960 register_power5p_lpar_sprs(env);
5961 register_power5p_ear_sprs(env);
5962 register_power5p_tb_sprs(env);
5963
5964 /* env variables */
5965 env->dcache_line_size = 128;
5966 env->icache_line_size = 128;
5967
5968 /* Allocate hardware IRQ controller */
5969 init_excp_970(env);
5970 ppc970_irq_init(env_archcpu(env));
5971 }
5972
5973 POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data)
5974 {
5975 DeviceClass *dc = DEVICE_CLASS(oc);
5976 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5977
5978 dc->fw_name = "PowerPC,POWER5";
5979 dc->desc = "POWER5+";
5980 pcc->init_proc = init_proc_power5plus;
5981 pcc->check_pow = check_pow_970;
5982 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5983 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5984 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
5985 PPC_FLOAT_STFIWX |
5986 PPC_FLOAT_EXT |
5987 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5988 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5989 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5990 PPC_64B |
5991 PPC_POPCNTB |
5992 PPC_SEGMENT_64B | PPC_SLBI;
5993 pcc->insns_flags2 = PPC2_FP_CVT_S64 | PPC2_MEM_LWSYNC;
5994 pcc->msr_mask = (1ull << MSR_SF) |
5995 (1ull << MSR_VR) |
5996 (1ull << MSR_POW) |
5997 (1ull << MSR_EE) |
5998 (1ull << MSR_PR) |
5999 (1ull << MSR_FP) |
6000 (1ull << MSR_ME) |
6001 (1ull << MSR_FE0) |
6002 (1ull << MSR_SE) |
6003 (1ull << MSR_DE) |
6004 (1ull << MSR_FE1) |
6005 (1ull << MSR_IR) |
6006 (1ull << MSR_DR) |
6007 (1ull << MSR_PMM) |
6008 (1ull << MSR_RI);
6009 pcc->lpcr_mask = LPCR_RMLS | LPCR_ILE | LPCR_LPES0 | LPCR_LPES1 |
6010 LPCR_RMI | LPCR_HDICE;
6011 pcc->mmu_model = POWERPC_MMU_2_03;
6012 #if !defined(CONFIG_USER_ONLY)
6013 pcc->hash64_opts = &ppc_hash64_opts_basic;
6014 pcc->lrg_decr_bits = 32;
6015 #endif
6016 pcc->excp_model = POWERPC_EXCP_970;
6017 pcc->bus_model = PPC_FLAGS_INPUT_970;
6018 pcc->bfd_mach = bfd_mach_ppc64;
6019 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6020 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6021 POWERPC_FLAG_BUS_CLK;
6022 pcc->l1_dcache_size = 0x8000;
6023 pcc->l1_icache_size = 0x10000;
6024 }
6025
6026 static void init_proc_POWER7(CPUPPCState *env)
6027 {
6028 /* Common Registers */
6029 init_proc_book3s_common(env);
6030 register_sdr1_sprs(env);
6031 register_book3s_dbg_sprs(env);
6032
6033 /* POWER7 Specific Registers */
6034 register_book3s_ids_sprs(env);
6035 register_rmor_sprs(env);
6036 register_amr_sprs(env);
6037 register_book3s_purr_sprs(env);
6038 register_power5p_common_sprs(env);
6039 register_power5p_lpar_sprs(env);
6040 register_power5p_ear_sprs(env);
6041 register_power5p_tb_sprs(env);
6042 register_power6_common_sprs(env);
6043 register_HEIR32_spr(env);
6044 register_power6_dbg_sprs(env);
6045 register_power7_book4_sprs(env);
6046
6047 /* env variables */
6048 env->dcache_line_size = 128;
6049 env->icache_line_size = 128;
6050
6051 /* Allocate hardware IRQ controller */
6052 init_excp_POWER7(env);
6053 ppcPOWER7_irq_init(env_archcpu(env));
6054 }
6055
6056 static bool ppc_pvr_match_power7(PowerPCCPUClass *pcc, uint32_t pvr, bool best)
6057 {
6058 uint32_t base = pvr & CPU_POWERPC_POWER_SERVER_MASK;
6059 uint32_t pcc_base = pcc->pvr & CPU_POWERPC_POWER_SERVER_MASK;
6060
6061 if (!best) {
6062 if (base == CPU_POWERPC_POWER7_BASE) {
6063 return true;
6064 }
6065 if (base == CPU_POWERPC_POWER7P_BASE) {
6066 return true;
6067 }
6068 }
6069
6070 if (base != pcc_base) {
6071 return false;
6072 }
6073
6074 return true;
6075 }
6076
6077 POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
6078 {
6079 DeviceClass *dc = DEVICE_CLASS(oc);
6080 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6081
6082 dc->fw_name = "PowerPC,POWER7";
6083 dc->desc = "POWER7";
6084 pcc->pvr_match = ppc_pvr_match_power7;
6085 pcc->pcr_mask = PCR_VEC_DIS | PCR_VSX_DIS | PCR_COMPAT_2_05;
6086 pcc->pcr_supported = PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
6087 pcc->init_proc = init_proc_POWER7;
6088 pcc->check_pow = check_pow_nocheck;
6089 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
6090 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6091 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6092 PPC_FLOAT_FRSQRTES |
6093 PPC_FLOAT_STFIWX |
6094 PPC_FLOAT_EXT |
6095 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6096 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6097 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6098 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
6099 PPC_SEGMENT_64B | PPC_SLBI |
6100 PPC_POPCNTB | PPC_POPCNTWD |
6101 PPC_CILDST;
6102 pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 |
6103 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
6104 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
6105 PPC2_FP_TST_ISA206 | PPC2_FP_CVT_S64 |
6106 PPC2_PM_ISA206 | PPC2_MEM_LWSYNC | PPC2_BCDA_ISA206;
6107 pcc->msr_mask = (1ull << MSR_SF) |
6108 (1ull << MSR_VR) |
6109 (1ull << MSR_VSX) |
6110 (1ull << MSR_EE) |
6111 (1ull << MSR_PR) |
6112 (1ull << MSR_FP) |
6113 (1ull << MSR_ME) |
6114 (1ull << MSR_FE0) |
6115 (1ull << MSR_SE) |
6116 (1ull << MSR_DE) |
6117 (1ull << MSR_FE1) |
6118 (1ull << MSR_IR) |
6119 (1ull << MSR_DR) |
6120 (1ull << MSR_PMM) |
6121 (1ull << MSR_RI) |
6122 (1ull << MSR_LE);
6123 pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_DPFD |
6124 LPCR_VRMASD | LPCR_RMLS | LPCR_ILE |
6125 LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2 |
6126 LPCR_MER | LPCR_TC |
6127 LPCR_LPES0 | LPCR_LPES1 | LPCR_HDICE;
6128 pcc->lpcr_pm = LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2;
6129 pcc->mmu_model = POWERPC_MMU_2_06;
6130 #if !defined(CONFIG_USER_ONLY)
6131 pcc->hash64_opts = &ppc_hash64_opts_POWER7;
6132 pcc->lrg_decr_bits = 32;
6133 #endif
6134 pcc->excp_model = POWERPC_EXCP_POWER7;
6135 pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
6136 pcc->bfd_mach = bfd_mach_ppc64;
6137 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6138 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6139 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
6140 POWERPC_FLAG_VSX;
6141 pcc->l1_dcache_size = 0x8000;
6142 pcc->l1_icache_size = 0x8000;
6143 }
6144
6145 static void init_proc_POWER8(CPUPPCState *env)
6146 {
6147 /* Common Registers */
6148 init_proc_book3s_common(env);
6149 register_sdr1_sprs(env);
6150 register_book3s_207_dbg_sprs(env);
6151
6152 /* Common TCG PMU */
6153 init_tcg_pmu_power8(env);
6154
6155 /* POWER8 Specific Registers */
6156 register_book3s_ids_sprs(env);
6157 register_rmor_sprs(env);
6158 register_amr_sprs(env);
6159 register_iamr_sprs(env);
6160 register_book3s_purr_sprs(env);
6161 register_power5p_common_sprs(env);
6162 register_power5p_lpar_sprs(env);
6163 register_power5p_ear_sprs(env);
6164 register_power5p_tb_sprs(env);
6165 register_power6_common_sprs(env);
6166 register_HEIR32_spr(env);
6167 register_power6_dbg_sprs(env);
6168 register_power8_tce_address_control_sprs(env);
6169 register_power8_ids_sprs(env);
6170 register_power8_ebb_sprs(env);
6171 register_power8_fscr_sprs(env);
6172 register_power8_pmu_sup_sprs(env);
6173 register_power8_pmu_user_sprs(env);
6174 register_power8_tm_sprs(env);
6175 register_power8_pspb_sprs(env);
6176 register_power8_dpdes_sprs(env);
6177 register_vtb_sprs(env);
6178 register_power8_ic_sprs(env);
6179 register_power8_book4_sprs(env);
6180 register_power8_rpr_sprs(env);
6181
6182 /* env variables */
6183 env->dcache_line_size = 128;
6184 env->icache_line_size = 128;
6185
6186 /* Allocate hardware IRQ controller */
6187 init_excp_POWER8(env);
6188 ppcPOWER7_irq_init(env_archcpu(env));
6189 }
6190
6191 static bool ppc_pvr_match_power8(PowerPCCPUClass *pcc, uint32_t pvr, bool best)
6192 {
6193 uint32_t base = pvr & CPU_POWERPC_POWER_SERVER_MASK;
6194 uint32_t pcc_base = pcc->pvr & CPU_POWERPC_POWER_SERVER_MASK;
6195
6196 if (!best) {
6197 if (base == CPU_POWERPC_POWER8_BASE) {
6198 return true;
6199 }
6200 if (base == CPU_POWERPC_POWER8E_BASE) {
6201 return true;
6202 }
6203 if (base == CPU_POWERPC_POWER8NVL_BASE) {
6204 return true;
6205 }
6206 }
6207 if (base != pcc_base) {
6208 return false;
6209 }
6210
6211 return true;
6212 }
6213
6214 POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
6215 {
6216 DeviceClass *dc = DEVICE_CLASS(oc);
6217 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6218
6219 dc->fw_name = "PowerPC,POWER8";
6220 dc->desc = "POWER8";
6221 pcc->pvr_match = ppc_pvr_match_power8;
6222 pcc->pcr_mask = PCR_TM_DIS | PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
6223 pcc->pcr_supported = PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
6224 pcc->init_proc = init_proc_POWER8;
6225 pcc->check_pow = check_pow_nocheck;
6226 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
6227 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6228 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6229 PPC_FLOAT_FRSQRTES |
6230 PPC_FLOAT_STFIWX |
6231 PPC_FLOAT_EXT |
6232 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6233 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6234 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6235 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
6236 PPC_SEGMENT_64B | PPC_SLBI |
6237 PPC_POPCNTB | PPC_POPCNTWD |
6238 PPC_CILDST;
6239 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
6240 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
6241 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
6242 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
6243 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
6244 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
6245 PPC2_TM | PPC2_PM_ISA206 | PPC2_MEM_LWSYNC |
6246 PPC2_BCDA_ISA206;
6247 pcc->msr_mask = (1ull << MSR_SF) |
6248 (1ull << MSR_HV) |
6249 (1ull << MSR_TM) |
6250 (1ull << MSR_VR) |
6251 (1ull << MSR_VSX) |
6252 (1ull << MSR_EE) |
6253 (1ull << MSR_PR) |
6254 (1ull << MSR_FP) |
6255 (1ull << MSR_ME) |
6256 (1ull << MSR_FE0) |
6257 (1ull << MSR_SE) |
6258 (1ull << MSR_DE) |
6259 (1ull << MSR_FE1) |
6260 (1ull << MSR_IR) |
6261 (1ull << MSR_DR) |
6262 (1ull << MSR_PMM) |
6263 (1ull << MSR_RI) |
6264 (1ull << MSR_TS0) |
6265 (1ull << MSR_TS1) |
6266 (1ull << MSR_LE);
6267 pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV |
6268 LPCR_DPFD | LPCR_VRMASD | LPCR_RMLS | LPCR_ILE |
6269 LPCR_AIL | LPCR_ONL | LPCR_P8_PECE0 | LPCR_P8_PECE1 |
6270 LPCR_P8_PECE2 | LPCR_P8_PECE3 | LPCR_P8_PECE4 |
6271 LPCR_MER | LPCR_TC | LPCR_LPES0 | LPCR_HDICE;
6272 pcc->lpcr_pm = LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_PECE2 |
6273 LPCR_P8_PECE3 | LPCR_P8_PECE4;
6274 pcc->mmu_model = POWERPC_MMU_2_07;
6275 #if !defined(CONFIG_USER_ONLY)
6276 pcc->hash64_opts = &ppc_hash64_opts_POWER7;
6277 pcc->lrg_decr_bits = 32;
6278 pcc->n_host_threads = 8;
6279 #endif
6280 pcc->excp_model = POWERPC_EXCP_POWER8;
6281 pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
6282 pcc->bfd_mach = bfd_mach_ppc64;
6283 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6284 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6285 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
6286 POWERPC_FLAG_VSX | POWERPC_FLAG_TM;
6287 pcc->l1_dcache_size = 0x8000;
6288 pcc->l1_icache_size = 0x8000;
6289 }
6290
6291 #ifndef CONFIG_USER_ONLY
6292 /*
6293 * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings
6294 * Encoded as array of int_32s in the form:
6295 * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy
6296 * x -> AP encoding
6297 * y -> radix mode supported page size (encoded as a shift)
6298 */
6299 static struct ppc_radix_page_info POWER9_radix_page_info = {
6300 .count = 4,
6301 .entries = {
6302 0x0000000c, /* 4K - enc: 0x0 */
6303 0xa0000010, /* 64K - enc: 0x5 */
6304 0x20000015, /* 2M - enc: 0x1 */
6305 0x4000001e /* 1G - enc: 0x2 */
6306 }
6307 };
6308 #endif /* CONFIG_USER_ONLY */
6309
6310 static void init_proc_POWER9(CPUPPCState *env)
6311 {
6312 /* Common Registers */
6313 init_proc_book3s_common(env);
6314 register_book3s_207_dbg_sprs(env);
6315
6316 /* Common TCG PMU */
6317 init_tcg_pmu_power8(env);
6318
6319 /* POWER8 Specific Registers */
6320 register_book3s_ids_sprs(env);
6321 register_amr_sprs(env);
6322 register_iamr_sprs(env);
6323 register_book3s_purr_sprs(env);
6324 register_power5p_common_sprs(env);
6325 register_power5p_lpar_sprs(env);
6326 register_power5p_ear_sprs(env);
6327 register_power5p_tb_sprs(env);
6328 register_power6_common_sprs(env);
6329 register_HEIR32_spr(env);
6330 register_power6_dbg_sprs(env);
6331 register_power8_tce_address_control_sprs(env);
6332 register_power8_ids_sprs(env);
6333 register_power8_ebb_sprs(env);
6334 register_power8_fscr_sprs(env);
6335 register_power8_pmu_sup_sprs(env);
6336 register_power8_pmu_user_sprs(env);
6337 register_power8_tm_sprs(env);
6338 register_power8_pspb_sprs(env);
6339 register_power8_dpdes_sprs(env);
6340 register_vtb_sprs(env);
6341 register_power8_ic_sprs(env);
6342 register_power9_book4_sprs(env);
6343 register_power8_rpr_sprs(env);
6344 register_power9_mmu_sprs(env);
6345
6346 /* POWER9 Specific registers */
6347 spr_register_kvm(env, SPR_TIDR, "TIDR", NULL, NULL,
6348 spr_read_generic, spr_write_generic,
6349 KVM_REG_PPC_TIDR, 0);
6350
6351 /* FIXME: Filter fields properly based on privilege level */
6352 spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL,
6353 spr_read_generic, spr_write_generic,
6354 KVM_REG_PPC_PSSCR, 0);
6355
6356 /* env variables */
6357 env->dcache_line_size = 128;
6358 env->icache_line_size = 128;
6359
6360 /* Allocate hardware IRQ controller */
6361 init_excp_POWER9(env);
6362 ppcPOWER9_irq_init(env_archcpu(env));
6363 }
6364
6365 static bool ppc_pvr_match_power9(PowerPCCPUClass *pcc, uint32_t pvr, bool best)
6366 {
6367 uint32_t base = pvr & CPU_POWERPC_POWER_SERVER_MASK;
6368 uint32_t pcc_base = pcc->pvr & CPU_POWERPC_POWER_SERVER_MASK;
6369
6370 if (!best) {
6371 if (base == CPU_POWERPC_POWER9_BASE) {
6372 return true;
6373 }
6374 }
6375
6376 if (base != pcc_base) {
6377 return false;
6378 }
6379
6380 if ((pvr & 0x0f00) != (pcc->pvr & 0x0f00)) {
6381 /* Major DD version does not match */
6382 return false;
6383 }
6384
6385 if ((pvr & 0x0f00) == 0x200) {
6386 if ((pvr & 0xf) < 2) {
6387 /* DD2.0, DD2.1 match power9_v2.0 */
6388 if ((pcc->pvr & 0xf) == 0) {
6389 return true;
6390 }
6391 } else {
6392 /* DD2.2, DD2.3 match power9_v2.2 */
6393 if ((pcc->pvr & 0xf) == 2) {
6394 return true;
6395 }
6396 }
6397 }
6398
6399 return false;
6400 }
6401
6402 POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data)
6403 {
6404 DeviceClass *dc = DEVICE_CLASS(oc);
6405 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6406
6407 dc->fw_name = "PowerPC,POWER9";
6408 dc->desc = "POWER9";
6409 pcc->pvr_match = ppc_pvr_match_power9;
6410 pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07;
6411 pcc->pcr_supported = PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | PCR_COMPAT_2_06 |
6412 PCR_COMPAT_2_05;
6413 pcc->init_proc = init_proc_POWER9;
6414 pcc->check_pow = check_pow_nocheck;
6415 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
6416 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6417 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6418 PPC_FLOAT_FRSQRTES |
6419 PPC_FLOAT_STFIWX |
6420 PPC_FLOAT_EXT |
6421 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6422 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6423 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6424 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
6425 PPC_SEGMENT_64B | PPC_SLBI |
6426 PPC_POPCNTB | PPC_POPCNTWD |
6427 PPC_CILDST;
6428 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
6429 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
6430 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
6431 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
6432 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
6433 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
6434 PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL | PPC2_MEM_LWSYNC |
6435 PPC2_BCDA_ISA206;
6436 pcc->msr_mask = (1ull << MSR_SF) |
6437 (1ull << MSR_HV) |
6438 (1ull << MSR_TM) |
6439 (1ull << MSR_VR) |
6440 (1ull << MSR_VSX) |
6441 (1ull << MSR_EE) |
6442 (1ull << MSR_PR) |
6443 (1ull << MSR_FP) |
6444 (1ull << MSR_ME) |
6445 (1ull << MSR_FE0) |
6446 (1ull << MSR_SE) |
6447 (1ull << MSR_DE) |
6448 (1ull << MSR_FE1) |
6449 (1ull << MSR_IR) |
6450 (1ull << MSR_DR) |
6451 (1ull << MSR_PMM) |
6452 (1ull << MSR_RI) |
6453 (1ull << MSR_LE);
6454 pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD |
6455 (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL |
6456 LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD |
6457 (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE |
6458 LPCR_DEE | LPCR_OEE))
6459 | LPCR_MER | LPCR_GTSE | LPCR_TC |
6460 LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE;
6461 pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE;
6462 pcc->mmu_model = POWERPC_MMU_3_00;
6463 #if !defined(CONFIG_USER_ONLY)
6464 /* segment page size remain the same */
6465 pcc->hash64_opts = &ppc_hash64_opts_POWER7;
6466 pcc->radix_page_info = &POWER9_radix_page_info;
6467 pcc->lrg_decr_bits = 56;
6468 pcc->n_host_threads = 4;
6469 #endif
6470 pcc->excp_model = POWERPC_EXCP_POWER9;
6471 pcc->bus_model = PPC_FLAGS_INPUT_POWER9;
6472 pcc->bfd_mach = bfd_mach_ppc64;
6473 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6474 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6475 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
6476 POWERPC_FLAG_VSX | POWERPC_FLAG_TM | POWERPC_FLAG_SCV;
6477 pcc->l1_dcache_size = 0x8000;
6478 pcc->l1_icache_size = 0x8000;
6479 }
6480
6481 #ifndef CONFIG_USER_ONLY
6482 /*
6483 * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings
6484 * Encoded as array of int_32s in the form:
6485 * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy
6486 * x -> AP encoding
6487 * y -> radix mode supported page size (encoded as a shift)
6488 */
6489 static struct ppc_radix_page_info POWER10_radix_page_info = {
6490 .count = 4,
6491 .entries = {
6492 0x0000000c, /* 4K - enc: 0x0 */
6493 0xa0000010, /* 64K - enc: 0x5 */
6494 0x20000015, /* 2M - enc: 0x1 */
6495 0x4000001e /* 1G - enc: 0x2 */
6496 }
6497 };
6498 #endif /* !CONFIG_USER_ONLY */
6499
6500 static void init_proc_POWER10(CPUPPCState *env)
6501 {
6502 /* Common Registers */
6503 init_proc_book3s_common(env);
6504 register_book3s_207_dbg_sprs(env);
6505
6506 /* Common TCG PMU */
6507 init_tcg_pmu_power8(env);
6508
6509 /* POWER8 Specific Registers */
6510 register_book3s_ids_sprs(env);
6511 register_amr_sprs(env);
6512 register_iamr_sprs(env);
6513 register_book3s_purr_sprs(env);
6514 register_power5p_common_sprs(env);
6515 register_power5p_lpar_sprs(env);
6516 register_power5p_ear_sprs(env);
6517 register_power5p_tb_sprs(env);
6518 register_power6_common_sprs(env);
6519 register_HEIR64_spr(env);
6520 register_power6_dbg_sprs(env);
6521 register_power8_tce_address_control_sprs(env);
6522 register_power8_ids_sprs(env);
6523 register_power8_ebb_sprs(env);
6524 register_power8_fscr_sprs(env);
6525 register_power8_pmu_sup_sprs(env);
6526 register_power8_pmu_user_sprs(env);
6527 register_power8_tm_sprs(env);
6528 register_power8_pspb_sprs(env);
6529 register_power8_dpdes_sprs(env);
6530 register_vtb_sprs(env);
6531 register_power8_ic_sprs(env);
6532 register_power9_book4_sprs(env);
6533 register_power8_rpr_sprs(env);
6534 register_power9_mmu_sprs(env);
6535 register_power10_hash_sprs(env);
6536 register_power10_dexcr_sprs(env);
6537 register_power10_pmu_sup_sprs(env);
6538 register_power10_pmu_user_sprs(env);
6539
6540 /* FIXME: Filter fields properly based on privilege level */
6541 spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL,
6542 spr_read_generic, spr_write_generic,
6543 KVM_REG_PPC_PSSCR, 0);
6544
6545 /* env variables */
6546 env->dcache_line_size = 128;
6547 env->icache_line_size = 128;
6548
6549 /* Allocate hardware IRQ controller */
6550 init_excp_POWER10(env);
6551 ppcPOWER9_irq_init(env_archcpu(env));
6552 }
6553
6554 static bool ppc_pvr_match_power10(PowerPCCPUClass *pcc, uint32_t pvr, bool best)
6555 {
6556 uint32_t base = pvr & CPU_POWERPC_POWER_SERVER_MASK;
6557 uint32_t pcc_base = pcc->pvr & CPU_POWERPC_POWER_SERVER_MASK;
6558
6559 if (!best) {
6560 if (base == CPU_POWERPC_POWER10_BASE) {
6561 return true;
6562 }
6563 }
6564
6565 if (base != pcc_base) {
6566 return false;
6567 }
6568
6569 if ((pvr & 0x0f00) == (pcc->pvr & 0x0f00)) {
6570 /* Major DD version matches power10_v2.0 */
6571 return true;
6572 }
6573
6574 return false;
6575 }
6576
6577 POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data)
6578 {
6579 DeviceClass *dc = DEVICE_CLASS(oc);
6580 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6581
6582 dc->fw_name = "PowerPC,POWER10";
6583 dc->desc = "POWER10";
6584 pcc->pvr_match = ppc_pvr_match_power10;
6585 pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07 |
6586 PCR_COMPAT_3_00;
6587 pcc->pcr_supported = PCR_COMPAT_3_10 | PCR_COMPAT_3_00 | PCR_COMPAT_2_07 |
6588 PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
6589 pcc->init_proc = init_proc_POWER10;
6590 pcc->check_pow = check_pow_nocheck;
6591 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
6592 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6593 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6594 PPC_FLOAT_FRSQRTES |
6595 PPC_FLOAT_STFIWX |
6596 PPC_FLOAT_EXT |
6597 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6598 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6599 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6600 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
6601 PPC_SEGMENT_64B | PPC_SLBI |
6602 PPC_POPCNTB | PPC_POPCNTWD |
6603 PPC_CILDST;
6604 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
6605 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
6606 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
6607 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
6608 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
6609 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
6610 PPC2_ISA300 | PPC2_PRCNTL | PPC2_ISA310 |
6611 PPC2_MEM_LWSYNC | PPC2_BCDA_ISA206;
6612 pcc->msr_mask = (1ull << MSR_SF) |
6613 (1ull << MSR_HV) |
6614 (1ull << MSR_VR) |
6615 (1ull << MSR_VSX) |
6616 (1ull << MSR_EE) |
6617 (1ull << MSR_PR) |
6618 (1ull << MSR_FP) |
6619 (1ull << MSR_ME) |
6620 (1ull << MSR_FE0) |
6621 (1ull << MSR_SE) |
6622 (1ull << MSR_DE) |
6623 (1ull << MSR_FE1) |
6624 (1ull << MSR_IR) |
6625 (1ull << MSR_DR) |
6626 (1ull << MSR_PMM) |
6627 (1ull << MSR_RI) |
6628 (1ull << MSR_LE);
6629 pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD |
6630 (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL |
6631 LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD |
6632 (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE |
6633 LPCR_DEE | LPCR_OEE))
6634 | LPCR_MER | LPCR_GTSE | LPCR_TC |
6635 LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE;
6636 /* DD2 adds an extra HAIL bit */
6637 pcc->lpcr_mask |= LPCR_HAIL;
6638
6639 pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE;
6640 pcc->mmu_model = POWERPC_MMU_3_00;
6641 #if !defined(CONFIG_USER_ONLY)
6642 /* segment page size remain the same */
6643 pcc->hash64_opts = &ppc_hash64_opts_POWER7;
6644 pcc->radix_page_info = &POWER10_radix_page_info;
6645 pcc->lrg_decr_bits = 56;
6646 #endif
6647 pcc->excp_model = POWERPC_EXCP_POWER10;
6648 pcc->bus_model = PPC_FLAGS_INPUT_POWER9;
6649 pcc->bfd_mach = bfd_mach_ppc64;
6650 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6651 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6652 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
6653 POWERPC_FLAG_VSX | POWERPC_FLAG_SCV;
6654 pcc->l1_dcache_size = 0x8000;
6655 pcc->l1_icache_size = 0x8000;
6656 }
6657
6658 #if !defined(CONFIG_USER_ONLY)
6659 void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp)
6660 {
6661 CPUPPCState *env = &cpu->env;
6662
6663 cpu->vhyp = vhyp;
6664
6665 /*
6666 * With a virtual hypervisor mode we never allow the CPU to go
6667 * hypervisor mode itself
6668 */
6669 env->msr_mask &= ~MSR_HVB;
6670 }
6671
6672 void cpu_ppc_set_1lpar(PowerPCCPU *cpu)
6673 {
6674 CPUPPCState *env = &cpu->env;
6675
6676 /*
6677 * pseries SMT means "LPAR per core" mode, e.g., msgsndp is usable
6678 * between threads.
6679 */
6680 if (env->flags & POWERPC_FLAG_SMT) {
6681 env->flags |= POWERPC_FLAG_SMT_1LPAR;
6682 }
6683 }
6684 #endif /* !defined(CONFIG_USER_ONLY) */
6685
6686 #endif /* defined(TARGET_PPC64) */
6687
6688 /*****************************************************************************/
6689 /* Generic CPU instantiation routine */
6690 static void init_ppc_proc(PowerPCCPU *cpu)
6691 {
6692 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
6693 CPUPPCState *env = &cpu->env;
6694 #if !defined(CONFIG_USER_ONLY)
6695 int i;
6696
6697 /* Set all exception vectors to an invalid address */
6698 for (i = 0; i < POWERPC_EXCP_NB; i++) {
6699 env->excp_vectors[i] = (target_ulong)(-1ULL);
6700 }
6701 env->ivor_mask = 0x00000000;
6702 env->ivpr_mask = 0x00000000;
6703 /* Default MMU definitions */
6704 env->nb_BATs = 0;
6705 env->nb_tlb = 0;
6706 env->nb_ways = 0;
6707 env->tlb_type = TLB_NONE;
6708 #endif
6709 /* Register SPR common to all PowerPC implementations */
6710 register_generic_sprs(cpu);
6711
6712 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */
6713 (*pcc->init_proc)(env);
6714
6715 /* MSR bits & flags consistency checks */
6716 if (env->msr_mask & (1 << 25)) {
6717 switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
6718 case POWERPC_FLAG_SPE:
6719 case POWERPC_FLAG_VRE:
6720 break;
6721 default:
6722 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6723 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n");
6724 exit(1);
6725 }
6726 } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
6727 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6728 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n");
6729 exit(1);
6730 }
6731 if (env->msr_mask & (1 << 17)) {
6732 switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
6733 case POWERPC_FLAG_TGPR:
6734 case POWERPC_FLAG_CE:
6735 break;
6736 default:
6737 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6738 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n");
6739 exit(1);
6740 }
6741 } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
6742 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6743 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n");
6744 exit(1);
6745 }
6746 if (env->msr_mask & (1 << 10)) {
6747 switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
6748 POWERPC_FLAG_UBLE)) {
6749 case POWERPC_FLAG_SE:
6750 case POWERPC_FLAG_DWE:
6751 case POWERPC_FLAG_UBLE:
6752 break;
6753 default:
6754 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6755 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or "
6756 "POWERPC_FLAG_UBLE\n");
6757 exit(1);
6758 }
6759 } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
6760 POWERPC_FLAG_UBLE)) {
6761 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6762 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor "
6763 "POWERPC_FLAG_UBLE\n");
6764 exit(1);
6765 }
6766 if (env->msr_mask & (1 << 9)) {
6767 switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
6768 case POWERPC_FLAG_BE:
6769 case POWERPC_FLAG_DE:
6770 break;
6771 default:
6772 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6773 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n");
6774 exit(1);
6775 }
6776 } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
6777 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6778 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n");
6779 exit(1);
6780 }
6781 if (env->msr_mask & (1 << 2)) {
6782 switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
6783 case POWERPC_FLAG_PX:
6784 case POWERPC_FLAG_PMM:
6785 break;
6786 default:
6787 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6788 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n");
6789 exit(1);
6790 }
6791 } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
6792 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6793 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n");
6794 exit(1);
6795 }
6796 if ((env->flags & POWERPC_FLAG_BUS_CLK) == 0) {
6797 fprintf(stderr, "PowerPC flags inconsistency\n"
6798 "Should define the time-base and decrementer clock source\n");
6799 exit(1);
6800 }
6801 /* Allocate TLBs buffer when needed */
6802 #if !defined(CONFIG_USER_ONLY)
6803 if (env->nb_tlb != 0) {
6804 int nb_tlb = env->nb_tlb;
6805 if (env->id_tlbs != 0) {
6806 nb_tlb *= 2;
6807 }
6808 switch (env->tlb_type) {
6809 case TLB_6XX:
6810 env->tlb.tlb6 = g_new0(ppc6xx_tlb_t, nb_tlb);
6811 break;
6812 case TLB_EMB:
6813 env->tlb.tlbe = g_new0(ppcemb_tlb_t, nb_tlb);
6814 break;
6815 case TLB_MAS:
6816 env->tlb.tlbm = g_new0(ppcmas_tlb_t, nb_tlb);
6817 break;
6818 }
6819 /* Pre-compute some useful values */
6820 env->tlb_per_way = env->nb_tlb / env->nb_ways;
6821 }
6822 #endif
6823 if (env->check_pow == NULL) {
6824 warn_report("no power management check handler registered."
6825 " Attempt QEMU to crash very soon !");
6826 }
6827 }
6828
6829
6830 static void ppc_cpu_realize(DeviceState *dev, Error **errp)
6831 {
6832 CPUState *cs = CPU(dev);
6833 PowerPCCPU *cpu = POWERPC_CPU(dev);
6834 CPUPPCState *env = &cpu->env;
6835 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
6836 Error *local_err = NULL;
6837
6838 cpu_exec_realizefn(cs, &local_err);
6839 if (local_err != NULL) {
6840 error_propagate(errp, local_err);
6841 return;
6842 }
6843 if (cpu->vcpu_id == UNASSIGNED_CPU_INDEX) {
6844 cpu->vcpu_id = cs->cpu_index;
6845 }
6846
6847 if (tcg_enabled()) {
6848 if (ppc_fixup_cpu(cpu) != 0) {
6849 error_setg(errp, "Unable to emulate selected CPU with TCG");
6850 goto unrealize;
6851 }
6852 }
6853
6854 create_ppc_opcodes(cpu, &local_err);
6855 if (local_err != NULL) {
6856 error_propagate(errp, local_err);
6857 goto unrealize;
6858 }
6859 init_ppc_proc(cpu);
6860
6861 ppc_gdb_init(cs, pcc);
6862 qemu_init_vcpu(cs);
6863
6864 pcc->parent_realize(dev, errp);
6865
6866 if (env_cpu(env)->nr_threads > 1) {
6867 env->flags |= POWERPC_FLAG_SMT;
6868 }
6869
6870 return;
6871
6872 unrealize:
6873 cpu_exec_unrealizefn(cs);
6874 }
6875
6876 static void ppc_cpu_unrealize(DeviceState *dev)
6877 {
6878 PowerPCCPU *cpu = POWERPC_CPU(dev);
6879 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
6880
6881 pcc->parent_unrealize(dev);
6882
6883 cpu_remove_sync(CPU(cpu));
6884
6885 destroy_ppc_opcodes(cpu);
6886 }
6887
6888 static gint ppc_cpu_compare_class_pvr(gconstpointer a, gconstpointer b)
6889 {
6890 ObjectClass *oc = (ObjectClass *)a;
6891 uint32_t pvr = *(uint32_t *)b;
6892 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a;
6893
6894 /* -cpu host does a PVR lookup during construction */
6895 if (unlikely(strcmp(object_class_get_name(oc),
6896 TYPE_HOST_POWERPC_CPU) == 0)) {
6897 return -1;
6898 }
6899
6900 return pcc->pvr == pvr ? 0 : -1;
6901 }
6902
6903 PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr)
6904 {
6905 GSList *list, *item;
6906 PowerPCCPUClass *pcc = NULL;
6907
6908 list = object_class_get_list(TYPE_POWERPC_CPU, false);
6909 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr);
6910 if (item != NULL) {
6911 pcc = POWERPC_CPU_CLASS(item->data);
6912 }
6913 g_slist_free(list);
6914
6915 return pcc;
6916 }
6917
6918 static gint ppc_cpu_compare_class_pvr_mask(gconstpointer a, gconstpointer b)
6919 {
6920 ObjectClass *oc = (ObjectClass *)a;
6921 uint32_t pvr = *(uint32_t *)b;
6922 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a;
6923
6924 /* -cpu host does a PVR lookup during construction */
6925 if (unlikely(strcmp(object_class_get_name(oc),
6926 TYPE_HOST_POWERPC_CPU) == 0)) {
6927 return -1;
6928 }
6929
6930 if (pcc->pvr_match(pcc, pvr, true)) {
6931 return 0;
6932 }
6933
6934 return -1;
6935 }
6936
6937 PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr)
6938 {
6939 GSList *list, *item;
6940 PowerPCCPUClass *pcc = NULL;
6941
6942 list = object_class_get_list(TYPE_POWERPC_CPU, true);
6943 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr_mask);
6944 if (item != NULL) {
6945 pcc = POWERPC_CPU_CLASS(item->data);
6946 }
6947 g_slist_free(list);
6948
6949 return pcc;
6950 }
6951
6952 static const char *ppc_cpu_lookup_alias(const char *alias)
6953 {
6954 int ai;
6955
6956 for (ai = 0; ppc_cpu_aliases[ai].alias != NULL; ai++) {
6957 if (strcmp(ppc_cpu_aliases[ai].alias, alias) == 0) {
6958 return ppc_cpu_aliases[ai].model;
6959 }
6960 }
6961
6962 return NULL;
6963 }
6964
6965 ObjectClass *ppc_cpu_class_by_name(const char *name)
6966 {
6967 char *cpu_model, *typename;
6968 ObjectClass *oc;
6969 const char *p;
6970 unsigned long pvr;
6971
6972 /*
6973 * Lookup by PVR if cpu_model is valid 8 digit hex number (excl:
6974 * 0x prefix if present)
6975 */
6976 if (!qemu_strtoul(name, &p, 16, &pvr)) {
6977 int len = p - name;
6978 len = (len == 10) && (name[1] == 'x') ? len - 2 : len;
6979 if ((len == 8) && (*p == '\0')) {
6980 return OBJECT_CLASS(ppc_cpu_class_by_pvr(pvr));
6981 }
6982 }
6983
6984 /*
6985 * All ppc CPUs represent hardware that exists in the real world, i.e.: we
6986 * do not have a "max" CPU with all possible emulated features enabled.
6987 * Return the default CPU type for the machine because that has greater
6988 * chance of being useful as the "max" CPU.
6989 */
6990 #if !defined(CONFIG_USER_ONLY)
6991 if (strcmp(name, "max") == 0) {
6992 MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine());
6993 if (mc) {
6994 return object_class_by_name(mc->default_cpu_type);
6995 }
6996 }
6997 #endif
6998
6999 cpu_model = g_ascii_strdown(name, -1);
7000 p = ppc_cpu_lookup_alias(cpu_model);
7001 if (p) {
7002 g_free(cpu_model);
7003 cpu_model = g_strdup(p);
7004 }
7005
7006 typename = g_strdup_printf("%s" POWERPC_CPU_TYPE_SUFFIX, cpu_model);
7007 oc = object_class_by_name(typename);
7008 g_free(typename);
7009 g_free(cpu_model);
7010
7011 return oc;
7012 }
7013
7014 PowerPCCPUClass *ppc_cpu_get_family_class(PowerPCCPUClass *pcc)
7015 {
7016 ObjectClass *oc = OBJECT_CLASS(pcc);
7017
7018 while (oc && !object_class_is_abstract(oc)) {
7019 oc = object_class_get_parent(oc);
7020 }
7021 assert(oc);
7022
7023 return POWERPC_CPU_CLASS(oc);
7024 }
7025
7026 /* Sort by PVR, ordering special case "host" last. */
7027 static gint ppc_cpu_list_compare(gconstpointer a, gconstpointer b)
7028 {
7029 ObjectClass *oc_a = (ObjectClass *)a;
7030 ObjectClass *oc_b = (ObjectClass *)b;
7031 PowerPCCPUClass *pcc_a = POWERPC_CPU_CLASS(oc_a);
7032 PowerPCCPUClass *pcc_b = POWERPC_CPU_CLASS(oc_b);
7033 const char *name_a = object_class_get_name(oc_a);
7034 const char *name_b = object_class_get_name(oc_b);
7035
7036 if (strcmp(name_a, TYPE_HOST_POWERPC_CPU) == 0) {
7037 return 1;
7038 } else if (strcmp(name_b, TYPE_HOST_POWERPC_CPU) == 0) {
7039 return -1;
7040 } else {
7041 /* Avoid an integer overflow during subtraction */
7042 if (pcc_a->pvr < pcc_b->pvr) {
7043 return -1;
7044 } else if (pcc_a->pvr > pcc_b->pvr) {
7045 return 1;
7046 } else {
7047 return 0;
7048 }
7049 }
7050 }
7051
7052 static void ppc_cpu_list_entry(gpointer data, gpointer user_data)
7053 {
7054 ObjectClass *oc = data;
7055 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7056 DeviceClass *family = DEVICE_CLASS(ppc_cpu_get_family_class(pcc));
7057 const char *typename = object_class_get_name(oc);
7058 char *name;
7059 int i;
7060
7061 if (unlikely(strcmp(typename, TYPE_HOST_POWERPC_CPU) == 0)) {
7062 return;
7063 }
7064
7065 name = cpu_model_from_type(typename);
7066 qemu_printf("PowerPC %-16s PVR %08x\n", name, pcc->pvr);
7067 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
7068 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i];
7069 ObjectClass *alias_oc = ppc_cpu_class_by_name(alias->model);
7070
7071 if (alias_oc != oc) {
7072 continue;
7073 }
7074 /*
7075 * If running with KVM, we might update the family alias later, so
7076 * avoid printing the wrong alias here and use "preferred" instead
7077 */
7078 if (strcmp(alias->alias, family->desc) == 0) {
7079 qemu_printf("PowerPC %-16s (alias for preferred %s CPU)\n",
7080 alias->alias, family->desc);
7081 } else {
7082 qemu_printf("PowerPC %-16s (alias for %s)\n",
7083 alias->alias, name);
7084 }
7085 }
7086 g_free(name);
7087 }
7088
7089 void ppc_cpu_list(void)
7090 {
7091 GSList *list;
7092
7093 list = object_class_get_list(TYPE_POWERPC_CPU, false);
7094 list = g_slist_sort(list, ppc_cpu_list_compare);
7095 g_slist_foreach(list, ppc_cpu_list_entry, NULL);
7096 g_slist_free(list);
7097
7098 #ifdef CONFIG_KVM
7099 qemu_printf("\n");
7100 qemu_printf("PowerPC %s\n", "host");
7101 #endif
7102 }
7103
7104 static void ppc_cpu_set_pc(CPUState *cs, vaddr value)
7105 {
7106 PowerPCCPU *cpu = POWERPC_CPU(cs);
7107
7108 cpu->env.nip = value;
7109 }
7110
7111 static vaddr ppc_cpu_get_pc(CPUState *cs)
7112 {
7113 PowerPCCPU *cpu = POWERPC_CPU(cs);
7114
7115 return cpu->env.nip;
7116 }
7117
7118 #ifdef CONFIG_TCG
7119 static void ppc_restore_state_to_opc(CPUState *cs,
7120 const TranslationBlock *tb,
7121 const uint64_t *data)
7122 {
7123 PowerPCCPU *cpu = POWERPC_CPU(cs);
7124
7125 cpu->env.nip = data[0];
7126 }
7127 #endif /* CONFIG_TCG */
7128
7129 static bool ppc_cpu_has_work(CPUState *cs)
7130 {
7131 return cs->interrupt_request & CPU_INTERRUPT_HARD;
7132 }
7133
7134 static int ppc_cpu_mmu_index(CPUState *cs, bool ifetch)
7135 {
7136 return ppc_env_mmu_index(cpu_env(cs), ifetch);
7137 }
7138
7139 static void ppc_cpu_reset_hold(Object *obj)
7140 {
7141 CPUState *cs = CPU(obj);
7142 PowerPCCPU *cpu = POWERPC_CPU(cs);
7143 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(obj);
7144 CPUPPCState *env = &cpu->env;
7145 target_ulong msr;
7146 int i;
7147
7148 if (pcc->parent_phases.hold) {
7149 pcc->parent_phases.hold(obj);
7150 }
7151
7152 msr = (target_ulong)0;
7153 msr |= (target_ulong)MSR_HVB;
7154 msr |= (target_ulong)1 << MSR_EP;
7155 #if defined(DO_SINGLE_STEP) && 0
7156 /* Single step trace mode */
7157 msr |= (target_ulong)1 << MSR_SE;
7158 msr |= (target_ulong)1 << MSR_BE;
7159 #endif
7160 #if defined(CONFIG_USER_ONLY)
7161 msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */
7162 msr |= (target_ulong)1 << MSR_FE0; /* Allow floating point exceptions */
7163 msr |= (target_ulong)1 << MSR_FE1;
7164 msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */
7165 msr |= (target_ulong)1 << MSR_VSX; /* Allow VSX usage */
7166 msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */
7167 msr |= (target_ulong)1 << MSR_PR;
7168 #if defined(TARGET_PPC64)
7169 msr |= (target_ulong)1 << MSR_TM; /* Transactional memory */
7170 #endif
7171 #if !TARGET_BIG_ENDIAN
7172 msr |= (target_ulong)1 << MSR_LE; /* Little-endian user mode */
7173 if (!((env->msr_mask >> MSR_LE) & 1)) {
7174 fprintf(stderr, "Selected CPU does not support little-endian.\n");
7175 exit(1);
7176 }
7177 #endif
7178 #endif
7179
7180 #if defined(TARGET_PPC64)
7181 if (mmu_is_64bit(env->mmu_model)) {
7182 msr |= (1ULL << MSR_SF);
7183 }
7184 #endif
7185
7186 hreg_store_msr(env, msr, 1);
7187
7188 #if !defined(CONFIG_USER_ONLY)
7189 env->nip = env->hreset_vector | env->excp_prefix;
7190
7191 if (tcg_enabled()) {
7192 cpu_breakpoint_remove_all(cs, BP_CPU);
7193 cpu_watchpoint_remove_all(cs, BP_CPU);
7194 if (env->mmu_model != POWERPC_MMU_REAL) {
7195 ppc_tlb_invalidate_all(env);
7196 }
7197 pmu_mmcr01_updated(env);
7198 }
7199
7200 /* clean any pending stop state */
7201 env->resume_as_sreset = 0;
7202 #endif
7203 hreg_compute_hflags(env);
7204 env->reserve_addr = (target_ulong)-1ULL;
7205 /* Be sure no exception or interrupt is pending */
7206 env->pending_interrupts = 0;
7207 cs->exception_index = POWERPC_EXCP_NONE;
7208 env->error_code = 0;
7209 ppc_irq_reset(cpu);
7210
7211 /* tininess for underflow is detected before rounding */
7212 set_float_detect_tininess(float_tininess_before_rounding,
7213 &env->fp_status);
7214
7215 for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) {
7216 ppc_spr_t *spr = &env->spr_cb[i];
7217
7218 if (!spr->name) {
7219 continue;
7220 }
7221 env->spr[i] = spr->default_value;
7222 }
7223 }
7224
7225 #ifndef CONFIG_USER_ONLY
7226
7227 static bool ppc_cpu_is_big_endian(CPUState *cs)
7228 {
7229 cpu_synchronize_state(cs);
7230
7231 return !FIELD_EX64(cpu_env(cs)->msr, MSR, LE);
7232 }
7233
7234 static bool ppc_get_irq_stats(InterruptStatsProvider *obj,
7235 uint64_t **irq_counts, unsigned int *nb_irqs)
7236 {
7237 CPUPPCState *env = &POWERPC_CPU(obj)->env;
7238
7239 *irq_counts = env->excp_stats;
7240 *nb_irqs = ARRAY_SIZE(env->excp_stats);
7241 return true;
7242 }
7243
7244 #ifdef CONFIG_TCG
7245 static void ppc_cpu_exec_enter(CPUState *cs)
7246 {
7247 PowerPCCPU *cpu = POWERPC_CPU(cs);
7248
7249 if (cpu->vhyp) {
7250 PPCVirtualHypervisorClass *vhc =
7251 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
7252 vhc->cpu_exec_enter(cpu->vhyp, cpu);
7253 }
7254 }
7255
7256 static void ppc_cpu_exec_exit(CPUState *cs)
7257 {
7258 PowerPCCPU *cpu = POWERPC_CPU(cs);
7259
7260 if (cpu->vhyp) {
7261 PPCVirtualHypervisorClass *vhc =
7262 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
7263 vhc->cpu_exec_exit(cpu->vhyp, cpu);
7264 }
7265 }
7266 #endif /* CONFIG_TCG */
7267
7268 #endif /* !CONFIG_USER_ONLY */
7269
7270 static void ppc_cpu_instance_init(Object *obj)
7271 {
7272 PowerPCCPU *cpu = POWERPC_CPU(obj);
7273 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
7274 CPUPPCState *env = &cpu->env;
7275
7276 cpu->vcpu_id = UNASSIGNED_CPU_INDEX;
7277
7278 env->msr_mask = pcc->msr_mask;
7279 env->mmu_model = pcc->mmu_model;
7280 env->excp_model = pcc->excp_model;
7281 env->bus_model = pcc->bus_model;
7282 env->insns_flags = pcc->insns_flags;
7283 env->insns_flags2 = pcc->insns_flags2;
7284 env->flags = pcc->flags;
7285 env->bfd_mach = pcc->bfd_mach;
7286 env->check_pow = pcc->check_pow;
7287
7288 /*
7289 * Mark HV mode as supported if the CPU has an MSR_HV bit in the
7290 * msr_mask. The mask can later be cleared by PAPR mode but the hv
7291 * mode support will remain, thus enforcing that we cannot use
7292 * priv. instructions in guest in PAPR mode. For 970 we currently
7293 * simply don't set HV in msr_mask thus simulating an "Apple mode"
7294 * 970. If we ever want to support 970 HV mode, we'll have to add
7295 * a processor attribute of some sort.
7296 */
7297 #if !defined(CONFIG_USER_ONLY)
7298 env->has_hv_mode = !!(env->msr_mask & MSR_HVB);
7299 #endif
7300
7301 ppc_hash64_init(cpu);
7302 }
7303
7304 static void ppc_cpu_instance_finalize(Object *obj)
7305 {
7306 PowerPCCPU *cpu = POWERPC_CPU(obj);
7307
7308 ppc_hash64_finalize(cpu);
7309 }
7310
7311 static bool ppc_pvr_match_default(PowerPCCPUClass *pcc, uint32_t pvr, bool best)
7312 {
7313 return pcc->pvr == pvr;
7314 }
7315
7316 static void ppc_disas_set_info(CPUState *cs, disassemble_info *info)
7317 {
7318 CPUPPCState *env = cpu_env(cs);
7319
7320 if ((env->hflags >> MSR_LE) & 1) {
7321 info->endian = BFD_ENDIAN_LITTLE;
7322 }
7323 info->mach = env->bfd_mach;
7324 if (!env->bfd_mach) {
7325 #ifdef TARGET_PPC64
7326 info->mach = bfd_mach_ppc64;
7327 #else
7328 info->mach = bfd_mach_ppc;
7329 #endif
7330 }
7331
7332 info->cap_arch = CS_ARCH_PPC;
7333 #ifdef TARGET_PPC64
7334 info->cap_mode = CS_MODE_64;
7335 #endif
7336 }
7337
7338 static Property ppc_cpu_properties[] = {
7339 DEFINE_PROP_BOOL("pre-2.8-migration", PowerPCCPU, pre_2_8_migration, false),
7340 DEFINE_PROP_BOOL("pre-2.10-migration", PowerPCCPU, pre_2_10_migration,
7341 false),
7342 DEFINE_PROP_BOOL("pre-3.0-migration", PowerPCCPU, pre_3_0_migration,
7343 false),
7344 DEFINE_PROP_END_OF_LIST(),
7345 };
7346
7347 #ifndef CONFIG_USER_ONLY
7348 #include "hw/core/sysemu-cpu-ops.h"
7349
7350 static const struct SysemuCPUOps ppc_sysemu_ops = {
7351 .get_phys_page_debug = ppc_cpu_get_phys_page_debug,
7352 .write_elf32_note = ppc32_cpu_write_elf32_note,
7353 .write_elf64_note = ppc64_cpu_write_elf64_note,
7354 .virtio_is_big_endian = ppc_cpu_is_big_endian,
7355 .legacy_vmsd = &vmstate_ppc_cpu,
7356 };
7357 #endif
7358
7359 #ifdef CONFIG_TCG
7360 #include "hw/core/tcg-cpu-ops.h"
7361
7362 static const TCGCPUOps ppc_tcg_ops = {
7363 .initialize = ppc_translate_init,
7364 .restore_state_to_opc = ppc_restore_state_to_opc,
7365
7366 #ifdef CONFIG_USER_ONLY
7367 .record_sigsegv = ppc_cpu_record_sigsegv,
7368 #else
7369 .tlb_fill = ppc_cpu_tlb_fill,
7370 .cpu_exec_interrupt = ppc_cpu_exec_interrupt,
7371 .do_interrupt = ppc_cpu_do_interrupt,
7372 .cpu_exec_enter = ppc_cpu_exec_enter,
7373 .cpu_exec_exit = ppc_cpu_exec_exit,
7374 .do_unaligned_access = ppc_cpu_do_unaligned_access,
7375 .do_transaction_failed = ppc_cpu_do_transaction_failed,
7376 .debug_excp_handler = ppc_cpu_debug_excp_handler,
7377 .debug_check_breakpoint = ppc_cpu_debug_check_breakpoint,
7378 .debug_check_watchpoint = ppc_cpu_debug_check_watchpoint,
7379 #endif /* !CONFIG_USER_ONLY */
7380 };
7381 #endif /* CONFIG_TCG */
7382
7383 static void ppc_cpu_class_init(ObjectClass *oc, void *data)
7384 {
7385 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7386 CPUClass *cc = CPU_CLASS(oc);
7387 DeviceClass *dc = DEVICE_CLASS(oc);
7388 ResettableClass *rc = RESETTABLE_CLASS(oc);
7389
7390 device_class_set_parent_realize(dc, ppc_cpu_realize,
7391 &pcc->parent_realize);
7392 device_class_set_parent_unrealize(dc, ppc_cpu_unrealize,
7393 &pcc->parent_unrealize);
7394 pcc->pvr_match = ppc_pvr_match_default;
7395 device_class_set_props(dc, ppc_cpu_properties);
7396
7397 resettable_class_set_parent_phases(rc, NULL, ppc_cpu_reset_hold, NULL,
7398 &pcc->parent_phases);
7399
7400 cc->class_by_name = ppc_cpu_class_by_name;
7401 cc->has_work = ppc_cpu_has_work;
7402 cc->mmu_index = ppc_cpu_mmu_index;
7403 cc->dump_state = ppc_cpu_dump_state;
7404 cc->set_pc = ppc_cpu_set_pc;
7405 cc->get_pc = ppc_cpu_get_pc;
7406 cc->gdb_read_register = ppc_cpu_gdb_read_register;
7407 cc->gdb_write_register = ppc_cpu_gdb_write_register;
7408 #ifndef CONFIG_USER_ONLY
7409 cc->sysemu_ops = &ppc_sysemu_ops;
7410 INTERRUPT_STATS_PROVIDER_CLASS(oc)->get_statistics = ppc_get_irq_stats;
7411 #endif
7412
7413 cc->gdb_num_core_regs = 71;
7414 #ifdef USE_APPLE_GDB
7415 cc->gdb_read_register = ppc_cpu_gdb_read_register_apple;
7416 cc->gdb_write_register = ppc_cpu_gdb_write_register_apple;
7417 cc->gdb_num_core_regs = 71 + 32;
7418 #endif
7419
7420 cc->gdb_arch_name = ppc_gdb_arch_name;
7421 #if defined(TARGET_PPC64)
7422 cc->gdb_core_xml_file = "power64-core.xml";
7423 #else
7424 cc->gdb_core_xml_file = "power-core.xml";
7425 #endif
7426 cc->disas_set_info = ppc_disas_set_info;
7427
7428 dc->fw_name = "PowerPC,UNKNOWN";
7429
7430 #ifdef CONFIG_TCG
7431 cc->tcg_ops = &ppc_tcg_ops;
7432 #endif /* CONFIG_TCG */
7433 }
7434
7435 static const TypeInfo ppc_cpu_type_info = {
7436 .name = TYPE_POWERPC_CPU,
7437 .parent = TYPE_CPU,
7438 .instance_size = sizeof(PowerPCCPU),
7439 .instance_align = __alignof__(PowerPCCPU),
7440 .instance_init = ppc_cpu_instance_init,
7441 .instance_finalize = ppc_cpu_instance_finalize,
7442 .abstract = true,
7443 .class_size = sizeof(PowerPCCPUClass),
7444 .class_init = ppc_cpu_class_init,
7445 #ifndef CONFIG_USER_ONLY
7446 .interfaces = (InterfaceInfo[]) {
7447 { TYPE_INTERRUPT_STATS_PROVIDER },
7448 { }
7449 },
7450 #endif
7451 };
7452
7453 #ifndef CONFIG_USER_ONLY
7454 static const TypeInfo ppc_vhyp_type_info = {
7455 .name = TYPE_PPC_VIRTUAL_HYPERVISOR,
7456 .parent = TYPE_INTERFACE,
7457 .class_size = sizeof(PPCVirtualHypervisorClass),
7458 };
7459 #endif
7460
7461 static void ppc_cpu_register_types(void)
7462 {
7463 type_register_static(&ppc_cpu_type_info);
7464 #ifndef CONFIG_USER_ONLY
7465 type_register_static(&ppc_vhyp_type_info);
7466 #endif
7467 }
7468
7469 void ppc_cpu_dump_state(CPUState *cs, FILE *f, int flags)
7470 {
7471 #define RGPL 4
7472 #define RFPL 4
7473
7474 CPUPPCState *env = cpu_env(cs);
7475 int i;
7476
7477 qemu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
7478 TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n",
7479 env->nip, env->lr, env->ctr, cpu_read_xer(env),
7480 cs->cpu_index);
7481 qemu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
7482 "%08x iidx %d didx %d\n",
7483 env->msr, env->spr[SPR_HID0], env->hflags,
7484 ppc_env_mmu_index(env, true), ppc_env_mmu_index(env, false));
7485 #if !defined(CONFIG_USER_ONLY)
7486 if (env->tb_env) {
7487 qemu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
7488 " DECR " TARGET_FMT_lu "\n", cpu_ppc_load_tbu(env),
7489 cpu_ppc_load_tbl(env), cpu_ppc_load_decr(env));
7490 }
7491 #else
7492 qemu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64 "\n", cpu_ppc_load_tbu(env),
7493 cpu_ppc_load_tbl(env));
7494 #endif
7495 for (i = 0; i < 32; i++) {
7496 if ((i & (RGPL - 1)) == 0) {
7497 qemu_fprintf(f, "GPR%02d", i);
7498 }
7499 qemu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
7500 if ((i & (RGPL - 1)) == (RGPL - 1)) {
7501 qemu_fprintf(f, "\n");
7502 }
7503 }
7504 qemu_fprintf(f, "CR ");
7505 for (i = 0; i < 8; i++)
7506 qemu_fprintf(f, "%01x", env->crf[i]);
7507 qemu_fprintf(f, " [");
7508 for (i = 0; i < 8; i++) {
7509 char a = '-';
7510 if (env->crf[i] & 0x08) {
7511 a = 'L';
7512 } else if (env->crf[i] & 0x04) {
7513 a = 'G';
7514 } else if (env->crf[i] & 0x02) {
7515 a = 'E';
7516 }
7517 qemu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
7518 }
7519 qemu_fprintf(f, " ] RES %03x@" TARGET_FMT_lx "\n",
7520 (int)env->reserve_length, env->reserve_addr);
7521
7522 if (flags & CPU_DUMP_FPU) {
7523 for (i = 0; i < 32; i++) {
7524 if ((i & (RFPL - 1)) == 0) {
7525 qemu_fprintf(f, "FPR%02d", i);
7526 }
7527 qemu_fprintf(f, " %016" PRIx64, *cpu_fpr_ptr(env, i));
7528 if ((i & (RFPL - 1)) == (RFPL - 1)) {
7529 qemu_fprintf(f, "\n");
7530 }
7531 }
7532 qemu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
7533 }
7534
7535 #if !defined(CONFIG_USER_ONLY)
7536 qemu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
7537 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
7538 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
7539 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
7540
7541 qemu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
7542 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
7543 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
7544 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
7545
7546 qemu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
7547 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
7548 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
7549 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
7550
7551 switch (env->excp_model) {
7552 #if defined(TARGET_PPC64)
7553 case POWERPC_EXCP_POWER7:
7554 case POWERPC_EXCP_POWER8:
7555 case POWERPC_EXCP_POWER9:
7556 case POWERPC_EXCP_POWER10:
7557 qemu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n",
7558 env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]);
7559 break;
7560 #endif
7561 case POWERPC_EXCP_BOOKE:
7562 qemu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
7563 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
7564 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
7565 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
7566
7567 qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
7568 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
7569 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
7570 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
7571
7572 qemu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
7573 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
7574 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
7575 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
7576
7577 qemu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
7578 " EPR " TARGET_FMT_lx "\n",
7579 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
7580 env->spr[SPR_BOOKE_EPR]);
7581
7582 /* FSL-specific */
7583 qemu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
7584 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
7585 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
7586 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
7587
7588 /*
7589 * IVORs are left out as they are large and do not change often --
7590 * they can be read with "p $ivor0", "p $ivor1", etc.
7591 */
7592 break;
7593 case POWERPC_EXCP_40x:
7594 qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
7595 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
7596 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR],
7597 env->spr[SPR_40x_ESR], env->spr[SPR_40x_DEAR]);
7598
7599 qemu_fprintf(f, " EVPR " TARGET_FMT_lx " SRR2 " TARGET_FMT_lx
7600 " SRR3 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
7601 env->spr[SPR_40x_EVPR], env->spr[SPR_40x_SRR2],
7602 env->spr[SPR_40x_SRR3], env->spr[SPR_40x_PID]);
7603 break;
7604 default:
7605 break;
7606 }
7607
7608 #if defined(TARGET_PPC64)
7609 if (env->flags & POWERPC_FLAG_CFAR) {
7610 qemu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
7611 }
7612 #endif
7613
7614 if (env->spr_cb[SPR_LPCR].name) {
7615 qemu_fprintf(f, " LPCR " TARGET_FMT_lx "\n", env->spr[SPR_LPCR]);
7616 }
7617
7618 switch (env->mmu_model) {
7619 case POWERPC_MMU_32B:
7620 case POWERPC_MMU_SOFT_6xx:
7621 #if defined(TARGET_PPC64)
7622 case POWERPC_MMU_64B:
7623 case POWERPC_MMU_2_03:
7624 case POWERPC_MMU_2_06:
7625 case POWERPC_MMU_2_07:
7626 case POWERPC_MMU_3_00:
7627 #endif
7628 if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */
7629 qemu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env->spr[SPR_SDR1]);
7630 }
7631 if (env->spr_cb[SPR_PTCR].name) { /* PTCR Exists */
7632 qemu_fprintf(f, " PTCR " TARGET_FMT_lx " ", env->spr[SPR_PTCR]);
7633 }
7634 qemu_fprintf(f, " DAR " TARGET_FMT_lx " DSISR " TARGET_FMT_lx "\n",
7635 env->spr[SPR_DAR], env->spr[SPR_DSISR]);
7636 break;
7637 case POWERPC_MMU_BOOKE206:
7638 qemu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
7639 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
7640 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
7641 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
7642
7643 qemu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
7644 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
7645 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
7646 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
7647
7648 qemu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
7649 " TLB1CFG " TARGET_FMT_lx "\n",
7650 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
7651 env->spr[SPR_BOOKE_TLB1CFG]);
7652 break;
7653 default:
7654 break;
7655 }
7656 #endif
7657
7658 #undef RGPL
7659 #undef RFPL
7660 }
7661 type_init(ppc_cpu_register_types)
armbru's QEMU hackery