hw/display/tcx.c

   1 /*
   2  * QEMU TCX Frame buffer
   3  *
   4  * Copyright (c) 2003-2005 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "qemu/osdep.h"
  26 #include "qapi/error.h"
  27 #include "qemu-common.h"
  28 #include "cpu.h" /* FIXME shouldn't use TARGET_PAGE_SIZE */
  29 #include "ui/console.h"
  30 #include "ui/pixel_ops.h"
  31 #include "hw/loader.h"
  32 #include "hw/sysbus.h"
  33 #include "qemu/error-report.h"
  34
  35 #define TCX_ROM_FILE "QEMU,tcx.bin"
  36 #define FCODE_MAX_ROM_SIZE 0x10000
  37
  38 #define MAXX 1024
  39 #define MAXY 768
  40 #define TCX_DAC_NREGS    16
  41 #define TCX_THC_NREGS    0x1000
  42 #define TCX_DHC_NREGS    0x4000
  43 #define TCX_TEC_NREGS    0x1000
  44 #define TCX_ALT_NREGS    0x8000
  45 #define TCX_STIP_NREGS   0x800000
  46 #define TCX_BLIT_NREGS   0x800000
  47 #define TCX_RSTIP_NREGS  0x800000
  48 #define TCX_RBLIT_NREGS  0x800000
  49
  50 #define TCX_THC_MISC     0x818
  51 #define TCX_THC_CURSXY   0x8fc
  52 #define TCX_THC_CURSMASK 0x900
  53 #define TCX_THC_CURSBITS 0x980
  54
  55 #define TYPE_TCX "SUNW,tcx"
  56 #define TCX(obj) OBJECT_CHECK(TCXState, (obj), TYPE_TCX)
  57
  58 typedef struct TCXState {
  59     SysBusDevice parent_obj;
  60
  61     QemuConsole *con;
  62     qemu_irq irq;
  63     uint8_t *vram;
  64     uint32_t *vram24, *cplane;
  65     hwaddr prom_addr;
  66     MemoryRegion rom;
  67     MemoryRegion vram_mem;
  68     MemoryRegion vram_8bit;
  69     MemoryRegion vram_24bit;
  70     MemoryRegion stip;
  71     MemoryRegion blit;
  72     MemoryRegion vram_cplane;
  73     MemoryRegion rstip;
  74     MemoryRegion rblit;
  75     MemoryRegion tec;
  76     MemoryRegion dac;
  77     MemoryRegion thc;
  78     MemoryRegion dhc;
  79     MemoryRegion alt;
  80     MemoryRegion thc24;
  81
  82     ram_addr_t vram24_offset, cplane_offset;
  83     uint32_t tmpblit;
  84     uint32_t vram_size;
  85     uint32_t palette[260];
  86     uint8_t r[260], g[260], b[260];
  87     uint16_t width, height, depth;
  88     uint8_t dac_index, dac_state;
  89     uint32_t thcmisc;
  90     uint32_t cursmask[32];
  91     uint32_t cursbits[32];
  92     uint16_t cursx;
  93     uint16_t cursy;
  94 } TCXState;
  95
  96 static void tcx_set_dirty(TCXState *s, ram_addr_t addr, int len)
  97 {
  98     memory_region_set_dirty(&s->vram_mem, addr, len);
  99
 100     if (s->depth == 24) {
 101         memory_region_set_dirty(&s->vram_mem, s->vram24_offset + addr * 4,
 102                                 len * 4);
 103         memory_region_set_dirty(&s->vram_mem, s->cplane_offset + addr * 4,
 104                                 len * 4);
 105     }
 106 }
 107
 108 static inline int tcx24_check_dirty(TCXState *s, ram_addr_t page,
 109                                     ram_addr_t page24, ram_addr_t cpage)
 110 {
 111     int ret;
 112
 113     ret = memory_region_get_dirty(&s->vram_mem, page, TARGET_PAGE_SIZE,
 114                                   DIRTY_MEMORY_VGA);
 115     ret |= memory_region_get_dirty(&s->vram_mem, page24, TARGET_PAGE_SIZE * 4,
 116                                    DIRTY_MEMORY_VGA);
 117     ret |= memory_region_get_dirty(&s->vram_mem, cpage, TARGET_PAGE_SIZE * 4,
 118                                    DIRTY_MEMORY_VGA);
 119     return ret;
 120 }
 121
 122 static inline void tcx24_reset_dirty(TCXState *ts, ram_addr_t page_min,
 123                                ram_addr_t page_max, ram_addr_t page24,
 124                               ram_addr_t cpage)
 125 {
 126     memory_region_reset_dirty(&ts->vram_mem,
 127                               page_min,
 128                               (page_max - page_min) + TARGET_PAGE_SIZE,
 129                               DIRTY_MEMORY_VGA);
 130     memory_region_reset_dirty(&ts->vram_mem,
 131                               page24 + page_min * 4,
 132                               (page_max - page_min) * 4 + TARGET_PAGE_SIZE,
 133                               DIRTY_MEMORY_VGA);
 134     memory_region_reset_dirty(&ts->vram_mem,
 135                               cpage + page_min * 4,
 136                               (page_max - page_min) * 4 + TARGET_PAGE_SIZE,
 137                               DIRTY_MEMORY_VGA);
 138 }
 139
 140 static void update_palette_entries(TCXState *s, int start, int end)
 141 {
 142     DisplaySurface *surface = qemu_console_surface(s->con);
 143     int i;
 144
 145     for (i = start; i < end; i++) {
 146         switch (surface_bits_per_pixel(surface)) {
 147         default:
 148         case 8:
 149             s->palette[i] = rgb_to_pixel8(s->r[i], s->g[i], s->b[i]);
 150             break;
 151         case 15:
 152             s->palette[i] = rgb_to_pixel15(s->r[i], s->g[i], s->b[i]);
 153             break;
 154         case 16:
 155             s->palette[i] = rgb_to_pixel16(s->r[i], s->g[i], s->b[i]);
 156             break;
 157         case 32:
 158             if (is_surface_bgr(surface)) {
 159                 s->palette[i] = rgb_to_pixel32bgr(s->r[i], s->g[i], s->b[i]);
 160             } else {
 161                 s->palette[i] = rgb_to_pixel32(s->r[i], s->g[i], s->b[i]);
 162             }
 163             break;
 164         }
 165     }
 166     tcx_set_dirty(s, 0, memory_region_size(&s->vram_mem));
 167 }
 168
 169 static void tcx_draw_line32(TCXState *s1, uint8_t *d,
 170                             const uint8_t *s, int width)
 171 {
 172     int x;
 173     uint8_t val;
 174     uint32_t *p = (uint32_t *)d;
 175
 176     for (x = 0; x < width; x++) {
 177         val = *s++;
 178         *p++ = s1->palette[val];
 179     }
 180 }
 181
 182 static void tcx_draw_line16(TCXState *s1, uint8_t *d,
 183                             const uint8_t *s, int width)
 184 {
 185     int x;
 186     uint8_t val;
 187     uint16_t *p = (uint16_t *)d;
 188
 189     for (x = 0; x < width; x++) {
 190         val = *s++;
 191         *p++ = s1->palette[val];
 192     }
 193 }
 194
 195 static void tcx_draw_line8(TCXState *s1, uint8_t *d,
 196                            const uint8_t *s, int width)
 197 {
 198     int x;
 199     uint8_t val;
 200
 201     for(x = 0; x < width; x++) {
 202         val = *s++;
 203         *d++ = s1->palette[val];
 204     }
 205 }
 206
 207 static void tcx_draw_cursor32(TCXState *s1, uint8_t *d,
 208                               int y, int width)
 209 {
 210     int x, len;
 211     uint32_t mask, bits;
 212     uint32_t *p = (uint32_t *)d;
 213
 214     y = y - s1->cursy;
 215     mask = s1->cursmask[y];
 216     bits = s1->cursbits[y];
 217     len = MIN(width - s1->cursx, 32);
 218     p = &p[s1->cursx];
 219     for (x = 0; x < len; x++) {
 220         if (mask & 0x80000000) {
 221             if (bits & 0x80000000) {
 222                 *p = s1->palette[259];
 223             } else {
 224                 *p = s1->palette[258];
 225             }
 226         }
 227         p++;
 228         mask <<= 1;
 229         bits <<= 1;
 230     }
 231 }
 232
 233 static void tcx_draw_cursor16(TCXState *s1, uint8_t *d,
 234                               int y, int width)
 235 {
 236     int x, len;
 237     uint32_t mask, bits;
 238     uint16_t *p = (uint16_t *)d;
 239
 240     y = y - s1->cursy;
 241     mask = s1->cursmask[y];
 242     bits = s1->cursbits[y];
 243     len = MIN(width - s1->cursx, 32);
 244     p = &p[s1->cursx];
 245     for (x = 0; x < len; x++) {
 246         if (mask & 0x80000000) {
 247             if (bits & 0x80000000) {
 248                 *p = s1->palette[259];
 249             } else {
 250                 *p = s1->palette[258];
 251             }
 252         }
 253         p++;
 254         mask <<= 1;
 255         bits <<= 1;
 256     }
 257 }
 258
 259 static void tcx_draw_cursor8(TCXState *s1, uint8_t *d,
 260                               int y, int width)
 261 {
 262     int x, len;
 263     uint32_t mask, bits;
 264
 265     y = y - s1->cursy;
 266     mask = s1->cursmask[y];
 267     bits = s1->cursbits[y];
 268     len = MIN(width - s1->cursx, 32);
 269     d = &d[s1->cursx];
 270     for (x = 0; x < len; x++) {
 271         if (mask & 0x80000000) {
 272             if (bits & 0x80000000) {
 273                 *d = s1->palette[259];
 274             } else {
 275                 *d = s1->palette[258];
 276             }
 277         }
 278         d++;
 279         mask <<= 1;
 280         bits <<= 1;
 281     }
 282 }
 283
 284 /*
 285   XXX Could be much more optimal:
 286   * detect if line/page/whole screen is in 24 bit mode
 287   * if destination is also BGR, use memcpy
 288   */
 289 static inline void tcx24_draw_line32(TCXState *s1, uint8_t *d,
 290                                      const uint8_t *s, int width,
 291                                      const uint32_t *cplane,
 292                                      const uint32_t *s24)
 293 {
 294     DisplaySurface *surface = qemu_console_surface(s1->con);
 295     int x, bgr, r, g, b;
 296     uint8_t val, *p8;
 297     uint32_t *p = (uint32_t *)d;
 298     uint32_t dval;
 299     bgr = is_surface_bgr(surface);
 300     for(x = 0; x < width; x++, s++, s24++) {
 301         if (be32_to_cpu(*cplane) & 0x03000000) {
 302             /* 24-bit direct, BGR order */
 303             p8 = (uint8_t *)s24;
 304             p8++;
 305             b = *p8++;
 306             g = *p8++;
 307             r = *p8;
 308             if (bgr)
 309                 dval = rgb_to_pixel32bgr(r, g, b);
 310             else
 311                 dval = rgb_to_pixel32(r, g, b);
 312         } else {
 313             /* 8-bit pseudocolor */
 314             val = *s;
 315             dval = s1->palette[val];
 316         }
 317         *p++ = dval;
 318         cplane++;
 319     }
 320 }
 321
 322 /* Fixed line length 1024 allows us to do nice tricks not possible on
 323    VGA... */
 324
 325 static void tcx_update_display(void *opaque)
 326 {
 327     TCXState *ts = opaque;
 328     DisplaySurface *surface = qemu_console_surface(ts->con);
 329     ram_addr_t page, page_min, page_max;
 330     int y, y_start, dd, ds;
 331     uint8_t *d, *s;
 332     void (*f)(TCXState *s1, uint8_t *dst, const uint8_t *src, int width);
 333     void (*fc)(TCXState *s1, uint8_t *dst, int y, int width);
 334
 335     if (surface_bits_per_pixel(surface) == 0) {
 336         return;
 337     }
 338
 339     page = 0;
 340     y_start = -1;
 341     page_min = -1;
 342     page_max = 0;
 343     d = surface_data(surface);
 344     s = ts->vram;
 345     dd = surface_stride(surface);
 346     ds = 1024;
 347
 348     switch (surface_bits_per_pixel(surface)) {
 349     case 32:
 350         f = tcx_draw_line32;
 351         fc = tcx_draw_cursor32;
 352         break;
 353     case 15:
 354     case 16:
 355         f = tcx_draw_line16;
 356         fc = tcx_draw_cursor16;
 357         break;
 358     default:
 359     case 8:
 360         f = tcx_draw_line8;
 361         fc = tcx_draw_cursor8;
 362         break;
 363     case 0:
 364         return;
 365     }
 366
 367     memory_region_sync_dirty_bitmap(&ts->vram_mem);
 368     for (y = 0; y < ts->height; page += TARGET_PAGE_SIZE) {
 369         if (memory_region_get_dirty(&ts->vram_mem, page, TARGET_PAGE_SIZE,
 370                                     DIRTY_MEMORY_VGA)) {
 371             if (y_start < 0)
 372                 y_start = y;
 373             if (page < page_min)
 374                 page_min = page;
 375             if (page > page_max)
 376                 page_max = page;
 377
 378             f(ts, d, s, ts->width);
 379             if (y >= ts->cursy && y < ts->cursy + 32 && ts->cursx < ts->width) {
 380                 fc(ts, d, y, ts->width);
 381             }
 382             d += dd;
 383             s += ds;
 384             y++;
 385
 386             f(ts, d, s, ts->width);
 387             if (y >= ts->cursy && y < ts->cursy + 32 && ts->cursx < ts->width) {
 388                 fc(ts, d, y, ts->width);
 389             }
 390             d += dd;
 391             s += ds;
 392             y++;
 393
 394             f(ts, d, s, ts->width);
 395             if (y >= ts->cursy && y < ts->cursy + 32 && ts->cursx < ts->width) {
 396                 fc(ts, d, y, ts->width);
 397             }
 398             d += dd;
 399             s += ds;
 400             y++;
 401
 402             f(ts, d, s, ts->width);
 403             if (y >= ts->cursy && y < ts->cursy + 32 && ts->cursx < ts->width) {
 404                 fc(ts, d, y, ts->width);
 405             }
 406             d += dd;
 407             s += ds;
 408             y++;
 409         } else {
 410             if (y_start >= 0) {
 411                 /* flush to display */
 412                 dpy_gfx_update(ts->con, 0, y_start,
 413                                ts->width, y - y_start);
 414                 y_start = -1;
 415             }
 416             d += dd * 4;
 417             s += ds * 4;
 418             y += 4;
 419         }
 420     }
 421     if (y_start >= 0) {
 422         /* flush to display */
 423         dpy_gfx_update(ts->con, 0, y_start,
 424                        ts->width, y - y_start);
 425     }
 426     /* reset modified pages */
 427     if (page_max >= page_min) {
 428         memory_region_reset_dirty(&ts->vram_mem,
 429                                   page_min,
 430                                   (page_max - page_min) + TARGET_PAGE_SIZE,
 431                                   DIRTY_MEMORY_VGA);
 432     }
 433 }
 434
 435 static void tcx24_update_display(void *opaque)
 436 {
 437     TCXState *ts = opaque;
 438     DisplaySurface *surface = qemu_console_surface(ts->con);
 439     ram_addr_t page, page_min, page_max, cpage, page24;
 440     int y, y_start, dd, ds;
 441     uint8_t *d, *s;
 442     uint32_t *cptr, *s24;
 443
 444     if (surface_bits_per_pixel(surface) != 32) {
 445             return;
 446     }
 447
 448     page = 0;
 449     page24 = ts->vram24_offset;
 450     cpage = ts->cplane_offset;
 451     y_start = -1;
 452     page_min = -1;
 453     page_max = 0;
 454     d = surface_data(surface);
 455     s = ts->vram;
 456     s24 = ts->vram24;
 457     cptr = ts->cplane;
 458     dd = surface_stride(surface);
 459     ds = 1024;
 460
 461     memory_region_sync_dirty_bitmap(&ts->vram_mem);
 462     for (y = 0; y < ts->height; page += TARGET_PAGE_SIZE,
 463             page24 += TARGET_PAGE_SIZE, cpage += TARGET_PAGE_SIZE) {
 464         if (tcx24_check_dirty(ts, page, page24, cpage)) {
 465             if (y_start < 0)
 466                 y_start = y;
 467             if (page < page_min)
 468                 page_min = page;
 469             if (page > page_max)
 470                 page_max = page;
 471             tcx24_draw_line32(ts, d, s, ts->width, cptr, s24);
 472             if (y >= ts->cursy && y < ts->cursy+32 && ts->cursx < ts->width) {
 473                 tcx_draw_cursor32(ts, d, y, ts->width);
 474             }
 475             d += dd;
 476             s += ds;
 477             cptr += ds;
 478             s24 += ds;
 479             y++;
 480             tcx24_draw_line32(ts, d, s, ts->width, cptr, s24);
 481             if (y >= ts->cursy && y < ts->cursy+32 && ts->cursx < ts->width) {
 482                 tcx_draw_cursor32(ts, d, y, ts->width);
 483             }
 484             d += dd;
 485             s += ds;
 486             cptr += ds;
 487             s24 += ds;
 488             y++;
 489             tcx24_draw_line32(ts, d, s, ts->width, cptr, s24);
 490             if (y >= ts->cursy && y < ts->cursy+32 && ts->cursx < ts->width) {
 491                 tcx_draw_cursor32(ts, d, y, ts->width);
 492             }
 493             d += dd;
 494             s += ds;
 495             cptr += ds;
 496             s24 += ds;
 497             y++;
 498             tcx24_draw_line32(ts, d, s, ts->width, cptr, s24);
 499             if (y >= ts->cursy && y < ts->cursy+32 && ts->cursx < ts->width) {
 500                 tcx_draw_cursor32(ts, d, y, ts->width);
 501             }
 502             d += dd;
 503             s += ds;
 504             cptr += ds;
 505             s24 += ds;
 506             y++;
 507         } else {
 508             if (y_start >= 0) {
 509                 /* flush to display */
 510                 dpy_gfx_update(ts->con, 0, y_start,
 511                                ts->width, y - y_start);
 512                 y_start = -1;
 513             }
 514             d += dd * 4;
 515             s += ds * 4;
 516             cptr += ds * 4;
 517             s24 += ds * 4;
 518             y += 4;
 519         }
 520     }
 521     if (y_start >= 0) {
 522         /* flush to display */
 523         dpy_gfx_update(ts->con, 0, y_start,
 524                        ts->width, y - y_start);
 525     }
 526     /* reset modified pages */
 527     if (page_max >= page_min) {
 528         tcx24_reset_dirty(ts, page_min, page_max, page24, cpage);
 529     }
 530 }
 531
 532 static void tcx_invalidate_display(void *opaque)
 533 {
 534     TCXState *s = opaque;
 535
 536     tcx_set_dirty(s, 0, memory_region_size(&s->vram_mem));
 537     qemu_console_resize(s->con, s->width, s->height);
 538 }
 539
 540 static void tcx24_invalidate_display(void *opaque)
 541 {
 542     TCXState *s = opaque;
 543
 544     tcx_set_dirty(s, 0, memory_region_size(&s->vram_mem));
 545     qemu_console_resize(s->con, s->width, s->height);
 546 }
 547
 548 static int vmstate_tcx_post_load(void *opaque, int version_id)
 549 {
 550     TCXState *s = opaque;
 551
 552     update_palette_entries(s, 0, 256);
 553     tcx_set_dirty(s, 0, memory_region_size(&s->vram_mem));
 554     return 0;
 555 }
 556
 557 static const VMStateDescription vmstate_tcx = {
 558     .name ="tcx",
 559     .version_id = 4,
 560     .minimum_version_id = 4,
 561     .post_load = vmstate_tcx_post_load,
 562     .fields = (VMStateField[]) {
 563         VMSTATE_UINT16(height, TCXState),
 564         VMSTATE_UINT16(width, TCXState),
 565         VMSTATE_UINT16(depth, TCXState),
 566         VMSTATE_BUFFER(r, TCXState),
 567         VMSTATE_BUFFER(g, TCXState),
 568         VMSTATE_BUFFER(b, TCXState),
 569         VMSTATE_UINT8(dac_index, TCXState),
 570         VMSTATE_UINT8(dac_state, TCXState),
 571         VMSTATE_END_OF_LIST()
 572     }
 573 };
 574
 575 static void tcx_reset(DeviceState *d)
 576 {
 577     TCXState *s = TCX(d);
 578
 579     /* Initialize palette */
 580     memset(s->r, 0, 260);
 581     memset(s->g, 0, 260);
 582     memset(s->b, 0, 260);
 583     s->r[255] = s->g[255] = s->b[255] = 255;
 584     s->r[256] = s->g[256] = s->b[256] = 255;
 585     s->r[258] = s->g[258] = s->b[258] = 255;
 586     update_palette_entries(s, 0, 260);
 587     memset(s->vram, 0, MAXX*MAXY);
 588     memory_region_reset_dirty(&s->vram_mem, 0, MAXX * MAXY * (1 + 4 + 4),
 589                               DIRTY_MEMORY_VGA);
 590     s->dac_index = 0;
 591     s->dac_state = 0;
 592     s->cursx = 0xf000; /* Put cursor off screen */
 593     s->cursy = 0xf000;
 594 }
 595
 596 static uint64_t tcx_dac_readl(void *opaque, hwaddr addr,
 597                               unsigned size)
 598 {
 599     TCXState *s = opaque;
 600     uint32_t val = 0;
 601
 602     switch (s->dac_state) {
 603     case 0:
 604         val = s->r[s->dac_index] << 24;
 605         s->dac_state++;
 606         break;
 607     case 1:
 608         val = s->g[s->dac_index] << 24;
 609         s->dac_state++;
 610         break;
 611     case 2:
 612         val = s->b[s->dac_index] << 24;
 613         s->dac_index = (s->dac_index + 1) & 0xff; /* Index autoincrement */
 614     default:
 615         s->dac_state = 0;
 616         break;
 617     }
 618
 619     return val;
 620 }
 621
 622 static void tcx_dac_writel(void *opaque, hwaddr addr, uint64_t val,
 623                            unsigned size)
 624 {
 625     TCXState *s = opaque;
 626     unsigned index;
 627
 628     switch (addr) {
 629     case 0: /* Address */
 630         s->dac_index = val >> 24;
 631         s->dac_state = 0;
 632         break;
 633     case 4:  /* Pixel colours */
 634     case 12: /* Overlay (cursor) colours */
 635         if (addr & 8) {
 636             index = (s->dac_index & 3) + 256;
 637         } else {
 638             index = s->dac_index;
 639         }
 640         switch (s->dac_state) {
 641         case 0:
 642             s->r[index] = val >> 24;
 643             update_palette_entries(s, index, index + 1);
 644             s->dac_state++;
 645             break;
 646         case 1:
 647             s->g[index] = val >> 24;
 648             update_palette_entries(s, index, index + 1);
 649             s->dac_state++;
 650             break;
 651         case 2:
 652             s->b[index] = val >> 24;
 653             update_palette_entries(s, index, index + 1);
 654             s->dac_index = (s->dac_index + 1) & 0xff; /* Index autoincrement */
 655         default:
 656             s->dac_state = 0;
 657             break;
 658         }
 659         break;
 660     default: /* Control registers */
 661         break;
 662     }
 663 }
 664
 665 static const MemoryRegionOps tcx_dac_ops = {
 666     .read = tcx_dac_readl,
 667     .write = tcx_dac_writel,
 668     .endianness = DEVICE_NATIVE_ENDIAN,
 669     .valid = {
 670         .min_access_size = 4,
 671         .max_access_size = 4,
 672     },
 673 };
 674
 675 static uint64_t tcx_stip_readl(void *opaque, hwaddr addr,
 676                                unsigned size)
 677 {
 678     return 0;
 679 }
 680
 681 static void tcx_stip_writel(void *opaque, hwaddr addr,
 682                             uint64_t val, unsigned size)
 683 {
 684     TCXState *s = opaque;
 685     int i;
 686     uint32_t col;
 687
 688     if (!(addr & 4)) {
 689         s->tmpblit = val;
 690     } else {
 691         addr = (addr >> 3) & 0xfffff;
 692         col = cpu_to_be32(s->tmpblit);
 693         if (s->depth == 24) {
 694             for (i = 0; i < 32; i++)  {
 695                 if (val & 0x80000000) {
 696                     s->vram[addr + i] = s->tmpblit;
 697                     s->vram24[addr + i] = col;
 698                 }
 699                 val <<= 1;
 700             }
 701         } else {
 702             for (i = 0; i < 32; i++)  {
 703                 if (val & 0x80000000) {
 704                     s->vram[addr + i] = s->tmpblit;
 705                 }
 706                 val <<= 1;
 707             }
 708         }
 709         memory_region_set_dirty(&s->vram_mem, addr, 32);
 710     }
 711 }
 712
 713 static void tcx_rstip_writel(void *opaque, hwaddr addr,
 714                              uint64_t val, unsigned size)
 715 {
 716     TCXState *s = opaque;
 717     int i;
 718     uint32_t col;
 719
 720     if (!(addr & 4)) {
 721         s->tmpblit = val;
 722     } else {
 723         addr = (addr >> 3) & 0xfffff;
 724         col = cpu_to_be32(s->tmpblit);
 725         if (s->depth == 24) {
 726             for (i = 0; i < 32; i++) {
 727                 if (val & 0x80000000) {
 728                     s->vram[addr + i] = s->tmpblit;
 729                     s->vram24[addr + i] = col;
 730                     s->cplane[addr + i] = col;
 731                 }
 732                 val <<= 1;
 733             }
 734         } else {
 735             for (i = 0; i < 32; i++)  {
 736                 if (val & 0x80000000) {
 737                     s->vram[addr + i] = s->tmpblit;
 738                 }
 739                 val <<= 1;
 740             }
 741         }
 742         memory_region_set_dirty(&s->vram_mem, addr, 32);
 743     }
 744 }
 745
 746 static const MemoryRegionOps tcx_stip_ops = {
 747     .read = tcx_stip_readl,
 748     .write = tcx_stip_writel,
 749     .endianness = DEVICE_NATIVE_ENDIAN,
 750     .valid = {
 751         .min_access_size = 4,
 752         .max_access_size = 4,
 753     },
 754 };
 755
 756 static const MemoryRegionOps tcx_rstip_ops = {
 757     .read = tcx_stip_readl,
 758     .write = tcx_rstip_writel,
 759     .endianness = DEVICE_NATIVE_ENDIAN,
 760     .valid = {
 761         .min_access_size = 4,
 762         .max_access_size = 4,
 763     },
 764 };
 765
 766 static uint64_t tcx_blit_readl(void *opaque, hwaddr addr,
 767                                unsigned size)
 768 {
 769     return 0;
 770 }
 771
 772 static void tcx_blit_writel(void *opaque, hwaddr addr,
 773                             uint64_t val, unsigned size)
 774 {
 775     TCXState *s = opaque;
 776     uint32_t adsr, len;
 777     int i;
 778
 779     if (!(addr & 4)) {
 780         s->tmpblit = val;
 781     } else {
 782         addr = (addr >> 3) & 0xfffff;
 783         adsr = val & 0xffffff;
 784         len = ((val >> 24) & 0x1f) + 1;
 785         if (adsr == 0xffffff) {
 786             memset(&s->vram[addr], s->tmpblit, len);
 787             if (s->depth == 24) {
 788                 val = s->tmpblit & 0xffffff;
 789                 val = cpu_to_be32(val);
 790                 for (i = 0; i < len; i++) {
 791                     s->vram24[addr + i] = val;
 792                 }
 793             }
 794         } else {
 795             memcpy(&s->vram[addr], &s->vram[adsr], len);
 796             if (s->depth == 24) {
 797                 memcpy(&s->vram24[addr], &s->vram24[adsr], len * 4);
 798             }
 799         }
 800         memory_region_set_dirty(&s->vram_mem, addr, len);
 801     }
 802 }
 803
 804 static void tcx_rblit_writel(void *opaque, hwaddr addr,
 805                          uint64_t val, unsigned size)
 806 {
 807     TCXState *s = opaque;
 808     uint32_t adsr, len;
 809     int i;
 810
 811     if (!(addr & 4)) {
 812         s->tmpblit = val;
 813     } else {
 814         addr = (addr >> 3) & 0xfffff;
 815         adsr = val & 0xffffff;
 816         len = ((val >> 24) & 0x1f) + 1;
 817         if (adsr == 0xffffff) {
 818             memset(&s->vram[addr], s->tmpblit, len);
 819             if (s->depth == 24) {
 820                 val = s->tmpblit & 0xffffff;
 821                 val = cpu_to_be32(val);
 822                 for (i = 0; i < len; i++) {
 823                     s->vram24[addr + i] = val;
 824                     s->cplane[addr + i] = val;
 825                 }
 826             }
 827         } else {
 828             memcpy(&s->vram[addr], &s->vram[adsr], len);
 829             if (s->depth == 24) {
 830                 memcpy(&s->vram24[addr], &s->vram24[adsr], len * 4);
 831                 memcpy(&s->cplane[addr], &s->cplane[adsr], len * 4);
 832             }
 833         }
 834         memory_region_set_dirty(&s->vram_mem, addr, len);
 835     }
 836 }
 837
 838 static const MemoryRegionOps tcx_blit_ops = {
 839     .read = tcx_blit_readl,
 840     .write = tcx_blit_writel,
 841     .endianness = DEVICE_NATIVE_ENDIAN,
 842     .valid = {
 843         .min_access_size = 4,
 844         .max_access_size = 4,
 845     },
 846 };
 847
 848 static const MemoryRegionOps tcx_rblit_ops = {
 849     .read = tcx_blit_readl,
 850     .write = tcx_rblit_writel,
 851     .endianness = DEVICE_NATIVE_ENDIAN,
 852     .valid = {
 853         .min_access_size = 4,
 854         .max_access_size = 4,
 855     },
 856 };
 857
 858 static void tcx_invalidate_cursor_position(TCXState *s)
 859 {
 860     int ymin, ymax, start, end;
 861
 862     /* invalidate only near the cursor */
 863     ymin = s->cursy;
 864     if (ymin >= s->height) {
 865         return;
 866     }
 867     ymax = MIN(s->height, ymin + 32);
 868     start = ymin * 1024;
 869     end   = ymax * 1024;
 870
 871     memory_region_set_dirty(&s->vram_mem, start, end-start);
 872 }
 873
 874 static uint64_t tcx_thc_readl(void *opaque, hwaddr addr,
 875                             unsigned size)
 876 {
 877     TCXState *s = opaque;
 878     uint64_t val;
 879
 880     if (addr == TCX_THC_MISC) {
 881         val = s->thcmisc | 0x02000000;
 882     } else {
 883         val = 0;
 884     }
 885     return val;
 886 }
 887
 888 static void tcx_thc_writel(void *opaque, hwaddr addr,
 889                          uint64_t val, unsigned size)
 890 {
 891     TCXState *s = opaque;
 892
 893     if (addr == TCX_THC_CURSXY) {
 894         tcx_invalidate_cursor_position(s);
 895         s->cursx = val >> 16;
 896         s->cursy = val;
 897         tcx_invalidate_cursor_position(s);
 898     } else if (addr >= TCX_THC_CURSMASK && addr < TCX_THC_CURSMASK + 128) {
 899         s->cursmask[(addr - TCX_THC_CURSMASK) >> 2] = val;
 900         tcx_invalidate_cursor_position(s);
 901     } else if (addr >= TCX_THC_CURSBITS && addr < TCX_THC_CURSBITS + 128) {
 902         s->cursbits[(addr - TCX_THC_CURSBITS) >> 2] = val;
 903         tcx_invalidate_cursor_position(s);
 904     } else if (addr == TCX_THC_MISC) {
 905         s->thcmisc = val;
 906     }
 907
 908 }
 909
 910 static const MemoryRegionOps tcx_thc_ops = {
 911     .read = tcx_thc_readl,
 912     .write = tcx_thc_writel,
 913     .endianness = DEVICE_NATIVE_ENDIAN,
 914     .valid = {
 915         .min_access_size = 4,
 916         .max_access_size = 4,
 917     },
 918 };
 919
 920 static uint64_t tcx_dummy_readl(void *opaque, hwaddr addr,
 921                             unsigned size)
 922 {
 923     return 0;
 924 }
 925
 926 static void tcx_dummy_writel(void *opaque, hwaddr addr,
 927                          uint64_t val, unsigned size)
 928 {
 929     return;
 930 }
 931
 932 static const MemoryRegionOps tcx_dummy_ops = {
 933     .read = tcx_dummy_readl,
 934     .write = tcx_dummy_writel,
 935     .endianness = DEVICE_NATIVE_ENDIAN,
 936     .valid = {
 937         .min_access_size = 4,
 938         .max_access_size = 4,
 939     },
 940 };
 941
 942 static const GraphicHwOps tcx_ops = {
 943     .invalidate = tcx_invalidate_display,
 944     .gfx_update = tcx_update_display,
 945 };
 946
 947 static const GraphicHwOps tcx24_ops = {
 948     .invalidate = tcx24_invalidate_display,
 949     .gfx_update = tcx24_update_display,
 950 };
 951
 952 static void tcx_initfn(Object *obj)
 953 {
 954     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 955     TCXState *s = TCX(obj);
 956
 957     memory_region_init_ram(&s->rom, obj, "tcx.prom", FCODE_MAX_ROM_SIZE,
 958                            &error_fatal);
 959     memory_region_set_readonly(&s->rom, true);
 960     sysbus_init_mmio(sbd, &s->rom);
 961
 962     /* 2/STIP : Stippler */
 963     memory_region_init_io(&s->stip, obj, &tcx_stip_ops, s, "tcx.stip",
 964                           TCX_STIP_NREGS);
 965     sysbus_init_mmio(sbd, &s->stip);
 966
 967     /* 3/BLIT : Blitter */
 968     memory_region_init_io(&s->blit, obj, &tcx_blit_ops, s, "tcx.blit",
 969                           TCX_BLIT_NREGS);
 970     sysbus_init_mmio(sbd, &s->blit);
 971
 972     /* 5/RSTIP : Raw Stippler */
 973     memory_region_init_io(&s->rstip, obj, &tcx_rstip_ops, s, "tcx.rstip",
 974                           TCX_RSTIP_NREGS);
 975     sysbus_init_mmio(sbd, &s->rstip);
 976
 977     /* 6/RBLIT : Raw Blitter */
 978     memory_region_init_io(&s->rblit, obj, &tcx_rblit_ops, s, "tcx.rblit",
 979                           TCX_RBLIT_NREGS);
 980     sysbus_init_mmio(sbd, &s->rblit);
 981
 982     /* 7/TEC : ??? */
 983     memory_region_init_io(&s->tec, obj, &tcx_dummy_ops, s, "tcx.tec",
 984                           TCX_TEC_NREGS);
 985     sysbus_init_mmio(sbd, &s->tec);
 986
 987     /* 8/CMAP : DAC */
 988     memory_region_init_io(&s->dac, obj, &tcx_dac_ops, s, "tcx.dac",
 989                           TCX_DAC_NREGS);
 990     sysbus_init_mmio(sbd, &s->dac);
 991
 992     /* 9/THC : Cursor */
 993     memory_region_init_io(&s->thc, obj, &tcx_thc_ops, s, "tcx.thc",
 994                           TCX_THC_NREGS);
 995     sysbus_init_mmio(sbd, &s->thc);
 996
 997     /* 11/DHC : ??? */
 998     memory_region_init_io(&s->dhc, obj, &tcx_dummy_ops, s, "tcx.dhc",
 999                           TCX_DHC_NREGS);
1000     sysbus_init_mmio(sbd, &s->dhc);
1001
1002     /* 12/ALT : ??? */
1003     memory_region_init_io(&s->alt, obj, &tcx_dummy_ops, s, "tcx.alt",
1004                           TCX_ALT_NREGS);
1005     sysbus_init_mmio(sbd, &s->alt);
1006 }
1007
1008 static void tcx_realizefn(DeviceState *dev, Error **errp)
1009 {
1010     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
1011     TCXState *s = TCX(dev);
1012     ram_addr_t vram_offset = 0;
1013     int size, ret;
1014     uint8_t *vram_base;
1015     char *fcode_filename;
1016
1017     memory_region_init_ram(&s->vram_mem, OBJECT(s), "tcx.vram",
1018                            s->vram_size * (1 + 4 + 4), &error_fatal);
1019     vmstate_register_ram_global(&s->vram_mem);
1020     memory_region_set_log(&s->vram_mem, true, DIRTY_MEMORY_VGA);
1021     vram_base = memory_region_get_ram_ptr(&s->vram_mem);
1022
1023     /* 10/ROM : FCode ROM */
1024     vmstate_register_ram_global(&s->rom);
1025     fcode_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, TCX_ROM_FILE);
1026     if (fcode_filename) {
1027         ret = load_image_targphys(fcode_filename, s->prom_addr,
1028                                   FCODE_MAX_ROM_SIZE);
1029         g_free(fcode_filename);
1030         if (ret < 0 || ret > FCODE_MAX_ROM_SIZE) {
1031             error_report("tcx: could not load prom '%s'", TCX_ROM_FILE);
1032         }
1033     }
1034
1035     /* 0/DFB8 : 8-bit plane */
1036     s->vram = vram_base;
1037     size = s->vram_size;
1038     memory_region_init_alias(&s->vram_8bit, OBJECT(s), "tcx.vram.8bit",
1039                              &s->vram_mem, vram_offset, size);
1040     sysbus_init_mmio(sbd, &s->vram_8bit);
1041     vram_offset += size;
1042     vram_base += size;
1043
1044     /* 1/DFB24 : 24bit plane */
1045     size = s->vram_size * 4;
1046     s->vram24 = (uint32_t *)vram_base;
1047     s->vram24_offset = vram_offset;
1048     memory_region_init_alias(&s->vram_24bit, OBJECT(s), "tcx.vram.24bit",
1049                              &s->vram_mem, vram_offset, size);
1050     sysbus_init_mmio(sbd, &s->vram_24bit);
1051     vram_offset += size;
1052     vram_base += size;
1053
1054     /* 4/RDFB32 : Raw Framebuffer */
1055     size = s->vram_size * 4;
1056     s->cplane = (uint32_t *)vram_base;
1057     s->cplane_offset = vram_offset;
1058     memory_region_init_alias(&s->vram_cplane, OBJECT(s), "tcx.vram.cplane",
1059                              &s->vram_mem, vram_offset, size);
1060     sysbus_init_mmio(sbd, &s->vram_cplane);
1061
1062     /* 9/THC24bits : NetBSD writes here even with 8-bit display: dummy */
1063     if (s->depth == 8) {
1064         memory_region_init_io(&s->thc24, OBJECT(s), &tcx_dummy_ops, s,
1065                               "tcx.thc24", TCX_THC_NREGS);
1066         sysbus_init_mmio(sbd, &s->thc24);
1067     }
1068
1069     sysbus_init_irq(sbd, &s->irq);
1070
1071     if (s->depth == 8) {
1072         s->con = graphic_console_init(DEVICE(dev), 0, &tcx_ops, s);
1073     } else {
1074         s->con = graphic_console_init(DEVICE(dev), 0, &tcx24_ops, s);
1075     }
1076     s->thcmisc = 0;
1077
1078     qemu_console_resize(s->con, s->width, s->height);
1079 }
1080
1081 static Property tcx_properties[] = {
1082     DEFINE_PROP_UINT32("vram_size", TCXState, vram_size, -1),
1083     DEFINE_PROP_UINT16("width",    TCXState, width,     -1),
1084     DEFINE_PROP_UINT16("height",   TCXState, height,    -1),
1085     DEFINE_PROP_UINT16("depth",    TCXState, depth,     -1),
1086     DEFINE_PROP_UINT64("prom_addr", TCXState, prom_addr, -1),
1087     DEFINE_PROP_END_OF_LIST(),
1088 };
1089
1090 static void tcx_class_init(ObjectClass *klass, void *data)
1091 {
1092     DeviceClass *dc = DEVICE_CLASS(klass);
1093
1094     dc->realize = tcx_realizefn;
1095     dc->reset = tcx_reset;
1096     dc->vmsd = &vmstate_tcx;
1097     dc->props = tcx_properties;
1098 }
1099
1100 static const TypeInfo tcx_info = {
1101     .name          = TYPE_TCX,
1102     .parent        = TYPE_SYS_BUS_DEVICE,
1103     .instance_size = sizeof(TCXState),
1104     .instance_init = tcx_initfn,
1105     .class_init    = tcx_class_init,
1106 };
1107
1108 static void tcx_register_types(void)
1109 {
1110     type_register_static(&tcx_info);
1111 }
1112
1113 type_init(tcx_register_types)