4 * This code is licensed under the GNU GPL v2 or later.
6 * SPDX-License-Identifier: GPL-2.0-or-later
9 #include "qemu/osdep.h"
13 #include "internals.h"
14 #include "cpu-features.h"
15 #include "exec/helper-proto.h"
16 #include "qemu/main-loop.h"
17 #include "qemu/timer.h"
18 #include "qemu/bitops.h"
19 #include "qemu/crc32c.h"
20 #include "qemu/qemu-print.h"
21 #include "exec/exec-all.h"
22 #include <zlib.h> /* For crc32 */
24 #include "sysemu/cpu-timers.h"
25 #include "sysemu/kvm.h"
26 #include "sysemu/tcg.h"
27 #include "qapi/error.h"
28 #include "qemu/guest-random.h"
30 #include "semihosting/common-semi.h"
33 #include "target/arm/gtimer.h"
35 #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */
37 static void switch_mode(CPUARMState
*env
, int mode
);
39 static uint64_t raw_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
41 assert(ri
->fieldoffset
);
42 if (cpreg_field_is_64bit(ri
)) {
43 return CPREG_FIELD64(env
, ri
);
45 return CPREG_FIELD32(env
, ri
);
49 void raw_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
51 assert(ri
->fieldoffset
);
52 if (cpreg_field_is_64bit(ri
)) {
53 CPREG_FIELD64(env
, ri
) = value
;
55 CPREG_FIELD32(env
, ri
) = value
;
59 static void *raw_ptr(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
61 return (char *)env
+ ri
->fieldoffset
;
64 uint64_t read_raw_cp_reg(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
66 /* Raw read of a coprocessor register (as needed for migration, etc). */
67 if (ri
->type
& ARM_CP_CONST
) {
68 return ri
->resetvalue
;
69 } else if (ri
->raw_readfn
) {
70 return ri
->raw_readfn(env
, ri
);
71 } else if (ri
->readfn
) {
72 return ri
->readfn(env
, ri
);
74 return raw_read(env
, ri
);
78 static void write_raw_cp_reg(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
82 * Raw write of a coprocessor register (as needed for migration, etc).
83 * Note that constant registers are treated as write-ignored; the
84 * caller should check for success by whether a readback gives the
87 if (ri
->type
& ARM_CP_CONST
) {
89 } else if (ri
->raw_writefn
) {
90 ri
->raw_writefn(env
, ri
, v
);
91 } else if (ri
->writefn
) {
92 ri
->writefn(env
, ri
, v
);
94 raw_write(env
, ri
, v
);
98 static bool raw_accessors_invalid(const ARMCPRegInfo
*ri
)
101 * Return true if the regdef would cause an assertion if you called
102 * read_raw_cp_reg() or write_raw_cp_reg() on it (ie if it is a
103 * program bug for it not to have the NO_RAW flag).
104 * NB that returning false here doesn't necessarily mean that calling
105 * read/write_raw_cp_reg() is safe, because we can't distinguish "has
106 * read/write access functions which are safe for raw use" from "has
107 * read/write access functions which have side effects but has forgotten
108 * to provide raw access functions".
109 * The tests here line up with the conditions in read/write_raw_cp_reg()
110 * and assertions in raw_read()/raw_write().
112 if ((ri
->type
& ARM_CP_CONST
) ||
114 ((ri
->raw_writefn
|| ri
->writefn
) && (ri
->raw_readfn
|| ri
->readfn
))) {
120 bool write_cpustate_to_list(ARMCPU
*cpu
, bool kvm_sync
)
122 /* Write the coprocessor state from cpu->env to the (index,value) list. */
126 for (i
= 0; i
< cpu
->cpreg_array_len
; i
++) {
127 uint32_t regidx
= kvm_to_cpreg_id(cpu
->cpreg_indexes
[i
]);
128 const ARMCPRegInfo
*ri
;
131 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
136 if (ri
->type
& ARM_CP_NO_RAW
) {
140 newval
= read_raw_cp_reg(&cpu
->env
, ri
);
143 * Only sync if the previous list->cpustate sync succeeded.
144 * Rather than tracking the success/failure state for every
145 * item in the list, we just recheck "does the raw write we must
146 * have made in write_list_to_cpustate() read back OK" here.
148 uint64_t oldval
= cpu
->cpreg_values
[i
];
150 if (oldval
== newval
) {
154 write_raw_cp_reg(&cpu
->env
, ri
, oldval
);
155 if (read_raw_cp_reg(&cpu
->env
, ri
) != oldval
) {
159 write_raw_cp_reg(&cpu
->env
, ri
, newval
);
161 cpu
->cpreg_values
[i
] = newval
;
166 bool write_list_to_cpustate(ARMCPU
*cpu
)
171 for (i
= 0; i
< cpu
->cpreg_array_len
; i
++) {
172 uint32_t regidx
= kvm_to_cpreg_id(cpu
->cpreg_indexes
[i
]);
173 uint64_t v
= cpu
->cpreg_values
[i
];
174 const ARMCPRegInfo
*ri
;
176 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
181 if (ri
->type
& ARM_CP_NO_RAW
) {
185 * Write value and confirm it reads back as written
186 * (to catch read-only registers and partially read-only
187 * registers where the incoming migration value doesn't match)
189 write_raw_cp_reg(&cpu
->env
, ri
, v
);
190 if (read_raw_cp_reg(&cpu
->env
, ri
) != v
) {
197 static void add_cpreg_to_list(gpointer key
, gpointer opaque
)
199 ARMCPU
*cpu
= opaque
;
200 uint32_t regidx
= (uintptr_t)key
;
201 const ARMCPRegInfo
*ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
203 if (!(ri
->type
& (ARM_CP_NO_RAW
| ARM_CP_ALIAS
))) {
204 cpu
->cpreg_indexes
[cpu
->cpreg_array_len
] = cpreg_to_kvm_id(regidx
);
205 /* The value array need not be initialized at this point */
206 cpu
->cpreg_array_len
++;
210 static void count_cpreg(gpointer key
, gpointer opaque
)
212 ARMCPU
*cpu
= opaque
;
213 const ARMCPRegInfo
*ri
;
215 ri
= g_hash_table_lookup(cpu
->cp_regs
, key
);
217 if (!(ri
->type
& (ARM_CP_NO_RAW
| ARM_CP_ALIAS
))) {
218 cpu
->cpreg_array_len
++;
222 static gint
cpreg_key_compare(gconstpointer a
, gconstpointer b
)
224 uint64_t aidx
= cpreg_to_kvm_id((uintptr_t)a
);
225 uint64_t bidx
= cpreg_to_kvm_id((uintptr_t)b
);
236 void init_cpreg_list(ARMCPU
*cpu
)
239 * Initialise the cpreg_tuples[] array based on the cp_regs hash.
240 * Note that we require cpreg_tuples[] to be sorted by key ID.
245 keys
= g_hash_table_get_keys(cpu
->cp_regs
);
246 keys
= g_list_sort(keys
, cpreg_key_compare
);
248 cpu
->cpreg_array_len
= 0;
250 g_list_foreach(keys
, count_cpreg
, cpu
);
252 arraylen
= cpu
->cpreg_array_len
;
253 cpu
->cpreg_indexes
= g_new(uint64_t, arraylen
);
254 cpu
->cpreg_values
= g_new(uint64_t, arraylen
);
255 cpu
->cpreg_vmstate_indexes
= g_new(uint64_t, arraylen
);
256 cpu
->cpreg_vmstate_values
= g_new(uint64_t, arraylen
);
257 cpu
->cpreg_vmstate_array_len
= cpu
->cpreg_array_len
;
258 cpu
->cpreg_array_len
= 0;
260 g_list_foreach(keys
, add_cpreg_to_list
, cpu
);
262 assert(cpu
->cpreg_array_len
== arraylen
);
267 static bool arm_pan_enabled(CPUARMState
*env
)
270 if ((arm_hcr_el2_eff(env
) & (HCR_NV
| HCR_NV1
)) == (HCR_NV
| HCR_NV1
)) {
273 return env
->pstate
& PSTATE_PAN
;
275 return env
->uncached_cpsr
& CPSR_PAN
;
280 * Some registers are not accessible from AArch32 EL3 if SCR.NS == 0.
282 static CPAccessResult
access_el3_aa32ns(CPUARMState
*env
,
283 const ARMCPRegInfo
*ri
,
286 if (!is_a64(env
) && arm_current_el(env
) == 3 &&
287 arm_is_secure_below_el3(env
)) {
288 return CP_ACCESS_TRAP_UNCATEGORIZED
;
294 * Some secure-only AArch32 registers trap to EL3 if used from
295 * Secure EL1 (but are just ordinary UNDEF in other non-EL3 contexts).
296 * Note that an access from Secure EL1 can only happen if EL3 is AArch64.
297 * We assume that the .access field is set to PL1_RW.
299 static CPAccessResult
access_trap_aa32s_el1(CPUARMState
*env
,
300 const ARMCPRegInfo
*ri
,
303 if (arm_current_el(env
) == 3) {
306 if (arm_is_secure_below_el3(env
)) {
307 if (env
->cp15
.scr_el3
& SCR_EEL2
) {
308 return CP_ACCESS_TRAP_EL2
;
310 return CP_ACCESS_TRAP_EL3
;
312 /* This will be EL1 NS and EL2 NS, which just UNDEF */
313 return CP_ACCESS_TRAP_UNCATEGORIZED
;
317 * Check for traps to performance monitor registers, which are controlled
318 * by MDCR_EL2.TPM for EL2 and MDCR_EL3.TPM for EL3.
320 static CPAccessResult
access_tpm(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
323 int el
= arm_current_el(env
);
324 uint64_t mdcr_el2
= arm_mdcr_el2_eff(env
);
326 if (el
< 2 && (mdcr_el2
& MDCR_TPM
)) {
327 return CP_ACCESS_TRAP_EL2
;
329 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TPM
)) {
330 return CP_ACCESS_TRAP_EL3
;
335 /* Check for traps from EL1 due to HCR_EL2.TVM and HCR_EL2.TRVM. */
336 CPAccessResult
access_tvm_trvm(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
339 if (arm_current_el(env
) == 1) {
340 uint64_t trap
= isread
? HCR_TRVM
: HCR_TVM
;
341 if (arm_hcr_el2_eff(env
) & trap
) {
342 return CP_ACCESS_TRAP_EL2
;
348 /* Check for traps from EL1 due to HCR_EL2.TSW. */
349 static CPAccessResult
access_tsw(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
352 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TSW
)) {
353 return CP_ACCESS_TRAP_EL2
;
358 /* Check for traps from EL1 due to HCR_EL2.TACR. */
359 static CPAccessResult
access_tacr(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
362 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TACR
)) {
363 return CP_ACCESS_TRAP_EL2
;
368 /* Check for traps from EL1 due to HCR_EL2.TTLB. */
369 static CPAccessResult
access_ttlb(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
372 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TTLB
)) {
373 return CP_ACCESS_TRAP_EL2
;
378 /* Check for traps from EL1 due to HCR_EL2.TTLB or TTLBIS. */
379 static CPAccessResult
access_ttlbis(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
382 if (arm_current_el(env
) == 1 &&
383 (arm_hcr_el2_eff(env
) & (HCR_TTLB
| HCR_TTLBIS
))) {
384 return CP_ACCESS_TRAP_EL2
;
389 #ifdef TARGET_AARCH64
390 /* Check for traps from EL1 due to HCR_EL2.TTLB or TTLBOS. */
391 static CPAccessResult
access_ttlbos(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
394 if (arm_current_el(env
) == 1 &&
395 (arm_hcr_el2_eff(env
) & (HCR_TTLB
| HCR_TTLBOS
))) {
396 return CP_ACCESS_TRAP_EL2
;
402 static void dacr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
404 ARMCPU
*cpu
= env_archcpu(env
);
406 raw_write(env
, ri
, value
);
407 tlb_flush(CPU(cpu
)); /* Flush TLB as domain not tracked in TLB */
410 static void fcse_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
412 ARMCPU
*cpu
= env_archcpu(env
);
414 if (raw_read(env
, ri
) != value
) {
416 * Unlike real hardware the qemu TLB uses virtual addresses,
417 * not modified virtual addresses, so this causes a TLB flush.
420 raw_write(env
, ri
, value
);
424 static void contextidr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
427 ARMCPU
*cpu
= env_archcpu(env
);
429 if (raw_read(env
, ri
) != value
&& !arm_feature(env
, ARM_FEATURE_PMSA
)
430 && !extended_addresses_enabled(env
)) {
432 * For VMSA (when not using the LPAE long descriptor page table
433 * format) this register includes the ASID, so do a TLB flush.
434 * For PMSA it is purely a process ID and no action is needed.
438 raw_write(env
, ri
, value
);
441 static int alle1_tlbmask(CPUARMState
*env
)
444 * Note that the 'ALL' scope must invalidate both stage 1 and
445 * stage 2 translations, whereas most other scopes only invalidate
446 * stage 1 translations.
448 return (ARMMMUIdxBit_E10_1
|
449 ARMMMUIdxBit_E10_1_PAN
|
451 ARMMMUIdxBit_Stage2
|
452 ARMMMUIdxBit_Stage2_S
);
456 /* IS variants of TLB operations must affect all cores */
457 static void tlbiall_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
460 CPUState
*cs
= env_cpu(env
);
462 tlb_flush_all_cpus_synced(cs
);
465 static void tlbiasid_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
468 CPUState
*cs
= env_cpu(env
);
470 tlb_flush_all_cpus_synced(cs
);
473 static void tlbimva_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
476 CPUState
*cs
= env_cpu(env
);
478 tlb_flush_page_all_cpus_synced(cs
, value
& TARGET_PAGE_MASK
);
481 static void tlbimvaa_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
484 CPUState
*cs
= env_cpu(env
);
486 tlb_flush_page_all_cpus_synced(cs
, value
& TARGET_PAGE_MASK
);
490 * Non-IS variants of TLB operations are upgraded to
491 * IS versions if we are at EL1 and HCR_EL2.FB is effectively set to
492 * force broadcast of these operations.
494 static bool tlb_force_broadcast(CPUARMState
*env
)
496 return arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_FB
);
499 static void tlbiall_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
502 /* Invalidate all (TLBIALL) */
503 CPUState
*cs
= env_cpu(env
);
505 if (tlb_force_broadcast(env
)) {
506 tlb_flush_all_cpus_synced(cs
);
512 static void tlbimva_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
515 /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
516 CPUState
*cs
= env_cpu(env
);
518 value
&= TARGET_PAGE_MASK
;
519 if (tlb_force_broadcast(env
)) {
520 tlb_flush_page_all_cpus_synced(cs
, value
);
522 tlb_flush_page(cs
, value
);
526 static void tlbiasid_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
529 /* Invalidate by ASID (TLBIASID) */
530 CPUState
*cs
= env_cpu(env
);
532 if (tlb_force_broadcast(env
)) {
533 tlb_flush_all_cpus_synced(cs
);
539 static void tlbimvaa_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
542 /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
543 CPUState
*cs
= env_cpu(env
);
545 value
&= TARGET_PAGE_MASK
;
546 if (tlb_force_broadcast(env
)) {
547 tlb_flush_page_all_cpus_synced(cs
, value
);
549 tlb_flush_page(cs
, value
);
553 static void tlbiall_nsnh_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
556 CPUState
*cs
= env_cpu(env
);
558 tlb_flush_by_mmuidx(cs
, alle1_tlbmask(env
));
561 static void tlbiall_nsnh_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
564 CPUState
*cs
= env_cpu(env
);
566 tlb_flush_by_mmuidx_all_cpus_synced(cs
, alle1_tlbmask(env
));
570 static void tlbiall_hyp_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
573 CPUState
*cs
= env_cpu(env
);
575 tlb_flush_by_mmuidx(cs
, ARMMMUIdxBit_E2
);
578 static void tlbiall_hyp_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
581 CPUState
*cs
= env_cpu(env
);
583 tlb_flush_by_mmuidx_all_cpus_synced(cs
, ARMMMUIdxBit_E2
);
586 static void tlbimva_hyp_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
589 CPUState
*cs
= env_cpu(env
);
590 uint64_t pageaddr
= value
& ~MAKE_64BIT_MASK(0, 12);
592 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_E2
);
595 static void tlbimva_hyp_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
598 CPUState
*cs
= env_cpu(env
);
599 uint64_t pageaddr
= value
& ~MAKE_64BIT_MASK(0, 12);
601 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
605 static void tlbiipas2_hyp_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
608 CPUState
*cs
= env_cpu(env
);
609 uint64_t pageaddr
= (value
& MAKE_64BIT_MASK(0, 28)) << 12;
611 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_Stage2
);
614 static void tlbiipas2is_hyp_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
617 CPUState
*cs
= env_cpu(env
);
618 uint64_t pageaddr
= (value
& MAKE_64BIT_MASK(0, 28)) << 12;
620 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
, ARMMMUIdxBit_Stage2
);
623 static const ARMCPRegInfo cp_reginfo
[] = {
625 * Define the secure and non-secure FCSE identifier CP registers
626 * separately because there is no secure bank in V8 (no _EL3). This allows
627 * the secure register to be properly reset and migrated. There is also no
628 * v8 EL1 version of the register so the non-secure instance stands alone.
631 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 0,
632 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_NS
,
633 .fieldoffset
= offsetof(CPUARMState
, cp15
.fcseidr_ns
),
634 .resetvalue
= 0, .writefn
= fcse_write
, .raw_writefn
= raw_write
, },
635 { .name
= "FCSEIDR_S",
636 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 0,
637 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_S
,
638 .fieldoffset
= offsetof(CPUARMState
, cp15
.fcseidr_s
),
639 .resetvalue
= 0, .writefn
= fcse_write
, .raw_writefn
= raw_write
, },
641 * Define the secure and non-secure context identifier CP registers
642 * separately because there is no secure bank in V8 (no _EL3). This allows
643 * the secure register to be properly reset and migrated. In the
644 * non-secure case, the 32-bit register will have reset and migration
645 * disabled during registration as it is handled by the 64-bit instance.
647 { .name
= "CONTEXTIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
648 .opc0
= 3, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 1,
649 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
650 .fgt
= FGT_CONTEXTIDR_EL1
,
651 .nv2_redirect_offset
= 0x108 | NV2_REDIR_NV1
,
652 .secure
= ARM_CP_SECSTATE_NS
,
653 .fieldoffset
= offsetof(CPUARMState
, cp15
.contextidr_el
[1]),
654 .resetvalue
= 0, .writefn
= contextidr_write
, .raw_writefn
= raw_write
, },
655 { .name
= "CONTEXTIDR_S", .state
= ARM_CP_STATE_AA32
,
656 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 1,
657 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
658 .secure
= ARM_CP_SECSTATE_S
,
659 .fieldoffset
= offsetof(CPUARMState
, cp15
.contextidr_s
),
660 .resetvalue
= 0, .writefn
= contextidr_write
, .raw_writefn
= raw_write
, },
663 static const ARMCPRegInfo not_v8_cp_reginfo
[] = {
665 * NB: Some of these registers exist in v8 but with more precise
666 * definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginfo[]).
668 /* MMU Domain access control / MPU write buffer control */
670 .cp
= 15, .opc1
= CP_ANY
, .crn
= 3, .crm
= CP_ANY
, .opc2
= CP_ANY
,
671 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
, .resetvalue
= 0,
672 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
673 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dacr_s
),
674 offsetoflow32(CPUARMState
, cp15
.dacr_ns
) } },
676 * ARMv7 allocates a range of implementation defined TLB LOCKDOWN regs.
677 * For v6 and v5, these mappings are overly broad.
679 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 0,
680 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
681 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 1,
682 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
683 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 4,
684 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
685 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 8,
686 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
687 /* Cache maintenance ops; some of this space may be overridden later. */
688 { .name
= "CACHEMAINT", .cp
= 15, .crn
= 7, .crm
= CP_ANY
,
689 .opc1
= 0, .opc2
= CP_ANY
, .access
= PL1_W
,
690 .type
= ARM_CP_NOP
| ARM_CP_OVERRIDE
},
693 static const ARMCPRegInfo not_v6_cp_reginfo
[] = {
695 * Not all pre-v6 cores implemented this WFI, so this is slightly
698 { .name
= "WFI_v5", .cp
= 15, .crn
= 7, .crm
= 8, .opc1
= 0, .opc2
= 2,
699 .access
= PL1_W
, .type
= ARM_CP_WFI
},
702 static const ARMCPRegInfo not_v7_cp_reginfo
[] = {
704 * Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
705 * is UNPREDICTABLE; we choose to NOP as most implementations do).
707 { .name
= "WFI_v6", .cp
= 15, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 4,
708 .access
= PL1_W
, .type
= ARM_CP_WFI
},
710 * L1 cache lockdown. Not architectural in v6 and earlier but in practice
711 * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
712 * OMAPCP will override this space.
714 { .name
= "DLOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 0, .opc2
= 0,
715 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_data
),
717 { .name
= "ILOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 0, .opc2
= 1,
718 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_insn
),
720 /* v6 doesn't have the cache ID registers but Linux reads them anyway */
721 { .name
= "DUMMY", .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= CP_ANY
,
722 .access
= PL1_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
725 * We don't implement pre-v7 debug but most CPUs had at least a DBGDIDR;
726 * implementing it as RAZ means the "debug architecture version" bits
727 * will read as a reserved value, which should cause Linux to not try
728 * to use the debug hardware.
730 { .name
= "DBGDIDR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 0,
731 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
733 * MMU TLB control. Note that the wildcarding means we cover not just
734 * the unified TLB ops but also the dside/iside/inner-shareable variants.
736 { .name
= "TLBIALL", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
737 .opc1
= CP_ANY
, .opc2
= 0, .access
= PL1_W
, .writefn
= tlbiall_write
,
738 .type
= ARM_CP_NO_RAW
},
739 { .name
= "TLBIMVA", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
740 .opc1
= CP_ANY
, .opc2
= 1, .access
= PL1_W
, .writefn
= tlbimva_write
,
741 .type
= ARM_CP_NO_RAW
},
742 { .name
= "TLBIASID", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
743 .opc1
= CP_ANY
, .opc2
= 2, .access
= PL1_W
, .writefn
= tlbiasid_write
,
744 .type
= ARM_CP_NO_RAW
},
745 { .name
= "TLBIMVAA", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
746 .opc1
= CP_ANY
, .opc2
= 3, .access
= PL1_W
, .writefn
= tlbimvaa_write
,
747 .type
= ARM_CP_NO_RAW
},
748 { .name
= "PRRR", .cp
= 15, .crn
= 10, .crm
= 2,
749 .opc1
= 0, .opc2
= 0, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
750 { .name
= "NMRR", .cp
= 15, .crn
= 10, .crm
= 2,
751 .opc1
= 0, .opc2
= 1, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
754 static void cpacr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
759 /* In ARMv8 most bits of CPACR_EL1 are RES0. */
760 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
762 * ARMv7 defines bits for unimplemented coprocessors as RAZ/WI.
763 * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP.
764 * TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell.
766 if (cpu_isar_feature(aa32_vfp_simd
, env_archcpu(env
))) {
767 /* VFP coprocessor: cp10 & cp11 [23:20] */
768 mask
|= R_CPACR_ASEDIS_MASK
|
769 R_CPACR_D32DIS_MASK
|
773 if (!arm_feature(env
, ARM_FEATURE_NEON
)) {
774 /* ASEDIS [31] bit is RAO/WI */
775 value
|= R_CPACR_ASEDIS_MASK
;
779 * VFPv3 and upwards with NEON implement 32 double precision
780 * registers (D0-D31).
782 if (!cpu_isar_feature(aa32_simd_r32
, env_archcpu(env
))) {
783 /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */
784 value
|= R_CPACR_D32DIS_MASK
;
791 * For A-profile AArch32 EL3 (but not M-profile secure mode), if NSACR.CP10
792 * is 0 then CPACR.{CP11,CP10} ignore writes and read as 0b00.
794 if (arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
795 !arm_is_secure(env
) && !extract32(env
->cp15
.nsacr
, 10, 1)) {
796 mask
= R_CPACR_CP11_MASK
| R_CPACR_CP10_MASK
;
797 value
= (value
& ~mask
) | (env
->cp15
.cpacr_el1
& mask
);
800 env
->cp15
.cpacr_el1
= value
;
803 static uint64_t cpacr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
806 * For A-profile AArch32 EL3 (but not M-profile secure mode), if NSACR.CP10
807 * is 0 then CPACR.{CP11,CP10} ignore writes and read as 0b00.
809 uint64_t value
= env
->cp15
.cpacr_el1
;
811 if (arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
812 !arm_is_secure(env
) && !extract32(env
->cp15
.nsacr
, 10, 1)) {
813 value
= ~(R_CPACR_CP11_MASK
| R_CPACR_CP10_MASK
);
819 static void cpacr_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
822 * Call cpacr_write() so that we reset with the correct RAO bits set
823 * for our CPU features.
825 cpacr_write(env
, ri
, 0);
828 static CPAccessResult
cpacr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
831 if (arm_feature(env
, ARM_FEATURE_V8
)) {
832 /* Check if CPACR accesses are to be trapped to EL2 */
833 if (arm_current_el(env
) == 1 && arm_is_el2_enabled(env
) &&
834 FIELD_EX64(env
->cp15
.cptr_el
[2], CPTR_EL2
, TCPAC
)) {
835 return CP_ACCESS_TRAP_EL2
;
836 /* Check if CPACR accesses are to be trapped to EL3 */
837 } else if (arm_current_el(env
) < 3 &&
838 FIELD_EX64(env
->cp15
.cptr_el
[3], CPTR_EL3
, TCPAC
)) {
839 return CP_ACCESS_TRAP_EL3
;
846 static CPAccessResult
cptr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
849 /* Check if CPTR accesses are set to trap to EL3 */
850 if (arm_current_el(env
) == 2 &&
851 FIELD_EX64(env
->cp15
.cptr_el
[3], CPTR_EL3
, TCPAC
)) {
852 return CP_ACCESS_TRAP_EL3
;
858 static const ARMCPRegInfo v6_cp_reginfo
[] = {
859 /* prefetch by MVA in v6, NOP in v7 */
860 { .name
= "MVA_prefetch",
861 .cp
= 15, .crn
= 7, .crm
= 13, .opc1
= 0, .opc2
= 1,
862 .access
= PL1_W
, .type
= ARM_CP_NOP
},
864 * We need to break the TB after ISB to execute self-modifying code
865 * correctly and also to take any pending interrupts immediately.
866 * So use arm_cp_write_ignore() function instead of ARM_CP_NOP flag.
868 { .name
= "ISB", .cp
= 15, .crn
= 7, .crm
= 5, .opc1
= 0, .opc2
= 4,
869 .access
= PL0_W
, .type
= ARM_CP_NO_RAW
, .writefn
= arm_cp_write_ignore
},
870 { .name
= "DSB", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 4,
871 .access
= PL0_W
, .type
= ARM_CP_NOP
},
872 { .name
= "DMB", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 5,
873 .access
= PL0_W
, .type
= ARM_CP_NOP
},
874 { .name
= "IFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 2,
875 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
876 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ifar_s
),
877 offsetof(CPUARMState
, cp15
.ifar_ns
) },
880 * Watchpoint Fault Address Register : should actually only be present
881 * for 1136, 1176, 11MPCore.
883 { .name
= "WFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 1,
884 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0, },
885 { .name
= "CPACR", .state
= ARM_CP_STATE_BOTH
, .opc0
= 3,
886 .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 2, .accessfn
= cpacr_access
,
887 .fgt
= FGT_CPACR_EL1
,
888 .nv2_redirect_offset
= 0x100 | NV2_REDIR_NV1
,
889 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.cpacr_el1
),
890 .resetfn
= cpacr_reset
, .writefn
= cpacr_write
, .readfn
= cpacr_read
},
893 typedef struct pm_event
{
894 uint16_t number
; /* PMEVTYPER.evtCount is 16 bits wide */
895 /* If the event is supported on this CPU (used to generate PMCEID[01]) */
896 bool (*supported
)(CPUARMState
*);
898 * Retrieve the current count of the underlying event. The programmed
899 * counters hold a difference from the return value from this function
901 uint64_t (*get_count
)(CPUARMState
*);
903 * Return how many nanoseconds it will take (at a minimum) for count events
904 * to occur. A negative value indicates the counter will never overflow, or
905 * that the counter has otherwise arranged for the overflow bit to be set
906 * and the PMU interrupt to be raised on overflow.
908 int64_t (*ns_per_count
)(uint64_t);
911 static bool event_always_supported(CPUARMState
*env
)
916 static uint64_t swinc_get_count(CPUARMState
*env
)
919 * SW_INCR events are written directly to the pmevcntr's by writes to
920 * PMSWINC, so there is no underlying count maintained by the PMU itself
925 static int64_t swinc_ns_per(uint64_t ignored
)
931 * Return the underlying cycle count for the PMU cycle counters. If we're in
932 * usermode, simply return 0.
934 static uint64_t cycles_get_count(CPUARMState
*env
)
936 #ifndef CONFIG_USER_ONLY
937 return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
),
938 ARM_CPU_FREQ
, NANOSECONDS_PER_SECOND
);
940 return cpu_get_host_ticks();
944 #ifndef CONFIG_USER_ONLY
945 static int64_t cycles_ns_per(uint64_t cycles
)
947 return (ARM_CPU_FREQ
/ NANOSECONDS_PER_SECOND
) * cycles
;
950 static bool instructions_supported(CPUARMState
*env
)
952 /* Precise instruction counting */
953 return icount_enabled() == ICOUNT_PRECISE
;
956 static uint64_t instructions_get_count(CPUARMState
*env
)
958 assert(icount_enabled() == ICOUNT_PRECISE
);
959 return (uint64_t)icount_get_raw();
962 static int64_t instructions_ns_per(uint64_t icount
)
964 assert(icount_enabled() == ICOUNT_PRECISE
);
965 return icount_to_ns((int64_t)icount
);
969 static bool pmuv3p1_events_supported(CPUARMState
*env
)
971 /* For events which are supported in any v8.1 PMU */
972 return cpu_isar_feature(any_pmuv3p1
, env_archcpu(env
));
975 static bool pmuv3p4_events_supported(CPUARMState
*env
)
977 /* For events which are supported in any v8.1 PMU */
978 return cpu_isar_feature(any_pmuv3p4
, env_archcpu(env
));
981 static uint64_t zero_event_get_count(CPUARMState
*env
)
983 /* For events which on QEMU never fire, so their count is always zero */
987 static int64_t zero_event_ns_per(uint64_t cycles
)
989 /* An event which never fires can never overflow */
993 static const pm_event pm_events
[] = {
994 { .number
= 0x000, /* SW_INCR */
995 .supported
= event_always_supported
,
996 .get_count
= swinc_get_count
,
997 .ns_per_count
= swinc_ns_per
,
999 #ifndef CONFIG_USER_ONLY
1000 { .number
= 0x008, /* INST_RETIRED, Instruction architecturally executed */
1001 .supported
= instructions_supported
,
1002 .get_count
= instructions_get_count
,
1003 .ns_per_count
= instructions_ns_per
,
1005 { .number
= 0x011, /* CPU_CYCLES, Cycle */
1006 .supported
= event_always_supported
,
1007 .get_count
= cycles_get_count
,
1008 .ns_per_count
= cycles_ns_per
,
1011 { .number
= 0x023, /* STALL_FRONTEND */
1012 .supported
= pmuv3p1_events_supported
,
1013 .get_count
= zero_event_get_count
,
1014 .ns_per_count
= zero_event_ns_per
,
1016 { .number
= 0x024, /* STALL_BACKEND */
1017 .supported
= pmuv3p1_events_supported
,
1018 .get_count
= zero_event_get_count
,
1019 .ns_per_count
= zero_event_ns_per
,
1021 { .number
= 0x03c, /* STALL */
1022 .supported
= pmuv3p4_events_supported
,
1023 .get_count
= zero_event_get_count
,
1024 .ns_per_count
= zero_event_ns_per
,
1029 * Note: Before increasing MAX_EVENT_ID beyond 0x3f into the 0x40xx range of
1030 * events (i.e. the statistical profiling extension), this implementation
1031 * should first be updated to something sparse instead of the current
1032 * supported_event_map[] array.
1034 #define MAX_EVENT_ID 0x3c
1035 #define UNSUPPORTED_EVENT UINT16_MAX
1036 static uint16_t supported_event_map
[MAX_EVENT_ID
+ 1];
1039 * Called upon CPU initialization to initialize PMCEID[01]_EL0 and build a map
1040 * of ARM event numbers to indices in our pm_events array.
1042 * Note: Events in the 0x40XX range are not currently supported.
1044 void pmu_init(ARMCPU
*cpu
)
1049 * Empty supported_event_map and cpu->pmceid[01] before adding supported
1052 for (i
= 0; i
< ARRAY_SIZE(supported_event_map
); i
++) {
1053 supported_event_map
[i
] = UNSUPPORTED_EVENT
;
1058 for (i
= 0; i
< ARRAY_SIZE(pm_events
); i
++) {
1059 const pm_event
*cnt
= &pm_events
[i
];
1060 assert(cnt
->number
<= MAX_EVENT_ID
);
1061 /* We do not currently support events in the 0x40xx range */
1062 assert(cnt
->number
<= 0x3f);
1064 if (cnt
->supported(&cpu
->env
)) {
1065 supported_event_map
[cnt
->number
] = i
;
1066 uint64_t event_mask
= 1ULL << (cnt
->number
& 0x1f);
1067 if (cnt
->number
& 0x20) {
1068 cpu
->pmceid1
|= event_mask
;
1070 cpu
->pmceid0
|= event_mask
;
1077 * Check at runtime whether a PMU event is supported for the current machine
1079 static bool event_supported(uint16_t number
)
1081 if (number
> MAX_EVENT_ID
) {
1084 return supported_event_map
[number
] != UNSUPPORTED_EVENT
;
1087 static CPAccessResult
pmreg_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1091 * Performance monitor registers user accessibility is controlled
1092 * by PMUSERENR. MDCR_EL2.TPM and MDCR_EL3.TPM allow configurable
1093 * trapping to EL2 or EL3 for other accesses.
1095 int el
= arm_current_el(env
);
1096 uint64_t mdcr_el2
= arm_mdcr_el2_eff(env
);
1098 if (el
== 0 && !(env
->cp15
.c9_pmuserenr
& 1)) {
1099 return CP_ACCESS_TRAP
;
1101 if (el
< 2 && (mdcr_el2
& MDCR_TPM
)) {
1102 return CP_ACCESS_TRAP_EL2
;
1104 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TPM
)) {
1105 return CP_ACCESS_TRAP_EL3
;
1108 return CP_ACCESS_OK
;
1111 static CPAccessResult
pmreg_access_xevcntr(CPUARMState
*env
,
1112 const ARMCPRegInfo
*ri
,
1115 /* ER: event counter read trap control */
1116 if (arm_feature(env
, ARM_FEATURE_V8
)
1117 && arm_current_el(env
) == 0
1118 && (env
->cp15
.c9_pmuserenr
& (1 << 3)) != 0
1120 return CP_ACCESS_OK
;
1123 return pmreg_access(env
, ri
, isread
);
1126 static CPAccessResult
pmreg_access_swinc(CPUARMState
*env
,
1127 const ARMCPRegInfo
*ri
,
1130 /* SW: software increment write trap control */
1131 if (arm_feature(env
, ARM_FEATURE_V8
)
1132 && arm_current_el(env
) == 0
1133 && (env
->cp15
.c9_pmuserenr
& (1 << 1)) != 0
1135 return CP_ACCESS_OK
;
1138 return pmreg_access(env
, ri
, isread
);
1141 static CPAccessResult
pmreg_access_selr(CPUARMState
*env
,
1142 const ARMCPRegInfo
*ri
,
1145 /* ER: event counter read trap control */
1146 if (arm_feature(env
, ARM_FEATURE_V8
)
1147 && arm_current_el(env
) == 0
1148 && (env
->cp15
.c9_pmuserenr
& (1 << 3)) != 0) {
1149 return CP_ACCESS_OK
;
1152 return pmreg_access(env
, ri
, isread
);
1155 static CPAccessResult
pmreg_access_ccntr(CPUARMState
*env
,
1156 const ARMCPRegInfo
*ri
,
1159 /* CR: cycle counter read trap control */
1160 if (arm_feature(env
, ARM_FEATURE_V8
)
1161 && arm_current_el(env
) == 0
1162 && (env
->cp15
.c9_pmuserenr
& (1 << 2)) != 0
1164 return CP_ACCESS_OK
;
1167 return pmreg_access(env
, ri
, isread
);
1171 * Bits in MDCR_EL2 and MDCR_EL3 which pmu_counter_enabled() looks at.
1172 * We use these to decide whether we need to wrap a write to MDCR_EL2
1173 * or MDCR_EL3 in pmu_op_start()/pmu_op_finish() calls.
1175 #define MDCR_EL2_PMU_ENABLE_BITS \
1176 (MDCR_HPME | MDCR_HPMD | MDCR_HPMN | MDCR_HCCD | MDCR_HLP)
1177 #define MDCR_EL3_PMU_ENABLE_BITS (MDCR_SPME | MDCR_SCCD)
1180 * Returns true if the counter (pass 31 for PMCCNTR) should count events using
1181 * the current EL, security state, and register configuration.
1183 static bool pmu_counter_enabled(CPUARMState
*env
, uint8_t counter
)
1186 bool e
, p
, u
, nsk
, nsu
, nsh
, m
;
1187 bool enabled
, prohibited
= false, filtered
;
1188 bool secure
= arm_is_secure(env
);
1189 int el
= arm_current_el(env
);
1194 * We might be called for M-profile cores where MDCR_EL2 doesn't
1195 * exist and arm_mdcr_el2_eff() will assert, so this early-exit check
1196 * must be before we read that value.
1198 if (!arm_feature(env
, ARM_FEATURE_PMU
)) {
1202 mdcr_el2
= arm_mdcr_el2_eff(env
);
1203 hpmn
= mdcr_el2
& MDCR_HPMN
;
1205 if (!arm_feature(env
, ARM_FEATURE_EL2
) ||
1206 (counter
< hpmn
|| counter
== 31)) {
1207 e
= env
->cp15
.c9_pmcr
& PMCRE
;
1209 e
= mdcr_el2
& MDCR_HPME
;
1211 enabled
= e
&& (env
->cp15
.c9_pmcnten
& (1 << counter
));
1213 /* Is event counting prohibited? */
1214 if (el
== 2 && (counter
< hpmn
|| counter
== 31)) {
1215 prohibited
= mdcr_el2
& MDCR_HPMD
;
1218 prohibited
= prohibited
|| !(env
->cp15
.mdcr_el3
& MDCR_SPME
);
1221 if (counter
== 31) {
1223 * The cycle counter defaults to running. PMCR.DP says "disable
1224 * the cycle counter when event counting is prohibited".
1225 * Some MDCR bits disable the cycle counter specifically.
1227 prohibited
= prohibited
&& env
->cp15
.c9_pmcr
& PMCRDP
;
1228 if (cpu_isar_feature(any_pmuv3p5
, env_archcpu(env
))) {
1230 prohibited
= prohibited
|| (env
->cp15
.mdcr_el3
& MDCR_SCCD
);
1233 prohibited
= prohibited
|| (mdcr_el2
& MDCR_HCCD
);
1238 if (counter
== 31) {
1239 filter
= env
->cp15
.pmccfiltr_el0
;
1241 filter
= env
->cp15
.c14_pmevtyper
[counter
];
1244 p
= filter
& PMXEVTYPER_P
;
1245 u
= filter
& PMXEVTYPER_U
;
1246 nsk
= arm_feature(env
, ARM_FEATURE_EL3
) && (filter
& PMXEVTYPER_NSK
);
1247 nsu
= arm_feature(env
, ARM_FEATURE_EL3
) && (filter
& PMXEVTYPER_NSU
);
1248 nsh
= arm_feature(env
, ARM_FEATURE_EL2
) && (filter
& PMXEVTYPER_NSH
);
1249 m
= arm_el_is_aa64(env
, 1) &&
1250 arm_feature(env
, ARM_FEATURE_EL3
) && (filter
& PMXEVTYPER_M
);
1253 filtered
= secure
? u
: u
!= nsu
;
1254 } else if (el
== 1) {
1255 filtered
= secure
? p
: p
!= nsk
;
1256 } else if (el
== 2) {
1262 if (counter
!= 31) {
1264 * If not checking PMCCNTR, ensure the counter is setup to an event we
1267 uint16_t event
= filter
& PMXEVTYPER_EVTCOUNT
;
1268 if (!event_supported(event
)) {
1273 return enabled
&& !prohibited
&& !filtered
;
1276 static void pmu_update_irq(CPUARMState
*env
)
1278 ARMCPU
*cpu
= env_archcpu(env
);
1279 qemu_set_irq(cpu
->pmu_interrupt
, (env
->cp15
.c9_pmcr
& PMCRE
) &&
1280 (env
->cp15
.c9_pminten
& env
->cp15
.c9_pmovsr
));
1283 static bool pmccntr_clockdiv_enabled(CPUARMState
*env
)
1286 * Return true if the clock divider is enabled and the cycle counter
1287 * is supposed to tick only once every 64 clock cycles. This is
1288 * controlled by PMCR.D, but if PMCR.LC is set to enable the long
1289 * (64-bit) cycle counter PMCR.D has no effect.
1291 return (env
->cp15
.c9_pmcr
& (PMCRD
| PMCRLC
)) == PMCRD
;
1294 static bool pmevcntr_is_64_bit(CPUARMState
*env
, int counter
)
1296 /* Return true if the specified event counter is configured to be 64 bit */
1298 /* This isn't intended to be used with the cycle counter */
1299 assert(counter
< 31);
1301 if (!cpu_isar_feature(any_pmuv3p5
, env_archcpu(env
))) {
1305 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
1307 * MDCR_EL2.HLP still applies even when EL2 is disabled in the
1308 * current security state, so we don't use arm_mdcr_el2_eff() here.
1310 bool hlp
= env
->cp15
.mdcr_el2
& MDCR_HLP
;
1311 int hpmn
= env
->cp15
.mdcr_el2
& MDCR_HPMN
;
1313 if (counter
>= hpmn
) {
1317 return env
->cp15
.c9_pmcr
& PMCRLP
;
1321 * Ensure c15_ccnt is the guest-visible count so that operations such as
1322 * enabling/disabling the counter or filtering, modifying the count itself,
1323 * etc. can be done logically. This is essentially a no-op if the counter is
1324 * not enabled at the time of the call.
1326 static void pmccntr_op_start(CPUARMState
*env
)
1328 uint64_t cycles
= cycles_get_count(env
);
1330 if (pmu_counter_enabled(env
, 31)) {
1331 uint64_t eff_cycles
= cycles
;
1332 if (pmccntr_clockdiv_enabled(env
)) {
1336 uint64_t new_pmccntr
= eff_cycles
- env
->cp15
.c15_ccnt_delta
;
1338 uint64_t overflow_mask
= env
->cp15
.c9_pmcr
& PMCRLC
? \
1339 1ull << 63 : 1ull << 31;
1340 if (env
->cp15
.c15_ccnt
& ~new_pmccntr
& overflow_mask
) {
1341 env
->cp15
.c9_pmovsr
|= (1ULL << 31);
1342 pmu_update_irq(env
);
1345 env
->cp15
.c15_ccnt
= new_pmccntr
;
1347 env
->cp15
.c15_ccnt_delta
= cycles
;
1351 * If PMCCNTR is enabled, recalculate the delta between the clock and the
1352 * guest-visible count. A call to pmccntr_op_finish should follow every call to
1355 static void pmccntr_op_finish(CPUARMState
*env
)
1357 if (pmu_counter_enabled(env
, 31)) {
1358 #ifndef CONFIG_USER_ONLY
1359 /* Calculate when the counter will next overflow */
1360 uint64_t remaining_cycles
= -env
->cp15
.c15_ccnt
;
1361 if (!(env
->cp15
.c9_pmcr
& PMCRLC
)) {
1362 remaining_cycles
= (uint32_t)remaining_cycles
;
1364 int64_t overflow_in
= cycles_ns_per(remaining_cycles
);
1366 if (overflow_in
> 0) {
1367 int64_t overflow_at
;
1369 if (!sadd64_overflow(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
),
1370 overflow_in
, &overflow_at
)) {
1371 ARMCPU
*cpu
= env_archcpu(env
);
1372 timer_mod_anticipate_ns(cpu
->pmu_timer
, overflow_at
);
1377 uint64_t prev_cycles
= env
->cp15
.c15_ccnt_delta
;
1378 if (pmccntr_clockdiv_enabled(env
)) {
1381 env
->cp15
.c15_ccnt_delta
= prev_cycles
- env
->cp15
.c15_ccnt
;
1385 static void pmevcntr_op_start(CPUARMState
*env
, uint8_t counter
)
1388 uint16_t event
= env
->cp15
.c14_pmevtyper
[counter
] & PMXEVTYPER_EVTCOUNT
;
1390 if (event_supported(event
)) {
1391 uint16_t event_idx
= supported_event_map
[event
];
1392 count
= pm_events
[event_idx
].get_count(env
);
1395 if (pmu_counter_enabled(env
, counter
)) {
1396 uint64_t new_pmevcntr
= count
- env
->cp15
.c14_pmevcntr_delta
[counter
];
1397 uint64_t overflow_mask
= pmevcntr_is_64_bit(env
, counter
) ?
1398 1ULL << 63 : 1ULL << 31;
1400 if (env
->cp15
.c14_pmevcntr
[counter
] & ~new_pmevcntr
& overflow_mask
) {
1401 env
->cp15
.c9_pmovsr
|= (1 << counter
);
1402 pmu_update_irq(env
);
1404 env
->cp15
.c14_pmevcntr
[counter
] = new_pmevcntr
;
1406 env
->cp15
.c14_pmevcntr_delta
[counter
] = count
;
1409 static void pmevcntr_op_finish(CPUARMState
*env
, uint8_t counter
)
1411 if (pmu_counter_enabled(env
, counter
)) {
1412 #ifndef CONFIG_USER_ONLY
1413 uint16_t event
= env
->cp15
.c14_pmevtyper
[counter
] & PMXEVTYPER_EVTCOUNT
;
1414 uint16_t event_idx
= supported_event_map
[event
];
1415 uint64_t delta
= -(env
->cp15
.c14_pmevcntr
[counter
] + 1);
1416 int64_t overflow_in
;
1418 if (!pmevcntr_is_64_bit(env
, counter
)) {
1419 delta
= (uint32_t)delta
;
1421 overflow_in
= pm_events
[event_idx
].ns_per_count(delta
);
1423 if (overflow_in
> 0) {
1424 int64_t overflow_at
;
1426 if (!sadd64_overflow(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
),
1427 overflow_in
, &overflow_at
)) {
1428 ARMCPU
*cpu
= env_archcpu(env
);
1429 timer_mod_anticipate_ns(cpu
->pmu_timer
, overflow_at
);
1434 env
->cp15
.c14_pmevcntr_delta
[counter
] -=
1435 env
->cp15
.c14_pmevcntr
[counter
];
1439 void pmu_op_start(CPUARMState
*env
)
1442 pmccntr_op_start(env
);
1443 for (i
= 0; i
< pmu_num_counters(env
); i
++) {
1444 pmevcntr_op_start(env
, i
);
1448 void pmu_op_finish(CPUARMState
*env
)
1451 pmccntr_op_finish(env
);
1452 for (i
= 0; i
< pmu_num_counters(env
); i
++) {
1453 pmevcntr_op_finish(env
, i
);
1457 void pmu_pre_el_change(ARMCPU
*cpu
, void *ignored
)
1459 pmu_op_start(&cpu
->env
);
1462 void pmu_post_el_change(ARMCPU
*cpu
, void *ignored
)
1464 pmu_op_finish(&cpu
->env
);
1467 void arm_pmu_timer_cb(void *opaque
)
1469 ARMCPU
*cpu
= opaque
;
1472 * Update all the counter values based on the current underlying counts,
1473 * triggering interrupts to be raised, if necessary. pmu_op_finish() also
1474 * has the effect of setting the cpu->pmu_timer to the next earliest time a
1475 * counter may expire.
1477 pmu_op_start(&cpu
->env
);
1478 pmu_op_finish(&cpu
->env
);
1481 static void pmcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1486 if (value
& PMCRC
) {
1487 /* The counter has been reset */
1488 env
->cp15
.c15_ccnt
= 0;
1491 if (value
& PMCRP
) {
1493 for (i
= 0; i
< pmu_num_counters(env
); i
++) {
1494 env
->cp15
.c14_pmevcntr
[i
] = 0;
1498 env
->cp15
.c9_pmcr
&= ~PMCR_WRITABLE_MASK
;
1499 env
->cp15
.c9_pmcr
|= (value
& PMCR_WRITABLE_MASK
);
1504 static uint64_t pmcr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1506 uint64_t pmcr
= env
->cp15
.c9_pmcr
;
1509 * If EL2 is implemented and enabled for the current security state, reads
1510 * of PMCR.N from EL1 or EL0 return the value of MDCR_EL2.HPMN or HDCR.HPMN.
1512 if (arm_current_el(env
) <= 1 && arm_is_el2_enabled(env
)) {
1513 pmcr
&= ~PMCRN_MASK
;
1514 pmcr
|= (env
->cp15
.mdcr_el2
& MDCR_HPMN
) << PMCRN_SHIFT
;
1520 static void pmswinc_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1524 uint64_t overflow_mask
, new_pmswinc
;
1526 for (i
= 0; i
< pmu_num_counters(env
); i
++) {
1527 /* Increment a counter's count iff: */
1528 if ((value
& (1 << i
)) && /* counter's bit is set */
1529 /* counter is enabled and not filtered */
1530 pmu_counter_enabled(env
, i
) &&
1531 /* counter is SW_INCR */
1532 (env
->cp15
.c14_pmevtyper
[i
] & PMXEVTYPER_EVTCOUNT
) == 0x0) {
1533 pmevcntr_op_start(env
, i
);
1536 * Detect if this write causes an overflow since we can't predict
1537 * PMSWINC overflows like we can for other events
1539 new_pmswinc
= env
->cp15
.c14_pmevcntr
[i
] + 1;
1541 overflow_mask
= pmevcntr_is_64_bit(env
, i
) ?
1542 1ULL << 63 : 1ULL << 31;
1544 if (env
->cp15
.c14_pmevcntr
[i
] & ~new_pmswinc
& overflow_mask
) {
1545 env
->cp15
.c9_pmovsr
|= (1 << i
);
1546 pmu_update_irq(env
);
1549 env
->cp15
.c14_pmevcntr
[i
] = new_pmswinc
;
1551 pmevcntr_op_finish(env
, i
);
1556 static uint64_t pmccntr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1559 pmccntr_op_start(env
);
1560 ret
= env
->cp15
.c15_ccnt
;
1561 pmccntr_op_finish(env
);
1565 static void pmselr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1569 * The value of PMSELR.SEL affects the behavior of PMXEVTYPER and
1570 * PMXEVCNTR. We allow [0..31] to be written to PMSELR here; in the
1571 * meanwhile, we check PMSELR.SEL when PMXEVTYPER and PMXEVCNTR are
1574 env
->cp15
.c9_pmselr
= value
& 0x1f;
1577 static void pmccntr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1580 pmccntr_op_start(env
);
1581 env
->cp15
.c15_ccnt
= value
;
1582 pmccntr_op_finish(env
);
1585 static void pmccntr_write32(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1588 uint64_t cur_val
= pmccntr_read(env
, NULL
);
1590 pmccntr_write(env
, ri
, deposit64(cur_val
, 0, 32, value
));
1593 static void pmccfiltr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1596 pmccntr_op_start(env
);
1597 env
->cp15
.pmccfiltr_el0
= value
& PMCCFILTR_EL0
;
1598 pmccntr_op_finish(env
);
1601 static void pmccfiltr_write_a32(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1604 pmccntr_op_start(env
);
1605 /* M is not accessible from AArch32 */
1606 env
->cp15
.pmccfiltr_el0
= (env
->cp15
.pmccfiltr_el0
& PMCCFILTR_M
) |
1607 (value
& PMCCFILTR
);
1608 pmccntr_op_finish(env
);
1611 static uint64_t pmccfiltr_read_a32(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1613 /* M is not visible in AArch32 */
1614 return env
->cp15
.pmccfiltr_el0
& PMCCFILTR
;
1617 static void pmcntenset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1621 value
&= pmu_counter_mask(env
);
1622 env
->cp15
.c9_pmcnten
|= value
;
1626 static void pmcntenclr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1630 value
&= pmu_counter_mask(env
);
1631 env
->cp15
.c9_pmcnten
&= ~value
;
1635 static void pmovsr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1638 value
&= pmu_counter_mask(env
);
1639 env
->cp15
.c9_pmovsr
&= ~value
;
1640 pmu_update_irq(env
);
1643 static void pmovsset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1646 value
&= pmu_counter_mask(env
);
1647 env
->cp15
.c9_pmovsr
|= value
;
1648 pmu_update_irq(env
);
1651 static void pmevtyper_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1652 uint64_t value
, const uint8_t counter
)
1654 if (counter
== 31) {
1655 pmccfiltr_write(env
, ri
, value
);
1656 } else if (counter
< pmu_num_counters(env
)) {
1657 pmevcntr_op_start(env
, counter
);
1660 * If this counter's event type is changing, store the current
1661 * underlying count for the new type in c14_pmevcntr_delta[counter] so
1662 * pmevcntr_op_finish has the correct baseline when it converts back to
1665 uint16_t old_event
= env
->cp15
.c14_pmevtyper
[counter
] &
1666 PMXEVTYPER_EVTCOUNT
;
1667 uint16_t new_event
= value
& PMXEVTYPER_EVTCOUNT
;
1668 if (old_event
!= new_event
) {
1670 if (event_supported(new_event
)) {
1671 uint16_t event_idx
= supported_event_map
[new_event
];
1672 count
= pm_events
[event_idx
].get_count(env
);
1674 env
->cp15
.c14_pmevcntr_delta
[counter
] = count
;
1677 env
->cp15
.c14_pmevtyper
[counter
] = value
& PMXEVTYPER_MASK
;
1678 pmevcntr_op_finish(env
, counter
);
1681 * Attempts to access PMXEVTYPER are CONSTRAINED UNPREDICTABLE when
1682 * PMSELR value is equal to or greater than the number of implemented
1683 * counters, but not equal to 0x1f. We opt to behave as a RAZ/WI.
1687 static uint64_t pmevtyper_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1688 const uint8_t counter
)
1690 if (counter
== 31) {
1691 return env
->cp15
.pmccfiltr_el0
;
1692 } else if (counter
< pmu_num_counters(env
)) {
1693 return env
->cp15
.c14_pmevtyper
[counter
];
1696 * We opt to behave as a RAZ/WI when attempts to access PMXEVTYPER
1697 * are CONSTRAINED UNPREDICTABLE. See comments in pmevtyper_write().
1703 static void pmevtyper_writefn(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1706 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1707 pmevtyper_write(env
, ri
, value
, counter
);
1710 static void pmevtyper_rawwrite(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1713 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1714 env
->cp15
.c14_pmevtyper
[counter
] = value
;
1717 * pmevtyper_rawwrite is called between a pair of pmu_op_start and
1718 * pmu_op_finish calls when loading saved state for a migration. Because
1719 * we're potentially updating the type of event here, the value written to
1720 * c14_pmevcntr_delta by the preceding pmu_op_start call may be for a
1721 * different counter type. Therefore, we need to set this value to the
1722 * current count for the counter type we're writing so that pmu_op_finish
1723 * has the correct count for its calculation.
1725 uint16_t event
= value
& PMXEVTYPER_EVTCOUNT
;
1726 if (event_supported(event
)) {
1727 uint16_t event_idx
= supported_event_map
[event
];
1728 env
->cp15
.c14_pmevcntr_delta
[counter
] =
1729 pm_events
[event_idx
].get_count(env
);
1733 static uint64_t pmevtyper_readfn(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1735 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1736 return pmevtyper_read(env
, ri
, counter
);
1739 static void pmxevtyper_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1742 pmevtyper_write(env
, ri
, value
, env
->cp15
.c9_pmselr
& 31);
1745 static uint64_t pmxevtyper_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1747 return pmevtyper_read(env
, ri
, env
->cp15
.c9_pmselr
& 31);
1750 static void pmevcntr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1751 uint64_t value
, uint8_t counter
)
1753 if (!cpu_isar_feature(any_pmuv3p5
, env_archcpu(env
))) {
1754 /* Before FEAT_PMUv3p5, top 32 bits of event counters are RES0 */
1755 value
&= MAKE_64BIT_MASK(0, 32);
1757 if (counter
< pmu_num_counters(env
)) {
1758 pmevcntr_op_start(env
, counter
);
1759 env
->cp15
.c14_pmevcntr
[counter
] = value
;
1760 pmevcntr_op_finish(env
, counter
);
1763 * We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR
1764 * are CONSTRAINED UNPREDICTABLE.
1768 static uint64_t pmevcntr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1771 if (counter
< pmu_num_counters(env
)) {
1773 pmevcntr_op_start(env
, counter
);
1774 ret
= env
->cp15
.c14_pmevcntr
[counter
];
1775 pmevcntr_op_finish(env
, counter
);
1776 if (!cpu_isar_feature(any_pmuv3p5
, env_archcpu(env
))) {
1777 /* Before FEAT_PMUv3p5, top 32 bits of event counters are RES0 */
1778 ret
&= MAKE_64BIT_MASK(0, 32);
1783 * We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR
1784 * are CONSTRAINED UNPREDICTABLE.
1790 static void pmevcntr_writefn(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1793 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1794 pmevcntr_write(env
, ri
, value
, counter
);
1797 static uint64_t pmevcntr_readfn(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1799 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1800 return pmevcntr_read(env
, ri
, counter
);
1803 static void pmevcntr_rawwrite(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1806 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1807 assert(counter
< pmu_num_counters(env
));
1808 env
->cp15
.c14_pmevcntr
[counter
] = value
;
1809 pmevcntr_write(env
, ri
, value
, counter
);
1812 static uint64_t pmevcntr_rawread(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1814 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1815 assert(counter
< pmu_num_counters(env
));
1816 return env
->cp15
.c14_pmevcntr
[counter
];
1819 static void pmxevcntr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1822 pmevcntr_write(env
, ri
, value
, env
->cp15
.c9_pmselr
& 31);
1825 static uint64_t pmxevcntr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1827 return pmevcntr_read(env
, ri
, env
->cp15
.c9_pmselr
& 31);
1830 static void pmuserenr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1833 if (arm_feature(env
, ARM_FEATURE_V8
)) {
1834 env
->cp15
.c9_pmuserenr
= value
& 0xf;
1836 env
->cp15
.c9_pmuserenr
= value
& 1;
1840 static void pmintenset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1843 /* We have no event counters so only the C bit can be changed */
1844 value
&= pmu_counter_mask(env
);
1845 env
->cp15
.c9_pminten
|= value
;
1846 pmu_update_irq(env
);
1849 static void pmintenclr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1852 value
&= pmu_counter_mask(env
);
1853 env
->cp15
.c9_pminten
&= ~value
;
1854 pmu_update_irq(env
);
1857 static void vbar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1861 * Note that even though the AArch64 view of this register has bits
1862 * [10:0] all RES0 we can only mask the bottom 5, to comply with the
1863 * architectural requirements for bits which are RES0 only in some
1864 * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7
1865 * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.)
1867 raw_write(env
, ri
, value
& ~0x1FULL
);
1870 static void scr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
1872 /* Begin with base v8.0 state. */
1873 uint64_t valid_mask
= 0x3fff;
1874 ARMCPU
*cpu
= env_archcpu(env
);
1878 * Because SCR_EL3 is the "real" cpreg and SCR is the alias, reset always
1879 * passes the reginfo for SCR_EL3, which has type ARM_CP_STATE_AA64.
1880 * Instead, choose the format based on the mode of EL3.
1882 if (arm_el_is_aa64(env
, 3)) {
1883 value
|= SCR_FW
| SCR_AW
; /* RES1 */
1884 valid_mask
&= ~SCR_NET
; /* RES0 */
1886 if (!cpu_isar_feature(aa64_aa32_el1
, cpu
) &&
1887 !cpu_isar_feature(aa64_aa32_el2
, cpu
)) {
1888 value
|= SCR_RW
; /* RAO/WI */
1890 if (cpu_isar_feature(aa64_ras
, cpu
)) {
1891 valid_mask
|= SCR_TERR
;
1893 if (cpu_isar_feature(aa64_lor
, cpu
)) {
1894 valid_mask
|= SCR_TLOR
;
1896 if (cpu_isar_feature(aa64_pauth
, cpu
)) {
1897 valid_mask
|= SCR_API
| SCR_APK
;
1899 if (cpu_isar_feature(aa64_sel2
, cpu
)) {
1900 valid_mask
|= SCR_EEL2
;
1901 } else if (cpu_isar_feature(aa64_rme
, cpu
)) {
1902 /* With RME and without SEL2, NS is RES1 (R_GSWWH, I_DJJQJ). */
1905 if (cpu_isar_feature(aa64_mte
, cpu
)) {
1906 valid_mask
|= SCR_ATA
;
1908 if (cpu_isar_feature(aa64_scxtnum
, cpu
)) {
1909 valid_mask
|= SCR_ENSCXT
;
1911 if (cpu_isar_feature(aa64_doublefault
, cpu
)) {
1912 valid_mask
|= SCR_EASE
| SCR_NMEA
;
1914 if (cpu_isar_feature(aa64_sme
, cpu
)) {
1915 valid_mask
|= SCR_ENTP2
;
1917 if (cpu_isar_feature(aa64_hcx
, cpu
)) {
1918 valid_mask
|= SCR_HXEN
;
1920 if (cpu_isar_feature(aa64_fgt
, cpu
)) {
1921 valid_mask
|= SCR_FGTEN
;
1923 if (cpu_isar_feature(aa64_rme
, cpu
)) {
1924 valid_mask
|= SCR_NSE
| SCR_GPF
;
1927 valid_mask
&= ~(SCR_RW
| SCR_ST
);
1928 if (cpu_isar_feature(aa32_ras
, cpu
)) {
1929 valid_mask
|= SCR_TERR
;
1933 if (!arm_feature(env
, ARM_FEATURE_EL2
)) {
1934 valid_mask
&= ~SCR_HCE
;
1937 * On ARMv7, SMD (or SCD as it is called in v7) is only
1938 * supported if EL2 exists. The bit is UNK/SBZP when
1939 * EL2 is unavailable. In QEMU ARMv7, we force it to always zero
1940 * when EL2 is unavailable.
1941 * On ARMv8, this bit is always available.
1943 if (arm_feature(env
, ARM_FEATURE_V7
) &&
1944 !arm_feature(env
, ARM_FEATURE_V8
)) {
1945 valid_mask
&= ~SCR_SMD
;
1949 /* Clear all-context RES0 bits. */
1950 value
&= valid_mask
;
1951 changed
= env
->cp15
.scr_el3
^ value
;
1952 env
->cp15
.scr_el3
= value
;
1955 * If SCR_EL3.{NS,NSE} changes, i.e. change of security state,
1956 * we must invalidate all TLBs below EL3.
1958 if (changed
& (SCR_NS
| SCR_NSE
)) {
1959 tlb_flush_by_mmuidx(env_cpu(env
), (ARMMMUIdxBit_E10_0
|
1960 ARMMMUIdxBit_E20_0
|
1961 ARMMMUIdxBit_E10_1
|
1962 ARMMMUIdxBit_E20_2
|
1963 ARMMMUIdxBit_E10_1_PAN
|
1964 ARMMMUIdxBit_E20_2_PAN
|
1969 static void scr_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1972 * scr_write will set the RES1 bits on an AArch64-only CPU.
1973 * The reset value will be 0x30 on an AArch64-only CPU and 0 otherwise.
1975 scr_write(env
, ri
, 0);
1978 static CPAccessResult
access_tid4(CPUARMState
*env
,
1979 const ARMCPRegInfo
*ri
,
1982 if (arm_current_el(env
) == 1 &&
1983 (arm_hcr_el2_eff(env
) & (HCR_TID2
| HCR_TID4
))) {
1984 return CP_ACCESS_TRAP_EL2
;
1987 return CP_ACCESS_OK
;
1990 static uint64_t ccsidr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1992 ARMCPU
*cpu
= env_archcpu(env
);
1995 * Acquire the CSSELR index from the bank corresponding to the CCSIDR
1998 uint32_t index
= A32_BANKED_REG_GET(env
, csselr
,
1999 ri
->secure
& ARM_CP_SECSTATE_S
);
2001 return cpu
->ccsidr
[index
];
2004 static void csselr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2007 raw_write(env
, ri
, value
& 0xf);
2010 static uint64_t isr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2012 CPUState
*cs
= env_cpu(env
);
2013 bool el1
= arm_current_el(env
) == 1;
2014 uint64_t hcr_el2
= el1
? arm_hcr_el2_eff(env
) : 0;
2017 if (hcr_el2
& HCR_IMO
) {
2018 if (cs
->interrupt_request
& CPU_INTERRUPT_VIRQ
) {
2022 if (cs
->interrupt_request
& CPU_INTERRUPT_HARD
) {
2027 if (hcr_el2
& HCR_FMO
) {
2028 if (cs
->interrupt_request
& CPU_INTERRUPT_VFIQ
) {
2032 if (cs
->interrupt_request
& CPU_INTERRUPT_FIQ
) {
2037 if (hcr_el2
& HCR_AMO
) {
2038 if (cs
->interrupt_request
& CPU_INTERRUPT_VSERR
) {
2046 static CPAccessResult
access_aa64_tid1(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2049 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TID1
)) {
2050 return CP_ACCESS_TRAP_EL2
;
2053 return CP_ACCESS_OK
;
2056 static CPAccessResult
access_aa32_tid1(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2059 if (arm_feature(env
, ARM_FEATURE_V8
)) {
2060 return access_aa64_tid1(env
, ri
, isread
);
2063 return CP_ACCESS_OK
;
2066 static const ARMCPRegInfo v7_cp_reginfo
[] = {
2067 /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
2068 { .name
= "NOP", .cp
= 15, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 4,
2069 .access
= PL1_W
, .type
= ARM_CP_NOP
},
2071 * Performance monitors are implementation defined in v7,
2072 * but with an ARM recommended set of registers, which we
2075 * Performance registers fall into three categories:
2076 * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
2077 * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
2078 * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
2079 * For the cases controlled by PMUSERENR we must set .access to PL0_RW
2080 * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
2082 { .name
= "PMCNTENSET", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 1,
2083 .access
= PL0_RW
, .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2084 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcnten
),
2085 .writefn
= pmcntenset_write
,
2086 .accessfn
= pmreg_access
,
2088 .raw_writefn
= raw_write
},
2089 { .name
= "PMCNTENSET_EL0", .state
= ARM_CP_STATE_AA64
, .type
= ARM_CP_IO
,
2090 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 1,
2091 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2093 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcnten
), .resetvalue
= 0,
2094 .writefn
= pmcntenset_write
, .raw_writefn
= raw_write
},
2095 { .name
= "PMCNTENCLR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 2,
2097 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcnten
),
2098 .accessfn
= pmreg_access
,
2100 .writefn
= pmcntenclr_write
,
2101 .type
= ARM_CP_ALIAS
| ARM_CP_IO
},
2102 { .name
= "PMCNTENCLR_EL0", .state
= ARM_CP_STATE_AA64
,
2103 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 2,
2104 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2106 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2107 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcnten
),
2108 .writefn
= pmcntenclr_write
},
2109 { .name
= "PMOVSR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 3,
2110 .access
= PL0_RW
, .type
= ARM_CP_IO
,
2111 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmovsr
),
2112 .accessfn
= pmreg_access
,
2114 .writefn
= pmovsr_write
,
2115 .raw_writefn
= raw_write
},
2116 { .name
= "PMOVSCLR_EL0", .state
= ARM_CP_STATE_AA64
,
2117 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 3,
2118 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2120 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2121 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmovsr
),
2122 .writefn
= pmovsr_write
,
2123 .raw_writefn
= raw_write
},
2124 { .name
= "PMSWINC", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 4,
2125 .access
= PL0_W
, .accessfn
= pmreg_access_swinc
,
2126 .fgt
= FGT_PMSWINC_EL0
,
2127 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2128 .writefn
= pmswinc_write
},
2129 { .name
= "PMSWINC_EL0", .state
= ARM_CP_STATE_AA64
,
2130 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 4,
2131 .access
= PL0_W
, .accessfn
= pmreg_access_swinc
,
2132 .fgt
= FGT_PMSWINC_EL0
,
2133 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2134 .writefn
= pmswinc_write
},
2135 { .name
= "PMSELR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 5,
2136 .access
= PL0_RW
, .type
= ARM_CP_ALIAS
,
2137 .fgt
= FGT_PMSELR_EL0
,
2138 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmselr
),
2139 .accessfn
= pmreg_access_selr
, .writefn
= pmselr_write
,
2140 .raw_writefn
= raw_write
},
2141 { .name
= "PMSELR_EL0", .state
= ARM_CP_STATE_AA64
,
2142 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 5,
2143 .access
= PL0_RW
, .accessfn
= pmreg_access_selr
,
2144 .fgt
= FGT_PMSELR_EL0
,
2145 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmselr
),
2146 .writefn
= pmselr_write
, .raw_writefn
= raw_write
, },
2147 { .name
= "PMCCNTR", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 0,
2148 .access
= PL0_RW
, .resetvalue
= 0, .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2149 .fgt
= FGT_PMCCNTR_EL0
,
2150 .readfn
= pmccntr_read
, .writefn
= pmccntr_write32
,
2151 .accessfn
= pmreg_access_ccntr
},
2152 { .name
= "PMCCNTR_EL0", .state
= ARM_CP_STATE_AA64
,
2153 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 13, .opc2
= 0,
2154 .access
= PL0_RW
, .accessfn
= pmreg_access_ccntr
,
2155 .fgt
= FGT_PMCCNTR_EL0
,
2157 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_ccnt
),
2158 .readfn
= pmccntr_read
, .writefn
= pmccntr_write
,
2159 .raw_readfn
= raw_read
, .raw_writefn
= raw_write
, },
2160 { .name
= "PMCCFILTR", .cp
= 15, .opc1
= 0, .crn
= 14, .crm
= 15, .opc2
= 7,
2161 .writefn
= pmccfiltr_write_a32
, .readfn
= pmccfiltr_read_a32
,
2162 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2163 .fgt
= FGT_PMCCFILTR_EL0
,
2164 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2166 { .name
= "PMCCFILTR_EL0", .state
= ARM_CP_STATE_AA64
,
2167 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 15, .opc2
= 7,
2168 .writefn
= pmccfiltr_write
, .raw_writefn
= raw_write
,
2169 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2170 .fgt
= FGT_PMCCFILTR_EL0
,
2172 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmccfiltr_el0
),
2174 { .name
= "PMXEVTYPER", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 1,
2175 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2176 .accessfn
= pmreg_access
,
2177 .fgt
= FGT_PMEVTYPERN_EL0
,
2178 .writefn
= pmxevtyper_write
, .readfn
= pmxevtyper_read
},
2179 { .name
= "PMXEVTYPER_EL0", .state
= ARM_CP_STATE_AA64
,
2180 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 13, .opc2
= 1,
2181 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2182 .accessfn
= pmreg_access
,
2183 .fgt
= FGT_PMEVTYPERN_EL0
,
2184 .writefn
= pmxevtyper_write
, .readfn
= pmxevtyper_read
},
2185 { .name
= "PMXEVCNTR", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 2,
2186 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2187 .accessfn
= pmreg_access_xevcntr
,
2188 .fgt
= FGT_PMEVCNTRN_EL0
,
2189 .writefn
= pmxevcntr_write
, .readfn
= pmxevcntr_read
},
2190 { .name
= "PMXEVCNTR_EL0", .state
= ARM_CP_STATE_AA64
,
2191 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 13, .opc2
= 2,
2192 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2193 .accessfn
= pmreg_access_xevcntr
,
2194 .fgt
= FGT_PMEVCNTRN_EL0
,
2195 .writefn
= pmxevcntr_write
, .readfn
= pmxevcntr_read
},
2196 { .name
= "PMUSERENR", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 0,
2197 .access
= PL0_R
| PL1_RW
, .accessfn
= access_tpm
,
2198 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmuserenr
),
2200 .writefn
= pmuserenr_write
, .raw_writefn
= raw_write
},
2201 { .name
= "PMUSERENR_EL0", .state
= ARM_CP_STATE_AA64
,
2202 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 14, .opc2
= 0,
2203 .access
= PL0_R
| PL1_RW
, .accessfn
= access_tpm
, .type
= ARM_CP_ALIAS
,
2204 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmuserenr
),
2206 .writefn
= pmuserenr_write
, .raw_writefn
= raw_write
},
2207 { .name
= "PMINTENSET", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 1,
2208 .access
= PL1_RW
, .accessfn
= access_tpm
,
2210 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2211 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pminten
),
2213 .writefn
= pmintenset_write
, .raw_writefn
= raw_write
},
2214 { .name
= "PMINTENSET_EL1", .state
= ARM_CP_STATE_AA64
,
2215 .opc0
= 3, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 1,
2216 .access
= PL1_RW
, .accessfn
= access_tpm
,
2219 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
2220 .writefn
= pmintenset_write
, .raw_writefn
= raw_write
,
2221 .resetvalue
= 0x0 },
2222 { .name
= "PMINTENCLR", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 2,
2223 .access
= PL1_RW
, .accessfn
= access_tpm
,
2225 .type
= ARM_CP_ALIAS
| ARM_CP_IO
| ARM_CP_NO_RAW
,
2226 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
2227 .writefn
= pmintenclr_write
, },
2228 { .name
= "PMINTENCLR_EL1", .state
= ARM_CP_STATE_AA64
,
2229 .opc0
= 3, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 2,
2230 .access
= PL1_RW
, .accessfn
= access_tpm
,
2232 .type
= ARM_CP_ALIAS
| ARM_CP_IO
| ARM_CP_NO_RAW
,
2233 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
2234 .writefn
= pmintenclr_write
},
2235 { .name
= "CCSIDR", .state
= ARM_CP_STATE_BOTH
,
2236 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= 0,
2238 .accessfn
= access_tid4
,
2239 .fgt
= FGT_CCSIDR_EL1
,
2240 .readfn
= ccsidr_read
, .type
= ARM_CP_NO_RAW
},
2241 { .name
= "CSSELR", .state
= ARM_CP_STATE_BOTH
,
2242 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 2, .opc2
= 0,
2244 .accessfn
= access_tid4
,
2245 .fgt
= FGT_CSSELR_EL1
,
2246 .writefn
= csselr_write
, .resetvalue
= 0,
2247 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.csselr_s
),
2248 offsetof(CPUARMState
, cp15
.csselr_ns
) } },
2250 * Auxiliary ID register: this actually has an IMPDEF value but for now
2251 * just RAZ for all cores:
2253 { .name
= "AIDR", .state
= ARM_CP_STATE_BOTH
,
2254 .opc0
= 3, .opc1
= 1, .crn
= 0, .crm
= 0, .opc2
= 7,
2255 .access
= PL1_R
, .type
= ARM_CP_CONST
,
2256 .accessfn
= access_aa64_tid1
,
2257 .fgt
= FGT_AIDR_EL1
,
2260 * Auxiliary fault status registers: these also are IMPDEF, and we
2261 * choose to RAZ/WI for all cores.
2263 { .name
= "AFSR0_EL1", .state
= ARM_CP_STATE_BOTH
,
2264 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 1, .opc2
= 0,
2265 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
2266 .fgt
= FGT_AFSR0_EL1
,
2267 .nv2_redirect_offset
= 0x128 | NV2_REDIR_NV1
,
2268 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2269 { .name
= "AFSR1_EL1", .state
= ARM_CP_STATE_BOTH
,
2270 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 1, .opc2
= 1,
2271 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
2272 .fgt
= FGT_AFSR1_EL1
,
2273 .nv2_redirect_offset
= 0x130 | NV2_REDIR_NV1
,
2274 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2276 * MAIR can just read-as-written because we don't implement caches
2277 * and so don't need to care about memory attributes.
2279 { .name
= "MAIR_EL1", .state
= ARM_CP_STATE_AA64
,
2280 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 0,
2281 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
2282 .fgt
= FGT_MAIR_EL1
,
2283 .nv2_redirect_offset
= 0x140 | NV2_REDIR_NV1
,
2284 .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[1]),
2286 { .name
= "MAIR_EL3", .state
= ARM_CP_STATE_AA64
,
2287 .opc0
= 3, .opc1
= 6, .crn
= 10, .crm
= 2, .opc2
= 0,
2288 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[3]),
2291 * For non-long-descriptor page tables these are PRRR and NMRR;
2292 * regardless they still act as reads-as-written for QEMU.
2295 * MAIR0/1 are defined separately from their 64-bit counterpart which
2296 * allows them to assign the correct fieldoffset based on the endianness
2297 * handled in the field definitions.
2299 { .name
= "MAIR0", .state
= ARM_CP_STATE_AA32
,
2300 .cp
= 15, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 0,
2301 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
2302 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.mair0_s
),
2303 offsetof(CPUARMState
, cp15
.mair0_ns
) },
2304 .resetfn
= arm_cp_reset_ignore
},
2305 { .name
= "MAIR1", .state
= ARM_CP_STATE_AA32
,
2306 .cp
= 15, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 1,
2307 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
2308 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.mair1_s
),
2309 offsetof(CPUARMState
, cp15
.mair1_ns
) },
2310 .resetfn
= arm_cp_reset_ignore
},
2311 { .name
= "ISR_EL1", .state
= ARM_CP_STATE_BOTH
,
2312 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 1, .opc2
= 0,
2314 .type
= ARM_CP_NO_RAW
, .access
= PL1_R
, .readfn
= isr_read
},
2315 /* 32 bit ITLB invalidates */
2316 { .name
= "ITLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 0,
2317 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2318 .writefn
= tlbiall_write
},
2319 { .name
= "ITLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 1,
2320 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2321 .writefn
= tlbimva_write
},
2322 { .name
= "ITLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 2,
2323 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2324 .writefn
= tlbiasid_write
},
2325 /* 32 bit DTLB invalidates */
2326 { .name
= "DTLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 0,
2327 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2328 .writefn
= tlbiall_write
},
2329 { .name
= "DTLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 1,
2330 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2331 .writefn
= tlbimva_write
},
2332 { .name
= "DTLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 2,
2333 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2334 .writefn
= tlbiasid_write
},
2335 /* 32 bit TLB invalidates */
2336 { .name
= "TLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 0,
2337 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2338 .writefn
= tlbiall_write
},
2339 { .name
= "TLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 1,
2340 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2341 .writefn
= tlbimva_write
},
2342 { .name
= "TLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 2,
2343 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2344 .writefn
= tlbiasid_write
},
2345 { .name
= "TLBIMVAA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 3,
2346 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2347 .writefn
= tlbimvaa_write
},
2350 static const ARMCPRegInfo v7mp_cp_reginfo
[] = {
2351 /* 32 bit TLB invalidates, Inner Shareable */
2352 { .name
= "TLBIALLIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 0,
2353 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlbis
,
2354 .writefn
= tlbiall_is_write
},
2355 { .name
= "TLBIMVAIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 1,
2356 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlbis
,
2357 .writefn
= tlbimva_is_write
},
2358 { .name
= "TLBIASIDIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 2,
2359 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlbis
,
2360 .writefn
= tlbiasid_is_write
},
2361 { .name
= "TLBIMVAAIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 3,
2362 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlbis
,
2363 .writefn
= tlbimvaa_is_write
},
2366 static const ARMCPRegInfo pmovsset_cp_reginfo
[] = {
2367 /* PMOVSSET is not implemented in v7 before v7ve */
2368 { .name
= "PMOVSSET", .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 3,
2369 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2371 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2372 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmovsr
),
2373 .writefn
= pmovsset_write
,
2374 .raw_writefn
= raw_write
},
2375 { .name
= "PMOVSSET_EL0", .state
= ARM_CP_STATE_AA64
,
2376 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 14, .opc2
= 3,
2377 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2379 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2380 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmovsr
),
2381 .writefn
= pmovsset_write
,
2382 .raw_writefn
= raw_write
},
2385 static void teecr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2392 static CPAccessResult
teecr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2396 * HSTR.TTEE only exists in v7A, not v8A, but v8A doesn't have T2EE
2397 * at all, so we don't need to check whether we're v8A.
2399 if (arm_current_el(env
) < 2 && !arm_is_secure_below_el3(env
) &&
2400 (env
->cp15
.hstr_el2
& HSTR_TTEE
)) {
2401 return CP_ACCESS_TRAP_EL2
;
2403 return CP_ACCESS_OK
;
2406 static CPAccessResult
teehbr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2409 if (arm_current_el(env
) == 0 && (env
->teecr
& 1)) {
2410 return CP_ACCESS_TRAP
;
2412 return teecr_access(env
, ri
, isread
);
2415 static const ARMCPRegInfo t2ee_cp_reginfo
[] = {
2416 { .name
= "TEECR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 6, .opc2
= 0,
2417 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, teecr
),
2419 .writefn
= teecr_write
, .accessfn
= teecr_access
},
2420 { .name
= "TEEHBR", .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 6, .opc2
= 0,
2421 .access
= PL0_RW
, .fieldoffset
= offsetof(CPUARMState
, teehbr
),
2422 .accessfn
= teehbr_access
, .resetvalue
= 0 },
2425 static const ARMCPRegInfo v6k_cp_reginfo
[] = {
2426 { .name
= "TPIDR_EL0", .state
= ARM_CP_STATE_AA64
,
2427 .opc0
= 3, .opc1
= 3, .opc2
= 2, .crn
= 13, .crm
= 0,
2429 .fgt
= FGT_TPIDR_EL0
,
2430 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[0]), .resetvalue
= 0 },
2431 { .name
= "TPIDRURW", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 2,
2433 .fgt
= FGT_TPIDR_EL0
,
2434 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidrurw_s
),
2435 offsetoflow32(CPUARMState
, cp15
.tpidrurw_ns
) },
2436 .resetfn
= arm_cp_reset_ignore
},
2437 { .name
= "TPIDRRO_EL0", .state
= ARM_CP_STATE_AA64
,
2438 .opc0
= 3, .opc1
= 3, .opc2
= 3, .crn
= 13, .crm
= 0,
2439 .access
= PL0_R
| PL1_W
,
2440 .fgt
= FGT_TPIDRRO_EL0
,
2441 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidrro_el
[0]),
2443 { .name
= "TPIDRURO", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 3,
2444 .access
= PL0_R
| PL1_W
,
2445 .fgt
= FGT_TPIDRRO_EL0
,
2446 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidruro_s
),
2447 offsetoflow32(CPUARMState
, cp15
.tpidruro_ns
) },
2448 .resetfn
= arm_cp_reset_ignore
},
2449 { .name
= "TPIDR_EL1", .state
= ARM_CP_STATE_AA64
,
2450 .opc0
= 3, .opc1
= 0, .opc2
= 4, .crn
= 13, .crm
= 0,
2452 .fgt
= FGT_TPIDR_EL1
,
2453 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[1]), .resetvalue
= 0 },
2454 { .name
= "TPIDRPRW", .opc1
= 0, .cp
= 15, .crn
= 13, .crm
= 0, .opc2
= 4,
2456 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidrprw_s
),
2457 offsetoflow32(CPUARMState
, cp15
.tpidrprw_ns
) },
2461 #ifndef CONFIG_USER_ONLY
2463 static CPAccessResult
gt_cntfrq_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2467 * CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero.
2468 * Writable only at the highest implemented exception level.
2470 int el
= arm_current_el(env
);
2476 hcr
= arm_hcr_el2_eff(env
);
2477 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
2478 cntkctl
= env
->cp15
.cnthctl_el2
;
2480 cntkctl
= env
->cp15
.c14_cntkctl
;
2482 if (!extract32(cntkctl
, 0, 2)) {
2483 return CP_ACCESS_TRAP
;
2487 if (!isread
&& ri
->state
== ARM_CP_STATE_AA32
&&
2488 arm_is_secure_below_el3(env
)) {
2489 /* Accesses from 32-bit Secure EL1 UNDEF (*not* trap to EL3!) */
2490 return CP_ACCESS_TRAP_UNCATEGORIZED
;
2498 if (!isread
&& el
< arm_highest_el(env
)) {
2499 return CP_ACCESS_TRAP_UNCATEGORIZED
;
2502 return CP_ACCESS_OK
;
2505 static CPAccessResult
gt_counter_access(CPUARMState
*env
, int timeridx
,
2508 unsigned int cur_el
= arm_current_el(env
);
2509 bool has_el2
= arm_is_el2_enabled(env
);
2510 uint64_t hcr
= arm_hcr_el2_eff(env
);
2514 /* If HCR_EL2.<E2H,TGE> == '11': check CNTHCTL_EL2.EL0[PV]CTEN. */
2515 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
2516 return (extract32(env
->cp15
.cnthctl_el2
, timeridx
, 1)
2517 ? CP_ACCESS_OK
: CP_ACCESS_TRAP_EL2
);
2520 /* CNT[PV]CT: not visible from PL0 if EL0[PV]CTEN is zero */
2521 if (!extract32(env
->cp15
.c14_cntkctl
, timeridx
, 1)) {
2522 return CP_ACCESS_TRAP
;
2526 /* Check CNTHCTL_EL2.EL1PCTEN, which changes location based on E2H. */
2527 if (has_el2
&& timeridx
== GTIMER_PHYS
&&
2529 ? !extract32(env
->cp15
.cnthctl_el2
, 10, 1)
2530 : !extract32(env
->cp15
.cnthctl_el2
, 0, 1))) {
2531 return CP_ACCESS_TRAP_EL2
;
2533 if (has_el2
&& timeridx
== GTIMER_VIRT
) {
2534 if (FIELD_EX64(env
->cp15
.cnthctl_el2
, CNTHCTL
, EL1TVCT
)) {
2535 return CP_ACCESS_TRAP_EL2
;
2540 return CP_ACCESS_OK
;
2543 static CPAccessResult
gt_timer_access(CPUARMState
*env
, int timeridx
,
2546 unsigned int cur_el
= arm_current_el(env
);
2547 bool has_el2
= arm_is_el2_enabled(env
);
2548 uint64_t hcr
= arm_hcr_el2_eff(env
);
2552 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
2553 /* If HCR_EL2.<E2H,TGE> == '11': check CNTHCTL_EL2.EL0[PV]TEN. */
2554 return (extract32(env
->cp15
.cnthctl_el2
, 9 - timeridx
, 1)
2555 ? CP_ACCESS_OK
: CP_ACCESS_TRAP_EL2
);
2559 * CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from
2560 * EL0 if EL0[PV]TEN is zero.
2562 if (!extract32(env
->cp15
.c14_cntkctl
, 9 - timeridx
, 1)) {
2563 return CP_ACCESS_TRAP
;
2568 if (has_el2
&& timeridx
== GTIMER_PHYS
) {
2569 if (hcr
& HCR_E2H
) {
2570 /* If HCR_EL2.<E2H,TGE> == '10': check CNTHCTL_EL2.EL1PTEN. */
2571 if (!extract32(env
->cp15
.cnthctl_el2
, 11, 1)) {
2572 return CP_ACCESS_TRAP_EL2
;
2575 /* If HCR_EL2.<E2H> == 0: check CNTHCTL_EL2.EL1PCEN. */
2576 if (!extract32(env
->cp15
.cnthctl_el2
, 1, 1)) {
2577 return CP_ACCESS_TRAP_EL2
;
2581 if (has_el2
&& timeridx
== GTIMER_VIRT
) {
2582 if (FIELD_EX64(env
->cp15
.cnthctl_el2
, CNTHCTL
, EL1TVT
)) {
2583 return CP_ACCESS_TRAP_EL2
;
2588 return CP_ACCESS_OK
;
2591 static CPAccessResult
gt_pct_access(CPUARMState
*env
,
2592 const ARMCPRegInfo
*ri
,
2595 return gt_counter_access(env
, GTIMER_PHYS
, isread
);
2598 static CPAccessResult
gt_vct_access(CPUARMState
*env
,
2599 const ARMCPRegInfo
*ri
,
2602 return gt_counter_access(env
, GTIMER_VIRT
, isread
);
2605 static CPAccessResult
gt_ptimer_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2608 return gt_timer_access(env
, GTIMER_PHYS
, isread
);
2611 static CPAccessResult
gt_vtimer_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2614 return gt_timer_access(env
, GTIMER_VIRT
, isread
);
2617 static CPAccessResult
gt_stimer_access(CPUARMState
*env
,
2618 const ARMCPRegInfo
*ri
,
2622 * The AArch64 register view of the secure physical timer is
2623 * always accessible from EL3, and configurably accessible from
2626 switch (arm_current_el(env
)) {
2628 if (!arm_is_secure(env
)) {
2629 return CP_ACCESS_TRAP
;
2631 if (!(env
->cp15
.scr_el3
& SCR_ST
)) {
2632 return CP_ACCESS_TRAP_EL3
;
2634 return CP_ACCESS_OK
;
2637 return CP_ACCESS_TRAP
;
2639 return CP_ACCESS_OK
;
2641 g_assert_not_reached();
2645 static uint64_t gt_get_countervalue(CPUARMState
*env
)
2647 ARMCPU
*cpu
= env_archcpu(env
);
2649 return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) / gt_cntfrq_period_ns(cpu
);
2652 static void gt_update_irq(ARMCPU
*cpu
, int timeridx
)
2654 CPUARMState
*env
= &cpu
->env
;
2655 uint64_t cnthctl
= env
->cp15
.cnthctl_el2
;
2656 ARMSecuritySpace ss
= arm_security_space(env
);
2657 /* ISTATUS && !IMASK */
2658 int irqstate
= (env
->cp15
.c14_timer
[timeridx
].ctl
& 6) == 4;
2661 * If bit CNTHCTL_EL2.CNT[VP]MASK is set, it overrides IMASK.
2662 * It is RES0 in Secure and NonSecure state.
2664 if ((ss
== ARMSS_Root
|| ss
== ARMSS_Realm
) &&
2665 ((timeridx
== GTIMER_VIRT
&& (cnthctl
& R_CNTHCTL_CNTVMASK_MASK
)) ||
2666 (timeridx
== GTIMER_PHYS
&& (cnthctl
& R_CNTHCTL_CNTPMASK_MASK
)))) {
2670 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
], irqstate
);
2671 trace_arm_gt_update_irq(timeridx
, irqstate
);
2674 void gt_rme_post_el_change(ARMCPU
*cpu
, void *ignored
)
2677 * Changing security state between Root and Secure/NonSecure, which may
2678 * happen when switching EL, can change the effective value of CNTHCTL_EL2
2679 * mask bits. Update the IRQ state accordingly.
2681 gt_update_irq(cpu
, GTIMER_VIRT
);
2682 gt_update_irq(cpu
, GTIMER_PHYS
);
2685 static void gt_recalc_timer(ARMCPU
*cpu
, int timeridx
)
2687 ARMGenericTimer
*gt
= &cpu
->env
.cp15
.c14_timer
[timeridx
];
2691 * Timer enabled: calculate and set current ISTATUS, irq, and
2692 * reset timer to when ISTATUS next has to change
2694 uint64_t offset
= timeridx
== GTIMER_VIRT
?
2695 cpu
->env
.cp15
.cntvoff_el2
: 0;
2696 uint64_t count
= gt_get_countervalue(&cpu
->env
);
2697 /* Note that this must be unsigned 64 bit arithmetic: */
2698 int istatus
= count
- offset
>= gt
->cval
;
2701 gt
->ctl
= deposit32(gt
->ctl
, 2, 1, istatus
);
2705 * Next transition is when (count - offset) rolls back over to 0.
2706 * If offset > count then this is when count == offset;
2707 * if offset <= count then this is when count == offset + 2^64
2708 * For the latter case we set nexttick to an "as far in future
2709 * as possible" value and let the code below handle it.
2711 if (offset
> count
) {
2714 nexttick
= UINT64_MAX
;
2718 * Next transition is when (count - offset) == cval, i.e.
2719 * when count == (cval + offset).
2720 * If that would overflow, then again we set up the next interrupt
2721 * for "as far in the future as possible" for the code below.
2723 if (uadd64_overflow(gt
->cval
, offset
, &nexttick
)) {
2724 nexttick
= UINT64_MAX
;
2728 * Note that the desired next expiry time might be beyond the
2729 * signed-64-bit range of a QEMUTimer -- in this case we just
2730 * set the timer for as far in the future as possible. When the
2731 * timer expires we will reset the timer for any remaining period.
2733 if (nexttick
> INT64_MAX
/ gt_cntfrq_period_ns(cpu
)) {
2734 timer_mod_ns(cpu
->gt_timer
[timeridx
], INT64_MAX
);
2736 timer_mod(cpu
->gt_timer
[timeridx
], nexttick
);
2738 trace_arm_gt_recalc(timeridx
, nexttick
);
2740 /* Timer disabled: ISTATUS and timer output always clear */
2742 timer_del(cpu
->gt_timer
[timeridx
]);
2743 trace_arm_gt_recalc_disabled(timeridx
);
2745 gt_update_irq(cpu
, timeridx
);
2748 static void gt_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2751 ARMCPU
*cpu
= env_archcpu(env
);
2753 timer_del(cpu
->gt_timer
[timeridx
]);
2756 static uint64_t gt_cnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2758 return gt_get_countervalue(env
);
2761 static uint64_t gt_virt_cnt_offset(CPUARMState
*env
)
2765 switch (arm_current_el(env
)) {
2767 hcr
= arm_hcr_el2_eff(env
);
2768 if (hcr
& HCR_E2H
) {
2773 hcr
= arm_hcr_el2_eff(env
);
2774 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
2780 return env
->cp15
.cntvoff_el2
;
2783 static uint64_t gt_virt_cnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2785 return gt_get_countervalue(env
) - gt_virt_cnt_offset(env
);
2788 static void gt_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2792 trace_arm_gt_cval_write(timeridx
, value
);
2793 env
->cp15
.c14_timer
[timeridx
].cval
= value
;
2794 gt_recalc_timer(env_archcpu(env
), timeridx
);
2797 static uint64_t gt_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2800 uint64_t offset
= 0;
2804 case GTIMER_HYPVIRT
:
2805 offset
= gt_virt_cnt_offset(env
);
2809 return (uint32_t)(env
->cp15
.c14_timer
[timeridx
].cval
-
2810 (gt_get_countervalue(env
) - offset
));
2813 static void gt_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2817 uint64_t offset
= 0;
2821 case GTIMER_HYPVIRT
:
2822 offset
= gt_virt_cnt_offset(env
);
2826 trace_arm_gt_tval_write(timeridx
, value
);
2827 env
->cp15
.c14_timer
[timeridx
].cval
= gt_get_countervalue(env
) - offset
+
2828 sextract64(value
, 0, 32);
2829 gt_recalc_timer(env_archcpu(env
), timeridx
);
2832 static void gt_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2836 ARMCPU
*cpu
= env_archcpu(env
);
2837 uint32_t oldval
= env
->cp15
.c14_timer
[timeridx
].ctl
;
2839 trace_arm_gt_ctl_write(timeridx
, value
);
2840 env
->cp15
.c14_timer
[timeridx
].ctl
= deposit64(oldval
, 0, 2, value
);
2841 if ((oldval
^ value
) & 1) {
2842 /* Enable toggled */
2843 gt_recalc_timer(cpu
, timeridx
);
2844 } else if ((oldval
^ value
) & 2) {
2846 * IMASK toggled: don't need to recalculate,
2847 * just set the interrupt line based on ISTATUS
2849 trace_arm_gt_imask_toggle(timeridx
);
2850 gt_update_irq(cpu
, timeridx
);
2854 static void gt_phys_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2856 gt_timer_reset(env
, ri
, GTIMER_PHYS
);
2859 static void gt_phys_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2862 gt_cval_write(env
, ri
, GTIMER_PHYS
, value
);
2865 static uint64_t gt_phys_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2867 return gt_tval_read(env
, ri
, GTIMER_PHYS
);
2870 static void gt_phys_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2873 gt_tval_write(env
, ri
, GTIMER_PHYS
, value
);
2876 static void gt_phys_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2879 gt_ctl_write(env
, ri
, GTIMER_PHYS
, value
);
2882 static int gt_phys_redir_timeridx(CPUARMState
*env
)
2884 switch (arm_mmu_idx(env
)) {
2885 case ARMMMUIdx_E20_0
:
2886 case ARMMMUIdx_E20_2
:
2887 case ARMMMUIdx_E20_2_PAN
:
2894 static int gt_virt_redir_timeridx(CPUARMState
*env
)
2896 switch (arm_mmu_idx(env
)) {
2897 case ARMMMUIdx_E20_0
:
2898 case ARMMMUIdx_E20_2
:
2899 case ARMMMUIdx_E20_2_PAN
:
2900 return GTIMER_HYPVIRT
;
2906 static uint64_t gt_phys_redir_cval_read(CPUARMState
*env
,
2907 const ARMCPRegInfo
*ri
)
2909 int timeridx
= gt_phys_redir_timeridx(env
);
2910 return env
->cp15
.c14_timer
[timeridx
].cval
;
2913 static void gt_phys_redir_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2916 int timeridx
= gt_phys_redir_timeridx(env
);
2917 gt_cval_write(env
, ri
, timeridx
, value
);
2920 static uint64_t gt_phys_redir_tval_read(CPUARMState
*env
,
2921 const ARMCPRegInfo
*ri
)
2923 int timeridx
= gt_phys_redir_timeridx(env
);
2924 return gt_tval_read(env
, ri
, timeridx
);
2927 static void gt_phys_redir_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2930 int timeridx
= gt_phys_redir_timeridx(env
);
2931 gt_tval_write(env
, ri
, timeridx
, value
);
2934 static uint64_t gt_phys_redir_ctl_read(CPUARMState
*env
,
2935 const ARMCPRegInfo
*ri
)
2937 int timeridx
= gt_phys_redir_timeridx(env
);
2938 return env
->cp15
.c14_timer
[timeridx
].ctl
;
2941 static void gt_phys_redir_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2944 int timeridx
= gt_phys_redir_timeridx(env
);
2945 gt_ctl_write(env
, ri
, timeridx
, value
);
2948 static void gt_virt_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2950 gt_timer_reset(env
, ri
, GTIMER_VIRT
);
2953 static void gt_virt_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2956 gt_cval_write(env
, ri
, GTIMER_VIRT
, value
);
2959 static uint64_t gt_virt_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2961 return gt_tval_read(env
, ri
, GTIMER_VIRT
);
2964 static void gt_virt_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2967 gt_tval_write(env
, ri
, GTIMER_VIRT
, value
);
2970 static void gt_virt_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2973 gt_ctl_write(env
, ri
, GTIMER_VIRT
, value
);
2976 static void gt_cnthctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2979 ARMCPU
*cpu
= env_archcpu(env
);
2980 uint32_t oldval
= env
->cp15
.cnthctl_el2
;
2981 uint32_t valid_mask
=
2982 R_CNTHCTL_EL0PCTEN_E2H1_MASK
|
2983 R_CNTHCTL_EL0VCTEN_E2H1_MASK
|
2984 R_CNTHCTL_EVNTEN_MASK
|
2985 R_CNTHCTL_EVNTDIR_MASK
|
2986 R_CNTHCTL_EVNTI_MASK
|
2987 R_CNTHCTL_EL0VTEN_MASK
|
2988 R_CNTHCTL_EL0PTEN_MASK
|
2989 R_CNTHCTL_EL1PCTEN_E2H1_MASK
|
2990 R_CNTHCTL_EL1PTEN_MASK
;
2992 if (cpu_isar_feature(aa64_rme
, cpu
)) {
2993 valid_mask
|= R_CNTHCTL_CNTVMASK_MASK
| R_CNTHCTL_CNTPMASK_MASK
;
2995 if (cpu_isar_feature(aa64_ecv_traps
, cpu
)) {
2997 R_CNTHCTL_EL1TVT_MASK
|
2998 R_CNTHCTL_EL1TVCT_MASK
|
2999 R_CNTHCTL_EL1NVPCT_MASK
|
3000 R_CNTHCTL_EL1NVVCT_MASK
|
3001 R_CNTHCTL_EVNTIS_MASK
;
3004 /* Clear RES0 bits */
3005 value
&= valid_mask
;
3007 raw_write(env
, ri
, value
);
3009 if ((oldval
^ value
) & R_CNTHCTL_CNTVMASK_MASK
) {
3010 gt_update_irq(cpu
, GTIMER_VIRT
);
3011 } else if ((oldval
^ value
) & R_CNTHCTL_CNTPMASK_MASK
) {
3012 gt_update_irq(cpu
, GTIMER_PHYS
);
3016 static void gt_cntvoff_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3019 ARMCPU
*cpu
= env_archcpu(env
);
3021 trace_arm_gt_cntvoff_write(value
);
3022 raw_write(env
, ri
, value
);
3023 gt_recalc_timer(cpu
, GTIMER_VIRT
);
3026 static uint64_t gt_virt_redir_cval_read(CPUARMState
*env
,
3027 const ARMCPRegInfo
*ri
)
3029 int timeridx
= gt_virt_redir_timeridx(env
);
3030 return env
->cp15
.c14_timer
[timeridx
].cval
;
3033 static void gt_virt_redir_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3036 int timeridx
= gt_virt_redir_timeridx(env
);
3037 gt_cval_write(env
, ri
, timeridx
, value
);
3040 static uint64_t gt_virt_redir_tval_read(CPUARMState
*env
,
3041 const ARMCPRegInfo
*ri
)
3043 int timeridx
= gt_virt_redir_timeridx(env
);
3044 return gt_tval_read(env
, ri
, timeridx
);
3047 static void gt_virt_redir_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3050 int timeridx
= gt_virt_redir_timeridx(env
);
3051 gt_tval_write(env
, ri
, timeridx
, value
);
3054 static uint64_t gt_virt_redir_ctl_read(CPUARMState
*env
,
3055 const ARMCPRegInfo
*ri
)
3057 int timeridx
= gt_virt_redir_timeridx(env
);
3058 return env
->cp15
.c14_timer
[timeridx
].ctl
;
3061 static void gt_virt_redir_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3064 int timeridx
= gt_virt_redir_timeridx(env
);
3065 gt_ctl_write(env
, ri
, timeridx
, value
);
3068 static void gt_hyp_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3070 gt_timer_reset(env
, ri
, GTIMER_HYP
);
3073 static void gt_hyp_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3076 gt_cval_write(env
, ri
, GTIMER_HYP
, value
);
3079 static uint64_t gt_hyp_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3081 return gt_tval_read(env
, ri
, GTIMER_HYP
);
3084 static void gt_hyp_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3087 gt_tval_write(env
, ri
, GTIMER_HYP
, value
);
3090 static void gt_hyp_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3093 gt_ctl_write(env
, ri
, GTIMER_HYP
, value
);
3096 static void gt_sec_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3098 gt_timer_reset(env
, ri
, GTIMER_SEC
);
3101 static void gt_sec_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3104 gt_cval_write(env
, ri
, GTIMER_SEC
, value
);
3107 static uint64_t gt_sec_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3109 return gt_tval_read(env
, ri
, GTIMER_SEC
);
3112 static void gt_sec_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3115 gt_tval_write(env
, ri
, GTIMER_SEC
, value
);
3118 static void gt_sec_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3121 gt_ctl_write(env
, ri
, GTIMER_SEC
, value
);
3124 static void gt_hv_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3126 gt_timer_reset(env
, ri
, GTIMER_HYPVIRT
);
3129 static void gt_hv_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3132 gt_cval_write(env
, ri
, GTIMER_HYPVIRT
, value
);
3135 static uint64_t gt_hv_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3137 return gt_tval_read(env
, ri
, GTIMER_HYPVIRT
);
3140 static void gt_hv_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3143 gt_tval_write(env
, ri
, GTIMER_HYPVIRT
, value
);
3146 static void gt_hv_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3149 gt_ctl_write(env
, ri
, GTIMER_HYPVIRT
, value
);
3152 void arm_gt_ptimer_cb(void *opaque
)
3154 ARMCPU
*cpu
= opaque
;
3156 gt_recalc_timer(cpu
, GTIMER_PHYS
);
3159 void arm_gt_vtimer_cb(void *opaque
)
3161 ARMCPU
*cpu
= opaque
;
3163 gt_recalc_timer(cpu
, GTIMER_VIRT
);
3166 void arm_gt_htimer_cb(void *opaque
)
3168 ARMCPU
*cpu
= opaque
;
3170 gt_recalc_timer(cpu
, GTIMER_HYP
);
3173 void arm_gt_stimer_cb(void *opaque
)
3175 ARMCPU
*cpu
= opaque
;
3177 gt_recalc_timer(cpu
, GTIMER_SEC
);
3180 void arm_gt_hvtimer_cb(void *opaque
)
3182 ARMCPU
*cpu
= opaque
;
3184 gt_recalc_timer(cpu
, GTIMER_HYPVIRT
);
3187 static void arm_gt_cntfrq_reset(CPUARMState
*env
, const ARMCPRegInfo
*opaque
)
3189 ARMCPU
*cpu
= env_archcpu(env
);
3191 cpu
->env
.cp15
.c14_cntfrq
= cpu
->gt_cntfrq_hz
;
3194 static const ARMCPRegInfo generic_timer_cp_reginfo
[] = {
3196 * Note that CNTFRQ is purely reads-as-written for the benefit
3197 * of software; writing it doesn't actually change the timer frequency.
3198 * Our reset value matches the fixed frequency we implement the timer at.
3200 { .name
= "CNTFRQ", .cp
= 15, .crn
= 14, .crm
= 0, .opc1
= 0, .opc2
= 0,
3201 .type
= ARM_CP_ALIAS
,
3202 .access
= PL1_RW
| PL0_R
, .accessfn
= gt_cntfrq_access
,
3203 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c14_cntfrq
),
3205 { .name
= "CNTFRQ_EL0", .state
= ARM_CP_STATE_AA64
,
3206 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 0,
3207 .access
= PL1_RW
| PL0_R
, .accessfn
= gt_cntfrq_access
,
3208 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntfrq
),
3209 .resetfn
= arm_gt_cntfrq_reset
,
3211 /* overall control: mostly access permissions */
3212 { .name
= "CNTKCTL", .state
= ARM_CP_STATE_BOTH
,
3213 .opc0
= 3, .opc1
= 0, .crn
= 14, .crm
= 1, .opc2
= 0,
3215 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntkctl
),
3218 /* per-timer control */
3219 { .name
= "CNTP_CTL", .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 1,
3220 .secure
= ARM_CP_SECSTATE_NS
,
3221 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL0_RW
,
3222 .accessfn
= gt_ptimer_access
,
3223 .fieldoffset
= offsetoflow32(CPUARMState
,
3224 cp15
.c14_timer
[GTIMER_PHYS
].ctl
),
3225 .readfn
= gt_phys_redir_ctl_read
, .raw_readfn
= raw_read
,
3226 .writefn
= gt_phys_redir_ctl_write
, .raw_writefn
= raw_write
,
3228 { .name
= "CNTP_CTL_S",
3229 .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 1,
3230 .secure
= ARM_CP_SECSTATE_S
,
3231 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL0_RW
,
3232 .accessfn
= gt_ptimer_access
,
3233 .fieldoffset
= offsetoflow32(CPUARMState
,
3234 cp15
.c14_timer
[GTIMER_SEC
].ctl
),
3235 .writefn
= gt_sec_ctl_write
, .raw_writefn
= raw_write
,
3237 { .name
= "CNTP_CTL_EL0", .state
= ARM_CP_STATE_AA64
,
3238 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 1,
3239 .type
= ARM_CP_IO
, .access
= PL0_RW
,
3240 .accessfn
= gt_ptimer_access
,
3241 .nv2_redirect_offset
= 0x180 | NV2_REDIR_NV1
,
3242 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].ctl
),
3244 .readfn
= gt_phys_redir_ctl_read
, .raw_readfn
= raw_read
,
3245 .writefn
= gt_phys_redir_ctl_write
, .raw_writefn
= raw_write
,
3247 { .name
= "CNTV_CTL", .cp
= 15, .crn
= 14, .crm
= 3, .opc1
= 0, .opc2
= 1,
3248 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL0_RW
,
3249 .accessfn
= gt_vtimer_access
,
3250 .fieldoffset
= offsetoflow32(CPUARMState
,
3251 cp15
.c14_timer
[GTIMER_VIRT
].ctl
),
3252 .readfn
= gt_virt_redir_ctl_read
, .raw_readfn
= raw_read
,
3253 .writefn
= gt_virt_redir_ctl_write
, .raw_writefn
= raw_write
,
3255 { .name
= "CNTV_CTL_EL0", .state
= ARM_CP_STATE_AA64
,
3256 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 1,
3257 .type
= ARM_CP_IO
, .access
= PL0_RW
,
3258 .accessfn
= gt_vtimer_access
,
3259 .nv2_redirect_offset
= 0x170 | NV2_REDIR_NV1
,
3260 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].ctl
),
3262 .readfn
= gt_virt_redir_ctl_read
, .raw_readfn
= raw_read
,
3263 .writefn
= gt_virt_redir_ctl_write
, .raw_writefn
= raw_write
,
3265 /* TimerValue views: a 32 bit downcounting view of the underlying state */
3266 { .name
= "CNTP_TVAL", .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 0,
3267 .secure
= ARM_CP_SECSTATE_NS
,
3268 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
3269 .accessfn
= gt_ptimer_access
,
3270 .readfn
= gt_phys_redir_tval_read
, .writefn
= gt_phys_redir_tval_write
,
3272 { .name
= "CNTP_TVAL_S",
3273 .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 0,
3274 .secure
= ARM_CP_SECSTATE_S
,
3275 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
3276 .accessfn
= gt_ptimer_access
,
3277 .readfn
= gt_sec_tval_read
, .writefn
= gt_sec_tval_write
,
3279 { .name
= "CNTP_TVAL_EL0", .state
= ARM_CP_STATE_AA64
,
3280 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 0,
3281 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
3282 .accessfn
= gt_ptimer_access
, .resetfn
= gt_phys_timer_reset
,
3283 .readfn
= gt_phys_redir_tval_read
, .writefn
= gt_phys_redir_tval_write
,
3285 { .name
= "CNTV_TVAL", .cp
= 15, .crn
= 14, .crm
= 3, .opc1
= 0, .opc2
= 0,
3286 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
3287 .accessfn
= gt_vtimer_access
,
3288 .readfn
= gt_virt_redir_tval_read
, .writefn
= gt_virt_redir_tval_write
,
3290 { .name
= "CNTV_TVAL_EL0", .state
= ARM_CP_STATE_AA64
,
3291 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 0,
3292 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
3293 .accessfn
= gt_vtimer_access
, .resetfn
= gt_virt_timer_reset
,
3294 .readfn
= gt_virt_redir_tval_read
, .writefn
= gt_virt_redir_tval_write
,
3296 /* The counter itself */
3297 { .name
= "CNTPCT", .cp
= 15, .crm
= 14, .opc1
= 0,
3298 .access
= PL0_R
, .type
= ARM_CP_64BIT
| ARM_CP_NO_RAW
| ARM_CP_IO
,
3299 .accessfn
= gt_pct_access
,
3300 .readfn
= gt_cnt_read
, .resetfn
= arm_cp_reset_ignore
,
3302 { .name
= "CNTPCT_EL0", .state
= ARM_CP_STATE_AA64
,
3303 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 1,
3304 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
3305 .accessfn
= gt_pct_access
, .readfn
= gt_cnt_read
,
3307 { .name
= "CNTVCT", .cp
= 15, .crm
= 14, .opc1
= 1,
3308 .access
= PL0_R
, .type
= ARM_CP_64BIT
| ARM_CP_NO_RAW
| ARM_CP_IO
,
3309 .accessfn
= gt_vct_access
,
3310 .readfn
= gt_virt_cnt_read
, .resetfn
= arm_cp_reset_ignore
,
3312 { .name
= "CNTVCT_EL0", .state
= ARM_CP_STATE_AA64
,
3313 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 2,
3314 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
3315 .accessfn
= gt_vct_access
, .readfn
= gt_virt_cnt_read
,
3317 /* Comparison value, indicating when the timer goes off */
3318 { .name
= "CNTP_CVAL", .cp
= 15, .crm
= 14, .opc1
= 2,
3319 .secure
= ARM_CP_SECSTATE_NS
,
3321 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
3322 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].cval
),
3323 .accessfn
= gt_ptimer_access
,
3324 .readfn
= gt_phys_redir_cval_read
, .raw_readfn
= raw_read
,
3325 .writefn
= gt_phys_redir_cval_write
, .raw_writefn
= raw_write
,
3327 { .name
= "CNTP_CVAL_S", .cp
= 15, .crm
= 14, .opc1
= 2,
3328 .secure
= ARM_CP_SECSTATE_S
,
3330 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
3331 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_SEC
].cval
),
3332 .accessfn
= gt_ptimer_access
,
3333 .writefn
= gt_sec_cval_write
, .raw_writefn
= raw_write
,
3335 { .name
= "CNTP_CVAL_EL0", .state
= ARM_CP_STATE_AA64
,
3336 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 2,
3339 .nv2_redirect_offset
= 0x178 | NV2_REDIR_NV1
,
3340 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].cval
),
3341 .resetvalue
= 0, .accessfn
= gt_ptimer_access
,
3342 .readfn
= gt_phys_redir_cval_read
, .raw_readfn
= raw_read
,
3343 .writefn
= gt_phys_redir_cval_write
, .raw_writefn
= raw_write
,
3345 { .name
= "CNTV_CVAL", .cp
= 15, .crm
= 14, .opc1
= 3,
3347 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
3348 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].cval
),
3349 .accessfn
= gt_vtimer_access
,
3350 .readfn
= gt_virt_redir_cval_read
, .raw_readfn
= raw_read
,
3351 .writefn
= gt_virt_redir_cval_write
, .raw_writefn
= raw_write
,
3353 { .name
= "CNTV_CVAL_EL0", .state
= ARM_CP_STATE_AA64
,
3354 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 2,
3357 .nv2_redirect_offset
= 0x168 | NV2_REDIR_NV1
,
3358 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].cval
),
3359 .resetvalue
= 0, .accessfn
= gt_vtimer_access
,
3360 .readfn
= gt_virt_redir_cval_read
, .raw_readfn
= raw_read
,
3361 .writefn
= gt_virt_redir_cval_write
, .raw_writefn
= raw_write
,
3364 * Secure timer -- this is actually restricted to only EL3
3365 * and configurably Secure-EL1 via the accessfn.
3367 { .name
= "CNTPS_TVAL_EL1", .state
= ARM_CP_STATE_AA64
,
3368 .opc0
= 3, .opc1
= 7, .crn
= 14, .crm
= 2, .opc2
= 0,
3369 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL1_RW
,
3370 .accessfn
= gt_stimer_access
,
3371 .readfn
= gt_sec_tval_read
,
3372 .writefn
= gt_sec_tval_write
,
3373 .resetfn
= gt_sec_timer_reset
,
3375 { .name
= "CNTPS_CTL_EL1", .state
= ARM_CP_STATE_AA64
,
3376 .opc0
= 3, .opc1
= 7, .crn
= 14, .crm
= 2, .opc2
= 1,
3377 .type
= ARM_CP_IO
, .access
= PL1_RW
,
3378 .accessfn
= gt_stimer_access
,
3379 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_SEC
].ctl
),
3381 .writefn
= gt_sec_ctl_write
, .raw_writefn
= raw_write
,
3383 { .name
= "CNTPS_CVAL_EL1", .state
= ARM_CP_STATE_AA64
,
3384 .opc0
= 3, .opc1
= 7, .crn
= 14, .crm
= 2, .opc2
= 2,
3385 .type
= ARM_CP_IO
, .access
= PL1_RW
,
3386 .accessfn
= gt_stimer_access
,
3387 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_SEC
].cval
),
3388 .writefn
= gt_sec_cval_write
, .raw_writefn
= raw_write
,
3393 * FEAT_ECV adds extra views of CNTVCT_EL0 and CNTPCT_EL0 which
3394 * are "self-synchronizing". For QEMU all sysregs are self-synchronizing,
3395 * so our implementations here are identical to the normal registers.
3397 static const ARMCPRegInfo gen_timer_ecv_cp_reginfo
[] = {
3398 { .name
= "CNTVCTSS", .cp
= 15, .crm
= 14, .opc1
= 9,
3399 .access
= PL0_R
, .type
= ARM_CP_64BIT
| ARM_CP_NO_RAW
| ARM_CP_IO
,
3400 .accessfn
= gt_vct_access
,
3401 .readfn
= gt_virt_cnt_read
, .resetfn
= arm_cp_reset_ignore
,
3403 { .name
= "CNTVCTSS_EL0", .state
= ARM_CP_STATE_AA64
,
3404 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 6,
3405 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
3406 .accessfn
= gt_vct_access
, .readfn
= gt_virt_cnt_read
,
3408 { .name
= "CNTPCTSS", .cp
= 15, .crm
= 14, .opc1
= 8,
3409 .access
= PL0_R
, .type
= ARM_CP_64BIT
| ARM_CP_NO_RAW
| ARM_CP_IO
,
3410 .accessfn
= gt_pct_access
,
3411 .readfn
= gt_cnt_read
, .resetfn
= arm_cp_reset_ignore
,
3413 { .name
= "CNTPCTSS_EL0", .state
= ARM_CP_STATE_AA64
,
3414 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 5,
3415 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
3416 .accessfn
= gt_pct_access
, .readfn
= gt_cnt_read
,
3423 * In user-mode most of the generic timer registers are inaccessible
3424 * however modern kernels (4.12+) allow access to cntvct_el0
3427 static uint64_t gt_virt_cnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3429 ARMCPU
*cpu
= env_archcpu(env
);
3432 * Currently we have no support for QEMUTimer in linux-user so we
3433 * can't call gt_get_countervalue(env), instead we directly
3434 * call the lower level functions.
3436 return cpu_get_clock() / gt_cntfrq_period_ns(cpu
);
3439 static const ARMCPRegInfo generic_timer_cp_reginfo
[] = {
3440 { .name
= "CNTFRQ_EL0", .state
= ARM_CP_STATE_AA64
,
3441 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 0,
3442 .type
= ARM_CP_CONST
, .access
= PL0_R
/* no PL1_RW in linux-user */,
3443 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntfrq
),
3444 .resetvalue
= NANOSECONDS_PER_SECOND
/ GTIMER_SCALE
,
3446 { .name
= "CNTVCT_EL0", .state
= ARM_CP_STATE_AA64
,
3447 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 2,
3448 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
3449 .readfn
= gt_virt_cnt_read
,
3454 * CNTVCTSS_EL0 has the same trap conditions as CNTVCT_EL0, so it also
3455 * is exposed to userspace by Linux.
3457 static const ARMCPRegInfo gen_timer_ecv_cp_reginfo
[] = {
3458 { .name
= "CNTVCTSS_EL0", .state
= ARM_CP_STATE_AA64
,
3459 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 6,
3460 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
3461 .readfn
= gt_virt_cnt_read
,
3467 static void par_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
3469 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
3470 raw_write(env
, ri
, value
);
3471 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
3472 raw_write(env
, ri
, value
& 0xfffff6ff);
3474 raw_write(env
, ri
, value
& 0xfffff1ff);
3478 #ifndef CONFIG_USER_ONLY
3479 /* get_phys_addr() isn't present for user-mode-only targets */
3481 static CPAccessResult
ats_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3486 * The ATS12NSO* operations must trap to EL3 or EL2 if executed in
3487 * Secure EL1 (which can only happen if EL3 is AArch64).
3488 * They are simply UNDEF if executed from NS EL1.
3489 * They function normally from EL2 or EL3.
3491 if (arm_current_el(env
) == 1) {
3492 if (arm_is_secure_below_el3(env
)) {
3493 if (env
->cp15
.scr_el3
& SCR_EEL2
) {
3494 return CP_ACCESS_TRAP_EL2
;
3496 return CP_ACCESS_TRAP_EL3
;
3498 return CP_ACCESS_TRAP_UNCATEGORIZED
;
3501 return CP_ACCESS_OK
;
3505 static int par_el1_shareability(GetPhysAddrResult
*res
)
3508 * The PAR_EL1.SH field must be 0b10 for Device or Normal-NC
3509 * memory -- see pseudocode PAREncodeShareability().
3511 if (((res
->cacheattrs
.attrs
& 0xf0) == 0) ||
3512 res
->cacheattrs
.attrs
== 0x44 || res
->cacheattrs
.attrs
== 0x40) {
3515 return res
->cacheattrs
.shareability
;
3518 static uint64_t do_ats_write(CPUARMState
*env
, uint64_t value
,
3519 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
3520 ARMSecuritySpace ss
)
3524 bool format64
= false;
3525 ARMMMUFaultInfo fi
= {};
3526 GetPhysAddrResult res
= {};
3529 * I_MXTJT: Granule protection checks are not performed on the final address
3530 * of a successful translation.
3532 ret
= get_phys_addr_with_space_nogpc(env
, value
, access_type
, mmu_idx
, ss
,
3536 * ATS operations only do S1 or S1+S2 translations, so we never
3537 * have to deal with the ARMCacheAttrs format for S2 only.
3539 assert(!res
.cacheattrs
.is_s2_format
);
3543 * Some kinds of translation fault must cause exceptions rather
3544 * than being reported in the PAR.
3546 int current_el
= arm_current_el(env
);
3548 uint32_t syn
, fsr
, fsc
;
3549 bool take_exc
= false;
3551 if (fi
.s1ptw
&& current_el
== 1
3552 && arm_mmu_idx_is_stage1_of_2(mmu_idx
)) {
3554 * Synchronous stage 2 fault on an access made as part of the
3555 * translation table walk for AT S1E0* or AT S1E1* insn
3556 * executed from NS EL1. If this is a synchronous external abort
3557 * and SCR_EL3.EA == 1, then we take a synchronous external abort
3558 * to EL3. Otherwise the fault is taken as an exception to EL2,
3559 * and HPFAR_EL2 holds the faulting IPA.
3561 if (fi
.type
== ARMFault_SyncExternalOnWalk
&&
3562 (env
->cp15
.scr_el3
& SCR_EA
)) {
3565 env
->cp15
.hpfar_el2
= extract64(fi
.s2addr
, 12, 47) << 4;
3566 if (arm_is_secure_below_el3(env
) && fi
.s1ns
) {
3567 env
->cp15
.hpfar_el2
|= HPFAR_NS
;
3572 } else if (fi
.type
== ARMFault_SyncExternalOnWalk
) {
3574 * Synchronous external aborts during a translation table walk
3575 * are taken as Data Abort exceptions.
3578 if (current_el
== 3) {
3584 target_el
= exception_target_el(env
);
3590 /* Construct FSR and FSC using same logic as arm_deliver_fault() */
3591 if (target_el
== 2 || arm_el_is_aa64(env
, target_el
) ||
3592 arm_s1_regime_using_lpae_format(env
, mmu_idx
)) {
3593 fsr
= arm_fi_to_lfsc(&fi
);
3594 fsc
= extract32(fsr
, 0, 6);
3596 fsr
= arm_fi_to_sfsc(&fi
);
3600 * Report exception with ESR indicating a fault due to a
3601 * translation table walk for a cache maintenance instruction.
3603 syn
= syn_data_abort_no_iss(current_el
== target_el
, 0,
3604 fi
.ea
, 1, fi
.s1ptw
, 1, fsc
);
3605 env
->exception
.vaddress
= value
;
3606 env
->exception
.fsr
= fsr
;
3607 raise_exception(env
, EXCP_DATA_ABORT
, syn
, target_el
);
3613 } else if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
3616 * * TTBCR.EAE determines whether the result is returned using the
3617 * 32-bit or the 64-bit PAR format
3618 * * Instructions executed in Hyp mode always use the 64bit format
3620 * ATS1S2NSOxx uses the 64bit format if any of the following is true:
3621 * * The Non-secure TTBCR.EAE bit is set to 1
3622 * * The implementation includes EL2, and the value of HCR.VM is 1
3624 * (Note that HCR.DC makes HCR.VM behave as if it is 1.)
3626 * ATS1Hx always uses the 64bit format.
3628 format64
= arm_s1_regime_using_lpae_format(env
, mmu_idx
);
3630 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
3631 if (mmu_idx
== ARMMMUIdx_E10_0
||
3632 mmu_idx
== ARMMMUIdx_E10_1
||
3633 mmu_idx
== ARMMMUIdx_E10_1_PAN
) {
3634 format64
|= env
->cp15
.hcr_el2
& (HCR_VM
| HCR_DC
);
3636 format64
|= arm_current_el(env
) == 2;
3642 /* Create a 64-bit PAR */
3643 par64
= (1 << 11); /* LPAE bit always set */
3645 par64
|= res
.f
.phys_addr
& ~0xfffULL
;
3646 if (!res
.f
.attrs
.secure
) {
3647 par64
|= (1 << 9); /* NS */
3649 par64
|= (uint64_t)res
.cacheattrs
.attrs
<< 56; /* ATTR */
3650 par64
|= par_el1_shareability(&res
) << 7; /* SH */
3652 uint32_t fsr
= arm_fi_to_lfsc(&fi
);
3655 par64
|= (fsr
& 0x3f) << 1; /* FS */
3657 par64
|= (1 << 9); /* S */
3660 par64
|= (1 << 8); /* PTW */
3665 * fsr is a DFSR/IFSR value for the short descriptor
3666 * translation table format (with WnR always clear).
3667 * Convert it to a 32-bit PAR.
3670 /* We do not set any attribute bits in the PAR */
3671 if (res
.f
.lg_page_size
== 24
3672 && arm_feature(env
, ARM_FEATURE_V7
)) {
3673 par64
= (res
.f
.phys_addr
& 0xff000000) | (1 << 1);
3675 par64
= res
.f
.phys_addr
& 0xfffff000;
3677 if (!res
.f
.attrs
.secure
) {
3678 par64
|= (1 << 9); /* NS */
3681 uint32_t fsr
= arm_fi_to_sfsc(&fi
);
3683 par64
= ((fsr
& (1 << 10)) >> 5) | ((fsr
& (1 << 12)) >> 6) |
3684 ((fsr
& 0xf) << 1) | 1;
3689 #endif /* CONFIG_TCG */
3691 static void ats_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
3694 MMUAccessType access_type
= ri
->opc2
& 1 ? MMU_DATA_STORE
: MMU_DATA_LOAD
;
3697 int el
= arm_current_el(env
);
3698 ARMSecuritySpace ss
= arm_security_space(env
);
3700 switch (ri
->opc2
& 6) {
3702 /* stage 1 current state PL1: ATS1CPR, ATS1CPW, ATS1CPRP, ATS1CPWP */
3705 mmu_idx
= ARMMMUIdx_E3
;
3708 g_assert(ss
!= ARMSS_Secure
); /* ARMv8.4-SecEL2 is 64-bit only */
3711 if (ri
->crm
== 9 && arm_pan_enabled(env
)) {
3712 mmu_idx
= ARMMMUIdx_Stage1_E1_PAN
;
3714 mmu_idx
= ARMMMUIdx_Stage1_E1
;
3718 g_assert_not_reached();
3722 /* stage 1 current state PL0: ATS1CUR, ATS1CUW */
3725 mmu_idx
= ARMMMUIdx_E10_0
;
3728 g_assert(ss
!= ARMSS_Secure
); /* ARMv8.4-SecEL2 is 64-bit only */
3729 mmu_idx
= ARMMMUIdx_Stage1_E0
;
3732 mmu_idx
= ARMMMUIdx_Stage1_E0
;
3735 g_assert_not_reached();
3739 /* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */
3740 mmu_idx
= ARMMMUIdx_E10_1
;
3741 ss
= ARMSS_NonSecure
;
3744 /* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */
3745 mmu_idx
= ARMMMUIdx_E10_0
;
3746 ss
= ARMSS_NonSecure
;
3749 g_assert_not_reached();
3752 par64
= do_ats_write(env
, value
, access_type
, mmu_idx
, ss
);
3754 A32_BANKED_CURRENT_REG_SET(env
, par
, par64
);
3756 /* Handled by hardware accelerator. */
3757 g_assert_not_reached();
3758 #endif /* CONFIG_TCG */
3761 static void ats1h_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3765 MMUAccessType access_type
= ri
->opc2
& 1 ? MMU_DATA_STORE
: MMU_DATA_LOAD
;
3768 /* There is no SecureEL2 for AArch32. */
3769 par64
= do_ats_write(env
, value
, access_type
, ARMMMUIdx_E2
,
3772 A32_BANKED_CURRENT_REG_SET(env
, par
, par64
);
3774 /* Handled by hardware accelerator. */
3775 g_assert_not_reached();
3776 #endif /* CONFIG_TCG */
3779 static CPAccessResult
at_e012_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3783 * R_NYXTL: instruction is UNDEFINED if it applies to an Exception level
3784 * lower than EL3 and the combination SCR_EL3.{NSE,NS} is reserved. This can
3785 * only happen when executing at EL3 because that combination also causes an
3786 * illegal exception return. We don't need to check FEAT_RME either, because
3787 * scr_write() ensures that the NSE bit is not set otherwise.
3789 if ((env
->cp15
.scr_el3
& (SCR_NSE
| SCR_NS
)) == SCR_NSE
) {
3790 return CP_ACCESS_TRAP
;
3792 return CP_ACCESS_OK
;
3795 static CPAccessResult
at_s1e2_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3798 if (arm_current_el(env
) == 3 &&
3799 !(env
->cp15
.scr_el3
& (SCR_NS
| SCR_EEL2
))) {
3800 return CP_ACCESS_TRAP
;
3802 return at_e012_access(env
, ri
, isread
);
3805 static CPAccessResult
at_s1e01_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3808 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_AT
)) {
3809 return CP_ACCESS_TRAP_EL2
;
3811 return at_e012_access(env
, ri
, isread
);
3814 static void ats_write64(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3818 MMUAccessType access_type
= ri
->opc2
& 1 ? MMU_DATA_STORE
: MMU_DATA_LOAD
;
3820 uint64_t hcr_el2
= arm_hcr_el2_eff(env
);
3821 bool regime_e20
= (hcr_el2
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
);
3823 switch (ri
->opc2
& 6) {
3826 case 0: /* AT S1E1R, AT S1E1W, AT S1E1RP, AT S1E1WP */
3827 if (ri
->crm
== 9 && arm_pan_enabled(env
)) {
3828 mmu_idx
= regime_e20
?
3829 ARMMMUIdx_E20_2_PAN
: ARMMMUIdx_Stage1_E1_PAN
;
3831 mmu_idx
= regime_e20
? ARMMMUIdx_E20_2
: ARMMMUIdx_Stage1_E1
;
3834 case 4: /* AT S1E2R, AT S1E2W */
3835 mmu_idx
= hcr_el2
& HCR_E2H
? ARMMMUIdx_E20_2
: ARMMMUIdx_E2
;
3837 case 6: /* AT S1E3R, AT S1E3W */
3838 mmu_idx
= ARMMMUIdx_E3
;
3841 g_assert_not_reached();
3844 case 2: /* AT S1E0R, AT S1E0W */
3845 mmu_idx
= regime_e20
? ARMMMUIdx_E20_0
: ARMMMUIdx_Stage1_E0
;
3847 case 4: /* AT S12E1R, AT S12E1W */
3848 mmu_idx
= regime_e20
? ARMMMUIdx_E20_2
: ARMMMUIdx_E10_1
;
3850 case 6: /* AT S12E0R, AT S12E0W */
3851 mmu_idx
= regime_e20
? ARMMMUIdx_E20_0
: ARMMMUIdx_E10_0
;
3854 g_assert_not_reached();
3857 env
->cp15
.par_el
[1] = do_ats_write(env
, value
, access_type
,
3858 mmu_idx
, arm_security_space(env
));
3860 /* Handled by hardware accelerator. */
3861 g_assert_not_reached();
3862 #endif /* CONFIG_TCG */
3866 /* Return basic MPU access permission bits. */
3867 static uint32_t simple_mpu_ap_bits(uint32_t val
)
3874 for (i
= 0; i
< 16; i
+= 2) {
3875 ret
|= (val
>> i
) & mask
;
3881 /* Pad basic MPU access permission bits to extended format. */
3882 static uint32_t extended_mpu_ap_bits(uint32_t val
)
3889 for (i
= 0; i
< 16; i
+= 2) {
3890 ret
|= (val
& mask
) << i
;
3896 static void pmsav5_data_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3899 env
->cp15
.pmsav5_data_ap
= extended_mpu_ap_bits(value
);
3902 static uint64_t pmsav5_data_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3904 return simple_mpu_ap_bits(env
->cp15
.pmsav5_data_ap
);
3907 static void pmsav5_insn_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3910 env
->cp15
.pmsav5_insn_ap
= extended_mpu_ap_bits(value
);
3913 static uint64_t pmsav5_insn_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3915 return simple_mpu_ap_bits(env
->cp15
.pmsav5_insn_ap
);
3918 static uint64_t pmsav7_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3920 uint32_t *u32p
= *(uint32_t **)raw_ptr(env
, ri
);
3926 u32p
+= env
->pmsav7
.rnr
[M_REG_NS
];
3930 static void pmsav7_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3933 ARMCPU
*cpu
= env_archcpu(env
);
3934 uint32_t *u32p
= *(uint32_t **)raw_ptr(env
, ri
);
3940 u32p
+= env
->pmsav7
.rnr
[M_REG_NS
];
3941 tlb_flush(CPU(cpu
)); /* Mappings may have changed - purge! */
3945 static void pmsav7_rgnr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3948 ARMCPU
*cpu
= env_archcpu(env
);
3949 uint32_t nrgs
= cpu
->pmsav7_dregion
;
3951 if (value
>= nrgs
) {
3952 qemu_log_mask(LOG_GUEST_ERROR
,
3953 "PMSAv7 RGNR write >= # supported regions, %" PRIu32
3954 " > %" PRIu32
"\n", (uint32_t)value
, nrgs
);
3958 raw_write(env
, ri
, value
);
3961 static void prbar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3964 ARMCPU
*cpu
= env_archcpu(env
);
3966 tlb_flush(CPU(cpu
)); /* Mappings may have changed - purge! */
3967 env
->pmsav8
.rbar
[M_REG_NS
][env
->pmsav7
.rnr
[M_REG_NS
]] = value
;
3970 static uint64_t prbar_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3972 return env
->pmsav8
.rbar
[M_REG_NS
][env
->pmsav7
.rnr
[M_REG_NS
]];
3975 static void prlar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3978 ARMCPU
*cpu
= env_archcpu(env
);
3980 tlb_flush(CPU(cpu
)); /* Mappings may have changed - purge! */
3981 env
->pmsav8
.rlar
[M_REG_NS
][env
->pmsav7
.rnr
[M_REG_NS
]] = value
;
3984 static uint64_t prlar_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3986 return env
->pmsav8
.rlar
[M_REG_NS
][env
->pmsav7
.rnr
[M_REG_NS
]];
3989 static void prselr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3992 ARMCPU
*cpu
= env_archcpu(env
);
3995 * Ignore writes that would select not implemented region.
3996 * This is architecturally UNPREDICTABLE.
3998 if (value
>= cpu
->pmsav7_dregion
) {
4002 env
->pmsav7
.rnr
[M_REG_NS
] = value
;
4005 static void hprbar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4008 ARMCPU
*cpu
= env_archcpu(env
);
4010 tlb_flush(CPU(cpu
)); /* Mappings may have changed - purge! */
4011 env
->pmsav8
.hprbar
[env
->pmsav8
.hprselr
] = value
;
4014 static uint64_t hprbar_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4016 return env
->pmsav8
.hprbar
[env
->pmsav8
.hprselr
];
4019 static void hprlar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4022 ARMCPU
*cpu
= env_archcpu(env
);
4024 tlb_flush(CPU(cpu
)); /* Mappings may have changed - purge! */
4025 env
->pmsav8
.hprlar
[env
->pmsav8
.hprselr
] = value
;
4028 static uint64_t hprlar_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4030 return env
->pmsav8
.hprlar
[env
->pmsav8
.hprselr
];
4033 static void hprenr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4038 ARMCPU
*cpu
= env_archcpu(env
);
4040 /* Ignore writes to unimplemented regions */
4041 int rmax
= MIN(cpu
->pmsav8r_hdregion
, 32);
4042 value
&= MAKE_64BIT_MASK(0, rmax
);
4044 tlb_flush(CPU(cpu
)); /* Mappings may have changed - purge! */
4046 /* Register alias is only valid for first 32 indexes */
4047 for (n
= 0; n
< rmax
; ++n
) {
4048 bit
= extract32(value
, n
, 1);
4049 env
->pmsav8
.hprlar
[n
] = deposit32(
4050 env
->pmsav8
.hprlar
[n
], 0, 1, bit
);
4054 static uint64_t hprenr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4057 uint32_t result
= 0x0;
4058 ARMCPU
*cpu
= env_archcpu(env
);
4060 /* Register alias is only valid for first 32 indexes */
4061 for (n
= 0; n
< MIN(cpu
->pmsav8r_hdregion
, 32); ++n
) {
4062 if (env
->pmsav8
.hprlar
[n
] & 0x1) {
4063 result
|= (0x1 << n
);
4069 static void hprselr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4072 ARMCPU
*cpu
= env_archcpu(env
);
4075 * Ignore writes that would select not implemented region.
4076 * This is architecturally UNPREDICTABLE.
4078 if (value
>= cpu
->pmsav8r_hdregion
) {
4082 env
->pmsav8
.hprselr
= value
;
4085 static void pmsav8r_regn_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4088 ARMCPU
*cpu
= env_archcpu(env
);
4089 uint8_t index
= (extract32(ri
->opc0
, 0, 1) << 4) |
4090 (extract32(ri
->crm
, 0, 3) << 1) | extract32(ri
->opc2
, 2, 1);
4092 tlb_flush(CPU(cpu
)); /* Mappings may have changed - purge! */
4095 if (index
>= cpu
->pmsav8r_hdregion
) {
4098 if (ri
->opc2
& 0x1) {
4099 env
->pmsav8
.hprlar
[index
] = value
;
4101 env
->pmsav8
.hprbar
[index
] = value
;
4104 if (index
>= cpu
->pmsav7_dregion
) {
4107 if (ri
->opc2
& 0x1) {
4108 env
->pmsav8
.rlar
[M_REG_NS
][index
] = value
;
4110 env
->pmsav8
.rbar
[M_REG_NS
][index
] = value
;
4115 static uint64_t pmsav8r_regn_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4117 ARMCPU
*cpu
= env_archcpu(env
);
4118 uint8_t index
= (extract32(ri
->opc0
, 0, 1) << 4) |
4119 (extract32(ri
->crm
, 0, 3) << 1) | extract32(ri
->opc2
, 2, 1);
4122 if (index
>= cpu
->pmsav8r_hdregion
) {
4125 if (ri
->opc2
& 0x1) {
4126 return env
->pmsav8
.hprlar
[index
];
4128 return env
->pmsav8
.hprbar
[index
];
4131 if (index
>= cpu
->pmsav7_dregion
) {
4134 if (ri
->opc2
& 0x1) {
4135 return env
->pmsav8
.rlar
[M_REG_NS
][index
];
4137 return env
->pmsav8
.rbar
[M_REG_NS
][index
];
4142 static const ARMCPRegInfo pmsav8r_cp_reginfo
[] = {
4144 .cp
= 15, .opc1
= 0, .crn
= 6, .crm
= 3, .opc2
= 0,
4145 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
4146 .accessfn
= access_tvm_trvm
,
4147 .readfn
= prbar_read
, .writefn
= prbar_write
},
4149 .cp
= 15, .opc1
= 0, .crn
= 6, .crm
= 3, .opc2
= 1,
4150 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
4151 .accessfn
= access_tvm_trvm
,
4152 .readfn
= prlar_read
, .writefn
= prlar_write
},
4153 { .name
= "PRSELR", .resetvalue
= 0,
4154 .cp
= 15, .opc1
= 0, .crn
= 6, .crm
= 2, .opc2
= 1,
4155 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4156 .writefn
= prselr_write
,
4157 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.rnr
[M_REG_NS
]) },
4158 { .name
= "HPRBAR", .resetvalue
= 0,
4159 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 3, .opc2
= 0,
4160 .access
= PL2_RW
, .type
= ARM_CP_NO_RAW
,
4161 .readfn
= hprbar_read
, .writefn
= hprbar_write
},
4163 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 3, .opc2
= 1,
4164 .access
= PL2_RW
, .type
= ARM_CP_NO_RAW
,
4165 .readfn
= hprlar_read
, .writefn
= hprlar_write
},
4166 { .name
= "HPRSELR", .resetvalue
= 0,
4167 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 2, .opc2
= 1,
4169 .writefn
= hprselr_write
,
4170 .fieldoffset
= offsetof(CPUARMState
, pmsav8
.hprselr
) },
4172 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 1, .opc2
= 1,
4173 .access
= PL2_RW
, .type
= ARM_CP_NO_RAW
,
4174 .readfn
= hprenr_read
, .writefn
= hprenr_write
},
4177 static const ARMCPRegInfo pmsav7_cp_reginfo
[] = {
4179 * Reset for all these registers is handled in arm_cpu_reset(),
4180 * because the PMSAv7 is also used by M-profile CPUs, which do
4181 * not register cpregs but still need the state to be reset.
4183 { .name
= "DRBAR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 0,
4184 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
4185 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.drbar
),
4186 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
,
4187 .resetfn
= arm_cp_reset_ignore
},
4188 { .name
= "DRSR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 2,
4189 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
4190 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.drsr
),
4191 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
,
4192 .resetfn
= arm_cp_reset_ignore
},
4193 { .name
= "DRACR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 4,
4194 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
4195 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.dracr
),
4196 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
,
4197 .resetfn
= arm_cp_reset_ignore
},
4198 { .name
= "RGNR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 2, .opc2
= 0,
4200 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.rnr
[M_REG_NS
]),
4201 .writefn
= pmsav7_rgnr_write
,
4202 .resetfn
= arm_cp_reset_ignore
},
4205 static const ARMCPRegInfo pmsav5_cp_reginfo
[] = {
4206 { .name
= "DATA_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 0,
4207 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
,
4208 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_data_ap
),
4209 .readfn
= pmsav5_data_ap_read
, .writefn
= pmsav5_data_ap_write
, },
4210 { .name
= "INSN_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 1,
4211 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
,
4212 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_insn_ap
),
4213 .readfn
= pmsav5_insn_ap_read
, .writefn
= pmsav5_insn_ap_write
, },
4214 { .name
= "DATA_EXT_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 2,
4216 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_data_ap
),
4218 { .name
= "INSN_EXT_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 3,
4220 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_insn_ap
),
4222 { .name
= "DCACHE_CFG", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 0,
4224 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_data
), .resetvalue
= 0, },
4225 { .name
= "ICACHE_CFG", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 1,
4227 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_insn
), .resetvalue
= 0, },
4228 /* Protection region base and size registers */
4229 { .name
= "946_PRBS0", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0,
4230 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
4231 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[0]) },
4232 { .name
= "946_PRBS1", .cp
= 15, .crn
= 6, .crm
= 1, .opc1
= 0,
4233 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
4234 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[1]) },
4235 { .name
= "946_PRBS2", .cp
= 15, .crn
= 6, .crm
= 2, .opc1
= 0,
4236 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
4237 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[2]) },
4238 { .name
= "946_PRBS3", .cp
= 15, .crn
= 6, .crm
= 3, .opc1
= 0,
4239 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
4240 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[3]) },
4241 { .name
= "946_PRBS4", .cp
= 15, .crn
= 6, .crm
= 4, .opc1
= 0,
4242 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
4243 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[4]) },
4244 { .name
= "946_PRBS5", .cp
= 15, .crn
= 6, .crm
= 5, .opc1
= 0,
4245 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
4246 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[5]) },
4247 { .name
= "946_PRBS6", .cp
= 15, .crn
= 6, .crm
= 6, .opc1
= 0,
4248 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
4249 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[6]) },
4250 { .name
= "946_PRBS7", .cp
= 15, .crn
= 6, .crm
= 7, .opc1
= 0,
4251 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
4252 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[7]) },
4255 static void vmsa_ttbcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4258 ARMCPU
*cpu
= env_archcpu(env
);
4260 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
4261 if (arm_feature(env
, ARM_FEATURE_LPAE
) && (value
& TTBCR_EAE
)) {
4263 * Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when
4264 * using Long-descriptor translation table format
4266 value
&= ~((7 << 19) | (3 << 14) | (0xf << 3));
4267 } else if (arm_feature(env
, ARM_FEATURE_EL3
)) {
4269 * In an implementation that includes the Security Extensions
4270 * TTBCR has additional fields PD0 [4] and PD1 [5] for
4271 * Short-descriptor translation table format.
4273 value
&= TTBCR_PD1
| TTBCR_PD0
| TTBCR_N
;
4279 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
4281 * With LPAE the TTBCR could result in a change of ASID
4282 * via the TTBCR.A1 bit, so do a TLB flush.
4284 tlb_flush(CPU(cpu
));
4286 raw_write(env
, ri
, value
);
4289 static void vmsa_tcr_el12_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4292 ARMCPU
*cpu
= env_archcpu(env
);
4294 /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */
4295 tlb_flush(CPU(cpu
));
4296 raw_write(env
, ri
, value
);
4299 static void vmsa_ttbr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4302 /* If the ASID changes (with a 64-bit write), we must flush the TLB. */
4303 if (cpreg_field_is_64bit(ri
) &&
4304 extract64(raw_read(env
, ri
) ^ value
, 48, 16) != 0) {
4305 ARMCPU
*cpu
= env_archcpu(env
);
4306 tlb_flush(CPU(cpu
));
4308 raw_write(env
, ri
, value
);
4311 static void vmsa_tcr_ttbr_el2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4315 * If we are running with E2&0 regime, then an ASID is active.
4316 * Flush if that might be changing. Note we're not checking
4317 * TCR_EL2.A1 to know if this is really the TTBRx_EL2 that
4318 * holds the active ASID, only checking the field that might.
4320 if (extract64(raw_read(env
, ri
) ^ value
, 48, 16) &&
4321 (arm_hcr_el2_eff(env
) & HCR_E2H
)) {
4322 uint16_t mask
= ARMMMUIdxBit_E20_2
|
4323 ARMMMUIdxBit_E20_2_PAN
|
4325 tlb_flush_by_mmuidx(env_cpu(env
), mask
);
4327 raw_write(env
, ri
, value
);
4330 static void vttbr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4333 ARMCPU
*cpu
= env_archcpu(env
);
4334 CPUState
*cs
= CPU(cpu
);
4337 * A change in VMID to the stage2 page table (Stage2) invalidates
4338 * the stage2 and combined stage 1&2 tlbs (EL10_1 and EL10_0).
4340 if (extract64(raw_read(env
, ri
) ^ value
, 48, 16) != 0) {
4341 tlb_flush_by_mmuidx(cs
, alle1_tlbmask(env
));
4343 raw_write(env
, ri
, value
);
4346 static const ARMCPRegInfo vmsa_pmsa_cp_reginfo
[] = {
4347 { .name
= "DFSR", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 0,
4348 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
, .type
= ARM_CP_ALIAS
,
4349 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dfsr_s
),
4350 offsetoflow32(CPUARMState
, cp15
.dfsr_ns
) }, },
4351 { .name
= "IFSR", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 1,
4352 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
, .resetvalue
= 0,
4353 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.ifsr_s
),
4354 offsetoflow32(CPUARMState
, cp15
.ifsr_ns
) } },
4355 { .name
= "DFAR", .cp
= 15, .opc1
= 0, .crn
= 6, .crm
= 0, .opc2
= 0,
4356 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
, .resetvalue
= 0,
4357 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.dfar_s
),
4358 offsetof(CPUARMState
, cp15
.dfar_ns
) } },
4359 { .name
= "FAR_EL1", .state
= ARM_CP_STATE_AA64
,
4360 .opc0
= 3, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 0,
4361 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4363 .nv2_redirect_offset
= 0x220 | NV2_REDIR_NV1
,
4364 .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[1]),
4368 static const ARMCPRegInfo vmsa_cp_reginfo
[] = {
4369 { .name
= "ESR_EL1", .state
= ARM_CP_STATE_AA64
,
4370 .opc0
= 3, .crn
= 5, .crm
= 2, .opc1
= 0, .opc2
= 0,
4371 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4373 .nv2_redirect_offset
= 0x138 | NV2_REDIR_NV1
,
4374 .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[1]), .resetvalue
= 0, },
4375 { .name
= "TTBR0_EL1", .state
= ARM_CP_STATE_BOTH
,
4376 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 0, .opc2
= 0,
4377 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4378 .fgt
= FGT_TTBR0_EL1
,
4379 .nv2_redirect_offset
= 0x200 | NV2_REDIR_NV1
,
4380 .writefn
= vmsa_ttbr_write
, .resetvalue
= 0, .raw_writefn
= raw_write
,
4381 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr0_s
),
4382 offsetof(CPUARMState
, cp15
.ttbr0_ns
) } },
4383 { .name
= "TTBR1_EL1", .state
= ARM_CP_STATE_BOTH
,
4384 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 0, .opc2
= 1,
4385 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4386 .fgt
= FGT_TTBR1_EL1
,
4387 .nv2_redirect_offset
= 0x210 | NV2_REDIR_NV1
,
4388 .writefn
= vmsa_ttbr_write
, .resetvalue
= 0, .raw_writefn
= raw_write
,
4389 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr1_s
),
4390 offsetof(CPUARMState
, cp15
.ttbr1_ns
) } },
4391 { .name
= "TCR_EL1", .state
= ARM_CP_STATE_AA64
,
4392 .opc0
= 3, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 2,
4393 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4395 .nv2_redirect_offset
= 0x120 | NV2_REDIR_NV1
,
4396 .writefn
= vmsa_tcr_el12_write
,
4397 .raw_writefn
= raw_write
,
4399 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[1]) },
4400 { .name
= "TTBCR", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 2,
4401 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4402 .type
= ARM_CP_ALIAS
, .writefn
= vmsa_ttbcr_write
,
4403 .raw_writefn
= raw_write
,
4404 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tcr_el
[3]),
4405 offsetoflow32(CPUARMState
, cp15
.tcr_el
[1])} },
4409 * Note that unlike TTBCR, writing to TTBCR2 does not require flushing
4410 * qemu tlbs nor adjusting cached masks.
4412 static const ARMCPRegInfo ttbcr2_reginfo
= {
4413 .name
= "TTBCR2", .cp
= 15, .opc1
= 0, .crn
= 2, .crm
= 0, .opc2
= 3,
4414 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4415 .type
= ARM_CP_ALIAS
,
4416 .bank_fieldoffsets
= {
4417 offsetofhigh32(CPUARMState
, cp15
.tcr_el
[3]),
4418 offsetofhigh32(CPUARMState
, cp15
.tcr_el
[1]),
4422 static void omap_ticonfig_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4425 env
->cp15
.c15_ticonfig
= value
& 0xe7;
4426 /* The OS_TYPE bit in this register changes the reported CPUID! */
4427 env
->cp15
.c0_cpuid
= (value
& (1 << 5)) ?
4428 ARM_CPUID_TI915T
: ARM_CPUID_TI925T
;
4431 static void omap_threadid_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4434 env
->cp15
.c15_threadid
= value
& 0xffff;
4437 static void omap_wfi_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4440 /* Wait-for-interrupt (deprecated) */
4441 cpu_interrupt(env_cpu(env
), CPU_INTERRUPT_HALT
);
4444 static void omap_cachemaint_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4448 * On OMAP there are registers indicating the max/min index of dcache lines
4449 * containing a dirty line; cache flush operations have to reset these.
4451 env
->cp15
.c15_i_max
= 0x000;
4452 env
->cp15
.c15_i_min
= 0xff0;
4455 static const ARMCPRegInfo omap_cp_reginfo
[] = {
4456 { .name
= "DFSR", .cp
= 15, .crn
= 5, .crm
= CP_ANY
,
4457 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_OVERRIDE
,
4458 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.esr_el
[1]),
4460 { .name
= "", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 0,
4461 .access
= PL1_RW
, .type
= ARM_CP_NOP
},
4462 { .name
= "TICONFIG", .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0,
4464 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_ticonfig
), .resetvalue
= 0,
4465 .writefn
= omap_ticonfig_write
},
4466 { .name
= "IMAX", .cp
= 15, .crn
= 15, .crm
= 2, .opc1
= 0, .opc2
= 0,
4468 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_i_max
), .resetvalue
= 0, },
4469 { .name
= "IMIN", .cp
= 15, .crn
= 15, .crm
= 3, .opc1
= 0, .opc2
= 0,
4470 .access
= PL1_RW
, .resetvalue
= 0xff0,
4471 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_i_min
) },
4472 { .name
= "THREADID", .cp
= 15, .crn
= 15, .crm
= 4, .opc1
= 0, .opc2
= 0,
4474 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_threadid
), .resetvalue
= 0,
4475 .writefn
= omap_threadid_write
},
4476 { .name
= "TI925T_STATUS", .cp
= 15, .crn
= 15,
4477 .crm
= 8, .opc1
= 0, .opc2
= 0, .access
= PL1_RW
,
4478 .type
= ARM_CP_NO_RAW
,
4479 .readfn
= arm_cp_read_zero
, .writefn
= omap_wfi_write
, },
4481 * TODO: Peripheral port remap register:
4482 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
4483 * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
4486 { .name
= "OMAP_CACHEMAINT", .cp
= 15, .crn
= 7, .crm
= CP_ANY
,
4487 .opc1
= 0, .opc2
= CP_ANY
, .access
= PL1_W
,
4488 .type
= ARM_CP_OVERRIDE
| ARM_CP_NO_RAW
,
4489 .writefn
= omap_cachemaint_write
},
4490 { .name
= "C9", .cp
= 15, .crn
= 9,
4491 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
,
4492 .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
, .resetvalue
= 0 },
4495 static void xscale_cpar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4498 env
->cp15
.c15_cpar
= value
& 0x3fff;
4501 static const ARMCPRegInfo xscale_cp_reginfo
[] = {
4502 { .name
= "XSCALE_CPAR",
4503 .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0, .access
= PL1_RW
,
4504 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_cpar
), .resetvalue
= 0,
4505 .writefn
= xscale_cpar_write
, },
4506 { .name
= "XSCALE_AUXCR",
4507 .cp
= 15, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 1, .access
= PL1_RW
,
4508 .fieldoffset
= offsetof(CPUARMState
, cp15
.c1_xscaleauxcr
),
4511 * XScale specific cache-lockdown: since we have no cache we NOP these
4512 * and hope the guest does not really rely on cache behaviour.
4514 { .name
= "XSCALE_LOCK_ICACHE_LINE",
4515 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 0,
4516 .access
= PL1_W
, .type
= ARM_CP_NOP
},
4517 { .name
= "XSCALE_UNLOCK_ICACHE",
4518 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 1,
4519 .access
= PL1_W
, .type
= ARM_CP_NOP
},
4520 { .name
= "XSCALE_DCACHE_LOCK",
4521 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 2, .opc2
= 0,
4522 .access
= PL1_RW
, .type
= ARM_CP_NOP
},
4523 { .name
= "XSCALE_UNLOCK_DCACHE",
4524 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 2, .opc2
= 1,
4525 .access
= PL1_W
, .type
= ARM_CP_NOP
},
4528 static const ARMCPRegInfo dummy_c15_cp_reginfo
[] = {
4530 * RAZ/WI the whole crn=15 space, when we don't have a more specific
4531 * implementation of this implementation-defined space.
4532 * Ideally this should eventually disappear in favour of actually
4533 * implementing the correct behaviour for all cores.
4535 { .name
= "C15_IMPDEF", .cp
= 15, .crn
= 15,
4536 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
4538 .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
| ARM_CP_OVERRIDE
,
4542 static const ARMCPRegInfo cache_dirty_status_cp_reginfo
[] = {
4543 /* Cache status: RAZ because we have no cache so it's always clean */
4544 { .name
= "CDSR", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 6,
4545 .access
= PL1_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
4549 static const ARMCPRegInfo cache_block_ops_cp_reginfo
[] = {
4550 /* We never have a block transfer operation in progress */
4551 { .name
= "BXSR", .cp
= 15, .crn
= 7, .crm
= 12, .opc1
= 0, .opc2
= 4,
4552 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
4554 /* The cache ops themselves: these all NOP for QEMU */
4555 { .name
= "IICR", .cp
= 15, .crm
= 5, .opc1
= 0,
4556 .access
= PL1_W
, .type
= ARM_CP_NOP
| ARM_CP_64BIT
},
4557 { .name
= "IDCR", .cp
= 15, .crm
= 6, .opc1
= 0,
4558 .access
= PL1_W
, .type
= ARM_CP_NOP
| ARM_CP_64BIT
},
4559 { .name
= "CDCR", .cp
= 15, .crm
= 12, .opc1
= 0,
4560 .access
= PL0_W
, .type
= ARM_CP_NOP
| ARM_CP_64BIT
},
4561 { .name
= "PIR", .cp
= 15, .crm
= 12, .opc1
= 1,
4562 .access
= PL0_W
, .type
= ARM_CP_NOP
| ARM_CP_64BIT
},
4563 { .name
= "PDR", .cp
= 15, .crm
= 12, .opc1
= 2,
4564 .access
= PL0_W
, .type
= ARM_CP_NOP
| ARM_CP_64BIT
},
4565 { .name
= "CIDCR", .cp
= 15, .crm
= 14, .opc1
= 0,
4566 .access
= PL1_W
, .type
= ARM_CP_NOP
| ARM_CP_64BIT
},
4569 static const ARMCPRegInfo cache_test_clean_cp_reginfo
[] = {
4571 * The cache test-and-clean instructions always return (1 << 30)
4572 * to indicate that there are no dirty cache lines.
4574 { .name
= "TC_DCACHE", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 3,
4575 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
4576 .resetvalue
= (1 << 30) },
4577 { .name
= "TCI_DCACHE", .cp
= 15, .crn
= 7, .crm
= 14, .opc1
= 0, .opc2
= 3,
4578 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
4579 .resetvalue
= (1 << 30) },
4582 static const ARMCPRegInfo strongarm_cp_reginfo
[] = {
4583 /* Ignore ReadBuffer accesses */
4584 { .name
= "C9_READBUFFER", .cp
= 15, .crn
= 9,
4585 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
4586 .access
= PL1_RW
, .resetvalue
= 0,
4587 .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
| ARM_CP_NO_RAW
},
4590 static uint64_t midr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4592 unsigned int cur_el
= arm_current_el(env
);
4594 if (arm_is_el2_enabled(env
) && cur_el
== 1) {
4595 return env
->cp15
.vpidr_el2
;
4597 return raw_read(env
, ri
);
4600 static uint64_t mpidr_read_val(CPUARMState
*env
)
4602 ARMCPU
*cpu
= env_archcpu(env
);
4603 uint64_t mpidr
= cpu
->mp_affinity
;
4605 if (arm_feature(env
, ARM_FEATURE_V7MP
)) {
4606 mpidr
|= (1U << 31);
4608 * Cores which are uniprocessor (non-coherent)
4609 * but still implement the MP extensions set
4610 * bit 30. (For instance, Cortex-R5).
4612 if (cpu
->mp_is_up
) {
4613 mpidr
|= (1u << 30);
4619 static uint64_t mpidr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4621 unsigned int cur_el
= arm_current_el(env
);
4623 if (arm_is_el2_enabled(env
) && cur_el
== 1) {
4624 return env
->cp15
.vmpidr_el2
;
4626 return mpidr_read_val(env
);
4629 static const ARMCPRegInfo lpae_cp_reginfo
[] = {
4631 { .name
= "AMAIR0", .state
= ARM_CP_STATE_BOTH
,
4632 .opc0
= 3, .crn
= 10, .crm
= 3, .opc1
= 0, .opc2
= 0,
4633 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4634 .fgt
= FGT_AMAIR_EL1
,
4635 .nv2_redirect_offset
= 0x148 | NV2_REDIR_NV1
,
4636 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4637 /* AMAIR1 is mapped to AMAIR_EL1[63:32] */
4638 { .name
= "AMAIR1", .cp
= 15, .crn
= 10, .crm
= 3, .opc1
= 0, .opc2
= 1,
4639 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4640 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4641 { .name
= "PAR", .cp
= 15, .crm
= 7, .opc1
= 0,
4642 .access
= PL1_RW
, .type
= ARM_CP_64BIT
, .resetvalue
= 0,
4643 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.par_s
),
4644 offsetof(CPUARMState
, cp15
.par_ns
)} },
4645 { .name
= "TTBR0", .cp
= 15, .crm
= 2, .opc1
= 0,
4646 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4647 .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
4648 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr0_s
),
4649 offsetof(CPUARMState
, cp15
.ttbr0_ns
) },
4650 .writefn
= vmsa_ttbr_write
, .raw_writefn
= raw_write
},
4651 { .name
= "TTBR1", .cp
= 15, .crm
= 2, .opc1
= 1,
4652 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4653 .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
4654 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr1_s
),
4655 offsetof(CPUARMState
, cp15
.ttbr1_ns
) },
4656 .writefn
= vmsa_ttbr_write
, .raw_writefn
= raw_write
},
4659 static uint64_t aa64_fpcr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4661 return vfp_get_fpcr(env
);
4664 static void aa64_fpcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4667 vfp_set_fpcr(env
, value
);
4670 static uint64_t aa64_fpsr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4672 return vfp_get_fpsr(env
);
4675 static void aa64_fpsr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4678 vfp_set_fpsr(env
, value
);
4681 static CPAccessResult
aa64_daif_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4684 if (arm_current_el(env
) == 0 && !(arm_sctlr(env
, 0) & SCTLR_UMA
)) {
4685 return CP_ACCESS_TRAP
;
4687 return CP_ACCESS_OK
;
4690 static void aa64_daif_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4693 env
->daif
= value
& PSTATE_DAIF
;
4696 static uint64_t aa64_pan_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4698 return env
->pstate
& PSTATE_PAN
;
4701 static void aa64_pan_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4704 env
->pstate
= (env
->pstate
& ~PSTATE_PAN
) | (value
& PSTATE_PAN
);
4707 static const ARMCPRegInfo pan_reginfo
= {
4708 .name
= "PAN", .state
= ARM_CP_STATE_AA64
,
4709 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 2, .opc2
= 3,
4710 .type
= ARM_CP_NO_RAW
, .access
= PL1_RW
,
4711 .readfn
= aa64_pan_read
, .writefn
= aa64_pan_write
4714 static uint64_t aa64_uao_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4716 return env
->pstate
& PSTATE_UAO
;
4719 static void aa64_uao_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4722 env
->pstate
= (env
->pstate
& ~PSTATE_UAO
) | (value
& PSTATE_UAO
);
4725 static const ARMCPRegInfo uao_reginfo
= {
4726 .name
= "UAO", .state
= ARM_CP_STATE_AA64
,
4727 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 2, .opc2
= 4,
4728 .type
= ARM_CP_NO_RAW
, .access
= PL1_RW
,
4729 .readfn
= aa64_uao_read
, .writefn
= aa64_uao_write
4732 static uint64_t aa64_dit_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4734 return env
->pstate
& PSTATE_DIT
;
4737 static void aa64_dit_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4740 env
->pstate
= (env
->pstate
& ~PSTATE_DIT
) | (value
& PSTATE_DIT
);
4743 static const ARMCPRegInfo dit_reginfo
= {
4744 .name
= "DIT", .state
= ARM_CP_STATE_AA64
,
4745 .opc0
= 3, .opc1
= 3, .crn
= 4, .crm
= 2, .opc2
= 5,
4746 .type
= ARM_CP_NO_RAW
, .access
= PL0_RW
,
4747 .readfn
= aa64_dit_read
, .writefn
= aa64_dit_write
4750 static uint64_t aa64_ssbs_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4752 return env
->pstate
& PSTATE_SSBS
;
4755 static void aa64_ssbs_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4758 env
->pstate
= (env
->pstate
& ~PSTATE_SSBS
) | (value
& PSTATE_SSBS
);
4761 static const ARMCPRegInfo ssbs_reginfo
= {
4762 .name
= "SSBS", .state
= ARM_CP_STATE_AA64
,
4763 .opc0
= 3, .opc1
= 3, .crn
= 4, .crm
= 2, .opc2
= 6,
4764 .type
= ARM_CP_NO_RAW
, .access
= PL0_RW
,
4765 .readfn
= aa64_ssbs_read
, .writefn
= aa64_ssbs_write
4768 static CPAccessResult
aa64_cacheop_poc_access(CPUARMState
*env
,
4769 const ARMCPRegInfo
*ri
,
4772 /* Cache invalidate/clean to Point of Coherency or Persistence... */
4773 switch (arm_current_el(env
)) {
4775 /* ... EL0 must UNDEF unless SCTLR_EL1.UCI is set. */
4776 if (!(arm_sctlr(env
, 0) & SCTLR_UCI
)) {
4777 return CP_ACCESS_TRAP
;
4781 /* ... EL1 must trap to EL2 if HCR_EL2.TPCP is set. */
4782 if (arm_hcr_el2_eff(env
) & HCR_TPCP
) {
4783 return CP_ACCESS_TRAP_EL2
;
4787 return CP_ACCESS_OK
;
4790 static CPAccessResult
do_cacheop_pou_access(CPUARMState
*env
, uint64_t hcrflags
)
4792 /* Cache invalidate/clean to Point of Unification... */
4793 switch (arm_current_el(env
)) {
4795 /* ... EL0 must UNDEF unless SCTLR_EL1.UCI is set. */
4796 if (!(arm_sctlr(env
, 0) & SCTLR_UCI
)) {
4797 return CP_ACCESS_TRAP
;
4801 /* ... EL1 must trap to EL2 if relevant HCR_EL2 flags are set. */
4802 if (arm_hcr_el2_eff(env
) & hcrflags
) {
4803 return CP_ACCESS_TRAP_EL2
;
4807 return CP_ACCESS_OK
;
4810 static CPAccessResult
access_ticab(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4813 return do_cacheop_pou_access(env
, HCR_TICAB
| HCR_TPU
);
4816 static CPAccessResult
access_tocu(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4819 return do_cacheop_pou_access(env
, HCR_TOCU
| HCR_TPU
);
4823 * See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions
4824 * Page D4-1736 (DDI0487A.b)
4827 static int vae1_tlbmask(CPUARMState
*env
)
4829 uint64_t hcr
= arm_hcr_el2_eff(env
);
4832 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
4833 mask
= ARMMMUIdxBit_E20_2
|
4834 ARMMMUIdxBit_E20_2_PAN
|
4837 mask
= ARMMMUIdxBit_E10_1
|
4838 ARMMMUIdxBit_E10_1_PAN
|
4844 static int vae2_tlbmask(CPUARMState
*env
)
4846 uint64_t hcr
= arm_hcr_el2_eff(env
);
4849 if (hcr
& HCR_E2H
) {
4850 mask
= ARMMMUIdxBit_E20_2
|
4851 ARMMMUIdxBit_E20_2_PAN
|
4854 mask
= ARMMMUIdxBit_E2
;
4859 /* Return 56 if TBI is enabled, 64 otherwise. */
4860 static int tlbbits_for_regime(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
4863 uint64_t tcr
= regime_tcr(env
, mmu_idx
);
4864 int tbi
= aa64_va_parameter_tbi(tcr
, mmu_idx
);
4865 int select
= extract64(addr
, 55, 1);
4867 return (tbi
>> select
) & 1 ? 56 : 64;
4870 static int vae1_tlbbits(CPUARMState
*env
, uint64_t addr
)
4872 uint64_t hcr
= arm_hcr_el2_eff(env
);
4875 /* Only the regime of the mmu_idx below is significant. */
4876 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
4877 mmu_idx
= ARMMMUIdx_E20_0
;
4879 mmu_idx
= ARMMMUIdx_E10_0
;
4882 return tlbbits_for_regime(env
, mmu_idx
, addr
);
4885 static int vae2_tlbbits(CPUARMState
*env
, uint64_t addr
)
4887 uint64_t hcr
= arm_hcr_el2_eff(env
);
4891 * Only the regime of the mmu_idx below is significant.
4892 * Regime EL2&0 has two ranges with separate TBI configuration, while EL2
4895 if (hcr
& HCR_E2H
) {
4896 mmu_idx
= ARMMMUIdx_E20_2
;
4898 mmu_idx
= ARMMMUIdx_E2
;
4901 return tlbbits_for_regime(env
, mmu_idx
, addr
);
4904 static void tlbi_aa64_vmalle1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4907 CPUState
*cs
= env_cpu(env
);
4908 int mask
= vae1_tlbmask(env
);
4910 tlb_flush_by_mmuidx_all_cpus_synced(cs
, mask
);
4913 static void tlbi_aa64_vmalle1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4916 CPUState
*cs
= env_cpu(env
);
4917 int mask
= vae1_tlbmask(env
);
4919 if (tlb_force_broadcast(env
)) {
4920 tlb_flush_by_mmuidx_all_cpus_synced(cs
, mask
);
4922 tlb_flush_by_mmuidx(cs
, mask
);
4926 static int e2_tlbmask(CPUARMState
*env
)
4928 return (ARMMMUIdxBit_E20_0
|
4929 ARMMMUIdxBit_E20_2
|
4930 ARMMMUIdxBit_E20_2_PAN
|
4934 static void tlbi_aa64_alle1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4937 CPUState
*cs
= env_cpu(env
);
4938 int mask
= alle1_tlbmask(env
);
4940 tlb_flush_by_mmuidx(cs
, mask
);
4943 static void tlbi_aa64_alle2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4946 CPUState
*cs
= env_cpu(env
);
4947 int mask
= e2_tlbmask(env
);
4949 tlb_flush_by_mmuidx(cs
, mask
);
4952 static void tlbi_aa64_alle3_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4955 ARMCPU
*cpu
= env_archcpu(env
);
4956 CPUState
*cs
= CPU(cpu
);
4958 tlb_flush_by_mmuidx(cs
, ARMMMUIdxBit_E3
);
4961 static void tlbi_aa64_alle1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4964 CPUState
*cs
= env_cpu(env
);
4965 int mask
= alle1_tlbmask(env
);
4967 tlb_flush_by_mmuidx_all_cpus_synced(cs
, mask
);
4970 static void tlbi_aa64_alle2is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4973 CPUState
*cs
= env_cpu(env
);
4974 int mask
= e2_tlbmask(env
);
4976 tlb_flush_by_mmuidx_all_cpus_synced(cs
, mask
);
4979 static void tlbi_aa64_alle3is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4982 CPUState
*cs
= env_cpu(env
);
4984 tlb_flush_by_mmuidx_all_cpus_synced(cs
, ARMMMUIdxBit_E3
);
4987 static void tlbi_aa64_vae2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4991 * Invalidate by VA, EL2
4992 * Currently handles both VAE2 and VALE2, since we don't support
4993 * flush-last-level-only.
4995 CPUState
*cs
= env_cpu(env
);
4996 int mask
= vae2_tlbmask(env
);
4997 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4998 int bits
= vae2_tlbbits(env
, pageaddr
);
5000 tlb_flush_page_bits_by_mmuidx(cs
, pageaddr
, mask
, bits
);
5003 static void tlbi_aa64_vae3_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5007 * Invalidate by VA, EL3
5008 * Currently handles both VAE3 and VALE3, since we don't support
5009 * flush-last-level-only.
5011 ARMCPU
*cpu
= env_archcpu(env
);
5012 CPUState
*cs
= CPU(cpu
);
5013 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
5015 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_E3
);
5018 static void tlbi_aa64_vae1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5021 CPUState
*cs
= env_cpu(env
);
5022 int mask
= vae1_tlbmask(env
);
5023 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
5024 int bits
= vae1_tlbbits(env
, pageaddr
);
5026 tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs
, pageaddr
, mask
, bits
);
5029 static void tlbi_aa64_vae1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5033 * Invalidate by VA, EL1&0 (AArch64 version).
5034 * Currently handles all of VAE1, VAAE1, VAALE1 and VALE1,
5035 * since we don't support flush-for-specific-ASID-only or
5036 * flush-last-level-only.
5038 CPUState
*cs
= env_cpu(env
);
5039 int mask
= vae1_tlbmask(env
);
5040 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
5041 int bits
= vae1_tlbbits(env
, pageaddr
);
5043 if (tlb_force_broadcast(env
)) {
5044 tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs
, pageaddr
, mask
, bits
);
5046 tlb_flush_page_bits_by_mmuidx(cs
, pageaddr
, mask
, bits
);
5050 static void tlbi_aa64_vae2is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5053 CPUState
*cs
= env_cpu(env
);
5054 int mask
= vae2_tlbmask(env
);
5055 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
5056 int bits
= vae2_tlbbits(env
, pageaddr
);
5058 tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs
, pageaddr
, mask
, bits
);
5061 static void tlbi_aa64_vae3is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5064 CPUState
*cs
= env_cpu(env
);
5065 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
5066 int bits
= tlbbits_for_regime(env
, ARMMMUIdx_E3
, pageaddr
);
5068 tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
5069 ARMMMUIdxBit_E3
, bits
);
5072 static int ipas2e1_tlbmask(CPUARMState
*env
, int64_t value
)
5075 * The MSB of value is the NS field, which only applies if SEL2
5076 * is implemented and SCR_EL3.NS is not set (i.e. in secure mode).
5079 && cpu_isar_feature(aa64_sel2
, env_archcpu(env
))
5080 && arm_is_secure_below_el3(env
)
5081 ? ARMMMUIdxBit_Stage2_S
5082 : ARMMMUIdxBit_Stage2
);
5085 static void tlbi_aa64_ipas2e1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5088 CPUState
*cs
= env_cpu(env
);
5089 int mask
= ipas2e1_tlbmask(env
, value
);
5090 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
5092 if (tlb_force_broadcast(env
)) {
5093 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
, mask
);
5095 tlb_flush_page_by_mmuidx(cs
, pageaddr
, mask
);
5099 static void tlbi_aa64_ipas2e1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5102 CPUState
*cs
= env_cpu(env
);
5103 int mask
= ipas2e1_tlbmask(env
, value
);
5104 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
5106 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
, mask
);
5109 #ifdef TARGET_AARCH64
5115 static ARMGranuleSize
tlbi_range_tg_to_gran_size(int tg
)
5118 * Note that the TLBI range TG field encoding differs from both
5119 * TG0 and TG1 encodings.
5133 static TLBIRange
tlbi_aa64_get_range(CPUARMState
*env
, ARMMMUIdx mmuidx
,
5136 unsigned int page_size_granule
, page_shift
, num
, scale
, exponent
;
5137 /* Extract one bit to represent the va selector in use. */
5138 uint64_t select
= sextract64(value
, 36, 1);
5139 ARMVAParameters param
= aa64_va_parameters(env
, select
, mmuidx
, true, false);
5140 TLBIRange ret
= { };
5141 ARMGranuleSize gran
;
5143 page_size_granule
= extract64(value
, 46, 2);
5144 gran
= tlbi_range_tg_to_gran_size(page_size_granule
);
5146 /* The granule encoded in value must match the granule in use. */
5147 if (gran
!= param
.gran
) {
5148 qemu_log_mask(LOG_GUEST_ERROR
, "Invalid tlbi page size granule %d\n",
5153 page_shift
= arm_granule_bits(gran
);
5154 num
= extract64(value
, 39, 5);
5155 scale
= extract64(value
, 44, 2);
5156 exponent
= (5 * scale
) + 1;
5158 ret
.length
= (num
+ 1) << (exponent
+ page_shift
);
5161 ret
.base
= sextract64(value
, 0, 37);
5163 ret
.base
= extract64(value
, 0, 37);
5167 * With DS=1, BaseADDR is always shifted 16 so that it is able
5168 * to address all 52 va bits. The input address is perforce
5169 * aligned on a 64k boundary regardless of translation granule.
5173 ret
.base
<<= page_shift
;
5178 static void do_rvae_write(CPUARMState
*env
, uint64_t value
,
5179 int idxmap
, bool synced
)
5181 ARMMMUIdx one_idx
= ARM_MMU_IDX_A
| ctz32(idxmap
);
5185 range
= tlbi_aa64_get_range(env
, one_idx
, value
);
5186 bits
= tlbbits_for_regime(env
, one_idx
, range
.base
);
5189 tlb_flush_range_by_mmuidx_all_cpus_synced(env_cpu(env
),
5195 tlb_flush_range_by_mmuidx(env_cpu(env
), range
.base
,
5196 range
.length
, idxmap
, bits
);
5200 static void tlbi_aa64_rvae1_write(CPUARMState
*env
,
5201 const ARMCPRegInfo
*ri
,
5205 * Invalidate by VA range, EL1&0.
5206 * Currently handles all of RVAE1, RVAAE1, RVAALE1 and RVALE1,
5207 * since we don't support flush-for-specific-ASID-only or
5208 * flush-last-level-only.
5211 do_rvae_write(env
, value
, vae1_tlbmask(env
),
5212 tlb_force_broadcast(env
));
5215 static void tlbi_aa64_rvae1is_write(CPUARMState
*env
,
5216 const ARMCPRegInfo
*ri
,
5220 * Invalidate by VA range, Inner/Outer Shareable EL1&0.
5221 * Currently handles all of RVAE1IS, RVAE1OS, RVAAE1IS, RVAAE1OS,
5222 * RVAALE1IS, RVAALE1OS, RVALE1IS and RVALE1OS, since we don't support
5223 * flush-for-specific-ASID-only, flush-last-level-only or inner/outer
5224 * shareable specific flushes.
5227 do_rvae_write(env
, value
, vae1_tlbmask(env
), true);
5230 static void tlbi_aa64_rvae2_write(CPUARMState
*env
,
5231 const ARMCPRegInfo
*ri
,
5235 * Invalidate by VA range, EL2.
5236 * Currently handles all of RVAE2 and RVALE2,
5237 * since we don't support flush-for-specific-ASID-only or
5238 * flush-last-level-only.
5241 do_rvae_write(env
, value
, vae2_tlbmask(env
),
5242 tlb_force_broadcast(env
));
5247 static void tlbi_aa64_rvae2is_write(CPUARMState
*env
,
5248 const ARMCPRegInfo
*ri
,
5252 * Invalidate by VA range, Inner/Outer Shareable, EL2.
5253 * Currently handles all of RVAE2IS, RVAE2OS, RVALE2IS and RVALE2OS,
5254 * since we don't support flush-for-specific-ASID-only,
5255 * flush-last-level-only or inner/outer shareable specific flushes.
5258 do_rvae_write(env
, value
, vae2_tlbmask(env
), true);
5262 static void tlbi_aa64_rvae3_write(CPUARMState
*env
,
5263 const ARMCPRegInfo
*ri
,
5267 * Invalidate by VA range, EL3.
5268 * Currently handles all of RVAE3 and RVALE3,
5269 * since we don't support flush-for-specific-ASID-only or
5270 * flush-last-level-only.
5273 do_rvae_write(env
, value
, ARMMMUIdxBit_E3
, tlb_force_broadcast(env
));
5276 static void tlbi_aa64_rvae3is_write(CPUARMState
*env
,
5277 const ARMCPRegInfo
*ri
,
5281 * Invalidate by VA range, EL3, Inner/Outer Shareable.
5282 * Currently handles all of RVAE3IS, RVAE3OS, RVALE3IS and RVALE3OS,
5283 * since we don't support flush-for-specific-ASID-only,
5284 * flush-last-level-only or inner/outer specific flushes.
5287 do_rvae_write(env
, value
, ARMMMUIdxBit_E3
, true);
5290 static void tlbi_aa64_ripas2e1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5293 do_rvae_write(env
, value
, ipas2e1_tlbmask(env
, value
),
5294 tlb_force_broadcast(env
));
5297 static void tlbi_aa64_ripas2e1is_write(CPUARMState
*env
,
5298 const ARMCPRegInfo
*ri
,
5301 do_rvae_write(env
, value
, ipas2e1_tlbmask(env
, value
), true);
5305 static CPAccessResult
aa64_zva_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5308 int cur_el
= arm_current_el(env
);
5311 uint64_t hcr
= arm_hcr_el2_eff(env
);
5314 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
5315 if (!(env
->cp15
.sctlr_el
[2] & SCTLR_DZE
)) {
5316 return CP_ACCESS_TRAP_EL2
;
5319 if (!(env
->cp15
.sctlr_el
[1] & SCTLR_DZE
)) {
5320 return CP_ACCESS_TRAP
;
5322 if (hcr
& HCR_TDZ
) {
5323 return CP_ACCESS_TRAP_EL2
;
5326 } else if (hcr
& HCR_TDZ
) {
5327 return CP_ACCESS_TRAP_EL2
;
5330 return CP_ACCESS_OK
;
5333 static uint64_t aa64_dczid_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
5335 ARMCPU
*cpu
= env_archcpu(env
);
5336 int dzp_bit
= 1 << 4;
5338 /* DZP indicates whether DC ZVA access is allowed */
5339 if (aa64_zva_access(env
, NULL
, false) == CP_ACCESS_OK
) {
5342 return cpu
->dcz_blocksize
| dzp_bit
;
5345 static CPAccessResult
sp_el0_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5348 if (!(env
->pstate
& PSTATE_SP
)) {
5350 * Access to SP_EL0 is undefined if it's being used as
5351 * the stack pointer.
5353 return CP_ACCESS_TRAP_UNCATEGORIZED
;
5355 return CP_ACCESS_OK
;
5358 static uint64_t spsel_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
5360 return env
->pstate
& PSTATE_SP
;
5363 static void spsel_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t val
)
5365 update_spsel(env
, val
);
5368 static void sctlr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5371 ARMCPU
*cpu
= env_archcpu(env
);
5373 if (arm_feature(env
, ARM_FEATURE_PMSA
) && !cpu
->has_mpu
) {
5374 /* M bit is RAZ/WI for PMSA with no MPU implemented */
5378 /* ??? Lots of these bits are not implemented. */
5380 if (ri
->state
== ARM_CP_STATE_AA64
&& !cpu_isar_feature(aa64_mte
, cpu
)) {
5381 if (ri
->opc1
== 6) { /* SCTLR_EL3 */
5382 value
&= ~(SCTLR_ITFSB
| SCTLR_TCF
| SCTLR_ATA
);
5384 value
&= ~(SCTLR_ITFSB
| SCTLR_TCF0
| SCTLR_TCF
|
5385 SCTLR_ATA0
| SCTLR_ATA
);
5389 if (raw_read(env
, ri
) == value
) {
5391 * Skip the TLB flush if nothing actually changed; Linux likes
5392 * to do a lot of pointless SCTLR writes.
5397 raw_write(env
, ri
, value
);
5399 /* This may enable/disable the MMU, so do a TLB flush. */
5400 tlb_flush(CPU(cpu
));
5402 if (tcg_enabled() && ri
->type
& ARM_CP_SUPPRESS_TB_END
) {
5404 * Normally we would always end the TB on an SCTLR write; see the
5405 * comment in ARMCPRegInfo sctlr initialization below for why Xscale
5406 * is special. Setting ARM_CP_SUPPRESS_TB_END also stops the rebuild
5407 * of hflags from the translator, so do it here.
5409 arm_rebuild_hflags(env
);
5413 static void mdcr_el3_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5417 * Some MDCR_EL3 bits affect whether PMU counters are running:
5418 * if we are trying to change any of those then we must
5419 * bracket this update with PMU start/finish calls.
5421 bool pmu_op
= (env
->cp15
.mdcr_el3
^ value
) & MDCR_EL3_PMU_ENABLE_BITS
;
5426 env
->cp15
.mdcr_el3
= value
;
5432 static void sdcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5435 /* Not all bits defined for MDCR_EL3 exist in the AArch32 SDCR */
5436 mdcr_el3_write(env
, ri
, value
& SDCR_VALID_MASK
);
5439 static void mdcr_el2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5443 * Some MDCR_EL2 bits affect whether PMU counters are running:
5444 * if we are trying to change any of those then we must
5445 * bracket this update with PMU start/finish calls.
5447 bool pmu_op
= (env
->cp15
.mdcr_el2
^ value
) & MDCR_EL2_PMU_ENABLE_BITS
;
5452 env
->cp15
.mdcr_el2
= value
;
5458 static CPAccessResult
access_nv1(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5461 if (arm_current_el(env
) == 1) {
5462 uint64_t hcr_nv
= arm_hcr_el2_eff(env
) & (HCR_NV
| HCR_NV1
| HCR_NV2
);
5464 if (hcr_nv
== (HCR_NV
| HCR_NV1
)) {
5465 return CP_ACCESS_TRAP_EL2
;
5468 return CP_ACCESS_OK
;
5471 #ifdef CONFIG_USER_ONLY
5473 * `IC IVAU` is handled to improve compatibility with JITs that dual-map their
5474 * code to get around W^X restrictions, where one region is writable and the
5475 * other is executable.
5477 * Since the executable region is never written to we cannot detect code
5478 * changes when running in user mode, and rely on the emulated JIT telling us
5479 * that the code has changed by executing this instruction.
5481 static void ic_ivau_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5484 uint64_t icache_line_mask
, start_address
, end_address
;
5487 cpu
= env_archcpu(env
);
5489 icache_line_mask
= (4 << extract32(cpu
->ctr
, 0, 4)) - 1;
5490 start_address
= value
& ~icache_line_mask
;
5491 end_address
= value
| icache_line_mask
;
5495 tb_invalidate_phys_range(start_address
, end_address
);
5501 static const ARMCPRegInfo v8_cp_reginfo
[] = {
5503 * Minimal set of EL0-visible registers. This will need to be expanded
5504 * significantly for system emulation of AArch64 CPUs.
5506 { .name
= "NZCV", .state
= ARM_CP_STATE_AA64
,
5507 .opc0
= 3, .opc1
= 3, .opc2
= 0, .crn
= 4, .crm
= 2,
5508 .access
= PL0_RW
, .type
= ARM_CP_NZCV
},
5509 { .name
= "DAIF", .state
= ARM_CP_STATE_AA64
,
5510 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 4, .crm
= 2,
5511 .type
= ARM_CP_NO_RAW
,
5512 .access
= PL0_RW
, .accessfn
= aa64_daif_access
,
5513 .fieldoffset
= offsetof(CPUARMState
, daif
),
5514 .writefn
= aa64_daif_write
, .resetfn
= arm_cp_reset_ignore
},
5515 { .name
= "FPCR", .state
= ARM_CP_STATE_AA64
,
5516 .opc0
= 3, .opc1
= 3, .opc2
= 0, .crn
= 4, .crm
= 4,
5517 .access
= PL0_RW
, .type
= ARM_CP_FPU
| ARM_CP_SUPPRESS_TB_END
,
5518 .readfn
= aa64_fpcr_read
, .writefn
= aa64_fpcr_write
},
5519 { .name
= "FPSR", .state
= ARM_CP_STATE_AA64
,
5520 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 4, .crm
= 4,
5521 .access
= PL0_RW
, .type
= ARM_CP_FPU
| ARM_CP_SUPPRESS_TB_END
,
5522 .readfn
= aa64_fpsr_read
, .writefn
= aa64_fpsr_write
},
5523 { .name
= "DCZID_EL0", .state
= ARM_CP_STATE_AA64
,
5524 .opc0
= 3, .opc1
= 3, .opc2
= 7, .crn
= 0, .crm
= 0,
5525 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
,
5526 .fgt
= FGT_DCZID_EL0
,
5527 .readfn
= aa64_dczid_read
},
5528 { .name
= "DC_ZVA", .state
= ARM_CP_STATE_AA64
,
5529 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 4, .opc2
= 1,
5530 .access
= PL0_W
, .type
= ARM_CP_DC_ZVA
,
5531 #ifndef CONFIG_USER_ONLY
5532 /* Avoid overhead of an access check that always passes in user-mode */
5533 .accessfn
= aa64_zva_access
,
5537 { .name
= "CURRENTEL", .state
= ARM_CP_STATE_AA64
,
5538 .opc0
= 3, .opc1
= 0, .opc2
= 2, .crn
= 4, .crm
= 2,
5539 .access
= PL1_R
, .type
= ARM_CP_CURRENTEL
},
5541 * Instruction cache ops. All of these except `IC IVAU` NOP because we
5542 * don't emulate caches.
5544 { .name
= "IC_IALLUIS", .state
= ARM_CP_STATE_AA64
,
5545 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 0,
5546 .access
= PL1_W
, .type
= ARM_CP_NOP
,
5547 .fgt
= FGT_ICIALLUIS
,
5548 .accessfn
= access_ticab
},
5549 { .name
= "IC_IALLU", .state
= ARM_CP_STATE_AA64
,
5550 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 0,
5551 .access
= PL1_W
, .type
= ARM_CP_NOP
,
5553 .accessfn
= access_tocu
},
5554 { .name
= "IC_IVAU", .state
= ARM_CP_STATE_AA64
,
5555 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 5, .opc2
= 1,
5558 .accessfn
= access_tocu
,
5559 #ifdef CONFIG_USER_ONLY
5560 .type
= ARM_CP_NO_RAW
,
5561 .writefn
= ic_ivau_write
5566 /* Cache ops: all NOPs since we don't emulate caches */
5567 { .name
= "DC_IVAC", .state
= ARM_CP_STATE_AA64
,
5568 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 1,
5569 .access
= PL1_W
, .accessfn
= aa64_cacheop_poc_access
,
5571 .type
= ARM_CP_NOP
},
5572 { .name
= "DC_ISW", .state
= ARM_CP_STATE_AA64
,
5573 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 2,
5575 .access
= PL1_W
, .accessfn
= access_tsw
, .type
= ARM_CP_NOP
},
5576 { .name
= "DC_CVAC", .state
= ARM_CP_STATE_AA64
,
5577 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 10, .opc2
= 1,
5578 .access
= PL0_W
, .type
= ARM_CP_NOP
,
5580 .accessfn
= aa64_cacheop_poc_access
},
5581 { .name
= "DC_CSW", .state
= ARM_CP_STATE_AA64
,
5582 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 2,
5584 .access
= PL1_W
, .accessfn
= access_tsw
, .type
= ARM_CP_NOP
},
5585 { .name
= "DC_CVAU", .state
= ARM_CP_STATE_AA64
,
5586 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 11, .opc2
= 1,
5587 .access
= PL0_W
, .type
= ARM_CP_NOP
,
5589 .accessfn
= access_tocu
},
5590 { .name
= "DC_CIVAC", .state
= ARM_CP_STATE_AA64
,
5591 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 14, .opc2
= 1,
5592 .access
= PL0_W
, .type
= ARM_CP_NOP
,
5594 .accessfn
= aa64_cacheop_poc_access
},
5595 { .name
= "DC_CISW", .state
= ARM_CP_STATE_AA64
,
5596 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 2,
5598 .access
= PL1_W
, .accessfn
= access_tsw
, .type
= ARM_CP_NOP
},
5599 /* TLBI operations */
5600 { .name
= "TLBI_VMALLE1IS", .state
= ARM_CP_STATE_AA64
,
5601 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 0,
5602 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
5603 .fgt
= FGT_TLBIVMALLE1IS
,
5604 .writefn
= tlbi_aa64_vmalle1is_write
},
5605 { .name
= "TLBI_VAE1IS", .state
= ARM_CP_STATE_AA64
,
5606 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 1,
5607 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
5608 .fgt
= FGT_TLBIVAE1IS
,
5609 .writefn
= tlbi_aa64_vae1is_write
},
5610 { .name
= "TLBI_ASIDE1IS", .state
= ARM_CP_STATE_AA64
,
5611 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 2,
5612 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
5613 .fgt
= FGT_TLBIASIDE1IS
,
5614 .writefn
= tlbi_aa64_vmalle1is_write
},
5615 { .name
= "TLBI_VAAE1IS", .state
= ARM_CP_STATE_AA64
,
5616 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 3,
5617 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
5618 .fgt
= FGT_TLBIVAAE1IS
,
5619 .writefn
= tlbi_aa64_vae1is_write
},
5620 { .name
= "TLBI_VALE1IS", .state
= ARM_CP_STATE_AA64
,
5621 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 5,
5622 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
5623 .fgt
= FGT_TLBIVALE1IS
,
5624 .writefn
= tlbi_aa64_vae1is_write
},
5625 { .name
= "TLBI_VAALE1IS", .state
= ARM_CP_STATE_AA64
,
5626 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 7,
5627 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
5628 .fgt
= FGT_TLBIVAALE1IS
,
5629 .writefn
= tlbi_aa64_vae1is_write
},
5630 { .name
= "TLBI_VMALLE1", .state
= ARM_CP_STATE_AA64
,
5631 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 0,
5632 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
5633 .fgt
= FGT_TLBIVMALLE1
,
5634 .writefn
= tlbi_aa64_vmalle1_write
},
5635 { .name
= "TLBI_VAE1", .state
= ARM_CP_STATE_AA64
,
5636 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 1,
5637 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
5638 .fgt
= FGT_TLBIVAE1
,
5639 .writefn
= tlbi_aa64_vae1_write
},
5640 { .name
= "TLBI_ASIDE1", .state
= ARM_CP_STATE_AA64
,
5641 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 2,
5642 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
5643 .fgt
= FGT_TLBIASIDE1
,
5644 .writefn
= tlbi_aa64_vmalle1_write
},
5645 { .name
= "TLBI_VAAE1", .state
= ARM_CP_STATE_AA64
,
5646 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 3,
5647 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
5648 .fgt
= FGT_TLBIVAAE1
,
5649 .writefn
= tlbi_aa64_vae1_write
},
5650 { .name
= "TLBI_VALE1", .state
= ARM_CP_STATE_AA64
,
5651 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 5,
5652 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
5653 .fgt
= FGT_TLBIVALE1
,
5654 .writefn
= tlbi_aa64_vae1_write
},
5655 { .name
= "TLBI_VAALE1", .state
= ARM_CP_STATE_AA64
,
5656 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 7,
5657 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
5658 .fgt
= FGT_TLBIVAALE1
,
5659 .writefn
= tlbi_aa64_vae1_write
},
5660 { .name
= "TLBI_IPAS2E1IS", .state
= ARM_CP_STATE_AA64
,
5661 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 1,
5662 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5663 .writefn
= tlbi_aa64_ipas2e1is_write
},
5664 { .name
= "TLBI_IPAS2LE1IS", .state
= ARM_CP_STATE_AA64
,
5665 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 5,
5666 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5667 .writefn
= tlbi_aa64_ipas2e1is_write
},
5668 { .name
= "TLBI_ALLE1IS", .state
= ARM_CP_STATE_AA64
,
5669 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 4,
5670 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5671 .writefn
= tlbi_aa64_alle1is_write
},
5672 { .name
= "TLBI_VMALLS12E1IS", .state
= ARM_CP_STATE_AA64
,
5673 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 6,
5674 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5675 .writefn
= tlbi_aa64_alle1is_write
},
5676 { .name
= "TLBI_IPAS2E1", .state
= ARM_CP_STATE_AA64
,
5677 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 1,
5678 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5679 .writefn
= tlbi_aa64_ipas2e1_write
},
5680 { .name
= "TLBI_IPAS2LE1", .state
= ARM_CP_STATE_AA64
,
5681 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 5,
5682 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5683 .writefn
= tlbi_aa64_ipas2e1_write
},
5684 { .name
= "TLBI_ALLE1", .state
= ARM_CP_STATE_AA64
,
5685 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 4,
5686 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5687 .writefn
= tlbi_aa64_alle1_write
},
5688 { .name
= "TLBI_VMALLS12E1", .state
= ARM_CP_STATE_AA64
,
5689 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 6,
5690 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5691 .writefn
= tlbi_aa64_alle1is_write
},
5692 #ifndef CONFIG_USER_ONLY
5693 /* 64 bit address translation operations */
5694 { .name
= "AT_S1E1R", .state
= ARM_CP_STATE_AA64
,
5695 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 0,
5696 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5698 .accessfn
= at_s1e01_access
, .writefn
= ats_write64
},
5699 { .name
= "AT_S1E1W", .state
= ARM_CP_STATE_AA64
,
5700 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 1,
5701 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5703 .accessfn
= at_s1e01_access
, .writefn
= ats_write64
},
5704 { .name
= "AT_S1E0R", .state
= ARM_CP_STATE_AA64
,
5705 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 2,
5706 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5708 .accessfn
= at_s1e01_access
, .writefn
= ats_write64
},
5709 { .name
= "AT_S1E0W", .state
= ARM_CP_STATE_AA64
,
5710 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 3,
5711 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5713 .accessfn
= at_s1e01_access
, .writefn
= ats_write64
},
5714 { .name
= "AT_S12E1R", .state
= ARM_CP_STATE_AA64
,
5715 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 4,
5716 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5717 .accessfn
= at_e012_access
, .writefn
= ats_write64
},
5718 { .name
= "AT_S12E1W", .state
= ARM_CP_STATE_AA64
,
5719 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 5,
5720 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5721 .accessfn
= at_e012_access
, .writefn
= ats_write64
},
5722 { .name
= "AT_S12E0R", .state
= ARM_CP_STATE_AA64
,
5723 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 6,
5724 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5725 .accessfn
= at_e012_access
, .writefn
= ats_write64
},
5726 { .name
= "AT_S12E0W", .state
= ARM_CP_STATE_AA64
,
5727 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 7,
5728 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5729 .accessfn
= at_e012_access
, .writefn
= ats_write64
},
5730 /* AT S1E2* are elsewhere as they UNDEF from EL3 if EL2 is not present */
5731 { .name
= "AT_S1E3R", .state
= ARM_CP_STATE_AA64
,
5732 .opc0
= 1, .opc1
= 6, .crn
= 7, .crm
= 8, .opc2
= 0,
5733 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5734 .writefn
= ats_write64
},
5735 { .name
= "AT_S1E3W", .state
= ARM_CP_STATE_AA64
,
5736 .opc0
= 1, .opc1
= 6, .crn
= 7, .crm
= 8, .opc2
= 1,
5737 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5738 .writefn
= ats_write64
},
5739 { .name
= "PAR_EL1", .state
= ARM_CP_STATE_AA64
,
5740 .type
= ARM_CP_ALIAS
,
5741 .opc0
= 3, .opc1
= 0, .crn
= 7, .crm
= 4, .opc2
= 0,
5742 .access
= PL1_RW
, .resetvalue
= 0,
5744 .fieldoffset
= offsetof(CPUARMState
, cp15
.par_el
[1]),
5745 .writefn
= par_write
},
5747 /* TLB invalidate last level of translation table walk */
5748 { .name
= "TLBIMVALIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 5,
5749 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlbis
,
5750 .writefn
= tlbimva_is_write
},
5751 { .name
= "TLBIMVAALIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 7,
5752 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlbis
,
5753 .writefn
= tlbimvaa_is_write
},
5754 { .name
= "TLBIMVAL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 5,
5755 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
5756 .writefn
= tlbimva_write
},
5757 { .name
= "TLBIMVAAL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 7,
5758 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
5759 .writefn
= tlbimvaa_write
},
5760 { .name
= "TLBIMVALH", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 5,
5761 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5762 .writefn
= tlbimva_hyp_write
},
5763 { .name
= "TLBIMVALHIS",
5764 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 5,
5765 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5766 .writefn
= tlbimva_hyp_is_write
},
5767 { .name
= "TLBIIPAS2",
5768 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 1,
5769 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5770 .writefn
= tlbiipas2_hyp_write
},
5771 { .name
= "TLBIIPAS2IS",
5772 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 1,
5773 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5774 .writefn
= tlbiipas2is_hyp_write
},
5775 { .name
= "TLBIIPAS2L",
5776 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 5,
5777 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5778 .writefn
= tlbiipas2_hyp_write
},
5779 { .name
= "TLBIIPAS2LIS",
5780 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 5,
5781 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5782 .writefn
= tlbiipas2is_hyp_write
},
5783 /* 32 bit cache operations */
5784 { .name
= "ICIALLUIS", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 0,
5785 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_ticab
},
5786 { .name
= "BPIALLUIS", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 6,
5787 .type
= ARM_CP_NOP
, .access
= PL1_W
},
5788 { .name
= "ICIALLU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 0,
5789 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tocu
},
5790 { .name
= "ICIMVAU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 1,
5791 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tocu
},
5792 { .name
= "BPIALL", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 6,
5793 .type
= ARM_CP_NOP
, .access
= PL1_W
},
5794 { .name
= "BPIMVA", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 7,
5795 .type
= ARM_CP_NOP
, .access
= PL1_W
},
5796 { .name
= "DCIMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 1,
5797 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= aa64_cacheop_poc_access
},
5798 { .name
= "DCISW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 2,
5799 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
5800 { .name
= "DCCMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 1,
5801 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= aa64_cacheop_poc_access
},
5802 { .name
= "DCCSW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 2,
5803 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
5804 { .name
= "DCCMVAU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 11, .opc2
= 1,
5805 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tocu
},
5806 { .name
= "DCCIMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 1,
5807 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= aa64_cacheop_poc_access
},
5808 { .name
= "DCCISW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 2,
5809 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
5810 /* MMU Domain access control / MPU write buffer control */
5811 { .name
= "DACR", .cp
= 15, .opc1
= 0, .crn
= 3, .crm
= 0, .opc2
= 0,
5812 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
, .resetvalue
= 0,
5813 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
5814 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dacr_s
),
5815 offsetoflow32(CPUARMState
, cp15
.dacr_ns
) } },
5816 { .name
= "ELR_EL1", .state
= ARM_CP_STATE_AA64
,
5817 .type
= ARM_CP_ALIAS
,
5818 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 0, .opc2
= 1,
5819 .access
= PL1_RW
, .accessfn
= access_nv1
,
5820 .nv2_redirect_offset
= 0x230 | NV2_REDIR_NV1
,
5821 .fieldoffset
= offsetof(CPUARMState
, elr_el
[1]) },
5822 { .name
= "SPSR_EL1", .state
= ARM_CP_STATE_AA64
,
5823 .type
= ARM_CP_ALIAS
,
5824 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 0, .opc2
= 0,
5825 .access
= PL1_RW
, .accessfn
= access_nv1
,
5826 .nv2_redirect_offset
= 0x160 | NV2_REDIR_NV1
,
5827 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_SVC
]) },
5829 * We rely on the access checks not allowing the guest to write to the
5830 * state field when SPSel indicates that it's being used as the stack
5833 { .name
= "SP_EL0", .state
= ARM_CP_STATE_AA64
,
5834 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 1, .opc2
= 0,
5835 .access
= PL1_RW
, .accessfn
= sp_el0_access
,
5836 .type
= ARM_CP_ALIAS
,
5837 .fieldoffset
= offsetof(CPUARMState
, sp_el
[0]) },
5838 { .name
= "SP_EL1", .state
= ARM_CP_STATE_AA64
,
5839 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 1, .opc2
= 0,
5840 .nv2_redirect_offset
= 0x240,
5841 .access
= PL2_RW
, .type
= ARM_CP_ALIAS
| ARM_CP_EL3_NO_EL2_KEEP
,
5842 .fieldoffset
= offsetof(CPUARMState
, sp_el
[1]) },
5843 { .name
= "SPSel", .state
= ARM_CP_STATE_AA64
,
5844 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 2, .opc2
= 0,
5845 .type
= ARM_CP_NO_RAW
,
5846 .access
= PL1_RW
, .readfn
= spsel_read
, .writefn
= spsel_write
},
5847 { .name
= "SPSR_IRQ", .state
= ARM_CP_STATE_AA64
,
5848 .type
= ARM_CP_ALIAS
,
5849 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 0,
5851 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_IRQ
]) },
5852 { .name
= "SPSR_ABT", .state
= ARM_CP_STATE_AA64
,
5853 .type
= ARM_CP_ALIAS
,
5854 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 1,
5856 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_ABT
]) },
5857 { .name
= "SPSR_UND", .state
= ARM_CP_STATE_AA64
,
5858 .type
= ARM_CP_ALIAS
,
5859 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 2,
5861 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_UND
]) },
5862 { .name
= "SPSR_FIQ", .state
= ARM_CP_STATE_AA64
,
5863 .type
= ARM_CP_ALIAS
,
5864 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 3,
5866 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_FIQ
]) },
5867 { .name
= "MDCR_EL3", .state
= ARM_CP_STATE_AA64
,
5869 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 3, .opc2
= 1,
5872 .writefn
= mdcr_el3_write
,
5873 .fieldoffset
= offsetof(CPUARMState
, cp15
.mdcr_el3
) },
5874 { .name
= "SDCR", .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
5875 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 3, .opc2
= 1,
5876 .access
= PL1_RW
, .accessfn
= access_trap_aa32s_el1
,
5877 .writefn
= sdcr_write
,
5878 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.mdcr_el3
) },
5881 /* These are present only when EL1 supports AArch32 */
5882 static const ARMCPRegInfo v8_aa32_el1_reginfo
[] = {
5883 { .name
= "FPEXC32_EL2", .state
= ARM_CP_STATE_AA64
,
5884 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 3, .opc2
= 0,
5886 .type
= ARM_CP_ALIAS
| ARM_CP_FPU
| ARM_CP_EL3_NO_EL2_KEEP
,
5887 .fieldoffset
= offsetof(CPUARMState
, vfp
.xregs
[ARM_VFP_FPEXC
]) },
5888 { .name
= "DACR32_EL2", .state
= ARM_CP_STATE_AA64
,
5889 .opc0
= 3, .opc1
= 4, .crn
= 3, .crm
= 0, .opc2
= 0,
5890 .access
= PL2_RW
, .resetvalue
= 0, .type
= ARM_CP_EL3_NO_EL2_KEEP
,
5891 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
5892 .fieldoffset
= offsetof(CPUARMState
, cp15
.dacr32_el2
) },
5893 { .name
= "IFSR32_EL2", .state
= ARM_CP_STATE_AA64
,
5894 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 0, .opc2
= 1,
5895 .access
= PL2_RW
, .resetvalue
= 0, .type
= ARM_CP_EL3_NO_EL2_KEEP
,
5896 .fieldoffset
= offsetof(CPUARMState
, cp15
.ifsr32_el2
) },
5899 static void do_hcr_write(CPUARMState
*env
, uint64_t value
, uint64_t valid_mask
)
5901 ARMCPU
*cpu
= env_archcpu(env
);
5903 if (arm_feature(env
, ARM_FEATURE_V8
)) {
5904 valid_mask
|= MAKE_64BIT_MASK(0, 34); /* ARMv8.0 */
5906 valid_mask
|= MAKE_64BIT_MASK(0, 28); /* ARMv7VE */
5909 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
5910 valid_mask
&= ~HCR_HCD
;
5911 } else if (cpu
->psci_conduit
!= QEMU_PSCI_CONDUIT_SMC
) {
5913 * Architecturally HCR.TSC is RES0 if EL3 is not implemented.
5914 * However, if we're using the SMC PSCI conduit then QEMU is
5915 * effectively acting like EL3 firmware and so the guest at
5916 * EL2 should retain the ability to prevent EL1 from being
5917 * able to make SMC calls into the ersatz firmware, so in
5918 * that case HCR.TSC should be read/write.
5920 valid_mask
&= ~HCR_TSC
;
5923 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
5924 if (cpu_isar_feature(aa64_vh
, cpu
)) {
5925 valid_mask
|= HCR_E2H
;
5927 if (cpu_isar_feature(aa64_ras
, cpu
)) {
5928 valid_mask
|= HCR_TERR
| HCR_TEA
;
5930 if (cpu_isar_feature(aa64_lor
, cpu
)) {
5931 valid_mask
|= HCR_TLOR
;
5933 if (cpu_isar_feature(aa64_pauth
, cpu
)) {
5934 valid_mask
|= HCR_API
| HCR_APK
;
5936 if (cpu_isar_feature(aa64_mte
, cpu
)) {
5937 valid_mask
|= HCR_ATA
| HCR_DCT
| HCR_TID5
;
5939 if (cpu_isar_feature(aa64_scxtnum
, cpu
)) {
5940 valid_mask
|= HCR_ENSCXT
;
5942 if (cpu_isar_feature(aa64_fwb
, cpu
)) {
5943 valid_mask
|= HCR_FWB
;
5945 if (cpu_isar_feature(aa64_rme
, cpu
)) {
5946 valid_mask
|= HCR_GPF
;
5948 if (cpu_isar_feature(aa64_nv
, cpu
)) {
5949 valid_mask
|= HCR_NV
| HCR_NV1
| HCR_AT
;
5951 if (cpu_isar_feature(aa64_nv2
, cpu
)) {
5952 valid_mask
|= HCR_NV2
;
5956 if (cpu_isar_feature(any_evt
, cpu
)) {
5957 valid_mask
|= HCR_TTLBIS
| HCR_TTLBOS
| HCR_TICAB
| HCR_TOCU
| HCR_TID4
;
5958 } else if (cpu_isar_feature(any_half_evt
, cpu
)) {
5959 valid_mask
|= HCR_TICAB
| HCR_TOCU
| HCR_TID4
;
5962 /* Clear RES0 bits. */
5963 value
&= valid_mask
;
5966 * These bits change the MMU setup:
5967 * HCR_VM enables stage 2 translation
5968 * HCR_PTW forbids certain page-table setups
5969 * HCR_DC disables stage1 and enables stage2 translation
5970 * HCR_DCT enables tagging on (disabled) stage1 translation
5971 * HCR_FWB changes the interpretation of stage2 descriptor bits
5972 * HCR_NV and HCR_NV1 affect interpretation of descriptor bits
5974 if ((env
->cp15
.hcr_el2
^ value
) &
5975 (HCR_VM
| HCR_PTW
| HCR_DC
| HCR_DCT
| HCR_FWB
| HCR_NV
| HCR_NV1
)) {
5976 tlb_flush(CPU(cpu
));
5978 env
->cp15
.hcr_el2
= value
;
5981 * Updates to VI and VF require us to update the status of
5982 * virtual interrupts, which are the logical OR of these bits
5983 * and the state of the input lines from the GIC. (This requires
5984 * that we have the BQL, which is done by marking the
5985 * reginfo structs as ARM_CP_IO.)
5986 * Note that if a write to HCR pends a VIRQ or VFIQ it is never
5987 * possible for it to be taken immediately, because VIRQ and
5988 * VFIQ are masked unless running at EL0 or EL1, and HCR
5989 * can only be written at EL2.
5991 g_assert(bql_locked());
5992 arm_cpu_update_virq(cpu
);
5993 arm_cpu_update_vfiq(cpu
);
5994 arm_cpu_update_vserr(cpu
);
5997 static void hcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
5999 do_hcr_write(env
, value
, 0);
6002 static void hcr_writehigh(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6005 /* Handle HCR2 write, i.e. write to high half of HCR_EL2 */
6006 value
= deposit64(env
->cp15
.hcr_el2
, 32, 32, value
);
6007 do_hcr_write(env
, value
, MAKE_64BIT_MASK(0, 32));
6010 static void hcr_writelow(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6013 /* Handle HCR write, i.e. write to low half of HCR_EL2 */
6014 value
= deposit64(env
->cp15
.hcr_el2
, 0, 32, value
);
6015 do_hcr_write(env
, value
, MAKE_64BIT_MASK(32, 32));
6019 * Return the effective value of HCR_EL2, at the given security state.
6020 * Bits that are not included here:
6021 * RW (read from SCR_EL3.RW as needed)
6023 uint64_t arm_hcr_el2_eff_secstate(CPUARMState
*env
, ARMSecuritySpace space
)
6025 uint64_t ret
= env
->cp15
.hcr_el2
;
6027 assert(space
!= ARMSS_Root
);
6029 if (!arm_is_el2_enabled_secstate(env
, space
)) {
6031 * "This register has no effect if EL2 is not enabled in the
6032 * current Security state". This is ARMv8.4-SecEL2 speak for
6033 * !(SCR_EL3.NS==1 || SCR_EL3.EEL2==1).
6035 * Prior to that, the language was "In an implementation that
6036 * includes EL3, when the value of SCR_EL3.NS is 0 the PE behaves
6037 * as if this field is 0 for all purposes other than a direct
6038 * read or write access of HCR_EL2". With lots of enumeration
6039 * on a per-field basis. In current QEMU, this is condition
6040 * is arm_is_secure_below_el3.
6042 * Since the v8.4 language applies to the entire register, and
6043 * appears to be backward compatible, use that.
6049 * For a cpu that supports both aarch64 and aarch32, we can set bits
6050 * in HCR_EL2 (e.g. via EL3) that are RES0 when we enter EL2 as aa32.
6051 * Ignore all of the bits in HCR+HCR2 that are not valid for aarch32.
6053 if (!arm_el_is_aa64(env
, 2)) {
6054 uint64_t aa32_valid
;
6057 * These bits are up-to-date as of ARMv8.6.
6058 * For HCR, it's easiest to list just the 2 bits that are invalid.
6059 * For HCR2, list those that are valid.
6061 aa32_valid
= MAKE_64BIT_MASK(0, 32) & ~(HCR_RW
| HCR_TDZ
);
6062 aa32_valid
|= (HCR_CD
| HCR_ID
| HCR_TERR
| HCR_TEA
| HCR_MIOCNCE
|
6063 HCR_TID4
| HCR_TICAB
| HCR_TOCU
| HCR_TTLBIS
);
6067 if (ret
& HCR_TGE
) {
6068 /* These bits are up-to-date as of ARMv8.6. */
6069 if (ret
& HCR_E2H
) {
6070 ret
&= ~(HCR_VM
| HCR_FMO
| HCR_IMO
| HCR_AMO
|
6071 HCR_BSU_MASK
| HCR_DC
| HCR_TWI
| HCR_TWE
|
6072 HCR_TID0
| HCR_TID2
| HCR_TPCP
| HCR_TPU
|
6073 HCR_TDZ
| HCR_CD
| HCR_ID
| HCR_MIOCNCE
|
6074 HCR_TID4
| HCR_TICAB
| HCR_TOCU
| HCR_ENSCXT
|
6075 HCR_TTLBIS
| HCR_TTLBOS
| HCR_TID5
);
6077 ret
|= HCR_FMO
| HCR_IMO
| HCR_AMO
;
6079 ret
&= ~(HCR_SWIO
| HCR_PTW
| HCR_VF
| HCR_VI
| HCR_VSE
|
6080 HCR_FB
| HCR_TID1
| HCR_TID3
| HCR_TSC
| HCR_TACR
|
6081 HCR_TSW
| HCR_TTLB
| HCR_TVM
| HCR_HCD
| HCR_TRVM
|
6088 uint64_t arm_hcr_el2_eff(CPUARMState
*env
)
6090 if (arm_feature(env
, ARM_FEATURE_M
)) {
6093 return arm_hcr_el2_eff_secstate(env
, arm_security_space_below_el3(env
));
6097 * Corresponds to ARM pseudocode function ELIsInHost().
6099 bool el_is_in_host(CPUARMState
*env
, int el
)
6104 * Since we only care about E2H and TGE, we can skip arm_hcr_el2_eff().
6105 * Perform the simplest bit tests first, and validate EL2 afterward.
6108 return false; /* EL1 or EL3 */
6112 * Note that hcr_write() checks isar_feature_aa64_vh(),
6113 * aka HaveVirtHostExt(), in allowing HCR_E2H to be set.
6115 mask
= el
? HCR_E2H
: HCR_E2H
| HCR_TGE
;
6116 if ((env
->cp15
.hcr_el2
& mask
) != mask
) {
6120 /* TGE and/or E2H set: double check those bits are currently legal. */
6121 return arm_is_el2_enabled(env
) && arm_el_is_aa64(env
, 2);
6124 static void hcrx_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6127 uint64_t valid_mask
= 0;
6129 /* FEAT_MOPS adds MSCEn and MCE2 */
6130 if (cpu_isar_feature(aa64_mops
, env_archcpu(env
))) {
6131 valid_mask
|= HCRX_MSCEN
| HCRX_MCE2
;
6134 /* Clear RES0 bits. */
6135 env
->cp15
.hcrx_el2
= value
& valid_mask
;
6138 static CPAccessResult
access_hxen(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6141 if (arm_current_el(env
) == 2
6142 && arm_feature(env
, ARM_FEATURE_EL3
)
6143 && !(env
->cp15
.scr_el3
& SCR_HXEN
)) {
6144 return CP_ACCESS_TRAP_EL3
;
6146 return CP_ACCESS_OK
;
6149 static const ARMCPRegInfo hcrx_el2_reginfo
= {
6150 .name
= "HCRX_EL2", .state
= ARM_CP_STATE_AA64
,
6151 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 2, .opc2
= 2,
6152 .access
= PL2_RW
, .writefn
= hcrx_write
, .accessfn
= access_hxen
,
6153 .nv2_redirect_offset
= 0xa0,
6154 .fieldoffset
= offsetof(CPUARMState
, cp15
.hcrx_el2
),
6157 /* Return the effective value of HCRX_EL2. */
6158 uint64_t arm_hcrx_el2_eff(CPUARMState
*env
)
6161 * The bits in this register behave as 0 for all purposes other than
6162 * direct reads of the register if SCR_EL3.HXEn is 0.
6163 * If EL2 is not enabled in the current security state, then the
6164 * bit may behave as if 0, or as if 1, depending on the bit.
6165 * For the moment, we treat the EL2-disabled case as taking
6166 * priority over the HXEn-disabled case. This is true for the only
6167 * bit for a feature which we implement where the answer is different
6168 * for the two cases (MSCEn for FEAT_MOPS).
6169 * This may need to be revisited for future bits.
6171 if (!arm_is_el2_enabled(env
)) {
6173 if (cpu_isar_feature(aa64_mops
, env_archcpu(env
))) {
6174 /* MSCEn behaves as 1 if EL2 is not enabled */
6179 if (arm_feature(env
, ARM_FEATURE_EL3
) && !(env
->cp15
.scr_el3
& SCR_HXEN
)) {
6182 return env
->cp15
.hcrx_el2
;
6185 static void cptr_el2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6189 * For A-profile AArch32 EL3, if NSACR.CP10
6190 * is 0 then HCPTR.{TCP11,TCP10} ignore writes and read as 1.
6192 if (arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
6193 !arm_is_secure(env
) && !extract32(env
->cp15
.nsacr
, 10, 1)) {
6194 uint64_t mask
= R_HCPTR_TCP11_MASK
| R_HCPTR_TCP10_MASK
;
6195 value
= (value
& ~mask
) | (env
->cp15
.cptr_el
[2] & mask
);
6197 env
->cp15
.cptr_el
[2] = value
;
6200 static uint64_t cptr_el2_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
6203 * For A-profile AArch32 EL3, if NSACR.CP10
6204 * is 0 then HCPTR.{TCP11,TCP10} ignore writes and read as 1.
6206 uint64_t value
= env
->cp15
.cptr_el
[2];
6208 if (arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
6209 !arm_is_secure(env
) && !extract32(env
->cp15
.nsacr
, 10, 1)) {
6210 value
|= R_HCPTR_TCP11_MASK
| R_HCPTR_TCP10_MASK
;
6215 static const ARMCPRegInfo el2_cp_reginfo
[] = {
6216 { .name
= "HCR_EL2", .state
= ARM_CP_STATE_AA64
,
6218 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 0,
6219 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.hcr_el2
),
6220 .nv2_redirect_offset
= 0x78,
6221 .writefn
= hcr_write
, .raw_writefn
= raw_write
},
6222 { .name
= "HCR", .state
= ARM_CP_STATE_AA32
,
6223 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
6224 .cp
= 15, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 0,
6225 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.hcr_el2
),
6226 .writefn
= hcr_writelow
},
6227 { .name
= "HACR_EL2", .state
= ARM_CP_STATE_BOTH
,
6228 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 7,
6229 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6230 { .name
= "ELR_EL2", .state
= ARM_CP_STATE_AA64
,
6231 .type
= ARM_CP_ALIAS
| ARM_CP_NV2_REDIRECT
,
6232 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 0, .opc2
= 1,
6234 .fieldoffset
= offsetof(CPUARMState
, elr_el
[2]) },
6235 { .name
= "ESR_EL2", .state
= ARM_CP_STATE_BOTH
,
6236 .type
= ARM_CP_NV2_REDIRECT
,
6237 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 2, .opc2
= 0,
6238 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[2]) },
6239 { .name
= "FAR_EL2", .state
= ARM_CP_STATE_BOTH
,
6240 .type
= ARM_CP_NV2_REDIRECT
,
6241 .opc0
= 3, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 0,
6242 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[2]) },
6243 { .name
= "HIFAR", .state
= ARM_CP_STATE_AA32
,
6244 .type
= ARM_CP_ALIAS
,
6245 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 2,
6247 .fieldoffset
= offsetofhigh32(CPUARMState
, cp15
.far_el
[2]) },
6248 { .name
= "SPSR_EL2", .state
= ARM_CP_STATE_AA64
,
6249 .type
= ARM_CP_ALIAS
| ARM_CP_NV2_REDIRECT
,
6250 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 0, .opc2
= 0,
6252 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_HYP
]) },
6253 { .name
= "VBAR_EL2", .state
= ARM_CP_STATE_BOTH
,
6254 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 0, .opc2
= 0,
6255 .access
= PL2_RW
, .writefn
= vbar_write
,
6256 .fieldoffset
= offsetof(CPUARMState
, cp15
.vbar_el
[2]),
6258 { .name
= "SP_EL2", .state
= ARM_CP_STATE_AA64
,
6259 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 1, .opc2
= 0,
6260 .access
= PL3_RW
, .type
= ARM_CP_ALIAS
,
6261 .fieldoffset
= offsetof(CPUARMState
, sp_el
[2]) },
6262 { .name
= "CPTR_EL2", .state
= ARM_CP_STATE_BOTH
,
6263 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 2,
6264 .access
= PL2_RW
, .accessfn
= cptr_access
, .resetvalue
= 0,
6265 .fieldoffset
= offsetof(CPUARMState
, cp15
.cptr_el
[2]),
6266 .readfn
= cptr_el2_read
, .writefn
= cptr_el2_write
},
6267 { .name
= "MAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
6268 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 0,
6269 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[2]),
6271 { .name
= "HMAIR1", .state
= ARM_CP_STATE_AA32
,
6272 .cp
= 15, .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 1,
6273 .access
= PL2_RW
, .type
= ARM_CP_ALIAS
,
6274 .fieldoffset
= offsetofhigh32(CPUARMState
, cp15
.mair_el
[2]) },
6275 { .name
= "AMAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
6276 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 0,
6277 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
6279 /* HAMAIR1 is mapped to AMAIR_EL2[63:32] */
6280 { .name
= "HAMAIR1", .state
= ARM_CP_STATE_AA32
,
6281 .cp
= 15, .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 1,
6282 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
6284 { .name
= "AFSR0_EL2", .state
= ARM_CP_STATE_BOTH
,
6285 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 0,
6286 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
6288 { .name
= "AFSR1_EL2", .state
= ARM_CP_STATE_BOTH
,
6289 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 1,
6290 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
6292 { .name
= "TCR_EL2", .state
= ARM_CP_STATE_BOTH
,
6293 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 2,
6294 .access
= PL2_RW
, .writefn
= vmsa_tcr_el12_write
,
6295 .raw_writefn
= raw_write
,
6296 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[2]) },
6297 { .name
= "VTCR", .state
= ARM_CP_STATE_AA32
,
6298 .cp
= 15, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 2,
6299 .type
= ARM_CP_ALIAS
,
6300 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
6301 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.vtcr_el2
) },
6302 { .name
= "VTCR_EL2", .state
= ARM_CP_STATE_AA64
,
6303 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 2,
6305 .nv2_redirect_offset
= 0x40,
6306 /* no .writefn needed as this can't cause an ASID change */
6307 .fieldoffset
= offsetof(CPUARMState
, cp15
.vtcr_el2
) },
6308 { .name
= "VTTBR", .state
= ARM_CP_STATE_AA32
,
6309 .cp
= 15, .opc1
= 6, .crm
= 2,
6310 .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
6311 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
6312 .fieldoffset
= offsetof(CPUARMState
, cp15
.vttbr_el2
),
6313 .writefn
= vttbr_write
, .raw_writefn
= raw_write
},
6314 { .name
= "VTTBR_EL2", .state
= ARM_CP_STATE_AA64
,
6315 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 0,
6316 .access
= PL2_RW
, .writefn
= vttbr_write
, .raw_writefn
= raw_write
,
6317 .nv2_redirect_offset
= 0x20,
6318 .fieldoffset
= offsetof(CPUARMState
, cp15
.vttbr_el2
) },
6319 { .name
= "SCTLR_EL2", .state
= ARM_CP_STATE_BOTH
,
6320 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 0,
6321 .access
= PL2_RW
, .raw_writefn
= raw_write
, .writefn
= sctlr_write
,
6322 .fieldoffset
= offsetof(CPUARMState
, cp15
.sctlr_el
[2]) },
6323 { .name
= "TPIDR_EL2", .state
= ARM_CP_STATE_BOTH
,
6324 .opc0
= 3, .opc1
= 4, .crn
= 13, .crm
= 0, .opc2
= 2,
6325 .access
= PL2_RW
, .resetvalue
= 0,
6326 .nv2_redirect_offset
= 0x90,
6327 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[2]) },
6328 { .name
= "TTBR0_EL2", .state
= ARM_CP_STATE_AA64
,
6329 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 0,
6330 .access
= PL2_RW
, .resetvalue
= 0,
6331 .writefn
= vmsa_tcr_ttbr_el2_write
, .raw_writefn
= raw_write
,
6332 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[2]) },
6333 { .name
= "HTTBR", .cp
= 15, .opc1
= 4, .crm
= 2,
6334 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
6335 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[2]) },
6336 { .name
= "TLBIALLNSNH",
6337 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 4,
6338 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
6339 .writefn
= tlbiall_nsnh_write
},
6340 { .name
= "TLBIALLNSNHIS",
6341 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 4,
6342 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
6343 .writefn
= tlbiall_nsnh_is_write
},
6344 { .name
= "TLBIALLH", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 0,
6345 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
6346 .writefn
= tlbiall_hyp_write
},
6347 { .name
= "TLBIALLHIS", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 0,
6348 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
6349 .writefn
= tlbiall_hyp_is_write
},
6350 { .name
= "TLBIMVAH", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 1,
6351 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
6352 .writefn
= tlbimva_hyp_write
},
6353 { .name
= "TLBIMVAHIS", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 1,
6354 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
6355 .writefn
= tlbimva_hyp_is_write
},
6356 { .name
= "TLBI_ALLE2", .state
= ARM_CP_STATE_AA64
,
6357 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 0,
6358 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
6359 .writefn
= tlbi_aa64_alle2_write
},
6360 { .name
= "TLBI_VAE2", .state
= ARM_CP_STATE_AA64
,
6361 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 1,
6362 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
6363 .writefn
= tlbi_aa64_vae2_write
},
6364 { .name
= "TLBI_VALE2", .state
= ARM_CP_STATE_AA64
,
6365 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 5,
6366 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
6367 .writefn
= tlbi_aa64_vae2_write
},
6368 { .name
= "TLBI_ALLE2IS", .state
= ARM_CP_STATE_AA64
,
6369 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 0,
6370 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
6371 .writefn
= tlbi_aa64_alle2is_write
},
6372 { .name
= "TLBI_VAE2IS", .state
= ARM_CP_STATE_AA64
,
6373 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 1,
6374 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
6375 .writefn
= tlbi_aa64_vae2is_write
},
6376 { .name
= "TLBI_VALE2IS", .state
= ARM_CP_STATE_AA64
,
6377 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 5,
6378 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
6379 .writefn
= tlbi_aa64_vae2is_write
},
6380 #ifndef CONFIG_USER_ONLY
6382 * Unlike the other EL2-related AT operations, these must
6383 * UNDEF from EL3 if EL2 is not implemented, which is why we
6384 * define them here rather than with the rest of the AT ops.
6386 { .name
= "AT_S1E2R", .state
= ARM_CP_STATE_AA64
,
6387 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 0,
6388 .access
= PL2_W
, .accessfn
= at_s1e2_access
,
6389 .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
| ARM_CP_EL3_NO_EL2_UNDEF
,
6390 .writefn
= ats_write64
},
6391 { .name
= "AT_S1E2W", .state
= ARM_CP_STATE_AA64
,
6392 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 1,
6393 .access
= PL2_W
, .accessfn
= at_s1e2_access
,
6394 .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
| ARM_CP_EL3_NO_EL2_UNDEF
,
6395 .writefn
= ats_write64
},
6397 * The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE
6398 * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3
6399 * with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose
6400 * to behave as if SCR.NS was 1.
6402 { .name
= "ATS1HR", .cp
= 15, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 0,
6404 .writefn
= ats1h_write
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
},
6405 { .name
= "ATS1HW", .cp
= 15, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 1,
6407 .writefn
= ats1h_write
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
},
6408 { .name
= "CNTHCTL_EL2", .state
= ARM_CP_STATE_BOTH
,
6409 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 1, .opc2
= 0,
6411 * ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the
6412 * reset values as IMPDEF. We choose to reset to 3 to comply with
6413 * both ARMv7 and ARMv8.
6415 .access
= PL2_RW
, .type
= ARM_CP_IO
, .resetvalue
= 3,
6416 .writefn
= gt_cnthctl_write
, .raw_writefn
= raw_write
,
6417 .fieldoffset
= offsetof(CPUARMState
, cp15
.cnthctl_el2
) },
6418 { .name
= "CNTVOFF_EL2", .state
= ARM_CP_STATE_AA64
,
6419 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 0, .opc2
= 3,
6420 .access
= PL2_RW
, .type
= ARM_CP_IO
, .resetvalue
= 0,
6421 .writefn
= gt_cntvoff_write
,
6422 .nv2_redirect_offset
= 0x60,
6423 .fieldoffset
= offsetof(CPUARMState
, cp15
.cntvoff_el2
) },
6424 { .name
= "CNTVOFF", .cp
= 15, .opc1
= 4, .crm
= 14,
6425 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
| ARM_CP_IO
,
6426 .writefn
= gt_cntvoff_write
,
6427 .fieldoffset
= offsetof(CPUARMState
, cp15
.cntvoff_el2
) },
6428 { .name
= "CNTHP_CVAL_EL2", .state
= ARM_CP_STATE_AA64
,
6429 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 2,
6430 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYP
].cval
),
6431 .type
= ARM_CP_IO
, .access
= PL2_RW
,
6432 .writefn
= gt_hyp_cval_write
, .raw_writefn
= raw_write
},
6433 { .name
= "CNTHP_CVAL", .cp
= 15, .opc1
= 6, .crm
= 14,
6434 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYP
].cval
),
6435 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_IO
,
6436 .writefn
= gt_hyp_cval_write
, .raw_writefn
= raw_write
},
6437 { .name
= "CNTHP_TVAL_EL2", .state
= ARM_CP_STATE_BOTH
,
6438 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 0,
6439 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL2_RW
,
6440 .resetfn
= gt_hyp_timer_reset
,
6441 .readfn
= gt_hyp_tval_read
, .writefn
= gt_hyp_tval_write
},
6442 { .name
= "CNTHP_CTL_EL2", .state
= ARM_CP_STATE_BOTH
,
6444 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 1,
6446 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYP
].ctl
),
6448 .writefn
= gt_hyp_ctl_write
, .raw_writefn
= raw_write
},
6450 { .name
= "HPFAR", .state
= ARM_CP_STATE_AA32
,
6451 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 4,
6452 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
6453 .fieldoffset
= offsetof(CPUARMState
, cp15
.hpfar_el2
) },
6454 { .name
= "HPFAR_EL2", .state
= ARM_CP_STATE_AA64
,
6455 .opc0
= 3, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 4,
6457 .fieldoffset
= offsetof(CPUARMState
, cp15
.hpfar_el2
) },
6458 { .name
= "HSTR_EL2", .state
= ARM_CP_STATE_BOTH
,
6459 .cp
= 15, .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 3,
6461 .nv2_redirect_offset
= 0x80,
6462 .fieldoffset
= offsetof(CPUARMState
, cp15
.hstr_el2
) },
6465 static const ARMCPRegInfo el2_v8_cp_reginfo
[] = {
6466 { .name
= "HCR2", .state
= ARM_CP_STATE_AA32
,
6467 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
6468 .cp
= 15, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 4,
6470 .fieldoffset
= offsetofhigh32(CPUARMState
, cp15
.hcr_el2
),
6471 .writefn
= hcr_writehigh
},
6474 static CPAccessResult
sel2_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6477 if (arm_current_el(env
) == 3 || arm_is_secure_below_el3(env
)) {
6478 return CP_ACCESS_OK
;
6480 return CP_ACCESS_TRAP_UNCATEGORIZED
;
6483 static const ARMCPRegInfo el2_sec_cp_reginfo
[] = {
6484 { .name
= "VSTTBR_EL2", .state
= ARM_CP_STATE_AA64
,
6485 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 6, .opc2
= 0,
6486 .access
= PL2_RW
, .accessfn
= sel2_access
,
6487 .nv2_redirect_offset
= 0x30,
6488 .fieldoffset
= offsetof(CPUARMState
, cp15
.vsttbr_el2
) },
6489 { .name
= "VSTCR_EL2", .state
= ARM_CP_STATE_AA64
,
6490 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 6, .opc2
= 2,
6491 .access
= PL2_RW
, .accessfn
= sel2_access
,
6492 .nv2_redirect_offset
= 0x48,
6493 .fieldoffset
= offsetof(CPUARMState
, cp15
.vstcr_el2
) },
6496 static CPAccessResult
nsacr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6500 * The NSACR is RW at EL3, and RO for NS EL1 and NS EL2.
6501 * At Secure EL1 it traps to EL3 or EL2.
6503 if (arm_current_el(env
) == 3) {
6504 return CP_ACCESS_OK
;
6506 if (arm_is_secure_below_el3(env
)) {
6507 if (env
->cp15
.scr_el3
& SCR_EEL2
) {
6508 return CP_ACCESS_TRAP_EL2
;
6510 return CP_ACCESS_TRAP_EL3
;
6512 /* Accesses from EL1 NS and EL2 NS are UNDEF for write but allow reads. */
6514 return CP_ACCESS_OK
;
6516 return CP_ACCESS_TRAP_UNCATEGORIZED
;
6519 static const ARMCPRegInfo el3_cp_reginfo
[] = {
6520 { .name
= "SCR_EL3", .state
= ARM_CP_STATE_AA64
,
6521 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 0,
6522 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.scr_el3
),
6523 .resetfn
= scr_reset
, .writefn
= scr_write
, .raw_writefn
= raw_write
},
6524 { .name
= "SCR", .type
= ARM_CP_ALIAS
| ARM_CP_NEWEL
,
6525 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 0,
6526 .access
= PL1_RW
, .accessfn
= access_trap_aa32s_el1
,
6527 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.scr_el3
),
6528 .writefn
= scr_write
, .raw_writefn
= raw_write
},
6529 { .name
= "SDER32_EL3", .state
= ARM_CP_STATE_AA64
,
6530 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 1,
6531 .access
= PL3_RW
, .resetvalue
= 0,
6532 .fieldoffset
= offsetof(CPUARMState
, cp15
.sder
) },
6534 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 1,
6535 .access
= PL3_RW
, .resetvalue
= 0,
6536 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.sder
) },
6537 { .name
= "MVBAR", .cp
= 15, .opc1
= 0, .crn
= 12, .crm
= 0, .opc2
= 1,
6538 .access
= PL1_RW
, .accessfn
= access_trap_aa32s_el1
,
6539 .writefn
= vbar_write
, .resetvalue
= 0,
6540 .fieldoffset
= offsetof(CPUARMState
, cp15
.mvbar
) },
6541 { .name
= "TTBR0_EL3", .state
= ARM_CP_STATE_AA64
,
6542 .opc0
= 3, .opc1
= 6, .crn
= 2, .crm
= 0, .opc2
= 0,
6543 .access
= PL3_RW
, .resetvalue
= 0,
6544 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[3]) },
6545 { .name
= "TCR_EL3", .state
= ARM_CP_STATE_AA64
,
6546 .opc0
= 3, .opc1
= 6, .crn
= 2, .crm
= 0, .opc2
= 2,
6548 /* no .writefn needed as this can't cause an ASID change */
6550 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[3]) },
6551 { .name
= "ELR_EL3", .state
= ARM_CP_STATE_AA64
,
6552 .type
= ARM_CP_ALIAS
,
6553 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 0, .opc2
= 1,
6555 .fieldoffset
= offsetof(CPUARMState
, elr_el
[3]) },
6556 { .name
= "ESR_EL3", .state
= ARM_CP_STATE_AA64
,
6557 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 2, .opc2
= 0,
6558 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[3]) },
6559 { .name
= "FAR_EL3", .state
= ARM_CP_STATE_AA64
,
6560 .opc0
= 3, .opc1
= 6, .crn
= 6, .crm
= 0, .opc2
= 0,
6561 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[3]) },
6562 { .name
= "SPSR_EL3", .state
= ARM_CP_STATE_AA64
,
6563 .type
= ARM_CP_ALIAS
,
6564 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 0, .opc2
= 0,
6566 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_MON
]) },
6567 { .name
= "VBAR_EL3", .state
= ARM_CP_STATE_AA64
,
6568 .opc0
= 3, .opc1
= 6, .crn
= 12, .crm
= 0, .opc2
= 0,
6569 .access
= PL3_RW
, .writefn
= vbar_write
,
6570 .fieldoffset
= offsetof(CPUARMState
, cp15
.vbar_el
[3]),
6572 { .name
= "CPTR_EL3", .state
= ARM_CP_STATE_AA64
,
6573 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 2,
6574 .access
= PL3_RW
, .accessfn
= cptr_access
, .resetvalue
= 0,
6575 .fieldoffset
= offsetof(CPUARMState
, cp15
.cptr_el
[3]) },
6576 { .name
= "TPIDR_EL3", .state
= ARM_CP_STATE_AA64
,
6577 .opc0
= 3, .opc1
= 6, .crn
= 13, .crm
= 0, .opc2
= 2,
6578 .access
= PL3_RW
, .resetvalue
= 0,
6579 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[3]) },
6580 { .name
= "AMAIR_EL3", .state
= ARM_CP_STATE_AA64
,
6581 .opc0
= 3, .opc1
= 6, .crn
= 10, .crm
= 3, .opc2
= 0,
6582 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
6584 { .name
= "AFSR0_EL3", .state
= ARM_CP_STATE_BOTH
,
6585 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 1, .opc2
= 0,
6586 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
6588 { .name
= "AFSR1_EL3", .state
= ARM_CP_STATE_BOTH
,
6589 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 1, .opc2
= 1,
6590 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
6592 { .name
= "TLBI_ALLE3IS", .state
= ARM_CP_STATE_AA64
,
6593 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 3, .opc2
= 0,
6594 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6595 .writefn
= tlbi_aa64_alle3is_write
},
6596 { .name
= "TLBI_VAE3IS", .state
= ARM_CP_STATE_AA64
,
6597 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 3, .opc2
= 1,
6598 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6599 .writefn
= tlbi_aa64_vae3is_write
},
6600 { .name
= "TLBI_VALE3IS", .state
= ARM_CP_STATE_AA64
,
6601 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 3, .opc2
= 5,
6602 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6603 .writefn
= tlbi_aa64_vae3is_write
},
6604 { .name
= "TLBI_ALLE3", .state
= ARM_CP_STATE_AA64
,
6605 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 0,
6606 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6607 .writefn
= tlbi_aa64_alle3_write
},
6608 { .name
= "TLBI_VAE3", .state
= ARM_CP_STATE_AA64
,
6609 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 1,
6610 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6611 .writefn
= tlbi_aa64_vae3_write
},
6612 { .name
= "TLBI_VALE3", .state
= ARM_CP_STATE_AA64
,
6613 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 5,
6614 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6615 .writefn
= tlbi_aa64_vae3_write
},
6618 #ifndef CONFIG_USER_ONLY
6620 static CPAccessResult
e2h_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6623 if (arm_current_el(env
) == 1) {
6624 /* This must be a FEAT_NV access */
6625 return CP_ACCESS_OK
;
6627 if (!(arm_hcr_el2_eff(env
) & HCR_E2H
)) {
6628 return CP_ACCESS_TRAP_UNCATEGORIZED
;
6630 return CP_ACCESS_OK
;
6633 static CPAccessResult
access_el1nvpct(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6636 if (arm_current_el(env
) == 1) {
6637 /* This must be a FEAT_NV access with NVx == 101 */
6638 if (FIELD_EX64(env
->cp15
.cnthctl_el2
, CNTHCTL
, EL1NVPCT
)) {
6639 return CP_ACCESS_TRAP_EL2
;
6642 return e2h_access(env
, ri
, isread
);
6645 static CPAccessResult
access_el1nvvct(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6648 if (arm_current_el(env
) == 1) {
6649 /* This must be a FEAT_NV access with NVx == 101 */
6650 if (FIELD_EX64(env
->cp15
.cnthctl_el2
, CNTHCTL
, EL1NVVCT
)) {
6651 return CP_ACCESS_TRAP_EL2
;
6654 return e2h_access(env
, ri
, isread
);
6657 /* Test if system register redirection is to occur in the current state. */
6658 static bool redirect_for_e2h(CPUARMState
*env
)
6660 return arm_current_el(env
) == 2 && (arm_hcr_el2_eff(env
) & HCR_E2H
);
6663 static uint64_t el2_e2h_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
6667 if (redirect_for_e2h(env
)) {
6668 /* Switch to the saved EL2 version of the register. */
6670 readfn
= ri
->readfn
;
6672 readfn
= ri
->orig_readfn
;
6674 if (readfn
== NULL
) {
6677 return readfn(env
, ri
);
6680 static void el2_e2h_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6685 if (redirect_for_e2h(env
)) {
6686 /* Switch to the saved EL2 version of the register. */
6688 writefn
= ri
->writefn
;
6690 writefn
= ri
->orig_writefn
;
6692 if (writefn
== NULL
) {
6693 writefn
= raw_write
;
6695 writefn(env
, ri
, value
);
6698 static uint64_t el2_e2h_e12_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
6700 /* Pass the EL1 register accessor its ri, not the EL12 alias ri */
6701 return ri
->orig_readfn(env
, ri
->opaque
);
6704 static void el2_e2h_e12_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6707 /* Pass the EL1 register accessor its ri, not the EL12 alias ri */
6708 return ri
->orig_writefn(env
, ri
->opaque
, value
);
6711 static CPAccessResult
el2_e2h_e12_access(CPUARMState
*env
,
6712 const ARMCPRegInfo
*ri
,
6715 if (arm_current_el(env
) == 1) {
6717 * This must be a FEAT_NV access (will either trap or redirect
6718 * to memory). None of the registers with _EL12 aliases want to
6719 * apply their trap controls for this kind of access, so don't
6720 * call the orig_accessfn or do the "UNDEF when E2H is 0" check.
6722 return CP_ACCESS_OK
;
6724 /* FOO_EL12 aliases only exist when E2H is 1; otherwise they UNDEF */
6725 if (!(arm_hcr_el2_eff(env
) & HCR_E2H
)) {
6726 return CP_ACCESS_TRAP_UNCATEGORIZED
;
6728 if (ri
->orig_accessfn
) {
6729 return ri
->orig_accessfn(env
, ri
->opaque
, isread
);
6731 return CP_ACCESS_OK
;
6734 static void define_arm_vh_e2h_redirects_aliases(ARMCPU
*cpu
)
6737 uint32_t src_key
, dst_key
, new_key
;
6738 const char *src_name
, *dst_name
, *new_name
;
6739 bool (*feature
)(const ARMISARegisters
*id
);
6742 #define K(op0, op1, crn, crm, op2) \
6743 ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, crn, crm, op0, op1, op2)
6745 static const struct E2HAlias aliases
[] = {
6746 { K(3, 0, 1, 0, 0), K(3, 4, 1, 0, 0), K(3, 5, 1, 0, 0),
6747 "SCTLR", "SCTLR_EL2", "SCTLR_EL12" },
6748 { K(3, 0, 1, 0, 2), K(3, 4, 1, 1, 2), K(3, 5, 1, 0, 2),
6749 "CPACR", "CPTR_EL2", "CPACR_EL12" },
6750 { K(3, 0, 2, 0, 0), K(3, 4, 2, 0, 0), K(3, 5, 2, 0, 0),
6751 "TTBR0_EL1", "TTBR0_EL2", "TTBR0_EL12" },
6752 { K(3, 0, 2, 0, 1), K(3, 4, 2, 0, 1), K(3, 5, 2, 0, 1),
6753 "TTBR1_EL1", "TTBR1_EL2", "TTBR1_EL12" },
6754 { K(3, 0, 2, 0, 2), K(3, 4, 2, 0, 2), K(3, 5, 2, 0, 2),
6755 "TCR_EL1", "TCR_EL2", "TCR_EL12" },
6756 { K(3, 0, 4, 0, 0), K(3, 4, 4, 0, 0), K(3, 5, 4, 0, 0),
6757 "SPSR_EL1", "SPSR_EL2", "SPSR_EL12" },
6758 { K(3, 0, 4, 0, 1), K(3, 4, 4, 0, 1), K(3, 5, 4, 0, 1),
6759 "ELR_EL1", "ELR_EL2", "ELR_EL12" },
6760 { K(3, 0, 5, 1, 0), K(3, 4, 5, 1, 0), K(3, 5, 5, 1, 0),
6761 "AFSR0_EL1", "AFSR0_EL2", "AFSR0_EL12" },
6762 { K(3, 0, 5, 1, 1), K(3, 4, 5, 1, 1), K(3, 5, 5, 1, 1),
6763 "AFSR1_EL1", "AFSR1_EL2", "AFSR1_EL12" },
6764 { K(3, 0, 5, 2, 0), K(3, 4, 5, 2, 0), K(3, 5, 5, 2, 0),
6765 "ESR_EL1", "ESR_EL2", "ESR_EL12" },
6766 { K(3, 0, 6, 0, 0), K(3, 4, 6, 0, 0), K(3, 5, 6, 0, 0),
6767 "FAR_EL1", "FAR_EL2", "FAR_EL12" },
6768 { K(3, 0, 10, 2, 0), K(3, 4, 10, 2, 0), K(3, 5, 10, 2, 0),
6769 "MAIR_EL1", "MAIR_EL2", "MAIR_EL12" },
6770 { K(3, 0, 10, 3, 0), K(3, 4, 10, 3, 0), K(3, 5, 10, 3, 0),
6771 "AMAIR0", "AMAIR_EL2", "AMAIR_EL12" },
6772 { K(3, 0, 12, 0, 0), K(3, 4, 12, 0, 0), K(3, 5, 12, 0, 0),
6773 "VBAR", "VBAR_EL2", "VBAR_EL12" },
6774 { K(3, 0, 13, 0, 1), K(3, 4, 13, 0, 1), K(3, 5, 13, 0, 1),
6775 "CONTEXTIDR_EL1", "CONTEXTIDR_EL2", "CONTEXTIDR_EL12" },
6776 { K(3, 0, 14, 1, 0), K(3, 4, 14, 1, 0), K(3, 5, 14, 1, 0),
6777 "CNTKCTL", "CNTHCTL_EL2", "CNTKCTL_EL12" },
6780 * Note that redirection of ZCR is mentioned in the description
6781 * of ZCR_EL2, and aliasing in the description of ZCR_EL1, but
6782 * not in the summary table.
6784 { K(3, 0, 1, 2, 0), K(3, 4, 1, 2, 0), K(3, 5, 1, 2, 0),
6785 "ZCR_EL1", "ZCR_EL2", "ZCR_EL12", isar_feature_aa64_sve
},
6786 { K(3, 0, 1, 2, 6), K(3, 4, 1, 2, 6), K(3, 5, 1, 2, 6),
6787 "SMCR_EL1", "SMCR_EL2", "SMCR_EL12", isar_feature_aa64_sme
},
6789 { K(3, 0, 5, 6, 0), K(3, 4, 5, 6, 0), K(3, 5, 5, 6, 0),
6790 "TFSR_EL1", "TFSR_EL2", "TFSR_EL12", isar_feature_aa64_mte
},
6792 { K(3, 0, 13, 0, 7), K(3, 4, 13, 0, 7), K(3, 5, 13, 0, 7),
6793 "SCXTNUM_EL1", "SCXTNUM_EL2", "SCXTNUM_EL12",
6794 isar_feature_aa64_scxtnum
},
6796 /* TODO: ARMv8.2-SPE -- PMSCR_EL2 */
6797 /* TODO: ARMv8.4-Trace -- TRFCR_EL2 */
6803 for (i
= 0; i
< ARRAY_SIZE(aliases
); i
++) {
6804 const struct E2HAlias
*a
= &aliases
[i
];
6805 ARMCPRegInfo
*src_reg
, *dst_reg
, *new_reg
;
6808 if (a
->feature
&& !a
->feature(&cpu
->isar
)) {
6812 src_reg
= g_hash_table_lookup(cpu
->cp_regs
,
6813 (gpointer
)(uintptr_t)a
->src_key
);
6814 dst_reg
= g_hash_table_lookup(cpu
->cp_regs
,
6815 (gpointer
)(uintptr_t)a
->dst_key
);
6816 g_assert(src_reg
!= NULL
);
6817 g_assert(dst_reg
!= NULL
);
6819 /* Cross-compare names to detect typos in the keys. */
6820 g_assert(strcmp(src_reg
->name
, a
->src_name
) == 0);
6821 g_assert(strcmp(dst_reg
->name
, a
->dst_name
) == 0);
6823 /* None of the core system registers use opaque; we will. */
6824 g_assert(src_reg
->opaque
== NULL
);
6826 /* Create alias before redirection so we dup the right data. */
6827 new_reg
= g_memdup(src_reg
, sizeof(ARMCPRegInfo
));
6829 new_reg
->name
= a
->new_name
;
6830 new_reg
->type
|= ARM_CP_ALIAS
;
6831 /* Remove PL1/PL0 access, leaving PL2/PL3 R/W in place. */
6832 new_reg
->access
&= PL2_RW
| PL3_RW
;
6833 /* The new_reg op fields are as per new_key, not the target reg */
6834 new_reg
->crn
= (a
->new_key
& CP_REG_ARM64_SYSREG_CRN_MASK
)
6835 >> CP_REG_ARM64_SYSREG_CRN_SHIFT
;
6836 new_reg
->crm
= (a
->new_key
& CP_REG_ARM64_SYSREG_CRM_MASK
)
6837 >> CP_REG_ARM64_SYSREG_CRM_SHIFT
;
6838 new_reg
->opc0
= (a
->new_key
& CP_REG_ARM64_SYSREG_OP0_MASK
)
6839 >> CP_REG_ARM64_SYSREG_OP0_SHIFT
;
6840 new_reg
->opc1
= (a
->new_key
& CP_REG_ARM64_SYSREG_OP1_MASK
)
6841 >> CP_REG_ARM64_SYSREG_OP1_SHIFT
;
6842 new_reg
->opc2
= (a
->new_key
& CP_REG_ARM64_SYSREG_OP2_MASK
)
6843 >> CP_REG_ARM64_SYSREG_OP2_SHIFT
;
6844 new_reg
->opaque
= src_reg
;
6845 new_reg
->orig_readfn
= src_reg
->readfn
?: raw_read
;
6846 new_reg
->orig_writefn
= src_reg
->writefn
?: raw_write
;
6847 new_reg
->orig_accessfn
= src_reg
->accessfn
;
6848 if (!new_reg
->raw_readfn
) {
6849 new_reg
->raw_readfn
= raw_read
;
6851 if (!new_reg
->raw_writefn
) {
6852 new_reg
->raw_writefn
= raw_write
;
6854 new_reg
->readfn
= el2_e2h_e12_read
;
6855 new_reg
->writefn
= el2_e2h_e12_write
;
6856 new_reg
->accessfn
= el2_e2h_e12_access
;
6859 * If the _EL1 register is redirected to memory by FEAT_NV2,
6860 * then it shares the offset with the _EL12 register,
6861 * and which one is redirected depends on HCR_EL2.NV1.
6863 if (new_reg
->nv2_redirect_offset
) {
6864 assert(new_reg
->nv2_redirect_offset
& NV2_REDIR_NV1
);
6865 new_reg
->nv2_redirect_offset
&= ~NV2_REDIR_NV1
;
6866 new_reg
->nv2_redirect_offset
|= NV2_REDIR_NO_NV1
;
6869 ok
= g_hash_table_insert(cpu
->cp_regs
,
6870 (gpointer
)(uintptr_t)a
->new_key
, new_reg
);
6873 src_reg
->opaque
= dst_reg
;
6874 src_reg
->orig_readfn
= src_reg
->readfn
?: raw_read
;
6875 src_reg
->orig_writefn
= src_reg
->writefn
?: raw_write
;
6876 if (!src_reg
->raw_readfn
) {
6877 src_reg
->raw_readfn
= raw_read
;
6879 if (!src_reg
->raw_writefn
) {
6880 src_reg
->raw_writefn
= raw_write
;
6882 src_reg
->readfn
= el2_e2h_read
;
6883 src_reg
->writefn
= el2_e2h_write
;
6888 static CPAccessResult
ctr_el0_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6891 int cur_el
= arm_current_el(env
);
6894 uint64_t hcr
= arm_hcr_el2_eff(env
);
6897 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
6898 if (!(env
->cp15
.sctlr_el
[2] & SCTLR_UCT
)) {
6899 return CP_ACCESS_TRAP_EL2
;
6902 if (!(env
->cp15
.sctlr_el
[1] & SCTLR_UCT
)) {
6903 return CP_ACCESS_TRAP
;
6905 if (hcr
& HCR_TID2
) {
6906 return CP_ACCESS_TRAP_EL2
;
6909 } else if (hcr
& HCR_TID2
) {
6910 return CP_ACCESS_TRAP_EL2
;
6914 if (arm_current_el(env
) < 2 && arm_hcr_el2_eff(env
) & HCR_TID2
) {
6915 return CP_ACCESS_TRAP_EL2
;
6918 return CP_ACCESS_OK
;
6922 * Check for traps to RAS registers, which are controlled
6923 * by HCR_EL2.TERR and SCR_EL3.TERR.
6925 static CPAccessResult
access_terr(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6928 int el
= arm_current_el(env
);
6930 if (el
< 2 && (arm_hcr_el2_eff(env
) & HCR_TERR
)) {
6931 return CP_ACCESS_TRAP_EL2
;
6933 if (el
< 3 && (env
->cp15
.scr_el3
& SCR_TERR
)) {
6934 return CP_ACCESS_TRAP_EL3
;
6936 return CP_ACCESS_OK
;
6939 static uint64_t disr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
6941 int el
= arm_current_el(env
);
6943 if (el
< 2 && (arm_hcr_el2_eff(env
) & HCR_AMO
)) {
6944 return env
->cp15
.vdisr_el2
;
6946 if (el
< 3 && (env
->cp15
.scr_el3
& SCR_EA
)) {
6947 return 0; /* RAZ/WI */
6949 return env
->cp15
.disr_el1
;
6952 static void disr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t val
)
6954 int el
= arm_current_el(env
);
6956 if (el
< 2 && (arm_hcr_el2_eff(env
) & HCR_AMO
)) {
6957 env
->cp15
.vdisr_el2
= val
;
6960 if (el
< 3 && (env
->cp15
.scr_el3
& SCR_EA
)) {
6961 return; /* RAZ/WI */
6963 env
->cp15
.disr_el1
= val
;
6967 * Minimal RAS implementation with no Error Records.
6968 * Which means that all of the Error Record registers:
6976 * ERXPFGCDN_EL1 (RASv1p1)
6977 * ERXPFGCTL_EL1 (RASv1p1)
6978 * ERXPFGF_EL1 (RASv1p1)
6982 * may generate UNDEFINED, which is the effect we get by not
6983 * listing them at all.
6985 * These registers have fine-grained trap bits, but UNDEF-to-EL1
6986 * is higher priority than FGT-to-EL2 so we do not need to list them
6987 * in order to check for an FGT.
6989 static const ARMCPRegInfo minimal_ras_reginfo
[] = {
6990 { .name
= "DISR_EL1", .state
= ARM_CP_STATE_BOTH
,
6991 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 1, .opc2
= 1,
6992 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.disr_el1
),
6993 .readfn
= disr_read
, .writefn
= disr_write
, .raw_writefn
= raw_write
},
6994 { .name
= "ERRIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
6995 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 3, .opc2
= 0,
6996 .access
= PL1_R
, .accessfn
= access_terr
,
6997 .fgt
= FGT_ERRIDR_EL1
,
6998 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6999 { .name
= "VDISR_EL2", .state
= ARM_CP_STATE_BOTH
,
7000 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 1, .opc2
= 1,
7001 .nv2_redirect_offset
= 0x500,
7002 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.vdisr_el2
) },
7003 { .name
= "VSESR_EL2", .state
= ARM_CP_STATE_BOTH
,
7004 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 2, .opc2
= 3,
7005 .nv2_redirect_offset
= 0x508,
7006 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.vsesr_el2
) },
7010 * Return the exception level to which exceptions should be taken
7011 * via SVEAccessTrap. This excludes the check for whether the exception
7012 * should be routed through AArch64.AdvSIMDFPAccessTrap. That can easily
7013 * be found by testing 0 < fp_exception_el < sve_exception_el.
7015 * C.f. the ARM pseudocode function CheckSVEEnabled. Note that the
7016 * pseudocode does *not* separate out the FP trap checks, but has them
7017 * all in one function.
7019 int sve_exception_el(CPUARMState
*env
, int el
)
7021 #ifndef CONFIG_USER_ONLY
7022 if (el
<= 1 && !el_is_in_host(env
, el
)) {
7023 switch (FIELD_EX64(env
->cp15
.cpacr_el1
, CPACR_EL1
, ZEN
)) {
7035 if (el
<= 2 && arm_is_el2_enabled(env
)) {
7036 /* CPTR_EL2 changes format with HCR_EL2.E2H (regardless of TGE). */
7037 if (env
->cp15
.hcr_el2
& HCR_E2H
) {
7038 switch (FIELD_EX64(env
->cp15
.cptr_el
[2], CPTR_EL2
, ZEN
)) {
7040 if (el
!= 0 || !(env
->cp15
.hcr_el2
& HCR_TGE
)) {
7049 if (FIELD_EX64(env
->cp15
.cptr_el
[2], CPTR_EL2
, TZ
)) {
7055 /* CPTR_EL3. Since EZ is negative we must check for EL3. */
7056 if (arm_feature(env
, ARM_FEATURE_EL3
)
7057 && !FIELD_EX64(env
->cp15
.cptr_el
[3], CPTR_EL3
, EZ
)) {
7065 * Return the exception level to which exceptions should be taken for SME.
7066 * C.f. the ARM pseudocode function CheckSMEAccess.
7068 int sme_exception_el(CPUARMState
*env
, int el
)
7070 #ifndef CONFIG_USER_ONLY
7071 if (el
<= 1 && !el_is_in_host(env
, el
)) {
7072 switch (FIELD_EX64(env
->cp15
.cpacr_el1
, CPACR_EL1
, SMEN
)) {
7084 if (el
<= 2 && arm_is_el2_enabled(env
)) {
7085 /* CPTR_EL2 changes format with HCR_EL2.E2H (regardless of TGE). */
7086 if (env
->cp15
.hcr_el2
& HCR_E2H
) {
7087 switch (FIELD_EX64(env
->cp15
.cptr_el
[2], CPTR_EL2
, SMEN
)) {
7089 if (el
!= 0 || !(env
->cp15
.hcr_el2
& HCR_TGE
)) {
7098 if (FIELD_EX64(env
->cp15
.cptr_el
[2], CPTR_EL2
, TSM
)) {
7104 /* CPTR_EL3. Since ESM is negative we must check for EL3. */
7105 if (arm_feature(env
, ARM_FEATURE_EL3
)
7106 && !FIELD_EX64(env
->cp15
.cptr_el
[3], CPTR_EL3
, ESM
)) {
7114 * Given that SVE is enabled, return the vector length for EL.
7116 uint32_t sve_vqm1_for_el_sm(CPUARMState
*env
, int el
, bool sm
)
7118 ARMCPU
*cpu
= env_archcpu(env
);
7119 uint64_t *cr
= env
->vfp
.zcr_el
;
7120 uint32_t map
= cpu
->sve_vq
.map
;
7121 uint32_t len
= ARM_MAX_VQ
- 1;
7124 cr
= env
->vfp
.smcr_el
;
7125 map
= cpu
->sme_vq
.map
;
7128 if (el
<= 1 && !el_is_in_host(env
, el
)) {
7129 len
= MIN(len
, 0xf & (uint32_t)cr
[1]);
7131 if (el
<= 2 && arm_feature(env
, ARM_FEATURE_EL2
)) {
7132 len
= MIN(len
, 0xf & (uint32_t)cr
[2]);
7134 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
7135 len
= MIN(len
, 0xf & (uint32_t)cr
[3]);
7138 map
&= MAKE_64BIT_MASK(0, len
+ 1);
7140 return 31 - clz32(map
);
7143 /* Bit 0 is always set for Normal SVE -- not so for Streaming SVE. */
7145 return ctz32(cpu
->sme_vq
.map
);
7148 uint32_t sve_vqm1_for_el(CPUARMState
*env
, int el
)
7150 return sve_vqm1_for_el_sm(env
, el
, FIELD_EX64(env
->svcr
, SVCR
, SM
));
7153 static void zcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7156 int cur_el
= arm_current_el(env
);
7157 int old_len
= sve_vqm1_for_el(env
, cur_el
);
7160 /* Bits other than [3:0] are RAZ/WI. */
7161 QEMU_BUILD_BUG_ON(ARM_MAX_VQ
> 16);
7162 raw_write(env
, ri
, value
& 0xf);
7165 * Because we arrived here, we know both FP and SVE are enabled;
7166 * otherwise we would have trapped access to the ZCR_ELn register.
7168 new_len
= sve_vqm1_for_el(env
, cur_el
);
7169 if (new_len
< old_len
) {
7170 aarch64_sve_narrow_vq(env
, new_len
+ 1);
7174 static const ARMCPRegInfo zcr_reginfo
[] = {
7175 { .name
= "ZCR_EL1", .state
= ARM_CP_STATE_AA64
,
7176 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 2, .opc2
= 0,
7177 .nv2_redirect_offset
= 0x1e0 | NV2_REDIR_NV1
,
7178 .access
= PL1_RW
, .type
= ARM_CP_SVE
,
7179 .fieldoffset
= offsetof(CPUARMState
, vfp
.zcr_el
[1]),
7180 .writefn
= zcr_write
, .raw_writefn
= raw_write
},
7181 { .name
= "ZCR_EL2", .state
= ARM_CP_STATE_AA64
,
7182 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 2, .opc2
= 0,
7183 .access
= PL2_RW
, .type
= ARM_CP_SVE
,
7184 .fieldoffset
= offsetof(CPUARMState
, vfp
.zcr_el
[2]),
7185 .writefn
= zcr_write
, .raw_writefn
= raw_write
},
7186 { .name
= "ZCR_EL3", .state
= ARM_CP_STATE_AA64
,
7187 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 2, .opc2
= 0,
7188 .access
= PL3_RW
, .type
= ARM_CP_SVE
,
7189 .fieldoffset
= offsetof(CPUARMState
, vfp
.zcr_el
[3]),
7190 .writefn
= zcr_write
, .raw_writefn
= raw_write
},
7193 #ifdef TARGET_AARCH64
7194 static CPAccessResult
access_tpidr2(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7197 int el
= arm_current_el(env
);
7200 uint64_t sctlr
= arm_sctlr(env
, el
);
7201 if (!(sctlr
& SCTLR_EnTP2
)) {
7202 return CP_ACCESS_TRAP
;
7205 /* TODO: FEAT_FGT */
7207 && arm_feature(env
, ARM_FEATURE_EL3
)
7208 && !(env
->cp15
.scr_el3
& SCR_ENTP2
)) {
7209 return CP_ACCESS_TRAP_EL3
;
7211 return CP_ACCESS_OK
;
7214 static CPAccessResult
access_smprimap(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7217 /* If EL1 this is a FEAT_NV access and CPTR_EL3.ESM doesn't apply */
7218 if (arm_current_el(env
) == 2
7219 && arm_feature(env
, ARM_FEATURE_EL3
)
7220 && !FIELD_EX64(env
->cp15
.cptr_el
[3], CPTR_EL3
, ESM
)) {
7221 return CP_ACCESS_TRAP_EL3
;
7223 return CP_ACCESS_OK
;
7226 static CPAccessResult
access_smpri(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7229 if (arm_current_el(env
) < 3
7230 && arm_feature(env
, ARM_FEATURE_EL3
)
7231 && !FIELD_EX64(env
->cp15
.cptr_el
[3], CPTR_EL3
, ESM
)) {
7232 return CP_ACCESS_TRAP_EL3
;
7234 return CP_ACCESS_OK
;
7238 static void arm_reset_sve_state(CPUARMState
*env
)
7240 memset(env
->vfp
.zregs
, 0, sizeof(env
->vfp
.zregs
));
7241 /* Recall that FFR is stored as pregs[16]. */
7242 memset(env
->vfp
.pregs
, 0, sizeof(env
->vfp
.pregs
));
7243 vfp_set_fpcr(env
, 0x0800009f);
7246 void aarch64_set_svcr(CPUARMState
*env
, uint64_t new, uint64_t mask
)
7248 uint64_t change
= (env
->svcr
^ new) & mask
;
7253 env
->svcr
^= change
;
7255 if (change
& R_SVCR_SM_MASK
) {
7256 arm_reset_sve_state(env
);
7262 * SetPSTATE_ZA zeros on enable and disable. We can zero this only
7263 * on enable: while disabled, the storage is inaccessible and the
7264 * value does not matter. We're not saving the storage in vmstate
7265 * when disabled either.
7267 if (change
& new & R_SVCR_ZA_MASK
) {
7268 memset(env
->zarray
, 0, sizeof(env
->zarray
));
7271 if (tcg_enabled()) {
7272 arm_rebuild_hflags(env
);
7276 static void svcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7279 aarch64_set_svcr(env
, value
, -1);
7282 static void smcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7285 int cur_el
= arm_current_el(env
);
7286 int old_len
= sve_vqm1_for_el(env
, cur_el
);
7289 QEMU_BUILD_BUG_ON(ARM_MAX_VQ
> R_SMCR_LEN_MASK
+ 1);
7290 value
&= R_SMCR_LEN_MASK
| R_SMCR_FA64_MASK
;
7291 raw_write(env
, ri
, value
);
7294 * Note that it is CONSTRAINED UNPREDICTABLE what happens to ZA storage
7295 * when SVL is widened (old values kept, or zeros). Choose to keep the
7296 * current values for simplicity. But for QEMU internals, we must still
7297 * apply the narrower SVL to the Zregs and Pregs -- see the comment
7298 * above aarch64_sve_narrow_vq.
7300 new_len
= sve_vqm1_for_el(env
, cur_el
);
7301 if (new_len
< old_len
) {
7302 aarch64_sve_narrow_vq(env
, new_len
+ 1);
7306 static const ARMCPRegInfo sme_reginfo
[] = {
7307 { .name
= "TPIDR2_EL0", .state
= ARM_CP_STATE_AA64
,
7308 .opc0
= 3, .opc1
= 3, .crn
= 13, .crm
= 0, .opc2
= 5,
7309 .access
= PL0_RW
, .accessfn
= access_tpidr2
,
7310 .fgt
= FGT_NTPIDR2_EL0
,
7311 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr2_el0
) },
7312 { .name
= "SVCR", .state
= ARM_CP_STATE_AA64
,
7313 .opc0
= 3, .opc1
= 3, .crn
= 4, .crm
= 2, .opc2
= 2,
7314 .access
= PL0_RW
, .type
= ARM_CP_SME
,
7315 .fieldoffset
= offsetof(CPUARMState
, svcr
),
7316 .writefn
= svcr_write
, .raw_writefn
= raw_write
},
7317 { .name
= "SMCR_EL1", .state
= ARM_CP_STATE_AA64
,
7318 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 2, .opc2
= 6,
7319 .nv2_redirect_offset
= 0x1f0 | NV2_REDIR_NV1
,
7320 .access
= PL1_RW
, .type
= ARM_CP_SME
,
7321 .fieldoffset
= offsetof(CPUARMState
, vfp
.smcr_el
[1]),
7322 .writefn
= smcr_write
, .raw_writefn
= raw_write
},
7323 { .name
= "SMCR_EL2", .state
= ARM_CP_STATE_AA64
,
7324 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 2, .opc2
= 6,
7325 .access
= PL2_RW
, .type
= ARM_CP_SME
,
7326 .fieldoffset
= offsetof(CPUARMState
, vfp
.smcr_el
[2]),
7327 .writefn
= smcr_write
, .raw_writefn
= raw_write
},
7328 { .name
= "SMCR_EL3", .state
= ARM_CP_STATE_AA64
,
7329 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 2, .opc2
= 6,
7330 .access
= PL3_RW
, .type
= ARM_CP_SME
,
7331 .fieldoffset
= offsetof(CPUARMState
, vfp
.smcr_el
[3]),
7332 .writefn
= smcr_write
, .raw_writefn
= raw_write
},
7333 { .name
= "SMIDR_EL1", .state
= ARM_CP_STATE_AA64
,
7334 .opc0
= 3, .opc1
= 1, .crn
= 0, .crm
= 0, .opc2
= 6,
7335 .access
= PL1_R
, .accessfn
= access_aa64_tid1
,
7337 * IMPLEMENTOR = 0 (software)
7338 * REVISION = 0 (implementation defined)
7339 * SMPS = 0 (no streaming execution priority in QEMU)
7340 * AFFINITY = 0 (streaming sve mode not shared with other PEs)
7342 .type
= ARM_CP_CONST
, .resetvalue
= 0, },
7344 * Because SMIDR_EL1.SMPS is 0, SMPRI_EL1 and SMPRIMAP_EL2 are RES 0.
7346 { .name
= "SMPRI_EL1", .state
= ARM_CP_STATE_AA64
,
7347 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 2, .opc2
= 4,
7348 .access
= PL1_RW
, .accessfn
= access_smpri
,
7349 .fgt
= FGT_NSMPRI_EL1
,
7350 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7351 { .name
= "SMPRIMAP_EL2", .state
= ARM_CP_STATE_AA64
,
7352 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 2, .opc2
= 5,
7353 .nv2_redirect_offset
= 0x1f8,
7354 .access
= PL2_RW
, .accessfn
= access_smprimap
,
7355 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7358 static void tlbi_aa64_paall_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7361 CPUState
*cs
= env_cpu(env
);
7366 static void gpccr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7369 /* L0GPTSZ is RO; other bits not mentioned are RES0. */
7370 uint64_t rw_mask
= R_GPCCR_PPS_MASK
| R_GPCCR_IRGN_MASK
|
7371 R_GPCCR_ORGN_MASK
| R_GPCCR_SH_MASK
| R_GPCCR_PGS_MASK
|
7372 R_GPCCR_GPC_MASK
| R_GPCCR_GPCP_MASK
;
7374 env
->cp15
.gpccr_el3
= (value
& rw_mask
) | (env
->cp15
.gpccr_el3
& ~rw_mask
);
7377 static void gpccr_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
7379 env
->cp15
.gpccr_el3
= FIELD_DP64(0, GPCCR
, L0GPTSZ
,
7380 env_archcpu(env
)->reset_l0gptsz
);
7383 static void tlbi_aa64_paallos_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7386 CPUState
*cs
= env_cpu(env
);
7388 tlb_flush_all_cpus_synced(cs
);
7391 static const ARMCPRegInfo rme_reginfo
[] = {
7392 { .name
= "GPCCR_EL3", .state
= ARM_CP_STATE_AA64
,
7393 .opc0
= 3, .opc1
= 6, .crn
= 2, .crm
= 1, .opc2
= 6,
7394 .access
= PL3_RW
, .writefn
= gpccr_write
, .resetfn
= gpccr_reset
,
7395 .fieldoffset
= offsetof(CPUARMState
, cp15
.gpccr_el3
) },
7396 { .name
= "GPTBR_EL3", .state
= ARM_CP_STATE_AA64
,
7397 .opc0
= 3, .opc1
= 6, .crn
= 2, .crm
= 1, .opc2
= 4,
7398 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.gptbr_el3
) },
7399 { .name
= "MFAR_EL3", .state
= ARM_CP_STATE_AA64
,
7400 .opc0
= 3, .opc1
= 6, .crn
= 6, .crm
= 0, .opc2
= 5,
7401 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mfar_el3
) },
7402 { .name
= "TLBI_PAALL", .state
= ARM_CP_STATE_AA64
,
7403 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 4,
7404 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7405 .writefn
= tlbi_aa64_paall_write
},
7406 { .name
= "TLBI_PAALLOS", .state
= ARM_CP_STATE_AA64
,
7407 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 1, .opc2
= 4,
7408 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7409 .writefn
= tlbi_aa64_paallos_write
},
7411 * QEMU does not have a way to invalidate by physical address, thus
7412 * invalidating a range of physical addresses is accomplished by
7413 * flushing all tlb entries in the outer shareable domain,
7414 * just like PAALLOS.
7416 { .name
= "TLBI_RPALOS", .state
= ARM_CP_STATE_AA64
,
7417 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 4, .opc2
= 7,
7418 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7419 .writefn
= tlbi_aa64_paallos_write
},
7420 { .name
= "TLBI_RPAOS", .state
= ARM_CP_STATE_AA64
,
7421 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 4, .opc2
= 3,
7422 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7423 .writefn
= tlbi_aa64_paallos_write
},
7424 { .name
= "DC_CIPAPA", .state
= ARM_CP_STATE_AA64
,
7425 .opc0
= 1, .opc1
= 6, .crn
= 7, .crm
= 14, .opc2
= 1,
7426 .access
= PL3_W
, .type
= ARM_CP_NOP
},
7429 static const ARMCPRegInfo rme_mte_reginfo
[] = {
7430 { .name
= "DC_CIGDPAPA", .state
= ARM_CP_STATE_AA64
,
7431 .opc0
= 1, .opc1
= 6, .crn
= 7, .crm
= 14, .opc2
= 5,
7432 .access
= PL3_W
, .type
= ARM_CP_NOP
},
7434 #endif /* TARGET_AARCH64 */
7436 static void define_pmu_regs(ARMCPU
*cpu
)
7439 * v7 performance monitor control register: same implementor
7440 * field as main ID register, and we implement four counters in
7441 * addition to the cycle count register.
7443 unsigned int i
, pmcrn
= pmu_num_counters(&cpu
->env
);
7444 ARMCPRegInfo pmcr
= {
7445 .name
= "PMCR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 0,
7447 .fgt
= FGT_PMCR_EL0
,
7448 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
7449 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcr
),
7450 .accessfn
= pmreg_access
,
7451 .readfn
= pmcr_read
, .raw_readfn
= raw_read
,
7452 .writefn
= pmcr_write
, .raw_writefn
= raw_write
,
7454 ARMCPRegInfo pmcr64
= {
7455 .name
= "PMCR_EL0", .state
= ARM_CP_STATE_AA64
,
7456 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 0,
7457 .access
= PL0_RW
, .accessfn
= pmreg_access
,
7458 .fgt
= FGT_PMCR_EL0
,
7460 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcr
),
7461 .resetvalue
= cpu
->isar
.reset_pmcr_el0
,
7462 .readfn
= pmcr_read
, .raw_readfn
= raw_read
,
7463 .writefn
= pmcr_write
, .raw_writefn
= raw_write
,
7466 define_one_arm_cp_reg(cpu
, &pmcr
);
7467 define_one_arm_cp_reg(cpu
, &pmcr64
);
7468 for (i
= 0; i
< pmcrn
; i
++) {
7469 char *pmevcntr_name
= g_strdup_printf("PMEVCNTR%d", i
);
7470 char *pmevcntr_el0_name
= g_strdup_printf("PMEVCNTR%d_EL0", i
);
7471 char *pmevtyper_name
= g_strdup_printf("PMEVTYPER%d", i
);
7472 char *pmevtyper_el0_name
= g_strdup_printf("PMEVTYPER%d_EL0", i
);
7473 ARMCPRegInfo pmev_regs
[] = {
7474 { .name
= pmevcntr_name
, .cp
= 15, .crn
= 14,
7475 .crm
= 8 | (3 & (i
>> 3)), .opc1
= 0, .opc2
= i
& 7,
7476 .access
= PL0_RW
, .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
7477 .fgt
= FGT_PMEVCNTRN_EL0
,
7478 .readfn
= pmevcntr_readfn
, .writefn
= pmevcntr_writefn
,
7479 .accessfn
= pmreg_access_xevcntr
},
7480 { .name
= pmevcntr_el0_name
, .state
= ARM_CP_STATE_AA64
,
7481 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 8 | (3 & (i
>> 3)),
7482 .opc2
= i
& 7, .access
= PL0_RW
, .accessfn
= pmreg_access_xevcntr
,
7484 .fgt
= FGT_PMEVCNTRN_EL0
,
7485 .readfn
= pmevcntr_readfn
, .writefn
= pmevcntr_writefn
,
7486 .raw_readfn
= pmevcntr_rawread
,
7487 .raw_writefn
= pmevcntr_rawwrite
},
7488 { .name
= pmevtyper_name
, .cp
= 15, .crn
= 14,
7489 .crm
= 12 | (3 & (i
>> 3)), .opc1
= 0, .opc2
= i
& 7,
7490 .access
= PL0_RW
, .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
7491 .fgt
= FGT_PMEVTYPERN_EL0
,
7492 .readfn
= pmevtyper_readfn
, .writefn
= pmevtyper_writefn
,
7493 .accessfn
= pmreg_access
},
7494 { .name
= pmevtyper_el0_name
, .state
= ARM_CP_STATE_AA64
,
7495 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 12 | (3 & (i
>> 3)),
7496 .opc2
= i
& 7, .access
= PL0_RW
, .accessfn
= pmreg_access
,
7497 .fgt
= FGT_PMEVTYPERN_EL0
,
7499 .readfn
= pmevtyper_readfn
, .writefn
= pmevtyper_writefn
,
7500 .raw_writefn
= pmevtyper_rawwrite
},
7502 define_arm_cp_regs(cpu
, pmev_regs
);
7503 g_free(pmevcntr_name
);
7504 g_free(pmevcntr_el0_name
);
7505 g_free(pmevtyper_name
);
7506 g_free(pmevtyper_el0_name
);
7508 if (cpu_isar_feature(aa32_pmuv3p1
, cpu
)) {
7509 ARMCPRegInfo v81_pmu_regs
[] = {
7510 { .name
= "PMCEID2", .state
= ARM_CP_STATE_AA32
,
7511 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 4,
7512 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
7513 .fgt
= FGT_PMCEIDN_EL0
,
7514 .resetvalue
= extract64(cpu
->pmceid0
, 32, 32) },
7515 { .name
= "PMCEID3", .state
= ARM_CP_STATE_AA32
,
7516 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 5,
7517 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
7518 .fgt
= FGT_PMCEIDN_EL0
,
7519 .resetvalue
= extract64(cpu
->pmceid1
, 32, 32) },
7521 define_arm_cp_regs(cpu
, v81_pmu_regs
);
7523 if (cpu_isar_feature(any_pmuv3p4
, cpu
)) {
7524 static const ARMCPRegInfo v84_pmmir
= {
7525 .name
= "PMMIR_EL1", .state
= ARM_CP_STATE_BOTH
,
7526 .opc0
= 3, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 6,
7527 .access
= PL1_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
7528 .fgt
= FGT_PMMIR_EL1
,
7531 define_one_arm_cp_reg(cpu
, &v84_pmmir
);
7535 #ifndef CONFIG_USER_ONLY
7537 * We don't know until after realize whether there's a GICv3
7538 * attached, and that is what registers the gicv3 sysregs.
7539 * So we have to fill in the GIC fields in ID_PFR/ID_PFR1_EL1/ID_AA64PFR0_EL1
7542 static uint64_t id_pfr1_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
7544 ARMCPU
*cpu
= env_archcpu(env
);
7545 uint64_t pfr1
= cpu
->isar
.id_pfr1
;
7547 if (env
->gicv3state
) {
7553 static uint64_t id_aa64pfr0_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
7555 ARMCPU
*cpu
= env_archcpu(env
);
7556 uint64_t pfr0
= cpu
->isar
.id_aa64pfr0
;
7558 if (env
->gicv3state
) {
7566 * Shared logic between LORID and the rest of the LOR* registers.
7567 * Secure state exclusion has already been dealt with.
7569 static CPAccessResult
access_lor_ns(CPUARMState
*env
,
7570 const ARMCPRegInfo
*ri
, bool isread
)
7572 int el
= arm_current_el(env
);
7574 if (el
< 2 && (arm_hcr_el2_eff(env
) & HCR_TLOR
)) {
7575 return CP_ACCESS_TRAP_EL2
;
7577 if (el
< 3 && (env
->cp15
.scr_el3
& SCR_TLOR
)) {
7578 return CP_ACCESS_TRAP_EL3
;
7580 return CP_ACCESS_OK
;
7583 static CPAccessResult
access_lor_other(CPUARMState
*env
,
7584 const ARMCPRegInfo
*ri
, bool isread
)
7586 if (arm_is_secure_below_el3(env
)) {
7587 /* Access denied in secure mode. */
7588 return CP_ACCESS_TRAP
;
7590 return access_lor_ns(env
, ri
, isread
);
7594 * A trivial implementation of ARMv8.1-LOR leaves all of these
7595 * registers fixed at 0, which indicates that there are zero
7596 * supported Limited Ordering regions.
7598 static const ARMCPRegInfo lor_reginfo
[] = {
7599 { .name
= "LORSA_EL1", .state
= ARM_CP_STATE_AA64
,
7600 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 0,
7601 .access
= PL1_RW
, .accessfn
= access_lor_other
,
7602 .fgt
= FGT_LORSA_EL1
,
7603 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7604 { .name
= "LOREA_EL1", .state
= ARM_CP_STATE_AA64
,
7605 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 1,
7606 .access
= PL1_RW
, .accessfn
= access_lor_other
,
7607 .fgt
= FGT_LOREA_EL1
,
7608 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7609 { .name
= "LORN_EL1", .state
= ARM_CP_STATE_AA64
,
7610 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 2,
7611 .access
= PL1_RW
, .accessfn
= access_lor_other
,
7612 .fgt
= FGT_LORN_EL1
,
7613 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7614 { .name
= "LORC_EL1", .state
= ARM_CP_STATE_AA64
,
7615 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 3,
7616 .access
= PL1_RW
, .accessfn
= access_lor_other
,
7617 .fgt
= FGT_LORC_EL1
,
7618 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7619 { .name
= "LORID_EL1", .state
= ARM_CP_STATE_AA64
,
7620 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 7,
7621 .access
= PL1_R
, .accessfn
= access_lor_ns
,
7622 .fgt
= FGT_LORID_EL1
,
7623 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7626 #ifdef TARGET_AARCH64
7627 static CPAccessResult
access_pauth(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7630 int el
= arm_current_el(env
);
7633 arm_is_el2_enabled(env
) &&
7634 !(arm_hcr_el2_eff(env
) & HCR_APK
)) {
7635 return CP_ACCESS_TRAP_EL2
;
7638 arm_feature(env
, ARM_FEATURE_EL3
) &&
7639 !(env
->cp15
.scr_el3
& SCR_APK
)) {
7640 return CP_ACCESS_TRAP_EL3
;
7642 return CP_ACCESS_OK
;
7645 static const ARMCPRegInfo pauth_reginfo
[] = {
7646 { .name
= "APDAKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
7647 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 2, .opc2
= 0,
7648 .access
= PL1_RW
, .accessfn
= access_pauth
,
7650 .fieldoffset
= offsetof(CPUARMState
, keys
.apda
.lo
) },
7651 { .name
= "APDAKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
7652 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 2, .opc2
= 1,
7653 .access
= PL1_RW
, .accessfn
= access_pauth
,
7655 .fieldoffset
= offsetof(CPUARMState
, keys
.apda
.hi
) },
7656 { .name
= "APDBKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
7657 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 2, .opc2
= 2,
7658 .access
= PL1_RW
, .accessfn
= access_pauth
,
7660 .fieldoffset
= offsetof(CPUARMState
, keys
.apdb
.lo
) },
7661 { .name
= "APDBKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
7662 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 2, .opc2
= 3,
7663 .access
= PL1_RW
, .accessfn
= access_pauth
,
7665 .fieldoffset
= offsetof(CPUARMState
, keys
.apdb
.hi
) },
7666 { .name
= "APGAKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
7667 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 3, .opc2
= 0,
7668 .access
= PL1_RW
, .accessfn
= access_pauth
,
7670 .fieldoffset
= offsetof(CPUARMState
, keys
.apga
.lo
) },
7671 { .name
= "APGAKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
7672 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 3, .opc2
= 1,
7673 .access
= PL1_RW
, .accessfn
= access_pauth
,
7675 .fieldoffset
= offsetof(CPUARMState
, keys
.apga
.hi
) },
7676 { .name
= "APIAKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
7677 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 1, .opc2
= 0,
7678 .access
= PL1_RW
, .accessfn
= access_pauth
,
7680 .fieldoffset
= offsetof(CPUARMState
, keys
.apia
.lo
) },
7681 { .name
= "APIAKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
7682 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 1, .opc2
= 1,
7683 .access
= PL1_RW
, .accessfn
= access_pauth
,
7685 .fieldoffset
= offsetof(CPUARMState
, keys
.apia
.hi
) },
7686 { .name
= "APIBKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
7687 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 1, .opc2
= 2,
7688 .access
= PL1_RW
, .accessfn
= access_pauth
,
7690 .fieldoffset
= offsetof(CPUARMState
, keys
.apib
.lo
) },
7691 { .name
= "APIBKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
7692 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 1, .opc2
= 3,
7693 .access
= PL1_RW
, .accessfn
= access_pauth
,
7695 .fieldoffset
= offsetof(CPUARMState
, keys
.apib
.hi
) },
7698 static const ARMCPRegInfo tlbirange_reginfo
[] = {
7699 { .name
= "TLBI_RVAE1IS", .state
= ARM_CP_STATE_AA64
,
7700 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 2, .opc2
= 1,
7701 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
7702 .fgt
= FGT_TLBIRVAE1IS
,
7703 .writefn
= tlbi_aa64_rvae1is_write
},
7704 { .name
= "TLBI_RVAAE1IS", .state
= ARM_CP_STATE_AA64
,
7705 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 2, .opc2
= 3,
7706 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
7707 .fgt
= FGT_TLBIRVAAE1IS
,
7708 .writefn
= tlbi_aa64_rvae1is_write
},
7709 { .name
= "TLBI_RVALE1IS", .state
= ARM_CP_STATE_AA64
,
7710 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 2, .opc2
= 5,
7711 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
7712 .fgt
= FGT_TLBIRVALE1IS
,
7713 .writefn
= tlbi_aa64_rvae1is_write
},
7714 { .name
= "TLBI_RVAALE1IS", .state
= ARM_CP_STATE_AA64
,
7715 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 2, .opc2
= 7,
7716 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
7717 .fgt
= FGT_TLBIRVAALE1IS
,
7718 .writefn
= tlbi_aa64_rvae1is_write
},
7719 { .name
= "TLBI_RVAE1OS", .state
= ARM_CP_STATE_AA64
,
7720 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 1,
7721 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7722 .fgt
= FGT_TLBIRVAE1OS
,
7723 .writefn
= tlbi_aa64_rvae1is_write
},
7724 { .name
= "TLBI_RVAAE1OS", .state
= ARM_CP_STATE_AA64
,
7725 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 3,
7726 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7727 .fgt
= FGT_TLBIRVAAE1OS
,
7728 .writefn
= tlbi_aa64_rvae1is_write
},
7729 { .name
= "TLBI_RVALE1OS", .state
= ARM_CP_STATE_AA64
,
7730 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 5,
7731 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7732 .fgt
= FGT_TLBIRVALE1OS
,
7733 .writefn
= tlbi_aa64_rvae1is_write
},
7734 { .name
= "TLBI_RVAALE1OS", .state
= ARM_CP_STATE_AA64
,
7735 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 7,
7736 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7737 .fgt
= FGT_TLBIRVAALE1OS
,
7738 .writefn
= tlbi_aa64_rvae1is_write
},
7739 { .name
= "TLBI_RVAE1", .state
= ARM_CP_STATE_AA64
,
7740 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 1,
7741 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
7742 .fgt
= FGT_TLBIRVAE1
,
7743 .writefn
= tlbi_aa64_rvae1_write
},
7744 { .name
= "TLBI_RVAAE1", .state
= ARM_CP_STATE_AA64
,
7745 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 3,
7746 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
7747 .fgt
= FGT_TLBIRVAAE1
,
7748 .writefn
= tlbi_aa64_rvae1_write
},
7749 { .name
= "TLBI_RVALE1", .state
= ARM_CP_STATE_AA64
,
7750 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 5,
7751 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
7752 .fgt
= FGT_TLBIRVALE1
,
7753 .writefn
= tlbi_aa64_rvae1_write
},
7754 { .name
= "TLBI_RVAALE1", .state
= ARM_CP_STATE_AA64
,
7755 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 7,
7756 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
7757 .fgt
= FGT_TLBIRVAALE1
,
7758 .writefn
= tlbi_aa64_rvae1_write
},
7759 { .name
= "TLBI_RIPAS2E1IS", .state
= ARM_CP_STATE_AA64
,
7760 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 2,
7761 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
7762 .writefn
= tlbi_aa64_ripas2e1is_write
},
7763 { .name
= "TLBI_RIPAS2LE1IS", .state
= ARM_CP_STATE_AA64
,
7764 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 6,
7765 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
7766 .writefn
= tlbi_aa64_ripas2e1is_write
},
7767 { .name
= "TLBI_RVAE2IS", .state
= ARM_CP_STATE_AA64
,
7768 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 2, .opc2
= 1,
7769 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7770 .writefn
= tlbi_aa64_rvae2is_write
},
7771 { .name
= "TLBI_RVALE2IS", .state
= ARM_CP_STATE_AA64
,
7772 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 2, .opc2
= 5,
7773 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7774 .writefn
= tlbi_aa64_rvae2is_write
},
7775 { .name
= "TLBI_RIPAS2E1", .state
= ARM_CP_STATE_AA64
,
7776 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 2,
7777 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
7778 .writefn
= tlbi_aa64_ripas2e1_write
},
7779 { .name
= "TLBI_RIPAS2LE1", .state
= ARM_CP_STATE_AA64
,
7780 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 6,
7781 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
7782 .writefn
= tlbi_aa64_ripas2e1_write
},
7783 { .name
= "TLBI_RVAE2OS", .state
= ARM_CP_STATE_AA64
,
7784 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 5, .opc2
= 1,
7785 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7786 .writefn
= tlbi_aa64_rvae2is_write
},
7787 { .name
= "TLBI_RVALE2OS", .state
= ARM_CP_STATE_AA64
,
7788 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 5, .opc2
= 5,
7789 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7790 .writefn
= tlbi_aa64_rvae2is_write
},
7791 { .name
= "TLBI_RVAE2", .state
= ARM_CP_STATE_AA64
,
7792 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 6, .opc2
= 1,
7793 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7794 .writefn
= tlbi_aa64_rvae2_write
},
7795 { .name
= "TLBI_RVALE2", .state
= ARM_CP_STATE_AA64
,
7796 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 6, .opc2
= 5,
7797 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7798 .writefn
= tlbi_aa64_rvae2_write
},
7799 { .name
= "TLBI_RVAE3IS", .state
= ARM_CP_STATE_AA64
,
7800 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 2, .opc2
= 1,
7801 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7802 .writefn
= tlbi_aa64_rvae3is_write
},
7803 { .name
= "TLBI_RVALE3IS", .state
= ARM_CP_STATE_AA64
,
7804 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 2, .opc2
= 5,
7805 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7806 .writefn
= tlbi_aa64_rvae3is_write
},
7807 { .name
= "TLBI_RVAE3OS", .state
= ARM_CP_STATE_AA64
,
7808 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 5, .opc2
= 1,
7809 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7810 .writefn
= tlbi_aa64_rvae3is_write
},
7811 { .name
= "TLBI_RVALE3OS", .state
= ARM_CP_STATE_AA64
,
7812 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 5, .opc2
= 5,
7813 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7814 .writefn
= tlbi_aa64_rvae3is_write
},
7815 { .name
= "TLBI_RVAE3", .state
= ARM_CP_STATE_AA64
,
7816 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 6, .opc2
= 1,
7817 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7818 .writefn
= tlbi_aa64_rvae3_write
},
7819 { .name
= "TLBI_RVALE3", .state
= ARM_CP_STATE_AA64
,
7820 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 6, .opc2
= 5,
7821 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7822 .writefn
= tlbi_aa64_rvae3_write
},
7825 static const ARMCPRegInfo tlbios_reginfo
[] = {
7826 { .name
= "TLBI_VMALLE1OS", .state
= ARM_CP_STATE_AA64
,
7827 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 1, .opc2
= 0,
7828 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7829 .fgt
= FGT_TLBIVMALLE1OS
,
7830 .writefn
= tlbi_aa64_vmalle1is_write
},
7831 { .name
= "TLBI_VAE1OS", .state
= ARM_CP_STATE_AA64
,
7832 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 1, .opc2
= 1,
7833 .fgt
= FGT_TLBIVAE1OS
,
7834 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7835 .writefn
= tlbi_aa64_vae1is_write
},
7836 { .name
= "TLBI_ASIDE1OS", .state
= ARM_CP_STATE_AA64
,
7837 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 1, .opc2
= 2,
7838 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7839 .fgt
= FGT_TLBIASIDE1OS
,
7840 .writefn
= tlbi_aa64_vmalle1is_write
},
7841 { .name
= "TLBI_VAAE1OS", .state
= ARM_CP_STATE_AA64
,
7842 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 1, .opc2
= 3,
7843 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7844 .fgt
= FGT_TLBIVAAE1OS
,
7845 .writefn
= tlbi_aa64_vae1is_write
},
7846 { .name
= "TLBI_VALE1OS", .state
= ARM_CP_STATE_AA64
,
7847 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 1, .opc2
= 5,
7848 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7849 .fgt
= FGT_TLBIVALE1OS
,
7850 .writefn
= tlbi_aa64_vae1is_write
},
7851 { .name
= "TLBI_VAALE1OS", .state
= ARM_CP_STATE_AA64
,
7852 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 1, .opc2
= 7,
7853 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7854 .fgt
= FGT_TLBIVAALE1OS
,
7855 .writefn
= tlbi_aa64_vae1is_write
},
7856 { .name
= "TLBI_ALLE2OS", .state
= ARM_CP_STATE_AA64
,
7857 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 1, .opc2
= 0,
7858 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7859 .writefn
= tlbi_aa64_alle2is_write
},
7860 { .name
= "TLBI_VAE2OS", .state
= ARM_CP_STATE_AA64
,
7861 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 1, .opc2
= 1,
7862 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7863 .writefn
= tlbi_aa64_vae2is_write
},
7864 { .name
= "TLBI_ALLE1OS", .state
= ARM_CP_STATE_AA64
,
7865 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 1, .opc2
= 4,
7866 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
7867 .writefn
= tlbi_aa64_alle1is_write
},
7868 { .name
= "TLBI_VALE2OS", .state
= ARM_CP_STATE_AA64
,
7869 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 1, .opc2
= 5,
7870 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7871 .writefn
= tlbi_aa64_vae2is_write
},
7872 { .name
= "TLBI_VMALLS12E1OS", .state
= ARM_CP_STATE_AA64
,
7873 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 1, .opc2
= 6,
7874 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
7875 .writefn
= tlbi_aa64_alle1is_write
},
7876 { .name
= "TLBI_IPAS2E1OS", .state
= ARM_CP_STATE_AA64
,
7877 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 0,
7878 .access
= PL2_W
, .type
= ARM_CP_NOP
},
7879 { .name
= "TLBI_RIPAS2E1OS", .state
= ARM_CP_STATE_AA64
,
7880 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 3,
7881 .access
= PL2_W
, .type
= ARM_CP_NOP
},
7882 { .name
= "TLBI_IPAS2LE1OS", .state
= ARM_CP_STATE_AA64
,
7883 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 4,
7884 .access
= PL2_W
, .type
= ARM_CP_NOP
},
7885 { .name
= "TLBI_RIPAS2LE1OS", .state
= ARM_CP_STATE_AA64
,
7886 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 7,
7887 .access
= PL2_W
, .type
= ARM_CP_NOP
},
7888 { .name
= "TLBI_ALLE3OS", .state
= ARM_CP_STATE_AA64
,
7889 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 1, .opc2
= 0,
7890 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7891 .writefn
= tlbi_aa64_alle3is_write
},
7892 { .name
= "TLBI_VAE3OS", .state
= ARM_CP_STATE_AA64
,
7893 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 1, .opc2
= 1,
7894 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7895 .writefn
= tlbi_aa64_vae3is_write
},
7896 { .name
= "TLBI_VALE3OS", .state
= ARM_CP_STATE_AA64
,
7897 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 1, .opc2
= 5,
7898 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7899 .writefn
= tlbi_aa64_vae3is_write
},
7902 static uint64_t rndr_readfn(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
7907 /* Success sets NZCV = 0000. */
7908 env
->NF
= env
->CF
= env
->VF
= 0, env
->ZF
= 1;
7910 if (qemu_guest_getrandom(&ret
, sizeof(ret
), &err
) < 0) {
7912 * ??? Failed, for unknown reasons in the crypto subsystem.
7913 * The best we can do is log the reason and return the
7914 * timed-out indication to the guest. There is no reason
7915 * we know to expect this failure to be transitory, so the
7916 * guest may well hang retrying the operation.
7918 qemu_log_mask(LOG_UNIMP
, "%s: Crypto failure: %s",
7919 ri
->name
, error_get_pretty(err
));
7922 env
->ZF
= 0; /* NZCF = 0100 */
7928 /* We do not support re-seeding, so the two registers operate the same. */
7929 static const ARMCPRegInfo rndr_reginfo
[] = {
7930 { .name
= "RNDR", .state
= ARM_CP_STATE_AA64
,
7931 .type
= ARM_CP_NO_RAW
| ARM_CP_SUPPRESS_TB_END
| ARM_CP_IO
,
7932 .opc0
= 3, .opc1
= 3, .crn
= 2, .crm
= 4, .opc2
= 0,
7933 .access
= PL0_R
, .readfn
= rndr_readfn
},
7934 { .name
= "RNDRRS", .state
= ARM_CP_STATE_AA64
,
7935 .type
= ARM_CP_NO_RAW
| ARM_CP_SUPPRESS_TB_END
| ARM_CP_IO
,
7936 .opc0
= 3, .opc1
= 3, .crn
= 2, .crm
= 4, .opc2
= 1,
7937 .access
= PL0_R
, .readfn
= rndr_readfn
},
7940 static void dccvap_writefn(CPUARMState
*env
, const ARMCPRegInfo
*opaque
,
7944 ARMCPU
*cpu
= env_archcpu(env
);
7945 /* CTR_EL0 System register -> DminLine, bits [19:16] */
7946 uint64_t dline_size
= 4 << ((cpu
->ctr
>> 16) & 0xF);
7947 uint64_t vaddr_in
= (uint64_t) value
;
7948 uint64_t vaddr
= vaddr_in
& ~(dline_size
- 1);
7950 int mem_idx
= arm_env_mmu_index(env
);
7952 /* This won't be crossing page boundaries */
7953 haddr
= probe_read(env
, vaddr
, dline_size
, mem_idx
, GETPC());
7955 #ifndef CONFIG_USER_ONLY
7960 /* RCU lock is already being held */
7961 mr
= memory_region_from_host(haddr
, &offset
);
7964 memory_region_writeback(mr
, offset
, dline_size
);
7966 #endif /*CONFIG_USER_ONLY*/
7969 /* Handled by hardware accelerator. */
7970 g_assert_not_reached();
7971 #endif /* CONFIG_TCG */
7974 static const ARMCPRegInfo dcpop_reg
[] = {
7975 { .name
= "DC_CVAP", .state
= ARM_CP_STATE_AA64
,
7976 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 12, .opc2
= 1,
7977 .access
= PL0_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_SUPPRESS_TB_END
,
7979 .accessfn
= aa64_cacheop_poc_access
, .writefn
= dccvap_writefn
},
7982 static const ARMCPRegInfo dcpodp_reg
[] = {
7983 { .name
= "DC_CVADP", .state
= ARM_CP_STATE_AA64
,
7984 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 13, .opc2
= 1,
7985 .access
= PL0_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_SUPPRESS_TB_END
,
7987 .accessfn
= aa64_cacheop_poc_access
, .writefn
= dccvap_writefn
},
7990 static CPAccessResult
access_aa64_tid5(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7993 if ((arm_current_el(env
) < 2) && (arm_hcr_el2_eff(env
) & HCR_TID5
)) {
7994 return CP_ACCESS_TRAP_EL2
;
7997 return CP_ACCESS_OK
;
8000 static CPAccessResult
access_mte(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
8003 int el
= arm_current_el(env
);
8004 if (el
< 2 && arm_is_el2_enabled(env
)) {
8005 uint64_t hcr
= arm_hcr_el2_eff(env
);
8006 if (!(hcr
& HCR_ATA
) && (!(hcr
& HCR_E2H
) || !(hcr
& HCR_TGE
))) {
8007 return CP_ACCESS_TRAP_EL2
;
8011 arm_feature(env
, ARM_FEATURE_EL3
) &&
8012 !(env
->cp15
.scr_el3
& SCR_ATA
)) {
8013 return CP_ACCESS_TRAP_EL3
;
8015 return CP_ACCESS_OK
;
8018 static CPAccessResult
access_tfsr_el1(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
8021 CPAccessResult nv1
= access_nv1(env
, ri
, isread
);
8023 if (nv1
!= CP_ACCESS_OK
) {
8026 return access_mte(env
, ri
, isread
);
8029 static CPAccessResult
access_tfsr_el2(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
8033 * TFSR_EL2: similar to generic access_mte(), but we need to
8034 * account for FEAT_NV. At EL1 this must be a FEAT_NV access;
8035 * if NV2 is enabled then we will redirect this to TFSR_EL1
8036 * after doing the HCR and SCR ATA traps; otherwise this will
8037 * be a trap to EL2 and the HCR/SCR traps do not apply.
8039 int el
= arm_current_el(env
);
8041 if (el
== 1 && (arm_hcr_el2_eff(env
) & HCR_NV2
)) {
8042 return CP_ACCESS_OK
;
8044 if (el
< 2 && arm_is_el2_enabled(env
)) {
8045 uint64_t hcr
= arm_hcr_el2_eff(env
);
8046 if (!(hcr
& HCR_ATA
) && (!(hcr
& HCR_E2H
) || !(hcr
& HCR_TGE
))) {
8047 return CP_ACCESS_TRAP_EL2
;
8051 arm_feature(env
, ARM_FEATURE_EL3
) &&
8052 !(env
->cp15
.scr_el3
& SCR_ATA
)) {
8053 return CP_ACCESS_TRAP_EL3
;
8055 return CP_ACCESS_OK
;
8058 static uint64_t tco_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
8060 return env
->pstate
& PSTATE_TCO
;
8063 static void tco_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t val
)
8065 env
->pstate
= (env
->pstate
& ~PSTATE_TCO
) | (val
& PSTATE_TCO
);
8068 static const ARMCPRegInfo mte_reginfo
[] = {
8069 { .name
= "TFSRE0_EL1", .state
= ARM_CP_STATE_AA64
,
8070 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 6, .opc2
= 1,
8071 .access
= PL1_RW
, .accessfn
= access_mte
,
8072 .fieldoffset
= offsetof(CPUARMState
, cp15
.tfsr_el
[0]) },
8073 { .name
= "TFSR_EL1", .state
= ARM_CP_STATE_AA64
,
8074 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 6, .opc2
= 0,
8075 .access
= PL1_RW
, .accessfn
= access_tfsr_el1
,
8076 .nv2_redirect_offset
= 0x190 | NV2_REDIR_NV1
,
8077 .fieldoffset
= offsetof(CPUARMState
, cp15
.tfsr_el
[1]) },
8078 { .name
= "TFSR_EL2", .state
= ARM_CP_STATE_AA64
,
8079 .type
= ARM_CP_NV2_REDIRECT
,
8080 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 6, .opc2
= 0,
8081 .access
= PL2_RW
, .accessfn
= access_tfsr_el2
,
8082 .fieldoffset
= offsetof(CPUARMState
, cp15
.tfsr_el
[2]) },
8083 { .name
= "TFSR_EL3", .state
= ARM_CP_STATE_AA64
,
8084 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 6, .opc2
= 0,
8086 .fieldoffset
= offsetof(CPUARMState
, cp15
.tfsr_el
[3]) },
8087 { .name
= "RGSR_EL1", .state
= ARM_CP_STATE_AA64
,
8088 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 5,
8089 .access
= PL1_RW
, .accessfn
= access_mte
,
8090 .fieldoffset
= offsetof(CPUARMState
, cp15
.rgsr_el1
) },
8091 { .name
= "GCR_EL1", .state
= ARM_CP_STATE_AA64
,
8092 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 6,
8093 .access
= PL1_RW
, .accessfn
= access_mte
,
8094 .fieldoffset
= offsetof(CPUARMState
, cp15
.gcr_el1
) },
8095 { .name
= "TCO", .state
= ARM_CP_STATE_AA64
,
8096 .opc0
= 3, .opc1
= 3, .crn
= 4, .crm
= 2, .opc2
= 7,
8097 .type
= ARM_CP_NO_RAW
,
8098 .access
= PL0_RW
, .readfn
= tco_read
, .writefn
= tco_write
},
8099 { .name
= "DC_IGVAC", .state
= ARM_CP_STATE_AA64
,
8100 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 3,
8101 .type
= ARM_CP_NOP
, .access
= PL1_W
,
8103 .accessfn
= aa64_cacheop_poc_access
},
8104 { .name
= "DC_IGSW", .state
= ARM_CP_STATE_AA64
,
8105 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 4,
8107 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
8108 { .name
= "DC_IGDVAC", .state
= ARM_CP_STATE_AA64
,
8109 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 5,
8110 .type
= ARM_CP_NOP
, .access
= PL1_W
,
8112 .accessfn
= aa64_cacheop_poc_access
},
8113 { .name
= "DC_IGDSW", .state
= ARM_CP_STATE_AA64
,
8114 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 6,
8116 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
8117 { .name
= "DC_CGSW", .state
= ARM_CP_STATE_AA64
,
8118 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 4,
8120 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
8121 { .name
= "DC_CGDSW", .state
= ARM_CP_STATE_AA64
,
8122 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 6,
8124 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
8125 { .name
= "DC_CIGSW", .state
= ARM_CP_STATE_AA64
,
8126 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 4,
8128 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
8129 { .name
= "DC_CIGDSW", .state
= ARM_CP_STATE_AA64
,
8130 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 6,
8132 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
8135 static const ARMCPRegInfo mte_tco_ro_reginfo
[] = {
8136 { .name
= "TCO", .state
= ARM_CP_STATE_AA64
,
8137 .opc0
= 3, .opc1
= 3, .crn
= 4, .crm
= 2, .opc2
= 7,
8138 .type
= ARM_CP_CONST
, .access
= PL0_RW
, },
8141 static const ARMCPRegInfo mte_el0_cacheop_reginfo
[] = {
8142 { .name
= "DC_CGVAC", .state
= ARM_CP_STATE_AA64
,
8143 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 10, .opc2
= 3,
8144 .type
= ARM_CP_NOP
, .access
= PL0_W
,
8146 .accessfn
= aa64_cacheop_poc_access
},
8147 { .name
= "DC_CGDVAC", .state
= ARM_CP_STATE_AA64
,
8148 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 10, .opc2
= 5,
8149 .type
= ARM_CP_NOP
, .access
= PL0_W
,
8151 .accessfn
= aa64_cacheop_poc_access
},
8152 { .name
= "DC_CGVAP", .state
= ARM_CP_STATE_AA64
,
8153 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 12, .opc2
= 3,
8154 .type
= ARM_CP_NOP
, .access
= PL0_W
,
8156 .accessfn
= aa64_cacheop_poc_access
},
8157 { .name
= "DC_CGDVAP", .state
= ARM_CP_STATE_AA64
,
8158 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 12, .opc2
= 5,
8159 .type
= ARM_CP_NOP
, .access
= PL0_W
,
8161 .accessfn
= aa64_cacheop_poc_access
},
8162 { .name
= "DC_CGVADP", .state
= ARM_CP_STATE_AA64
,
8163 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 13, .opc2
= 3,
8164 .type
= ARM_CP_NOP
, .access
= PL0_W
,
8166 .accessfn
= aa64_cacheop_poc_access
},
8167 { .name
= "DC_CGDVADP", .state
= ARM_CP_STATE_AA64
,
8168 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 13, .opc2
= 5,
8169 .type
= ARM_CP_NOP
, .access
= PL0_W
,
8171 .accessfn
= aa64_cacheop_poc_access
},
8172 { .name
= "DC_CIGVAC", .state
= ARM_CP_STATE_AA64
,
8173 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 14, .opc2
= 3,
8174 .type
= ARM_CP_NOP
, .access
= PL0_W
,
8176 .accessfn
= aa64_cacheop_poc_access
},
8177 { .name
= "DC_CIGDVAC", .state
= ARM_CP_STATE_AA64
,
8178 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 14, .opc2
= 5,
8179 .type
= ARM_CP_NOP
, .access
= PL0_W
,
8181 .accessfn
= aa64_cacheop_poc_access
},
8182 { .name
= "DC_GVA", .state
= ARM_CP_STATE_AA64
,
8183 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 4, .opc2
= 3,
8184 .access
= PL0_W
, .type
= ARM_CP_DC_GVA
,
8185 #ifndef CONFIG_USER_ONLY
8186 /* Avoid overhead of an access check that always passes in user-mode */
8187 .accessfn
= aa64_zva_access
,
8191 { .name
= "DC_GZVA", .state
= ARM_CP_STATE_AA64
,
8192 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 4, .opc2
= 4,
8193 .access
= PL0_W
, .type
= ARM_CP_DC_GZVA
,
8194 #ifndef CONFIG_USER_ONLY
8195 /* Avoid overhead of an access check that always passes in user-mode */
8196 .accessfn
= aa64_zva_access
,
8202 static CPAccessResult
access_scxtnum(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
8205 uint64_t hcr
= arm_hcr_el2_eff(env
);
8206 int el
= arm_current_el(env
);
8208 if (el
== 0 && !((hcr
& HCR_E2H
) && (hcr
& HCR_TGE
))) {
8209 if (env
->cp15
.sctlr_el
[1] & SCTLR_TSCXT
) {
8210 if (hcr
& HCR_TGE
) {
8211 return CP_ACCESS_TRAP_EL2
;
8213 return CP_ACCESS_TRAP
;
8215 } else if (el
< 2 && (env
->cp15
.sctlr_el
[2] & SCTLR_TSCXT
)) {
8216 return CP_ACCESS_TRAP_EL2
;
8218 if (el
< 2 && arm_is_el2_enabled(env
) && !(hcr
& HCR_ENSCXT
)) {
8219 return CP_ACCESS_TRAP_EL2
;
8222 && arm_feature(env
, ARM_FEATURE_EL3
)
8223 && !(env
->cp15
.scr_el3
& SCR_ENSCXT
)) {
8224 return CP_ACCESS_TRAP_EL3
;
8226 return CP_ACCESS_OK
;
8229 static CPAccessResult
access_scxtnum_el1(CPUARMState
*env
,
8230 const ARMCPRegInfo
*ri
,
8233 CPAccessResult nv1
= access_nv1(env
, ri
, isread
);
8235 if (nv1
!= CP_ACCESS_OK
) {
8238 return access_scxtnum(env
, ri
, isread
);
8241 static const ARMCPRegInfo scxtnum_reginfo
[] = {
8242 { .name
= "SCXTNUM_EL0", .state
= ARM_CP_STATE_AA64
,
8243 .opc0
= 3, .opc1
= 3, .crn
= 13, .crm
= 0, .opc2
= 7,
8244 .access
= PL0_RW
, .accessfn
= access_scxtnum
,
8245 .fgt
= FGT_SCXTNUM_EL0
,
8246 .fieldoffset
= offsetof(CPUARMState
, scxtnum_el
[0]) },
8247 { .name
= "SCXTNUM_EL1", .state
= ARM_CP_STATE_AA64
,
8248 .opc0
= 3, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 7,
8249 .access
= PL1_RW
, .accessfn
= access_scxtnum_el1
,
8250 .fgt
= FGT_SCXTNUM_EL1
,
8251 .nv2_redirect_offset
= 0x188 | NV2_REDIR_NV1
,
8252 .fieldoffset
= offsetof(CPUARMState
, scxtnum_el
[1]) },
8253 { .name
= "SCXTNUM_EL2", .state
= ARM_CP_STATE_AA64
,
8254 .opc0
= 3, .opc1
= 4, .crn
= 13, .crm
= 0, .opc2
= 7,
8255 .access
= PL2_RW
, .accessfn
= access_scxtnum
,
8256 .fieldoffset
= offsetof(CPUARMState
, scxtnum_el
[2]) },
8257 { .name
= "SCXTNUM_EL3", .state
= ARM_CP_STATE_AA64
,
8258 .opc0
= 3, .opc1
= 6, .crn
= 13, .crm
= 0, .opc2
= 7,
8260 .fieldoffset
= offsetof(CPUARMState
, scxtnum_el
[3]) },
8263 static CPAccessResult
access_fgt(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
8266 if (arm_current_el(env
) == 2 &&
8267 arm_feature(env
, ARM_FEATURE_EL3
) && !(env
->cp15
.scr_el3
& SCR_FGTEN
)) {
8268 return CP_ACCESS_TRAP_EL3
;
8270 return CP_ACCESS_OK
;
8273 static const ARMCPRegInfo fgt_reginfo
[] = {
8274 { .name
= "HFGRTR_EL2", .state
= ARM_CP_STATE_AA64
,
8275 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 4,
8276 .nv2_redirect_offset
= 0x1b8,
8277 .access
= PL2_RW
, .accessfn
= access_fgt
,
8278 .fieldoffset
= offsetof(CPUARMState
, cp15
.fgt_read
[FGTREG_HFGRTR
]) },
8279 { .name
= "HFGWTR_EL2", .state
= ARM_CP_STATE_AA64
,
8280 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 5,
8281 .nv2_redirect_offset
= 0x1c0,
8282 .access
= PL2_RW
, .accessfn
= access_fgt
,
8283 .fieldoffset
= offsetof(CPUARMState
, cp15
.fgt_write
[FGTREG_HFGWTR
]) },
8284 { .name
= "HDFGRTR_EL2", .state
= ARM_CP_STATE_AA64
,
8285 .opc0
= 3, .opc1
= 4, .crn
= 3, .crm
= 1, .opc2
= 4,
8286 .nv2_redirect_offset
= 0x1d0,
8287 .access
= PL2_RW
, .accessfn
= access_fgt
,
8288 .fieldoffset
= offsetof(CPUARMState
, cp15
.fgt_read
[FGTREG_HDFGRTR
]) },
8289 { .name
= "HDFGWTR_EL2", .state
= ARM_CP_STATE_AA64
,
8290 .opc0
= 3, .opc1
= 4, .crn
= 3, .crm
= 1, .opc2
= 5,
8291 .nv2_redirect_offset
= 0x1d8,
8292 .access
= PL2_RW
, .accessfn
= access_fgt
,
8293 .fieldoffset
= offsetof(CPUARMState
, cp15
.fgt_write
[FGTREG_HDFGWTR
]) },
8294 { .name
= "HFGITR_EL2", .state
= ARM_CP_STATE_AA64
,
8295 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 6,
8296 .nv2_redirect_offset
= 0x1c8,
8297 .access
= PL2_RW
, .accessfn
= access_fgt
,
8298 .fieldoffset
= offsetof(CPUARMState
, cp15
.fgt_exec
[FGTREG_HFGITR
]) },
8301 static void vncr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
8305 * Clear the RES0 bottom 12 bits; this means at runtime we can guarantee
8306 * that VNCR_EL2 + offset is 64-bit aligned. We don't need to do anything
8307 * about the RESS bits at the top -- we choose the "generate an EL2
8308 * translation abort on use" CONSTRAINED UNPREDICTABLE option (i.e. let
8309 * the ptw.c code detect the resulting invalid address).
8311 env
->cp15
.vncr_el2
= value
& ~0xfffULL
;
8314 static const ARMCPRegInfo nv2_reginfo
[] = {
8315 { .name
= "VNCR_EL2", .state
= ARM_CP_STATE_AA64
,
8316 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 2, .opc2
= 0,
8318 .writefn
= vncr_write
,
8319 .nv2_redirect_offset
= 0xb0,
8320 .fieldoffset
= offsetof(CPUARMState
, cp15
.vncr_el2
) },
8323 #endif /* TARGET_AARCH64 */
8325 static CPAccessResult
access_predinv(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
8328 int el
= arm_current_el(env
);
8331 uint64_t sctlr
= arm_sctlr(env
, el
);
8332 if (!(sctlr
& SCTLR_EnRCTX
)) {
8333 return CP_ACCESS_TRAP
;
8335 } else if (el
== 1) {
8336 uint64_t hcr
= arm_hcr_el2_eff(env
);
8338 return CP_ACCESS_TRAP_EL2
;
8341 return CP_ACCESS_OK
;
8344 static const ARMCPRegInfo predinv_reginfo
[] = {
8345 { .name
= "CFP_RCTX", .state
= ARM_CP_STATE_AA64
,
8346 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 3, .opc2
= 4,
8348 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
8349 { .name
= "DVP_RCTX", .state
= ARM_CP_STATE_AA64
,
8350 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 3, .opc2
= 5,
8352 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
8353 { .name
= "CPP_RCTX", .state
= ARM_CP_STATE_AA64
,
8354 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 3, .opc2
= 7,
8356 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
8358 * Note the AArch32 opcodes have a different OPC1.
8360 { .name
= "CFPRCTX", .state
= ARM_CP_STATE_AA32
,
8361 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 3, .opc2
= 4,
8363 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
8364 { .name
= "DVPRCTX", .state
= ARM_CP_STATE_AA32
,
8365 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 3, .opc2
= 5,
8367 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
8368 { .name
= "CPPRCTX", .state
= ARM_CP_STATE_AA32
,
8369 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 3, .opc2
= 7,
8371 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
8374 static uint64_t ccsidr2_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
8376 /* Read the high 32 bits of the current CCSIDR */
8377 return extract64(ccsidr_read(env
, ri
), 32, 32);
8380 static const ARMCPRegInfo ccsidr2_reginfo
[] = {
8381 { .name
= "CCSIDR2", .state
= ARM_CP_STATE_BOTH
,
8382 .opc0
= 3, .opc1
= 1, .crn
= 0, .crm
= 0, .opc2
= 2,
8384 .accessfn
= access_tid4
,
8385 .readfn
= ccsidr2_read
, .type
= ARM_CP_NO_RAW
},
8388 static CPAccessResult
access_aa64_tid3(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
8391 if ((arm_current_el(env
) < 2) && (arm_hcr_el2_eff(env
) & HCR_TID3
)) {
8392 return CP_ACCESS_TRAP_EL2
;
8395 return CP_ACCESS_OK
;
8398 static CPAccessResult
access_aa32_tid3(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
8401 if (arm_feature(env
, ARM_FEATURE_V8
)) {
8402 return access_aa64_tid3(env
, ri
, isread
);
8405 return CP_ACCESS_OK
;
8408 static CPAccessResult
access_jazelle(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
8411 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TID0
)) {
8412 return CP_ACCESS_TRAP_EL2
;
8415 return CP_ACCESS_OK
;
8418 static CPAccessResult
access_joscr_jmcr(CPUARMState
*env
,
8419 const ARMCPRegInfo
*ri
, bool isread
)
8422 * HSTR.TJDBX traps JOSCR and JMCR accesses, but it exists only
8423 * in v7A, not in v8A.
8425 if (!arm_feature(env
, ARM_FEATURE_V8
) &&
8426 arm_current_el(env
) < 2 && !arm_is_secure_below_el3(env
) &&
8427 (env
->cp15
.hstr_el2
& HSTR_TJDBX
)) {
8428 return CP_ACCESS_TRAP_EL2
;
8430 return CP_ACCESS_OK
;
8433 static const ARMCPRegInfo jazelle_regs
[] = {
8435 .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 7, .opc2
= 0,
8436 .access
= PL1_R
, .accessfn
= access_jazelle
,
8437 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
8439 .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 7, .opc2
= 0,
8440 .accessfn
= access_joscr_jmcr
,
8441 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
8443 .cp
= 14, .crn
= 2, .crm
= 0, .opc1
= 7, .opc2
= 0,
8444 .accessfn
= access_joscr_jmcr
,
8445 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
8448 static const ARMCPRegInfo contextidr_el2
= {
8449 .name
= "CONTEXTIDR_EL2", .state
= ARM_CP_STATE_AA64
,
8450 .opc0
= 3, .opc1
= 4, .crn
= 13, .crm
= 0, .opc2
= 1,
8452 .fieldoffset
= offsetof(CPUARMState
, cp15
.contextidr_el
[2])
8455 static const ARMCPRegInfo vhe_reginfo
[] = {
8456 { .name
= "TTBR1_EL2", .state
= ARM_CP_STATE_AA64
,
8457 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 1,
8458 .access
= PL2_RW
, .writefn
= vmsa_tcr_ttbr_el2_write
,
8459 .raw_writefn
= raw_write
,
8460 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr1_el
[2]) },
8461 #ifndef CONFIG_USER_ONLY
8462 { .name
= "CNTHV_CVAL_EL2", .state
= ARM_CP_STATE_AA64
,
8463 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 3, .opc2
= 2,
8465 offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYPVIRT
].cval
),
8466 .type
= ARM_CP_IO
, .access
= PL2_RW
,
8467 .writefn
= gt_hv_cval_write
, .raw_writefn
= raw_write
},
8468 { .name
= "CNTHV_TVAL_EL2", .state
= ARM_CP_STATE_BOTH
,
8469 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 3, .opc2
= 0,
8470 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL2_RW
,
8471 .resetfn
= gt_hv_timer_reset
,
8472 .readfn
= gt_hv_tval_read
, .writefn
= gt_hv_tval_write
},
8473 { .name
= "CNTHV_CTL_EL2", .state
= ARM_CP_STATE_BOTH
,
8475 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 3, .opc2
= 1,
8477 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYPVIRT
].ctl
),
8478 .writefn
= gt_hv_ctl_write
, .raw_writefn
= raw_write
},
8479 { .name
= "CNTP_CTL_EL02", .state
= ARM_CP_STATE_AA64
,
8480 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 2, .opc2
= 1,
8481 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
8482 .access
= PL2_RW
, .accessfn
= access_el1nvpct
,
8483 .nv2_redirect_offset
= 0x180 | NV2_REDIR_NO_NV1
,
8484 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].ctl
),
8485 .writefn
= gt_phys_ctl_write
, .raw_writefn
= raw_write
},
8486 { .name
= "CNTV_CTL_EL02", .state
= ARM_CP_STATE_AA64
,
8487 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 3, .opc2
= 1,
8488 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
8489 .access
= PL2_RW
, .accessfn
= access_el1nvvct
,
8490 .nv2_redirect_offset
= 0x170 | NV2_REDIR_NO_NV1
,
8491 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].ctl
),
8492 .writefn
= gt_virt_ctl_write
, .raw_writefn
= raw_write
},
8493 { .name
= "CNTP_TVAL_EL02", .state
= ARM_CP_STATE_AA64
,
8494 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 2, .opc2
= 0,
8495 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
| ARM_CP_ALIAS
,
8496 .access
= PL2_RW
, .accessfn
= e2h_access
,
8497 .readfn
= gt_phys_tval_read
, .writefn
= gt_phys_tval_write
},
8498 { .name
= "CNTV_TVAL_EL02", .state
= ARM_CP_STATE_AA64
,
8499 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 3, .opc2
= 0,
8500 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
| ARM_CP_ALIAS
,
8501 .access
= PL2_RW
, .accessfn
= e2h_access
,
8502 .readfn
= gt_virt_tval_read
, .writefn
= gt_virt_tval_write
},
8503 { .name
= "CNTP_CVAL_EL02", .state
= ARM_CP_STATE_AA64
,
8504 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 2, .opc2
= 2,
8505 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
8506 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].cval
),
8507 .nv2_redirect_offset
= 0x178 | NV2_REDIR_NO_NV1
,
8508 .access
= PL2_RW
, .accessfn
= access_el1nvpct
,
8509 .writefn
= gt_phys_cval_write
, .raw_writefn
= raw_write
},
8510 { .name
= "CNTV_CVAL_EL02", .state
= ARM_CP_STATE_AA64
,
8511 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 3, .opc2
= 2,
8512 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
8513 .nv2_redirect_offset
= 0x168 | NV2_REDIR_NO_NV1
,
8514 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].cval
),
8515 .access
= PL2_RW
, .accessfn
= access_el1nvvct
,
8516 .writefn
= gt_virt_cval_write
, .raw_writefn
= raw_write
},
8520 #ifndef CONFIG_USER_ONLY
8521 static const ARMCPRegInfo ats1e1_reginfo
[] = {
8522 { .name
= "AT_S1E1RP", .state
= ARM_CP_STATE_AA64
,
8523 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 9, .opc2
= 0,
8524 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
8525 .fgt
= FGT_ATS1E1RP
,
8526 .accessfn
= at_s1e01_access
, .writefn
= ats_write64
},
8527 { .name
= "AT_S1E1WP", .state
= ARM_CP_STATE_AA64
,
8528 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 9, .opc2
= 1,
8529 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
8530 .fgt
= FGT_ATS1E1WP
,
8531 .accessfn
= at_s1e01_access
, .writefn
= ats_write64
},
8534 static const ARMCPRegInfo ats1cp_reginfo
[] = {
8535 { .name
= "ATS1CPRP",
8536 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 9, .opc2
= 0,
8537 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
8538 .writefn
= ats_write
},
8539 { .name
= "ATS1CPWP",
8540 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 9, .opc2
= 1,
8541 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
8542 .writefn
= ats_write
},
8547 * ACTLR2 and HACTLR2 map to ACTLR_EL1[63:32] and
8548 * ACTLR_EL2[63:32]. They exist only if the ID_MMFR4.AC2 field
8549 * is non-zero, which is never for ARMv7, optionally in ARMv8
8550 * and mandatorily for ARMv8.2 and up.
8551 * ACTLR2 is banked for S and NS if EL3 is AArch32. Since QEMU's
8552 * implementation is RAZ/WI we can ignore this detail, as we
8555 static const ARMCPRegInfo actlr2_hactlr2_reginfo
[] = {
8556 { .name
= "ACTLR2", .state
= ARM_CP_STATE_AA32
,
8557 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 3,
8558 .access
= PL1_RW
, .accessfn
= access_tacr
,
8559 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
8560 { .name
= "HACTLR2", .state
= ARM_CP_STATE_AA32
,
8561 .cp
= 15, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 3,
8562 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
8566 void register_cp_regs_for_features(ARMCPU
*cpu
)
8568 /* Register all the coprocessor registers based on feature bits */
8569 CPUARMState
*env
= &cpu
->env
;
8570 if (arm_feature(env
, ARM_FEATURE_M
)) {
8571 /* M profile has no coprocessor registers */
8575 define_arm_cp_regs(cpu
, cp_reginfo
);
8576 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
8578 * Must go early as it is full of wildcards that may be
8579 * overridden by later definitions.
8581 define_arm_cp_regs(cpu
, not_v8_cp_reginfo
);
8584 if (arm_feature(env
, ARM_FEATURE_V6
)) {
8585 /* The ID registers all have impdef reset values */
8586 ARMCPRegInfo v6_idregs
[] = {
8587 { .name
= "ID_PFR0", .state
= ARM_CP_STATE_BOTH
,
8588 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 0,
8589 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8590 .accessfn
= access_aa32_tid3
,
8591 .resetvalue
= cpu
->isar
.id_pfr0
},
8593 * ID_PFR1 is not a plain ARM_CP_CONST because we don't know
8594 * the value of the GIC field until after we define these regs.
8596 { .name
= "ID_PFR1", .state
= ARM_CP_STATE_BOTH
,
8597 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 1,
8598 .access
= PL1_R
, .type
= ARM_CP_NO_RAW
,
8599 .accessfn
= access_aa32_tid3
,
8600 #ifdef CONFIG_USER_ONLY
8601 .type
= ARM_CP_CONST
,
8602 .resetvalue
= cpu
->isar
.id_pfr1
,
8604 .type
= ARM_CP_NO_RAW
,
8605 .accessfn
= access_aa32_tid3
,
8606 .readfn
= id_pfr1_read
,
8607 .writefn
= arm_cp_write_ignore
8610 { .name
= "ID_DFR0", .state
= ARM_CP_STATE_BOTH
,
8611 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 2,
8612 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8613 .accessfn
= access_aa32_tid3
,
8614 .resetvalue
= cpu
->isar
.id_dfr0
},
8615 { .name
= "ID_AFR0", .state
= ARM_CP_STATE_BOTH
,
8616 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 3,
8617 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8618 .accessfn
= access_aa32_tid3
,
8619 .resetvalue
= cpu
->id_afr0
},
8620 { .name
= "ID_MMFR0", .state
= ARM_CP_STATE_BOTH
,
8621 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 4,
8622 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8623 .accessfn
= access_aa32_tid3
,
8624 .resetvalue
= cpu
->isar
.id_mmfr0
},
8625 { .name
= "ID_MMFR1", .state
= ARM_CP_STATE_BOTH
,
8626 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 5,
8627 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8628 .accessfn
= access_aa32_tid3
,
8629 .resetvalue
= cpu
->isar
.id_mmfr1
},
8630 { .name
= "ID_MMFR2", .state
= ARM_CP_STATE_BOTH
,
8631 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 6,
8632 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8633 .accessfn
= access_aa32_tid3
,
8634 .resetvalue
= cpu
->isar
.id_mmfr2
},
8635 { .name
= "ID_MMFR3", .state
= ARM_CP_STATE_BOTH
,
8636 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 7,
8637 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8638 .accessfn
= access_aa32_tid3
,
8639 .resetvalue
= cpu
->isar
.id_mmfr3
},
8640 { .name
= "ID_ISAR0", .state
= ARM_CP_STATE_BOTH
,
8641 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 0,
8642 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8643 .accessfn
= access_aa32_tid3
,
8644 .resetvalue
= cpu
->isar
.id_isar0
},
8645 { .name
= "ID_ISAR1", .state
= ARM_CP_STATE_BOTH
,
8646 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 1,
8647 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8648 .accessfn
= access_aa32_tid3
,
8649 .resetvalue
= cpu
->isar
.id_isar1
},
8650 { .name
= "ID_ISAR2", .state
= ARM_CP_STATE_BOTH
,
8651 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 2,
8652 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8653 .accessfn
= access_aa32_tid3
,
8654 .resetvalue
= cpu
->isar
.id_isar2
},
8655 { .name
= "ID_ISAR3", .state
= ARM_CP_STATE_BOTH
,
8656 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 3,
8657 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8658 .accessfn
= access_aa32_tid3
,
8659 .resetvalue
= cpu
->isar
.id_isar3
},
8660 { .name
= "ID_ISAR4", .state
= ARM_CP_STATE_BOTH
,
8661 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 4,
8662 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8663 .accessfn
= access_aa32_tid3
,
8664 .resetvalue
= cpu
->isar
.id_isar4
},
8665 { .name
= "ID_ISAR5", .state
= ARM_CP_STATE_BOTH
,
8666 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 5,
8667 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8668 .accessfn
= access_aa32_tid3
,
8669 .resetvalue
= cpu
->isar
.id_isar5
},
8670 { .name
= "ID_MMFR4", .state
= ARM_CP_STATE_BOTH
,
8671 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 6,
8672 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8673 .accessfn
= access_aa32_tid3
,
8674 .resetvalue
= cpu
->isar
.id_mmfr4
},
8675 { .name
= "ID_ISAR6", .state
= ARM_CP_STATE_BOTH
,
8676 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 7,
8677 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8678 .accessfn
= access_aa32_tid3
,
8679 .resetvalue
= cpu
->isar
.id_isar6
},
8681 define_arm_cp_regs(cpu
, v6_idregs
);
8682 define_arm_cp_regs(cpu
, v6_cp_reginfo
);
8684 define_arm_cp_regs(cpu
, not_v6_cp_reginfo
);
8686 if (arm_feature(env
, ARM_FEATURE_V6K
)) {
8687 define_arm_cp_regs(cpu
, v6k_cp_reginfo
);
8689 if (arm_feature(env
, ARM_FEATURE_V7MP
) &&
8690 !arm_feature(env
, ARM_FEATURE_PMSA
)) {
8691 define_arm_cp_regs(cpu
, v7mp_cp_reginfo
);
8693 if (arm_feature(env
, ARM_FEATURE_V7VE
)) {
8694 define_arm_cp_regs(cpu
, pmovsset_cp_reginfo
);
8696 if (arm_feature(env
, ARM_FEATURE_V7
)) {
8697 ARMCPRegInfo clidr
= {
8698 .name
= "CLIDR", .state
= ARM_CP_STATE_BOTH
,
8699 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= 1,
8700 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8701 .accessfn
= access_tid4
,
8702 .fgt
= FGT_CLIDR_EL1
,
8703 .resetvalue
= cpu
->clidr
8705 define_one_arm_cp_reg(cpu
, &clidr
);
8706 define_arm_cp_regs(cpu
, v7_cp_reginfo
);
8707 define_debug_regs(cpu
);
8708 define_pmu_regs(cpu
);
8710 define_arm_cp_regs(cpu
, not_v7_cp_reginfo
);
8712 if (arm_feature(env
, ARM_FEATURE_V8
)) {
8714 * v8 ID registers, which all have impdef reset values.
8715 * Note that within the ID register ranges the unused slots
8716 * must all RAZ, not UNDEF; future architecture versions may
8717 * define new registers here.
8718 * ID registers which are AArch64 views of the AArch32 ID registers
8719 * which already existed in v6 and v7 are handled elsewhere,
8723 ARMCPRegInfo v8_idregs
[] = {
8725 * ID_AA64PFR0_EL1 is not a plain ARM_CP_CONST in system
8726 * emulation because we don't know the right value for the
8727 * GIC field until after we define these regs.
8729 { .name
= "ID_AA64PFR0_EL1", .state
= ARM_CP_STATE_AA64
,
8730 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 0,
8732 #ifdef CONFIG_USER_ONLY
8733 .type
= ARM_CP_CONST
,
8734 .resetvalue
= cpu
->isar
.id_aa64pfr0
8736 .type
= ARM_CP_NO_RAW
,
8737 .accessfn
= access_aa64_tid3
,
8738 .readfn
= id_aa64pfr0_read
,
8739 .writefn
= arm_cp_write_ignore
8742 { .name
= "ID_AA64PFR1_EL1", .state
= ARM_CP_STATE_AA64
,
8743 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 1,
8744 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8745 .accessfn
= access_aa64_tid3
,
8746 .resetvalue
= cpu
->isar
.id_aa64pfr1
},
8747 { .name
= "ID_AA64PFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8748 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 2,
8749 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8750 .accessfn
= access_aa64_tid3
,
8752 { .name
= "ID_AA64PFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8753 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 3,
8754 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8755 .accessfn
= access_aa64_tid3
,
8757 { .name
= "ID_AA64ZFR0_EL1", .state
= ARM_CP_STATE_AA64
,
8758 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 4,
8759 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8760 .accessfn
= access_aa64_tid3
,
8761 .resetvalue
= cpu
->isar
.id_aa64zfr0
},
8762 { .name
= "ID_AA64SMFR0_EL1", .state
= ARM_CP_STATE_AA64
,
8763 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 5,
8764 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8765 .accessfn
= access_aa64_tid3
,
8766 .resetvalue
= cpu
->isar
.id_aa64smfr0
},
8767 { .name
= "ID_AA64PFR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8768 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 6,
8769 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8770 .accessfn
= access_aa64_tid3
,
8772 { .name
= "ID_AA64PFR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8773 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 7,
8774 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8775 .accessfn
= access_aa64_tid3
,
8777 { .name
= "ID_AA64DFR0_EL1", .state
= ARM_CP_STATE_AA64
,
8778 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 0,
8779 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8780 .accessfn
= access_aa64_tid3
,
8781 .resetvalue
= cpu
->isar
.id_aa64dfr0
},
8782 { .name
= "ID_AA64DFR1_EL1", .state
= ARM_CP_STATE_AA64
,
8783 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 1,
8784 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8785 .accessfn
= access_aa64_tid3
,
8786 .resetvalue
= cpu
->isar
.id_aa64dfr1
},
8787 { .name
= "ID_AA64DFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8788 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 2,
8789 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8790 .accessfn
= access_aa64_tid3
,
8792 { .name
= "ID_AA64DFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8793 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 3,
8794 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8795 .accessfn
= access_aa64_tid3
,
8797 { .name
= "ID_AA64AFR0_EL1", .state
= ARM_CP_STATE_AA64
,
8798 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 4,
8799 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8800 .accessfn
= access_aa64_tid3
,
8801 .resetvalue
= cpu
->id_aa64afr0
},
8802 { .name
= "ID_AA64AFR1_EL1", .state
= ARM_CP_STATE_AA64
,
8803 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 5,
8804 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8805 .accessfn
= access_aa64_tid3
,
8806 .resetvalue
= cpu
->id_aa64afr1
},
8807 { .name
= "ID_AA64AFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8808 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 6,
8809 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8810 .accessfn
= access_aa64_tid3
,
8812 { .name
= "ID_AA64AFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8813 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 7,
8814 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8815 .accessfn
= access_aa64_tid3
,
8817 { .name
= "ID_AA64ISAR0_EL1", .state
= ARM_CP_STATE_AA64
,
8818 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 0,
8819 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8820 .accessfn
= access_aa64_tid3
,
8821 .resetvalue
= cpu
->isar
.id_aa64isar0
},
8822 { .name
= "ID_AA64ISAR1_EL1", .state
= ARM_CP_STATE_AA64
,
8823 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 1,
8824 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8825 .accessfn
= access_aa64_tid3
,
8826 .resetvalue
= cpu
->isar
.id_aa64isar1
},
8827 { .name
= "ID_AA64ISAR2_EL1", .state
= ARM_CP_STATE_AA64
,
8828 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 2,
8829 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8830 .accessfn
= access_aa64_tid3
,
8831 .resetvalue
= cpu
->isar
.id_aa64isar2
},
8832 { .name
= "ID_AA64ISAR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8833 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 3,
8834 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8835 .accessfn
= access_aa64_tid3
,
8837 { .name
= "ID_AA64ISAR4_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8838 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 4,
8839 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8840 .accessfn
= access_aa64_tid3
,
8842 { .name
= "ID_AA64ISAR5_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8843 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 5,
8844 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8845 .accessfn
= access_aa64_tid3
,
8847 { .name
= "ID_AA64ISAR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8848 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 6,
8849 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8850 .accessfn
= access_aa64_tid3
,
8852 { .name
= "ID_AA64ISAR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8853 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 7,
8854 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8855 .accessfn
= access_aa64_tid3
,
8857 { .name
= "ID_AA64MMFR0_EL1", .state
= ARM_CP_STATE_AA64
,
8858 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 0,
8859 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8860 .accessfn
= access_aa64_tid3
,
8861 .resetvalue
= cpu
->isar
.id_aa64mmfr0
},
8862 { .name
= "ID_AA64MMFR1_EL1", .state
= ARM_CP_STATE_AA64
,
8863 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 1,
8864 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8865 .accessfn
= access_aa64_tid3
,
8866 .resetvalue
= cpu
->isar
.id_aa64mmfr1
},
8867 { .name
= "ID_AA64MMFR2_EL1", .state
= ARM_CP_STATE_AA64
,
8868 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 2,
8869 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8870 .accessfn
= access_aa64_tid3
,
8871 .resetvalue
= cpu
->isar
.id_aa64mmfr2
},
8872 { .name
= "ID_AA64MMFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8873 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 3,
8874 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8875 .accessfn
= access_aa64_tid3
,
8877 { .name
= "ID_AA64MMFR4_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8878 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 4,
8879 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8880 .accessfn
= access_aa64_tid3
,
8882 { .name
= "ID_AA64MMFR5_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8883 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 5,
8884 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8885 .accessfn
= access_aa64_tid3
,
8887 { .name
= "ID_AA64MMFR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8888 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 6,
8889 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8890 .accessfn
= access_aa64_tid3
,
8892 { .name
= "ID_AA64MMFR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8893 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 7,
8894 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8895 .accessfn
= access_aa64_tid3
,
8897 { .name
= "MVFR0_EL1", .state
= ARM_CP_STATE_AA64
,
8898 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 0,
8899 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8900 .accessfn
= access_aa64_tid3
,
8901 .resetvalue
= cpu
->isar
.mvfr0
},
8902 { .name
= "MVFR1_EL1", .state
= ARM_CP_STATE_AA64
,
8903 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 1,
8904 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8905 .accessfn
= access_aa64_tid3
,
8906 .resetvalue
= cpu
->isar
.mvfr1
},
8907 { .name
= "MVFR2_EL1", .state
= ARM_CP_STATE_AA64
,
8908 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 2,
8909 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8910 .accessfn
= access_aa64_tid3
,
8911 .resetvalue
= cpu
->isar
.mvfr2
},
8913 * "0, c0, c3, {0,1,2}" are the encodings corresponding to
8914 * AArch64 MVFR[012]_EL1. Define the STATE_AA32 encoding
8915 * as RAZ, since it is in the "reserved for future ID
8916 * registers, RAZ" part of the AArch32 encoding space.
8918 { .name
= "RES_0_C0_C3_0", .state
= ARM_CP_STATE_AA32
,
8919 .cp
= 15, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 0,
8920 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8921 .accessfn
= access_aa64_tid3
,
8923 { .name
= "RES_0_C0_C3_1", .state
= ARM_CP_STATE_AA32
,
8924 .cp
= 15, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 1,
8925 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8926 .accessfn
= access_aa64_tid3
,
8928 { .name
= "RES_0_C0_C3_2", .state
= ARM_CP_STATE_AA32
,
8929 .cp
= 15, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 2,
8930 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8931 .accessfn
= access_aa64_tid3
,
8934 * Other encodings in "0, c0, c3, ..." are STATE_BOTH because
8935 * they're also RAZ for AArch64, and in v8 are gradually
8936 * being filled with AArch64-view-of-AArch32-ID-register
8937 * for new ID registers.
8939 { .name
= "RES_0_C0_C3_3", .state
= ARM_CP_STATE_BOTH
,
8940 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 3,
8941 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8942 .accessfn
= access_aa64_tid3
,
8944 { .name
= "ID_PFR2", .state
= ARM_CP_STATE_BOTH
,
8945 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 4,
8946 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8947 .accessfn
= access_aa64_tid3
,
8948 .resetvalue
= cpu
->isar
.id_pfr2
},
8949 { .name
= "ID_DFR1", .state
= ARM_CP_STATE_BOTH
,
8950 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 5,
8951 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8952 .accessfn
= access_aa64_tid3
,
8953 .resetvalue
= cpu
->isar
.id_dfr1
},
8954 { .name
= "ID_MMFR5", .state
= ARM_CP_STATE_BOTH
,
8955 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 6,
8956 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8957 .accessfn
= access_aa64_tid3
,
8958 .resetvalue
= cpu
->isar
.id_mmfr5
},
8959 { .name
= "RES_0_C0_C3_7", .state
= ARM_CP_STATE_BOTH
,
8960 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 7,
8961 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8962 .accessfn
= access_aa64_tid3
,
8964 { .name
= "PMCEID0", .state
= ARM_CP_STATE_AA32
,
8965 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 12, .opc2
= 6,
8966 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
8967 .fgt
= FGT_PMCEIDN_EL0
,
8968 .resetvalue
= extract64(cpu
->pmceid0
, 0, 32) },
8969 { .name
= "PMCEID0_EL0", .state
= ARM_CP_STATE_AA64
,
8970 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 6,
8971 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
8972 .fgt
= FGT_PMCEIDN_EL0
,
8973 .resetvalue
= cpu
->pmceid0
},
8974 { .name
= "PMCEID1", .state
= ARM_CP_STATE_AA32
,
8975 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 12, .opc2
= 7,
8976 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
8977 .fgt
= FGT_PMCEIDN_EL0
,
8978 .resetvalue
= extract64(cpu
->pmceid1
, 0, 32) },
8979 { .name
= "PMCEID1_EL0", .state
= ARM_CP_STATE_AA64
,
8980 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 7,
8981 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
8982 .fgt
= FGT_PMCEIDN_EL0
,
8983 .resetvalue
= cpu
->pmceid1
},
8985 #ifdef CONFIG_USER_ONLY
8986 static const ARMCPRegUserSpaceInfo v8_user_idregs
[] = {
8987 { .name
= "ID_AA64PFR0_EL1",
8988 .exported_bits
= R_ID_AA64PFR0_FP_MASK
|
8989 R_ID_AA64PFR0_ADVSIMD_MASK
|
8990 R_ID_AA64PFR0_SVE_MASK
|
8991 R_ID_AA64PFR0_DIT_MASK
,
8992 .fixed_bits
= (0x1u
<< R_ID_AA64PFR0_EL0_SHIFT
) |
8993 (0x1u
<< R_ID_AA64PFR0_EL1_SHIFT
) },
8994 { .name
= "ID_AA64PFR1_EL1",
8995 .exported_bits
= R_ID_AA64PFR1_BT_MASK
|
8996 R_ID_AA64PFR1_SSBS_MASK
|
8997 R_ID_AA64PFR1_MTE_MASK
|
8998 R_ID_AA64PFR1_SME_MASK
},
8999 { .name
= "ID_AA64PFR*_EL1_RESERVED",
9001 { .name
= "ID_AA64ZFR0_EL1",
9002 .exported_bits
= R_ID_AA64ZFR0_SVEVER_MASK
|
9003 R_ID_AA64ZFR0_AES_MASK
|
9004 R_ID_AA64ZFR0_BITPERM_MASK
|
9005 R_ID_AA64ZFR0_BFLOAT16_MASK
|
9006 R_ID_AA64ZFR0_B16B16_MASK
|
9007 R_ID_AA64ZFR0_SHA3_MASK
|
9008 R_ID_AA64ZFR0_SM4_MASK
|
9009 R_ID_AA64ZFR0_I8MM_MASK
|
9010 R_ID_AA64ZFR0_F32MM_MASK
|
9011 R_ID_AA64ZFR0_F64MM_MASK
},
9012 { .name
= "ID_AA64SMFR0_EL1",
9013 .exported_bits
= R_ID_AA64SMFR0_F32F32_MASK
|
9014 R_ID_AA64SMFR0_BI32I32_MASK
|
9015 R_ID_AA64SMFR0_B16F32_MASK
|
9016 R_ID_AA64SMFR0_F16F32_MASK
|
9017 R_ID_AA64SMFR0_I8I32_MASK
|
9018 R_ID_AA64SMFR0_F16F16_MASK
|
9019 R_ID_AA64SMFR0_B16B16_MASK
|
9020 R_ID_AA64SMFR0_I16I32_MASK
|
9021 R_ID_AA64SMFR0_F64F64_MASK
|
9022 R_ID_AA64SMFR0_I16I64_MASK
|
9023 R_ID_AA64SMFR0_SMEVER_MASK
|
9024 R_ID_AA64SMFR0_FA64_MASK
},
9025 { .name
= "ID_AA64MMFR0_EL1",
9026 .exported_bits
= R_ID_AA64MMFR0_ECV_MASK
,
9027 .fixed_bits
= (0xfu
<< R_ID_AA64MMFR0_TGRAN64_SHIFT
) |
9028 (0xfu
<< R_ID_AA64MMFR0_TGRAN4_SHIFT
) },
9029 { .name
= "ID_AA64MMFR1_EL1",
9030 .exported_bits
= R_ID_AA64MMFR1_AFP_MASK
},
9031 { .name
= "ID_AA64MMFR2_EL1",
9032 .exported_bits
= R_ID_AA64MMFR2_AT_MASK
},
9033 { .name
= "ID_AA64MMFR*_EL1_RESERVED",
9035 { .name
= "ID_AA64DFR0_EL1",
9036 .fixed_bits
= (0x6u
<< R_ID_AA64DFR0_DEBUGVER_SHIFT
) },
9037 { .name
= "ID_AA64DFR1_EL1" },
9038 { .name
= "ID_AA64DFR*_EL1_RESERVED",
9040 { .name
= "ID_AA64AFR*",
9042 { .name
= "ID_AA64ISAR0_EL1",
9043 .exported_bits
= R_ID_AA64ISAR0_AES_MASK
|
9044 R_ID_AA64ISAR0_SHA1_MASK
|
9045 R_ID_AA64ISAR0_SHA2_MASK
|
9046 R_ID_AA64ISAR0_CRC32_MASK
|
9047 R_ID_AA64ISAR0_ATOMIC_MASK
|
9048 R_ID_AA64ISAR0_RDM_MASK
|
9049 R_ID_AA64ISAR0_SHA3_MASK
|
9050 R_ID_AA64ISAR0_SM3_MASK
|
9051 R_ID_AA64ISAR0_SM4_MASK
|
9052 R_ID_AA64ISAR0_DP_MASK
|
9053 R_ID_AA64ISAR0_FHM_MASK
|
9054 R_ID_AA64ISAR0_TS_MASK
|
9055 R_ID_AA64ISAR0_RNDR_MASK
},
9056 { .name
= "ID_AA64ISAR1_EL1",
9057 .exported_bits
= R_ID_AA64ISAR1_DPB_MASK
|
9058 R_ID_AA64ISAR1_APA_MASK
|
9059 R_ID_AA64ISAR1_API_MASK
|
9060 R_ID_AA64ISAR1_JSCVT_MASK
|
9061 R_ID_AA64ISAR1_FCMA_MASK
|
9062 R_ID_AA64ISAR1_LRCPC_MASK
|
9063 R_ID_AA64ISAR1_GPA_MASK
|
9064 R_ID_AA64ISAR1_GPI_MASK
|
9065 R_ID_AA64ISAR1_FRINTTS_MASK
|
9066 R_ID_AA64ISAR1_SB_MASK
|
9067 R_ID_AA64ISAR1_BF16_MASK
|
9068 R_ID_AA64ISAR1_DGH_MASK
|
9069 R_ID_AA64ISAR1_I8MM_MASK
},
9070 { .name
= "ID_AA64ISAR2_EL1",
9071 .exported_bits
= R_ID_AA64ISAR2_WFXT_MASK
|
9072 R_ID_AA64ISAR2_RPRES_MASK
|
9073 R_ID_AA64ISAR2_GPA3_MASK
|
9074 R_ID_AA64ISAR2_APA3_MASK
|
9075 R_ID_AA64ISAR2_MOPS_MASK
|
9076 R_ID_AA64ISAR2_BC_MASK
|
9077 R_ID_AA64ISAR2_RPRFM_MASK
|
9078 R_ID_AA64ISAR2_CSSC_MASK
},
9079 { .name
= "ID_AA64ISAR*_EL1_RESERVED",
9082 modify_arm_cp_regs(v8_idregs
, v8_user_idregs
);
9085 * RVBAR_EL1 and RMR_EL1 only implemented if EL1 is the highest EL.
9086 * TODO: For RMR, a write with bit 1 set should do something with
9087 * cpu_reset(). In the meantime, "the bit is strictly a request",
9088 * so we are in spec just ignoring writes.
9090 if (!arm_feature(env
, ARM_FEATURE_EL3
) &&
9091 !arm_feature(env
, ARM_FEATURE_EL2
)) {
9092 ARMCPRegInfo el1_reset_regs
[] = {
9093 { .name
= "RVBAR_EL1", .state
= ARM_CP_STATE_BOTH
,
9094 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 0, .opc2
= 1,
9096 .fieldoffset
= offsetof(CPUARMState
, cp15
.rvbar
) },
9097 { .name
= "RMR_EL1", .state
= ARM_CP_STATE_BOTH
,
9098 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 0, .opc2
= 2,
9099 .access
= PL1_RW
, .type
= ARM_CP_CONST
,
9100 .resetvalue
= arm_feature(env
, ARM_FEATURE_AARCH64
) }
9102 define_arm_cp_regs(cpu
, el1_reset_regs
);
9104 define_arm_cp_regs(cpu
, v8_idregs
);
9105 define_arm_cp_regs(cpu
, v8_cp_reginfo
);
9106 if (cpu_isar_feature(aa64_aa32_el1
, cpu
)) {
9107 define_arm_cp_regs(cpu
, v8_aa32_el1_reginfo
);
9110 for (i
= 4; i
< 16; i
++) {
9112 * Encodings in "0, c0, {c4-c7}, {0-7}" are RAZ for AArch32.
9113 * For pre-v8 cores there are RAZ patterns for these in
9114 * id_pre_v8_midr_cp_reginfo[]; for v8 we do that here.
9115 * v8 extends the "must RAZ" part of the ID register space
9116 * to also cover c0, 0, c{8-15}, {0-7}.
9117 * These are STATE_AA32 because in the AArch64 sysreg space
9118 * c4-c7 is where the AArch64 ID registers live (and we've
9119 * already defined those in v8_idregs[]), and c8-c15 are not
9120 * "must RAZ" for AArch64.
9122 g_autofree
char *name
= g_strdup_printf("RES_0_C0_C%d_X", i
);
9123 ARMCPRegInfo v8_aa32_raz_idregs
= {
9125 .state
= ARM_CP_STATE_AA32
,
9126 .cp
= 15, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= CP_ANY
,
9127 .access
= PL1_R
, .type
= ARM_CP_CONST
,
9128 .accessfn
= access_aa64_tid3
,
9130 define_one_arm_cp_reg(cpu
, &v8_aa32_raz_idregs
);
9135 * Register the base EL2 cpregs.
9136 * Pre v8, these registers are implemented only as part of the
9137 * Virtualization Extensions (EL2 present). Beginning with v8,
9138 * if EL2 is missing but EL3 is enabled, mostly these become
9139 * RES0 from EL3, with some specific exceptions.
9141 if (arm_feature(env
, ARM_FEATURE_EL2
)
9142 || (arm_feature(env
, ARM_FEATURE_EL3
)
9143 && arm_feature(env
, ARM_FEATURE_V8
))) {
9144 uint64_t vmpidr_def
= mpidr_read_val(env
);
9145 ARMCPRegInfo vpidr_regs
[] = {
9146 { .name
= "VPIDR", .state
= ARM_CP_STATE_AA32
,
9147 .cp
= 15, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 0,
9148 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
9149 .resetvalue
= cpu
->midr
,
9150 .type
= ARM_CP_ALIAS
| ARM_CP_EL3_NO_EL2_C_NZ
,
9151 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.vpidr_el2
) },
9152 { .name
= "VPIDR_EL2", .state
= ARM_CP_STATE_AA64
,
9153 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 0,
9154 .access
= PL2_RW
, .resetvalue
= cpu
->midr
,
9155 .type
= ARM_CP_EL3_NO_EL2_C_NZ
,
9156 .nv2_redirect_offset
= 0x88,
9157 .fieldoffset
= offsetof(CPUARMState
, cp15
.vpidr_el2
) },
9158 { .name
= "VMPIDR", .state
= ARM_CP_STATE_AA32
,
9159 .cp
= 15, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 5,
9160 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
9161 .resetvalue
= vmpidr_def
,
9162 .type
= ARM_CP_ALIAS
| ARM_CP_EL3_NO_EL2_C_NZ
,
9163 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.vmpidr_el2
) },
9164 { .name
= "VMPIDR_EL2", .state
= ARM_CP_STATE_AA64
,
9165 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 5,
9166 .access
= PL2_RW
, .resetvalue
= vmpidr_def
,
9167 .type
= ARM_CP_EL3_NO_EL2_C_NZ
,
9168 .nv2_redirect_offset
= 0x50,
9169 .fieldoffset
= offsetof(CPUARMState
, cp15
.vmpidr_el2
) },
9172 * The only field of MDCR_EL2 that has a defined architectural reset
9173 * value is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N.
9175 ARMCPRegInfo mdcr_el2
= {
9176 .name
= "MDCR_EL2", .state
= ARM_CP_STATE_BOTH
, .type
= ARM_CP_IO
,
9177 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 1,
9178 .writefn
= mdcr_el2_write
,
9179 .access
= PL2_RW
, .resetvalue
= pmu_num_counters(env
),
9180 .fieldoffset
= offsetof(CPUARMState
, cp15
.mdcr_el2
),
9182 define_one_arm_cp_reg(cpu
, &mdcr_el2
);
9183 define_arm_cp_regs(cpu
, vpidr_regs
);
9184 define_arm_cp_regs(cpu
, el2_cp_reginfo
);
9185 if (arm_feature(env
, ARM_FEATURE_V8
)) {
9186 define_arm_cp_regs(cpu
, el2_v8_cp_reginfo
);
9188 if (cpu_isar_feature(aa64_sel2
, cpu
)) {
9189 define_arm_cp_regs(cpu
, el2_sec_cp_reginfo
);
9192 * RVBAR_EL2 and RMR_EL2 only implemented if EL2 is the highest EL.
9193 * See commentary near RMR_EL1.
9195 if (!arm_feature(env
, ARM_FEATURE_EL3
)) {
9196 static const ARMCPRegInfo el2_reset_regs
[] = {
9197 { .name
= "RVBAR_EL2", .state
= ARM_CP_STATE_AA64
,
9198 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 0, .opc2
= 1,
9200 .fieldoffset
= offsetof(CPUARMState
, cp15
.rvbar
) },
9201 { .name
= "RVBAR", .type
= ARM_CP_ALIAS
,
9202 .cp
= 15, .opc1
= 0, .crn
= 12, .crm
= 0, .opc2
= 1,
9204 .fieldoffset
= offsetof(CPUARMState
, cp15
.rvbar
) },
9205 { .name
= "RMR_EL2", .state
= ARM_CP_STATE_AA64
,
9206 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 0, .opc2
= 2,
9207 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 1 },
9209 define_arm_cp_regs(cpu
, el2_reset_regs
);
9213 /* Register the base EL3 cpregs. */
9214 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
9215 define_arm_cp_regs(cpu
, el3_cp_reginfo
);
9216 ARMCPRegInfo el3_regs
[] = {
9217 { .name
= "RVBAR_EL3", .state
= ARM_CP_STATE_AA64
,
9218 .opc0
= 3, .opc1
= 6, .crn
= 12, .crm
= 0, .opc2
= 1,
9220 .fieldoffset
= offsetof(CPUARMState
, cp15
.rvbar
), },
9221 { .name
= "RMR_EL3", .state
= ARM_CP_STATE_AA64
,
9222 .opc0
= 3, .opc1
= 6, .crn
= 12, .crm
= 0, .opc2
= 2,
9223 .access
= PL3_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 1 },
9224 { .name
= "RMR", .state
= ARM_CP_STATE_AA32
,
9225 .cp
= 15, .opc1
= 0, .crn
= 12, .crm
= 0, .opc2
= 2,
9226 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
9227 .resetvalue
= arm_feature(env
, ARM_FEATURE_AARCH64
) },
9228 { .name
= "SCTLR_EL3", .state
= ARM_CP_STATE_AA64
,
9229 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 0, .opc2
= 0,
9231 .raw_writefn
= raw_write
, .writefn
= sctlr_write
,
9232 .fieldoffset
= offsetof(CPUARMState
, cp15
.sctlr_el
[3]),
9233 .resetvalue
= cpu
->reset_sctlr
},
9236 define_arm_cp_regs(cpu
, el3_regs
);
9239 * The behaviour of NSACR is sufficiently various that we don't
9240 * try to describe it in a single reginfo:
9241 * if EL3 is 64 bit, then trap to EL3 from S EL1,
9242 * reads as constant 0xc00 from NS EL1 and NS EL2
9243 * if EL3 is 32 bit, then RW at EL3, RO at NS EL1 and NS EL2
9244 * if v7 without EL3, register doesn't exist
9245 * if v8 without EL3, reads as constant 0xc00 from NS EL1 and NS EL2
9247 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
9248 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
9249 static const ARMCPRegInfo nsacr
= {
9250 .name
= "NSACR", .type
= ARM_CP_CONST
,
9251 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 2,
9252 .access
= PL1_RW
, .accessfn
= nsacr_access
,
9255 define_one_arm_cp_reg(cpu
, &nsacr
);
9257 static const ARMCPRegInfo nsacr
= {
9259 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 2,
9260 .access
= PL3_RW
| PL1_R
,
9262 .fieldoffset
= offsetof(CPUARMState
, cp15
.nsacr
)
9264 define_one_arm_cp_reg(cpu
, &nsacr
);
9267 if (arm_feature(env
, ARM_FEATURE_V8
)) {
9268 static const ARMCPRegInfo nsacr
= {
9269 .name
= "NSACR", .type
= ARM_CP_CONST
,
9270 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 2,
9274 define_one_arm_cp_reg(cpu
, &nsacr
);
9278 if (arm_feature(env
, ARM_FEATURE_PMSA
)) {
9279 if (arm_feature(env
, ARM_FEATURE_V6
)) {
9280 /* PMSAv6 not implemented */
9281 assert(arm_feature(env
, ARM_FEATURE_V7
));
9282 define_arm_cp_regs(cpu
, vmsa_pmsa_cp_reginfo
);
9283 define_arm_cp_regs(cpu
, pmsav7_cp_reginfo
);
9285 define_arm_cp_regs(cpu
, pmsav5_cp_reginfo
);
9288 define_arm_cp_regs(cpu
, vmsa_pmsa_cp_reginfo
);
9289 define_arm_cp_regs(cpu
, vmsa_cp_reginfo
);
9290 /* TTCBR2 is introduced with ARMv8.2-AA32HPD. */
9291 if (cpu_isar_feature(aa32_hpd
, cpu
)) {
9292 define_one_arm_cp_reg(cpu
, &ttbcr2_reginfo
);
9295 if (arm_feature(env
, ARM_FEATURE_THUMB2EE
)) {
9296 define_arm_cp_regs(cpu
, t2ee_cp_reginfo
);
9298 if (arm_feature(env
, ARM_FEATURE_GENERIC_TIMER
)) {
9299 define_arm_cp_regs(cpu
, generic_timer_cp_reginfo
);
9301 if (cpu_isar_feature(aa64_ecv_traps
, cpu
)) {
9302 define_arm_cp_regs(cpu
, gen_timer_ecv_cp_reginfo
);
9304 if (arm_feature(env
, ARM_FEATURE_VAPA
)) {
9305 ARMCPRegInfo vapa_cp_reginfo
[] = {
9306 { .name
= "PAR", .cp
= 15, .crn
= 7, .crm
= 4, .opc1
= 0, .opc2
= 0,
9307 .access
= PL1_RW
, .resetvalue
= 0,
9308 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.par_s
),
9309 offsetoflow32(CPUARMState
, cp15
.par_ns
) },
9310 .writefn
= par_write
},
9311 #ifndef CONFIG_USER_ONLY
9312 /* This underdecoding is safe because the reginfo is NO_RAW. */
9313 { .name
= "ATS", .cp
= 15, .crn
= 7, .crm
= 8, .opc1
= 0, .opc2
= CP_ANY
,
9314 .access
= PL1_W
, .accessfn
= ats_access
,
9315 .writefn
= ats_write
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
},
9320 * When LPAE exists this 32-bit PAR register is an alias of the
9321 * 64-bit AArch32 PAR register defined in lpae_cp_reginfo[]
9323 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
9324 vapa_cp_reginfo
[0].type
= ARM_CP_ALIAS
| ARM_CP_NO_GDB
;
9326 define_arm_cp_regs(cpu
, vapa_cp_reginfo
);
9328 if (arm_feature(env
, ARM_FEATURE_CACHE_TEST_CLEAN
)) {
9329 define_arm_cp_regs(cpu
, cache_test_clean_cp_reginfo
);
9331 if (arm_feature(env
, ARM_FEATURE_CACHE_DIRTY_REG
)) {
9332 define_arm_cp_regs(cpu
, cache_dirty_status_cp_reginfo
);
9334 if (arm_feature(env
, ARM_FEATURE_CACHE_BLOCK_OPS
)) {
9335 define_arm_cp_regs(cpu
, cache_block_ops_cp_reginfo
);
9337 if (arm_feature(env
, ARM_FEATURE_OMAPCP
)) {
9338 define_arm_cp_regs(cpu
, omap_cp_reginfo
);
9340 if (arm_feature(env
, ARM_FEATURE_STRONGARM
)) {
9341 define_arm_cp_regs(cpu
, strongarm_cp_reginfo
);
9343 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
9344 define_arm_cp_regs(cpu
, xscale_cp_reginfo
);
9346 if (arm_feature(env
, ARM_FEATURE_DUMMY_C15_REGS
)) {
9347 define_arm_cp_regs(cpu
, dummy_c15_cp_reginfo
);
9349 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
9350 define_arm_cp_regs(cpu
, lpae_cp_reginfo
);
9352 if (cpu_isar_feature(aa32_jazelle
, cpu
)) {
9353 define_arm_cp_regs(cpu
, jazelle_regs
);
9356 * Slightly awkwardly, the OMAP and StrongARM cores need all of
9357 * cp15 crn=0 to be writes-ignored, whereas for other cores they should
9358 * be read-only (ie write causes UNDEF exception).
9361 ARMCPRegInfo id_pre_v8_midr_cp_reginfo
[] = {
9363 * Pre-v8 MIDR space.
9364 * Note that the MIDR isn't a simple constant register because
9365 * of the TI925 behaviour where writes to another register can
9366 * cause the MIDR value to change.
9368 * Unimplemented registers in the c15 0 0 0 space default to
9369 * MIDR. Define MIDR first as this entire space, then CTR, TCMTR
9370 * and friends override accordingly.
9373 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= CP_ANY
,
9374 .access
= PL1_R
, .resetvalue
= cpu
->midr
,
9375 .writefn
= arm_cp_write_ignore
, .raw_writefn
= raw_write
,
9376 .readfn
= midr_read
,
9377 .fieldoffset
= offsetof(CPUARMState
, cp15
.c0_cpuid
),
9378 .type
= ARM_CP_OVERRIDE
},
9379 /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
9381 .cp
= 15, .crn
= 0, .crm
= 3, .opc1
= 0, .opc2
= CP_ANY
,
9382 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
9384 .cp
= 15, .crn
= 0, .crm
= 4, .opc1
= 0, .opc2
= CP_ANY
,
9385 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
9387 .cp
= 15, .crn
= 0, .crm
= 5, .opc1
= 0, .opc2
= CP_ANY
,
9388 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
9390 .cp
= 15, .crn
= 0, .crm
= 6, .opc1
= 0, .opc2
= CP_ANY
,
9391 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
9393 .cp
= 15, .crn
= 0, .crm
= 7, .opc1
= 0, .opc2
= CP_ANY
,
9394 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
9396 ARMCPRegInfo id_v8_midr_cp_reginfo
[] = {
9397 { .name
= "MIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
9398 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 0, .opc2
= 0,
9399 .access
= PL1_R
, .type
= ARM_CP_NO_RAW
, .resetvalue
= cpu
->midr
,
9400 .fgt
= FGT_MIDR_EL1
,
9401 .fieldoffset
= offsetof(CPUARMState
, cp15
.c0_cpuid
),
9402 .readfn
= midr_read
},
9403 /* crn = 0 op1 = 0 crm = 0 op2 = 7 : AArch32 aliases of MIDR */
9404 { .name
= "MIDR", .type
= ARM_CP_ALIAS
| ARM_CP_CONST
,
9405 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 7,
9406 .access
= PL1_R
, .resetvalue
= cpu
->midr
},
9407 { .name
= "REVIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
9408 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 0, .opc2
= 6,
9410 .accessfn
= access_aa64_tid1
,
9411 .fgt
= FGT_REVIDR_EL1
,
9412 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->revidr
},
9414 ARMCPRegInfo id_v8_midr_alias_cp_reginfo
= {
9415 .name
= "MIDR", .type
= ARM_CP_ALIAS
| ARM_CP_CONST
| ARM_CP_NO_GDB
,
9416 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 4,
9417 .access
= PL1_R
, .resetvalue
= cpu
->midr
9419 ARMCPRegInfo id_cp_reginfo
[] = {
9420 /* These are common to v8 and pre-v8 */
9422 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 1,
9423 .access
= PL1_R
, .accessfn
= ctr_el0_access
,
9424 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->ctr
},
9425 { .name
= "CTR_EL0", .state
= ARM_CP_STATE_AA64
,
9426 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 0, .crm
= 0,
9427 .access
= PL0_R
, .accessfn
= ctr_el0_access
,
9429 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->ctr
},
9430 /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */
9432 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 2,
9434 .accessfn
= access_aa32_tid1
,
9435 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
9437 /* TLBTR is specific to VMSA */
9438 ARMCPRegInfo id_tlbtr_reginfo
= {
9440 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 3,
9442 .accessfn
= access_aa32_tid1
,
9443 .type
= ARM_CP_CONST
, .resetvalue
= 0,
9445 /* MPUIR is specific to PMSA V6+ */
9446 ARMCPRegInfo id_mpuir_reginfo
= {
9448 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 4,
9449 .access
= PL1_R
, .type
= ARM_CP_CONST
,
9450 .resetvalue
= cpu
->pmsav7_dregion
<< 8
9452 /* HMPUIR is specific to PMSA V8 */
9453 ARMCPRegInfo id_hmpuir_reginfo
= {
9455 .cp
= 15, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 4,
9456 .access
= PL2_R
, .type
= ARM_CP_CONST
,
9457 .resetvalue
= cpu
->pmsav8r_hdregion
9459 static const ARMCPRegInfo crn0_wi_reginfo
= {
9460 .name
= "CRN0_WI", .cp
= 15, .crn
= 0, .crm
= CP_ANY
,
9461 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_W
,
9462 .type
= ARM_CP_NOP
| ARM_CP_OVERRIDE
9464 #ifdef CONFIG_USER_ONLY
9465 static const ARMCPRegUserSpaceInfo id_v8_user_midr_cp_reginfo
[] = {
9466 { .name
= "MIDR_EL1",
9467 .exported_bits
= R_MIDR_EL1_REVISION_MASK
|
9468 R_MIDR_EL1_PARTNUM_MASK
|
9469 R_MIDR_EL1_ARCHITECTURE_MASK
|
9470 R_MIDR_EL1_VARIANT_MASK
|
9471 R_MIDR_EL1_IMPLEMENTER_MASK
},
9472 { .name
= "REVIDR_EL1" },
9474 modify_arm_cp_regs(id_v8_midr_cp_reginfo
, id_v8_user_midr_cp_reginfo
);
9476 if (arm_feature(env
, ARM_FEATURE_OMAPCP
) ||
9477 arm_feature(env
, ARM_FEATURE_STRONGARM
)) {
9480 * Register the blanket "writes ignored" value first to cover the
9481 * whole space. Then update the specific ID registers to allow write
9482 * access, so that they ignore writes rather than causing them to
9485 define_one_arm_cp_reg(cpu
, &crn0_wi_reginfo
);
9486 for (i
= 0; i
< ARRAY_SIZE(id_pre_v8_midr_cp_reginfo
); ++i
) {
9487 id_pre_v8_midr_cp_reginfo
[i
].access
= PL1_RW
;
9489 for (i
= 0; i
< ARRAY_SIZE(id_cp_reginfo
); ++i
) {
9490 id_cp_reginfo
[i
].access
= PL1_RW
;
9492 id_mpuir_reginfo
.access
= PL1_RW
;
9493 id_tlbtr_reginfo
.access
= PL1_RW
;
9495 if (arm_feature(env
, ARM_FEATURE_V8
)) {
9496 define_arm_cp_regs(cpu
, id_v8_midr_cp_reginfo
);
9497 if (!arm_feature(env
, ARM_FEATURE_PMSA
)) {
9498 define_one_arm_cp_reg(cpu
, &id_v8_midr_alias_cp_reginfo
);
9501 define_arm_cp_regs(cpu
, id_pre_v8_midr_cp_reginfo
);
9503 define_arm_cp_regs(cpu
, id_cp_reginfo
);
9504 if (!arm_feature(env
, ARM_FEATURE_PMSA
)) {
9505 define_one_arm_cp_reg(cpu
, &id_tlbtr_reginfo
);
9506 } else if (arm_feature(env
, ARM_FEATURE_PMSA
) &&
9507 arm_feature(env
, ARM_FEATURE_V8
)) {
9511 define_one_arm_cp_reg(cpu
, &id_mpuir_reginfo
);
9512 define_one_arm_cp_reg(cpu
, &id_hmpuir_reginfo
);
9513 define_arm_cp_regs(cpu
, pmsav8r_cp_reginfo
);
9515 /* Register alias is only valid for first 32 indexes */
9516 for (i
= 0; i
< MIN(cpu
->pmsav7_dregion
, 32); ++i
) {
9517 uint8_t crm
= 0b1000 | extract32(i
, 1, 3);
9518 uint8_t opc1
= extract32(i
, 4, 1);
9519 uint8_t opc2
= extract32(i
, 0, 1) << 2;
9521 tmp_string
= g_strdup_printf("PRBAR%u", i
);
9522 ARMCPRegInfo tmp_prbarn_reginfo
= {
9523 .name
= tmp_string
, .type
= ARM_CP_ALIAS
| ARM_CP_NO_RAW
,
9524 .cp
= 15, .opc1
= opc1
, .crn
= 6, .crm
= crm
, .opc2
= opc2
,
9525 .access
= PL1_RW
, .resetvalue
= 0,
9526 .accessfn
= access_tvm_trvm
,
9527 .writefn
= pmsav8r_regn_write
, .readfn
= pmsav8r_regn_read
9529 define_one_arm_cp_reg(cpu
, &tmp_prbarn_reginfo
);
9532 opc2
= extract32(i
, 0, 1) << 2 | 0x1;
9533 tmp_string
= g_strdup_printf("PRLAR%u", i
);
9534 ARMCPRegInfo tmp_prlarn_reginfo
= {
9535 .name
= tmp_string
, .type
= ARM_CP_ALIAS
| ARM_CP_NO_RAW
,
9536 .cp
= 15, .opc1
= opc1
, .crn
= 6, .crm
= crm
, .opc2
= opc2
,
9537 .access
= PL1_RW
, .resetvalue
= 0,
9538 .accessfn
= access_tvm_trvm
,
9539 .writefn
= pmsav8r_regn_write
, .readfn
= pmsav8r_regn_read
9541 define_one_arm_cp_reg(cpu
, &tmp_prlarn_reginfo
);
9545 /* Register alias is only valid for first 32 indexes */
9546 for (i
= 0; i
< MIN(cpu
->pmsav8r_hdregion
, 32); ++i
) {
9547 uint8_t crm
= 0b1000 | extract32(i
, 1, 3);
9548 uint8_t opc1
= 0b100 | extract32(i
, 4, 1);
9549 uint8_t opc2
= extract32(i
, 0, 1) << 2;
9551 tmp_string
= g_strdup_printf("HPRBAR%u", i
);
9552 ARMCPRegInfo tmp_hprbarn_reginfo
= {
9554 .type
= ARM_CP_NO_RAW
,
9555 .cp
= 15, .opc1
= opc1
, .crn
= 6, .crm
= crm
, .opc2
= opc2
,
9556 .access
= PL2_RW
, .resetvalue
= 0,
9557 .writefn
= pmsav8r_regn_write
, .readfn
= pmsav8r_regn_read
9559 define_one_arm_cp_reg(cpu
, &tmp_hprbarn_reginfo
);
9562 opc2
= extract32(i
, 0, 1) << 2 | 0x1;
9563 tmp_string
= g_strdup_printf("HPRLAR%u", i
);
9564 ARMCPRegInfo tmp_hprlarn_reginfo
= {
9566 .type
= ARM_CP_NO_RAW
,
9567 .cp
= 15, .opc1
= opc1
, .crn
= 6, .crm
= crm
, .opc2
= opc2
,
9568 .access
= PL2_RW
, .resetvalue
= 0,
9569 .writefn
= pmsav8r_regn_write
, .readfn
= pmsav8r_regn_read
9571 define_one_arm_cp_reg(cpu
, &tmp_hprlarn_reginfo
);
9574 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
9575 define_one_arm_cp_reg(cpu
, &id_mpuir_reginfo
);
9579 if (arm_feature(env
, ARM_FEATURE_MPIDR
)) {
9580 ARMCPRegInfo mpidr_cp_reginfo
[] = {
9581 { .name
= "MPIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
9582 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 5,
9583 .fgt
= FGT_MPIDR_EL1
,
9584 .access
= PL1_R
, .readfn
= mpidr_read
, .type
= ARM_CP_NO_RAW
},
9586 #ifdef CONFIG_USER_ONLY
9587 static const ARMCPRegUserSpaceInfo mpidr_user_cp_reginfo
[] = {
9588 { .name
= "MPIDR_EL1",
9589 .fixed_bits
= 0x0000000080000000 },
9591 modify_arm_cp_regs(mpidr_cp_reginfo
, mpidr_user_cp_reginfo
);
9593 define_arm_cp_regs(cpu
, mpidr_cp_reginfo
);
9596 if (arm_feature(env
, ARM_FEATURE_AUXCR
)) {
9597 ARMCPRegInfo auxcr_reginfo
[] = {
9598 { .name
= "ACTLR_EL1", .state
= ARM_CP_STATE_BOTH
,
9599 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 1,
9600 .access
= PL1_RW
, .accessfn
= access_tacr
,
9601 .nv2_redirect_offset
= 0x118,
9602 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->reset_auxcr
},
9603 { .name
= "ACTLR_EL2", .state
= ARM_CP_STATE_BOTH
,
9604 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 1,
9605 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
9607 { .name
= "ACTLR_EL3", .state
= ARM_CP_STATE_AA64
,
9608 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 0, .opc2
= 1,
9609 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
9612 define_arm_cp_regs(cpu
, auxcr_reginfo
);
9613 if (cpu_isar_feature(aa32_ac2
, cpu
)) {
9614 define_arm_cp_regs(cpu
, actlr2_hactlr2_reginfo
);
9618 if (arm_feature(env
, ARM_FEATURE_CBAR
)) {
9620 * CBAR is IMPDEF, but common on Arm Cortex-A implementations.
9621 * There are two flavours:
9622 * (1) older 32-bit only cores have a simple 32-bit CBAR
9623 * (2) 64-bit cores have a 64-bit CBAR visible to AArch64, plus a
9624 * 32-bit register visible to AArch32 at a different encoding
9625 * to the "flavour 1" register and with the bits rearranged to
9626 * be able to squash a 64-bit address into the 32-bit view.
9627 * We distinguish the two via the ARM_FEATURE_AARCH64 flag, but
9628 * in future if we support AArch32-only configs of some of the
9629 * AArch64 cores we might need to add a specific feature flag
9630 * to indicate cores with "flavour 2" CBAR.
9632 if (arm_feature(env
, ARM_FEATURE_V8
)) {
9633 /* 32 bit view is [31:18] 0...0 [43:32]. */
9634 uint32_t cbar32
= (extract64(cpu
->reset_cbar
, 18, 14) << 18)
9635 | extract64(cpu
->reset_cbar
, 32, 12);
9636 ARMCPRegInfo cbar_reginfo
[] = {
9638 .type
= ARM_CP_CONST
,
9639 .cp
= 15, .crn
= 15, .crm
= 3, .opc1
= 1, .opc2
= 0,
9640 .access
= PL1_R
, .resetvalue
= cbar32
},
9641 { .name
= "CBAR_EL1", .state
= ARM_CP_STATE_AA64
,
9642 .type
= ARM_CP_CONST
,
9643 .opc0
= 3, .opc1
= 1, .crn
= 15, .crm
= 3, .opc2
= 0,
9644 .access
= PL1_R
, .resetvalue
= cpu
->reset_cbar
},
9646 /* We don't implement a r/w 64 bit CBAR currently */
9647 assert(arm_feature(env
, ARM_FEATURE_CBAR_RO
));
9648 define_arm_cp_regs(cpu
, cbar_reginfo
);
9650 ARMCPRegInfo cbar
= {
9652 .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 4, .opc2
= 0,
9653 .access
= PL1_R
| PL3_W
, .resetvalue
= cpu
->reset_cbar
,
9654 .fieldoffset
= offsetof(CPUARMState
,
9655 cp15
.c15_config_base_address
)
9657 if (arm_feature(env
, ARM_FEATURE_CBAR_RO
)) {
9658 cbar
.access
= PL1_R
;
9659 cbar
.fieldoffset
= 0;
9660 cbar
.type
= ARM_CP_CONST
;
9662 define_one_arm_cp_reg(cpu
, &cbar
);
9666 if (arm_feature(env
, ARM_FEATURE_VBAR
)) {
9667 static const ARMCPRegInfo vbar_cp_reginfo
[] = {
9668 { .name
= "VBAR", .state
= ARM_CP_STATE_BOTH
,
9669 .opc0
= 3, .crn
= 12, .crm
= 0, .opc1
= 0, .opc2
= 0,
9670 .access
= PL1_RW
, .writefn
= vbar_write
,
9671 .accessfn
= access_nv1
,
9672 .fgt
= FGT_VBAR_EL1
,
9673 .nv2_redirect_offset
= 0x250 | NV2_REDIR_NV1
,
9674 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.vbar_s
),
9675 offsetof(CPUARMState
, cp15
.vbar_ns
) },
9678 define_arm_cp_regs(cpu
, vbar_cp_reginfo
);
9681 /* Generic registers whose values depend on the implementation */
9683 ARMCPRegInfo sctlr
= {
9684 .name
= "SCTLR", .state
= ARM_CP_STATE_BOTH
,
9685 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 0,
9686 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
9687 .fgt
= FGT_SCTLR_EL1
,
9688 .nv2_redirect_offset
= 0x110 | NV2_REDIR_NV1
,
9689 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.sctlr_s
),
9690 offsetof(CPUARMState
, cp15
.sctlr_ns
) },
9691 .writefn
= sctlr_write
, .resetvalue
= cpu
->reset_sctlr
,
9692 .raw_writefn
= raw_write
,
9694 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
9696 * Normally we would always end the TB on an SCTLR write, but Linux
9697 * arch/arm/mach-pxa/sleep.S expects two instructions following
9698 * an MMU enable to execute from cache. Imitate this behaviour.
9700 sctlr
.type
|= ARM_CP_SUPPRESS_TB_END
;
9702 define_one_arm_cp_reg(cpu
, &sctlr
);
9704 if (arm_feature(env
, ARM_FEATURE_PMSA
) &&
9705 arm_feature(env
, ARM_FEATURE_V8
)) {
9706 ARMCPRegInfo vsctlr
= {
9707 .name
= "VSCTLR", .state
= ARM_CP_STATE_AA32
,
9708 .cp
= 15, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 0,
9709 .access
= PL2_RW
, .resetvalue
= 0x0,
9710 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.vsctlr
),
9712 define_one_arm_cp_reg(cpu
, &vsctlr
);
9716 if (cpu_isar_feature(aa64_lor
, cpu
)) {
9717 define_arm_cp_regs(cpu
, lor_reginfo
);
9719 if (cpu_isar_feature(aa64_pan
, cpu
)) {
9720 define_one_arm_cp_reg(cpu
, &pan_reginfo
);
9722 #ifndef CONFIG_USER_ONLY
9723 if (cpu_isar_feature(aa64_ats1e1
, cpu
)) {
9724 define_arm_cp_regs(cpu
, ats1e1_reginfo
);
9726 if (cpu_isar_feature(aa32_ats1e1
, cpu
)) {
9727 define_arm_cp_regs(cpu
, ats1cp_reginfo
);
9730 if (cpu_isar_feature(aa64_uao
, cpu
)) {
9731 define_one_arm_cp_reg(cpu
, &uao_reginfo
);
9734 if (cpu_isar_feature(aa64_dit
, cpu
)) {
9735 define_one_arm_cp_reg(cpu
, &dit_reginfo
);
9737 if (cpu_isar_feature(aa64_ssbs
, cpu
)) {
9738 define_one_arm_cp_reg(cpu
, &ssbs_reginfo
);
9740 if (cpu_isar_feature(any_ras
, cpu
)) {
9741 define_arm_cp_regs(cpu
, minimal_ras_reginfo
);
9744 if (cpu_isar_feature(aa64_vh
, cpu
) ||
9745 cpu_isar_feature(aa64_debugv8p2
, cpu
)) {
9746 define_one_arm_cp_reg(cpu
, &contextidr_el2
);
9748 if (arm_feature(env
, ARM_FEATURE_EL2
) && cpu_isar_feature(aa64_vh
, cpu
)) {
9749 define_arm_cp_regs(cpu
, vhe_reginfo
);
9752 if (cpu_isar_feature(aa64_sve
, cpu
)) {
9753 define_arm_cp_regs(cpu
, zcr_reginfo
);
9756 if (cpu_isar_feature(aa64_hcx
, cpu
)) {
9757 define_one_arm_cp_reg(cpu
, &hcrx_el2_reginfo
);
9760 #ifdef TARGET_AARCH64
9761 if (cpu_isar_feature(aa64_sme
, cpu
)) {
9762 define_arm_cp_regs(cpu
, sme_reginfo
);
9764 if (cpu_isar_feature(aa64_pauth
, cpu
)) {
9765 define_arm_cp_regs(cpu
, pauth_reginfo
);
9767 if (cpu_isar_feature(aa64_rndr
, cpu
)) {
9768 define_arm_cp_regs(cpu
, rndr_reginfo
);
9770 if (cpu_isar_feature(aa64_tlbirange
, cpu
)) {
9771 define_arm_cp_regs(cpu
, tlbirange_reginfo
);
9773 if (cpu_isar_feature(aa64_tlbios
, cpu
)) {
9774 define_arm_cp_regs(cpu
, tlbios_reginfo
);
9776 /* Data Cache clean instructions up to PoP */
9777 if (cpu_isar_feature(aa64_dcpop
, cpu
)) {
9778 define_one_arm_cp_reg(cpu
, dcpop_reg
);
9780 if (cpu_isar_feature(aa64_dcpodp
, cpu
)) {
9781 define_one_arm_cp_reg(cpu
, dcpodp_reg
);
9786 * If full MTE is enabled, add all of the system registers.
9787 * If only "instructions available at EL0" are enabled,
9788 * then define only a RAZ/WI version of PSTATE.TCO.
9790 if (cpu_isar_feature(aa64_mte
, cpu
)) {
9791 ARMCPRegInfo gmid_reginfo
= {
9792 .name
= "GMID_EL1", .state
= ARM_CP_STATE_AA64
,
9793 .opc0
= 3, .opc1
= 1, .crn
= 0, .crm
= 0, .opc2
= 4,
9794 .access
= PL1_R
, .accessfn
= access_aa64_tid5
,
9795 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->gm_blocksize
,
9797 define_one_arm_cp_reg(cpu
, &gmid_reginfo
);
9798 define_arm_cp_regs(cpu
, mte_reginfo
);
9799 define_arm_cp_regs(cpu
, mte_el0_cacheop_reginfo
);
9800 } else if (cpu_isar_feature(aa64_mte_insn_reg
, cpu
)) {
9801 define_arm_cp_regs(cpu
, mte_tco_ro_reginfo
);
9802 define_arm_cp_regs(cpu
, mte_el0_cacheop_reginfo
);
9805 if (cpu_isar_feature(aa64_scxtnum
, cpu
)) {
9806 define_arm_cp_regs(cpu
, scxtnum_reginfo
);
9809 if (cpu_isar_feature(aa64_fgt
, cpu
)) {
9810 define_arm_cp_regs(cpu
, fgt_reginfo
);
9813 if (cpu_isar_feature(aa64_rme
, cpu
)) {
9814 define_arm_cp_regs(cpu
, rme_reginfo
);
9815 if (cpu_isar_feature(aa64_mte
, cpu
)) {
9816 define_arm_cp_regs(cpu
, rme_mte_reginfo
);
9820 if (cpu_isar_feature(aa64_nv2
, cpu
)) {
9821 define_arm_cp_regs(cpu
, nv2_reginfo
);
9825 if (cpu_isar_feature(any_predinv
, cpu
)) {
9826 define_arm_cp_regs(cpu
, predinv_reginfo
);
9829 if (cpu_isar_feature(any_ccidx
, cpu
)) {
9830 define_arm_cp_regs(cpu
, ccsidr2_reginfo
);
9833 #ifndef CONFIG_USER_ONLY
9835 * Register redirections and aliases must be done last,
9836 * after the registers from the other extensions have been defined.
9838 if (arm_feature(env
, ARM_FEATURE_EL2
) && cpu_isar_feature(aa64_vh
, cpu
)) {
9839 define_arm_vh_e2h_redirects_aliases(cpu
);
9845 * Private utility function for define_one_arm_cp_reg_with_opaque():
9846 * add a single reginfo struct to the hash table.
9848 static void add_cpreg_to_hashtable(ARMCPU
*cpu
, const ARMCPRegInfo
*r
,
9849 void *opaque
, CPState state
,
9850 CPSecureState secstate
,
9851 int crm
, int opc1
, int opc2
,
9854 CPUARMState
*env
= &cpu
->env
;
9857 bool is64
= r
->type
& ARM_CP_64BIT
;
9858 bool ns
= secstate
& ARM_CP_SECSTATE_NS
;
9864 case ARM_CP_STATE_AA32
:
9865 /* We assume it is a cp15 register if the .cp field is left unset. */
9866 if (cp
== 0 && r
->state
== ARM_CP_STATE_BOTH
) {
9869 key
= ENCODE_CP_REG(cp
, is64
, ns
, r
->crn
, crm
, opc1
, opc2
);
9871 case ARM_CP_STATE_AA64
:
9873 * To allow abbreviation of ARMCPRegInfo definitions, we treat
9874 * cp == 0 as equivalent to the value for "standard guest-visible
9875 * sysreg". STATE_BOTH definitions are also always "standard sysreg"
9876 * in their AArch64 view (the .cp value may be non-zero for the
9877 * benefit of the AArch32 view).
9879 if (cp
== 0 || r
->state
== ARM_CP_STATE_BOTH
) {
9880 cp
= CP_REG_ARM64_SYSREG_CP
;
9882 key
= ENCODE_AA64_CP_REG(cp
, r
->crn
, crm
, r
->opc0
, opc1
, opc2
);
9885 g_assert_not_reached();
9888 /* Overriding of an existing definition must be explicitly requested. */
9889 if (!(r
->type
& ARM_CP_OVERRIDE
)) {
9890 const ARMCPRegInfo
*oldreg
= get_arm_cp_reginfo(cpu
->cp_regs
, key
);
9892 assert(oldreg
->type
& ARM_CP_OVERRIDE
);
9897 * Eliminate registers that are not present because the EL is missing.
9898 * Doing this here makes it easier to put all registers for a given
9899 * feature into the same ARMCPRegInfo array and define them all at once.
9902 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
9904 * An EL2 register without EL2 but with EL3 is (usually) RES0.
9905 * See rule RJFFP in section D1.1.3 of DDI0487H.a.
9907 int min_el
= ctz32(r
->access
) / 2;
9908 if (min_el
== 2 && !arm_feature(env
, ARM_FEATURE_EL2
)) {
9909 if (r
->type
& ARM_CP_EL3_NO_EL2_UNDEF
) {
9912 make_const
= !(r
->type
& ARM_CP_EL3_NO_EL2_KEEP
);
9915 CPAccessRights max_el
= (arm_feature(env
, ARM_FEATURE_EL2
)
9917 if ((r
->access
& max_el
) == 0) {
9922 /* Combine cpreg and name into one allocation. */
9923 name_len
= strlen(name
) + 1;
9924 r2
= g_malloc(sizeof(*r2
) + name_len
);
9926 r2
->name
= memcpy(r2
+ 1, name
, name_len
);
9929 * Update fields to match the instantiation, overwiting wildcards
9930 * such as CP_ANY, ARM_CP_STATE_BOTH, or ARM_CP_SECSTATE_BOTH.
9937 r2
->secure
= secstate
;
9939 r2
->opaque
= opaque
;
9943 /* This should not have been a very special register to begin. */
9944 int old_special
= r2
->type
& ARM_CP_SPECIAL_MASK
;
9945 assert(old_special
== 0 || old_special
== ARM_CP_NOP
);
9947 * Set the special function to CONST, retaining the other flags.
9948 * This is important for e.g. ARM_CP_SVE so that we still
9949 * take the SVE trap if CPTR_EL3.EZ == 0.
9951 r2
->type
= (r2
->type
& ~ARM_CP_SPECIAL_MASK
) | ARM_CP_CONST
;
9953 * Usually, these registers become RES0, but there are a few
9954 * special cases like VPIDR_EL2 which have a constant non-zero
9955 * value with writes ignored.
9957 if (!(r
->type
& ARM_CP_EL3_NO_EL2_C_NZ
)) {
9961 * ARM_CP_CONST has precedence, so removing the callbacks and
9962 * offsets are not strictly necessary, but it is potentially
9963 * less confusing to debug later.
9967 r2
->raw_readfn
= NULL
;
9968 r2
->raw_writefn
= NULL
;
9970 r2
->fieldoffset
= 0;
9971 r2
->bank_fieldoffsets
[0] = 0;
9972 r2
->bank_fieldoffsets
[1] = 0;
9974 bool isbanked
= r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1];
9978 * Register is banked (using both entries in array).
9979 * Overwriting fieldoffset as the array is only used to define
9980 * banked registers but later only fieldoffset is used.
9982 r2
->fieldoffset
= r
->bank_fieldoffsets
[ns
];
9984 if (state
== ARM_CP_STATE_AA32
) {
9987 * If the register is banked then we don't need to migrate or
9988 * reset the 32-bit instance in certain cases:
9990 * 1) If the register has both 32-bit and 64-bit instances
9991 * then we can count on the 64-bit instance taking care
9992 * of the non-secure bank.
9993 * 2) If ARMv8 is enabled then we can count on a 64-bit
9994 * version taking care of the secure bank. This requires
9995 * that separate 32 and 64-bit definitions are provided.
9997 if ((r
->state
== ARM_CP_STATE_BOTH
&& ns
) ||
9998 (arm_feature(env
, ARM_FEATURE_V8
) && !ns
)) {
9999 r2
->type
|= ARM_CP_ALIAS
;
10001 } else if ((secstate
!= r
->secure
) && !ns
) {
10003 * The register is not banked so we only want to allow
10004 * migration of the non-secure instance.
10006 r2
->type
|= ARM_CP_ALIAS
;
10009 if (HOST_BIG_ENDIAN
&&
10010 r
->state
== ARM_CP_STATE_BOTH
&& r2
->fieldoffset
) {
10011 r2
->fieldoffset
+= sizeof(uint32_t);
10017 * By convention, for wildcarded registers only the first
10018 * entry is used for migration; the others are marked as
10019 * ALIAS so we don't try to transfer the register
10020 * multiple times. Special registers (ie NOP/WFI) are
10021 * never migratable and not even raw-accessible.
10023 if (r2
->type
& ARM_CP_SPECIAL_MASK
) {
10024 r2
->type
|= ARM_CP_NO_RAW
;
10026 if (((r
->crm
== CP_ANY
) && crm
!= 0) ||
10027 ((r
->opc1
== CP_ANY
) && opc1
!= 0) ||
10028 ((r
->opc2
== CP_ANY
) && opc2
!= 0)) {
10029 r2
->type
|= ARM_CP_ALIAS
| ARM_CP_NO_GDB
;
10033 * Check that raw accesses are either forbidden or handled. Note that
10034 * we can't assert this earlier because the setup of fieldoffset for
10035 * banked registers has to be done first.
10037 if (!(r2
->type
& ARM_CP_NO_RAW
)) {
10038 assert(!raw_accessors_invalid(r2
));
10041 g_hash_table_insert(cpu
->cp_regs
, (gpointer
)(uintptr_t)key
, r2
);
10045 void define_one_arm_cp_reg_with_opaque(ARMCPU
*cpu
,
10046 const ARMCPRegInfo
*r
, void *opaque
)
10049 * Define implementations of coprocessor registers.
10050 * We store these in a hashtable because typically
10051 * there are less than 150 registers in a space which
10052 * is 16*16*16*8*8 = 262144 in size.
10053 * Wildcarding is supported for the crm, opc1 and opc2 fields.
10054 * If a register is defined twice then the second definition is
10055 * used, so this can be used to define some generic registers and
10056 * then override them with implementation specific variations.
10057 * At least one of the original and the second definition should
10058 * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
10059 * against accidental use.
10061 * The state field defines whether the register is to be
10062 * visible in the AArch32 or AArch64 execution state. If the
10063 * state is set to ARM_CP_STATE_BOTH then we synthesise a
10064 * reginfo structure for the AArch32 view, which sees the lower
10065 * 32 bits of the 64 bit register.
10067 * Only registers visible in AArch64 may set r->opc0; opc0 cannot
10068 * be wildcarded. AArch64 registers are always considered to be 64
10069 * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of
10070 * the register, if any.
10072 int crm
, opc1
, opc2
;
10073 int crmmin
= (r
->crm
== CP_ANY
) ? 0 : r
->crm
;
10074 int crmmax
= (r
->crm
== CP_ANY
) ? 15 : r
->crm
;
10075 int opc1min
= (r
->opc1
== CP_ANY
) ? 0 : r
->opc1
;
10076 int opc1max
= (r
->opc1
== CP_ANY
) ? 7 : r
->opc1
;
10077 int opc2min
= (r
->opc2
== CP_ANY
) ? 0 : r
->opc2
;
10078 int opc2max
= (r
->opc2
== CP_ANY
) ? 7 : r
->opc2
;
10081 /* 64 bit registers have only CRm and Opc1 fields */
10082 assert(!((r
->type
& ARM_CP_64BIT
) && (r
->opc2
|| r
->crn
)));
10083 /* op0 only exists in the AArch64 encodings */
10084 assert((r
->state
!= ARM_CP_STATE_AA32
) || (r
->opc0
== 0));
10085 /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */
10086 assert((r
->state
!= ARM_CP_STATE_AA64
) || !(r
->type
& ARM_CP_64BIT
));
10088 * This API is only for Arm's system coprocessors (14 and 15) or
10089 * (M-profile or v7A-and-earlier only) for implementation defined
10090 * coprocessors in the range 0..7. Our decode assumes this, since
10091 * 8..13 can be used for other insns including VFP and Neon. See
10092 * valid_cp() in translate.c. Assert here that we haven't tried
10093 * to use an invalid coprocessor number.
10095 switch (r
->state
) {
10096 case ARM_CP_STATE_BOTH
:
10097 /* 0 has a special meaning, but otherwise the same rules as AA32. */
10102 case ARM_CP_STATE_AA32
:
10103 if (arm_feature(&cpu
->env
, ARM_FEATURE_V8
) &&
10104 !arm_feature(&cpu
->env
, ARM_FEATURE_M
)) {
10105 assert(r
->cp
>= 14 && r
->cp
<= 15);
10107 assert(r
->cp
< 8 || (r
->cp
>= 14 && r
->cp
<= 15));
10110 case ARM_CP_STATE_AA64
:
10111 assert(r
->cp
== 0 || r
->cp
== CP_REG_ARM64_SYSREG_CP
);
10114 g_assert_not_reached();
10117 * The AArch64 pseudocode CheckSystemAccess() specifies that op1
10118 * encodes a minimum access level for the register. We roll this
10119 * runtime check into our general permission check code, so check
10120 * here that the reginfo's specified permissions are strict enough
10121 * to encompass the generic architectural permission check.
10123 if (r
->state
!= ARM_CP_STATE_AA32
) {
10124 CPAccessRights mask
;
10127 /* min_EL EL1, but some accessible to EL0 via kernel ABI */
10128 mask
= PL0U_R
| PL1_RW
;
10148 /* min_EL EL1, secure mode only (we don't check the latter) */
10152 /* broken reginfo with out-of-range opc1 */
10153 g_assert_not_reached();
10155 /* assert our permissions are not too lax (stricter is fine) */
10156 assert((r
->access
& ~mask
) == 0);
10160 * Check that the register definition has enough info to handle
10161 * reads and writes if they are permitted.
10163 if (!(r
->type
& (ARM_CP_SPECIAL_MASK
| ARM_CP_CONST
))) {
10164 if (r
->access
& PL3_R
) {
10165 assert((r
->fieldoffset
||
10166 (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1])) ||
10169 if (r
->access
& PL3_W
) {
10170 assert((r
->fieldoffset
||
10171 (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1])) ||
10176 for (crm
= crmmin
; crm
<= crmmax
; crm
++) {
10177 for (opc1
= opc1min
; opc1
<= opc1max
; opc1
++) {
10178 for (opc2
= opc2min
; opc2
<= opc2max
; opc2
++) {
10179 for (state
= ARM_CP_STATE_AA32
;
10180 state
<= ARM_CP_STATE_AA64
; state
++) {
10181 if (r
->state
!= state
&& r
->state
!= ARM_CP_STATE_BOTH
) {
10184 if (state
== ARM_CP_STATE_AA32
) {
10186 * Under AArch32 CP registers can be common
10187 * (same for secure and non-secure world) or banked.
10191 switch (r
->secure
) {
10192 case ARM_CP_SECSTATE_S
:
10193 case ARM_CP_SECSTATE_NS
:
10194 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
10195 r
->secure
, crm
, opc1
, opc2
,
10198 case ARM_CP_SECSTATE_BOTH
:
10199 name
= g_strdup_printf("%s_S", r
->name
);
10200 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
10202 crm
, opc1
, opc2
, name
);
10204 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
10205 ARM_CP_SECSTATE_NS
,
10206 crm
, opc1
, opc2
, r
->name
);
10209 g_assert_not_reached();
10213 * AArch64 registers get mapped to non-secure instance
10216 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
10217 ARM_CP_SECSTATE_NS
,
10218 crm
, opc1
, opc2
, r
->name
);
10226 /* Define a whole list of registers */
10227 void define_arm_cp_regs_with_opaque_len(ARMCPU
*cpu
, const ARMCPRegInfo
*regs
,
10228 void *opaque
, size_t len
)
10231 for (i
= 0; i
< len
; ++i
) {
10232 define_one_arm_cp_reg_with_opaque(cpu
, regs
+ i
, opaque
);
10237 * Modify ARMCPRegInfo for access from userspace.
10239 * This is a data driven modification directed by
10240 * ARMCPRegUserSpaceInfo. All registers become ARM_CP_CONST as
10241 * user-space cannot alter any values and dynamic values pertaining to
10242 * execution state are hidden from user space view anyway.
10244 void modify_arm_cp_regs_with_len(ARMCPRegInfo
*regs
, size_t regs_len
,
10245 const ARMCPRegUserSpaceInfo
*mods
,
10248 for (size_t mi
= 0; mi
< mods_len
; ++mi
) {
10249 const ARMCPRegUserSpaceInfo
*m
= mods
+ mi
;
10250 GPatternSpec
*pat
= NULL
;
10253 pat
= g_pattern_spec_new(m
->name
);
10255 for (size_t ri
= 0; ri
< regs_len
; ++ri
) {
10256 ARMCPRegInfo
*r
= regs
+ ri
;
10258 if (pat
&& g_pattern_match_string(pat
, r
->name
)) {
10259 r
->type
= ARM_CP_CONST
;
10260 r
->access
= PL0U_R
;
10263 } else if (strcmp(r
->name
, m
->name
) == 0) {
10264 r
->type
= ARM_CP_CONST
;
10265 r
->access
= PL0U_R
;
10266 r
->resetvalue
&= m
->exported_bits
;
10267 r
->resetvalue
|= m
->fixed_bits
;
10272 g_pattern_spec_free(pat
);
10277 const ARMCPRegInfo
*get_arm_cp_reginfo(GHashTable
*cpregs
, uint32_t encoded_cp
)
10279 return g_hash_table_lookup(cpregs
, (gpointer
)(uintptr_t)encoded_cp
);
10282 void arm_cp_write_ignore(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
10285 /* Helper coprocessor write function for write-ignore registers */
10288 uint64_t arm_cp_read_zero(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
10290 /* Helper coprocessor write function for read-as-zero registers */
10294 void arm_cp_reset_ignore(CPUARMState
*env
, const ARMCPRegInfo
*opaque
)
10296 /* Helper coprocessor reset function for do-nothing-on-reset registers */
10299 static int bad_mode_switch(CPUARMState
*env
, int mode
, CPSRWriteType write_type
)
10302 * Return true if it is not valid for us to switch to
10303 * this CPU mode (ie all the UNPREDICTABLE cases in
10304 * the ARM ARM CPSRWriteByInstr pseudocode).
10307 /* Changes to or from Hyp via MSR and CPS are illegal. */
10308 if (write_type
== CPSRWriteByInstr
&&
10309 ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_HYP
||
10310 mode
== ARM_CPU_MODE_HYP
)) {
10315 case ARM_CPU_MODE_USR
:
10317 case ARM_CPU_MODE_SYS
:
10318 case ARM_CPU_MODE_SVC
:
10319 case ARM_CPU_MODE_ABT
:
10320 case ARM_CPU_MODE_UND
:
10321 case ARM_CPU_MODE_IRQ
:
10322 case ARM_CPU_MODE_FIQ
:
10324 * Note that we don't implement the IMPDEF NSACR.RFR which in v7
10325 * allows FIQ mode to be Secure-only. (In v8 this doesn't exist.)
10328 * If HCR.TGE is set then changes from Monitor to NS PL1 via MSR
10329 * and CPS are treated as illegal mode changes.
10331 if (write_type
== CPSRWriteByInstr
&&
10332 (env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_MON
&&
10333 (arm_hcr_el2_eff(env
) & HCR_TGE
)) {
10337 case ARM_CPU_MODE_HYP
:
10338 return !arm_is_el2_enabled(env
) || arm_current_el(env
) < 2;
10339 case ARM_CPU_MODE_MON
:
10340 return arm_current_el(env
) < 3;
10346 uint32_t cpsr_read(CPUARMState
*env
)
10349 ZF
= (env
->ZF
== 0);
10350 return env
->uncached_cpsr
| (env
->NF
& 0x80000000) | (ZF
<< 30) |
10351 (env
->CF
<< 29) | ((env
->VF
& 0x80000000) >> 3) | (env
->QF
<< 27)
10352 | (env
->thumb
<< 5) | ((env
->condexec_bits
& 3) << 25)
10353 | ((env
->condexec_bits
& 0xfc) << 8)
10354 | (env
->GE
<< 16) | (env
->daif
& CPSR_AIF
);
10357 void cpsr_write(CPUARMState
*env
, uint32_t val
, uint32_t mask
,
10358 CPSRWriteType write_type
)
10360 uint32_t changed_daif
;
10361 bool rebuild_hflags
= (write_type
!= CPSRWriteRaw
) &&
10362 (mask
& (CPSR_M
| CPSR_E
| CPSR_IL
));
10364 if (mask
& CPSR_NZCV
) {
10365 env
->ZF
= (~val
) & CPSR_Z
;
10367 env
->CF
= (val
>> 29) & 1;
10368 env
->VF
= (val
<< 3) & 0x80000000;
10370 if (mask
& CPSR_Q
) {
10371 env
->QF
= ((val
& CPSR_Q
) != 0);
10373 if (mask
& CPSR_T
) {
10374 env
->thumb
= ((val
& CPSR_T
) != 0);
10376 if (mask
& CPSR_IT_0_1
) {
10377 env
->condexec_bits
&= ~3;
10378 env
->condexec_bits
|= (val
>> 25) & 3;
10380 if (mask
& CPSR_IT_2_7
) {
10381 env
->condexec_bits
&= 3;
10382 env
->condexec_bits
|= (val
>> 8) & 0xfc;
10384 if (mask
& CPSR_GE
) {
10385 env
->GE
= (val
>> 16) & 0xf;
10389 * In a V7 implementation that includes the security extensions but does
10390 * not include Virtualization Extensions the SCR.FW and SCR.AW bits control
10391 * whether non-secure software is allowed to change the CPSR_F and CPSR_A
10392 * bits respectively.
10394 * In a V8 implementation, it is permitted for privileged software to
10395 * change the CPSR A/F bits regardless of the SCR.AW/FW bits.
10397 if (write_type
!= CPSRWriteRaw
&& !arm_feature(env
, ARM_FEATURE_V8
) &&
10398 arm_feature(env
, ARM_FEATURE_EL3
) &&
10399 !arm_feature(env
, ARM_FEATURE_EL2
) &&
10400 !arm_is_secure(env
)) {
10402 changed_daif
= (env
->daif
^ val
) & mask
;
10404 if (changed_daif
& CPSR_A
) {
10406 * Check to see if we are allowed to change the masking of async
10407 * abort exceptions from a non-secure state.
10409 if (!(env
->cp15
.scr_el3
& SCR_AW
)) {
10410 qemu_log_mask(LOG_GUEST_ERROR
,
10411 "Ignoring attempt to switch CPSR_A flag from "
10412 "non-secure world with SCR.AW bit clear\n");
10417 if (changed_daif
& CPSR_F
) {
10419 * Check to see if we are allowed to change the masking of FIQ
10420 * exceptions from a non-secure state.
10422 if (!(env
->cp15
.scr_el3
& SCR_FW
)) {
10423 qemu_log_mask(LOG_GUEST_ERROR
,
10424 "Ignoring attempt to switch CPSR_F flag from "
10425 "non-secure world with SCR.FW bit clear\n");
10430 * Check whether non-maskable FIQ (NMFI) support is enabled.
10431 * If this bit is set software is not allowed to mask
10432 * FIQs, but is allowed to set CPSR_F to 0.
10434 if ((A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_NMFI
) &&
10436 qemu_log_mask(LOG_GUEST_ERROR
,
10437 "Ignoring attempt to enable CPSR_F flag "
10438 "(non-maskable FIQ [NMFI] support enabled)\n");
10444 env
->daif
&= ~(CPSR_AIF
& mask
);
10445 env
->daif
|= val
& CPSR_AIF
& mask
;
10447 if (write_type
!= CPSRWriteRaw
&&
10448 ((env
->uncached_cpsr
^ val
) & mask
& CPSR_M
)) {
10449 if ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_USR
) {
10451 * Note that we can only get here in USR mode if this is a
10452 * gdb stub write; for this case we follow the architectural
10453 * behaviour for guest writes in USR mode of ignoring an attempt
10454 * to switch mode. (Those are caught by translate.c for writes
10455 * triggered by guest instructions.)
10458 } else if (bad_mode_switch(env
, val
& CPSR_M
, write_type
)) {
10460 * Attempt to switch to an invalid mode: this is UNPREDICTABLE in
10461 * v7, and has defined behaviour in v8:
10462 * + leave CPSR.M untouched
10463 * + allow changes to the other CPSR fields
10465 * For user changes via the GDB stub, we don't set PSTATE.IL,
10466 * as this would be unnecessarily harsh for a user error.
10469 if (write_type
!= CPSRWriteByGDBStub
&&
10470 arm_feature(env
, ARM_FEATURE_V8
)) {
10474 qemu_log_mask(LOG_GUEST_ERROR
,
10475 "Illegal AArch32 mode switch attempt from %s to %s\n",
10476 aarch32_mode_name(env
->uncached_cpsr
),
10477 aarch32_mode_name(val
));
10479 qemu_log_mask(CPU_LOG_INT
, "%s %s to %s PC 0x%" PRIx32
"\n",
10480 write_type
== CPSRWriteExceptionReturn
?
10481 "Exception return from AArch32" :
10482 "AArch32 mode switch from",
10483 aarch32_mode_name(env
->uncached_cpsr
),
10484 aarch32_mode_name(val
), env
->regs
[15]);
10485 switch_mode(env
, val
& CPSR_M
);
10488 mask
&= ~CACHED_CPSR_BITS
;
10489 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~mask
) | (val
& mask
);
10490 if (tcg_enabled() && rebuild_hflags
) {
10491 arm_rebuild_hflags(env
);
10495 #ifdef CONFIG_USER_ONLY
10497 static void switch_mode(CPUARMState
*env
, int mode
)
10499 ARMCPU
*cpu
= env_archcpu(env
);
10501 if (mode
!= ARM_CPU_MODE_USR
) {
10502 cpu_abort(CPU(cpu
), "Tried to switch out of user mode\n");
10506 uint32_t arm_phys_excp_target_el(CPUState
*cs
, uint32_t excp_idx
,
10507 uint32_t cur_el
, bool secure
)
10512 void aarch64_sync_64_to_32(CPUARMState
*env
)
10514 g_assert_not_reached();
10519 static void switch_mode(CPUARMState
*env
, int mode
)
10524 old_mode
= env
->uncached_cpsr
& CPSR_M
;
10525 if (mode
== old_mode
) {
10529 if (old_mode
== ARM_CPU_MODE_FIQ
) {
10530 memcpy(env
->fiq_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
10531 memcpy(env
->regs
+ 8, env
->usr_regs
, 5 * sizeof(uint32_t));
10532 } else if (mode
== ARM_CPU_MODE_FIQ
) {
10533 memcpy(env
->usr_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
10534 memcpy(env
->regs
+ 8, env
->fiq_regs
, 5 * sizeof(uint32_t));
10537 i
= bank_number(old_mode
);
10538 env
->banked_r13
[i
] = env
->regs
[13];
10539 env
->banked_spsr
[i
] = env
->spsr
;
10541 i
= bank_number(mode
);
10542 env
->regs
[13] = env
->banked_r13
[i
];
10543 env
->spsr
= env
->banked_spsr
[i
];
10545 env
->banked_r14
[r14_bank_number(old_mode
)] = env
->regs
[14];
10546 env
->regs
[14] = env
->banked_r14
[r14_bank_number(mode
)];
10550 * Physical Interrupt Target EL Lookup Table
10552 * [ From ARM ARM section G1.13.4 (Table G1-15) ]
10554 * The below multi-dimensional table is used for looking up the target
10555 * exception level given numerous condition criteria. Specifically, the
10556 * target EL is based on SCR and HCR routing controls as well as the
10557 * currently executing EL and secure state.
10560 * target_el_table[2][2][2][2][2][4]
10561 * | | | | | +--- Current EL
10562 * | | | | +------ Non-secure(0)/Secure(1)
10563 * | | | +--------- HCR mask override
10564 * | | +------------ SCR exec state control
10565 * | +--------------- SCR mask override
10566 * +------------------ 32-bit(0)/64-bit(1) EL3
10568 * The table values are as such:
10570 * -1 = Cannot occur
10572 * The ARM ARM target EL table includes entries indicating that an "exception
10573 * is not taken". The two cases where this is applicable are:
10574 * 1) An exception is taken from EL3 but the SCR does not have the exception
10576 * 2) An exception is taken from EL2 but the HCR does not have the exception
10578 * In these two cases, the below table contain a target of EL1. This value is
10579 * returned as it is expected that the consumer of the table data will check
10580 * for "target EL >= current EL" to ensure the exception is not taken.
10584 * BIT IRQ IMO Non-secure Secure
10585 * EL3 FIQ RW FMO EL0 EL1 EL2 EL3 EL0 EL1 EL2 EL3
10587 static const int8_t target_el_table
[2][2][2][2][2][4] = {
10588 {{{{/* 0 0 0 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },},
10589 {/* 0 0 0 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},
10590 {{/* 0 0 1 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },},
10591 {/* 0 0 1 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},},
10592 {{{/* 0 1 0 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},
10593 {/* 0 1 0 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},
10594 {{/* 0 1 1 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},
10595 {/* 0 1 1 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},},},
10596 {{{{/* 1 0 0 0 */{ 1, 1, 2, -1 },{ 1, 1, -1, 1 },},
10597 {/* 1 0 0 1 */{ 2, 2, 2, -1 },{ 2, 2, -1, 1 },},},
10598 {{/* 1 0 1 0 */{ 1, 1, 1, -1 },{ 1, 1, 1, 1 },},
10599 {/* 1 0 1 1 */{ 2, 2, 2, -1 },{ 2, 2, 2, 1 },},},},
10600 {{{/* 1 1 0 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},
10601 {/* 1 1 0 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},},
10602 {{/* 1 1 1 0 */{ 3, 3, 3, -1 },{ 3, 3, 3, 3 },},
10603 {/* 1 1 1 1 */{ 3, 3, 3, -1 },{ 3, 3, 3, 3 },},},},},
10607 * Determine the target EL for physical exceptions
10609 uint32_t arm_phys_excp_target_el(CPUState
*cs
, uint32_t excp_idx
,
10610 uint32_t cur_el
, bool secure
)
10612 CPUARMState
*env
= cpu_env(cs
);
10617 /* Is the highest EL AArch64? */
10618 bool is64
= arm_feature(env
, ARM_FEATURE_AARCH64
);
10621 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
10622 rw
= ((env
->cp15
.scr_el3
& SCR_RW
) == SCR_RW
);
10625 * Either EL2 is the highest EL (and so the EL2 register width
10626 * is given by is64); or there is no EL2 or EL3, in which case
10627 * the value of 'rw' does not affect the table lookup anyway.
10632 hcr_el2
= arm_hcr_el2_eff(env
);
10633 switch (excp_idx
) {
10635 scr
= ((env
->cp15
.scr_el3
& SCR_IRQ
) == SCR_IRQ
);
10636 hcr
= hcr_el2
& HCR_IMO
;
10639 scr
= ((env
->cp15
.scr_el3
& SCR_FIQ
) == SCR_FIQ
);
10640 hcr
= hcr_el2
& HCR_FMO
;
10643 scr
= ((env
->cp15
.scr_el3
& SCR_EA
) == SCR_EA
);
10644 hcr
= hcr_el2
& HCR_AMO
;
10649 * For these purposes, TGE and AMO/IMO/FMO both force the
10650 * interrupt to EL2. Fold TGE into the bit extracted above.
10652 hcr
|= (hcr_el2
& HCR_TGE
) != 0;
10654 /* Perform a table-lookup for the target EL given the current state */
10655 target_el
= target_el_table
[is64
][scr
][rw
][hcr
][secure
][cur_el
];
10657 assert(target_el
> 0);
10662 void arm_log_exception(CPUState
*cs
)
10664 int idx
= cs
->exception_index
;
10666 if (qemu_loglevel_mask(CPU_LOG_INT
)) {
10667 const char *exc
= NULL
;
10668 static const char * const excnames
[] = {
10669 [EXCP_UDEF
] = "Undefined Instruction",
10670 [EXCP_SWI
] = "SVC",
10671 [EXCP_PREFETCH_ABORT
] = "Prefetch Abort",
10672 [EXCP_DATA_ABORT
] = "Data Abort",
10673 [EXCP_IRQ
] = "IRQ",
10674 [EXCP_FIQ
] = "FIQ",
10675 [EXCP_BKPT
] = "Breakpoint",
10676 [EXCP_EXCEPTION_EXIT
] = "QEMU v7M exception exit",
10677 [EXCP_KERNEL_TRAP
] = "QEMU intercept of kernel commpage",
10678 [EXCP_HVC
] = "Hypervisor Call",
10679 [EXCP_HYP_TRAP
] = "Hypervisor Trap",
10680 [EXCP_SMC
] = "Secure Monitor Call",
10681 [EXCP_VIRQ
] = "Virtual IRQ",
10682 [EXCP_VFIQ
] = "Virtual FIQ",
10683 [EXCP_SEMIHOST
] = "Semihosting call",
10684 [EXCP_NOCP
] = "v7M NOCP UsageFault",
10685 [EXCP_INVSTATE
] = "v7M INVSTATE UsageFault",
10686 [EXCP_STKOF
] = "v8M STKOF UsageFault",
10687 [EXCP_LAZYFP
] = "v7M exception during lazy FP stacking",
10688 [EXCP_LSERR
] = "v8M LSERR UsageFault",
10689 [EXCP_UNALIGNED
] = "v7M UNALIGNED UsageFault",
10690 [EXCP_DIVBYZERO
] = "v7M DIVBYZERO UsageFault",
10691 [EXCP_VSERR
] = "Virtual SERR",
10692 [EXCP_GPC
] = "Granule Protection Check",
10695 if (idx
>= 0 && idx
< ARRAY_SIZE(excnames
)) {
10696 exc
= excnames
[idx
];
10701 qemu_log_mask(CPU_LOG_INT
, "Taking exception %d [%s] on CPU %d\n",
10702 idx
, exc
, cs
->cpu_index
);
10707 * Function used to synchronize QEMU's AArch64 register set with AArch32
10708 * register set. This is necessary when switching between AArch32 and AArch64
10711 void aarch64_sync_32_to_64(CPUARMState
*env
)
10714 uint32_t mode
= env
->uncached_cpsr
& CPSR_M
;
10716 /* We can blanket copy R[0:7] to X[0:7] */
10717 for (i
= 0; i
< 8; i
++) {
10718 env
->xregs
[i
] = env
->regs
[i
];
10722 * Unless we are in FIQ mode, x8-x12 come from the user registers r8-r12.
10723 * Otherwise, they come from the banked user regs.
10725 if (mode
== ARM_CPU_MODE_FIQ
) {
10726 for (i
= 8; i
< 13; i
++) {
10727 env
->xregs
[i
] = env
->usr_regs
[i
- 8];
10730 for (i
= 8; i
< 13; i
++) {
10731 env
->xregs
[i
] = env
->regs
[i
];
10736 * Registers x13-x23 are the various mode SP and FP registers. Registers
10737 * r13 and r14 are only copied if we are in that mode, otherwise we copy
10738 * from the mode banked register.
10740 if (mode
== ARM_CPU_MODE_USR
|| mode
== ARM_CPU_MODE_SYS
) {
10741 env
->xregs
[13] = env
->regs
[13];
10742 env
->xregs
[14] = env
->regs
[14];
10744 env
->xregs
[13] = env
->banked_r13
[bank_number(ARM_CPU_MODE_USR
)];
10745 /* HYP is an exception in that it is copied from r14 */
10746 if (mode
== ARM_CPU_MODE_HYP
) {
10747 env
->xregs
[14] = env
->regs
[14];
10749 env
->xregs
[14] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_USR
)];
10753 if (mode
== ARM_CPU_MODE_HYP
) {
10754 env
->xregs
[15] = env
->regs
[13];
10756 env
->xregs
[15] = env
->banked_r13
[bank_number(ARM_CPU_MODE_HYP
)];
10759 if (mode
== ARM_CPU_MODE_IRQ
) {
10760 env
->xregs
[16] = env
->regs
[14];
10761 env
->xregs
[17] = env
->regs
[13];
10763 env
->xregs
[16] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_IRQ
)];
10764 env
->xregs
[17] = env
->banked_r13
[bank_number(ARM_CPU_MODE_IRQ
)];
10767 if (mode
== ARM_CPU_MODE_SVC
) {
10768 env
->xregs
[18] = env
->regs
[14];
10769 env
->xregs
[19] = env
->regs
[13];
10771 env
->xregs
[18] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_SVC
)];
10772 env
->xregs
[19] = env
->banked_r13
[bank_number(ARM_CPU_MODE_SVC
)];
10775 if (mode
== ARM_CPU_MODE_ABT
) {
10776 env
->xregs
[20] = env
->regs
[14];
10777 env
->xregs
[21] = env
->regs
[13];
10779 env
->xregs
[20] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_ABT
)];
10780 env
->xregs
[21] = env
->banked_r13
[bank_number(ARM_CPU_MODE_ABT
)];
10783 if (mode
== ARM_CPU_MODE_UND
) {
10784 env
->xregs
[22] = env
->regs
[14];
10785 env
->xregs
[23] = env
->regs
[13];
10787 env
->xregs
[22] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_UND
)];
10788 env
->xregs
[23] = env
->banked_r13
[bank_number(ARM_CPU_MODE_UND
)];
10792 * Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
10793 * mode, then we can copy from r8-r14. Otherwise, we copy from the
10794 * FIQ bank for r8-r14.
10796 if (mode
== ARM_CPU_MODE_FIQ
) {
10797 for (i
= 24; i
< 31; i
++) {
10798 env
->xregs
[i
] = env
->regs
[i
- 16]; /* X[24:30] <- R[8:14] */
10801 for (i
= 24; i
< 29; i
++) {
10802 env
->xregs
[i
] = env
->fiq_regs
[i
- 24];
10804 env
->xregs
[29] = env
->banked_r13
[bank_number(ARM_CPU_MODE_FIQ
)];
10805 env
->xregs
[30] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_FIQ
)];
10808 env
->pc
= env
->regs
[15];
10812 * Function used to synchronize QEMU's AArch32 register set with AArch64
10813 * register set. This is necessary when switching between AArch32 and AArch64
10816 void aarch64_sync_64_to_32(CPUARMState
*env
)
10819 uint32_t mode
= env
->uncached_cpsr
& CPSR_M
;
10821 /* We can blanket copy X[0:7] to R[0:7] */
10822 for (i
= 0; i
< 8; i
++) {
10823 env
->regs
[i
] = env
->xregs
[i
];
10827 * Unless we are in FIQ mode, r8-r12 come from the user registers x8-x12.
10828 * Otherwise, we copy x8-x12 into the banked user regs.
10830 if (mode
== ARM_CPU_MODE_FIQ
) {
10831 for (i
= 8; i
< 13; i
++) {
10832 env
->usr_regs
[i
- 8] = env
->xregs
[i
];
10835 for (i
= 8; i
< 13; i
++) {
10836 env
->regs
[i
] = env
->xregs
[i
];
10841 * Registers r13 & r14 depend on the current mode.
10842 * If we are in a given mode, we copy the corresponding x registers to r13
10843 * and r14. Otherwise, we copy the x register to the banked r13 and r14
10846 if (mode
== ARM_CPU_MODE_USR
|| mode
== ARM_CPU_MODE_SYS
) {
10847 env
->regs
[13] = env
->xregs
[13];
10848 env
->regs
[14] = env
->xregs
[14];
10850 env
->banked_r13
[bank_number(ARM_CPU_MODE_USR
)] = env
->xregs
[13];
10853 * HYP is an exception in that it does not have its own banked r14 but
10854 * shares the USR r14
10856 if (mode
== ARM_CPU_MODE_HYP
) {
10857 env
->regs
[14] = env
->xregs
[14];
10859 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_USR
)] = env
->xregs
[14];
10863 if (mode
== ARM_CPU_MODE_HYP
) {
10864 env
->regs
[13] = env
->xregs
[15];
10866 env
->banked_r13
[bank_number(ARM_CPU_MODE_HYP
)] = env
->xregs
[15];
10869 if (mode
== ARM_CPU_MODE_IRQ
) {
10870 env
->regs
[14] = env
->xregs
[16];
10871 env
->regs
[13] = env
->xregs
[17];
10873 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_IRQ
)] = env
->xregs
[16];
10874 env
->banked_r13
[bank_number(ARM_CPU_MODE_IRQ
)] = env
->xregs
[17];
10877 if (mode
== ARM_CPU_MODE_SVC
) {
10878 env
->regs
[14] = env
->xregs
[18];
10879 env
->regs
[13] = env
->xregs
[19];
10881 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_SVC
)] = env
->xregs
[18];
10882 env
->banked_r13
[bank_number(ARM_CPU_MODE_SVC
)] = env
->xregs
[19];
10885 if (mode
== ARM_CPU_MODE_ABT
) {
10886 env
->regs
[14] = env
->xregs
[20];
10887 env
->regs
[13] = env
->xregs
[21];
10889 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_ABT
)] = env
->xregs
[20];
10890 env
->banked_r13
[bank_number(ARM_CPU_MODE_ABT
)] = env
->xregs
[21];
10893 if (mode
== ARM_CPU_MODE_UND
) {
10894 env
->regs
[14] = env
->xregs
[22];
10895 env
->regs
[13] = env
->xregs
[23];
10897 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_UND
)] = env
->xregs
[22];
10898 env
->banked_r13
[bank_number(ARM_CPU_MODE_UND
)] = env
->xregs
[23];
10902 * Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
10903 * mode, then we can copy to r8-r14. Otherwise, we copy to the
10904 * FIQ bank for r8-r14.
10906 if (mode
== ARM_CPU_MODE_FIQ
) {
10907 for (i
= 24; i
< 31; i
++) {
10908 env
->regs
[i
- 16] = env
->xregs
[i
]; /* X[24:30] -> R[8:14] */
10911 for (i
= 24; i
< 29; i
++) {
10912 env
->fiq_regs
[i
- 24] = env
->xregs
[i
];
10914 env
->banked_r13
[bank_number(ARM_CPU_MODE_FIQ
)] = env
->xregs
[29];
10915 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_FIQ
)] = env
->xregs
[30];
10918 env
->regs
[15] = env
->pc
;
10921 static void take_aarch32_exception(CPUARMState
*env
, int new_mode
,
10922 uint32_t mask
, uint32_t offset
,
10927 /* Change the CPU state so as to actually take the exception. */
10928 switch_mode(env
, new_mode
);
10931 * For exceptions taken to AArch32 we must clear the SS bit in both
10932 * PSTATE and in the old-state value we save to SPSR_<mode>, so zero it now.
10934 env
->pstate
&= ~PSTATE_SS
;
10935 env
->spsr
= cpsr_read(env
);
10936 /* Clear IT bits. */
10937 env
->condexec_bits
= 0;
10938 /* Switch to the new mode, and to the correct instruction set. */
10939 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~CPSR_M
) | new_mode
;
10941 /* This must be after mode switching. */
10942 new_el
= arm_current_el(env
);
10944 /* Set new mode endianness */
10945 env
->uncached_cpsr
&= ~CPSR_E
;
10946 if (env
->cp15
.sctlr_el
[new_el
] & SCTLR_EE
) {
10947 env
->uncached_cpsr
|= CPSR_E
;
10949 /* J and IL must always be cleared for exception entry */
10950 env
->uncached_cpsr
&= ~(CPSR_IL
| CPSR_J
);
10953 if (cpu_isar_feature(aa32_ssbs
, env_archcpu(env
))) {
10954 if (env
->cp15
.sctlr_el
[new_el
] & SCTLR_DSSBS_32
) {
10955 env
->uncached_cpsr
|= CPSR_SSBS
;
10957 env
->uncached_cpsr
&= ~CPSR_SSBS
;
10961 if (new_mode
== ARM_CPU_MODE_HYP
) {
10962 env
->thumb
= (env
->cp15
.sctlr_el
[2] & SCTLR_TE
) != 0;
10963 env
->elr_el
[2] = env
->regs
[15];
10965 /* CPSR.PAN is normally preserved preserved unless... */
10966 if (cpu_isar_feature(aa32_pan
, env_archcpu(env
))) {
10969 if (!arm_is_secure_below_el3(env
)) {
10970 /* ... the target is EL3, from non-secure state. */
10971 env
->uncached_cpsr
&= ~CPSR_PAN
;
10974 /* ... the target is EL3, from secure state ... */
10977 /* ... the target is EL1 and SCTLR.SPAN is 0. */
10978 if (!(env
->cp15
.sctlr_el
[new_el
] & SCTLR_SPAN
)) {
10979 env
->uncached_cpsr
|= CPSR_PAN
;
10985 * this is a lie, as there was no c1_sys on V4T/V5, but who cares
10986 * and we should just guard the thumb mode on V4
10988 if (arm_feature(env
, ARM_FEATURE_V4T
)) {
10990 (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_TE
) != 0;
10992 env
->regs
[14] = env
->regs
[15] + offset
;
10994 env
->regs
[15] = newpc
;
10996 if (tcg_enabled()) {
10997 arm_rebuild_hflags(env
);
11001 static void arm_cpu_do_interrupt_aarch32_hyp(CPUState
*cs
)
11004 * Handle exception entry to Hyp mode; this is sufficiently
11005 * different to entry to other AArch32 modes that we handle it
11008 * The vector table entry used is always the 0x14 Hyp mode entry point,
11009 * unless this is an UNDEF/SVC/HVC/abort taken from Hyp to Hyp.
11010 * The offset applied to the preferred return address is always zero
11011 * (see DDI0487C.a section G1.12.3).
11012 * PSTATE A/I/F masks are set based only on the SCR.EA/IRQ/FIQ values.
11014 uint32_t addr
, mask
;
11015 ARMCPU
*cpu
= ARM_CPU(cs
);
11016 CPUARMState
*env
= &cpu
->env
;
11018 switch (cs
->exception_index
) {
11026 /* Fall through to prefetch abort. */
11027 case EXCP_PREFETCH_ABORT
:
11028 env
->cp15
.ifar_s
= env
->exception
.vaddress
;
11029 qemu_log_mask(CPU_LOG_INT
, "...with HIFAR 0x%x\n",
11030 (uint32_t)env
->exception
.vaddress
);
11033 case EXCP_DATA_ABORT
:
11034 env
->cp15
.dfar_s
= env
->exception
.vaddress
;
11035 qemu_log_mask(CPU_LOG_INT
, "...with HDFAR 0x%x\n",
11036 (uint32_t)env
->exception
.vaddress
);
11048 case EXCP_HYP_TRAP
:
11052 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
11055 if (cs
->exception_index
!= EXCP_IRQ
&& cs
->exception_index
!= EXCP_FIQ
) {
11056 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
11058 * QEMU syndrome values are v8-style. v7 has the IL bit
11059 * UNK/SBZP for "field not valid" cases, where v8 uses RES1.
11060 * If this is a v7 CPU, squash the IL bit in those cases.
11062 if (cs
->exception_index
== EXCP_PREFETCH_ABORT
||
11063 (cs
->exception_index
== EXCP_DATA_ABORT
&&
11064 !(env
->exception
.syndrome
& ARM_EL_ISV
)) ||
11065 syn_get_ec(env
->exception
.syndrome
) == EC_UNCATEGORIZED
) {
11066 env
->exception
.syndrome
&= ~ARM_EL_IL
;
11069 env
->cp15
.esr_el
[2] = env
->exception
.syndrome
;
11072 if (arm_current_el(env
) != 2 && addr
< 0x14) {
11077 if (!(env
->cp15
.scr_el3
& SCR_EA
)) {
11080 if (!(env
->cp15
.scr_el3
& SCR_IRQ
)) {
11083 if (!(env
->cp15
.scr_el3
& SCR_FIQ
)) {
11087 addr
+= env
->cp15
.hvbar
;
11089 take_aarch32_exception(env
, ARM_CPU_MODE_HYP
, mask
, 0, addr
);
11092 static void arm_cpu_do_interrupt_aarch32(CPUState
*cs
)
11094 ARMCPU
*cpu
= ARM_CPU(cs
);
11095 CPUARMState
*env
= &cpu
->env
;
11102 /* If this is a debug exception we must update the DBGDSCR.MOE bits */
11103 switch (syn_get_ec(env
->exception
.syndrome
)) {
11104 case EC_BREAKPOINT
:
11105 case EC_BREAKPOINT_SAME_EL
:
11108 case EC_WATCHPOINT
:
11109 case EC_WATCHPOINT_SAME_EL
:
11115 case EC_VECTORCATCH
:
11124 env
->cp15
.mdscr_el1
= deposit64(env
->cp15
.mdscr_el1
, 2, 4, moe
);
11127 if (env
->exception
.target_el
== 2) {
11128 /* Debug exceptions are reported differently on AArch32 */
11129 switch (syn_get_ec(env
->exception
.syndrome
)) {
11130 case EC_BREAKPOINT
:
11131 case EC_BREAKPOINT_SAME_EL
:
11133 case EC_VECTORCATCH
:
11134 env
->exception
.syndrome
= syn_insn_abort(arm_current_el(env
) == 2,
11137 case EC_WATCHPOINT
:
11138 env
->exception
.syndrome
= syn_set_ec(env
->exception
.syndrome
,
11141 case EC_WATCHPOINT_SAME_EL
:
11142 env
->exception
.syndrome
= syn_set_ec(env
->exception
.syndrome
,
11143 EC_DATAABORT_SAME_EL
);
11146 arm_cpu_do_interrupt_aarch32_hyp(cs
);
11150 switch (cs
->exception_index
) {
11152 new_mode
= ARM_CPU_MODE_UND
;
11162 new_mode
= ARM_CPU_MODE_SVC
;
11165 /* The PC already points to the next instruction. */
11169 /* Fall through to prefetch abort. */
11170 case EXCP_PREFETCH_ABORT
:
11171 A32_BANKED_CURRENT_REG_SET(env
, ifsr
, env
->exception
.fsr
);
11172 A32_BANKED_CURRENT_REG_SET(env
, ifar
, env
->exception
.vaddress
);
11173 qemu_log_mask(CPU_LOG_INT
, "...with IFSR 0x%x IFAR 0x%x\n",
11174 env
->exception
.fsr
, (uint32_t)env
->exception
.vaddress
);
11175 new_mode
= ARM_CPU_MODE_ABT
;
11177 mask
= CPSR_A
| CPSR_I
;
11180 case EXCP_DATA_ABORT
:
11181 A32_BANKED_CURRENT_REG_SET(env
, dfsr
, env
->exception
.fsr
);
11182 A32_BANKED_CURRENT_REG_SET(env
, dfar
, env
->exception
.vaddress
);
11183 qemu_log_mask(CPU_LOG_INT
, "...with DFSR 0x%x DFAR 0x%x\n",
11184 env
->exception
.fsr
,
11185 (uint32_t)env
->exception
.vaddress
);
11186 new_mode
= ARM_CPU_MODE_ABT
;
11188 mask
= CPSR_A
| CPSR_I
;
11192 new_mode
= ARM_CPU_MODE_IRQ
;
11194 /* Disable IRQ and imprecise data aborts. */
11195 mask
= CPSR_A
| CPSR_I
;
11197 if (env
->cp15
.scr_el3
& SCR_IRQ
) {
11198 /* IRQ routed to monitor mode */
11199 new_mode
= ARM_CPU_MODE_MON
;
11204 new_mode
= ARM_CPU_MODE_FIQ
;
11206 /* Disable FIQ, IRQ and imprecise data aborts. */
11207 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
11208 if (env
->cp15
.scr_el3
& SCR_FIQ
) {
11209 /* FIQ routed to monitor mode */
11210 new_mode
= ARM_CPU_MODE_MON
;
11215 new_mode
= ARM_CPU_MODE_IRQ
;
11217 /* Disable IRQ and imprecise data aborts. */
11218 mask
= CPSR_A
| CPSR_I
;
11222 new_mode
= ARM_CPU_MODE_FIQ
;
11224 /* Disable FIQ, IRQ and imprecise data aborts. */
11225 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
11231 * Note that this is reported as a data abort, but the DFAR
11232 * has an UNKNOWN value. Construct the SError syndrome from
11233 * AET and ExT fields.
11235 ARMMMUFaultInfo fi
= { .type
= ARMFault_AsyncExternal
, };
11237 if (extended_addresses_enabled(env
)) {
11238 env
->exception
.fsr
= arm_fi_to_lfsc(&fi
);
11240 env
->exception
.fsr
= arm_fi_to_sfsc(&fi
);
11242 env
->exception
.fsr
|= env
->cp15
.vsesr_el2
& 0xd000;
11243 A32_BANKED_CURRENT_REG_SET(env
, dfsr
, env
->exception
.fsr
);
11244 qemu_log_mask(CPU_LOG_INT
, "...with IFSR 0x%x\n",
11245 env
->exception
.fsr
);
11247 new_mode
= ARM_CPU_MODE_ABT
;
11249 mask
= CPSR_A
| CPSR_I
;
11254 new_mode
= ARM_CPU_MODE_MON
;
11256 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
11260 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
11261 return; /* Never happens. Keep compiler happy. */
11264 if (new_mode
== ARM_CPU_MODE_MON
) {
11265 addr
+= env
->cp15
.mvbar
;
11266 } else if (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_V
) {
11267 /* High vectors. When enabled, base address cannot be remapped. */
11268 addr
+= 0xffff0000;
11271 * ARM v7 architectures provide a vector base address register to remap
11272 * the interrupt vector table.
11273 * This register is only followed in non-monitor mode, and is banked.
11274 * Note: only bits 31:5 are valid.
11276 addr
+= A32_BANKED_CURRENT_REG_GET(env
, vbar
);
11279 if ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_MON
) {
11280 env
->cp15
.scr_el3
&= ~SCR_NS
;
11283 take_aarch32_exception(env
, new_mode
, mask
, offset
, addr
);
11286 static int aarch64_regnum(CPUARMState
*env
, int aarch32_reg
)
11289 * Return the register number of the AArch64 view of the AArch32
11290 * register @aarch32_reg. The CPUARMState CPSR is assumed to still
11291 * be that of the AArch32 mode the exception came from.
11293 int mode
= env
->uncached_cpsr
& CPSR_M
;
11295 switch (aarch32_reg
) {
11297 return aarch32_reg
;
11299 return mode
== ARM_CPU_MODE_FIQ
? aarch32_reg
+ 16 : aarch32_reg
;
11302 case ARM_CPU_MODE_USR
:
11303 case ARM_CPU_MODE_SYS
:
11305 case ARM_CPU_MODE_HYP
:
11307 case ARM_CPU_MODE_IRQ
:
11309 case ARM_CPU_MODE_SVC
:
11311 case ARM_CPU_MODE_ABT
:
11313 case ARM_CPU_MODE_UND
:
11315 case ARM_CPU_MODE_FIQ
:
11318 g_assert_not_reached();
11322 case ARM_CPU_MODE_USR
:
11323 case ARM_CPU_MODE_SYS
:
11324 case ARM_CPU_MODE_HYP
:
11326 case ARM_CPU_MODE_IRQ
:
11328 case ARM_CPU_MODE_SVC
:
11330 case ARM_CPU_MODE_ABT
:
11332 case ARM_CPU_MODE_UND
:
11334 case ARM_CPU_MODE_FIQ
:
11337 g_assert_not_reached();
11342 g_assert_not_reached();
11346 static uint32_t cpsr_read_for_spsr_elx(CPUARMState
*env
)
11348 uint32_t ret
= cpsr_read(env
);
11350 /* Move DIT to the correct location for SPSR_ELx */
11351 if (ret
& CPSR_DIT
) {
11355 /* Merge PSTATE.SS into SPSR_ELx */
11356 ret
|= env
->pstate
& PSTATE_SS
;
11361 static bool syndrome_is_sync_extabt(uint32_t syndrome
)
11363 /* Return true if this syndrome value is a synchronous external abort */
11364 switch (syn_get_ec(syndrome
)) {
11366 case EC_INSNABORT_SAME_EL
:
11368 case EC_DATAABORT_SAME_EL
:
11369 /* Look at fault status code for all the synchronous ext abort cases */
11370 switch (syndrome
& 0x3f) {
11386 /* Handle exception entry to a target EL which is using AArch64 */
11387 static void arm_cpu_do_interrupt_aarch64(CPUState
*cs
)
11389 ARMCPU
*cpu
= ARM_CPU(cs
);
11390 CPUARMState
*env
= &cpu
->env
;
11391 unsigned int new_el
= env
->exception
.target_el
;
11392 target_ulong addr
= env
->cp15
.vbar_el
[new_el
];
11393 unsigned int new_mode
= aarch64_pstate_mode(new_el
, true);
11394 unsigned int old_mode
;
11395 unsigned int cur_el
= arm_current_el(env
);
11398 if (tcg_enabled()) {
11400 * Note that new_el can never be 0. If cur_el is 0, then
11401 * el0_a64 is is_a64(), else el0_a64 is ignored.
11403 aarch64_sve_change_el(env
, cur_el
, new_el
, is_a64(env
));
11406 if (cur_el
< new_el
) {
11408 * Entry vector offset depends on whether the implemented EL
11409 * immediately lower than the target level is using AArch32 or AArch64
11416 is_aa64
= (env
->cp15
.scr_el3
& SCR_RW
) != 0;
11419 hcr
= arm_hcr_el2_eff(env
);
11420 if ((hcr
& (HCR_E2H
| HCR_TGE
)) != (HCR_E2H
| HCR_TGE
)) {
11421 is_aa64
= (hcr
& HCR_RW
) != 0;
11426 is_aa64
= is_a64(env
);
11429 g_assert_not_reached();
11437 } else if (pstate_read(env
) & PSTATE_SP
) {
11441 switch (cs
->exception_index
) {
11443 qemu_log_mask(CPU_LOG_INT
, "...with MFAR 0x%" PRIx64
"\n",
11444 env
->cp15
.mfar_el3
);
11446 case EXCP_PREFETCH_ABORT
:
11447 case EXCP_DATA_ABORT
:
11449 * FEAT_DoubleFault allows synchronous external aborts taken to EL3
11450 * to be taken to the SError vector entrypoint.
11452 if (new_el
== 3 && (env
->cp15
.scr_el3
& SCR_EASE
) &&
11453 syndrome_is_sync_extabt(env
->exception
.syndrome
)) {
11456 env
->cp15
.far_el
[new_el
] = env
->exception
.vaddress
;
11457 qemu_log_mask(CPU_LOG_INT
, "...with FAR 0x%" PRIx64
"\n",
11458 env
->cp15
.far_el
[new_el
]);
11464 case EXCP_HYP_TRAP
:
11466 switch (syn_get_ec(env
->exception
.syndrome
)) {
11467 case EC_ADVSIMDFPACCESSTRAP
:
11469 * QEMU internal FP/SIMD syndromes from AArch32 include the
11470 * TA and coproc fields which are only exposed if the exception
11471 * is taken to AArch32 Hyp mode. Mask them out to get a valid
11472 * AArch64 format syndrome.
11474 env
->exception
.syndrome
&= ~MAKE_64BIT_MASK(0, 20);
11476 case EC_CP14RTTRAP
:
11477 case EC_CP15RTTRAP
:
11478 case EC_CP14DTTRAP
:
11480 * For a trap on AArch32 MRC/MCR/LDC/STC the Rt field is currently
11481 * the raw register field from the insn; when taking this to
11482 * AArch64 we must convert it to the AArch64 view of the register
11483 * number. Notice that we read a 4-bit AArch32 register number and
11484 * write back a 5-bit AArch64 one.
11486 rt
= extract32(env
->exception
.syndrome
, 5, 4);
11487 rt
= aarch64_regnum(env
, rt
);
11488 env
->exception
.syndrome
= deposit32(env
->exception
.syndrome
,
11491 case EC_CP15RRTTRAP
:
11492 case EC_CP14RRTTRAP
:
11493 /* Similarly for MRRC/MCRR traps for Rt and Rt2 fields */
11494 rt
= extract32(env
->exception
.syndrome
, 5, 4);
11495 rt
= aarch64_regnum(env
, rt
);
11496 env
->exception
.syndrome
= deposit32(env
->exception
.syndrome
,
11498 rt
= extract32(env
->exception
.syndrome
, 10, 4);
11499 rt
= aarch64_regnum(env
, rt
);
11500 env
->exception
.syndrome
= deposit32(env
->exception
.syndrome
,
11504 env
->cp15
.esr_el
[new_el
] = env
->exception
.syndrome
;
11516 /* Construct the SError syndrome from IDS and ISS fields. */
11517 env
->exception
.syndrome
= syn_serror(env
->cp15
.vsesr_el2
& 0x1ffffff);
11518 env
->cp15
.esr_el
[new_el
] = env
->exception
.syndrome
;
11521 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
11525 old_mode
= pstate_read(env
);
11526 aarch64_save_sp(env
, arm_current_el(env
));
11527 env
->elr_el
[new_el
] = env
->pc
;
11529 if (cur_el
== 1 && new_el
== 1) {
11530 uint64_t hcr
= arm_hcr_el2_eff(env
);
11531 if ((hcr
& (HCR_NV
| HCR_NV1
| HCR_NV2
)) == HCR_NV
||
11532 (hcr
& (HCR_NV
| HCR_NV2
)) == (HCR_NV
| HCR_NV2
)) {
11534 * FEAT_NV, FEAT_NV2 may need to report EL2 in the SPSR
11535 * by setting M[3:2] to 0b10.
11536 * If NV2 is disabled, change SPSR when NV,NV1 == 1,0 (I_ZJRNN)
11537 * If NV2 is enabled, change SPSR when NV is 1 (I_DBTLM)
11539 old_mode
= deposit32(old_mode
, 2, 2, 2);
11543 old_mode
= cpsr_read_for_spsr_elx(env
);
11544 env
->elr_el
[new_el
] = env
->regs
[15];
11546 aarch64_sync_32_to_64(env
);
11548 env
->condexec_bits
= 0;
11550 env
->banked_spsr
[aarch64_banked_spsr_index(new_el
)] = old_mode
;
11552 qemu_log_mask(CPU_LOG_INT
, "...with SPSR 0x%x\n", old_mode
);
11553 qemu_log_mask(CPU_LOG_INT
, "...with ELR 0x%" PRIx64
"\n",
11554 env
->elr_el
[new_el
]);
11556 if (cpu_isar_feature(aa64_pan
, cpu
)) {
11557 /* The value of PSTATE.PAN is normally preserved, except when ... */
11558 new_mode
|= old_mode
& PSTATE_PAN
;
11561 /* ... the target is EL2 with HCR_EL2.{E2H,TGE} == '11' ... */
11562 if ((arm_hcr_el2_eff(env
) & (HCR_E2H
| HCR_TGE
))
11563 != (HCR_E2H
| HCR_TGE
)) {
11568 /* ... the target is EL1 ... */
11569 /* ... and SCTLR_ELx.SPAN == 0, then set to 1. */
11570 if ((env
->cp15
.sctlr_el
[new_el
] & SCTLR_SPAN
) == 0) {
11571 new_mode
|= PSTATE_PAN
;
11576 if (cpu_isar_feature(aa64_mte
, cpu
)) {
11577 new_mode
|= PSTATE_TCO
;
11580 if (cpu_isar_feature(aa64_ssbs
, cpu
)) {
11581 if (env
->cp15
.sctlr_el
[new_el
] & SCTLR_DSSBS_64
) {
11582 new_mode
|= PSTATE_SSBS
;
11584 new_mode
&= ~PSTATE_SSBS
;
11588 pstate_write(env
, PSTATE_DAIF
| new_mode
);
11589 env
->aarch64
= true;
11590 aarch64_restore_sp(env
, new_el
);
11592 if (tcg_enabled()) {
11593 helper_rebuild_hflags_a64(env
, new_el
);
11598 qemu_log_mask(CPU_LOG_INT
, "...to EL%d PC 0x%" PRIx64
" PSTATE 0x%x\n",
11599 new_el
, env
->pc
, pstate_read(env
));
11603 * Do semihosting call and set the appropriate return value. All the
11604 * permission and validity checks have been done at translate time.
11606 * We only see semihosting exceptions in TCG only as they are not
11607 * trapped to the hypervisor in KVM.
11610 static void tcg_handle_semihosting(CPUState
*cs
)
11612 ARMCPU
*cpu
= ARM_CPU(cs
);
11613 CPUARMState
*env
= &cpu
->env
;
11616 qemu_log_mask(CPU_LOG_INT
,
11617 "...handling as semihosting call 0x%" PRIx64
"\n",
11619 do_common_semihosting(cs
);
11622 qemu_log_mask(CPU_LOG_INT
,
11623 "...handling as semihosting call 0x%x\n",
11625 do_common_semihosting(cs
);
11626 env
->regs
[15] += env
->thumb
? 2 : 4;
11632 * Handle a CPU exception for A and R profile CPUs.
11633 * Do any appropriate logging, handle PSCI calls, and then hand off
11634 * to the AArch64-entry or AArch32-entry function depending on the
11635 * target exception level's register width.
11637 * Note: this is used for both TCG (as the do_interrupt tcg op),
11638 * and KVM to re-inject guest debug exceptions, and to
11639 * inject a Synchronous-External-Abort.
11641 void arm_cpu_do_interrupt(CPUState
*cs
)
11643 ARMCPU
*cpu
= ARM_CPU(cs
);
11644 CPUARMState
*env
= &cpu
->env
;
11645 unsigned int new_el
= env
->exception
.target_el
;
11647 assert(!arm_feature(env
, ARM_FEATURE_M
));
11649 arm_log_exception(cs
);
11650 qemu_log_mask(CPU_LOG_INT
, "...from EL%d to EL%d\n", arm_current_el(env
),
11652 if (qemu_loglevel_mask(CPU_LOG_INT
)
11653 && !excp_is_internal(cs
->exception_index
)) {
11654 qemu_log_mask(CPU_LOG_INT
, "...with ESR 0x%x/0x%" PRIx32
"\n",
11655 syn_get_ec(env
->exception
.syndrome
),
11656 env
->exception
.syndrome
);
11659 if (tcg_enabled() && arm_is_psci_call(cpu
, cs
->exception_index
)) {
11660 arm_handle_psci_call(cpu
);
11661 qemu_log_mask(CPU_LOG_INT
, "...handled as PSCI call\n");
11666 * Semihosting semantics depend on the register width of the code
11667 * that caused the exception, not the target exception level, so
11668 * must be handled here.
11671 if (cs
->exception_index
== EXCP_SEMIHOST
) {
11672 tcg_handle_semihosting(cs
);
11678 * Hooks may change global state so BQL should be held, also the
11679 * BQL needs to be held for any modification of
11680 * cs->interrupt_request.
11682 g_assert(bql_locked());
11684 arm_call_pre_el_change_hook(cpu
);
11686 assert(!excp_is_internal(cs
->exception_index
));
11687 if (arm_el_is_aa64(env
, new_el
)) {
11688 arm_cpu_do_interrupt_aarch64(cs
);
11690 arm_cpu_do_interrupt_aarch32(cs
);
11693 arm_call_el_change_hook(cpu
);
11695 if (!kvm_enabled()) {
11696 cs
->interrupt_request
|= CPU_INTERRUPT_EXITTB
;
11699 #endif /* !CONFIG_USER_ONLY */
11701 uint64_t arm_sctlr(CPUARMState
*env
, int el
)
11703 /* Only EL0 needs to be adjusted for EL1&0 or EL2&0. */
11705 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, 0);
11706 el
= mmu_idx
== ARMMMUIdx_E20_0
? 2 : 1;
11708 return env
->cp15
.sctlr_el
[el
];
11711 int aa64_va_parameter_tbi(uint64_t tcr
, ARMMMUIdx mmu_idx
)
11713 if (regime_has_2_ranges(mmu_idx
)) {
11714 return extract64(tcr
, 37, 2);
11715 } else if (regime_is_stage2(mmu_idx
)) {
11716 return 0; /* VTCR_EL2 */
11718 /* Replicate the single TBI bit so we always have 2 bits. */
11719 return extract32(tcr
, 20, 1) * 3;
11723 int aa64_va_parameter_tbid(uint64_t tcr
, ARMMMUIdx mmu_idx
)
11725 if (regime_has_2_ranges(mmu_idx
)) {
11726 return extract64(tcr
, 51, 2);
11727 } else if (regime_is_stage2(mmu_idx
)) {
11728 return 0; /* VTCR_EL2 */
11730 /* Replicate the single TBID bit so we always have 2 bits. */
11731 return extract32(tcr
, 29, 1) * 3;
11735 int aa64_va_parameter_tcma(uint64_t tcr
, ARMMMUIdx mmu_idx
)
11737 if (regime_has_2_ranges(mmu_idx
)) {
11738 return extract64(tcr
, 57, 2);
11740 /* Replicate the single TCMA bit so we always have 2 bits. */
11741 return extract32(tcr
, 30, 1) * 3;
11745 static ARMGranuleSize
tg0_to_gran_size(int tg
)
11755 return GranInvalid
;
11759 static ARMGranuleSize
tg1_to_gran_size(int tg
)
11769 return GranInvalid
;
11773 static inline bool have4k(ARMCPU
*cpu
, bool stage2
)
11775 return stage2
? cpu_isar_feature(aa64_tgran4_2
, cpu
)
11776 : cpu_isar_feature(aa64_tgran4
, cpu
);
11779 static inline bool have16k(ARMCPU
*cpu
, bool stage2
)
11781 return stage2
? cpu_isar_feature(aa64_tgran16_2
, cpu
)
11782 : cpu_isar_feature(aa64_tgran16
, cpu
);
11785 static inline bool have64k(ARMCPU
*cpu
, bool stage2
)
11787 return stage2
? cpu_isar_feature(aa64_tgran64_2
, cpu
)
11788 : cpu_isar_feature(aa64_tgran64
, cpu
);
11791 static ARMGranuleSize
sanitize_gran_size(ARMCPU
*cpu
, ARMGranuleSize gran
,
11796 if (have4k(cpu
, stage2
)) {
11801 if (have16k(cpu
, stage2
)) {
11806 if (have64k(cpu
, stage2
)) {
11814 * If the guest selects a granule size that isn't implemented,
11815 * the architecture requires that we behave as if it selected one
11816 * that is (with an IMPDEF choice of which one to pick). We choose
11817 * to implement the smallest supported granule size.
11819 if (have4k(cpu
, stage2
)) {
11822 if (have16k(cpu
, stage2
)) {
11825 assert(have64k(cpu
, stage2
));
11829 ARMVAParameters
aa64_va_parameters(CPUARMState
*env
, uint64_t va
,
11830 ARMMMUIdx mmu_idx
, bool data
,
11833 uint64_t tcr
= regime_tcr(env
, mmu_idx
);
11834 bool epd
, hpd
, tsz_oob
, ds
, ha
, hd
;
11835 int select
, tsz
, tbi
, max_tsz
, min_tsz
, ps
, sh
;
11836 ARMGranuleSize gran
;
11837 ARMCPU
*cpu
= env_archcpu(env
);
11838 bool stage2
= regime_is_stage2(mmu_idx
);
11840 if (!regime_has_2_ranges(mmu_idx
)) {
11842 tsz
= extract32(tcr
, 0, 6);
11843 gran
= tg0_to_gran_size(extract32(tcr
, 14, 2));
11848 hpd
= extract32(tcr
, 24, 1);
11851 sh
= extract32(tcr
, 12, 2);
11852 ps
= extract32(tcr
, 16, 3);
11853 ha
= extract32(tcr
, 21, 1) && cpu_isar_feature(aa64_hafs
, cpu
);
11854 hd
= extract32(tcr
, 22, 1) && cpu_isar_feature(aa64_hdbs
, cpu
);
11855 ds
= extract64(tcr
, 32, 1);
11860 * Bit 55 is always between the two regions, and is canonical for
11861 * determining if address tagging is enabled.
11863 select
= extract64(va
, 55, 1);
11865 tsz
= extract32(tcr
, 0, 6);
11866 gran
= tg0_to_gran_size(extract32(tcr
, 14, 2));
11867 epd
= extract32(tcr
, 7, 1);
11868 sh
= extract32(tcr
, 12, 2);
11869 hpd
= extract64(tcr
, 41, 1);
11870 e0pd
= extract64(tcr
, 55, 1);
11872 tsz
= extract32(tcr
, 16, 6);
11873 gran
= tg1_to_gran_size(extract32(tcr
, 30, 2));
11874 epd
= extract32(tcr
, 23, 1);
11875 sh
= extract32(tcr
, 28, 2);
11876 hpd
= extract64(tcr
, 42, 1);
11877 e0pd
= extract64(tcr
, 56, 1);
11879 ps
= extract64(tcr
, 32, 3);
11880 ha
= extract64(tcr
, 39, 1) && cpu_isar_feature(aa64_hafs
, cpu
);
11881 hd
= extract64(tcr
, 40, 1) && cpu_isar_feature(aa64_hdbs
, cpu
);
11882 ds
= extract64(tcr
, 59, 1);
11884 if (e0pd
&& cpu_isar_feature(aa64_e0pd
, cpu
) &&
11885 regime_is_user(env
, mmu_idx
)) {
11890 gran
= sanitize_gran_size(cpu
, gran
, stage2
);
11892 if (cpu_isar_feature(aa64_st
, cpu
)) {
11893 max_tsz
= 48 - (gran
== Gran64K
);
11899 * DS is RES0 unless FEAT_LPA2 is supported for the given page size;
11900 * adjust the effective value of DS, as documented.
11903 if (gran
== Gran64K
) {
11904 if (cpu_isar_feature(aa64_lva
, cpu
)) {
11909 if (regime_is_stage2(mmu_idx
)) {
11910 if (gran
== Gran16K
) {
11911 ds
= cpu_isar_feature(aa64_tgran16_2_lpa2
, cpu
);
11913 ds
= cpu_isar_feature(aa64_tgran4_2_lpa2
, cpu
);
11916 if (gran
== Gran16K
) {
11917 ds
= cpu_isar_feature(aa64_tgran16_lpa2
, cpu
);
11919 ds
= cpu_isar_feature(aa64_tgran4_lpa2
, cpu
);
11927 if (stage2
&& el1_is_aa32
) {
11929 * For AArch32 EL1 the min txsz (and thus max IPA size) requirements
11930 * are loosened: a configured IPA of 40 bits is permitted even if
11931 * the implemented PA is less than that (and so a 40 bit IPA would
11932 * fault for an AArch64 EL1). See R_DTLMN.
11934 min_tsz
= MIN(min_tsz
, 24);
11937 if (tsz
> max_tsz
) {
11940 } else if (tsz
< min_tsz
) {
11947 /* Present TBI as a composite with TBID. */
11948 tbi
= aa64_va_parameter_tbi(tcr
, mmu_idx
);
11950 tbi
&= ~aa64_va_parameter_tbid(tcr
, mmu_idx
);
11952 tbi
= (tbi
>> select
) & 1;
11954 return (ARMVAParameters
) {
11962 .tsz_oob
= tsz_oob
,
11971 * Note that signed overflow is undefined in C. The following routines are
11972 * careful to use unsigned types where modulo arithmetic is required.
11973 * Failure to do so _will_ break on newer gcc.
11976 /* Signed saturating arithmetic. */
11978 /* Perform 16-bit signed saturating addition. */
11979 static inline uint16_t add16_sat(uint16_t a
, uint16_t b
)
11984 if (((res
^ a
) & 0x8000) && !((a
^ b
) & 0x8000)) {
11994 /* Perform 8-bit signed saturating addition. */
11995 static inline uint8_t add8_sat(uint8_t a
, uint8_t b
)
12000 if (((res
^ a
) & 0x80) && !((a
^ b
) & 0x80)) {
12010 /* Perform 16-bit signed saturating subtraction. */
12011 static inline uint16_t sub16_sat(uint16_t a
, uint16_t b
)
12016 if (((res
^ a
) & 0x8000) && ((a
^ b
) & 0x8000)) {
12026 /* Perform 8-bit signed saturating subtraction. */
12027 static inline uint8_t sub8_sat(uint8_t a
, uint8_t b
)
12032 if (((res
^ a
) & 0x80) && ((a
^ b
) & 0x80)) {
12042 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
12043 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
12044 #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
12045 #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
12048 #include "op_addsub.h"
12050 /* Unsigned saturating arithmetic. */
12051 static inline uint16_t add16_usat(uint16_t a
, uint16_t b
)
12061 static inline uint16_t sub16_usat(uint16_t a
, uint16_t b
)
12070 static inline uint8_t add8_usat(uint8_t a
, uint8_t b
)
12080 static inline uint8_t sub8_usat(uint8_t a
, uint8_t b
)
12089 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
12090 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
12091 #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
12092 #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
12095 #include "op_addsub.h"
12097 /* Signed modulo arithmetic. */
12098 #define SARITH16(a, b, n, op) do { \
12100 sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
12101 RESULT(sum, n, 16); \
12103 ge |= 3 << (n * 2); \
12106 #define SARITH8(a, b, n, op) do { \
12108 sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
12109 RESULT(sum, n, 8); \
12115 #define ADD16(a, b, n) SARITH16(a, b, n, +)
12116 #define SUB16(a, b, n) SARITH16(a, b, n, -)
12117 #define ADD8(a, b, n) SARITH8(a, b, n, +)
12118 #define SUB8(a, b, n) SARITH8(a, b, n, -)
12122 #include "op_addsub.h"
12124 /* Unsigned modulo arithmetic. */
12125 #define ADD16(a, b, n) do { \
12127 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
12128 RESULT(sum, n, 16); \
12129 if ((sum >> 16) == 1) \
12130 ge |= 3 << (n * 2); \
12133 #define ADD8(a, b, n) do { \
12135 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
12136 RESULT(sum, n, 8); \
12137 if ((sum >> 8) == 1) \
12141 #define SUB16(a, b, n) do { \
12143 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
12144 RESULT(sum, n, 16); \
12145 if ((sum >> 16) == 0) \
12146 ge |= 3 << (n * 2); \
12149 #define SUB8(a, b, n) do { \
12151 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
12152 RESULT(sum, n, 8); \
12153 if ((sum >> 8) == 0) \
12160 #include "op_addsub.h"
12162 /* Halved signed arithmetic. */
12163 #define ADD16(a, b, n) \
12164 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
12165 #define SUB16(a, b, n) \
12166 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
12167 #define ADD8(a, b, n) \
12168 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
12169 #define SUB8(a, b, n) \
12170 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
12173 #include "op_addsub.h"
12175 /* Halved unsigned arithmetic. */
12176 #define ADD16(a, b, n) \
12177 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
12178 #define SUB16(a, b, n) \
12179 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
12180 #define ADD8(a, b, n) \
12181 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
12182 #define SUB8(a, b, n) \
12183 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
12186 #include "op_addsub.h"
12188 static inline uint8_t do_usad(uint8_t a
, uint8_t b
)
12197 /* Unsigned sum of absolute byte differences. */
12198 uint32_t HELPER(usad8
)(uint32_t a
, uint32_t b
)
12201 sum
= do_usad(a
, b
);
12202 sum
+= do_usad(a
>> 8, b
>> 8);
12203 sum
+= do_usad(a
>> 16, b
>> 16);
12204 sum
+= do_usad(a
>> 24, b
>> 24);
12208 /* For ARMv6 SEL instruction. */
12209 uint32_t HELPER(sel_flags
)(uint32_t flags
, uint32_t a
, uint32_t b
)
12224 mask
|= 0xff000000;
12226 return (a
& mask
) | (b
& ~mask
);
12231 * The upper bytes of val (above the number specified by 'bytes') must have
12232 * been zeroed out by the caller.
12234 uint32_t HELPER(crc32
)(uint32_t acc
, uint32_t val
, uint32_t bytes
)
12238 stl_le_p(buf
, val
);
12240 /* zlib crc32 converts the accumulator and output to one's complement. */
12241 return crc32(acc
^ 0xffffffff, buf
, bytes
) ^ 0xffffffff;
12244 uint32_t HELPER(crc32c
)(uint32_t acc
, uint32_t val
, uint32_t bytes
)
12248 stl_le_p(buf
, val
);
12250 /* Linux crc32c converts the output to one's complement. */
12251 return crc32c(acc
, buf
, bytes
) ^ 0xffffffff;
12255 * Return the exception level to which FP-disabled exceptions should
12256 * be taken, or 0 if FP is enabled.
12258 int fp_exception_el(CPUARMState
*env
, int cur_el
)
12260 #ifndef CONFIG_USER_ONLY
12264 * CPACR and the CPTR registers don't exist before v6, so FP is
12265 * always accessible
12267 if (!arm_feature(env
, ARM_FEATURE_V6
)) {
12271 if (arm_feature(env
, ARM_FEATURE_M
)) {
12272 /* CPACR can cause a NOCP UsageFault taken to current security state */
12273 if (!v7m_cpacr_pass(env
, env
->v7m
.secure
, cur_el
!= 0)) {
12277 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
) && !env
->v7m
.secure
) {
12278 if (!extract32(env
->v7m
.nsacr
, 10, 1)) {
12279 /* FP insns cause a NOCP UsageFault taken to Secure */
12287 hcr_el2
= arm_hcr_el2_eff(env
);
12290 * The CPACR controls traps to EL1, or PL1 if we're 32 bit:
12291 * 0, 2 : trap EL0 and EL1/PL1 accesses
12292 * 1 : trap only EL0 accesses
12293 * 3 : trap no accesses
12294 * This register is ignored if E2H+TGE are both set.
12296 if ((hcr_el2
& (HCR_E2H
| HCR_TGE
)) != (HCR_E2H
| HCR_TGE
)) {
12297 int fpen
= FIELD_EX64(env
->cp15
.cpacr_el1
, CPACR_EL1
, FPEN
);
12307 /* Trap from Secure PL0 or PL1 to Secure PL1. */
12308 if (!arm_el_is_aa64(env
, 3)
12309 && (cur_el
== 3 || arm_is_secure_below_el3(env
))) {
12320 * The NSACR allows A-profile AArch32 EL3 and M-profile secure mode
12321 * to control non-secure access to the FPU. It doesn't have any
12322 * effect if EL3 is AArch64 or if EL3 doesn't exist at all.
12324 if ((arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
12325 cur_el
<= 2 && !arm_is_secure_below_el3(env
))) {
12326 if (!extract32(env
->cp15
.nsacr
, 10, 1)) {
12327 /* FP insns act as UNDEF */
12328 return cur_el
== 2 ? 2 : 1;
12333 * CPTR_EL2 is present in v7VE or v8, and changes format
12334 * with HCR_EL2.E2H (regardless of TGE).
12337 if (hcr_el2
& HCR_E2H
) {
12338 switch (FIELD_EX64(env
->cp15
.cptr_el
[2], CPTR_EL2
, FPEN
)) {
12340 if (cur_el
!= 0 || !(hcr_el2
& HCR_TGE
)) {
12348 } else if (arm_is_el2_enabled(env
)) {
12349 if (FIELD_EX64(env
->cp15
.cptr_el
[2], CPTR_EL2
, TFP
)) {
12355 /* CPTR_EL3 : present in v8 */
12356 if (FIELD_EX64(env
->cp15
.cptr_el
[3], CPTR_EL3
, TFP
)) {
12357 /* Trap all FP ops to EL3 */
12364 /* Return the exception level we're running at if this is our mmu_idx */
12365 int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx
)
12367 if (mmu_idx
& ARM_MMU_IDX_M
) {
12368 return mmu_idx
& ARM_MMU_IDX_M_PRIV
;
12372 case ARMMMUIdx_E10_0
:
12373 case ARMMMUIdx_E20_0
:
12375 case ARMMMUIdx_E10_1
:
12376 case ARMMMUIdx_E10_1_PAN
:
12379 case ARMMMUIdx_E20_2
:
12380 case ARMMMUIdx_E20_2_PAN
:
12385 g_assert_not_reached();
12390 ARMMMUIdx
arm_v7m_mmu_idx_for_secstate(CPUARMState
*env
, bool secstate
)
12392 g_assert_not_reached();
12396 ARMMMUIdx
arm_mmu_idx_el(CPUARMState
*env
, int el
)
12401 if (arm_feature(env
, ARM_FEATURE_M
)) {
12402 return arm_v7m_mmu_idx_for_secstate(env
, env
->v7m
.secure
);
12405 /* See ARM pseudo-function ELIsInHost. */
12408 hcr
= arm_hcr_el2_eff(env
);
12409 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
12410 idx
= ARMMMUIdx_E20_0
;
12412 idx
= ARMMMUIdx_E10_0
;
12416 if (arm_pan_enabled(env
)) {
12417 idx
= ARMMMUIdx_E10_1_PAN
;
12419 idx
= ARMMMUIdx_E10_1
;
12423 /* Note that TGE does not apply at EL2. */
12424 if (arm_hcr_el2_eff(env
) & HCR_E2H
) {
12425 if (arm_pan_enabled(env
)) {
12426 idx
= ARMMMUIdx_E20_2_PAN
;
12428 idx
= ARMMMUIdx_E20_2
;
12431 idx
= ARMMMUIdx_E2
;
12435 return ARMMMUIdx_E3
;
12437 g_assert_not_reached();
12443 ARMMMUIdx
arm_mmu_idx(CPUARMState
*env
)
12445 return arm_mmu_idx_el(env
, arm_current_el(env
));
12448 static bool mve_no_pred(CPUARMState
*env
)
12451 * Return true if there is definitely no predication of MVE
12452 * instructions by VPR or LTPSIZE. (Returning false even if there
12453 * isn't any predication is OK; generated code will just be
12455 * If the CPU does not implement MVE then this TB flag is always 0.
12457 * NOTE: if you change this logic, the "recalculate s->mve_no_pred"
12458 * logic in gen_update_fp_context() needs to be updated to match.
12460 * We do not include the effect of the ECI bits here -- they are
12461 * tracked in other TB flags. This simplifies the logic for
12462 * "when did we emit code that changes the MVE_NO_PRED TB flag
12463 * and thus need to end the TB?".
12465 if (cpu_isar_feature(aa32_mve
, env_archcpu(env
))) {
12468 if (env
->v7m
.vpr
) {
12471 if (env
->v7m
.ltpsize
< 4) {
12477 void cpu_get_tb_cpu_state(CPUARMState
*env
, vaddr
*pc
,
12478 uint64_t *cs_base
, uint32_t *pflags
)
12480 CPUARMTBFlags flags
;
12482 assert_hflags_rebuild_correctly(env
);
12483 flags
= env
->hflags
;
12485 if (EX_TBFLAG_ANY(flags
, AARCH64_STATE
)) {
12487 if (cpu_isar_feature(aa64_bti
, env_archcpu(env
))) {
12488 DP_TBFLAG_A64(flags
, BTYPE
, env
->btype
);
12491 *pc
= env
->regs
[15];
12493 if (arm_feature(env
, ARM_FEATURE_M
)) {
12494 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
) &&
12495 FIELD_EX32(env
->v7m
.fpccr
[M_REG_S
], V7M_FPCCR
, S
)
12496 != env
->v7m
.secure
) {
12497 DP_TBFLAG_M32(flags
, FPCCR_S_WRONG
, 1);
12500 if ((env
->v7m
.fpccr
[env
->v7m
.secure
] & R_V7M_FPCCR_ASPEN_MASK
) &&
12501 (!(env
->v7m
.control
[M_REG_S
] & R_V7M_CONTROL_FPCA_MASK
) ||
12502 (env
->v7m
.secure
&&
12503 !(env
->v7m
.control
[M_REG_S
] & R_V7M_CONTROL_SFPA_MASK
)))) {
12505 * ASPEN is set, but FPCA/SFPA indicate that there is no
12506 * active FP context; we must create a new FP context before
12507 * executing any FP insn.
12509 DP_TBFLAG_M32(flags
, NEW_FP_CTXT_NEEDED
, 1);
12512 bool is_secure
= env
->v7m
.fpccr
[M_REG_S
] & R_V7M_FPCCR_S_MASK
;
12513 if (env
->v7m
.fpccr
[is_secure
] & R_V7M_FPCCR_LSPACT_MASK
) {
12514 DP_TBFLAG_M32(flags
, LSPACT
, 1);
12517 if (mve_no_pred(env
)) {
12518 DP_TBFLAG_M32(flags
, MVE_NO_PRED
, 1);
12522 * Note that XSCALE_CPAR shares bits with VECSTRIDE.
12523 * Note that VECLEN+VECSTRIDE are RES0 for M-profile.
12525 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
12526 DP_TBFLAG_A32(flags
, XSCALE_CPAR
, env
->cp15
.c15_cpar
);
12528 DP_TBFLAG_A32(flags
, VECLEN
, env
->vfp
.vec_len
);
12529 DP_TBFLAG_A32(flags
, VECSTRIDE
, env
->vfp
.vec_stride
);
12531 if (env
->vfp
.xregs
[ARM_VFP_FPEXC
] & (1 << 30)) {
12532 DP_TBFLAG_A32(flags
, VFPEN
, 1);
12536 DP_TBFLAG_AM32(flags
, THUMB
, env
->thumb
);
12537 DP_TBFLAG_AM32(flags
, CONDEXEC
, env
->condexec_bits
);
12541 * The SS_ACTIVE and PSTATE_SS bits correspond to the state machine
12542 * states defined in the ARM ARM for software singlestep:
12543 * SS_ACTIVE PSTATE.SS State
12544 * 0 x Inactive (the TB flag for SS is always 0)
12545 * 1 0 Active-pending
12546 * 1 1 Active-not-pending
12547 * SS_ACTIVE is set in hflags; PSTATE__SS is computed every TB.
12549 if (EX_TBFLAG_ANY(flags
, SS_ACTIVE
) && (env
->pstate
& PSTATE_SS
)) {
12550 DP_TBFLAG_ANY(flags
, PSTATE__SS
, 1);
12553 *pflags
= flags
.flags
;
12554 *cs_base
= flags
.flags2
;
12557 #ifdef TARGET_AARCH64
12559 * The manual says that when SVE is enabled and VQ is widened the
12560 * implementation is allowed to zero the previously inaccessible
12561 * portion of the registers. The corollary to that is that when
12562 * SVE is enabled and VQ is narrowed we are also allowed to zero
12563 * the now inaccessible portion of the registers.
12565 * The intent of this is that no predicate bit beyond VQ is ever set.
12566 * Which means that some operations on predicate registers themselves
12567 * may operate on full uint64_t or even unrolled across the maximum
12568 * uint64_t[4]. Performing 4 bits of host arithmetic unconditionally
12569 * may well be cheaper than conditionals to restrict the operation
12570 * to the relevant portion of a uint16_t[16].
12572 void aarch64_sve_narrow_vq(CPUARMState
*env
, unsigned vq
)
12577 assert(vq
>= 1 && vq
<= ARM_MAX_VQ
);
12578 assert(vq
<= env_archcpu(env
)->sve_max_vq
);
12580 /* Zap the high bits of the zregs. */
12581 for (i
= 0; i
< 32; i
++) {
12582 memset(&env
->vfp
.zregs
[i
].d
[2 * vq
], 0, 16 * (ARM_MAX_VQ
- vq
));
12585 /* Zap the high bits of the pregs and ffr. */
12588 pmask
= ~(-1ULL << (16 * (vq
& 3)));
12590 for (j
= vq
/ 4; j
< ARM_MAX_VQ
/ 4; j
++) {
12591 for (i
= 0; i
< 17; ++i
) {
12592 env
->vfp
.pregs
[i
].p
[j
] &= pmask
;
12598 static uint32_t sve_vqm1_for_el_sm_ena(CPUARMState
*env
, int el
, bool sm
)
12603 exc_el
= sme_exception_el(env
, el
);
12605 exc_el
= sve_exception_el(env
, el
);
12608 return 0; /* disabled */
12610 return sve_vqm1_for_el_sm(env
, el
, sm
);
12614 * Notice a change in SVE vector size when changing EL.
12616 void aarch64_sve_change_el(CPUARMState
*env
, int old_el
,
12617 int new_el
, bool el0_a64
)
12619 ARMCPU
*cpu
= env_archcpu(env
);
12620 int old_len
, new_len
;
12621 bool old_a64
, new_a64
, sm
;
12623 /* Nothing to do if no SVE. */
12624 if (!cpu_isar_feature(aa64_sve
, cpu
)) {
12628 /* Nothing to do if FP is disabled in either EL. */
12629 if (fp_exception_el(env
, old_el
) || fp_exception_el(env
, new_el
)) {
12633 old_a64
= old_el
? arm_el_is_aa64(env
, old_el
) : el0_a64
;
12634 new_a64
= new_el
? arm_el_is_aa64(env
, new_el
) : el0_a64
;
12637 * Both AArch64.TakeException and AArch64.ExceptionReturn
12638 * invoke ResetSVEState when taking an exception from, or
12639 * returning to, AArch32 state when PSTATE.SM is enabled.
12641 sm
= FIELD_EX64(env
->svcr
, SVCR
, SM
);
12642 if (old_a64
!= new_a64
&& sm
) {
12643 arm_reset_sve_state(env
);
12648 * DDI0584A.d sec 3.2: "If SVE instructions are disabled or trapped
12649 * at ELx, or not available because the EL is in AArch32 state, then
12650 * for all purposes other than a direct read, the ZCR_ELx.LEN field
12651 * has an effective value of 0".
12653 * Consider EL2 (aa64, vq=4) -> EL0 (aa32) -> EL1 (aa64, vq=0).
12654 * If we ignore aa32 state, we would fail to see the vq4->vq0 transition
12655 * from EL2->EL1. Thus we go ahead and narrow when entering aa32 so that
12656 * we already have the correct register contents when encountering the
12657 * vq0->vq0 transition between EL0->EL1.
12659 old_len
= new_len
= 0;
12661 old_len
= sve_vqm1_for_el_sm_ena(env
, old_el
, sm
);
12664 new_len
= sve_vqm1_for_el_sm_ena(env
, new_el
, sm
);
12667 /* When changing vector length, clear inaccessible state. */
12668 if (new_len
< old_len
) {
12669 aarch64_sve_narrow_vq(env
, new_len
+ 1);
12674 #ifndef CONFIG_USER_ONLY
12675 ARMSecuritySpace
arm_security_space(CPUARMState
*env
)
12677 if (arm_feature(env
, ARM_FEATURE_M
)) {
12678 return arm_secure_to_space(env
->v7m
.secure
);
12682 * If EL3 is not supported then the secure state is implementation
12683 * defined, in which case QEMU defaults to non-secure.
12685 if (!arm_feature(env
, ARM_FEATURE_EL3
)) {
12686 return ARMSS_NonSecure
;
12689 /* Check for AArch64 EL3 or AArch32 Mon. */
12691 if (extract32(env
->pstate
, 2, 2) == 3) {
12692 if (cpu_isar_feature(aa64_rme
, env_archcpu(env
))) {
12695 return ARMSS_Secure
;
12699 if ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_MON
) {
12700 return ARMSS_Secure
;
12704 return arm_security_space_below_el3(env
);
12707 ARMSecuritySpace
arm_security_space_below_el3(CPUARMState
*env
)
12709 assert(!arm_feature(env
, ARM_FEATURE_M
));
12712 * If EL3 is not supported then the secure state is implementation
12713 * defined, in which case QEMU defaults to non-secure.
12715 if (!arm_feature(env
, ARM_FEATURE_EL3
)) {
12716 return ARMSS_NonSecure
;
12720 * Note NSE cannot be set without RME, and NSE & !NS is Reserved.
12721 * Ignoring NSE when !NS retains consistency without having to
12722 * modify other predicates.
12724 if (!(env
->cp15
.scr_el3
& SCR_NS
)) {
12725 return ARMSS_Secure
;
12726 } else if (env
->cp15
.scr_el3
& SCR_NSE
) {
12727 return ARMSS_Realm
;
12729 return ARMSS_NonSecure
;
12732 #endif /* !CONFIG_USER_ONLY */