4 * The code in this source file is derived from release 2a of the SoftFloat
5 * IEC/IEEE Floating-point Arithmetic Package. Those parts of the code (and
6 * some later contributions) are provided under that license, as detailed below.
7 * It has subsequently been modified by contributors to the QEMU Project,
8 * so some portions are provided under:
9 * the SoftFloat-2a license
13 * Any future contributions to this file after December 1st 2014 will be
14 * taken to be licensed under the Softfloat-2a license unless specifically
15 * indicated otherwise.
19 ===============================================================================
20 This C source fragment is part of the SoftFloat IEC/IEEE Floating-point
21 Arithmetic Package, Release 2a.
23 Written by John R. Hauser. This work was made possible in part by the
24 International Computer Science Institute, located at Suite 600, 1947 Center
25 Street, Berkeley, California 94704. Funding was partially provided by the
26 National Science Foundation under grant MIP-9311980. The original version
27 of this code was written as part of a project to build a fixed-point vector
28 processor in collaboration with the University of California at Berkeley,
29 overseen by Profs. Nelson Morgan and John Wawrzynek. More information
30 is available through the Web page `http://HTTP.CS.Berkeley.EDU/~jhauser/
31 arithmetic/SoftFloat.html'.
33 THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort
34 has been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT
35 TIMES RESULT IN INCORRECT BEHAVIOR. USE OF THIS SOFTWARE IS RESTRICTED TO
36 PERSONS AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ANY
37 AND ALL LOSSES, COSTS, OR OTHER PROBLEMS ARISING FROM ITS USE.
39 Derivative works are acceptable, even for commercial purposes, so long as
40 (1) they include prominent notice that the work is derivative, and (2) they
41 include prominent notice akin to these four paragraphs for those parts of
42 this code that are retained.
44 ===============================================================================
48 * Copyright (c) 2006, Fabrice Bellard
49 * All rights reserved.
51 * Redistribution and use in source and binary forms, with or without
52 * modification, are permitted provided that the following conditions are met:
54 * 1. Redistributions of source code must retain the above copyright notice,
55 * this list of conditions and the following disclaimer.
57 * 2. Redistributions in binary form must reproduce the above copyright notice,
58 * this list of conditions and the following disclaimer in the documentation
59 * and/or other materials provided with the distribution.
61 * 3. Neither the name of the copyright holder nor the names of its contributors
62 * may be used to endorse or promote products derived from this software without
63 * specific prior written permission.
65 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
66 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
67 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
68 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
69 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
70 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
71 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
72 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
73 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
74 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
75 * THE POSSIBILITY OF SUCH DAMAGE.
78 /* Portions of this work are licensed under the terms of the GNU GPL,
79 * version 2 or later. See the COPYING file in the top-level directory.
83 * Define whether architecture deviates from IEEE in not supporting
84 * signaling NaNs (so all NaNs are treated as quiet).
86 static inline bool no_signaling_nans(float_status *status)
88 #if defined(TARGET_XTENSA)
89 return status->no_signaling_nans;
95 /* Define how the architecture discriminates signaling NaNs.
96 * This done with the most significant bit of the fraction.
97 * In IEEE 754-1985 this was implementation defined, but in IEEE 754-2008
98 * the msb must be zero. MIPS is (so far) unique in supporting both the
99 * 2008 revision and backward compatibility with their original choice.
100 * Thus for MIPS we must make the choice at runtime.
102 static inline bool snan_bit_is_one(float_status *status)
104 #if defined(TARGET_MIPS)
105 return status->snan_bit_is_one;
106 #elif defined(TARGET_HPPA) || defined(TARGET_SH4)
113 /*----------------------------------------------------------------------------
114 | For the deconstructed floating-point with fraction FRAC, return true
115 | if the fraction represents a signalling NaN; otherwise false.
116 *----------------------------------------------------------------------------*/
118 static bool parts_is_snan_frac(uint64_t frac, float_status *status)
120 if (no_signaling_nans(status)) {
123 bool msb = extract64(frac, DECOMPOSED_BINARY_POINT - 1, 1);
124 return msb == snan_bit_is_one(status);
128 /*----------------------------------------------------------------------------
129 | The pattern for a default generated deconstructed floating-point NaN.
130 *----------------------------------------------------------------------------*/
132 static void parts64_default_nan(FloatParts64 *p, float_status *status)
137 #if defined(TARGET_SPARC) || defined(TARGET_M68K)
138 /* !snan_bit_is_one, set all bits */
139 frac = (1ULL << DECOMPOSED_BINARY_POINT) - 1;
140 #elif defined(TARGET_I386) || defined(TARGET_X86_64) \
141 || defined(TARGET_MICROBLAZE)
142 /* !snan_bit_is_one, set sign and msb */
143 frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1);
145 #elif defined(TARGET_HPPA)
146 /* snan_bit_is_one, set msb-1. */
147 frac = 1ULL << (DECOMPOSED_BINARY_POINT - 2);
148 #elif defined(TARGET_HEXAGON)
153 * This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V,
154 * S390, SH4, TriCore, and Xtensa. Our other supported targets,
155 * such CRIS, do not have floating-point.
157 if (snan_bit_is_one(status)) {
158 /* set all bits other than msb */
159 frac = (1ULL << (DECOMPOSED_BINARY_POINT - 1)) - 1;
162 frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1);
166 *p = (FloatParts64) {
167 .cls = float_class_qnan,
174 static void parts128_default_nan(FloatParts128 *p, float_status *status)
177 * Extrapolate from the choices made by parts64_default_nan to fill
178 * in the quad-floating format. If the low bit is set, assume we
179 * want to set all non-snan bits.
182 parts64_default_nan(&p64, status);
184 *p = (FloatParts128) {
185 .cls = float_class_qnan,
189 .frac_lo = -(p64.frac & 1)
193 /*----------------------------------------------------------------------------
194 | Returns a quiet NaN from a signalling NaN for the deconstructed
195 | floating-point parts.
196 *----------------------------------------------------------------------------*/
198 static uint64_t parts_silence_nan_frac(uint64_t frac, float_status *status)
200 g_assert(!no_signaling_nans(status));
202 /* The only snan_bit_is_one target without default_nan_mode is HPPA. */
203 if (snan_bit_is_one(status)) {
204 frac &= ~(1ULL << (DECOMPOSED_BINARY_POINT - 1));
205 frac |= 1ULL << (DECOMPOSED_BINARY_POINT - 2);
207 frac |= 1ULL << (DECOMPOSED_BINARY_POINT - 1);
212 static void parts64_silence_nan(FloatParts64 *p, float_status *status)
214 p->frac = parts_silence_nan_frac(p->frac, status);
215 p->cls = float_class_qnan;
218 static void parts128_silence_nan(FloatParts128 *p, float_status *status)
220 p->frac_hi = parts_silence_nan_frac(p->frac_hi, status);
221 p->cls = float_class_qnan;
224 /*----------------------------------------------------------------------------
225 | The pattern for a default generated extended double-precision NaN.
226 *----------------------------------------------------------------------------*/
227 floatx80 floatx80_default_nan(float_status *status)
231 /* None of the targets that have snan_bit_is_one use floatx80. */
232 assert(!snan_bit_is_one(status));
233 #if defined(TARGET_M68K)
234 r.low = UINT64_C(0xFFFFFFFFFFFFFFFF);
238 r.low = UINT64_C(0xC000000000000000);
244 /*----------------------------------------------------------------------------
245 | The pattern for a default generated extended double-precision inf.
246 *----------------------------------------------------------------------------*/
248 #define floatx80_infinity_high 0x7FFF
249 #if defined(TARGET_M68K)
250 #define floatx80_infinity_low UINT64_C(0x0000000000000000)
252 #define floatx80_infinity_low UINT64_C(0x8000000000000000)
255 const floatx80 floatx80_infinity
256 = make_floatx80_init(floatx80_infinity_high, floatx80_infinity_low);
258 /*----------------------------------------------------------------------------
259 | Returns 1 if the half-precision floating-point value `a' is a quiet
260 | NaN; otherwise returns 0.
261 *----------------------------------------------------------------------------*/
263 bool float16_is_quiet_nan(float16 a_, float_status *status)
265 if (no_signaling_nans(status)) {
266 return float16_is_any_nan(a_);
268 uint16_t a = float16_val(a_);
269 if (snan_bit_is_one(status)) {
270 return (((a >> 9) & 0x3F) == 0x3E) && (a & 0x1FF);
273 return ((a >> 9) & 0x3F) == 0x3F;
278 /*----------------------------------------------------------------------------
279 | Returns 1 if the bfloat16 value `a' is a quiet
280 | NaN; otherwise returns 0.
281 *----------------------------------------------------------------------------*/
283 bool bfloat16_is_quiet_nan(bfloat16 a_, float_status *status)
285 if (no_signaling_nans(status)) {
286 return bfloat16_is_any_nan(a_);
289 if (snan_bit_is_one(status)) {
290 return (((a >> 6) & 0x1FF) == 0x1FE) && (a & 0x3F);
292 return ((a >> 6) & 0x1FF) == 0x1FF;
297 /*----------------------------------------------------------------------------
298 | Returns 1 if the half-precision floating-point value `a' is a signaling
299 | NaN; otherwise returns 0.
300 *----------------------------------------------------------------------------*/
302 bool float16_is_signaling_nan(float16 a_, float_status *status)
304 if (no_signaling_nans(status)) {
307 uint16_t a = float16_val(a_);
308 if (snan_bit_is_one(status)) {
309 return ((a >> 9) & 0x3F) == 0x3F;
311 return (((a >> 9) & 0x3F) == 0x3E) && (a & 0x1FF);
316 /*----------------------------------------------------------------------------
317 | Returns 1 if the bfloat16 value `a' is a signaling
318 | NaN; otherwise returns 0.
319 *----------------------------------------------------------------------------*/
321 bool bfloat16_is_signaling_nan(bfloat16 a_, float_status *status)
323 if (no_signaling_nans(status)) {
327 if (snan_bit_is_one(status)) {
328 return ((a >> 6) & 0x1FF) == 0x1FF;
330 return (((a >> 6) & 0x1FF) == 0x1FE) && (a & 0x3F);
335 /*----------------------------------------------------------------------------
336 | Returns 1 if the single-precision floating-point value `a' is a quiet
337 | NaN; otherwise returns 0.
338 *----------------------------------------------------------------------------*/
340 bool float32_is_quiet_nan(float32 a_, float_status *status)
342 if (no_signaling_nans(status)) {
343 return float32_is_any_nan(a_);
345 uint32_t a = float32_val(a_);
346 if (snan_bit_is_one(status)) {
347 return (((a >> 22) & 0x1FF) == 0x1FE) && (a & 0x003FFFFF);
349 return ((uint32_t)(a << 1) >= 0xFF800000);
354 /*----------------------------------------------------------------------------
355 | Returns 1 if the single-precision floating-point value `a' is a signaling
356 | NaN; otherwise returns 0.
357 *----------------------------------------------------------------------------*/
359 bool float32_is_signaling_nan(float32 a_, float_status *status)
361 if (no_signaling_nans(status)) {
364 uint32_t a = float32_val(a_);
365 if (snan_bit_is_one(status)) {
366 return ((uint32_t)(a << 1) >= 0xFF800000);
368 return (((a >> 22) & 0x1FF) == 0x1FE) && (a & 0x003FFFFF);
373 /*----------------------------------------------------------------------------
374 | Select which NaN to propagate for a two-input operation.
375 | IEEE754 doesn't specify all the details of this, so the
376 | algorithm is target-specific.
377 | The routine is passed various bits of information about the
378 | two NaNs and should return 0 to select NaN a and 1 for NaN b.
379 | Note that signalling NaNs are always squashed to quiet NaNs
380 | by the caller, by calling floatXX_silence_nan() before
383 | aIsLargerSignificand is only valid if both a and b are NaNs
384 | of some kind, and is true if a has the larger significand,
385 | or if both a and b have the same significand but a is
386 | positive but b is negative. It is only needed for the x87
388 *----------------------------------------------------------------------------*/
390 static int pickNaN(FloatClass a_cls, FloatClass b_cls,
391 bool aIsLargerSignificand, float_status *status)
393 #if defined(TARGET_ARM) || defined(TARGET_MIPS) || defined(TARGET_HPPA) || \
394 defined(TARGET_LOONGARCH64) || defined(TARGET_S390X)
395 /* ARM mandated NaN propagation rules (see FPProcessNaNs()), take
397 * 1. A if it is signaling
398 * 2. B if it is signaling
401 * A signaling NaN is always quietened before returning it.
403 /* According to MIPS specifications, if one of the two operands is
404 * a sNaN, a new qNaN has to be generated. This is done in
405 * floatXX_silence_nan(). For qNaN inputs the specifications
406 * says: "When possible, this QNaN result is one of the operand QNaN
407 * values." In practice it seems that most implementations choose
408 * the first operand if both operands are qNaN. In short this gives
409 * the following rules:
410 * 1. A if it is signaling
411 * 2. B if it is signaling
414 * A signaling NaN is always silenced before returning it.
416 if (is_snan(a_cls)) {
418 } else if (is_snan(b_cls)) {
420 } else if (is_qnan(a_cls)) {
425 #elif defined(TARGET_PPC) || defined(TARGET_M68K)
426 /* PowerPC propagation rules:
427 * 1. A if it sNaN or qNaN
428 * 2. B if it sNaN or qNaN
429 * A signaling NaN is always silenced before returning it.
431 /* M68000 FAMILY PROGRAMMER'S REFERENCE MANUAL
432 * 3.4 FLOATING-POINT INSTRUCTION DETAILS
433 * If either operand, but not both operands, of an operation is a
434 * nonsignaling NaN, then that NaN is returned as the result. If both
435 * operands are nonsignaling NaNs, then the destination operand
436 * nonsignaling NaN is returned as the result.
437 * If either operand to an operation is a signaling NaN (SNaN), then the
438 * SNaN bit is set in the FPSR EXC byte. If the SNaN exception enable bit
439 * is set in the FPCR ENABLE byte, then the exception is taken and the
440 * destination is not modified. If the SNaN exception enable bit is not
441 * set, setting the SNaN bit in the operand to a one converts the SNaN to
442 * a nonsignaling NaN. The operation then continues as described in the
443 * preceding paragraph for nonsignaling NaNs.
450 #elif defined(TARGET_SPARC)
451 /* Prefer SNaN over QNaN, order B then A. */
452 if (is_snan(b_cls)) {
454 } else if (is_snan(a_cls)) {
456 } else if (is_qnan(b_cls)) {
461 #elif defined(TARGET_XTENSA)
463 * Xtensa has two NaN propagation modes.
464 * Which one is active is controlled by float_status::use_first_nan.
466 if (status->use_first_nan) {
480 /* This implements x87 NaN propagation rules:
481 * SNaN + QNaN => return the QNaN
482 * two SNaNs => return the one with the larger significand, silenced
483 * two QNaNs => return the one with the larger significand
484 * SNaN and a non-NaN => return the SNaN, silenced
485 * QNaN and a non-NaN => return the QNaN
487 * If we get down to comparing significands and they are the same,
488 * return the NaN with the positive sign bit (if any).
490 if (is_snan(a_cls)) {
491 if (is_snan(b_cls)) {
492 return aIsLargerSignificand ? 0 : 1;
494 return is_qnan(b_cls) ? 1 : 0;
495 } else if (is_qnan(a_cls)) {
496 if (is_snan(b_cls) || !is_qnan(b_cls)) {
499 return aIsLargerSignificand ? 0 : 1;
507 /*----------------------------------------------------------------------------
508 | Select which NaN to propagate for a three-input operation.
509 | For the moment we assume that no CPU needs the 'larger significand'
511 | Return values : 0 : a; 1 : b; 2 : c; 3 : default-NaN
512 *----------------------------------------------------------------------------*/
513 static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
514 bool infzero, float_status *status)
516 #if defined(TARGET_ARM)
517 /* For ARM, the (inf,zero,qnan) case sets InvalidOp and returns
520 if (infzero && is_qnan(c_cls)) {
521 float_raise(float_flag_invalid | float_flag_invalid_imz, status);
525 /* This looks different from the ARM ARM pseudocode, because the ARM ARM
526 * puts the operands to a fused mac operation (a*b)+c in the order c,a,b.
528 if (is_snan(c_cls)) {
530 } else if (is_snan(a_cls)) {
532 } else if (is_snan(b_cls)) {
534 } else if (is_qnan(c_cls)) {
536 } else if (is_qnan(a_cls)) {
541 #elif defined(TARGET_MIPS)
542 if (snan_bit_is_one(status)) {
544 * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan)
545 * case sets InvalidOp and returns the default NaN
548 float_raise(float_flag_invalid | float_flag_invalid_imz, status);
551 /* Prefer sNaN over qNaN, in the a, b, c order. */
552 if (is_snan(a_cls)) {
554 } else if (is_snan(b_cls)) {
556 } else if (is_snan(c_cls)) {
558 } else if (is_qnan(a_cls)) {
560 } else if (is_qnan(b_cls)) {
567 * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan)
568 * case sets InvalidOp and returns the input value 'c'
571 float_raise(float_flag_invalid | float_flag_invalid_imz, status);
574 /* Prefer sNaN over qNaN, in the c, a, b order. */
575 if (is_snan(c_cls)) {
577 } else if (is_snan(a_cls)) {
579 } else if (is_snan(b_cls)) {
581 } else if (is_qnan(c_cls)) {
583 } else if (is_qnan(a_cls)) {
589 #elif defined(TARGET_LOONGARCH64)
591 * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
592 * case sets InvalidOp and returns the input value 'c'
595 float_raise(float_flag_invalid | float_flag_invalid_imz, status);
598 /* Prefer sNaN over qNaN, in the c, a, b order. */
599 if (is_snan(c_cls)) {
601 } else if (is_snan(a_cls)) {
603 } else if (is_snan(b_cls)) {
605 } else if (is_qnan(c_cls)) {
607 } else if (is_qnan(a_cls)) {
612 #elif defined(TARGET_PPC)
613 /* For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer
614 * to return an input NaN if we have one (ie c) rather than generating
618 float_raise(float_flag_invalid | float_flag_invalid_imz, status);
622 /* If fRA is a NaN return it; otherwise if fRB is a NaN return it;
623 * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB
627 } else if (is_nan(c_cls)) {
632 #elif defined(TARGET_RISCV)
633 /* For RISC-V, InvalidOp is set when multiplicands are Inf and zero */
635 float_raise(float_flag_invalid | float_flag_invalid_imz, status);
637 return 3; /* default NaN */
638 #elif defined(TARGET_SPARC)
639 /* For (inf,0,nan) return c. */
641 float_raise(float_flag_invalid | float_flag_invalid_imz, status);
644 /* Prefer SNaN over QNaN, order C, B, A. */
645 if (is_snan(c_cls)) {
647 } else if (is_snan(b_cls)) {
649 } else if (is_snan(a_cls)) {
651 } else if (is_qnan(c_cls)) {
653 } else if (is_qnan(b_cls)) {
658 #elif defined(TARGET_XTENSA)
660 * For Xtensa, the (inf,zero,nan) case sets InvalidOp and returns
661 * an input NaN if we have one (ie c).
664 float_raise(float_flag_invalid | float_flag_invalid_imz, status);
667 if (status->use_first_nan) {
670 } else if (is_nan(b_cls)) {
678 } else if (is_nan(b_cls)) {
685 /* A default implementation: prefer a to b to c.
686 * This is unlikely to actually match any real implementation.
690 } else if (is_nan(b_cls)) {
698 /*----------------------------------------------------------------------------
699 | Returns 1 if the double-precision floating-point value `a' is a quiet
700 | NaN; otherwise returns 0.
701 *----------------------------------------------------------------------------*/
703 bool float64_is_quiet_nan(float64 a_, float_status *status)
705 if (no_signaling_nans(status)) {
706 return float64_is_any_nan(a_);
708 uint64_t a = float64_val(a_);
709 if (snan_bit_is_one(status)) {
710 return (((a >> 51) & 0xFFF) == 0xFFE)
711 && (a & 0x0007FFFFFFFFFFFFULL);
713 return ((a << 1) >= 0xFFF0000000000000ULL);
718 /*----------------------------------------------------------------------------
719 | Returns 1 if the double-precision floating-point value `a' is a signaling
720 | NaN; otherwise returns 0.
721 *----------------------------------------------------------------------------*/
723 bool float64_is_signaling_nan(float64 a_, float_status *status)
725 if (no_signaling_nans(status)) {
728 uint64_t a = float64_val(a_);
729 if (snan_bit_is_one(status)) {
730 return ((a << 1) >= 0xFFF0000000000000ULL);
732 return (((a >> 51) & 0xFFF) == 0xFFE)
733 && (a & UINT64_C(0x0007FFFFFFFFFFFF));
738 /*----------------------------------------------------------------------------
739 | Returns 1 if the extended double-precision floating-point value `a' is a
740 | quiet NaN; otherwise returns 0. This slightly differs from the same
741 | function for other types as floatx80 has an explicit bit.
742 *----------------------------------------------------------------------------*/
744 int floatx80_is_quiet_nan(floatx80 a, float_status *status)
746 if (no_signaling_nans(status)) {
747 return floatx80_is_any_nan(a);
749 if (snan_bit_is_one(status)) {
752 aLow = a.low & ~0x4000000000000000ULL;
753 return ((a.high & 0x7FFF) == 0x7FFF)
757 return ((a.high & 0x7FFF) == 0x7FFF)
758 && (UINT64_C(0x8000000000000000) <= ((uint64_t)(a.low << 1)));
763 /*----------------------------------------------------------------------------
764 | Returns 1 if the extended double-precision floating-point value `a' is a
765 | signaling NaN; otherwise returns 0. This slightly differs from the same
766 | function for other types as floatx80 has an explicit bit.
767 *----------------------------------------------------------------------------*/
769 int floatx80_is_signaling_nan(floatx80 a, float_status *status)
771 if (no_signaling_nans(status)) {
774 if (snan_bit_is_one(status)) {
775 return ((a.high & 0x7FFF) == 0x7FFF)
776 && ((a.low << 1) >= 0x8000000000000000ULL);
780 aLow = a.low & ~UINT64_C(0x4000000000000000);
781 return ((a.high & 0x7FFF) == 0x7FFF)
782 && (uint64_t)(aLow << 1)
788 /*----------------------------------------------------------------------------
789 | Returns a quiet NaN from a signalling NaN for the extended double-precision
790 | floating point value `a'.
791 *----------------------------------------------------------------------------*/
793 floatx80 floatx80_silence_nan(floatx80 a, float_status *status)
795 /* None of the targets that have snan_bit_is_one use floatx80. */
796 assert(!snan_bit_is_one(status));
797 a.low |= UINT64_C(0xC000000000000000);
801 /*----------------------------------------------------------------------------
802 | Takes two extended double-precision floating-point values `a' and `b', one
803 | of which is a NaN, and returns the appropriate NaN result. If either `a' or
804 | `b' is a signaling NaN, the invalid exception is raised.
805 *----------------------------------------------------------------------------*/
807 floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status)
809 bool aIsLargerSignificand;
810 FloatClass a_cls, b_cls;
812 /* This is not complete, but is good enough for pickNaN. */
813 a_cls = (!floatx80_is_any_nan(a)
815 : floatx80_is_signaling_nan(a, status)
818 b_cls = (!floatx80_is_any_nan(b)
820 : floatx80_is_signaling_nan(b, status)
824 if (is_snan(a_cls) || is_snan(b_cls)) {
825 float_raise(float_flag_invalid, status);
828 if (status->default_nan_mode) {
829 return floatx80_default_nan(status);
833 aIsLargerSignificand = 0;
834 } else if (b.low < a.low) {
835 aIsLargerSignificand = 1;
837 aIsLargerSignificand = (a.high < b.high) ? 1 : 0;
840 if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) {
841 if (is_snan(b_cls)) {
842 return floatx80_silence_nan(b, status);
846 if (is_snan(a_cls)) {
847 return floatx80_silence_nan(a, status);
853 /*----------------------------------------------------------------------------
854 | Returns 1 if the quadruple-precision floating-point value `a' is a quiet
855 | NaN; otherwise returns 0.
856 *----------------------------------------------------------------------------*/
858 bool float128_is_quiet_nan(float128 a, float_status *status)
860 if (no_signaling_nans(status)) {
861 return float128_is_any_nan(a);
863 if (snan_bit_is_one(status)) {
864 return (((a.high >> 47) & 0xFFFF) == 0xFFFE)
865 && (a.low || (a.high & 0x00007FFFFFFFFFFFULL));
867 return ((a.high << 1) >= 0xFFFF000000000000ULL)
868 && (a.low || (a.high & 0x0000FFFFFFFFFFFFULL));
873 /*----------------------------------------------------------------------------
874 | Returns 1 if the quadruple-precision floating-point value `a' is a
875 | signaling NaN; otherwise returns 0.
876 *----------------------------------------------------------------------------*/
878 bool float128_is_signaling_nan(float128 a, float_status *status)
880 if (no_signaling_nans(status)) {
883 if (snan_bit_is_one(status)) {
884 return ((a.high << 1) >= 0xFFFF000000000000ULL)
885 && (a.low || (a.high & 0x0000FFFFFFFFFFFFULL));
887 return (((a.high >> 47) & 0xFFFF) == 0xFFFE)
888 && (a.low || (a.high & UINT64_C(0x00007FFFFFFFFFFF)));