hw/arm/xlnx-zynqmp.c

   1 /*
   2  * Xilinx Zynq MPSoC emulation
   3  *
   4  * Copyright (C) 2015 Xilinx Inc
   5  * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License as published by the
   9  * Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  15  * for more details.
  16  */
  17
  18 #include "qemu/osdep.h"
  19 #include "qapi/error.h"
  20 #include "qemu/module.h"
  21 #include "cpu.h"
  22 #include "hw/arm/xlnx-zynqmp.h"
  23 #include "hw/intc/arm_gic_common.h"
  24 #include "hw/boards.h"
  25 #include "exec/address-spaces.h"
  26 #include "sysemu/kvm.h"
  27 #include "sysemu/sysemu.h"
  28 #include "kvm_arm.h"
  29
  30 #define GIC_NUM_SPI_INTR 160
  31
  32 #define ARM_PHYS_TIMER_PPI  30
  33 #define ARM_VIRT_TIMER_PPI  27
  34 #define ARM_HYP_TIMER_PPI   26
  35 #define ARM_SEC_TIMER_PPI   29
  36 #define GIC_MAINTENANCE_PPI 25
  37
  38 #define GEM_REVISION        0x40070106
  39
  40 #define GIC_BASE_ADDR       0xf9000000
  41 #define GIC_DIST_ADDR       0xf9010000
  42 #define GIC_CPU_ADDR        0xf9020000
  43 #define GIC_VIFACE_ADDR     0xf9040000
  44 #define GIC_VCPU_ADDR       0xf9060000
  45
  46 #define SATA_INTR           133
  47 #define SATA_ADDR           0xFD0C0000
  48 #define SATA_NUM_PORTS      2
  49
  50 #define QSPI_ADDR           0xff0f0000
  51 #define LQSPI_ADDR          0xc0000000
  52 #define QSPI_IRQ            15
  53 #define QSPI_DMA_ADDR       0xff0f0800
  54
  55 #define DP_ADDR             0xfd4a0000
  56 #define DP_IRQ              113
  57
  58 #define DPDMA_ADDR          0xfd4c0000
  59 #define DPDMA_IRQ           116
  60
  61 #define IPI_ADDR            0xFF300000
  62 #define IPI_IRQ             64
  63
  64 #define RTC_ADDR            0xffa60000
  65 #define RTC_IRQ             26
  66
  67 #define SDHCI_CAPABILITIES  0x280737ec6481 /* Datasheet: UG1085 (v1.7) */
  68
  69 static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = {
  70     0xFF0B0000, 0xFF0C0000, 0xFF0D0000, 0xFF0E0000,
  71 };
  72
  73 static const int gem_intr[XLNX_ZYNQMP_NUM_GEMS] = {
  74     57, 59, 61, 63,
  75 };
  76
  77 static const uint64_t uart_addr[XLNX_ZYNQMP_NUM_UARTS] = {
  78     0xFF000000, 0xFF010000,
  79 };
  80
  81 static const int uart_intr[XLNX_ZYNQMP_NUM_UARTS] = {
  82     21, 22,
  83 };
  84
  85 static const uint64_t can_addr[XLNX_ZYNQMP_NUM_CAN] = {
  86     0xFF060000, 0xFF070000,
  87 };
  88
  89 static const int can_intr[XLNX_ZYNQMP_NUM_CAN] = {
  90     23, 24,
  91 };
  92
  93 static const uint64_t sdhci_addr[XLNX_ZYNQMP_NUM_SDHCI] = {
  94     0xFF160000, 0xFF170000,
  95 };
  96
  97 static const int sdhci_intr[XLNX_ZYNQMP_NUM_SDHCI] = {
  98     48, 49,
  99 };
 100
 101 static const uint64_t spi_addr[XLNX_ZYNQMP_NUM_SPIS] = {
 102     0xFF040000, 0xFF050000,
 103 };
 104
 105 static const int spi_intr[XLNX_ZYNQMP_NUM_SPIS] = {
 106     19, 20,
 107 };
 108
 109 static const uint64_t gdma_ch_addr[XLNX_ZYNQMP_NUM_GDMA_CH] = {
 110     0xFD500000, 0xFD510000, 0xFD520000, 0xFD530000,
 111     0xFD540000, 0xFD550000, 0xFD560000, 0xFD570000
 112 };
 113
 114 static const int gdma_ch_intr[XLNX_ZYNQMP_NUM_GDMA_CH] = {
 115     124, 125, 126, 127, 128, 129, 130, 131
 116 };
 117
 118 static const uint64_t adma_ch_addr[XLNX_ZYNQMP_NUM_ADMA_CH] = {
 119     0xFFA80000, 0xFFA90000, 0xFFAA0000, 0xFFAB0000,
 120     0xFFAC0000, 0xFFAD0000, 0xFFAE0000, 0xFFAF0000
 121 };
 122
 123 static const int adma_ch_intr[XLNX_ZYNQMP_NUM_ADMA_CH] = {
 124     77, 78, 79, 80, 81, 82, 83, 84
 125 };
 126
 127 typedef struct XlnxZynqMPGICRegion {
 128     int region_index;
 129     uint32_t address;
 130     uint32_t offset;
 131     bool virt;
 132 } XlnxZynqMPGICRegion;
 133
 134 static const XlnxZynqMPGICRegion xlnx_zynqmp_gic_regions[] = {
 135     /* Distributor */
 136     {
 137         .region_index = 0,
 138         .address = GIC_DIST_ADDR,
 139         .offset = 0,
 140         .virt = false
 141     },
 142
 143     /* CPU interface */
 144     {
 145         .region_index = 1,
 146         .address = GIC_CPU_ADDR,
 147         .offset = 0,
 148         .virt = false
 149     },
 150     {
 151         .region_index = 1,
 152         .address = GIC_CPU_ADDR + 0x10000,
 153         .offset = 0x1000,
 154         .virt = false
 155     },
 156
 157     /* Virtual interface */
 158     {
 159         .region_index = 2,
 160         .address = GIC_VIFACE_ADDR,
 161         .offset = 0,
 162         .virt = true
 163     },
 164
 165     /* Virtual CPU interface */
 166     {
 167         .region_index = 3,
 168         .address = GIC_VCPU_ADDR,
 169         .offset = 0,
 170         .virt = true
 171     },
 172     {
 173         .region_index = 3,
 174         .address = GIC_VCPU_ADDR + 0x10000,
 175         .offset = 0x1000,
 176         .virt = true
 177     },
 178 };
 179
 180 static inline int arm_gic_ppi_index(int cpu_nr, int ppi_index)
 181 {
 182     return GIC_NUM_SPI_INTR + cpu_nr * GIC_INTERNAL + ppi_index;
 183 }
 184
 185 static void xlnx_zynqmp_create_rpu(MachineState *ms, XlnxZynqMPState *s,
 186                                    const char *boot_cpu, Error **errp)
 187 {
 188     int i;
 189     int num_rpus = MIN(ms->smp.cpus - XLNX_ZYNQMP_NUM_APU_CPUS,
 190                        XLNX_ZYNQMP_NUM_RPU_CPUS);
 191
 192     if (num_rpus <= 0) {
 193         /* Don't create rpu-cluster object if there's nothing to put in it */
 194         return;
 195     }
 196
 197     object_initialize_child(OBJECT(s), "rpu-cluster", &s->rpu_cluster,
 198                             TYPE_CPU_CLUSTER);
 199     qdev_prop_set_uint32(DEVICE(&s->rpu_cluster), "cluster-id", 1);
 200
 201     for (i = 0; i < num_rpus; i++) {
 202         const char *name;
 203
 204         object_initialize_child(OBJECT(&s->rpu_cluster), "rpu-cpu[*]",
 205                                 &s->rpu_cpu[i],
 206                                 ARM_CPU_TYPE_NAME("cortex-r5f"));
 207
 208         name = object_get_canonical_path_component(OBJECT(&s->rpu_cpu[i]));
 209         if (strcmp(name, boot_cpu)) {
 210             /* Secondary CPUs start in PSCI powered-down state */
 211             object_property_set_bool(OBJECT(&s->rpu_cpu[i]),
 212                                      "start-powered-off", true, &error_abort);
 213         } else {
 214             s->boot_cpu_ptr = &s->rpu_cpu[i];
 215         }
 216
 217         object_property_set_bool(OBJECT(&s->rpu_cpu[i]), "reset-hivecs", true,
 218                                  &error_abort);
 219         if (!qdev_realize(DEVICE(&s->rpu_cpu[i]), NULL, errp)) {
 220             return;
 221         }
 222     }
 223
 224     qdev_realize(DEVICE(&s->rpu_cluster), NULL, &error_fatal);
 225 }
 226
 227 static void xlnx_zynqmp_init(Object *obj)
 228 {
 229     MachineState *ms = MACHINE(qdev_get_machine());
 230     XlnxZynqMPState *s = XLNX_ZYNQMP(obj);
 231     int i;
 232     int num_apus = MIN(ms->smp.cpus, XLNX_ZYNQMP_NUM_APU_CPUS);
 233
 234     object_initialize_child(obj, "apu-cluster", &s->apu_cluster,
 235                             TYPE_CPU_CLUSTER);
 236     qdev_prop_set_uint32(DEVICE(&s->apu_cluster), "cluster-id", 0);
 237
 238     for (i = 0; i < num_apus; i++) {
 239         object_initialize_child(OBJECT(&s->apu_cluster), "apu-cpu[*]",
 240                                 &s->apu_cpu[i],
 241                                 ARM_CPU_TYPE_NAME("cortex-a53"));
 242     }
 243
 244     object_initialize_child(obj, "gic", &s->gic, gic_class_name());
 245
 246     for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) {
 247         object_initialize_child(obj, "gem[*]", &s->gem[i], TYPE_CADENCE_GEM);
 248     }
 249
 250     for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) {
 251         object_initialize_child(obj, "uart[*]", &s->uart[i],
 252                                 TYPE_CADENCE_UART);
 253     }
 254
 255     for (i = 0; i < XLNX_ZYNQMP_NUM_CAN; i++) {
 256         object_initialize_child(obj, "can[*]", &s->can[i],
 257                                 TYPE_XLNX_ZYNQMP_CAN);
 258     }
 259
 260     object_initialize_child(obj, "sata", &s->sata, TYPE_SYSBUS_AHCI);
 261
 262     for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) {
 263         object_initialize_child(obj, "sdhci[*]", &s->sdhci[i],
 264                                 TYPE_SYSBUS_SDHCI);
 265     }
 266
 267     for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) {
 268         object_initialize_child(obj, "spi[*]", &s->spi[i], TYPE_XILINX_SPIPS);
 269     }
 270
 271     object_initialize_child(obj, "qspi", &s->qspi, TYPE_XLNX_ZYNQMP_QSPIPS);
 272
 273     object_initialize_child(obj, "xxxdp", &s->dp, TYPE_XLNX_DP);
 274
 275     object_initialize_child(obj, "dp-dma", &s->dpdma, TYPE_XLNX_DPDMA);
 276
 277     object_initialize_child(obj, "ipi", &s->ipi, TYPE_XLNX_ZYNQMP_IPI);
 278
 279     object_initialize_child(obj, "rtc", &s->rtc, TYPE_XLNX_ZYNQMP_RTC);
 280
 281     for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) {
 282         object_initialize_child(obj, "gdma[*]", &s->gdma[i], TYPE_XLNX_ZDMA);
 283     }
 284
 285     for (i = 0; i < XLNX_ZYNQMP_NUM_ADMA_CH; i++) {
 286         object_initialize_child(obj, "adma[*]", &s->adma[i], TYPE_XLNX_ZDMA);
 287     }
 288
 289     object_initialize_child(obj, "qspi-dma", &s->qspi_dma, TYPE_XLNX_CSU_DMA);
 290 }
 291
 292 static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
 293 {
 294     MachineState *ms = MACHINE(qdev_get_machine());
 295     XlnxZynqMPState *s = XLNX_ZYNQMP(dev);
 296     MemoryRegion *system_memory = get_system_memory();
 297     uint8_t i;
 298     uint64_t ram_size;
 299     int num_apus = MIN(ms->smp.cpus, XLNX_ZYNQMP_NUM_APU_CPUS);
 300     const char *boot_cpu = s->boot_cpu ? s->boot_cpu : "apu-cpu[0]";
 301     ram_addr_t ddr_low_size, ddr_high_size;
 302     qemu_irq gic_spi[GIC_NUM_SPI_INTR];
 303     Error *err = NULL;
 304
 305     ram_size = memory_region_size(s->ddr_ram);
 306
 307     /*
 308      * Create the DDR Memory Regions. User friendly checks should happen at
 309      * the board level
 310      */
 311     if (ram_size > XLNX_ZYNQMP_MAX_LOW_RAM_SIZE) {
 312         /*
 313          * The RAM size is above the maximum available for the low DDR.
 314          * Create the high DDR memory region as well.
 315          */
 316         assert(ram_size <= XLNX_ZYNQMP_MAX_RAM_SIZE);
 317         ddr_low_size = XLNX_ZYNQMP_MAX_LOW_RAM_SIZE;
 318         ddr_high_size = ram_size - XLNX_ZYNQMP_MAX_LOW_RAM_SIZE;
 319
 320         memory_region_init_alias(&s->ddr_ram_high, OBJECT(dev),
 321                                  "ddr-ram-high", s->ddr_ram, ddr_low_size,
 322                                  ddr_high_size);
 323         memory_region_add_subregion(get_system_memory(),
 324                                     XLNX_ZYNQMP_HIGH_RAM_START,
 325                                     &s->ddr_ram_high);
 326     } else {
 327         /* RAM must be non-zero */
 328         assert(ram_size);
 329         ddr_low_size = ram_size;
 330     }
 331
 332     memory_region_init_alias(&s->ddr_ram_low, OBJECT(dev), "ddr-ram-low",
 333                              s->ddr_ram, 0, ddr_low_size);
 334     memory_region_add_subregion(get_system_memory(), 0, &s->ddr_ram_low);
 335
 336     /* Create the four OCM banks */
 337     for (i = 0; i < XLNX_ZYNQMP_NUM_OCM_BANKS; i++) {
 338         char *ocm_name = g_strdup_printf("zynqmp.ocm_ram_bank_%d", i);
 339
 340         memory_region_init_ram(&s->ocm_ram[i], NULL, ocm_name,
 341                                XLNX_ZYNQMP_OCM_RAM_SIZE, &error_fatal);
 342         memory_region_add_subregion(get_system_memory(),
 343                                     XLNX_ZYNQMP_OCM_RAM_0_ADDRESS +
 344                                         i * XLNX_ZYNQMP_OCM_RAM_SIZE,
 345                                     &s->ocm_ram[i]);
 346
 347         g_free(ocm_name);
 348     }
 349
 350     qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", GIC_NUM_SPI_INTR + 32);
 351     qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2);
 352     qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", num_apus);
 353     qdev_prop_set_bit(DEVICE(&s->gic), "has-security-extensions", s->secure);
 354     qdev_prop_set_bit(DEVICE(&s->gic),
 355                       "has-virtualization-extensions", s->virt);
 356
 357     qdev_realize(DEVICE(&s->apu_cluster), NULL, &error_fatal);
 358
 359     /* Realize APUs before realizing the GIC. KVM requires this.  */
 360     for (i = 0; i < num_apus; i++) {
 361         const char *name;
 362
 363         object_property_set_int(OBJECT(&s->apu_cpu[i]), "psci-conduit",
 364                                 QEMU_PSCI_CONDUIT_SMC, &error_abort);
 365
 366         name = object_get_canonical_path_component(OBJECT(&s->apu_cpu[i]));
 367         if (strcmp(name, boot_cpu)) {
 368             /* Secondary CPUs start in PSCI powered-down state */
 369             object_property_set_bool(OBJECT(&s->apu_cpu[i]),
 370                                      "start-powered-off", true, &error_abort);
 371         } else {
 372             s->boot_cpu_ptr = &s->apu_cpu[i];
 373         }
 374
 375         object_property_set_bool(OBJECT(&s->apu_cpu[i]), "has_el3", s->secure,
 376                                  NULL);
 377         object_property_set_bool(OBJECT(&s->apu_cpu[i]), "has_el2", s->virt,
 378                                  NULL);
 379         object_property_set_int(OBJECT(&s->apu_cpu[i]), "reset-cbar",
 380                                 GIC_BASE_ADDR, &error_abort);
 381         object_property_set_int(OBJECT(&s->apu_cpu[i]), "core-count",
 382                                 num_apus, &error_abort);
 383         if (!qdev_realize(DEVICE(&s->apu_cpu[i]), NULL, errp)) {
 384             return;
 385         }
 386     }
 387
 388     if (!sysbus_realize(SYS_BUS_DEVICE(&s->gic), errp)) {
 389         return;
 390     }
 391
 392     assert(ARRAY_SIZE(xlnx_zynqmp_gic_regions) == XLNX_ZYNQMP_GIC_REGIONS);
 393     for (i = 0; i < XLNX_ZYNQMP_GIC_REGIONS; i++) {
 394         SysBusDevice *gic = SYS_BUS_DEVICE(&s->gic);
 395         const XlnxZynqMPGICRegion *r = &xlnx_zynqmp_gic_regions[i];
 396         MemoryRegion *mr;
 397         uint32_t addr = r->address;
 398         int j;
 399
 400         if (r->virt && !s->virt) {
 401             continue;
 402         }
 403
 404         mr = sysbus_mmio_get_region(gic, r->region_index);
 405         for (j = 0; j < XLNX_ZYNQMP_GIC_ALIASES; j++) {
 406             MemoryRegion *alias = &s->gic_mr[i][j];
 407
 408             memory_region_init_alias(alias, OBJECT(s), "zynqmp-gic-alias", mr,
 409                                      r->offset, XLNX_ZYNQMP_GIC_REGION_SIZE);
 410             memory_region_add_subregion(system_memory, addr, alias);
 411
 412             addr += XLNX_ZYNQMP_GIC_REGION_SIZE;
 413         }
 414     }
 415
 416     for (i = 0; i < num_apus; i++) {
 417         qemu_irq irq;
 418
 419         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i,
 420                            qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]),
 421                                             ARM_CPU_IRQ));
 422         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus,
 423                            qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]),
 424                                             ARM_CPU_FIQ));
 425         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus * 2,
 426                            qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]),
 427                                             ARM_CPU_VIRQ));
 428         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus * 3,
 429                            qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]),
 430                                             ARM_CPU_VFIQ));
 431         irq = qdev_get_gpio_in(DEVICE(&s->gic),
 432                                arm_gic_ppi_index(i, ARM_PHYS_TIMER_PPI));
 433         qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_PHYS, irq);
 434         irq = qdev_get_gpio_in(DEVICE(&s->gic),
 435                                arm_gic_ppi_index(i, ARM_VIRT_TIMER_PPI));
 436         qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_VIRT, irq);
 437         irq = qdev_get_gpio_in(DEVICE(&s->gic),
 438                                arm_gic_ppi_index(i, ARM_HYP_TIMER_PPI));
 439         qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_HYP, irq);
 440         irq = qdev_get_gpio_in(DEVICE(&s->gic),
 441                                arm_gic_ppi_index(i, ARM_SEC_TIMER_PPI));
 442         qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_SEC, irq);
 443
 444         if (s->virt) {
 445             irq = qdev_get_gpio_in(DEVICE(&s->gic),
 446                                    arm_gic_ppi_index(i, GIC_MAINTENANCE_PPI));
 447             sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus * 4, irq);
 448         }
 449     }
 450
 451     xlnx_zynqmp_create_rpu(ms, s, boot_cpu, &err);
 452     if (err) {
 453         error_propagate(errp, err);
 454         return;
 455     }
 456
 457     if (!s->boot_cpu_ptr) {
 458         error_setg(errp, "ZynqMP Boot cpu %s not found", boot_cpu);
 459         return;
 460     }
 461
 462     for (i = 0; i < GIC_NUM_SPI_INTR; i++) {
 463         gic_spi[i] = qdev_get_gpio_in(DEVICE(&s->gic), i);
 464     }
 465
 466     for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) {
 467         NICInfo *nd = &nd_table[i];
 468
 469         /* FIXME use qdev NIC properties instead of nd_table[] */
 470         if (nd->used) {
 471             qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
 472             qdev_set_nic_properties(DEVICE(&s->gem[i]), nd);
 473         }
 474         object_property_set_int(OBJECT(&s->gem[i]), "revision", GEM_REVISION,
 475                                 &error_abort);
 476         object_property_set_int(OBJECT(&s->gem[i]), "phy-addr", 23,
 477                                 &error_abort);
 478         object_property_set_int(OBJECT(&s->gem[i]), "num-priority-queues", 2,
 479                                 &error_abort);
 480         if (!sysbus_realize(SYS_BUS_DEVICE(&s->gem[i]), errp)) {
 481             return;
 482         }
 483         sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem[i]), 0, gem_addr[i]);
 484         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem[i]), 0,
 485                            gic_spi[gem_intr[i]]);
 486     }
 487
 488     for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) {
 489         qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i));
 490         if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart[i]), errp)) {
 491             return;
 492         }
 493         sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, uart_addr[i]);
 494         sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
 495                            gic_spi[uart_intr[i]]);
 496     }
 497
 498     for (i = 0; i < XLNX_ZYNQMP_NUM_CAN; i++) {
 499         object_property_set_int(OBJECT(&s->can[i]), "ext_clk_freq",
 500                                 XLNX_ZYNQMP_CAN_REF_CLK, &error_abort);
 501
 502         object_property_set_link(OBJECT(&s->can[i]), "canbus",
 503                                  OBJECT(s->canbus[i]), &error_fatal);
 504
 505         sysbus_realize(SYS_BUS_DEVICE(&s->can[i]), &err);
 506         if (err) {
 507             error_propagate(errp, err);
 508             return;
 509         }
 510         sysbus_mmio_map(SYS_BUS_DEVICE(&s->can[i]), 0, can_addr[i]);
 511         sysbus_connect_irq(SYS_BUS_DEVICE(&s->can[i]), 0,
 512                            gic_spi[can_intr[i]]);
 513     }
 514
 515     object_property_set_int(OBJECT(&s->sata), "num-ports", SATA_NUM_PORTS,
 516                             &error_abort);
 517     if (!sysbus_realize(SYS_BUS_DEVICE(&s->sata), errp)) {
 518         return;
 519     }
 520
 521     sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, SATA_ADDR);
 522     sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, gic_spi[SATA_INTR]);
 523
 524     for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) {
 525         char *bus_name;
 526         SysBusDevice *sbd = SYS_BUS_DEVICE(&s->sdhci[i]);
 527         Object *sdhci = OBJECT(&s->sdhci[i]);
 528
 529         /*
 530          * Compatible with:
 531          * - SD Host Controller Specification Version 3.00
 532          * - SDIO Specification Version 3.0
 533          * - eMMC Specification Version 4.51
 534          */
 535         if (!object_property_set_uint(sdhci, "sd-spec-version", 3, errp)) {
 536             return;
 537         }
 538         if (!object_property_set_uint(sdhci, "capareg", SDHCI_CAPABILITIES,
 539                                       errp)) {
 540             return;
 541         }
 542         if (!object_property_set_uint(sdhci, "uhs", UHS_I, errp)) {
 543             return;
 544         }
 545         if (!sysbus_realize(SYS_BUS_DEVICE(sdhci), errp)) {
 546             return;
 547         }
 548         sysbus_mmio_map(sbd, 0, sdhci_addr[i]);
 549         sysbus_connect_irq(sbd, 0, gic_spi[sdhci_intr[i]]);
 550
 551         /* Alias controller SD bus to the SoC itself */
 552         bus_name = g_strdup_printf("sd-bus%d", i);
 553         object_property_add_alias(OBJECT(s), bus_name, sdhci, "sd-bus");
 554         g_free(bus_name);
 555     }
 556
 557     for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) {
 558         gchar *bus_name;
 559
 560         if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) {
 561             return;
 562         }
 563
 564         sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]);
 565         sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
 566                            gic_spi[spi_intr[i]]);
 567
 568         /* Alias controller SPI bus to the SoC itself */
 569         bus_name = g_strdup_printf("spi%d", i);
 570         object_property_add_alias(OBJECT(s), bus_name,
 571                                   OBJECT(&s->spi[i]), "spi0");
 572         g_free(bus_name);
 573     }
 574
 575     if (!sysbus_realize(SYS_BUS_DEVICE(&s->qspi), errp)) {
 576         return;
 577     }
 578     sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi), 0, QSPI_ADDR);
 579     sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi), 1, LQSPI_ADDR);
 580     sysbus_connect_irq(SYS_BUS_DEVICE(&s->qspi), 0, gic_spi[QSPI_IRQ]);
 581
 582     for (i = 0; i < XLNX_ZYNQMP_NUM_QSPI_BUS; i++) {
 583         gchar *bus_name;
 584         gchar *target_bus;
 585
 586         /* Alias controller SPI bus to the SoC itself */
 587         bus_name = g_strdup_printf("qspi%d", i);
 588         target_bus = g_strdup_printf("spi%d", i);
 589         object_property_add_alias(OBJECT(s), bus_name,
 590                                   OBJECT(&s->qspi), target_bus);
 591         g_free(bus_name);
 592         g_free(target_bus);
 593     }
 594
 595     if (!sysbus_realize(SYS_BUS_DEVICE(&s->dp), errp)) {
 596         return;
 597     }
 598     sysbus_mmio_map(SYS_BUS_DEVICE(&s->dp), 0, DP_ADDR);
 599     sysbus_connect_irq(SYS_BUS_DEVICE(&s->dp), 0, gic_spi[DP_IRQ]);
 600
 601     if (!sysbus_realize(SYS_BUS_DEVICE(&s->dpdma), errp)) {
 602         return;
 603     }
 604     object_property_set_link(OBJECT(&s->dp), "dpdma", OBJECT(&s->dpdma),
 605                              &error_abort);
 606     sysbus_mmio_map(SYS_BUS_DEVICE(&s->dpdma), 0, DPDMA_ADDR);
 607     sysbus_connect_irq(SYS_BUS_DEVICE(&s->dpdma), 0, gic_spi[DPDMA_IRQ]);
 608
 609     if (!sysbus_realize(SYS_BUS_DEVICE(&s->ipi), errp)) {
 610         return;
 611     }
 612     sysbus_mmio_map(SYS_BUS_DEVICE(&s->ipi), 0, IPI_ADDR);
 613     sysbus_connect_irq(SYS_BUS_DEVICE(&s->ipi), 0, gic_spi[IPI_IRQ]);
 614
 615     if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) {
 616         return;
 617     }
 618     sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, RTC_ADDR);
 619     sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, gic_spi[RTC_IRQ]);
 620
 621     for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) {
 622         if (!object_property_set_uint(OBJECT(&s->gdma[i]), "bus-width", 128,
 623                                       errp)) {
 624             return;
 625         }
 626         if (!sysbus_realize(SYS_BUS_DEVICE(&s->gdma[i]), errp)) {
 627             return;
 628         }
 629
 630         sysbus_mmio_map(SYS_BUS_DEVICE(&s->gdma[i]), 0, gdma_ch_addr[i]);
 631         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gdma[i]), 0,
 632                            gic_spi[gdma_ch_intr[i]]);
 633     }
 634
 635     for (i = 0; i < XLNX_ZYNQMP_NUM_ADMA_CH; i++) {
 636         if (!sysbus_realize(SYS_BUS_DEVICE(&s->adma[i]), errp)) {
 637             return;
 638         }
 639
 640         sysbus_mmio_map(SYS_BUS_DEVICE(&s->adma[i]), 0, adma_ch_addr[i]);
 641         sysbus_connect_irq(SYS_BUS_DEVICE(&s->adma[i]), 0,
 642                            gic_spi[adma_ch_intr[i]]);
 643     }
 644
 645     if (!sysbus_realize(SYS_BUS_DEVICE(&s->qspi_dma), errp)) {
 646         return;
 647     }
 648
 649     sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi_dma), 0, QSPI_DMA_ADDR);
 650     sysbus_connect_irq(SYS_BUS_DEVICE(&s->qspi_dma), 0, gic_spi[QSPI_IRQ]);
 651     object_property_set_link(OBJECT(&s->qspi), "stream-connected-dma",
 652                              OBJECT(&s->qspi_dma), errp);
 653 }
 654
 655 static Property xlnx_zynqmp_props[] = {
 656     DEFINE_PROP_STRING("boot-cpu", XlnxZynqMPState, boot_cpu),
 657     DEFINE_PROP_BOOL("secure", XlnxZynqMPState, secure, false),
 658     DEFINE_PROP_BOOL("virtualization", XlnxZynqMPState, virt, false),
 659     DEFINE_PROP_LINK("ddr-ram", XlnxZynqMPState, ddr_ram, TYPE_MEMORY_REGION,
 660                      MemoryRegion *),
 661     DEFINE_PROP_LINK("canbus0", XlnxZynqMPState, canbus[0], TYPE_CAN_BUS,
 662                      CanBusState *),
 663     DEFINE_PROP_LINK("canbus1", XlnxZynqMPState, canbus[1], TYPE_CAN_BUS,
 664                      CanBusState *),
 665     DEFINE_PROP_END_OF_LIST()
 666 };
 667
 668 static void xlnx_zynqmp_class_init(ObjectClass *oc, void *data)
 669 {
 670     DeviceClass *dc = DEVICE_CLASS(oc);
 671
 672     device_class_set_props(dc, xlnx_zynqmp_props);
 673     dc->realize = xlnx_zynqmp_realize;
 674     /* Reason: Uses serial_hds in realize function, thus can't be used twice */
 675     dc->user_creatable = false;
 676 }
 677
 678 static const TypeInfo xlnx_zynqmp_type_info = {
 679     .name = TYPE_XLNX_ZYNQMP,
 680     .parent = TYPE_DEVICE,
 681     .instance_size = sizeof(XlnxZynqMPState),
 682     .instance_init = xlnx_zynqmp_init,
 683     .class_init = xlnx_zynqmp_class_init,
 684 };
 685
 686 static void xlnx_zynqmp_register_types(void)
 687 {
 688     type_register_static(&xlnx_zynqmp_type_info);
 689 }
 690
 691 type_init(xlnx_zynqmp_register_types)