2 * ARM page table walking.
4 * This code is licensed under the GNU GPL v2 or later.
6 * SPDX-License-Identifier: GPL-2.0-or-later
9 #include "qemu/osdep.h"
11 #include "qemu/range.h"
12 #include "qemu/main-loop.h"
13 #include "exec/exec-all.h"
15 #include "internals.h"
18 # include "tcg/oversized-guest.h"
21 typedef struct S1Translate
{
23 * in_mmu_idx : specifies which TTBR, TCR, etc to use for the walk.
24 * Together with in_space, specifies the architectural translation regime.
28 * in_ptw_idx: specifies which mmuidx to use for the actual
29 * page table descriptor load operations. This will be one of the
30 * ARMMMUIdx_Stage2* or one of the ARMMMUIdx_Phys_* indexes.
31 * If a Secure ptw is "downgraded" to NonSecure by an NSTable bit,
32 * this field is updated accordingly.
36 * in_space: the security space for this walk. This plus
37 * the in_mmu_idx specify the architectural translation regime.
38 * If a Secure ptw is "downgraded" to NonSecure by an NSTable bit,
39 * this field is updated accordingly.
41 * Note that the security space for the in_ptw_idx may be different
42 * from that for the in_mmu_idx. We do not need to explicitly track
43 * the in_ptw_idx security space because:
44 * - if the in_ptw_idx is an ARMMMUIdx_Phys_* then the mmuidx
45 * itself specifies the security space
46 * - if the in_ptw_idx is an ARMMMUIdx_Stage2* then the security
47 * space used for ptw reads is the same as that of the security
48 * space of the stage 1 translation for all cases except where
49 * stage 1 is Secure; in that case the only possibilities for
50 * the ptw read are Secure and NonSecure, and the in_ptw_idx
51 * value being Stage2 vs Stage2_S distinguishes those.
53 ARMSecuritySpace in_space
;
55 * in_debug: is this a QEMU debug access (gdbstub, etc)? Debug
56 * accesses will not update the guest page table access flags
57 * and will not change the state of the softmmu TLBs.
61 * If this is stage 2 of a stage 1+2 page table walk, then this must
62 * be true if stage 1 is an EL0 access; otherwise this is ignored.
63 * Stage 2 is indicated by in_mmu_idx set to ARMMMUIdx_Stage2{,_S}.
68 ARMSecuritySpace out_space
;
74 static bool get_phys_addr_nogpc(CPUARMState
*env
, S1Translate
*ptw
,
76 MMUAccessType access_type
,
77 GetPhysAddrResult
*result
,
80 static bool get_phys_addr_gpc(CPUARMState
*env
, S1Translate
*ptw
,
82 MMUAccessType access_type
,
83 GetPhysAddrResult
*result
,
86 /* This mapping is common between ID_AA64MMFR0.PARANGE and TCR_ELx.{I}PS. */
87 static const uint8_t pamax_map
[] = {
97 /* The cpu-specific constant value of PAMax; also used by hw/arm/virt. */
98 unsigned int arm_pamax(ARMCPU
*cpu
)
100 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
101 unsigned int parange
=
102 FIELD_EX64(cpu
->isar
.id_aa64mmfr0
, ID_AA64MMFR0
, PARANGE
);
105 * id_aa64mmfr0 is a read-only register so values outside of the
106 * supported mappings can be considered an implementation error.
108 assert(parange
< ARRAY_SIZE(pamax_map
));
109 return pamax_map
[parange
];
113 * In machvirt_init, we call arm_pamax on a cpu that is not fully
114 * initialized, so we can't rely on the propagation done in realize.
116 if (arm_feature(&cpu
->env
, ARM_FEATURE_LPAE
) ||
117 arm_feature(&cpu
->env
, ARM_FEATURE_V7VE
)) {
126 * Convert a possible stage1+2 MMU index into the appropriate stage 1 MMU index
128 ARMMMUIdx
stage_1_mmu_idx(ARMMMUIdx mmu_idx
)
131 case ARMMMUIdx_E10_0
:
132 return ARMMMUIdx_Stage1_E0
;
133 case ARMMMUIdx_E10_1
:
134 return ARMMMUIdx_Stage1_E1
;
135 case ARMMMUIdx_E10_1_PAN
:
136 return ARMMMUIdx_Stage1_E1_PAN
;
142 ARMMMUIdx
arm_stage1_mmu_idx(CPUARMState
*env
)
144 return stage_1_mmu_idx(arm_mmu_idx(env
));
148 * Return where we should do ptw loads from for a stage 2 walk.
149 * This depends on whether the address we are looking up is a
150 * Secure IPA or a NonSecure IPA, which we know from whether this is
151 * Stage2 or Stage2_S.
152 * If this is the Secure EL1&0 regime we need to check the NSW and SW bits.
154 static ARMMMUIdx
ptw_idx_for_stage_2(CPUARMState
*env
, ARMMMUIdx stage2idx
)
159 * We're OK to check the current state of the CPU here because
160 * (1) we always invalidate all TLBs when the SCR_EL3.NS or SCR_EL3.NSE bit
162 * (2) there's no way to do a lookup that cares about Stage 2 for a
163 * different security state to the current one for AArch64, and AArch32
164 * never has a secure EL2. (AArch32 ATS12NSO[UP][RW] allow EL3 to do
165 * an NS stage 1+2 lookup while the NS bit is 0.)
167 if (!arm_el_is_aa64(env
, 3)) {
168 return ARMMMUIdx_Phys_NS
;
171 switch (arm_security_space_below_el3(env
)) {
172 case ARMSS_NonSecure
:
173 return ARMMMUIdx_Phys_NS
;
175 return ARMMMUIdx_Phys_Realm
;
177 if (stage2idx
== ARMMMUIdx_Stage2_S
) {
178 s2walk_secure
= !(env
->cp15
.vstcr_el2
& VSTCR_SW
);
180 s2walk_secure
= !(env
->cp15
.vtcr_el2
& VTCR_NSW
);
182 return s2walk_secure
? ARMMMUIdx_Phys_S
: ARMMMUIdx_Phys_NS
;
184 g_assert_not_reached();
188 static bool regime_translation_big_endian(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
190 return (regime_sctlr(env
, mmu_idx
) & SCTLR_EE
) != 0;
193 /* Return the TTBR associated with this translation regime */
194 static uint64_t regime_ttbr(CPUARMState
*env
, ARMMMUIdx mmu_idx
, int ttbrn
)
196 if (mmu_idx
== ARMMMUIdx_Stage2
) {
197 return env
->cp15
.vttbr_el2
;
199 if (mmu_idx
== ARMMMUIdx_Stage2_S
) {
200 return env
->cp15
.vsttbr_el2
;
203 return env
->cp15
.ttbr0_el
[regime_el(env
, mmu_idx
)];
205 return env
->cp15
.ttbr1_el
[regime_el(env
, mmu_idx
)];
209 /* Return true if the specified stage of address translation is disabled */
210 static bool regime_translation_disabled(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
211 ARMSecuritySpace space
)
215 if (arm_feature(env
, ARM_FEATURE_M
)) {
216 bool is_secure
= arm_space_is_secure(space
);
217 switch (env
->v7m
.mpu_ctrl
[is_secure
] &
218 (R_V7M_MPU_CTRL_ENABLE_MASK
| R_V7M_MPU_CTRL_HFNMIENA_MASK
)) {
219 case R_V7M_MPU_CTRL_ENABLE_MASK
:
220 /* Enabled, but not for HardFault and NMI */
221 return mmu_idx
& ARM_MMU_IDX_M_NEGPRI
;
222 case R_V7M_MPU_CTRL_ENABLE_MASK
| R_V7M_MPU_CTRL_HFNMIENA_MASK
:
223 /* Enabled for all cases */
228 * HFNMIENA set and ENABLE clear is UNPREDICTABLE, but
229 * we warned about that in armv7m_nvic.c when the guest set it.
237 case ARMMMUIdx_Stage2
:
238 case ARMMMUIdx_Stage2_S
:
239 /* HCR.DC means HCR.VM behaves as 1 */
240 hcr_el2
= arm_hcr_el2_eff_secstate(env
, space
);
241 return (hcr_el2
& (HCR_DC
| HCR_VM
)) == 0;
243 case ARMMMUIdx_E10_0
:
244 case ARMMMUIdx_E10_1
:
245 case ARMMMUIdx_E10_1_PAN
:
246 /* TGE means that EL0/1 act as if SCTLR_EL1.M is zero */
247 hcr_el2
= arm_hcr_el2_eff_secstate(env
, space
);
248 if (hcr_el2
& HCR_TGE
) {
253 case ARMMMUIdx_Stage1_E0
:
254 case ARMMMUIdx_Stage1_E1
:
255 case ARMMMUIdx_Stage1_E1_PAN
:
256 /* HCR.DC means SCTLR_EL1.M behaves as 0 */
257 hcr_el2
= arm_hcr_el2_eff_secstate(env
, space
);
258 if (hcr_el2
& HCR_DC
) {
263 case ARMMMUIdx_E20_0
:
264 case ARMMMUIdx_E20_2
:
265 case ARMMMUIdx_E20_2_PAN
:
270 case ARMMMUIdx_Phys_S
:
271 case ARMMMUIdx_Phys_NS
:
272 case ARMMMUIdx_Phys_Root
:
273 case ARMMMUIdx_Phys_Realm
:
274 /* No translation for physical address spaces. */
278 g_assert_not_reached();
281 return (regime_sctlr(env
, mmu_idx
) & SCTLR_M
) == 0;
284 static bool granule_protection_check(CPUARMState
*env
, uint64_t paddress
,
285 ARMSecuritySpace pspace
,
292 ARMCPU
*cpu
= env_archcpu(env
);
293 uint64_t gpccr
= env
->cp15
.gpccr_el3
;
294 unsigned pps
, pgs
, l0gptsz
, level
= 0;
295 uint64_t tableaddr
, pps_mask
, align
, entry
, index
;
300 if (!FIELD_EX64(gpccr
, GPCCR
, GPC
)) {
305 * GPC Priority 1 (R_GMGRR):
306 * R_JWCSM: If the configuration of GPCCR_EL3 is invalid,
307 * the access fails as GPT walk fault at level 0.
311 * Configuration of PPS to a value exceeding the implemented
312 * physical address size is invalid.
314 pps
= FIELD_EX64(gpccr
, GPCCR
, PPS
);
315 if (pps
> FIELD_EX64(cpu
->isar
.id_aa64mmfr0
, ID_AA64MMFR0
, PARANGE
)) {
318 pps
= pamax_map
[pps
];
319 pps_mask
= MAKE_64BIT_MASK(0, pps
);
321 switch (FIELD_EX64(gpccr
, GPCCR
, SH
)) {
322 case 0b10: /* outer shareable */
324 case 0b00: /* non-shareable */
325 case 0b11: /* inner shareable */
326 /* Inner and Outer non-cacheable requires Outer shareable. */
327 if (FIELD_EX64(gpccr
, GPCCR
, ORGN
) == 0 &&
328 FIELD_EX64(gpccr
, GPCCR
, IRGN
) == 0) {
332 default: /* reserved */
336 switch (FIELD_EX64(gpccr
, GPCCR
, PGS
)) {
340 case 0b01: /* 64KB */
343 case 0b10: /* 16KB */
346 default: /* reserved */
350 /* Note this field is read-only and fixed at reset. */
351 l0gptsz
= 30 + FIELD_EX64(gpccr
, GPCCR
, L0GPTSZ
);
354 * GPC Priority 2: Secure, Realm or Root address exceeds PPS.
355 * R_CPDSB: A NonSecure physical address input exceeding PPS
356 * does not experience any fault.
358 if (paddress
& ~pps_mask
) {
359 if (pspace
== ARMSS_NonSecure
) {
365 /* GPC Priority 3: the base address of GPTBR_EL3 exceeds PPS. */
366 tableaddr
= env
->cp15
.gptbr_el3
<< 12;
367 if (tableaddr
& ~pps_mask
) {
372 * BADDR is aligned per a function of PPS and L0GPTSZ.
373 * These bits of GPTBR_EL3 are RES0, but are not a configuration error,
374 * unlike the RES0 bits of the GPT entries (R_XNKFZ).
376 align
= MAX(pps
- l0gptsz
+ 3, 12);
377 align
= MAKE_64BIT_MASK(0, align
);
380 as
= arm_addressspace(env_cpu(env
), attrs
);
382 /* Level 0 lookup. */
383 index
= extract64(paddress
, l0gptsz
, pps
- l0gptsz
);
384 tableaddr
+= index
* 8;
385 entry
= address_space_ldq_le(as
, tableaddr
, attrs
, &result
);
386 if (result
!= MEMTX_OK
) {
390 switch (extract32(entry
, 0, 4)) {
391 case 1: /* block descriptor */
393 goto fault_walk
; /* RES0 bits not 0 */
395 gpi
= extract32(entry
, 4, 4);
397 case 3: /* table descriptor */
398 tableaddr
= entry
& ~0xf;
399 align
= MAX(l0gptsz
- pgs
- 1, 12);
400 align
= MAKE_64BIT_MASK(0, align
);
401 if (tableaddr
& (~pps_mask
| align
)) {
402 goto fault_walk
; /* RES0 bits not 0 */
405 default: /* invalid */
411 index
= extract64(paddress
, pgs
+ 4, l0gptsz
- pgs
- 4);
412 tableaddr
+= index
* 8;
413 entry
= address_space_ldq_le(as
, tableaddr
, attrs
, &result
);
414 if (result
!= MEMTX_OK
) {
418 switch (extract32(entry
, 0, 4)) {
419 case 1: /* contiguous descriptor */
421 goto fault_walk
; /* RES0 bits not 0 */
424 * Because the softmmu tlb only works on units of TARGET_PAGE_SIZE,
425 * and because we cannot invalidate by pa, and thus will always
426 * flush entire tlbs, we don't actually care about the range here
427 * and can simply extract the GPI as the result.
429 if (extract32(entry
, 8, 2) == 0) {
430 goto fault_walk
; /* reserved contig */
432 gpi
= extract32(entry
, 4, 4);
435 index
= extract64(paddress
, pgs
, 4);
436 gpi
= extract64(entry
, index
* 4, 4);
442 case 0b0000: /* no access */
444 case 0b1111: /* all access */
450 if (pspace
== (gpi
& 3)) {
455 goto fault_walk
; /* reserved */
458 fi
->gpcf
= GPCF_Fail
;
461 fi
->gpcf
= GPCF_EABT
;
464 fi
->gpcf
= GPCF_AddressSize
;
467 fi
->gpcf
= GPCF_Walk
;
470 fi
->paddr
= paddress
;
471 fi
->paddr_space
= pspace
;
475 static bool S2_attrs_are_device(uint64_t hcr
, uint8_t attrs
)
478 * For an S1 page table walk, the stage 1 attributes are always
479 * some form of "this is Normal memory". The combined S1+S2
480 * attributes are therefore only Device if stage 2 specifies Device.
481 * With HCR_EL2.FWB == 0 this is when descriptor bits [5:4] are 0b00,
482 * ie when cacheattrs.attrs bits [3:2] are 0b00.
483 * With HCR_EL2.FWB == 1 this is when descriptor bit [4] is 0, ie
484 * when cacheattrs.attrs bit [2] is 0.
487 return (attrs
& 0x4) == 0;
489 return (attrs
& 0xc) == 0;
493 static ARMSecuritySpace
S2_security_space(ARMSecuritySpace s1_space
,
494 ARMMMUIdx s2_mmu_idx
)
497 * Return the security space to use for stage 2 when doing
498 * the S1 page table descriptor load.
500 if (regime_is_stage2(s2_mmu_idx
)) {
502 * The security space for ptw reads is almost always the same
503 * as that of the security space of the stage 1 translation.
504 * The only exception is when stage 1 is Secure; in that case
505 * the ptw read might be to the Secure or the NonSecure space
506 * (but never Realm or Root), and the s2_mmu_idx tells us which.
507 * Root translations are always single-stage.
509 if (s1_space
== ARMSS_Secure
) {
510 return arm_secure_to_space(s2_mmu_idx
== ARMMMUIdx_Stage2_S
);
512 assert(s2_mmu_idx
!= ARMMMUIdx_Stage2_S
);
513 assert(s1_space
!= ARMSS_Root
);
517 /* ptw loads are from phys: the mmu idx itself says which space */
518 return arm_phys_to_space(s2_mmu_idx
);
522 static bool fault_s1ns(ARMSecuritySpace space
, ARMMMUIdx s2_mmu_idx
)
525 * For stage 2 faults in Secure EL22, S1NS indicates
526 * whether the faulting IPA is in the Secure or NonSecure
527 * IPA space. For all other kinds of fault, it is false.
529 return space
== ARMSS_Secure
&& regime_is_stage2(s2_mmu_idx
)
530 && s2_mmu_idx
== ARMMMUIdx_Stage2_S
;
533 /* Translate a S1 pagetable walk through S2 if needed. */
534 static bool S1_ptw_translate(CPUARMState
*env
, S1Translate
*ptw
,
535 hwaddr addr
, ARMMMUFaultInfo
*fi
)
537 ARMMMUIdx mmu_idx
= ptw
->in_mmu_idx
;
538 ARMMMUIdx s2_mmu_idx
= ptw
->in_ptw_idx
;
541 ptw
->out_virt
= addr
;
543 if (unlikely(ptw
->in_debug
)) {
545 * From gdbstub, do not use softmmu so that we don't modify the
546 * state of the cpu at all, including softmmu tlb contents.
548 ARMSecuritySpace s2_space
= S2_security_space(ptw
->in_space
, s2_mmu_idx
);
549 S1Translate s2ptw
= {
550 .in_mmu_idx
= s2_mmu_idx
,
551 .in_ptw_idx
= ptw_idx_for_stage_2(env
, s2_mmu_idx
),
552 .in_space
= s2_space
,
555 GetPhysAddrResult s2
= { };
557 if (get_phys_addr_gpc(env
, &s2ptw
, addr
, MMU_DATA_LOAD
, &s2
, fi
)) {
561 ptw
->out_phys
= s2
.f
.phys_addr
;
562 pte_attrs
= s2
.cacheattrs
.attrs
;
563 ptw
->out_host
= NULL
;
565 ptw
->out_space
= s2
.f
.attrs
.space
;
568 CPUTLBEntryFull
*full
;
572 flags
= probe_access_full_mmu(env
, addr
, 0, MMU_DATA_LOAD
,
573 arm_to_core_mmu_idx(s2_mmu_idx
),
574 &ptw
->out_host
, &full
);
577 if (unlikely(flags
& TLB_INVALID_MASK
)) {
580 ptw
->out_phys
= full
->phys_addr
| (addr
& ~TARGET_PAGE_MASK
);
581 ptw
->out_rw
= full
->prot
& PAGE_WRITE
;
582 pte_attrs
= full
->extra
.arm
.pte_attrs
;
583 ptw
->out_space
= full
->attrs
.space
;
585 g_assert_not_reached();
589 if (regime_is_stage2(s2_mmu_idx
)) {
590 uint64_t hcr
= arm_hcr_el2_eff_secstate(env
, ptw
->in_space
);
592 if ((hcr
& HCR_PTW
) && S2_attrs_are_device(hcr
, pte_attrs
)) {
594 * PTW set and S1 walk touched S2 Device memory:
595 * generate Permission fault.
597 fi
->type
= ARMFault_Permission
;
601 fi
->s1ns
= fault_s1ns(ptw
->in_space
, s2_mmu_idx
);
606 ptw
->out_be
= regime_translation_big_endian(env
, mmu_idx
);
610 assert(fi
->type
!= ARMFault_None
);
611 if (fi
->type
== ARMFault_GPCFOnOutput
) {
612 fi
->type
= ARMFault_GPCFOnWalk
;
615 fi
->stage2
= regime_is_stage2(s2_mmu_idx
);
616 fi
->s1ptw
= fi
->stage2
;
617 fi
->s1ns
= fault_s1ns(ptw
->in_space
, s2_mmu_idx
);
621 /* All loads done in the course of a page table walk go through here. */
622 static uint32_t arm_ldl_ptw(CPUARMState
*env
, S1Translate
*ptw
,
625 CPUState
*cs
= env_cpu(env
);
626 void *host
= ptw
->out_host
;
630 /* Page tables are in RAM, and we have the host address. */
631 data
= qatomic_read((uint32_t *)host
);
633 data
= be32_to_cpu(data
);
635 data
= le32_to_cpu(data
);
638 /* Page tables are in MMIO. */
640 .space
= ptw
->out_space
,
641 .secure
= arm_space_is_secure(ptw
->out_space
),
643 AddressSpace
*as
= arm_addressspace(cs
, attrs
);
644 MemTxResult result
= MEMTX_OK
;
647 data
= address_space_ldl_be(as
, ptw
->out_phys
, attrs
, &result
);
649 data
= address_space_ldl_le(as
, ptw
->out_phys
, attrs
, &result
);
651 if (unlikely(result
!= MEMTX_OK
)) {
652 fi
->type
= ARMFault_SyncExternalOnWalk
;
653 fi
->ea
= arm_extabort_type(result
);
660 static uint64_t arm_ldq_ptw(CPUARMState
*env
, S1Translate
*ptw
,
663 CPUState
*cs
= env_cpu(env
);
664 void *host
= ptw
->out_host
;
668 /* Page tables are in RAM, and we have the host address. */
669 #ifdef CONFIG_ATOMIC64
670 data
= qatomic_read__nocheck((uint64_t *)host
);
672 data
= be64_to_cpu(data
);
674 data
= le64_to_cpu(data
);
678 data
= ldq_be_p(host
);
680 data
= ldq_le_p(host
);
684 /* Page tables are in MMIO. */
686 .space
= ptw
->out_space
,
687 .secure
= arm_space_is_secure(ptw
->out_space
),
689 AddressSpace
*as
= arm_addressspace(cs
, attrs
);
690 MemTxResult result
= MEMTX_OK
;
693 data
= address_space_ldq_be(as
, ptw
->out_phys
, attrs
, &result
);
695 data
= address_space_ldq_le(as
, ptw
->out_phys
, attrs
, &result
);
697 if (unlikely(result
!= MEMTX_OK
)) {
698 fi
->type
= ARMFault_SyncExternalOnWalk
;
699 fi
->ea
= arm_extabort_type(result
);
706 static uint64_t arm_casq_ptw(CPUARMState
*env
, uint64_t old_val
,
707 uint64_t new_val
, S1Translate
*ptw
,
710 #if defined(TARGET_AARCH64) && defined(CONFIG_TCG)
712 void *host
= ptw
->out_host
;
714 if (unlikely(!host
)) {
715 fi
->type
= ARMFault_UnsuppAtomicUpdate
;
720 * Raising a stage2 Protection fault for an atomic update to a read-only
721 * page is delayed until it is certain that there is a change to make.
723 if (unlikely(!ptw
->out_rw
)) {
727 flags
= probe_access_full_mmu(env
, ptw
->out_virt
, 0,
729 arm_to_core_mmu_idx(ptw
->in_ptw_idx
),
733 if (unlikely(flags
& TLB_INVALID_MASK
)) {
735 * We know this must be a stage 2 fault because the granule
736 * protection table does not separately track read and write
737 * permission, so all GPC faults are caught in S1_ptw_translate():
738 * we only get here for "readable but not writeable".
740 assert(fi
->type
!= ARMFault_None
);
741 fi
->s2addr
= ptw
->out_virt
;
744 fi
->s1ns
= fault_s1ns(ptw
->in_space
, ptw
->in_ptw_idx
);
748 /* In case CAS mismatches and we loop, remember writability. */
752 #ifdef CONFIG_ATOMIC64
754 old_val
= cpu_to_be64(old_val
);
755 new_val
= cpu_to_be64(new_val
);
756 cur_val
= qatomic_cmpxchg__nocheck((uint64_t *)host
, old_val
, new_val
);
757 cur_val
= be64_to_cpu(cur_val
);
759 old_val
= cpu_to_le64(old_val
);
760 new_val
= cpu_to_le64(new_val
);
761 cur_val
= qatomic_cmpxchg__nocheck((uint64_t *)host
, old_val
, new_val
);
762 cur_val
= le64_to_cpu(cur_val
);
766 * We can't support the full 64-bit atomic cmpxchg on the host.
767 * Because this is only used for FEAT_HAFDBS, which is only for AA64,
768 * we know that TCG_OVERSIZED_GUEST is set, which means that we are
769 * running in round-robin mode and could only race with dma i/o.
771 #if !TCG_OVERSIZED_GUEST
772 # error "Unexpected configuration"
774 bool locked
= qemu_mutex_iothread_locked();
776 qemu_mutex_lock_iothread();
779 cur_val
= ldq_be_p(host
);
780 if (cur_val
== old_val
) {
781 stq_be_p(host
, new_val
);
784 cur_val
= ldq_le_p(host
);
785 if (cur_val
== old_val
) {
786 stq_le_p(host
, new_val
);
790 qemu_mutex_unlock_iothread();
796 /* AArch32 does not have FEAT_HADFS; non-TCG guests only use debug-mode. */
797 g_assert_not_reached();
801 static bool get_level1_table_address(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
802 uint32_t *table
, uint32_t address
)
804 /* Note that we can only get here for an AArch32 PL0/PL1 lookup */
805 uint64_t tcr
= regime_tcr(env
, mmu_idx
);
806 int maskshift
= extract32(tcr
, 0, 3);
807 uint32_t mask
= ~(((uint32_t)0xffffffffu
) >> maskshift
);
810 if (address
& mask
) {
811 if (tcr
& TTBCR_PD1
) {
812 /* Translation table walk disabled for TTBR1 */
815 *table
= regime_ttbr(env
, mmu_idx
, 1) & 0xffffc000;
817 if (tcr
& TTBCR_PD0
) {
818 /* Translation table walk disabled for TTBR0 */
821 base_mask
= ~((uint32_t)0x3fffu
>> maskshift
);
822 *table
= regime_ttbr(env
, mmu_idx
, 0) & base_mask
;
824 *table
|= (address
>> 18) & 0x3ffc;
829 * Translate section/page access permissions to page R/W protection flags
831 * @mmu_idx: MMU index indicating required translation regime
832 * @ap: The 3-bit access permissions (AP[2:0])
833 * @domain_prot: The 2-bit domain access permissions
834 * @is_user: TRUE if accessing from PL0
836 static int ap_to_rw_prot_is_user(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
837 int ap
, int domain_prot
, bool is_user
)
839 if (domain_prot
== 3) {
840 return PAGE_READ
| PAGE_WRITE
;
845 if (arm_feature(env
, ARM_FEATURE_V7
)) {
848 switch (regime_sctlr(env
, mmu_idx
) & (SCTLR_S
| SCTLR_R
)) {
850 return is_user
? 0 : PAGE_READ
;
857 return is_user
? 0 : PAGE_READ
| PAGE_WRITE
;
862 return PAGE_READ
| PAGE_WRITE
;
865 return PAGE_READ
| PAGE_WRITE
;
866 case 4: /* Reserved. */
869 return is_user
? 0 : PAGE_READ
;
873 if (!arm_feature(env
, ARM_FEATURE_V6K
)) {
878 g_assert_not_reached();
883 * Translate section/page access permissions to page R/W protection flags
885 * @mmu_idx: MMU index indicating required translation regime
886 * @ap: The 3-bit access permissions (AP[2:0])
887 * @domain_prot: The 2-bit domain access permissions
889 static int ap_to_rw_prot(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
890 int ap
, int domain_prot
)
892 return ap_to_rw_prot_is_user(env
, mmu_idx
, ap
, domain_prot
,
893 regime_is_user(env
, mmu_idx
));
897 * Translate section/page access permissions to page R/W protection flags.
898 * @ap: The 2-bit simple AP (AP[2:1])
899 * @is_user: TRUE if accessing from PL0
901 static int simple_ap_to_rw_prot_is_user(int ap
, bool is_user
)
905 return is_user
? 0 : PAGE_READ
| PAGE_WRITE
;
907 return PAGE_READ
| PAGE_WRITE
;
909 return is_user
? 0 : PAGE_READ
;
913 g_assert_not_reached();
917 static int simple_ap_to_rw_prot(CPUARMState
*env
, ARMMMUIdx mmu_idx
, int ap
)
919 return simple_ap_to_rw_prot_is_user(ap
, regime_is_user(env
, mmu_idx
));
922 static bool get_phys_addr_v5(CPUARMState
*env
, S1Translate
*ptw
,
923 uint32_t address
, MMUAccessType access_type
,
924 GetPhysAddrResult
*result
, ARMMMUFaultInfo
*fi
)
936 /* Pagetable walk. */
937 /* Lookup l1 descriptor. */
938 if (!get_level1_table_address(env
, ptw
->in_mmu_idx
, &table
, address
)) {
939 /* Section translation fault if page walk is disabled by PD0 or PD1 */
940 fi
->type
= ARMFault_Translation
;
943 if (!S1_ptw_translate(env
, ptw
, table
, fi
)) {
946 desc
= arm_ldl_ptw(env
, ptw
, fi
);
947 if (fi
->type
!= ARMFault_None
) {
951 domain
= (desc
>> 5) & 0x0f;
952 if (regime_el(env
, ptw
->in_mmu_idx
) == 1) {
953 dacr
= env
->cp15
.dacr_ns
;
955 dacr
= env
->cp15
.dacr_s
;
957 domain_prot
= (dacr
>> (domain
* 2)) & 3;
959 /* Section translation fault. */
960 fi
->type
= ARMFault_Translation
;
966 if (domain_prot
== 0 || domain_prot
== 2) {
967 fi
->type
= ARMFault_Domain
;
972 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
973 ap
= (desc
>> 10) & 3;
974 result
->f
.lg_page_size
= 20; /* 1MB */
976 /* Lookup l2 entry. */
978 /* Coarse pagetable. */
979 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
981 /* Fine pagetable. */
982 table
= (desc
& 0xfffff000) | ((address
>> 8) & 0xffc);
984 if (!S1_ptw_translate(env
, ptw
, table
, fi
)) {
987 desc
= arm_ldl_ptw(env
, ptw
, fi
);
988 if (fi
->type
!= ARMFault_None
) {
992 case 0: /* Page translation fault. */
993 fi
->type
= ARMFault_Translation
;
995 case 1: /* 64k page. */
996 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
997 ap
= (desc
>> (4 + ((address
>> 13) & 6))) & 3;
998 result
->f
.lg_page_size
= 16;
1000 case 2: /* 4k page. */
1001 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
1002 ap
= (desc
>> (4 + ((address
>> 9) & 6))) & 3;
1003 result
->f
.lg_page_size
= 12;
1005 case 3: /* 1k page, or ARMv6/XScale "extended small (4k) page" */
1007 /* ARMv6/XScale extended small page format */
1008 if (arm_feature(env
, ARM_FEATURE_XSCALE
)
1009 || arm_feature(env
, ARM_FEATURE_V6
)) {
1010 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
1011 result
->f
.lg_page_size
= 12;
1014 * UNPREDICTABLE in ARMv5; we choose to take a
1015 * page translation fault.
1017 fi
->type
= ARMFault_Translation
;
1021 phys_addr
= (desc
& 0xfffffc00) | (address
& 0x3ff);
1022 result
->f
.lg_page_size
= 10;
1024 ap
= (desc
>> 4) & 3;
1027 /* Never happens, but compiler isn't smart enough to tell. */
1028 g_assert_not_reached();
1031 result
->f
.prot
= ap_to_rw_prot(env
, ptw
->in_mmu_idx
, ap
, domain_prot
);
1032 result
->f
.prot
|= result
->f
.prot
? PAGE_EXEC
: 0;
1033 if (!(result
->f
.prot
& (1 << access_type
))) {
1034 /* Access permission fault. */
1035 fi
->type
= ARMFault_Permission
;
1038 result
->f
.phys_addr
= phys_addr
;
1041 fi
->domain
= domain
;
1046 static bool get_phys_addr_v6(CPUARMState
*env
, S1Translate
*ptw
,
1047 uint32_t address
, MMUAccessType access_type
,
1048 GetPhysAddrResult
*result
, ARMMMUFaultInfo
*fi
)
1050 ARMCPU
*cpu
= env_archcpu(env
);
1051 ARMMMUIdx mmu_idx
= ptw
->in_mmu_idx
;
1066 /* Pagetable walk. */
1067 /* Lookup l1 descriptor. */
1068 if (!get_level1_table_address(env
, mmu_idx
, &table
, address
)) {
1069 /* Section translation fault if page walk is disabled by PD0 or PD1 */
1070 fi
->type
= ARMFault_Translation
;
1073 if (!S1_ptw_translate(env
, ptw
, table
, fi
)) {
1076 desc
= arm_ldl_ptw(env
, ptw
, fi
);
1077 if (fi
->type
!= ARMFault_None
) {
1081 if (type
== 0 || (type
== 3 && !cpu_isar_feature(aa32_pxn
, cpu
))) {
1082 /* Section translation fault, or attempt to use the encoding
1083 * which is Reserved on implementations without PXN.
1085 fi
->type
= ARMFault_Translation
;
1088 if ((type
== 1) || !(desc
& (1 << 18))) {
1089 /* Page or Section. */
1090 domain
= (desc
>> 5) & 0x0f;
1092 if (regime_el(env
, mmu_idx
) == 1) {
1093 dacr
= env
->cp15
.dacr_ns
;
1095 dacr
= env
->cp15
.dacr_s
;
1100 domain_prot
= (dacr
>> (domain
* 2)) & 3;
1101 if (domain_prot
== 0 || domain_prot
== 2) {
1102 /* Section or Page domain fault */
1103 fi
->type
= ARMFault_Domain
;
1107 if (desc
& (1 << 18)) {
1109 phys_addr
= (desc
& 0xff000000) | (address
& 0x00ffffff);
1110 phys_addr
|= (uint64_t)extract32(desc
, 20, 4) << 32;
1111 phys_addr
|= (uint64_t)extract32(desc
, 5, 4) << 36;
1112 result
->f
.lg_page_size
= 24; /* 16MB */
1115 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
1116 result
->f
.lg_page_size
= 20; /* 1MB */
1118 ap
= ((desc
>> 10) & 3) | ((desc
>> 13) & 4);
1119 xn
= desc
& (1 << 4);
1121 ns
= extract32(desc
, 19, 1);
1123 if (cpu_isar_feature(aa32_pxn
, cpu
)) {
1124 pxn
= (desc
>> 2) & 1;
1126 ns
= extract32(desc
, 3, 1);
1127 /* Lookup l2 entry. */
1128 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
1129 if (!S1_ptw_translate(env
, ptw
, table
, fi
)) {
1132 desc
= arm_ldl_ptw(env
, ptw
, fi
);
1133 if (fi
->type
!= ARMFault_None
) {
1136 ap
= ((desc
>> 4) & 3) | ((desc
>> 7) & 4);
1138 case 0: /* Page translation fault. */
1139 fi
->type
= ARMFault_Translation
;
1141 case 1: /* 64k page. */
1142 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
1143 xn
= desc
& (1 << 15);
1144 result
->f
.lg_page_size
= 16;
1146 case 2: case 3: /* 4k page. */
1147 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
1149 result
->f
.lg_page_size
= 12;
1152 /* Never happens, but compiler isn't smart enough to tell. */
1153 g_assert_not_reached();
1156 if (domain_prot
== 3) {
1157 result
->f
.prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
1159 if (pxn
&& !regime_is_user(env
, mmu_idx
)) {
1162 if (xn
&& access_type
== MMU_INST_FETCH
) {
1163 fi
->type
= ARMFault_Permission
;
1167 if (arm_feature(env
, ARM_FEATURE_V6K
) &&
1168 (regime_sctlr(env
, mmu_idx
) & SCTLR_AFE
)) {
1169 /* The simplified model uses AP[0] as an access control bit. */
1170 if ((ap
& 1) == 0) {
1171 /* Access flag fault. */
1172 fi
->type
= ARMFault_AccessFlag
;
1175 result
->f
.prot
= simple_ap_to_rw_prot(env
, mmu_idx
, ap
>> 1);
1176 user_prot
= simple_ap_to_rw_prot_is_user(ap
>> 1, 1);
1178 result
->f
.prot
= ap_to_rw_prot(env
, mmu_idx
, ap
, domain_prot
);
1179 user_prot
= ap_to_rw_prot_is_user(env
, mmu_idx
, ap
, domain_prot
, 1);
1181 if (result
->f
.prot
&& !xn
) {
1182 result
->f
.prot
|= PAGE_EXEC
;
1184 if (!(result
->f
.prot
& (1 << access_type
))) {
1185 /* Access permission fault. */
1186 fi
->type
= ARMFault_Permission
;
1189 if (regime_is_pan(env
, mmu_idx
) &&
1190 !regime_is_user(env
, mmu_idx
) &&
1192 access_type
!= MMU_INST_FETCH
) {
1193 /* Privileged Access Never fault */
1194 fi
->type
= ARMFault_Permission
;
1199 /* The NS bit will (as required by the architecture) have no effect if
1200 * the CPU doesn't support TZ or this is a non-secure translation
1201 * regime, because the attribute will already be non-secure.
1203 result
->f
.attrs
.secure
= false;
1204 result
->f
.attrs
.space
= ARMSS_NonSecure
;
1206 result
->f
.phys_addr
= phys_addr
;
1209 fi
->domain
= domain
;
1215 * Translate S2 section/page access permissions to protection flags
1217 * @s2ap: The 2-bit stage2 access permissions (S2AP)
1218 * @xn: XN (execute-never) bits
1219 * @s1_is_el0: true if this is S2 of an S1+2 walk for EL0
1221 static int get_S2prot_noexecute(int s2ap
)
1234 static int get_S2prot(CPUARMState
*env
, int s2ap
, int xn
, bool s1_is_el0
)
1236 int prot
= get_S2prot_noexecute(s2ap
);
1238 if (cpu_isar_feature(any_tts2uxn
, env_archcpu(env
))) {
1256 g_assert_not_reached();
1259 if (!extract32(xn
, 1, 1)) {
1260 if (arm_el_is_aa64(env
, 2) || prot
& PAGE_READ
) {
1269 * Translate section/page access permissions to protection flags
1271 * @mmu_idx: MMU index indicating required translation regime
1272 * @is_aa64: TRUE if AArch64
1273 * @ap: The 2-bit simple AP (AP[2:1])
1274 * @xn: XN (execute-never) bit
1275 * @pxn: PXN (privileged execute-never) bit
1276 * @in_pa: The original input pa space
1277 * @out_pa: The output pa space, modified by NSTable, NS, and NSE
1279 static int get_S1prot(CPUARMState
*env
, ARMMMUIdx mmu_idx
, bool is_aa64
,
1280 int ap
, int xn
, int pxn
,
1281 ARMSecuritySpace in_pa
, ARMSecuritySpace out_pa
)
1283 ARMCPU
*cpu
= env_archcpu(env
);
1284 bool is_user
= regime_is_user(env
, mmu_idx
);
1285 int prot_rw
, user_rw
;
1289 assert(!regime_is_stage2(mmu_idx
));
1291 user_rw
= simple_ap_to_rw_prot_is_user(ap
, true);
1296 * PAN controls can forbid data accesses but don't affect insn fetch.
1297 * Plain PAN forbids data accesses if EL0 has data permissions;
1298 * PAN3 forbids data accesses if EL0 has either data or exec perms.
1299 * Note that for AArch64 the 'user can exec' case is exactly !xn.
1300 * We make the IMPDEF choices that SCR_EL3.SIF and Realm EL2&0
1301 * do not affect EPAN.
1303 if (user_rw
&& regime_is_pan(env
, mmu_idx
)) {
1305 } else if (cpu_isar_feature(aa64_pan3
, cpu
) && is_aa64
&&
1306 regime_is_pan(env
, mmu_idx
) &&
1307 (regime_sctlr(env
, mmu_idx
) & SCTLR_EPAN
) && !xn
) {
1310 prot_rw
= simple_ap_to_rw_prot_is_user(ap
, false);
1314 if (in_pa
!= out_pa
) {
1318 * R_ZWRVD: permission fault for insn fetched from non-Root,
1319 * I_WWBFB: SIF has no effect in EL3.
1324 * R_PKTDS: permission fault for insn fetched from non-Realm,
1325 * for Realm EL2 or EL2&0. The corresponding fault for EL1&0
1326 * happens during any stage2 translation.
1330 case ARMMMUIdx_E20_0
:
1331 case ARMMMUIdx_E20_2
:
1332 case ARMMMUIdx_E20_2_PAN
:
1339 if (env
->cp15
.scr_el3
& SCR_SIF
) {
1344 /* Input NonSecure must have output NonSecure. */
1345 g_assert_not_reached();
1349 /* TODO have_wxn should be replaced with
1350 * ARM_FEATURE_V8 || (ARM_FEATURE_V7 && ARM_FEATURE_EL2)
1351 * when ARM_FEATURE_EL2 starts getting set. For now we assume all LPAE
1352 * compatible processors have EL2, which is required for [U]WXN.
1354 have_wxn
= arm_feature(env
, ARM_FEATURE_LPAE
);
1357 wxn
= regime_sctlr(env
, mmu_idx
) & SCTLR_WXN
;
1361 if (regime_has_2_ranges(mmu_idx
) && !is_user
) {
1362 xn
= pxn
|| (user_rw
& PAGE_WRITE
);
1364 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
1365 switch (regime_el(env
, mmu_idx
)) {
1369 xn
= xn
|| !(user_rw
& PAGE_READ
);
1373 uwxn
= regime_sctlr(env
, mmu_idx
) & SCTLR_UWXN
;
1375 xn
= xn
|| !(prot_rw
& PAGE_READ
) || pxn
||
1376 (uwxn
&& (user_rw
& PAGE_WRITE
));
1386 if (xn
|| (wxn
&& (prot_rw
& PAGE_WRITE
))) {
1389 return prot_rw
| PAGE_EXEC
;
1392 static ARMVAParameters
aa32_va_parameters(CPUARMState
*env
, uint32_t va
,
1395 uint64_t tcr
= regime_tcr(env
, mmu_idx
);
1396 uint32_t el
= regime_el(env
, mmu_idx
);
1400 assert(mmu_idx
!= ARMMMUIdx_Stage2_S
);
1402 if (mmu_idx
== ARMMMUIdx_Stage2
) {
1404 bool sext
= extract32(tcr
, 4, 1);
1405 bool sign
= extract32(tcr
, 3, 1);
1408 * If the sign-extend bit is not the same as t0sz[3], the result
1409 * is unpredictable. Flag this as a guest error.
1412 qemu_log_mask(LOG_GUEST_ERROR
,
1413 "AArch32: VTCR.S / VTCR.T0SZ[3] mismatch\n");
1415 tsz
= sextract32(tcr
, 0, 4) + 8;
1419 } else if (el
== 2) {
1421 tsz
= extract32(tcr
, 0, 3);
1423 hpd
= extract64(tcr
, 24, 1);
1426 int t0sz
= extract32(tcr
, 0, 3);
1427 int t1sz
= extract32(tcr
, 16, 3);
1430 select
= va
> (0xffffffffu
>> t0sz
);
1432 /* Note that we will detect errors later. */
1433 select
= va
>= ~(0xffffffffu
>> t1sz
);
1437 epd
= extract32(tcr
, 7, 1);
1438 hpd
= extract64(tcr
, 41, 1);
1441 epd
= extract32(tcr
, 23, 1);
1442 hpd
= extract64(tcr
, 42, 1);
1444 /* For aarch32, hpd0 is not enabled without t2e as well. */
1445 hpd
&= extract32(tcr
, 6, 1);
1448 return (ARMVAParameters
) {
1457 * check_s2_mmu_setup
1459 * @is_aa64: True if the translation regime is in AArch64 state
1460 * @tcr: VTCR_EL2 or VSTCR_EL2
1461 * @ds: Effective value of TCR.DS.
1462 * @iasize: Bitsize of IPAs
1463 * @stride: Page-table stride (See the ARM ARM)
1465 * Decode the starting level of the S2 lookup, returning INT_MIN if
1466 * the configuration is invalid.
1468 static int check_s2_mmu_setup(ARMCPU
*cpu
, bool is_aa64
, uint64_t tcr
,
1469 bool ds
, int iasize
, int stride
)
1471 int sl0
, sl2
, startlevel
, granulebits
, levels
;
1472 int s1_min_iasize
, s1_max_iasize
;
1474 sl0
= extract32(tcr
, 6, 2);
1477 * AArch64.S2InvalidSL: Interpretation of SL depends on the page size,
1478 * so interleave AArch64.S2StartLevel.
1482 /* SL2 is RES0 unless DS=1 & 4KB granule. */
1483 sl2
= extract64(tcr
, 33, 1);
1490 startlevel
= 2 - sl0
;
1493 if (arm_pamax(cpu
) < 44) {
1498 if (!cpu_isar_feature(aa64_st
, cpu
)) {
1509 if (arm_pamax(cpu
) < 42) {
1519 startlevel
= 3 - sl0
;
1524 if (arm_pamax(cpu
) < 44) {
1531 startlevel
= 3 - sl0
;
1534 g_assert_not_reached();
1538 * Things are simpler for AArch32 EL2, with only 4k pages.
1539 * There is no separate S2InvalidSL function, but AArch32.S2Walk
1540 * begins with walkparms.sl0 in {'1x'}.
1542 assert(stride
== 9);
1546 startlevel
= 2 - sl0
;
1549 /* AArch{64,32}.S2InconsistentSL are functionally equivalent. */
1550 levels
= 3 - startlevel
;
1551 granulebits
= stride
+ 3;
1553 s1_min_iasize
= levels
* stride
+ granulebits
+ 1;
1554 s1_max_iasize
= s1_min_iasize
+ (stride
- 1) + 4;
1556 if (iasize
>= s1_min_iasize
&& iasize
<= s1_max_iasize
) {
1564 static bool lpae_block_desc_valid(ARMCPU
*cpu
, bool ds
,
1565 ARMGranuleSize gran
, int level
)
1568 * See pseudocode AArch46.BlockDescSupported(): block descriptors
1569 * are not valid at all levels, depending on the page size.
1573 return (level
== 0 && ds
) || level
== 1 || level
== 2;
1575 return (level
== 1 && ds
) || level
== 2;
1577 return (level
== 1 && arm_pamax(cpu
) == 52) || level
== 2;
1579 g_assert_not_reached();
1584 * get_phys_addr_lpae: perform one stage of page table walk, LPAE format
1586 * Returns false if the translation was successful. Otherwise, phys_ptr,
1587 * attrs, prot and page_size may not be filled in, and the populated fsr
1588 * value provides information on why the translation aborted, in the format
1589 * of a long-format DFSR/IFSR fault register, with the following caveat:
1590 * the WnR bit is never set (the caller must do this).
1593 * @ptw: Current and next stage parameters for the walk.
1594 * @address: virtual address to get physical address for
1595 * @access_type: MMU_DATA_LOAD, MMU_DATA_STORE or MMU_INST_FETCH
1596 * @result: set on translation success,
1597 * @fi: set to fault info if the translation fails
1599 static bool get_phys_addr_lpae(CPUARMState
*env
, S1Translate
*ptw
,
1601 MMUAccessType access_type
,
1602 GetPhysAddrResult
*result
, ARMMMUFaultInfo
*fi
)
1604 ARMCPU
*cpu
= env_archcpu(env
);
1605 ARMMMUIdx mmu_idx
= ptw
->in_mmu_idx
;
1607 ARMVAParameters param
;
1609 hwaddr descaddr
, indexmask
, indexmask_grainsize
;
1610 uint32_t tableattrs
;
1611 target_ulong page_size
;
1614 int addrsize
, inputsize
, outputsize
;
1615 uint64_t tcr
= regime_tcr(env
, mmu_idx
);
1617 uint32_t el
= regime_el(env
, mmu_idx
);
1618 uint64_t descaddrmask
;
1619 bool aarch64
= arm_el_is_aa64(env
, el
);
1620 uint64_t descriptor
, new_descriptor
;
1621 ARMSecuritySpace out_space
;
1623 /* TODO: This code does not support shareability levels. */
1627 param
= aa64_va_parameters(env
, address
, mmu_idx
,
1628 access_type
!= MMU_INST_FETCH
,
1629 !arm_el_is_aa64(env
, 1));
1633 * If TxSZ is programmed to a value larger than the maximum,
1634 * or smaller than the effective minimum, it is IMPLEMENTATION
1635 * DEFINED whether we behave as if the field were programmed
1636 * within bounds, or if a level 0 Translation fault is generated.
1638 * With FEAT_LVA, fault on less than minimum becomes required,
1639 * so our choice is to always raise the fault.
1641 if (param
.tsz_oob
) {
1642 goto do_translation_fault
;
1645 addrsize
= 64 - 8 * param
.tbi
;
1646 inputsize
= 64 - param
.tsz
;
1649 * Bound PS by PARANGE to find the effective output address size.
1650 * ID_AA64MMFR0 is a read-only register so values outside of the
1651 * supported mappings can be considered an implementation error.
1653 ps
= FIELD_EX64(cpu
->isar
.id_aa64mmfr0
, ID_AA64MMFR0
, PARANGE
);
1654 ps
= MIN(ps
, param
.ps
);
1655 assert(ps
< ARRAY_SIZE(pamax_map
));
1656 outputsize
= pamax_map
[ps
];
1659 * With LPA2, the effective output address (OA) size is at most 48 bits
1660 * unless TCR.DS == 1
1662 if (!param
.ds
&& param
.gran
!= Gran64K
) {
1663 outputsize
= MIN(outputsize
, 48);
1666 param
= aa32_va_parameters(env
, address
, mmu_idx
);
1668 addrsize
= (mmu_idx
== ARMMMUIdx_Stage2
? 40 : 32);
1669 inputsize
= addrsize
- param
.tsz
;
1674 * We determined the region when collecting the parameters, but we
1675 * have not yet validated that the address is valid for the region.
1676 * Extract the top bits and verify that they all match select.
1678 * For aa32, if inputsize == addrsize, then we have selected the
1679 * region by exclusion in aa32_va_parameters and there is no more
1680 * validation to do here.
1682 if (inputsize
< addrsize
) {
1683 target_ulong top_bits
= sextract64(address
, inputsize
,
1684 addrsize
- inputsize
);
1685 if (-top_bits
!= param
.select
) {
1686 /* The gap between the two regions is a Translation fault */
1687 goto do_translation_fault
;
1691 stride
= arm_granule_bits(param
.gran
) - 3;
1694 * Note that QEMU ignores shareability and cacheability attributes,
1695 * so we don't need to do anything with the SH, ORGN, IRGN fields
1696 * in the TTBCR. Similarly, TTBCR:A1 selects whether we get the
1697 * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently
1698 * implement any ASID-like capability so we can ignore it (instead
1699 * we will always flush the TLB any time the ASID is changed).
1701 ttbr
= regime_ttbr(env
, mmu_idx
, param
.select
);
1704 * Here we should have set up all the parameters for the translation:
1705 * inputsize, ttbr, epd, stride, tbi
1710 * Translation table walk disabled => Translation fault on TLB miss
1711 * Note: This is always 0 on 64-bit EL2 and EL3.
1713 goto do_translation_fault
;
1716 if (!regime_is_stage2(mmu_idx
)) {
1718 * The starting level depends on the virtual address size (which can
1719 * be up to 48 bits) and the translation granule size. It indicates
1720 * the number of strides (stride bits at a time) needed to
1721 * consume the bits of the input address. In the pseudocode this is:
1722 * level = 4 - RoundUp((inputsize - grainsize) / stride)
1723 * where their 'inputsize' is our 'inputsize', 'grainsize' is
1724 * our 'stride + 3' and 'stride' is our 'stride'.
1725 * Applying the usual "rounded up m/n is (m+n-1)/n" and simplifying:
1726 * = 4 - (inputsize - stride - 3 + stride - 1) / stride
1727 * = 4 - (inputsize - 4) / stride;
1729 level
= 4 - (inputsize
- 4) / stride
;
1731 int startlevel
= check_s2_mmu_setup(cpu
, aarch64
, tcr
, param
.ds
,
1733 if (startlevel
== INT_MIN
) {
1735 goto do_translation_fault
;
1740 indexmask_grainsize
= MAKE_64BIT_MASK(0, stride
+ 3);
1741 indexmask
= MAKE_64BIT_MASK(0, inputsize
- (stride
* (4 - level
)));
1743 /* Now we can extract the actual base address from the TTBR */
1744 descaddr
= extract64(ttbr
, 0, 48);
1747 * For FEAT_LPA and PS=6, bits [51:48] of descaddr are in [5:2] of TTBR.
1749 * Otherwise, if the base address is out of range, raise AddressSizeFault.
1750 * In the pseudocode, this is !IsZero(baseregister<47:outputsize>),
1751 * but we've just cleared the bits above 47, so simplify the test.
1753 if (outputsize
> 48) {
1754 descaddr
|= extract64(ttbr
, 2, 4) << 48;
1755 } else if (descaddr
>> outputsize
) {
1757 fi
->type
= ARMFault_AddressSize
;
1762 * We rely on this masking to clear the RES0 bits at the bottom of the TTBR
1763 * and also to mask out CnP (bit 0) which could validly be non-zero.
1765 descaddr
&= ~indexmask
;
1768 * For AArch32, the address field in the descriptor goes up to bit 39
1769 * for both v7 and v8. However, for v8 the SBZ bits [47:40] must be 0
1770 * or an AddressSize fault is raised. So for v8 we extract those SBZ
1771 * bits as part of the address, which will be checked via outputsize.
1772 * For AArch64, the address field goes up to bit 47, or 49 with FEAT_LPA2;
1773 * the highest bits of a 52-bit output are placed elsewhere.
1776 descaddrmask
= MAKE_64BIT_MASK(0, 50);
1777 } else if (arm_feature(env
, ARM_FEATURE_V8
)) {
1778 descaddrmask
= MAKE_64BIT_MASK(0, 48);
1780 descaddrmask
= MAKE_64BIT_MASK(0, 40);
1782 descaddrmask
&= ~indexmask_grainsize
;
1786 descaddr
|= (address
>> (stride
* (4 - level
))) & indexmask
;
1790 * Process the NSTable bit from the previous level. This changes
1791 * the table address space and the output space from Secure to
1792 * NonSecure. With RME, the EL3 translation regime does not change
1793 * from Root to NonSecure.
1795 if (ptw
->in_space
== ARMSS_Secure
1796 && !regime_is_stage2(mmu_idx
)
1797 && extract32(tableattrs
, 4, 1)) {
1799 * Stage2_S -> Stage2 or Phys_S -> Phys_NS
1800 * Assert the relative order of the secure/non-secure indexes.
1802 QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_S
+ 1 != ARMMMUIdx_Phys_NS
);
1803 QEMU_BUILD_BUG_ON(ARMMMUIdx_Stage2_S
+ 1 != ARMMMUIdx_Stage2
);
1804 ptw
->in_ptw_idx
+= 1;
1805 ptw
->in_space
= ARMSS_NonSecure
;
1808 if (!S1_ptw_translate(env
, ptw
, descaddr
, fi
)) {
1811 descriptor
= arm_ldq_ptw(env
, ptw
, fi
);
1812 if (fi
->type
!= ARMFault_None
) {
1815 new_descriptor
= descriptor
;
1817 restart_atomic_update
:
1818 if (!(descriptor
& 1) ||
1819 (!(descriptor
& 2) &&
1820 !lpae_block_desc_valid(cpu
, param
.ds
, param
.gran
, level
))) {
1821 /* Invalid, or a block descriptor at an invalid level */
1822 goto do_translation_fault
;
1825 descaddr
= descriptor
& descaddrmask
;
1828 * For FEAT_LPA and PS=6, bits [51:48] of descaddr are in [15:12]
1829 * of descriptor. For FEAT_LPA2 and effective DS, bits [51:50] of
1830 * descaddr are in [9:8]. Otherwise, if descaddr is out of range,
1831 * raise AddressSizeFault.
1833 if (outputsize
> 48) {
1835 descaddr
|= extract64(descriptor
, 8, 2) << 50;
1837 descaddr
|= extract64(descriptor
, 12, 4) << 48;
1839 } else if (descaddr
>> outputsize
) {
1840 fi
->type
= ARMFault_AddressSize
;
1844 if ((descriptor
& 2) && (level
< 3)) {
1846 * Table entry. The top five bits are attributes which may
1847 * propagate down through lower levels of the table (and
1848 * which are all arranged so that 0 means "no effect", so
1849 * we can gather them up by ORing in the bits at each level).
1851 tableattrs
|= extract64(descriptor
, 59, 5);
1853 indexmask
= indexmask_grainsize
;
1858 * Block entry at level 1 or 2, or page entry at level 3.
1859 * These are basically the same thing, although the number
1860 * of bits we pull in from the vaddr varies. Note that although
1861 * descaddrmask masks enough of the low bits of the descriptor
1862 * to give a correct page or table address, the address field
1863 * in a block descriptor is smaller; so we need to explicitly
1864 * clear the lower bits here before ORing in the low vaddr bits.
1866 * Afterward, descaddr is the final physical address.
1868 page_size
= (1ULL << ((stride
* (4 - level
)) + 3));
1869 descaddr
&= ~(hwaddr
)(page_size
- 1);
1870 descaddr
|= (address
& (page_size
- 1));
1872 if (likely(!ptw
->in_debug
)) {
1875 * If HA is enabled, prepare to update the descriptor below.
1876 * Otherwise, pass the access fault on to software.
1878 if (!(descriptor
& (1 << 10))) {
1880 new_descriptor
|= 1 << 10; /* AF */
1882 fi
->type
= ARMFault_AccessFlag
;
1889 * If HD is enabled, pre-emptively set/clear the appropriate AP/S2AP
1890 * bit for writeback. The actual write protection test may still be
1891 * overridden by tableattrs, to be merged below.
1894 && extract64(descriptor
, 51, 1) /* DBM */
1895 && access_type
== MMU_DATA_STORE
) {
1896 if (regime_is_stage2(mmu_idx
)) {
1897 new_descriptor
|= 1ull << 7; /* set S2AP[1] */
1899 new_descriptor
&= ~(1ull << 7); /* clear AP[2] */
1905 * Extract attributes from the (modified) descriptor, and apply
1906 * table descriptors. Stage 2 table descriptors do not include
1907 * any attribute fields. HPD disables all the table attributes
1908 * except NSTable (which we have already handled).
1910 attrs
= new_descriptor
& (MAKE_64BIT_MASK(2, 10) | MAKE_64BIT_MASK(50, 14));
1911 if (!regime_is_stage2(mmu_idx
)) {
1913 attrs
|= extract64(tableattrs
, 0, 2) << 53; /* XN, PXN */
1915 * The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1
1916 * means "force PL1 access only", which means forcing AP[1] to 0.
1918 attrs
&= ~(extract64(tableattrs
, 2, 1) << 6); /* !APT[0] => AP[1] */
1919 attrs
|= extract32(tableattrs
, 3, 1) << 7; /* APT[1] => AP[2] */
1923 ap
= extract32(attrs
, 6, 2);
1924 out_space
= ptw
->in_space
;
1925 if (regime_is_stage2(mmu_idx
)) {
1927 * R_GYNXY: For stage2 in Realm security state, bit 55 is NS.
1928 * The bit remains ignored for other security states.
1929 * R_YMCSL: Executing an insn fetched from non-Realm causes
1930 * a stage2 permission fault.
1932 if (out_space
== ARMSS_Realm
&& extract64(attrs
, 55, 1)) {
1933 out_space
= ARMSS_NonSecure
;
1934 result
->f
.prot
= get_S2prot_noexecute(ap
);
1936 xn
= extract64(attrs
, 53, 2);
1937 result
->f
.prot
= get_S2prot(env
, ap
, xn
, ptw
->in_s1_is_el0
);
1940 int nse
, ns
= extract32(attrs
, 5, 1);
1941 switch (out_space
) {
1944 * R_GVZML: Bit 11 becomes the NSE field in the EL3 regime.
1945 * R_XTYPW: NSE and NS together select the output pa space.
1947 nse
= extract32(attrs
, 11, 1);
1948 out_space
= (nse
<< 1) | ns
;
1949 if (out_space
== ARMSS_Secure
&&
1950 !cpu_isar_feature(aa64_sel2
, cpu
)) {
1951 out_space
= ARMSS_NonSecure
;
1956 out_space
= ARMSS_NonSecure
;
1961 case ARMMMUIdx_Stage1_E0
:
1962 case ARMMMUIdx_Stage1_E1
:
1963 case ARMMMUIdx_Stage1_E1_PAN
:
1964 /* I_CZPRF: For Realm EL1&0 stage1, NS bit is RES0. */
1967 case ARMMMUIdx_E20_0
:
1968 case ARMMMUIdx_E20_2
:
1969 case ARMMMUIdx_E20_2_PAN
:
1971 * R_LYKFZ, R_WGRZN: For Realm EL2 and EL2&1,
1972 * NS changes the output to non-secure space.
1975 out_space
= ARMSS_NonSecure
;
1979 g_assert_not_reached();
1982 case ARMSS_NonSecure
:
1983 /* R_QRMFF: For NonSecure state, the NS bit is RES0. */
1986 g_assert_not_reached();
1988 xn
= extract64(attrs
, 54, 1);
1989 pxn
= extract64(attrs
, 53, 1);
1992 * Note that we modified ptw->in_space earlier for NSTable, but
1993 * result->f.attrs retains a copy of the original security space.
1995 result
->f
.prot
= get_S1prot(env
, mmu_idx
, aarch64
, ap
, xn
, pxn
,
1996 result
->f
.attrs
.space
, out_space
);
1999 if (!(result
->f
.prot
& (1 << access_type
))) {
2000 fi
->type
= ARMFault_Permission
;
2004 /* If FEAT_HAFDBS has made changes, update the PTE. */
2005 if (new_descriptor
!= descriptor
) {
2006 new_descriptor
= arm_casq_ptw(env
, descriptor
, new_descriptor
, ptw
, fi
);
2007 if (fi
->type
!= ARMFault_None
) {
2011 * I_YZSVV says that if the in-memory descriptor has changed,
2012 * then we must use the information in that new value
2013 * (which might include a different output address, different
2014 * attributes, or generate a fault).
2015 * Restart the handling of the descriptor value from scratch.
2017 if (new_descriptor
!= descriptor
) {
2018 descriptor
= new_descriptor
;
2019 goto restart_atomic_update
;
2023 result
->f
.attrs
.space
= out_space
;
2024 result
->f
.attrs
.secure
= arm_space_is_secure(out_space
);
2026 if (regime_is_stage2(mmu_idx
)) {
2027 result
->cacheattrs
.is_s2_format
= true;
2028 result
->cacheattrs
.attrs
= extract32(attrs
, 2, 4);
2030 /* Index into MAIR registers for cache attributes */
2031 uint8_t attrindx
= extract32(attrs
, 2, 3);
2032 uint64_t mair
= env
->cp15
.mair_el
[regime_el(env
, mmu_idx
)];
2033 assert(attrindx
<= 7);
2034 result
->cacheattrs
.is_s2_format
= false;
2035 result
->cacheattrs
.attrs
= extract64(mair
, attrindx
* 8, 8);
2037 /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */
2038 if (aarch64
&& cpu_isar_feature(aa64_bti
, cpu
)) {
2039 result
->f
.extra
.arm
.guarded
= extract64(attrs
, 50, 1); /* GP */
2044 * For FEAT_LPA2 and effective DS, the SH field in the attributes
2045 * was re-purposed for output address bits. The SH attribute in
2046 * that case comes from TCR_ELx, which we extracted earlier.
2049 result
->cacheattrs
.shareability
= param
.sh
;
2051 result
->cacheattrs
.shareability
= extract32(attrs
, 8, 2);
2054 result
->f
.phys_addr
= descaddr
;
2055 result
->f
.lg_page_size
= ctz64(page_size
);
2058 do_translation_fault
:
2059 fi
->type
= ARMFault_Translation
;
2062 /* Retain the existing stage 2 fi->level */
2066 fi
->stage2
= regime_is_stage2(mmu_idx
);
2068 fi
->s1ns
= fault_s1ns(ptw
->in_space
, mmu_idx
);
2072 static bool get_phys_addr_pmsav5(CPUARMState
*env
,
2075 MMUAccessType access_type
,
2076 GetPhysAddrResult
*result
,
2077 ARMMMUFaultInfo
*fi
)
2082 ARMMMUIdx mmu_idx
= ptw
->in_mmu_idx
;
2083 bool is_user
= regime_is_user(env
, mmu_idx
);
2085 if (regime_translation_disabled(env
, mmu_idx
, ptw
->in_space
)) {
2087 result
->f
.phys_addr
= address
;
2088 result
->f
.prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
2092 result
->f
.phys_addr
= address
;
2093 for (n
= 7; n
>= 0; n
--) {
2094 base
= env
->cp15
.c6_region
[n
];
2095 if ((base
& 1) == 0) {
2098 mask
= 1 << ((base
>> 1) & 0x1f);
2099 /* Keep this shift separate from the above to avoid an
2100 (undefined) << 32. */
2101 mask
= (mask
<< 1) - 1;
2102 if (((base
^ address
) & ~mask
) == 0) {
2107 fi
->type
= ARMFault_Background
;
2111 if (access_type
== MMU_INST_FETCH
) {
2112 mask
= env
->cp15
.pmsav5_insn_ap
;
2114 mask
= env
->cp15
.pmsav5_data_ap
;
2116 mask
= (mask
>> (n
* 4)) & 0xf;
2119 fi
->type
= ARMFault_Permission
;
2124 fi
->type
= ARMFault_Permission
;
2128 result
->f
.prot
= PAGE_READ
| PAGE_WRITE
;
2131 result
->f
.prot
= PAGE_READ
;
2133 result
->f
.prot
|= PAGE_WRITE
;
2137 result
->f
.prot
= PAGE_READ
| PAGE_WRITE
;
2141 fi
->type
= ARMFault_Permission
;
2145 result
->f
.prot
= PAGE_READ
;
2148 result
->f
.prot
= PAGE_READ
;
2151 /* Bad permission. */
2152 fi
->type
= ARMFault_Permission
;
2156 result
->f
.prot
|= PAGE_EXEC
;
2160 static void get_phys_addr_pmsav7_default(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
2161 int32_t address
, uint8_t *prot
)
2163 if (!arm_feature(env
, ARM_FEATURE_M
)) {
2164 *prot
= PAGE_READ
| PAGE_WRITE
;
2166 case 0xF0000000 ... 0xFFFFFFFF:
2167 if (regime_sctlr(env
, mmu_idx
) & SCTLR_V
) {
2168 /* hivecs execing is ok */
2172 case 0x00000000 ... 0x7FFFFFFF:
2177 /* Default system address map for M profile cores.
2178 * The architecture specifies which regions are execute-never;
2179 * at the MPU level no other checks are defined.
2182 case 0x00000000 ... 0x1fffffff: /* ROM */
2183 case 0x20000000 ... 0x3fffffff: /* SRAM */
2184 case 0x60000000 ... 0x7fffffff: /* RAM */
2185 case 0x80000000 ... 0x9fffffff: /* RAM */
2186 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
2188 case 0x40000000 ... 0x5fffffff: /* Peripheral */
2189 case 0xa0000000 ... 0xbfffffff: /* Device */
2190 case 0xc0000000 ... 0xdfffffff: /* Device */
2191 case 0xe0000000 ... 0xffffffff: /* System */
2192 *prot
= PAGE_READ
| PAGE_WRITE
;
2195 g_assert_not_reached();
2200 static bool m_is_ppb_region(CPUARMState
*env
, uint32_t address
)
2202 /* True if address is in the M profile PPB region 0xe0000000 - 0xe00fffff */
2203 return arm_feature(env
, ARM_FEATURE_M
) &&
2204 extract32(address
, 20, 12) == 0xe00;
2207 static bool m_is_system_region(CPUARMState
*env
, uint32_t address
)
2210 * True if address is in the M profile system region
2211 * 0xe0000000 - 0xffffffff
2213 return arm_feature(env
, ARM_FEATURE_M
) && extract32(address
, 29, 3) == 0x7;
2216 static bool pmsav7_use_background_region(ARMCPU
*cpu
, ARMMMUIdx mmu_idx
,
2217 bool is_secure
, bool is_user
)
2220 * Return true if we should use the default memory map as a
2221 * "background" region if there are no hits against any MPU regions.
2223 CPUARMState
*env
= &cpu
->env
;
2229 if (arm_feature(env
, ARM_FEATURE_M
)) {
2230 return env
->v7m
.mpu_ctrl
[is_secure
] & R_V7M_MPU_CTRL_PRIVDEFENA_MASK
;
2233 if (mmu_idx
== ARMMMUIdx_Stage2
) {
2237 return regime_sctlr(env
, mmu_idx
) & SCTLR_BR
;
2240 static bool get_phys_addr_pmsav7(CPUARMState
*env
,
2243 MMUAccessType access_type
,
2244 GetPhysAddrResult
*result
,
2245 ARMMMUFaultInfo
*fi
)
2247 ARMCPU
*cpu
= env_archcpu(env
);
2249 ARMMMUIdx mmu_idx
= ptw
->in_mmu_idx
;
2250 bool is_user
= regime_is_user(env
, mmu_idx
);
2251 bool secure
= arm_space_is_secure(ptw
->in_space
);
2253 result
->f
.phys_addr
= address
;
2254 result
->f
.lg_page_size
= TARGET_PAGE_BITS
;
2257 if (regime_translation_disabled(env
, mmu_idx
, ptw
->in_space
) ||
2258 m_is_ppb_region(env
, address
)) {
2260 * MPU disabled or M profile PPB access: use default memory map.
2261 * The other case which uses the default memory map in the
2262 * v7M ARM ARM pseudocode is exception vector reads from the vector
2263 * table. In QEMU those accesses are done in arm_v7m_load_vector(),
2264 * which always does a direct read using address_space_ldl(), rather
2265 * than going via this function, so we don't need to check that here.
2267 get_phys_addr_pmsav7_default(env
, mmu_idx
, address
, &result
->f
.prot
);
2268 } else { /* MPU enabled */
2269 for (n
= (int)cpu
->pmsav7_dregion
- 1; n
>= 0; n
--) {
2271 uint32_t base
= env
->pmsav7
.drbar
[n
];
2272 uint32_t rsize
= extract32(env
->pmsav7
.drsr
[n
], 1, 5);
2276 if (!(env
->pmsav7
.drsr
[n
] & 0x1)) {
2281 qemu_log_mask(LOG_GUEST_ERROR
,
2282 "DRSR[%d]: Rsize field cannot be 0\n", n
);
2286 rmask
= (1ull << rsize
) - 1;
2289 qemu_log_mask(LOG_GUEST_ERROR
,
2290 "DRBAR[%d]: 0x%" PRIx32
" misaligned "
2291 "to DRSR region size, mask = 0x%" PRIx32
"\n",
2296 if (address
< base
|| address
> base
+ rmask
) {
2298 * Address not in this region. We must check whether the
2299 * region covers addresses in the same page as our address.
2300 * In that case we must not report a size that covers the
2301 * whole page for a subsequent hit against a different MPU
2302 * region or the background region, because it would result in
2303 * incorrect TLB hits for subsequent accesses to addresses that
2304 * are in this MPU region.
2306 if (ranges_overlap(base
, rmask
,
2307 address
& TARGET_PAGE_MASK
,
2308 TARGET_PAGE_SIZE
)) {
2309 result
->f
.lg_page_size
= 0;
2314 /* Region matched */
2316 if (rsize
>= 8) { /* no subregions for regions < 256 bytes */
2318 uint32_t srdis_mask
;
2320 rsize
-= 3; /* sub region size (power of 2) */
2321 snd
= ((address
- base
) >> rsize
) & 0x7;
2322 srdis
= extract32(env
->pmsav7
.drsr
[n
], snd
+ 8, 1);
2324 srdis_mask
= srdis
? 0x3 : 0x0;
2325 for (i
= 2; i
<= 8 && rsize
< TARGET_PAGE_BITS
; i
*= 2) {
2327 * This will check in groups of 2, 4 and then 8, whether
2328 * the subregion bits are consistent. rsize is incremented
2329 * back up to give the region size, considering consistent
2330 * adjacent subregions as one region. Stop testing if rsize
2331 * is already big enough for an entire QEMU page.
2333 int snd_rounded
= snd
& ~(i
- 1);
2334 uint32_t srdis_multi
= extract32(env
->pmsav7
.drsr
[n
],
2335 snd_rounded
+ 8, i
);
2336 if (srdis_mask
^ srdis_multi
) {
2339 srdis_mask
= (srdis_mask
<< i
) | srdis_mask
;
2346 if (rsize
< TARGET_PAGE_BITS
) {
2347 result
->f
.lg_page_size
= rsize
;
2352 if (n
== -1) { /* no hits */
2353 if (!pmsav7_use_background_region(cpu
, mmu_idx
, secure
, is_user
)) {
2354 /* background fault */
2355 fi
->type
= ARMFault_Background
;
2358 get_phys_addr_pmsav7_default(env
, mmu_idx
, address
,
2360 } else { /* a MPU hit! */
2361 uint32_t ap
= extract32(env
->pmsav7
.dracr
[n
], 8, 3);
2362 uint32_t xn
= extract32(env
->pmsav7
.dracr
[n
], 12, 1);
2364 if (m_is_system_region(env
, address
)) {
2365 /* System space is always execute never */
2369 if (is_user
) { /* User mode AP bit decoding */
2374 break; /* no access */
2376 result
->f
.prot
|= PAGE_WRITE
;
2380 result
->f
.prot
|= PAGE_READ
| PAGE_EXEC
;
2383 /* for v7M, same as 6; for R profile a reserved value */
2384 if (arm_feature(env
, ARM_FEATURE_M
)) {
2385 result
->f
.prot
|= PAGE_READ
| PAGE_EXEC
;
2390 qemu_log_mask(LOG_GUEST_ERROR
,
2391 "DRACR[%d]: Bad value for AP bits: 0x%"
2392 PRIx32
"\n", n
, ap
);
2394 } else { /* Priv. mode AP bits decoding */
2397 break; /* no access */
2401 result
->f
.prot
|= PAGE_WRITE
;
2405 result
->f
.prot
|= PAGE_READ
| PAGE_EXEC
;
2408 /* for v7M, same as 6; for R profile a reserved value */
2409 if (arm_feature(env
, ARM_FEATURE_M
)) {
2410 result
->f
.prot
|= PAGE_READ
| PAGE_EXEC
;
2415 qemu_log_mask(LOG_GUEST_ERROR
,
2416 "DRACR[%d]: Bad value for AP bits: 0x%"
2417 PRIx32
"\n", n
, ap
);
2423 result
->f
.prot
&= ~PAGE_EXEC
;
2428 fi
->type
= ARMFault_Permission
;
2430 return !(result
->f
.prot
& (1 << access_type
));
2433 static uint32_t *regime_rbar(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
2436 if (regime_el(env
, mmu_idx
) == 2) {
2437 return env
->pmsav8
.hprbar
;
2439 return env
->pmsav8
.rbar
[secure
];
2443 static uint32_t *regime_rlar(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
2446 if (regime_el(env
, mmu_idx
) == 2) {
2447 return env
->pmsav8
.hprlar
;
2449 return env
->pmsav8
.rlar
[secure
];
2453 bool pmsav8_mpu_lookup(CPUARMState
*env
, uint32_t address
,
2454 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
2455 bool secure
, GetPhysAddrResult
*result
,
2456 ARMMMUFaultInfo
*fi
, uint32_t *mregion
)
2459 * Perform a PMSAv8 MPU lookup (without also doing the SAU check
2460 * that a full phys-to-virt translation does).
2461 * mregion is (if not NULL) set to the region number which matched,
2462 * or -1 if no region number is returned (MPU off, address did not
2463 * hit a region, address hit in multiple regions).
2464 * If the region hit doesn't cover the entire TARGET_PAGE the address
2465 * is within, then we set the result page_size to 1 to force the
2466 * memory system to use a subpage.
2468 ARMCPU
*cpu
= env_archcpu(env
);
2469 bool is_user
= regime_is_user(env
, mmu_idx
);
2471 int matchregion
= -1;
2473 uint32_t addr_page_base
= address
& TARGET_PAGE_MASK
;
2474 uint32_t addr_page_limit
= addr_page_base
+ (TARGET_PAGE_SIZE
- 1);
2477 if (regime_el(env
, mmu_idx
) == 2) {
2478 region_counter
= cpu
->pmsav8r_hdregion
;
2480 region_counter
= cpu
->pmsav7_dregion
;
2483 result
->f
.lg_page_size
= TARGET_PAGE_BITS
;
2484 result
->f
.phys_addr
= address
;
2490 if (mmu_idx
== ARMMMUIdx_Stage2
) {
2495 * Unlike the ARM ARM pseudocode, we don't need to check whether this
2496 * was an exception vector read from the vector table (which is always
2497 * done using the default system address map), because those accesses
2498 * are done in arm_v7m_load_vector(), which always does a direct
2499 * read using address_space_ldl(), rather than going via this function.
2501 if (regime_translation_disabled(env
, mmu_idx
, arm_secure_to_space(secure
))) {
2504 } else if (m_is_ppb_region(env
, address
)) {
2507 if (pmsav7_use_background_region(cpu
, mmu_idx
, secure
, is_user
)) {
2512 if (arm_feature(env
, ARM_FEATURE_M
)) {
2519 for (n
= region_counter
- 1; n
>= 0; n
--) {
2522 * Note that the base address is bits [31:x] from the register
2523 * with bits [x-1:0] all zeroes, but the limit address is bits
2524 * [31:x] from the register with bits [x:0] all ones. Where x is
2525 * 5 for Cortex-M and 6 for Cortex-R
2527 uint32_t base
= regime_rbar(env
, mmu_idx
, secure
)[n
] & ~bitmask
;
2528 uint32_t limit
= regime_rlar(env
, mmu_idx
, secure
)[n
] | bitmask
;
2530 if (!(regime_rlar(env
, mmu_idx
, secure
)[n
] & 0x1)) {
2531 /* Region disabled */
2535 if (address
< base
|| address
> limit
) {
2537 * Address not in this region. We must check whether the
2538 * region covers addresses in the same page as our address.
2539 * In that case we must not report a size that covers the
2540 * whole page for a subsequent hit against a different MPU
2541 * region or the background region, because it would result in
2542 * incorrect TLB hits for subsequent accesses to addresses that
2543 * are in this MPU region.
2545 if (limit
>= base
&&
2546 ranges_overlap(base
, limit
- base
+ 1,
2548 TARGET_PAGE_SIZE
)) {
2549 result
->f
.lg_page_size
= 0;
2554 if (base
> addr_page_base
|| limit
< addr_page_limit
) {
2555 result
->f
.lg_page_size
= 0;
2558 if (matchregion
!= -1) {
2560 * Multiple regions match -- always a failure (unlike
2561 * PMSAv7 where highest-numbered-region wins)
2563 fi
->type
= ARMFault_Permission
;
2564 if (arm_feature(env
, ARM_FEATURE_M
)) {
2576 if (arm_feature(env
, ARM_FEATURE_M
)) {
2577 fi
->type
= ARMFault_Background
;
2579 fi
->type
= ARMFault_Permission
;
2584 if (matchregion
== -1) {
2585 /* hit using the background region */
2586 get_phys_addr_pmsav7_default(env
, mmu_idx
, address
, &result
->f
.prot
);
2588 uint32_t matched_rbar
= regime_rbar(env
, mmu_idx
, secure
)[matchregion
];
2589 uint32_t matched_rlar
= regime_rlar(env
, mmu_idx
, secure
)[matchregion
];
2590 uint32_t ap
= extract32(matched_rbar
, 1, 2);
2591 uint32_t xn
= extract32(matched_rbar
, 0, 1);
2594 if (arm_feature(env
, ARM_FEATURE_V8_1M
)) {
2595 pxn
= extract32(matched_rlar
, 4, 1);
2598 if (m_is_system_region(env
, address
)) {
2599 /* System space is always execute never */
2603 if (regime_el(env
, mmu_idx
) == 2) {
2604 result
->f
.prot
= simple_ap_to_rw_prot_is_user(ap
,
2605 mmu_idx
!= ARMMMUIdx_E2
);
2607 result
->f
.prot
= simple_ap_to_rw_prot(env
, mmu_idx
, ap
);
2610 if (!arm_feature(env
, ARM_FEATURE_M
)) {
2611 uint8_t attrindx
= extract32(matched_rlar
, 1, 3);
2612 uint64_t mair
= env
->cp15
.mair_el
[regime_el(env
, mmu_idx
)];
2613 uint8_t sh
= extract32(matched_rlar
, 3, 2);
2615 if (regime_sctlr(env
, mmu_idx
) & SCTLR_WXN
&&
2616 result
->f
.prot
& PAGE_WRITE
&& mmu_idx
!= ARMMMUIdx_Stage2
) {
2620 if ((regime_el(env
, mmu_idx
) == 1) &&
2621 regime_sctlr(env
, mmu_idx
) & SCTLR_UWXN
&& ap
== 0x1) {
2625 result
->cacheattrs
.is_s2_format
= false;
2626 result
->cacheattrs
.attrs
= extract64(mair
, attrindx
* 8, 8);
2627 result
->cacheattrs
.shareability
= sh
;
2630 if (result
->f
.prot
&& !xn
&& !(pxn
&& !is_user
)) {
2631 result
->f
.prot
|= PAGE_EXEC
;
2635 *mregion
= matchregion
;
2639 fi
->type
= ARMFault_Permission
;
2640 if (arm_feature(env
, ARM_FEATURE_M
)) {
2643 return !(result
->f
.prot
& (1 << access_type
));
2646 static bool v8m_is_sau_exempt(CPUARMState
*env
,
2647 uint32_t address
, MMUAccessType access_type
)
2650 * The architecture specifies that certain address ranges are
2651 * exempt from v8M SAU/IDAU checks.
2654 (access_type
== MMU_INST_FETCH
&& m_is_system_region(env
, address
)) ||
2655 (address
>= 0xe0000000 && address
<= 0xe0002fff) ||
2656 (address
>= 0xe000e000 && address
<= 0xe000efff) ||
2657 (address
>= 0xe002e000 && address
<= 0xe002efff) ||
2658 (address
>= 0xe0040000 && address
<= 0xe0041fff) ||
2659 (address
>= 0xe00ff000 && address
<= 0xe00fffff);
2662 void v8m_security_lookup(CPUARMState
*env
, uint32_t address
,
2663 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
2664 bool is_secure
, V8M_SAttributes
*sattrs
)
2667 * Look up the security attributes for this address. Compare the
2668 * pseudocode SecurityCheck() function.
2669 * We assume the caller has zero-initialized *sattrs.
2671 ARMCPU
*cpu
= env_archcpu(env
);
2673 bool idau_exempt
= false, idau_ns
= true, idau_nsc
= true;
2674 int idau_region
= IREGION_NOTVALID
;
2675 uint32_t addr_page_base
= address
& TARGET_PAGE_MASK
;
2676 uint32_t addr_page_limit
= addr_page_base
+ (TARGET_PAGE_SIZE
- 1);
2679 IDAUInterfaceClass
*iic
= IDAU_INTERFACE_GET_CLASS(cpu
->idau
);
2680 IDAUInterface
*ii
= IDAU_INTERFACE(cpu
->idau
);
2682 iic
->check(ii
, address
, &idau_region
, &idau_exempt
, &idau_ns
,
2686 if (access_type
== MMU_INST_FETCH
&& extract32(address
, 28, 4) == 0xf) {
2687 /* 0xf0000000..0xffffffff is always S for insn fetches */
2691 if (idau_exempt
|| v8m_is_sau_exempt(env
, address
, access_type
)) {
2692 sattrs
->ns
= !is_secure
;
2696 if (idau_region
!= IREGION_NOTVALID
) {
2697 sattrs
->irvalid
= true;
2698 sattrs
->iregion
= idau_region
;
2701 switch (env
->sau
.ctrl
& 3) {
2702 case 0: /* SAU.ENABLE == 0, SAU.ALLNS == 0 */
2704 case 2: /* SAU.ENABLE == 0, SAU.ALLNS == 1 */
2707 default: /* SAU.ENABLE == 1 */
2708 for (r
= 0; r
< cpu
->sau_sregion
; r
++) {
2709 if (env
->sau
.rlar
[r
] & 1) {
2710 uint32_t base
= env
->sau
.rbar
[r
] & ~0x1f;
2711 uint32_t limit
= env
->sau
.rlar
[r
] | 0x1f;
2713 if (base
<= address
&& limit
>= address
) {
2714 if (base
> addr_page_base
|| limit
< addr_page_limit
) {
2715 sattrs
->subpage
= true;
2717 if (sattrs
->srvalid
) {
2719 * If we hit in more than one region then we must report
2720 * as Secure, not NS-Callable, with no valid region
2724 sattrs
->nsc
= false;
2725 sattrs
->sregion
= 0;
2726 sattrs
->srvalid
= false;
2729 if (env
->sau
.rlar
[r
] & 2) {
2734 sattrs
->srvalid
= true;
2735 sattrs
->sregion
= r
;
2739 * Address not in this region. We must check whether the
2740 * region covers addresses in the same page as our address.
2741 * In that case we must not report a size that covers the
2742 * whole page for a subsequent hit against a different MPU
2743 * region or the background region, because it would result
2744 * in incorrect TLB hits for subsequent accesses to
2745 * addresses that are in this MPU region.
2747 if (limit
>= base
&&
2748 ranges_overlap(base
, limit
- base
+ 1,
2750 TARGET_PAGE_SIZE
)) {
2751 sattrs
->subpage
= true;
2760 * The IDAU will override the SAU lookup results if it specifies
2761 * higher security than the SAU does.
2764 if (sattrs
->ns
|| (!idau_nsc
&& sattrs
->nsc
)) {
2766 sattrs
->nsc
= idau_nsc
;
2771 static bool get_phys_addr_pmsav8(CPUARMState
*env
,
2774 MMUAccessType access_type
,
2775 GetPhysAddrResult
*result
,
2776 ARMMMUFaultInfo
*fi
)
2778 V8M_SAttributes sattrs
= {};
2779 ARMMMUIdx mmu_idx
= ptw
->in_mmu_idx
;
2780 bool secure
= arm_space_is_secure(ptw
->in_space
);
2783 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
2784 v8m_security_lookup(env
, address
, access_type
, mmu_idx
,
2786 if (access_type
== MMU_INST_FETCH
) {
2788 * Instruction fetches always use the MMU bank and the
2789 * transaction attribute determined by the fetch address,
2790 * regardless of CPU state. This is painful for QEMU
2791 * to handle, because it would mean we need to encode
2792 * into the mmu_idx not just the (user, negpri) information
2793 * for the current security state but also that for the
2794 * other security state, which would balloon the number
2795 * of mmu_idx values needed alarmingly.
2796 * Fortunately we can avoid this because it's not actually
2797 * possible to arbitrarily execute code from memory with
2798 * the wrong security attribute: it will always generate
2799 * an exception of some kind or another, apart from the
2800 * special case of an NS CPU executing an SG instruction
2801 * in S&NSC memory. So we always just fail the translation
2802 * here and sort things out in the exception handler
2803 * (including possibly emulating an SG instruction).
2805 if (sattrs
.ns
!= !secure
) {
2807 fi
->type
= ARMFault_QEMU_NSCExec
;
2809 fi
->type
= ARMFault_QEMU_SFault
;
2811 result
->f
.lg_page_size
= sattrs
.subpage
? 0 : TARGET_PAGE_BITS
;
2812 result
->f
.phys_addr
= address
;
2818 * For data accesses we always use the MMU bank indicated
2819 * by the current CPU state, but the security attributes
2820 * might downgrade a secure access to nonsecure.
2823 result
->f
.attrs
.secure
= false;
2824 result
->f
.attrs
.space
= ARMSS_NonSecure
;
2825 } else if (!secure
) {
2827 * NS access to S memory must fault.
2828 * Architecturally we should first check whether the
2829 * MPU information for this address indicates that we
2830 * are doing an unaligned access to Device memory, which
2831 * should generate a UsageFault instead. QEMU does not
2832 * currently check for that kind of unaligned access though.
2833 * If we added it we would need to do so as a special case
2834 * for M_FAKE_FSR_SFAULT in arm_v7m_cpu_do_interrupt().
2836 fi
->type
= ARMFault_QEMU_SFault
;
2837 result
->f
.lg_page_size
= sattrs
.subpage
? 0 : TARGET_PAGE_BITS
;
2838 result
->f
.phys_addr
= address
;
2845 ret
= pmsav8_mpu_lookup(env
, address
, access_type
, mmu_idx
, secure
,
2847 if (sattrs
.subpage
) {
2848 result
->f
.lg_page_size
= 0;
2854 * Translate from the 4-bit stage 2 representation of
2855 * memory attributes (without cache-allocation hints) to
2856 * the 8-bit representation of the stage 1 MAIR registers
2857 * (which includes allocation hints).
2859 * ref: shared/translation/attrs/S2AttrDecode()
2860 * .../S2ConvertAttrsHints()
2862 static uint8_t convert_stage2_attrs(uint64_t hcr
, uint8_t s2attrs
)
2864 uint8_t hiattr
= extract32(s2attrs
, 2, 2);
2865 uint8_t loattr
= extract32(s2attrs
, 0, 2);
2866 uint8_t hihint
= 0, lohint
= 0;
2868 if (hiattr
!= 0) { /* normal memory */
2869 if (hcr
& HCR_CD
) { /* cache disabled */
2870 hiattr
= loattr
= 1; /* non-cacheable */
2872 if (hiattr
!= 1) { /* Write-through or write-back */
2873 hihint
= 3; /* RW allocate */
2875 if (loattr
!= 1) { /* Write-through or write-back */
2876 lohint
= 3; /* RW allocate */
2881 return (hiattr
<< 6) | (hihint
<< 4) | (loattr
<< 2) | lohint
;
2885 * Combine either inner or outer cacheability attributes for normal
2886 * memory, according to table D4-42 and pseudocode procedure
2887 * CombineS1S2AttrHints() of ARM DDI 0487B.b (the ARMv8 ARM).
2889 * NB: only stage 1 includes allocation hints (RW bits), leading to
2892 static uint8_t combine_cacheattr_nibble(uint8_t s1
, uint8_t s2
)
2894 if (s1
== 4 || s2
== 4) {
2895 /* non-cacheable has precedence */
2897 } else if (extract32(s1
, 2, 2) == 0 || extract32(s1
, 2, 2) == 2) {
2898 /* stage 1 write-through takes precedence */
2900 } else if (extract32(s2
, 2, 2) == 2) {
2901 /* stage 2 write-through takes precedence, but the allocation hint
2902 * is still taken from stage 1
2904 return (2 << 2) | extract32(s1
, 0, 2);
2905 } else { /* write-back */
2911 * Combine the memory type and cacheability attributes of
2912 * s1 and s2 for the HCR_EL2.FWB == 0 case, returning the
2913 * combined attributes in MAIR_EL1 format.
2915 static uint8_t combined_attrs_nofwb(uint64_t hcr
,
2916 ARMCacheAttrs s1
, ARMCacheAttrs s2
)
2918 uint8_t s1lo
, s2lo
, s1hi
, s2hi
, s2_mair_attrs
, ret_attrs
;
2920 if (s2
.is_s2_format
) {
2921 s2_mair_attrs
= convert_stage2_attrs(hcr
, s2
.attrs
);
2923 s2_mair_attrs
= s2
.attrs
;
2926 s1lo
= extract32(s1
.attrs
, 0, 4);
2927 s2lo
= extract32(s2_mair_attrs
, 0, 4);
2928 s1hi
= extract32(s1
.attrs
, 4, 4);
2929 s2hi
= extract32(s2_mair_attrs
, 4, 4);
2931 /* Combine memory type and cacheability attributes */
2932 if (s1hi
== 0 || s2hi
== 0) {
2933 /* Device has precedence over normal */
2934 if (s1lo
== 0 || s2lo
== 0) {
2935 /* nGnRnE has precedence over anything */
2937 } else if (s1lo
== 4 || s2lo
== 4) {
2938 /* non-Reordering has precedence over Reordering */
2939 ret_attrs
= 4; /* nGnRE */
2940 } else if (s1lo
== 8 || s2lo
== 8) {
2941 /* non-Gathering has precedence over Gathering */
2942 ret_attrs
= 8; /* nGRE */
2944 ret_attrs
= 0xc; /* GRE */
2946 } else { /* Normal memory */
2947 /* Outer/inner cacheability combine independently */
2948 ret_attrs
= combine_cacheattr_nibble(s1hi
, s2hi
) << 4
2949 | combine_cacheattr_nibble(s1lo
, s2lo
);
2954 static uint8_t force_cacheattr_nibble_wb(uint8_t attr
)
2957 * Given the 4 bits specifying the outer or inner cacheability
2958 * in MAIR format, return a value specifying Normal Write-Back,
2959 * with the allocation and transient hints taken from the input
2960 * if the input specified some kind of cacheable attribute.
2962 if (attr
== 0 || attr
== 4) {
2964 * 0 == an UNPREDICTABLE encoding
2965 * 4 == Non-cacheable
2966 * Either way, force Write-Back RW allocate non-transient
2970 /* Change WriteThrough to WriteBack, keep allocation and transient hints */
2975 * Combine the memory type and cacheability attributes of
2976 * s1 and s2 for the HCR_EL2.FWB == 1 case, returning the
2977 * combined attributes in MAIR_EL1 format.
2979 static uint8_t combined_attrs_fwb(ARMCacheAttrs s1
, ARMCacheAttrs s2
)
2981 assert(s2
.is_s2_format
&& !s1
.is_s2_format
);
2985 /* Use stage 1 attributes */
2989 * Force Normal Write-Back. Note that if S1 is Normal cacheable
2990 * then we take the allocation hints from it; otherwise it is
2991 * RW allocate, non-transient.
2993 if ((s1
.attrs
& 0xf0) == 0) {
2997 /* Need to check the Inner and Outer nibbles separately */
2998 return force_cacheattr_nibble_wb(s1
.attrs
& 0xf) |
2999 force_cacheattr_nibble_wb(s1
.attrs
>> 4) << 4;
3001 /* If S1 attrs are Device, use them; otherwise Normal Non-cacheable */
3002 if ((s1
.attrs
& 0xf0) == 0) {
3007 /* Force Device, of subtype specified by S2 */
3008 return s2
.attrs
<< 2;
3011 * RESERVED values (including RES0 descriptor bit [5] being nonzero);
3012 * arbitrarily force Device.
3019 * Combine S1 and S2 cacheability/shareability attributes, per D4.5.4
3020 * and CombineS1S2Desc()
3023 * @s1: Attributes from stage 1 walk
3024 * @s2: Attributes from stage 2 walk
3026 static ARMCacheAttrs
combine_cacheattrs(uint64_t hcr
,
3027 ARMCacheAttrs s1
, ARMCacheAttrs s2
)
3030 bool tagged
= false;
3032 assert(!s1
.is_s2_format
);
3033 ret
.is_s2_format
= false;
3034 ret
.guarded
= s1
.guarded
;
3036 if (s1
.attrs
== 0xf0) {
3041 /* Combine shareability attributes (table D4-43) */
3042 if (s1
.shareability
== 2 || s2
.shareability
== 2) {
3043 /* if either are outer-shareable, the result is outer-shareable */
3044 ret
.shareability
= 2;
3045 } else if (s1
.shareability
== 3 || s2
.shareability
== 3) {
3046 /* if either are inner-shareable, the result is inner-shareable */
3047 ret
.shareability
= 3;
3049 /* both non-shareable */
3050 ret
.shareability
= 0;
3053 /* Combine memory type and cacheability attributes */
3054 if (hcr
& HCR_FWB
) {
3055 ret
.attrs
= combined_attrs_fwb(s1
, s2
);
3057 ret
.attrs
= combined_attrs_nofwb(hcr
, s1
, s2
);
3061 * Any location for which the resultant memory type is any
3062 * type of Device memory is always treated as Outer Shareable.
3063 * Any location for which the resultant memory type is Normal
3064 * Inner Non-cacheable, Outer Non-cacheable is always treated
3065 * as Outer Shareable.
3066 * TODO: FEAT_XS adds another value (0x40) also meaning iNCoNC
3068 if ((ret
.attrs
& 0xf0) == 0 || ret
.attrs
== 0x44) {
3069 ret
.shareability
= 2;
3072 /* TODO: CombineS1S2Desc does not consider transient, only WB, RWA. */
3073 if (tagged
&& ret
.attrs
== 0xff) {
3081 * MMU disabled. S1 addresses within aa64 translation regimes are
3082 * still checked for bounds -- see AArch64.S1DisabledOutput().
3084 static bool get_phys_addr_disabled(CPUARMState
*env
,
3086 target_ulong address
,
3087 MMUAccessType access_type
,
3088 GetPhysAddrResult
*result
,
3089 ARMMMUFaultInfo
*fi
)
3091 ARMMMUIdx mmu_idx
= ptw
->in_mmu_idx
;
3092 uint8_t memattr
= 0x00; /* Device nGnRnE */
3093 uint8_t shareability
= 0; /* non-shareable */
3097 case ARMMMUIdx_Stage2
:
3098 case ARMMMUIdx_Stage2_S
:
3099 case ARMMMUIdx_Phys_S
:
3100 case ARMMMUIdx_Phys_NS
:
3101 case ARMMMUIdx_Phys_Root
:
3102 case ARMMMUIdx_Phys_Realm
:
3106 r_el
= regime_el(env
, mmu_idx
);
3107 if (arm_el_is_aa64(env
, r_el
)) {
3108 int pamax
= arm_pamax(env_archcpu(env
));
3109 uint64_t tcr
= env
->cp15
.tcr_el
[r_el
];
3112 tbi
= aa64_va_parameter_tbi(tcr
, mmu_idx
);
3113 if (access_type
== MMU_INST_FETCH
) {
3114 tbi
&= ~aa64_va_parameter_tbid(tcr
, mmu_idx
);
3116 tbi
= (tbi
>> extract64(address
, 55, 1)) & 1;
3117 addrtop
= (tbi
? 55 : 63);
3119 if (extract64(address
, pamax
, addrtop
- pamax
+ 1) != 0) {
3120 fi
->type
= ARMFault_AddressSize
;
3127 * When TBI is disabled, we've just validated that all of the
3128 * bits above PAMax are zero, so logically we only need to
3129 * clear the top byte for TBI. But it's clearer to follow
3130 * the pseudocode set of addrdesc.paddress.
3132 address
= extract64(address
, 0, 52);
3135 /* Fill in cacheattr a-la AArch64.TranslateAddressS1Off. */
3137 uint64_t hcr
= arm_hcr_el2_eff_secstate(env
, ptw
->in_space
);
3139 if (hcr
& HCR_DCT
) {
3140 memattr
= 0xf0; /* Tagged, Normal, WB, RWA */
3142 memattr
= 0xff; /* Normal, WB, RWA */
3147 if (access_type
== MMU_INST_FETCH
) {
3148 if (regime_sctlr(env
, mmu_idx
) & SCTLR_I
) {
3149 memattr
= 0xee; /* Normal, WT, RA, NT */
3151 memattr
= 0x44; /* Normal, NC, No */
3154 shareability
= 2; /* outer shareable */
3156 result
->cacheattrs
.is_s2_format
= false;
3160 result
->f
.phys_addr
= address
;
3161 result
->f
.prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
3162 result
->f
.lg_page_size
= TARGET_PAGE_BITS
;
3163 result
->cacheattrs
.shareability
= shareability
;
3164 result
->cacheattrs
.attrs
= memattr
;
3168 static bool get_phys_addr_twostage(CPUARMState
*env
, S1Translate
*ptw
,
3169 target_ulong address
,
3170 MMUAccessType access_type
,
3171 GetPhysAddrResult
*result
,
3172 ARMMMUFaultInfo
*fi
)
3175 int s1_prot
, s1_lgpgsz
;
3176 ARMSecuritySpace in_space
= ptw
->in_space
;
3177 bool ret
, ipa_secure
;
3178 ARMCacheAttrs cacheattrs1
;
3179 ARMSecuritySpace ipa_space
;
3182 ret
= get_phys_addr_nogpc(env
, ptw
, address
, access_type
, result
, fi
);
3184 /* If S1 fails, return early. */
3189 ipa
= result
->f
.phys_addr
;
3190 ipa_secure
= result
->f
.attrs
.secure
;
3191 ipa_space
= result
->f
.attrs
.space
;
3193 ptw
->in_s1_is_el0
= ptw
->in_mmu_idx
== ARMMMUIdx_Stage1_E0
;
3194 ptw
->in_mmu_idx
= ipa_secure
? ARMMMUIdx_Stage2_S
: ARMMMUIdx_Stage2
;
3195 ptw
->in_space
= ipa_space
;
3196 ptw
->in_ptw_idx
= ptw_idx_for_stage_2(env
, ptw
->in_mmu_idx
);
3199 * S1 is done, now do S2 translation.
3200 * Save the stage1 results so that we may merge prot and cacheattrs later.
3202 s1_prot
= result
->f
.prot
;
3203 s1_lgpgsz
= result
->f
.lg_page_size
;
3204 cacheattrs1
= result
->cacheattrs
;
3205 memset(result
, 0, sizeof(*result
));
3207 ret
= get_phys_addr_nogpc(env
, ptw
, ipa
, access_type
, result
, fi
);
3210 /* Combine the S1 and S2 perms. */
3211 result
->f
.prot
&= s1_prot
;
3213 /* If S2 fails, return early. */
3219 * If either S1 or S2 returned a result smaller than TARGET_PAGE_SIZE,
3220 * this means "don't put this in the TLB"; in this case, return a
3221 * result with lg_page_size == 0 to achieve that. Otherwise,
3222 * use the maximum of the S1 & S2 page size, so that invalidation
3223 * of pages > TARGET_PAGE_SIZE works correctly. (This works even though
3224 * we know the combined result permissions etc only cover the minimum
3225 * of the S1 and S2 page size, because we know that the common TLB code
3226 * never actually creates TLB entries bigger than TARGET_PAGE_SIZE,
3227 * and passing a larger page size value only affects invalidations.)
3229 if (result
->f
.lg_page_size
< TARGET_PAGE_BITS
||
3230 s1_lgpgsz
< TARGET_PAGE_BITS
) {
3231 result
->f
.lg_page_size
= 0;
3232 } else if (result
->f
.lg_page_size
< s1_lgpgsz
) {
3233 result
->f
.lg_page_size
= s1_lgpgsz
;
3236 /* Combine the S1 and S2 cache attributes. */
3237 hcr
= arm_hcr_el2_eff_secstate(env
, in_space
);
3240 * HCR.DC forces the first stage attributes to
3241 * Normal Non-Shareable,
3242 * Inner Write-Back Read-Allocate Write-Allocate,
3243 * Outer Write-Back Read-Allocate Write-Allocate.
3244 * Do not overwrite Tagged within attrs.
3246 if (cacheattrs1
.attrs
!= 0xf0) {
3247 cacheattrs1
.attrs
= 0xff;
3249 cacheattrs1
.shareability
= 0;
3251 result
->cacheattrs
= combine_cacheattrs(hcr
, cacheattrs1
,
3252 result
->cacheattrs
);
3255 * Check if IPA translates to secure or non-secure PA space.
3256 * Note that VSTCR overrides VTCR and {N}SW overrides {N}SA.
3258 if (in_space
== ARMSS_Secure
) {
3259 result
->f
.attrs
.secure
=
3260 !(env
->cp15
.vstcr_el2
& (VSTCR_SA
| VSTCR_SW
))
3262 || !(env
->cp15
.vtcr_el2
& (VTCR_NSA
| VTCR_NSW
)));
3263 result
->f
.attrs
.space
= arm_secure_to_space(result
->f
.attrs
.secure
);
3269 static bool get_phys_addr_nogpc(CPUARMState
*env
, S1Translate
*ptw
,
3270 target_ulong address
,
3271 MMUAccessType access_type
,
3272 GetPhysAddrResult
*result
,
3273 ARMMMUFaultInfo
*fi
)
3275 ARMMMUIdx mmu_idx
= ptw
->in_mmu_idx
;
3276 ARMMMUIdx s1_mmu_idx
;
3279 * The page table entries may downgrade Secure to NonSecure, but
3280 * cannot upgrade a NonSecure translation regime's attributes
3281 * to Secure or Realm.
3283 result
->f
.attrs
.space
= ptw
->in_space
;
3284 result
->f
.attrs
.secure
= arm_space_is_secure(ptw
->in_space
);
3287 case ARMMMUIdx_Phys_S
:
3288 case ARMMMUIdx_Phys_NS
:
3289 case ARMMMUIdx_Phys_Root
:
3290 case ARMMMUIdx_Phys_Realm
:
3291 /* Checking Phys early avoids special casing later vs regime_el. */
3292 return get_phys_addr_disabled(env
, ptw
, address
, access_type
,
3295 case ARMMMUIdx_Stage1_E0
:
3296 case ARMMMUIdx_Stage1_E1
:
3297 case ARMMMUIdx_Stage1_E1_PAN
:
3299 * First stage lookup uses second stage for ptw; only
3300 * Secure has both S and NS IPA and starts with Stage2_S.
3302 ptw
->in_ptw_idx
= (ptw
->in_space
== ARMSS_Secure
) ?
3303 ARMMMUIdx_Stage2_S
: ARMMMUIdx_Stage2
;
3306 case ARMMMUIdx_Stage2
:
3307 case ARMMMUIdx_Stage2_S
:
3309 * Second stage lookup uses physical for ptw; whether this is S or
3310 * NS may depend on the SW/NSW bits if this is a stage 2 lookup for
3311 * the Secure EL2&0 regime.
3313 ptw
->in_ptw_idx
= ptw_idx_for_stage_2(env
, mmu_idx
);
3316 case ARMMMUIdx_E10_0
:
3317 s1_mmu_idx
= ARMMMUIdx_Stage1_E0
;
3319 case ARMMMUIdx_E10_1
:
3320 s1_mmu_idx
= ARMMMUIdx_Stage1_E1
;
3322 case ARMMMUIdx_E10_1_PAN
:
3323 s1_mmu_idx
= ARMMMUIdx_Stage1_E1_PAN
;
3326 * Call ourselves recursively to do the stage 1 and then stage 2
3327 * translations if mmu_idx is a two-stage regime, and EL2 present.
3328 * Otherwise, a stage1+stage2 translation is just stage 1.
3330 ptw
->in_mmu_idx
= mmu_idx
= s1_mmu_idx
;
3331 if (arm_feature(env
, ARM_FEATURE_EL2
) &&
3332 !regime_translation_disabled(env
, ARMMMUIdx_Stage2
, ptw
->in_space
)) {
3333 return get_phys_addr_twostage(env
, ptw
, address
, access_type
,
3339 /* Single stage uses physical for ptw. */
3340 ptw
->in_ptw_idx
= arm_space_to_phys(ptw
->in_space
);
3344 result
->f
.attrs
.user
= regime_is_user(env
, mmu_idx
);
3347 * Fast Context Switch Extension. This doesn't exist at all in v8.
3348 * In v7 and earlier it affects all stage 1 translations.
3350 if (address
< 0x02000000 && mmu_idx
!= ARMMMUIdx_Stage2
3351 && !arm_feature(env
, ARM_FEATURE_V8
)) {
3352 if (regime_el(env
, mmu_idx
) == 3) {
3353 address
+= env
->cp15
.fcseidr_s
;
3355 address
+= env
->cp15
.fcseidr_ns
;
3359 if (arm_feature(env
, ARM_FEATURE_PMSA
)) {
3361 result
->f
.lg_page_size
= TARGET_PAGE_BITS
;
3363 if (arm_feature(env
, ARM_FEATURE_V8
)) {
3365 ret
= get_phys_addr_pmsav8(env
, ptw
, address
, access_type
,
3367 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
3369 ret
= get_phys_addr_pmsav7(env
, ptw
, address
, access_type
,
3373 ret
= get_phys_addr_pmsav5(env
, ptw
, address
, access_type
,
3376 qemu_log_mask(CPU_LOG_MMU
, "PMSA MPU lookup for %s at 0x%08" PRIx32
3377 " mmu_idx %u -> %s (prot %c%c%c)\n",
3378 access_type
== MMU_DATA_LOAD
? "reading" :
3379 (access_type
== MMU_DATA_STORE
? "writing" : "execute"),
3380 (uint32_t)address
, mmu_idx
,
3381 ret
? "Miss" : "Hit",
3382 result
->f
.prot
& PAGE_READ
? 'r' : '-',
3383 result
->f
.prot
& PAGE_WRITE
? 'w' : '-',
3384 result
->f
.prot
& PAGE_EXEC
? 'x' : '-');
3389 /* Definitely a real MMU, not an MPU */
3391 if (regime_translation_disabled(env
, mmu_idx
, ptw
->in_space
)) {
3392 return get_phys_addr_disabled(env
, ptw
, address
, access_type
,
3396 if (regime_using_lpae_format(env
, mmu_idx
)) {
3397 return get_phys_addr_lpae(env
, ptw
, address
, access_type
, result
, fi
);
3398 } else if (arm_feature(env
, ARM_FEATURE_V7
) ||
3399 regime_sctlr(env
, mmu_idx
) & SCTLR_XP
) {
3400 return get_phys_addr_v6(env
, ptw
, address
, access_type
, result
, fi
);
3402 return get_phys_addr_v5(env
, ptw
, address
, access_type
, result
, fi
);
3406 static bool get_phys_addr_gpc(CPUARMState
*env
, S1Translate
*ptw
,
3407 target_ulong address
,
3408 MMUAccessType access_type
,
3409 GetPhysAddrResult
*result
,
3410 ARMMMUFaultInfo
*fi
)
3412 if (get_phys_addr_nogpc(env
, ptw
, address
, access_type
, result
, fi
)) {
3415 if (!granule_protection_check(env
, result
->f
.phys_addr
,
3416 result
->f
.attrs
.space
, fi
)) {
3417 fi
->type
= ARMFault_GPCFOnOutput
;
3423 bool get_phys_addr_with_space_nogpc(CPUARMState
*env
, target_ulong address
,
3424 MMUAccessType access_type
,
3425 ARMMMUIdx mmu_idx
, ARMSecuritySpace space
,
3426 GetPhysAddrResult
*result
,
3427 ARMMMUFaultInfo
*fi
)
3430 .in_mmu_idx
= mmu_idx
,
3433 return get_phys_addr_nogpc(env
, &ptw
, address
, access_type
, result
, fi
);
3436 bool get_phys_addr(CPUARMState
*env
, target_ulong address
,
3437 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
3438 GetPhysAddrResult
*result
, ARMMMUFaultInfo
*fi
)
3441 .in_mmu_idx
= mmu_idx
,
3443 ARMSecuritySpace ss
;
3446 case ARMMMUIdx_E10_0
:
3447 case ARMMMUIdx_E10_1
:
3448 case ARMMMUIdx_E10_1_PAN
:
3449 case ARMMMUIdx_E20_0
:
3450 case ARMMMUIdx_E20_2
:
3451 case ARMMMUIdx_E20_2_PAN
:
3452 case ARMMMUIdx_Stage1_E0
:
3453 case ARMMMUIdx_Stage1_E1
:
3454 case ARMMMUIdx_Stage1_E1_PAN
:
3456 ss
= arm_security_space_below_el3(env
);
3458 case ARMMMUIdx_Stage2
:
3460 * For Secure EL2, we need this index to be NonSecure;
3461 * otherwise this will already be NonSecure or Realm.
3463 ss
= arm_security_space_below_el3(env
);
3464 if (ss
== ARMSS_Secure
) {
3465 ss
= ARMSS_NonSecure
;
3468 case ARMMMUIdx_Phys_NS
:
3469 case ARMMMUIdx_MPrivNegPri
:
3470 case ARMMMUIdx_MUserNegPri
:
3471 case ARMMMUIdx_MPriv
:
3472 case ARMMMUIdx_MUser
:
3473 ss
= ARMSS_NonSecure
;
3475 case ARMMMUIdx_Stage2_S
:
3476 case ARMMMUIdx_Phys_S
:
3477 case ARMMMUIdx_MSPrivNegPri
:
3478 case ARMMMUIdx_MSUserNegPri
:
3479 case ARMMMUIdx_MSPriv
:
3480 case ARMMMUIdx_MSUser
:
3484 if (arm_feature(env
, ARM_FEATURE_AARCH64
) &&
3485 cpu_isar_feature(aa64_rme
, env_archcpu(env
))) {
3491 case ARMMMUIdx_Phys_Root
:
3494 case ARMMMUIdx_Phys_Realm
:
3498 g_assert_not_reached();
3502 return get_phys_addr_gpc(env
, &ptw
, address
, access_type
, result
, fi
);
3505 hwaddr
arm_cpu_get_phys_page_attrs_debug(CPUState
*cs
, vaddr addr
,
3508 ARMCPU
*cpu
= ARM_CPU(cs
);
3509 CPUARMState
*env
= &cpu
->env
;
3510 ARMMMUIdx mmu_idx
= arm_mmu_idx(env
);
3511 ARMSecuritySpace ss
= arm_security_space(env
);
3513 .in_mmu_idx
= mmu_idx
,
3517 GetPhysAddrResult res
= {};
3518 ARMMMUFaultInfo fi
= {};
3521 ret
= get_phys_addr_gpc(env
, &ptw
, addr
, MMU_DATA_LOAD
, &res
, &fi
);
3522 *attrs
= res
.f
.attrs
;
3527 return res
.f
.phys_addr
;