2 * QEMU emulation of an Intel IOMMU (VT-d)
3 * (DMA Remapping device)
5 * Copyright (C) 2013 Knut Omang, Oracle <knut.omang@oracle.com>
6 * Copyright (C) 2014 Le Tan, <tamlokveer@gmail.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, see <http://www.gnu.org/licenses/>.
22 #include "qemu/osdep.h"
23 #include "qemu/error-report.h"
24 #include "qapi/error.h"
25 #include "hw/sysbus.h"
26 #include "exec/address-spaces.h"
27 #include "intel_iommu_internal.h"
28 #include "hw/pci/pci.h"
29 #include "hw/pci/pci_bus.h"
30 #include "hw/i386/pc.h"
31 #include "hw/i386/apic-msidef.h"
32 #include "hw/boards.h"
33 #include "hw/i386/x86-iommu.h"
34 #include "hw/pci-host/q35.h"
35 #include "sysemu/kvm.h"
36 #include "hw/i386/apic_internal.h"
40 static void vtd_define_quad(IntelIOMMUState
*s
, hwaddr addr
, uint64_t val
,
41 uint64_t wmask
, uint64_t w1cmask
)
43 stq_le_p(&s
->csr
[addr
], val
);
44 stq_le_p(&s
->wmask
[addr
], wmask
);
45 stq_le_p(&s
->w1cmask
[addr
], w1cmask
);
48 static void vtd_define_quad_wo(IntelIOMMUState
*s
, hwaddr addr
, uint64_t mask
)
50 stq_le_p(&s
->womask
[addr
], mask
);
53 static void vtd_define_long(IntelIOMMUState
*s
, hwaddr addr
, uint32_t val
,
54 uint32_t wmask
, uint32_t w1cmask
)
56 stl_le_p(&s
->csr
[addr
], val
);
57 stl_le_p(&s
->wmask
[addr
], wmask
);
58 stl_le_p(&s
->w1cmask
[addr
], w1cmask
);
61 static void vtd_define_long_wo(IntelIOMMUState
*s
, hwaddr addr
, uint32_t mask
)
63 stl_le_p(&s
->womask
[addr
], mask
);
66 /* "External" get/set operations */
67 static void vtd_set_quad(IntelIOMMUState
*s
, hwaddr addr
, uint64_t val
)
69 uint64_t oldval
= ldq_le_p(&s
->csr
[addr
]);
70 uint64_t wmask
= ldq_le_p(&s
->wmask
[addr
]);
71 uint64_t w1cmask
= ldq_le_p(&s
->w1cmask
[addr
]);
72 stq_le_p(&s
->csr
[addr
],
73 ((oldval
& ~wmask
) | (val
& wmask
)) & ~(w1cmask
& val
));
76 static void vtd_set_long(IntelIOMMUState
*s
, hwaddr addr
, uint32_t val
)
78 uint32_t oldval
= ldl_le_p(&s
->csr
[addr
]);
79 uint32_t wmask
= ldl_le_p(&s
->wmask
[addr
]);
80 uint32_t w1cmask
= ldl_le_p(&s
->w1cmask
[addr
]);
81 stl_le_p(&s
->csr
[addr
],
82 ((oldval
& ~wmask
) | (val
& wmask
)) & ~(w1cmask
& val
));
85 static uint64_t vtd_get_quad(IntelIOMMUState
*s
, hwaddr addr
)
87 uint64_t val
= ldq_le_p(&s
->csr
[addr
]);
88 uint64_t womask
= ldq_le_p(&s
->womask
[addr
]);
92 static uint32_t vtd_get_long(IntelIOMMUState
*s
, hwaddr addr
)
94 uint32_t val
= ldl_le_p(&s
->csr
[addr
]);
95 uint32_t womask
= ldl_le_p(&s
->womask
[addr
]);
99 /* "Internal" get/set operations */
100 static uint64_t vtd_get_quad_raw(IntelIOMMUState
*s
, hwaddr addr
)
102 return ldq_le_p(&s
->csr
[addr
]);
105 static uint32_t vtd_get_long_raw(IntelIOMMUState
*s
, hwaddr addr
)
107 return ldl_le_p(&s
->csr
[addr
]);
110 static void vtd_set_quad_raw(IntelIOMMUState
*s
, hwaddr addr
, uint64_t val
)
112 stq_le_p(&s
->csr
[addr
], val
);
115 static uint32_t vtd_set_clear_mask_long(IntelIOMMUState
*s
, hwaddr addr
,
116 uint32_t clear
, uint32_t mask
)
118 uint32_t new_val
= (ldl_le_p(&s
->csr
[addr
]) & ~clear
) | mask
;
119 stl_le_p(&s
->csr
[addr
], new_val
);
123 static uint64_t vtd_set_clear_mask_quad(IntelIOMMUState
*s
, hwaddr addr
,
124 uint64_t clear
, uint64_t mask
)
126 uint64_t new_val
= (ldq_le_p(&s
->csr
[addr
]) & ~clear
) | mask
;
127 stq_le_p(&s
->csr
[addr
], new_val
);
131 /* GHashTable functions */
132 static gboolean
vtd_uint64_equal(gconstpointer v1
, gconstpointer v2
)
134 return *((const uint64_t *)v1
) == *((const uint64_t *)v2
);
137 static guint
vtd_uint64_hash(gconstpointer v
)
139 return (guint
)*(const uint64_t *)v
;
142 static gboolean
vtd_hash_remove_by_domain(gpointer key
, gpointer value
,
145 VTDIOTLBEntry
*entry
= (VTDIOTLBEntry
*)value
;
146 uint16_t domain_id
= *(uint16_t *)user_data
;
147 return entry
->domain_id
== domain_id
;
150 /* The shift of an addr for a certain level of paging structure */
151 static inline uint32_t vtd_slpt_level_shift(uint32_t level
)
154 return VTD_PAGE_SHIFT_4K
+ (level
- 1) * VTD_SL_LEVEL_BITS
;
157 static inline uint64_t vtd_slpt_level_page_mask(uint32_t level
)
159 return ~((1ULL << vtd_slpt_level_shift(level
)) - 1);
162 static gboolean
vtd_hash_remove_by_page(gpointer key
, gpointer value
,
165 VTDIOTLBEntry
*entry
= (VTDIOTLBEntry
*)value
;
166 VTDIOTLBPageInvInfo
*info
= (VTDIOTLBPageInvInfo
*)user_data
;
167 uint64_t gfn
= (info
->addr
>> VTD_PAGE_SHIFT_4K
) & info
->mask
;
168 uint64_t gfn_tlb
= (info
->addr
& entry
->mask
) >> VTD_PAGE_SHIFT_4K
;
169 return (entry
->domain_id
== info
->domain_id
) &&
170 (((entry
->gfn
& info
->mask
) == gfn
) ||
171 (entry
->gfn
== gfn_tlb
));
174 /* Reset all the gen of VTDAddressSpace to zero and set the gen of
175 * IntelIOMMUState to 1.
177 static void vtd_reset_context_cache(IntelIOMMUState
*s
)
179 VTDAddressSpace
*vtd_as
;
181 GHashTableIter bus_it
;
184 trace_vtd_context_cache_reset();
186 g_hash_table_iter_init(&bus_it
, s
->vtd_as_by_busptr
);
188 while (g_hash_table_iter_next (&bus_it
, NULL
, (void**)&vtd_bus
)) {
189 for (devfn_it
= 0; devfn_it
< PCI_DEVFN_MAX
; ++devfn_it
) {
190 vtd_as
= vtd_bus
->dev_as
[devfn_it
];
194 vtd_as
->context_cache_entry
.context_cache_gen
= 0;
197 s
->context_cache_gen
= 1;
200 static void vtd_reset_iotlb(IntelIOMMUState
*s
)
203 g_hash_table_remove_all(s
->iotlb
);
206 static uint64_t vtd_get_iotlb_key(uint64_t gfn
, uint16_t source_id
,
209 return gfn
| ((uint64_t)(source_id
) << VTD_IOTLB_SID_SHIFT
) |
210 ((uint64_t)(level
) << VTD_IOTLB_LVL_SHIFT
);
213 static uint64_t vtd_get_iotlb_gfn(hwaddr addr
, uint32_t level
)
215 return (addr
& vtd_slpt_level_page_mask(level
)) >> VTD_PAGE_SHIFT_4K
;
218 static VTDIOTLBEntry
*vtd_lookup_iotlb(IntelIOMMUState
*s
, uint16_t source_id
,
221 VTDIOTLBEntry
*entry
;
225 for (level
= VTD_SL_PT_LEVEL
; level
< VTD_SL_PML4_LEVEL
; level
++) {
226 key
= vtd_get_iotlb_key(vtd_get_iotlb_gfn(addr
, level
),
228 entry
= g_hash_table_lookup(s
->iotlb
, &key
);
238 static void vtd_update_iotlb(IntelIOMMUState
*s
, uint16_t source_id
,
239 uint16_t domain_id
, hwaddr addr
, uint64_t slpte
,
240 uint8_t access_flags
, uint32_t level
)
242 VTDIOTLBEntry
*entry
= g_malloc(sizeof(*entry
));
243 uint64_t *key
= g_malloc(sizeof(*key
));
244 uint64_t gfn
= vtd_get_iotlb_gfn(addr
, level
);
246 trace_vtd_iotlb_page_update(source_id
, addr
, slpte
, domain_id
);
247 if (g_hash_table_size(s
->iotlb
) >= VTD_IOTLB_MAX_SIZE
) {
248 trace_vtd_iotlb_reset("iotlb exceeds size limit");
253 entry
->domain_id
= domain_id
;
254 entry
->slpte
= slpte
;
255 entry
->access_flags
= access_flags
;
256 entry
->mask
= vtd_slpt_level_page_mask(level
);
257 *key
= vtd_get_iotlb_key(gfn
, source_id
, level
);
258 g_hash_table_replace(s
->iotlb
, key
, entry
);
261 /* Given the reg addr of both the message data and address, generate an
264 static void vtd_generate_interrupt(IntelIOMMUState
*s
, hwaddr mesg_addr_reg
,
265 hwaddr mesg_data_reg
)
269 assert(mesg_data_reg
< DMAR_REG_SIZE
);
270 assert(mesg_addr_reg
< DMAR_REG_SIZE
);
272 msi
.address
= vtd_get_long_raw(s
, mesg_addr_reg
);
273 msi
.data
= vtd_get_long_raw(s
, mesg_data_reg
);
275 trace_vtd_irq_generate(msi
.address
, msi
.data
);
277 apic_get_class()->send_msi(&msi
);
280 /* Generate a fault event to software via MSI if conditions are met.
281 * Notice that the value of FSTS_REG being passed to it should be the one
284 static void vtd_generate_fault_event(IntelIOMMUState
*s
, uint32_t pre_fsts
)
286 if (pre_fsts
& VTD_FSTS_PPF
|| pre_fsts
& VTD_FSTS_PFO
||
287 pre_fsts
& VTD_FSTS_IQE
) {
288 trace_vtd_err("There are previous interrupt conditions "
289 "to be serviced by software, fault event "
290 "is not generated.");
293 vtd_set_clear_mask_long(s
, DMAR_FECTL_REG
, 0, VTD_FECTL_IP
);
294 if (vtd_get_long_raw(s
, DMAR_FECTL_REG
) & VTD_FECTL_IM
) {
295 trace_vtd_err("Interrupt Mask set, irq is not generated.");
297 vtd_generate_interrupt(s
, DMAR_FEADDR_REG
, DMAR_FEDATA_REG
);
298 vtd_set_clear_mask_long(s
, DMAR_FECTL_REG
, VTD_FECTL_IP
, 0);
302 /* Check if the Fault (F) field of the Fault Recording Register referenced by
305 static bool vtd_is_frcd_set(IntelIOMMUState
*s
, uint16_t index
)
307 /* Each reg is 128-bit */
308 hwaddr addr
= DMAR_FRCD_REG_OFFSET
+ (((uint64_t)index
) << 4);
309 addr
+= 8; /* Access the high 64-bit half */
311 assert(index
< DMAR_FRCD_REG_NR
);
313 return vtd_get_quad_raw(s
, addr
) & VTD_FRCD_F
;
316 /* Update the PPF field of Fault Status Register.
317 * Should be called whenever change the F field of any fault recording
320 static void vtd_update_fsts_ppf(IntelIOMMUState
*s
)
323 uint32_t ppf_mask
= 0;
325 for (i
= 0; i
< DMAR_FRCD_REG_NR
; i
++) {
326 if (vtd_is_frcd_set(s
, i
)) {
327 ppf_mask
= VTD_FSTS_PPF
;
331 vtd_set_clear_mask_long(s
, DMAR_FSTS_REG
, VTD_FSTS_PPF
, ppf_mask
);
332 trace_vtd_fsts_ppf(!!ppf_mask
);
335 static void vtd_set_frcd_and_update_ppf(IntelIOMMUState
*s
, uint16_t index
)
337 /* Each reg is 128-bit */
338 hwaddr addr
= DMAR_FRCD_REG_OFFSET
+ (((uint64_t)index
) << 4);
339 addr
+= 8; /* Access the high 64-bit half */
341 assert(index
< DMAR_FRCD_REG_NR
);
343 vtd_set_clear_mask_quad(s
, addr
, 0, VTD_FRCD_F
);
344 vtd_update_fsts_ppf(s
);
347 /* Must not update F field now, should be done later */
348 static void vtd_record_frcd(IntelIOMMUState
*s
, uint16_t index
,
349 uint16_t source_id
, hwaddr addr
,
350 VTDFaultReason fault
, bool is_write
)
353 hwaddr frcd_reg_addr
= DMAR_FRCD_REG_OFFSET
+ (((uint64_t)index
) << 4);
355 assert(index
< DMAR_FRCD_REG_NR
);
357 lo
= VTD_FRCD_FI(addr
);
358 hi
= VTD_FRCD_SID(source_id
) | VTD_FRCD_FR(fault
);
362 vtd_set_quad_raw(s
, frcd_reg_addr
, lo
);
363 vtd_set_quad_raw(s
, frcd_reg_addr
+ 8, hi
);
365 trace_vtd_frr_new(index
, hi
, lo
);
368 /* Try to collapse multiple pending faults from the same requester */
369 static bool vtd_try_collapse_fault(IntelIOMMUState
*s
, uint16_t source_id
)
373 hwaddr addr
= DMAR_FRCD_REG_OFFSET
+ 8; /* The high 64-bit half */
375 for (i
= 0; i
< DMAR_FRCD_REG_NR
; i
++) {
376 frcd_reg
= vtd_get_quad_raw(s
, addr
);
377 if ((frcd_reg
& VTD_FRCD_F
) &&
378 ((frcd_reg
& VTD_FRCD_SID_MASK
) == source_id
)) {
381 addr
+= 16; /* 128-bit for each */
386 /* Log and report an DMAR (address translation) fault to software */
387 static void vtd_report_dmar_fault(IntelIOMMUState
*s
, uint16_t source_id
,
388 hwaddr addr
, VTDFaultReason fault
,
391 uint32_t fsts_reg
= vtd_get_long_raw(s
, DMAR_FSTS_REG
);
393 assert(fault
< VTD_FR_MAX
);
395 if (fault
== VTD_FR_RESERVED_ERR
) {
396 /* This is not a normal fault reason case. Drop it. */
400 trace_vtd_dmar_fault(source_id
, fault
, addr
, is_write
);
402 if (fsts_reg
& VTD_FSTS_PFO
) {
403 trace_vtd_err("New fault is not recorded due to "
404 "Primary Fault Overflow.");
408 if (vtd_try_collapse_fault(s
, source_id
)) {
409 trace_vtd_err("New fault is not recorded due to "
410 "compression of faults.");
414 if (vtd_is_frcd_set(s
, s
->next_frcd_reg
)) {
415 trace_vtd_err("Next Fault Recording Reg is used, "
416 "new fault is not recorded, set PFO field.");
417 vtd_set_clear_mask_long(s
, DMAR_FSTS_REG
, 0, VTD_FSTS_PFO
);
421 vtd_record_frcd(s
, s
->next_frcd_reg
, source_id
, addr
, fault
, is_write
);
423 if (fsts_reg
& VTD_FSTS_PPF
) {
424 trace_vtd_err("There are pending faults already, "
425 "fault event is not generated.");
426 vtd_set_frcd_and_update_ppf(s
, s
->next_frcd_reg
);
428 if (s
->next_frcd_reg
== DMAR_FRCD_REG_NR
) {
429 s
->next_frcd_reg
= 0;
432 vtd_set_clear_mask_long(s
, DMAR_FSTS_REG
, VTD_FSTS_FRI_MASK
,
433 VTD_FSTS_FRI(s
->next_frcd_reg
));
434 vtd_set_frcd_and_update_ppf(s
, s
->next_frcd_reg
); /* Will set PPF */
436 if (s
->next_frcd_reg
== DMAR_FRCD_REG_NR
) {
437 s
->next_frcd_reg
= 0;
439 /* This case actually cause the PPF to be Set.
440 * So generate fault event (interrupt).
442 vtd_generate_fault_event(s
, fsts_reg
);
446 /* Handle Invalidation Queue Errors of queued invalidation interface error
449 static void vtd_handle_inv_queue_error(IntelIOMMUState
*s
)
451 uint32_t fsts_reg
= vtd_get_long_raw(s
, DMAR_FSTS_REG
);
453 vtd_set_clear_mask_long(s
, DMAR_FSTS_REG
, 0, VTD_FSTS_IQE
);
454 vtd_generate_fault_event(s
, fsts_reg
);
457 /* Set the IWC field and try to generate an invalidation completion interrupt */
458 static void vtd_generate_completion_event(IntelIOMMUState
*s
)
460 if (vtd_get_long_raw(s
, DMAR_ICS_REG
) & VTD_ICS_IWC
) {
461 trace_vtd_inv_desc_wait_irq("One pending, skip current");
464 vtd_set_clear_mask_long(s
, DMAR_ICS_REG
, 0, VTD_ICS_IWC
);
465 vtd_set_clear_mask_long(s
, DMAR_IECTL_REG
, 0, VTD_IECTL_IP
);
466 if (vtd_get_long_raw(s
, DMAR_IECTL_REG
) & VTD_IECTL_IM
) {
467 trace_vtd_inv_desc_wait_irq("IM in IECTL_REG is set, "
468 "new event not generated");
471 /* Generate the interrupt event */
472 trace_vtd_inv_desc_wait_irq("Generating complete event");
473 vtd_generate_interrupt(s
, DMAR_IEADDR_REG
, DMAR_IEDATA_REG
);
474 vtd_set_clear_mask_long(s
, DMAR_IECTL_REG
, VTD_IECTL_IP
, 0);
478 static inline bool vtd_root_entry_present(VTDRootEntry
*root
)
480 return root
->val
& VTD_ROOT_ENTRY_P
;
483 static int vtd_get_root_entry(IntelIOMMUState
*s
, uint8_t index
,
488 addr
= s
->root
+ index
* sizeof(*re
);
489 if (dma_memory_read(&address_space_memory
, addr
, re
, sizeof(*re
))) {
490 trace_vtd_re_invalid(re
->rsvd
, re
->val
);
492 return -VTD_FR_ROOT_TABLE_INV
;
494 re
->val
= le64_to_cpu(re
->val
);
498 static inline bool vtd_ce_present(VTDContextEntry
*context
)
500 return context
->lo
& VTD_CONTEXT_ENTRY_P
;
503 static int vtd_get_context_entry_from_root(VTDRootEntry
*root
, uint8_t index
,
508 /* we have checked that root entry is present */
509 addr
= (root
->val
& VTD_ROOT_ENTRY_CTP
) + index
* sizeof(*ce
);
510 if (dma_memory_read(&address_space_memory
, addr
, ce
, sizeof(*ce
))) {
511 trace_vtd_re_invalid(root
->rsvd
, root
->val
);
512 return -VTD_FR_CONTEXT_TABLE_INV
;
514 ce
->lo
= le64_to_cpu(ce
->lo
);
515 ce
->hi
= le64_to_cpu(ce
->hi
);
519 static inline dma_addr_t
vtd_ce_get_slpt_base(VTDContextEntry
*ce
)
521 return ce
->lo
& VTD_CONTEXT_ENTRY_SLPTPTR
;
524 static inline uint64_t vtd_get_slpte_addr(uint64_t slpte
, uint8_t aw
)
526 return slpte
& VTD_SL_PT_BASE_ADDR_MASK(aw
);
529 /* Whether the pte indicates the address of the page frame */
530 static inline bool vtd_is_last_slpte(uint64_t slpte
, uint32_t level
)
532 return level
== VTD_SL_PT_LEVEL
|| (slpte
& VTD_SL_PT_PAGE_SIZE_MASK
);
535 /* Get the content of a spte located in @base_addr[@index] */
536 static uint64_t vtd_get_slpte(dma_addr_t base_addr
, uint32_t index
)
540 assert(index
< VTD_SL_PT_ENTRY_NR
);
542 if (dma_memory_read(&address_space_memory
,
543 base_addr
+ index
* sizeof(slpte
), &slpte
,
545 slpte
= (uint64_t)-1;
548 slpte
= le64_to_cpu(slpte
);
552 /* Given an iova and the level of paging structure, return the offset
555 static inline uint32_t vtd_iova_level_offset(uint64_t iova
, uint32_t level
)
557 return (iova
>> vtd_slpt_level_shift(level
)) &
558 ((1ULL << VTD_SL_LEVEL_BITS
) - 1);
561 /* Check Capability Register to see if the @level of page-table is supported */
562 static inline bool vtd_is_level_supported(IntelIOMMUState
*s
, uint32_t level
)
564 return VTD_CAP_SAGAW_MASK
& s
->cap
&
565 (1ULL << (level
- 2 + VTD_CAP_SAGAW_SHIFT
));
568 /* Get the page-table level that hardware should use for the second-level
569 * page-table walk from the Address Width field of context-entry.
571 static inline uint32_t vtd_ce_get_level(VTDContextEntry
*ce
)
573 return 2 + (ce
->hi
& VTD_CONTEXT_ENTRY_AW
);
576 static inline uint32_t vtd_ce_get_agaw(VTDContextEntry
*ce
)
578 return 30 + (ce
->hi
& VTD_CONTEXT_ENTRY_AW
) * 9;
581 static inline uint32_t vtd_ce_get_type(VTDContextEntry
*ce
)
583 return ce
->lo
& VTD_CONTEXT_ENTRY_TT
;
586 /* Return true if check passed, otherwise false */
587 static inline bool vtd_ce_type_check(X86IOMMUState
*x86_iommu
,
590 switch (vtd_ce_get_type(ce
)) {
591 case VTD_CONTEXT_TT_MULTI_LEVEL
:
592 /* Always supported */
594 case VTD_CONTEXT_TT_DEV_IOTLB
:
595 if (!x86_iommu
->dt_supported
) {
599 case VTD_CONTEXT_TT_PASS_THROUGH
:
600 if (!x86_iommu
->pt_supported
) {
611 static inline uint64_t vtd_iova_limit(VTDContextEntry
*ce
, uint8_t aw
)
613 uint32_t ce_agaw
= vtd_ce_get_agaw(ce
);
614 return 1ULL << MIN(ce_agaw
, aw
);
617 /* Return true if IOVA passes range check, otherwise false. */
618 static inline bool vtd_iova_range_check(uint64_t iova
, VTDContextEntry
*ce
,
622 * Check if @iova is above 2^X-1, where X is the minimum of MGAW
623 * in CAP_REG and AW in context-entry.
625 return !(iova
& ~(vtd_iova_limit(ce
, aw
) - 1));
629 * Rsvd field masks for spte:
630 * Index [1] to [4] 4k pages
631 * Index [5] to [8] large pages
633 static uint64_t vtd_paging_entry_rsvd_field
[9];
635 static bool vtd_slpte_nonzero_rsvd(uint64_t slpte
, uint32_t level
)
637 if (slpte
& VTD_SL_PT_PAGE_SIZE_MASK
) {
638 /* Maybe large page */
639 return slpte
& vtd_paging_entry_rsvd_field
[level
+ 4];
641 return slpte
& vtd_paging_entry_rsvd_field
[level
];
645 /* Find the VTD address space associated with a given bus number */
646 static VTDBus
*vtd_find_as_from_bus_num(IntelIOMMUState
*s
, uint8_t bus_num
)
648 VTDBus
*vtd_bus
= s
->vtd_as_by_bus_num
[bus_num
];
651 * Iterate over the registered buses to find the one which
652 * currently hold this bus number, and update the bus_num
657 g_hash_table_iter_init(&iter
, s
->vtd_as_by_busptr
);
658 while (g_hash_table_iter_next(&iter
, NULL
, (void **)&vtd_bus
)) {
659 if (pci_bus_num(vtd_bus
->bus
) == bus_num
) {
660 s
->vtd_as_by_bus_num
[bus_num
] = vtd_bus
;
668 /* Given the @iova, get relevant @slptep. @slpte_level will be the last level
669 * of the translation, can be used for deciding the size of large page.
671 static int vtd_iova_to_slpte(VTDContextEntry
*ce
, uint64_t iova
, bool is_write
,
672 uint64_t *slptep
, uint32_t *slpte_level
,
673 bool *reads
, bool *writes
, uint8_t aw_bits
)
675 dma_addr_t addr
= vtd_ce_get_slpt_base(ce
);
676 uint32_t level
= vtd_ce_get_level(ce
);
679 uint64_t access_right_check
;
681 if (!vtd_iova_range_check(iova
, ce
, aw_bits
)) {
682 trace_vtd_err_dmar_iova_overflow(iova
);
683 return -VTD_FR_ADDR_BEYOND_MGAW
;
686 /* FIXME: what is the Atomics request here? */
687 access_right_check
= is_write
? VTD_SL_W
: VTD_SL_R
;
690 offset
= vtd_iova_level_offset(iova
, level
);
691 slpte
= vtd_get_slpte(addr
, offset
);
693 if (slpte
== (uint64_t)-1) {
694 trace_vtd_err_dmar_slpte_read_error(iova
, level
);
695 if (level
== vtd_ce_get_level(ce
)) {
696 /* Invalid programming of context-entry */
697 return -VTD_FR_CONTEXT_ENTRY_INV
;
699 return -VTD_FR_PAGING_ENTRY_INV
;
702 *reads
= (*reads
) && (slpte
& VTD_SL_R
);
703 *writes
= (*writes
) && (slpte
& VTD_SL_W
);
704 if (!(slpte
& access_right_check
)) {
705 trace_vtd_err_dmar_slpte_perm_error(iova
, level
, slpte
, is_write
);
706 return is_write
? -VTD_FR_WRITE
: -VTD_FR_READ
;
708 if (vtd_slpte_nonzero_rsvd(slpte
, level
)) {
709 trace_vtd_err_dmar_slpte_resv_error(iova
, level
, slpte
);
710 return -VTD_FR_PAGING_ENTRY_RSVD
;
713 if (vtd_is_last_slpte(slpte
, level
)) {
715 *slpte_level
= level
;
718 addr
= vtd_get_slpte_addr(slpte
, aw_bits
);
723 typedef int (*vtd_page_walk_hook
)(IOMMUTLBEntry
*entry
, void *private);
725 static int vtd_page_walk_one(IOMMUTLBEntry
*entry
, int level
,
726 vtd_page_walk_hook hook_fn
, void *private)
729 trace_vtd_page_walk_one(level
, entry
->iova
, entry
->translated_addr
,
730 entry
->addr_mask
, entry
->perm
);
731 return hook_fn(entry
, private);
735 * vtd_page_walk_level - walk over specific level for IOVA range
737 * @addr: base GPA addr to start the walk
738 * @start: IOVA range start address
739 * @end: IOVA range end address (start <= addr < end)
740 * @hook_fn: hook func to be called when detected page
741 * @private: private data to be passed into hook func
742 * @read: whether parent level has read permission
743 * @write: whether parent level has write permission
744 * @notify_unmap: whether we should notify invalid entries
745 * @aw: maximum address width
747 static int vtd_page_walk_level(dma_addr_t addr
, uint64_t start
,
748 uint64_t end
, vtd_page_walk_hook hook_fn
,
749 void *private, uint32_t level
, bool read
,
750 bool write
, bool notify_unmap
, uint8_t aw
)
752 bool read_cur
, write_cur
, entry_valid
;
755 uint64_t subpage_size
, subpage_mask
;
757 uint64_t iova
= start
;
761 trace_vtd_page_walk_level(addr
, level
, start
, end
);
763 subpage_size
= 1ULL << vtd_slpt_level_shift(level
);
764 subpage_mask
= vtd_slpt_level_page_mask(level
);
767 iova_next
= (iova
& subpage_mask
) + subpage_size
;
769 offset
= vtd_iova_level_offset(iova
, level
);
770 slpte
= vtd_get_slpte(addr
, offset
);
772 if (slpte
== (uint64_t)-1) {
773 trace_vtd_page_walk_skip_read(iova
, iova_next
);
777 if (vtd_slpte_nonzero_rsvd(slpte
, level
)) {
778 trace_vtd_page_walk_skip_reserve(iova
, iova_next
);
782 /* Permissions are stacked with parents' */
783 read_cur
= read
&& (slpte
& VTD_SL_R
);
784 write_cur
= write
&& (slpte
& VTD_SL_W
);
787 * As long as we have either read/write permission, this is a
788 * valid entry. The rule works for both page entries and page
791 entry_valid
= read_cur
| write_cur
;
793 entry
.target_as
= &address_space_memory
;
794 entry
.iova
= iova
& subpage_mask
;
795 entry
.perm
= IOMMU_ACCESS_FLAG(read_cur
, write_cur
);
796 entry
.addr_mask
= ~subpage_mask
;
798 if (vtd_is_last_slpte(slpte
, level
)) {
799 /* NOTE: this is only meaningful if entry_valid == true */
800 entry
.translated_addr
= vtd_get_slpte_addr(slpte
, aw
);
801 if (!entry_valid
&& !notify_unmap
) {
802 trace_vtd_page_walk_skip_perm(iova
, iova_next
);
805 ret
= vtd_page_walk_one(&entry
, level
, hook_fn
, private);
813 * The whole entry is invalid; unmap it all.
814 * Translated address is meaningless, zero it.
816 entry
.translated_addr
= 0x0;
817 ret
= vtd_page_walk_one(&entry
, level
, hook_fn
, private);
822 trace_vtd_page_walk_skip_perm(iova
, iova_next
);
826 ret
= vtd_page_walk_level(vtd_get_slpte_addr(slpte
, aw
), iova
,
827 MIN(iova_next
, end
), hook_fn
, private,
828 level
- 1, read_cur
, write_cur
,
843 * vtd_page_walk - walk specific IOVA range, and call the hook
845 * @ce: context entry to walk upon
846 * @start: IOVA address to start the walk
847 * @end: IOVA range end address (start <= addr < end)
848 * @hook_fn: the hook that to be called for each detected area
849 * @private: private data for the hook function
850 * @aw: maximum address width
852 static int vtd_page_walk(VTDContextEntry
*ce
, uint64_t start
, uint64_t end
,
853 vtd_page_walk_hook hook_fn
, void *private,
854 bool notify_unmap
, uint8_t aw
)
856 dma_addr_t addr
= vtd_ce_get_slpt_base(ce
);
857 uint32_t level
= vtd_ce_get_level(ce
);
859 if (!vtd_iova_range_check(start
, ce
, aw
)) {
860 return -VTD_FR_ADDR_BEYOND_MGAW
;
863 if (!vtd_iova_range_check(end
, ce
, aw
)) {
864 /* Fix end so that it reaches the maximum */
865 end
= vtd_iova_limit(ce
, aw
);
868 return vtd_page_walk_level(addr
, start
, end
, hook_fn
, private,
869 level
, true, true, notify_unmap
, aw
);
872 /* Map a device to its corresponding domain (context-entry) */
873 static int vtd_dev_to_context_entry(IntelIOMMUState
*s
, uint8_t bus_num
,
874 uint8_t devfn
, VTDContextEntry
*ce
)
878 X86IOMMUState
*x86_iommu
= X86_IOMMU_DEVICE(s
);
880 ret_fr
= vtd_get_root_entry(s
, bus_num
, &re
);
885 if (!vtd_root_entry_present(&re
)) {
886 /* Not error - it's okay we don't have root entry. */
887 trace_vtd_re_not_present(bus_num
);
888 return -VTD_FR_ROOT_ENTRY_P
;
891 if (re
.rsvd
|| (re
.val
& VTD_ROOT_ENTRY_RSVD(s
->aw_bits
))) {
892 trace_vtd_re_invalid(re
.rsvd
, re
.val
);
893 return -VTD_FR_ROOT_ENTRY_RSVD
;
896 ret_fr
= vtd_get_context_entry_from_root(&re
, devfn
, ce
);
901 if (!vtd_ce_present(ce
)) {
902 /* Not error - it's okay we don't have context entry. */
903 trace_vtd_ce_not_present(bus_num
, devfn
);
904 return -VTD_FR_CONTEXT_ENTRY_P
;
907 if ((ce
->hi
& VTD_CONTEXT_ENTRY_RSVD_HI
) ||
908 (ce
->lo
& VTD_CONTEXT_ENTRY_RSVD_LO(s
->aw_bits
))) {
909 trace_vtd_ce_invalid(ce
->hi
, ce
->lo
);
910 return -VTD_FR_CONTEXT_ENTRY_RSVD
;
913 /* Check if the programming of context-entry is valid */
914 if (!vtd_is_level_supported(s
, vtd_ce_get_level(ce
))) {
915 trace_vtd_ce_invalid(ce
->hi
, ce
->lo
);
916 return -VTD_FR_CONTEXT_ENTRY_INV
;
919 /* Do translation type check */
920 if (!vtd_ce_type_check(x86_iommu
, ce
)) {
921 trace_vtd_ce_invalid(ce
->hi
, ce
->lo
);
922 return -VTD_FR_CONTEXT_ENTRY_INV
;
929 * Fetch translation type for specific device. Returns <0 if error
930 * happens, otherwise return the shifted type to check against
933 static int vtd_dev_get_trans_type(VTDAddressSpace
*as
)
941 ret
= vtd_dev_to_context_entry(s
, pci_bus_num(as
->bus
),
947 return vtd_ce_get_type(&ce
);
950 static bool vtd_dev_pt_enabled(VTDAddressSpace
*as
)
956 ret
= vtd_dev_get_trans_type(as
);
959 * Possibly failed to parse the context entry for some reason
960 * (e.g., during init, or any guest configuration errors on
961 * context entries). We should assume PT not enabled for
967 return ret
== VTD_CONTEXT_TT_PASS_THROUGH
;
970 /* Return whether the device is using IOMMU translation. */
971 static bool vtd_switch_address_space(VTDAddressSpace
*as
)
974 /* Whether we need to take the BQL on our own */
975 bool take_bql
= !qemu_mutex_iothread_locked();
979 use_iommu
= as
->iommu_state
->dmar_enabled
& !vtd_dev_pt_enabled(as
);
981 trace_vtd_switch_address_space(pci_bus_num(as
->bus
),
982 VTD_PCI_SLOT(as
->devfn
),
983 VTD_PCI_FUNC(as
->devfn
),
987 * It's possible that we reach here without BQL, e.g., when called
988 * from vtd_pt_enable_fast_path(). However the memory APIs need
989 * it. We'd better make sure we have had it already, or, take it.
992 qemu_mutex_lock_iothread();
995 /* Turn off first then on the other */
997 memory_region_set_enabled(&as
->sys_alias
, false);
998 memory_region_set_enabled(MEMORY_REGION(&as
->iommu
), true);
1000 memory_region_set_enabled(MEMORY_REGION(&as
->iommu
), false);
1001 memory_region_set_enabled(&as
->sys_alias
, true);
1005 qemu_mutex_unlock_iothread();
1011 static void vtd_switch_address_space_all(IntelIOMMUState
*s
)
1013 GHashTableIter iter
;
1017 g_hash_table_iter_init(&iter
, s
->vtd_as_by_busptr
);
1018 while (g_hash_table_iter_next(&iter
, NULL
, (void **)&vtd_bus
)) {
1019 for (i
= 0; i
< PCI_DEVFN_MAX
; i
++) {
1020 if (!vtd_bus
->dev_as
[i
]) {
1023 vtd_switch_address_space(vtd_bus
->dev_as
[i
]);
1028 static inline uint16_t vtd_make_source_id(uint8_t bus_num
, uint8_t devfn
)
1030 return ((bus_num
& 0xffUL
) << 8) | (devfn
& 0xffUL
);
1033 static const bool vtd_qualified_faults
[] = {
1034 [VTD_FR_RESERVED
] = false,
1035 [VTD_FR_ROOT_ENTRY_P
] = false,
1036 [VTD_FR_CONTEXT_ENTRY_P
] = true,
1037 [VTD_FR_CONTEXT_ENTRY_INV
] = true,
1038 [VTD_FR_ADDR_BEYOND_MGAW
] = true,
1039 [VTD_FR_WRITE
] = true,
1040 [VTD_FR_READ
] = true,
1041 [VTD_FR_PAGING_ENTRY_INV
] = true,
1042 [VTD_FR_ROOT_TABLE_INV
] = false,
1043 [VTD_FR_CONTEXT_TABLE_INV
] = false,
1044 [VTD_FR_ROOT_ENTRY_RSVD
] = false,
1045 [VTD_FR_PAGING_ENTRY_RSVD
] = true,
1046 [VTD_FR_CONTEXT_ENTRY_TT
] = true,
1047 [VTD_FR_RESERVED_ERR
] = false,
1048 [VTD_FR_MAX
] = false,
1051 /* To see if a fault condition is "qualified", which is reported to software
1052 * only if the FPD field in the context-entry used to process the faulting
1055 static inline bool vtd_is_qualified_fault(VTDFaultReason fault
)
1057 return vtd_qualified_faults
[fault
];
1060 static inline bool vtd_is_interrupt_addr(hwaddr addr
)
1062 return VTD_INTERRUPT_ADDR_FIRST
<= addr
&& addr
<= VTD_INTERRUPT_ADDR_LAST
;
1065 static void vtd_pt_enable_fast_path(IntelIOMMUState
*s
, uint16_t source_id
)
1068 VTDAddressSpace
*vtd_as
;
1069 bool success
= false;
1071 vtd_bus
= vtd_find_as_from_bus_num(s
, VTD_SID_TO_BUS(source_id
));
1076 vtd_as
= vtd_bus
->dev_as
[VTD_SID_TO_DEVFN(source_id
)];
1081 if (vtd_switch_address_space(vtd_as
) == false) {
1082 /* We switched off IOMMU region successfully. */
1087 trace_vtd_pt_enable_fast_path(source_id
, success
);
1090 /* Map dev to context-entry then do a paging-structures walk to do a iommu
1093 * Called from RCU critical section.
1095 * @bus_num: The bus number
1096 * @devfn: The devfn, which is the combined of device and function number
1097 * @is_write: The access is a write operation
1098 * @entry: IOMMUTLBEntry that contain the addr to be translated and result
1100 * Returns true if translation is successful, otherwise false.
1102 static bool vtd_do_iommu_translate(VTDAddressSpace
*vtd_as
, PCIBus
*bus
,
1103 uint8_t devfn
, hwaddr addr
, bool is_write
,
1104 IOMMUTLBEntry
*entry
)
1106 IntelIOMMUState
*s
= vtd_as
->iommu_state
;
1108 uint8_t bus_num
= pci_bus_num(bus
);
1109 VTDContextCacheEntry
*cc_entry
= &vtd_as
->context_cache_entry
;
1110 uint64_t slpte
, page_mask
;
1112 uint16_t source_id
= vtd_make_source_id(bus_num
, devfn
);
1114 bool is_fpd_set
= false;
1117 uint8_t access_flags
;
1118 VTDIOTLBEntry
*iotlb_entry
;
1121 * We have standalone memory region for interrupt addresses, we
1122 * should never receive translation requests in this region.
1124 assert(!vtd_is_interrupt_addr(addr
));
1126 /* Try to fetch slpte form IOTLB */
1127 iotlb_entry
= vtd_lookup_iotlb(s
, source_id
, addr
);
1129 trace_vtd_iotlb_page_hit(source_id
, addr
, iotlb_entry
->slpte
,
1130 iotlb_entry
->domain_id
);
1131 slpte
= iotlb_entry
->slpte
;
1132 access_flags
= iotlb_entry
->access_flags
;
1133 page_mask
= iotlb_entry
->mask
;
1137 /* Try to fetch context-entry from cache first */
1138 if (cc_entry
->context_cache_gen
== s
->context_cache_gen
) {
1139 trace_vtd_iotlb_cc_hit(bus_num
, devfn
, cc_entry
->context_entry
.hi
,
1140 cc_entry
->context_entry
.lo
,
1141 cc_entry
->context_cache_gen
);
1142 ce
= cc_entry
->context_entry
;
1143 is_fpd_set
= ce
.lo
& VTD_CONTEXT_ENTRY_FPD
;
1145 ret_fr
= vtd_dev_to_context_entry(s
, bus_num
, devfn
, &ce
);
1146 is_fpd_set
= ce
.lo
& VTD_CONTEXT_ENTRY_FPD
;
1149 if (is_fpd_set
&& vtd_is_qualified_fault(ret_fr
)) {
1150 trace_vtd_fault_disabled();
1152 vtd_report_dmar_fault(s
, source_id
, addr
, ret_fr
, is_write
);
1156 /* Update context-cache */
1157 trace_vtd_iotlb_cc_update(bus_num
, devfn
, ce
.hi
, ce
.lo
,
1158 cc_entry
->context_cache_gen
,
1159 s
->context_cache_gen
);
1160 cc_entry
->context_entry
= ce
;
1161 cc_entry
->context_cache_gen
= s
->context_cache_gen
;
1165 * We don't need to translate for pass-through context entries.
1166 * Also, let's ignore IOTLB caching as well for PT devices.
1168 if (vtd_ce_get_type(&ce
) == VTD_CONTEXT_TT_PASS_THROUGH
) {
1169 entry
->iova
= addr
& VTD_PAGE_MASK_4K
;
1170 entry
->translated_addr
= entry
->iova
;
1171 entry
->addr_mask
= ~VTD_PAGE_MASK_4K
;
1172 entry
->perm
= IOMMU_RW
;
1173 trace_vtd_translate_pt(source_id
, entry
->iova
);
1176 * When this happens, it means firstly caching-mode is not
1177 * enabled, and this is the first passthrough translation for
1178 * the device. Let's enable the fast path for passthrough.
1180 * When passthrough is disabled again for the device, we can
1181 * capture it via the context entry invalidation, then the
1182 * IOMMU region can be swapped back.
1184 vtd_pt_enable_fast_path(s
, source_id
);
1189 ret_fr
= vtd_iova_to_slpte(&ce
, addr
, is_write
, &slpte
, &level
,
1190 &reads
, &writes
, s
->aw_bits
);
1193 if (is_fpd_set
&& vtd_is_qualified_fault(ret_fr
)) {
1194 trace_vtd_fault_disabled();
1196 vtd_report_dmar_fault(s
, source_id
, addr
, ret_fr
, is_write
);
1201 page_mask
= vtd_slpt_level_page_mask(level
);
1202 access_flags
= IOMMU_ACCESS_FLAG(reads
, writes
);
1203 vtd_update_iotlb(s
, source_id
, VTD_CONTEXT_ENTRY_DID(ce
.hi
), addr
, slpte
,
1204 access_flags
, level
);
1206 entry
->iova
= addr
& page_mask
;
1207 entry
->translated_addr
= vtd_get_slpte_addr(slpte
, s
->aw_bits
) & page_mask
;
1208 entry
->addr_mask
= ~page_mask
;
1209 entry
->perm
= access_flags
;
1214 entry
->translated_addr
= 0;
1215 entry
->addr_mask
= 0;
1216 entry
->perm
= IOMMU_NONE
;
1220 static void vtd_root_table_setup(IntelIOMMUState
*s
)
1222 s
->root
= vtd_get_quad_raw(s
, DMAR_RTADDR_REG
);
1223 s
->root_extended
= s
->root
& VTD_RTADDR_RTT
;
1224 s
->root
&= VTD_RTADDR_ADDR_MASK(s
->aw_bits
);
1226 trace_vtd_reg_dmar_root(s
->root
, s
->root_extended
);
1229 static void vtd_iec_notify_all(IntelIOMMUState
*s
, bool global
,
1230 uint32_t index
, uint32_t mask
)
1232 x86_iommu_iec_notify_all(X86_IOMMU_DEVICE(s
), global
, index
, mask
);
1235 static void vtd_interrupt_remap_table_setup(IntelIOMMUState
*s
)
1238 value
= vtd_get_quad_raw(s
, DMAR_IRTA_REG
);
1239 s
->intr_size
= 1UL << ((value
& VTD_IRTA_SIZE_MASK
) + 1);
1240 s
->intr_root
= value
& VTD_IRTA_ADDR_MASK(s
->aw_bits
);
1241 s
->intr_eime
= value
& VTD_IRTA_EIME
;
1243 /* Notify global invalidation */
1244 vtd_iec_notify_all(s
, true, 0, 0);
1246 trace_vtd_reg_ir_root(s
->intr_root
, s
->intr_size
);
1249 static void vtd_iommu_replay_all(IntelIOMMUState
*s
)
1251 IntelIOMMUNotifierNode
*node
;
1253 QLIST_FOREACH(node
, &s
->notifiers_list
, next
) {
1254 memory_region_iommu_replay_all(&node
->vtd_as
->iommu
);
1258 static void vtd_context_global_invalidate(IntelIOMMUState
*s
)
1260 trace_vtd_inv_desc_cc_global();
1261 s
->context_cache_gen
++;
1262 if (s
->context_cache_gen
== VTD_CONTEXT_CACHE_GEN_MAX
) {
1263 vtd_reset_context_cache(s
);
1265 vtd_switch_address_space_all(s
);
1267 * From VT-d spec 6.5.2.1, a global context entry invalidation
1268 * should be followed by a IOTLB global invalidation, so we should
1269 * be safe even without this. Hoewever, let's replay the region as
1270 * well to be safer, and go back here when we need finer tunes for
1271 * VT-d emulation codes.
1273 vtd_iommu_replay_all(s
);
1276 /* Do a context-cache device-selective invalidation.
1277 * @func_mask: FM field after shifting
1279 static void vtd_context_device_invalidate(IntelIOMMUState
*s
,
1285 VTDAddressSpace
*vtd_as
;
1286 uint8_t bus_n
, devfn
;
1289 trace_vtd_inv_desc_cc_devices(source_id
, func_mask
);
1291 switch (func_mask
& 3) {
1293 mask
= 0; /* No bits in the SID field masked */
1296 mask
= 4; /* Mask bit 2 in the SID field */
1299 mask
= 6; /* Mask bit 2:1 in the SID field */
1302 mask
= 7; /* Mask bit 2:0 in the SID field */
1307 bus_n
= VTD_SID_TO_BUS(source_id
);
1308 vtd_bus
= vtd_find_as_from_bus_num(s
, bus_n
);
1310 devfn
= VTD_SID_TO_DEVFN(source_id
);
1311 for (devfn_it
= 0; devfn_it
< PCI_DEVFN_MAX
; ++devfn_it
) {
1312 vtd_as
= vtd_bus
->dev_as
[devfn_it
];
1313 if (vtd_as
&& ((devfn_it
& mask
) == (devfn
& mask
))) {
1314 trace_vtd_inv_desc_cc_device(bus_n
, VTD_PCI_SLOT(devfn_it
),
1315 VTD_PCI_FUNC(devfn_it
));
1316 vtd_as
->context_cache_entry
.context_cache_gen
= 0;
1318 * Do switch address space when needed, in case if the
1319 * device passthrough bit is switched.
1321 vtd_switch_address_space(vtd_as
);
1323 * So a device is moving out of (or moving into) a
1324 * domain, a replay() suites here to notify all the
1325 * IOMMU_NOTIFIER_MAP registers about this change.
1326 * This won't bring bad even if we have no such
1327 * notifier registered - the IOMMU notification
1328 * framework will skip MAP notifications if that
1331 memory_region_iommu_replay_all(&vtd_as
->iommu
);
1337 /* Context-cache invalidation
1338 * Returns the Context Actual Invalidation Granularity.
1339 * @val: the content of the CCMD_REG
1341 static uint64_t vtd_context_cache_invalidate(IntelIOMMUState
*s
, uint64_t val
)
1344 uint64_t type
= val
& VTD_CCMD_CIRG_MASK
;
1347 case VTD_CCMD_DOMAIN_INVL
:
1349 case VTD_CCMD_GLOBAL_INVL
:
1350 caig
= VTD_CCMD_GLOBAL_INVL_A
;
1351 vtd_context_global_invalidate(s
);
1354 case VTD_CCMD_DEVICE_INVL
:
1355 caig
= VTD_CCMD_DEVICE_INVL_A
;
1356 vtd_context_device_invalidate(s
, VTD_CCMD_SID(val
), VTD_CCMD_FM(val
));
1360 trace_vtd_err("Context cache invalidate type error.");
1366 static void vtd_iotlb_global_invalidate(IntelIOMMUState
*s
)
1368 trace_vtd_inv_desc_iotlb_global();
1370 vtd_iommu_replay_all(s
);
1373 static void vtd_iotlb_domain_invalidate(IntelIOMMUState
*s
, uint16_t domain_id
)
1375 IntelIOMMUNotifierNode
*node
;
1377 VTDAddressSpace
*vtd_as
;
1379 trace_vtd_inv_desc_iotlb_domain(domain_id
);
1381 g_hash_table_foreach_remove(s
->iotlb
, vtd_hash_remove_by_domain
,
1384 QLIST_FOREACH(node
, &s
->notifiers_list
, next
) {
1385 vtd_as
= node
->vtd_as
;
1386 if (!vtd_dev_to_context_entry(s
, pci_bus_num(vtd_as
->bus
),
1387 vtd_as
->devfn
, &ce
) &&
1388 domain_id
== VTD_CONTEXT_ENTRY_DID(ce
.hi
)) {
1389 memory_region_iommu_replay_all(&vtd_as
->iommu
);
1394 static int vtd_page_invalidate_notify_hook(IOMMUTLBEntry
*entry
,
1397 memory_region_notify_iommu((IOMMUMemoryRegion
*)private, *entry
);
1401 static void vtd_iotlb_page_invalidate_notify(IntelIOMMUState
*s
,
1402 uint16_t domain_id
, hwaddr addr
,
1405 IntelIOMMUNotifierNode
*node
;
1409 QLIST_FOREACH(node
, &(s
->notifiers_list
), next
) {
1410 VTDAddressSpace
*vtd_as
= node
->vtd_as
;
1411 ret
= vtd_dev_to_context_entry(s
, pci_bus_num(vtd_as
->bus
),
1412 vtd_as
->devfn
, &ce
);
1413 if (!ret
&& domain_id
== VTD_CONTEXT_ENTRY_DID(ce
.hi
)) {
1414 vtd_page_walk(&ce
, addr
, addr
+ (1 << am
) * VTD_PAGE_SIZE
,
1415 vtd_page_invalidate_notify_hook
,
1416 (void *)&vtd_as
->iommu
, true, s
->aw_bits
);
1421 static void vtd_iotlb_page_invalidate(IntelIOMMUState
*s
, uint16_t domain_id
,
1422 hwaddr addr
, uint8_t am
)
1424 VTDIOTLBPageInvInfo info
;
1426 trace_vtd_inv_desc_iotlb_pages(domain_id
, addr
, am
);
1428 assert(am
<= VTD_MAMV
);
1429 info
.domain_id
= domain_id
;
1431 info
.mask
= ~((1 << am
) - 1);
1432 g_hash_table_foreach_remove(s
->iotlb
, vtd_hash_remove_by_page
, &info
);
1433 vtd_iotlb_page_invalidate_notify(s
, domain_id
, addr
, am
);
1437 * Returns the IOTLB Actual Invalidation Granularity.
1438 * @val: the content of the IOTLB_REG
1440 static uint64_t vtd_iotlb_flush(IntelIOMMUState
*s
, uint64_t val
)
1443 uint64_t type
= val
& VTD_TLB_FLUSH_GRANU_MASK
;
1449 case VTD_TLB_GLOBAL_FLUSH
:
1450 iaig
= VTD_TLB_GLOBAL_FLUSH_A
;
1451 vtd_iotlb_global_invalidate(s
);
1454 case VTD_TLB_DSI_FLUSH
:
1455 domain_id
= VTD_TLB_DID(val
);
1456 iaig
= VTD_TLB_DSI_FLUSH_A
;
1457 vtd_iotlb_domain_invalidate(s
, domain_id
);
1460 case VTD_TLB_PSI_FLUSH
:
1461 domain_id
= VTD_TLB_DID(val
);
1462 addr
= vtd_get_quad_raw(s
, DMAR_IVA_REG
);
1463 am
= VTD_IVA_AM(addr
);
1464 addr
= VTD_IVA_ADDR(addr
);
1465 if (am
> VTD_MAMV
) {
1466 trace_vtd_err("IOTLB PSI flush: address mask overflow.");
1470 iaig
= VTD_TLB_PSI_FLUSH_A
;
1471 vtd_iotlb_page_invalidate(s
, domain_id
, addr
, am
);
1475 trace_vtd_err("IOTLB flush: invalid granularity.");
1481 static void vtd_fetch_inv_desc(IntelIOMMUState
*s
);
1483 static inline bool vtd_queued_inv_disable_check(IntelIOMMUState
*s
)
1485 return s
->qi_enabled
&& (s
->iq_tail
== s
->iq_head
) &&
1486 (s
->iq_last_desc_type
== VTD_INV_DESC_WAIT
);
1489 static void vtd_handle_gcmd_qie(IntelIOMMUState
*s
, bool en
)
1491 uint64_t iqa_val
= vtd_get_quad_raw(s
, DMAR_IQA_REG
);
1493 trace_vtd_inv_qi_enable(en
);
1496 s
->iq
= iqa_val
& VTD_IQA_IQA_MASK(s
->aw_bits
);
1497 /* 2^(x+8) entries */
1498 s
->iq_size
= 1UL << ((iqa_val
& VTD_IQA_QS
) + 8);
1499 s
->qi_enabled
= true;
1500 trace_vtd_inv_qi_setup(s
->iq
, s
->iq_size
);
1501 /* Ok - report back to driver */
1502 vtd_set_clear_mask_long(s
, DMAR_GSTS_REG
, 0, VTD_GSTS_QIES
);
1504 if (s
->iq_tail
!= 0) {
1506 * This is a spec violation but Windows guests are known to set up
1507 * Queued Invalidation this way so we allow the write and process
1508 * Invalidation Descriptors right away.
1510 trace_vtd_warn_invalid_qi_tail(s
->iq_tail
);
1511 if (!(vtd_get_long_raw(s
, DMAR_FSTS_REG
) & VTD_FSTS_IQE
)) {
1512 vtd_fetch_inv_desc(s
);
1516 if (vtd_queued_inv_disable_check(s
)) {
1517 /* disable Queued Invalidation */
1518 vtd_set_quad_raw(s
, DMAR_IQH_REG
, 0);
1520 s
->qi_enabled
= false;
1521 /* Ok - report back to driver */
1522 vtd_set_clear_mask_long(s
, DMAR_GSTS_REG
, VTD_GSTS_QIES
, 0);
1524 trace_vtd_err_qi_disable(s
->iq_head
, s
->iq_tail
, s
->iq_last_desc_type
);
1529 /* Set Root Table Pointer */
1530 static void vtd_handle_gcmd_srtp(IntelIOMMUState
*s
)
1532 vtd_root_table_setup(s
);
1533 /* Ok - report back to driver */
1534 vtd_set_clear_mask_long(s
, DMAR_GSTS_REG
, 0, VTD_GSTS_RTPS
);
1537 /* Set Interrupt Remap Table Pointer */
1538 static void vtd_handle_gcmd_sirtp(IntelIOMMUState
*s
)
1540 vtd_interrupt_remap_table_setup(s
);
1541 /* Ok - report back to driver */
1542 vtd_set_clear_mask_long(s
, DMAR_GSTS_REG
, 0, VTD_GSTS_IRTPS
);
1545 /* Handle Translation Enable/Disable */
1546 static void vtd_handle_gcmd_te(IntelIOMMUState
*s
, bool en
)
1548 if (s
->dmar_enabled
== en
) {
1552 trace_vtd_dmar_enable(en
);
1555 s
->dmar_enabled
= true;
1556 /* Ok - report back to driver */
1557 vtd_set_clear_mask_long(s
, DMAR_GSTS_REG
, 0, VTD_GSTS_TES
);
1559 s
->dmar_enabled
= false;
1561 /* Clear the index of Fault Recording Register */
1562 s
->next_frcd_reg
= 0;
1563 /* Ok - report back to driver */
1564 vtd_set_clear_mask_long(s
, DMAR_GSTS_REG
, VTD_GSTS_TES
, 0);
1567 vtd_switch_address_space_all(s
);
1570 /* Handle Interrupt Remap Enable/Disable */
1571 static void vtd_handle_gcmd_ire(IntelIOMMUState
*s
, bool en
)
1573 trace_vtd_ir_enable(en
);
1576 s
->intr_enabled
= true;
1577 /* Ok - report back to driver */
1578 vtd_set_clear_mask_long(s
, DMAR_GSTS_REG
, 0, VTD_GSTS_IRES
);
1580 s
->intr_enabled
= false;
1581 /* Ok - report back to driver */
1582 vtd_set_clear_mask_long(s
, DMAR_GSTS_REG
, VTD_GSTS_IRES
, 0);
1586 /* Handle write to Global Command Register */
1587 static void vtd_handle_gcmd_write(IntelIOMMUState
*s
)
1589 uint32_t status
= vtd_get_long_raw(s
, DMAR_GSTS_REG
);
1590 uint32_t val
= vtd_get_long_raw(s
, DMAR_GCMD_REG
);
1591 uint32_t changed
= status
^ val
;
1593 trace_vtd_reg_write_gcmd(status
, val
);
1594 if (changed
& VTD_GCMD_TE
) {
1595 /* Translation enable/disable */
1596 vtd_handle_gcmd_te(s
, val
& VTD_GCMD_TE
);
1598 if (val
& VTD_GCMD_SRTP
) {
1599 /* Set/update the root-table pointer */
1600 vtd_handle_gcmd_srtp(s
);
1602 if (changed
& VTD_GCMD_QIE
) {
1603 /* Queued Invalidation Enable */
1604 vtd_handle_gcmd_qie(s
, val
& VTD_GCMD_QIE
);
1606 if (val
& VTD_GCMD_SIRTP
) {
1607 /* Set/update the interrupt remapping root-table pointer */
1608 vtd_handle_gcmd_sirtp(s
);
1610 if (changed
& VTD_GCMD_IRE
) {
1611 /* Interrupt remap enable/disable */
1612 vtd_handle_gcmd_ire(s
, val
& VTD_GCMD_IRE
);
1616 /* Handle write to Context Command Register */
1617 static void vtd_handle_ccmd_write(IntelIOMMUState
*s
)
1620 uint64_t val
= vtd_get_quad_raw(s
, DMAR_CCMD_REG
);
1622 /* Context-cache invalidation request */
1623 if (val
& VTD_CCMD_ICC
) {
1624 if (s
->qi_enabled
) {
1625 trace_vtd_err("Queued Invalidation enabled, "
1626 "should not use register-based invalidation");
1629 ret
= vtd_context_cache_invalidate(s
, val
);
1630 /* Invalidation completed. Change something to show */
1631 vtd_set_clear_mask_quad(s
, DMAR_CCMD_REG
, VTD_CCMD_ICC
, 0ULL);
1632 ret
= vtd_set_clear_mask_quad(s
, DMAR_CCMD_REG
, VTD_CCMD_CAIG_MASK
,
1637 /* Handle write to IOTLB Invalidation Register */
1638 static void vtd_handle_iotlb_write(IntelIOMMUState
*s
)
1641 uint64_t val
= vtd_get_quad_raw(s
, DMAR_IOTLB_REG
);
1643 /* IOTLB invalidation request */
1644 if (val
& VTD_TLB_IVT
) {
1645 if (s
->qi_enabled
) {
1646 trace_vtd_err("Queued Invalidation enabled, "
1647 "should not use register-based invalidation.");
1650 ret
= vtd_iotlb_flush(s
, val
);
1651 /* Invalidation completed. Change something to show */
1652 vtd_set_clear_mask_quad(s
, DMAR_IOTLB_REG
, VTD_TLB_IVT
, 0ULL);
1653 ret
= vtd_set_clear_mask_quad(s
, DMAR_IOTLB_REG
,
1654 VTD_TLB_FLUSH_GRANU_MASK_A
, ret
);
1658 /* Fetch an Invalidation Descriptor from the Invalidation Queue */
1659 static bool vtd_get_inv_desc(dma_addr_t base_addr
, uint32_t offset
,
1660 VTDInvDesc
*inv_desc
)
1662 dma_addr_t addr
= base_addr
+ offset
* sizeof(*inv_desc
);
1663 if (dma_memory_read(&address_space_memory
, addr
, inv_desc
,
1664 sizeof(*inv_desc
))) {
1665 trace_vtd_err("Read INV DESC failed.");
1670 inv_desc
->lo
= le64_to_cpu(inv_desc
->lo
);
1671 inv_desc
->hi
= le64_to_cpu(inv_desc
->hi
);
1675 static bool vtd_process_wait_desc(IntelIOMMUState
*s
, VTDInvDesc
*inv_desc
)
1677 if ((inv_desc
->hi
& VTD_INV_DESC_WAIT_RSVD_HI
) ||
1678 (inv_desc
->lo
& VTD_INV_DESC_WAIT_RSVD_LO
)) {
1679 trace_vtd_inv_desc_wait_invalid(inv_desc
->hi
, inv_desc
->lo
);
1682 if (inv_desc
->lo
& VTD_INV_DESC_WAIT_SW
) {
1684 uint32_t status_data
= (uint32_t)(inv_desc
->lo
>>
1685 VTD_INV_DESC_WAIT_DATA_SHIFT
);
1687 assert(!(inv_desc
->lo
& VTD_INV_DESC_WAIT_IF
));
1689 /* FIXME: need to be masked with HAW? */
1690 dma_addr_t status_addr
= inv_desc
->hi
;
1691 trace_vtd_inv_desc_wait_sw(status_addr
, status_data
);
1692 status_data
= cpu_to_le32(status_data
);
1693 if (dma_memory_write(&address_space_memory
, status_addr
, &status_data
,
1694 sizeof(status_data
))) {
1695 trace_vtd_inv_desc_wait_write_fail(inv_desc
->hi
, inv_desc
->lo
);
1698 } else if (inv_desc
->lo
& VTD_INV_DESC_WAIT_IF
) {
1699 /* Interrupt flag */
1700 vtd_generate_completion_event(s
);
1702 trace_vtd_inv_desc_wait_invalid(inv_desc
->hi
, inv_desc
->lo
);
1708 static bool vtd_process_context_cache_desc(IntelIOMMUState
*s
,
1709 VTDInvDesc
*inv_desc
)
1711 uint16_t sid
, fmask
;
1713 if ((inv_desc
->lo
& VTD_INV_DESC_CC_RSVD
) || inv_desc
->hi
) {
1714 trace_vtd_inv_desc_cc_invalid(inv_desc
->hi
, inv_desc
->lo
);
1717 switch (inv_desc
->lo
& VTD_INV_DESC_CC_G
) {
1718 case VTD_INV_DESC_CC_DOMAIN
:
1719 trace_vtd_inv_desc_cc_domain(
1720 (uint16_t)VTD_INV_DESC_CC_DID(inv_desc
->lo
));
1722 case VTD_INV_DESC_CC_GLOBAL
:
1723 vtd_context_global_invalidate(s
);
1726 case VTD_INV_DESC_CC_DEVICE
:
1727 sid
= VTD_INV_DESC_CC_SID(inv_desc
->lo
);
1728 fmask
= VTD_INV_DESC_CC_FM(inv_desc
->lo
);
1729 vtd_context_device_invalidate(s
, sid
, fmask
);
1733 trace_vtd_inv_desc_cc_invalid(inv_desc
->hi
, inv_desc
->lo
);
1739 static bool vtd_process_iotlb_desc(IntelIOMMUState
*s
, VTDInvDesc
*inv_desc
)
1745 if ((inv_desc
->lo
& VTD_INV_DESC_IOTLB_RSVD_LO
) ||
1746 (inv_desc
->hi
& VTD_INV_DESC_IOTLB_RSVD_HI
)) {
1747 trace_vtd_inv_desc_iotlb_invalid(inv_desc
->hi
, inv_desc
->lo
);
1751 switch (inv_desc
->lo
& VTD_INV_DESC_IOTLB_G
) {
1752 case VTD_INV_DESC_IOTLB_GLOBAL
:
1753 vtd_iotlb_global_invalidate(s
);
1756 case VTD_INV_DESC_IOTLB_DOMAIN
:
1757 domain_id
= VTD_INV_DESC_IOTLB_DID(inv_desc
->lo
);
1758 vtd_iotlb_domain_invalidate(s
, domain_id
);
1761 case VTD_INV_DESC_IOTLB_PAGE
:
1762 domain_id
= VTD_INV_DESC_IOTLB_DID(inv_desc
->lo
);
1763 addr
= VTD_INV_DESC_IOTLB_ADDR(inv_desc
->hi
);
1764 am
= VTD_INV_DESC_IOTLB_AM(inv_desc
->hi
);
1765 if (am
> VTD_MAMV
) {
1766 trace_vtd_inv_desc_iotlb_invalid(inv_desc
->hi
, inv_desc
->lo
);
1769 vtd_iotlb_page_invalidate(s
, domain_id
, addr
, am
);
1773 trace_vtd_inv_desc_iotlb_invalid(inv_desc
->hi
, inv_desc
->lo
);
1779 static bool vtd_process_inv_iec_desc(IntelIOMMUState
*s
,
1780 VTDInvDesc
*inv_desc
)
1782 trace_vtd_inv_desc_iec(inv_desc
->iec
.granularity
,
1783 inv_desc
->iec
.index
,
1784 inv_desc
->iec
.index_mask
);
1786 vtd_iec_notify_all(s
, !inv_desc
->iec
.granularity
,
1787 inv_desc
->iec
.index
,
1788 inv_desc
->iec
.index_mask
);
1792 static bool vtd_process_device_iotlb_desc(IntelIOMMUState
*s
,
1793 VTDInvDesc
*inv_desc
)
1795 VTDAddressSpace
*vtd_dev_as
;
1796 IOMMUTLBEntry entry
;
1797 struct VTDBus
*vtd_bus
;
1805 addr
= VTD_INV_DESC_DEVICE_IOTLB_ADDR(inv_desc
->hi
);
1806 sid
= VTD_INV_DESC_DEVICE_IOTLB_SID(inv_desc
->lo
);
1809 size
= VTD_INV_DESC_DEVICE_IOTLB_SIZE(inv_desc
->hi
);
1811 if ((inv_desc
->lo
& VTD_INV_DESC_DEVICE_IOTLB_RSVD_LO
) ||
1812 (inv_desc
->hi
& VTD_INV_DESC_DEVICE_IOTLB_RSVD_HI
)) {
1813 trace_vtd_inv_desc_iotlb_invalid(inv_desc
->hi
, inv_desc
->lo
);
1817 vtd_bus
= vtd_find_as_from_bus_num(s
, bus_num
);
1822 vtd_dev_as
= vtd_bus
->dev_as
[devfn
];
1827 /* According to ATS spec table 2.4:
1828 * S = 0, bits 15:12 = xxxx range size: 4K
1829 * S = 1, bits 15:12 = xxx0 range size: 8K
1830 * S = 1, bits 15:12 = xx01 range size: 16K
1831 * S = 1, bits 15:12 = x011 range size: 32K
1832 * S = 1, bits 15:12 = 0111 range size: 64K
1836 sz
= (VTD_PAGE_SIZE
* 2) << cto64(addr
>> VTD_PAGE_SHIFT
);
1842 entry
.target_as
= &vtd_dev_as
->as
;
1843 entry
.addr_mask
= sz
- 1;
1845 entry
.perm
= IOMMU_NONE
;
1846 entry
.translated_addr
= 0;
1847 memory_region_notify_iommu(&vtd_dev_as
->iommu
, entry
);
1853 static bool vtd_process_inv_desc(IntelIOMMUState
*s
)
1855 VTDInvDesc inv_desc
;
1858 trace_vtd_inv_qi_head(s
->iq_head
);
1859 if (!vtd_get_inv_desc(s
->iq
, s
->iq_head
, &inv_desc
)) {
1860 s
->iq_last_desc_type
= VTD_INV_DESC_NONE
;
1863 desc_type
= inv_desc
.lo
& VTD_INV_DESC_TYPE
;
1864 /* FIXME: should update at first or at last? */
1865 s
->iq_last_desc_type
= desc_type
;
1867 switch (desc_type
) {
1868 case VTD_INV_DESC_CC
:
1869 trace_vtd_inv_desc("context-cache", inv_desc
.hi
, inv_desc
.lo
);
1870 if (!vtd_process_context_cache_desc(s
, &inv_desc
)) {
1875 case VTD_INV_DESC_IOTLB
:
1876 trace_vtd_inv_desc("iotlb", inv_desc
.hi
, inv_desc
.lo
);
1877 if (!vtd_process_iotlb_desc(s
, &inv_desc
)) {
1882 case VTD_INV_DESC_WAIT
:
1883 trace_vtd_inv_desc("wait", inv_desc
.hi
, inv_desc
.lo
);
1884 if (!vtd_process_wait_desc(s
, &inv_desc
)) {
1889 case VTD_INV_DESC_IEC
:
1890 trace_vtd_inv_desc("iec", inv_desc
.hi
, inv_desc
.lo
);
1891 if (!vtd_process_inv_iec_desc(s
, &inv_desc
)) {
1896 case VTD_INV_DESC_DEVICE
:
1897 trace_vtd_inv_desc("device", inv_desc
.hi
, inv_desc
.lo
);
1898 if (!vtd_process_device_iotlb_desc(s
, &inv_desc
)) {
1904 trace_vtd_inv_desc_invalid(inv_desc
.hi
, inv_desc
.lo
);
1908 if (s
->iq_head
== s
->iq_size
) {
1914 /* Try to fetch and process more Invalidation Descriptors */
1915 static void vtd_fetch_inv_desc(IntelIOMMUState
*s
)
1917 trace_vtd_inv_qi_fetch();
1919 if (s
->iq_tail
>= s
->iq_size
) {
1920 /* Detects an invalid Tail pointer */
1921 trace_vtd_err_qi_tail(s
->iq_tail
, s
->iq_size
);
1922 vtd_handle_inv_queue_error(s
);
1925 while (s
->iq_head
!= s
->iq_tail
) {
1926 if (!vtd_process_inv_desc(s
)) {
1927 /* Invalidation Queue Errors */
1928 vtd_handle_inv_queue_error(s
);
1931 /* Must update the IQH_REG in time */
1932 vtd_set_quad_raw(s
, DMAR_IQH_REG
,
1933 (((uint64_t)(s
->iq_head
)) << VTD_IQH_QH_SHIFT
) &
1938 /* Handle write to Invalidation Queue Tail Register */
1939 static void vtd_handle_iqt_write(IntelIOMMUState
*s
)
1941 uint64_t val
= vtd_get_quad_raw(s
, DMAR_IQT_REG
);
1943 s
->iq_tail
= VTD_IQT_QT(val
);
1944 trace_vtd_inv_qi_tail(s
->iq_tail
);
1946 if (s
->qi_enabled
&& !(vtd_get_long_raw(s
, DMAR_FSTS_REG
) & VTD_FSTS_IQE
)) {
1947 /* Process Invalidation Queue here */
1948 vtd_fetch_inv_desc(s
);
1952 static void vtd_handle_fsts_write(IntelIOMMUState
*s
)
1954 uint32_t fsts_reg
= vtd_get_long_raw(s
, DMAR_FSTS_REG
);
1955 uint32_t fectl_reg
= vtd_get_long_raw(s
, DMAR_FECTL_REG
);
1956 uint32_t status_fields
= VTD_FSTS_PFO
| VTD_FSTS_PPF
| VTD_FSTS_IQE
;
1958 if ((fectl_reg
& VTD_FECTL_IP
) && !(fsts_reg
& status_fields
)) {
1959 vtd_set_clear_mask_long(s
, DMAR_FECTL_REG
, VTD_FECTL_IP
, 0);
1960 trace_vtd_fsts_clear_ip();
1962 /* FIXME: when IQE is Clear, should we try to fetch some Invalidation
1963 * Descriptors if there are any when Queued Invalidation is enabled?
1967 static void vtd_handle_fectl_write(IntelIOMMUState
*s
)
1970 /* FIXME: when software clears the IM field, check the IP field. But do we
1971 * need to compare the old value and the new value to conclude that
1972 * software clears the IM field? Or just check if the IM field is zero?
1974 fectl_reg
= vtd_get_long_raw(s
, DMAR_FECTL_REG
);
1976 trace_vtd_reg_write_fectl(fectl_reg
);
1978 if ((fectl_reg
& VTD_FECTL_IP
) && !(fectl_reg
& VTD_FECTL_IM
)) {
1979 vtd_generate_interrupt(s
, DMAR_FEADDR_REG
, DMAR_FEDATA_REG
);
1980 vtd_set_clear_mask_long(s
, DMAR_FECTL_REG
, VTD_FECTL_IP
, 0);
1984 static void vtd_handle_ics_write(IntelIOMMUState
*s
)
1986 uint32_t ics_reg
= vtd_get_long_raw(s
, DMAR_ICS_REG
);
1987 uint32_t iectl_reg
= vtd_get_long_raw(s
, DMAR_IECTL_REG
);
1989 if ((iectl_reg
& VTD_IECTL_IP
) && !(ics_reg
& VTD_ICS_IWC
)) {
1990 trace_vtd_reg_ics_clear_ip();
1991 vtd_set_clear_mask_long(s
, DMAR_IECTL_REG
, VTD_IECTL_IP
, 0);
1995 static void vtd_handle_iectl_write(IntelIOMMUState
*s
)
1998 /* FIXME: when software clears the IM field, check the IP field. But do we
1999 * need to compare the old value and the new value to conclude that
2000 * software clears the IM field? Or just check if the IM field is zero?
2002 iectl_reg
= vtd_get_long_raw(s
, DMAR_IECTL_REG
);
2004 trace_vtd_reg_write_iectl(iectl_reg
);
2006 if ((iectl_reg
& VTD_IECTL_IP
) && !(iectl_reg
& VTD_IECTL_IM
)) {
2007 vtd_generate_interrupt(s
, DMAR_IEADDR_REG
, DMAR_IEDATA_REG
);
2008 vtd_set_clear_mask_long(s
, DMAR_IECTL_REG
, VTD_IECTL_IP
, 0);
2012 static uint64_t vtd_mem_read(void *opaque
, hwaddr addr
, unsigned size
)
2014 IntelIOMMUState
*s
= opaque
;
2017 trace_vtd_reg_read(addr
, size
);
2019 if (addr
+ size
> DMAR_REG_SIZE
) {
2020 trace_vtd_err("Read MMIO over range.");
2021 return (uint64_t)-1;
2025 /* Root Table Address Register, 64-bit */
2026 case DMAR_RTADDR_REG
:
2028 val
= s
->root
& ((1ULL << 32) - 1);
2034 case DMAR_RTADDR_REG_HI
:
2036 val
= s
->root
>> 32;
2039 /* Invalidation Queue Address Register, 64-bit */
2041 val
= s
->iq
| (vtd_get_quad(s
, DMAR_IQA_REG
) & VTD_IQA_QS
);
2043 val
= val
& ((1ULL << 32) - 1);
2047 case DMAR_IQA_REG_HI
:
2054 val
= vtd_get_long(s
, addr
);
2056 val
= vtd_get_quad(s
, addr
);
2063 static void vtd_mem_write(void *opaque
, hwaddr addr
,
2064 uint64_t val
, unsigned size
)
2066 IntelIOMMUState
*s
= opaque
;
2068 trace_vtd_reg_write(addr
, size
, val
);
2070 if (addr
+ size
> DMAR_REG_SIZE
) {
2071 trace_vtd_err("Write MMIO over range.");
2076 /* Global Command Register, 32-bit */
2078 vtd_set_long(s
, addr
, val
);
2079 vtd_handle_gcmd_write(s
);
2082 /* Context Command Register, 64-bit */
2085 vtd_set_long(s
, addr
, val
);
2087 vtd_set_quad(s
, addr
, val
);
2088 vtd_handle_ccmd_write(s
);
2092 case DMAR_CCMD_REG_HI
:
2094 vtd_set_long(s
, addr
, val
);
2095 vtd_handle_ccmd_write(s
);
2098 /* IOTLB Invalidation Register, 64-bit */
2099 case DMAR_IOTLB_REG
:
2101 vtd_set_long(s
, addr
, val
);
2103 vtd_set_quad(s
, addr
, val
);
2104 vtd_handle_iotlb_write(s
);
2108 case DMAR_IOTLB_REG_HI
:
2110 vtd_set_long(s
, addr
, val
);
2111 vtd_handle_iotlb_write(s
);
2114 /* Invalidate Address Register, 64-bit */
2117 vtd_set_long(s
, addr
, val
);
2119 vtd_set_quad(s
, addr
, val
);
2123 case DMAR_IVA_REG_HI
:
2125 vtd_set_long(s
, addr
, val
);
2128 /* Fault Status Register, 32-bit */
2131 vtd_set_long(s
, addr
, val
);
2132 vtd_handle_fsts_write(s
);
2135 /* Fault Event Control Register, 32-bit */
2136 case DMAR_FECTL_REG
:
2138 vtd_set_long(s
, addr
, val
);
2139 vtd_handle_fectl_write(s
);
2142 /* Fault Event Data Register, 32-bit */
2143 case DMAR_FEDATA_REG
:
2145 vtd_set_long(s
, addr
, val
);
2148 /* Fault Event Address Register, 32-bit */
2149 case DMAR_FEADDR_REG
:
2151 vtd_set_long(s
, addr
, val
);
2154 * While the register is 32-bit only, some guests (Xen...) write to
2157 vtd_set_quad(s
, addr
, val
);
2161 /* Fault Event Upper Address Register, 32-bit */
2162 case DMAR_FEUADDR_REG
:
2164 vtd_set_long(s
, addr
, val
);
2167 /* Protected Memory Enable Register, 32-bit */
2170 vtd_set_long(s
, addr
, val
);
2173 /* Root Table Address Register, 64-bit */
2174 case DMAR_RTADDR_REG
:
2176 vtd_set_long(s
, addr
, val
);
2178 vtd_set_quad(s
, addr
, val
);
2182 case DMAR_RTADDR_REG_HI
:
2184 vtd_set_long(s
, addr
, val
);
2187 /* Invalidation Queue Tail Register, 64-bit */
2190 vtd_set_long(s
, addr
, val
);
2192 vtd_set_quad(s
, addr
, val
);
2194 vtd_handle_iqt_write(s
);
2197 case DMAR_IQT_REG_HI
:
2199 vtd_set_long(s
, addr
, val
);
2200 /* 19:63 of IQT_REG is RsvdZ, do nothing here */
2203 /* Invalidation Queue Address Register, 64-bit */
2206 vtd_set_long(s
, addr
, val
);
2208 vtd_set_quad(s
, addr
, val
);
2212 case DMAR_IQA_REG_HI
:
2214 vtd_set_long(s
, addr
, val
);
2217 /* Invalidation Completion Status Register, 32-bit */
2220 vtd_set_long(s
, addr
, val
);
2221 vtd_handle_ics_write(s
);
2224 /* Invalidation Event Control Register, 32-bit */
2225 case DMAR_IECTL_REG
:
2227 vtd_set_long(s
, addr
, val
);
2228 vtd_handle_iectl_write(s
);
2231 /* Invalidation Event Data Register, 32-bit */
2232 case DMAR_IEDATA_REG
:
2234 vtd_set_long(s
, addr
, val
);
2237 /* Invalidation Event Address Register, 32-bit */
2238 case DMAR_IEADDR_REG
:
2240 vtd_set_long(s
, addr
, val
);
2243 /* Invalidation Event Upper Address Register, 32-bit */
2244 case DMAR_IEUADDR_REG
:
2246 vtd_set_long(s
, addr
, val
);
2249 /* Fault Recording Registers, 128-bit */
2250 case DMAR_FRCD_REG_0_0
:
2252 vtd_set_long(s
, addr
, val
);
2254 vtd_set_quad(s
, addr
, val
);
2258 case DMAR_FRCD_REG_0_1
:
2260 vtd_set_long(s
, addr
, val
);
2263 case DMAR_FRCD_REG_0_2
:
2265 vtd_set_long(s
, addr
, val
);
2267 vtd_set_quad(s
, addr
, val
);
2268 /* May clear bit 127 (Fault), update PPF */
2269 vtd_update_fsts_ppf(s
);
2273 case DMAR_FRCD_REG_0_3
:
2275 vtd_set_long(s
, addr
, val
);
2276 /* May clear bit 127 (Fault), update PPF */
2277 vtd_update_fsts_ppf(s
);
2282 vtd_set_long(s
, addr
, val
);
2284 vtd_set_quad(s
, addr
, val
);
2288 case DMAR_IRTA_REG_HI
:
2290 vtd_set_long(s
, addr
, val
);
2295 vtd_set_long(s
, addr
, val
);
2297 vtd_set_quad(s
, addr
, val
);
2302 static IOMMUTLBEntry
vtd_iommu_translate(IOMMUMemoryRegion
*iommu
, hwaddr addr
,
2303 IOMMUAccessFlags flag
)
2305 VTDAddressSpace
*vtd_as
= container_of(iommu
, VTDAddressSpace
, iommu
);
2306 IntelIOMMUState
*s
= vtd_as
->iommu_state
;
2307 IOMMUTLBEntry iotlb
= {
2308 /* We'll fill in the rest later. */
2309 .target_as
= &address_space_memory
,
2313 if (likely(s
->dmar_enabled
)) {
2314 success
= vtd_do_iommu_translate(vtd_as
, vtd_as
->bus
, vtd_as
->devfn
,
2315 addr
, flag
& IOMMU_WO
, &iotlb
);
2317 /* DMAR disabled, passthrough, use 4k-page*/
2318 iotlb
.iova
= addr
& VTD_PAGE_MASK_4K
;
2319 iotlb
.translated_addr
= addr
& VTD_PAGE_MASK_4K
;
2320 iotlb
.addr_mask
= ~VTD_PAGE_MASK_4K
;
2321 iotlb
.perm
= IOMMU_RW
;
2325 if (likely(success
)) {
2326 trace_vtd_dmar_translate(pci_bus_num(vtd_as
->bus
),
2327 VTD_PCI_SLOT(vtd_as
->devfn
),
2328 VTD_PCI_FUNC(vtd_as
->devfn
),
2329 iotlb
.iova
, iotlb
.translated_addr
,
2332 trace_vtd_err_dmar_translate(pci_bus_num(vtd_as
->bus
),
2333 VTD_PCI_SLOT(vtd_as
->devfn
),
2334 VTD_PCI_FUNC(vtd_as
->devfn
),
2341 static void vtd_iommu_notify_flag_changed(IOMMUMemoryRegion
*iommu
,
2342 IOMMUNotifierFlag old
,
2343 IOMMUNotifierFlag
new)
2345 VTDAddressSpace
*vtd_as
= container_of(iommu
, VTDAddressSpace
, iommu
);
2346 IntelIOMMUState
*s
= vtd_as
->iommu_state
;
2347 IntelIOMMUNotifierNode
*node
= NULL
;
2348 IntelIOMMUNotifierNode
*next_node
= NULL
;
2350 if (!s
->caching_mode
&& new & IOMMU_NOTIFIER_MAP
) {
2351 error_report("We need to set caching-mode=1 for intel-iommu to enable "
2352 "device assignment with IOMMU protection.");
2356 if (old
== IOMMU_NOTIFIER_NONE
) {
2357 node
= g_malloc0(sizeof(*node
));
2358 node
->vtd_as
= vtd_as
;
2359 QLIST_INSERT_HEAD(&s
->notifiers_list
, node
, next
);
2363 /* update notifier node with new flags */
2364 QLIST_FOREACH_SAFE(node
, &s
->notifiers_list
, next
, next_node
) {
2365 if (node
->vtd_as
== vtd_as
) {
2366 if (new == IOMMU_NOTIFIER_NONE
) {
2367 QLIST_REMOVE(node
, next
);
2375 static int vtd_post_load(void *opaque
, int version_id
)
2377 IntelIOMMUState
*iommu
= opaque
;
2380 * Memory regions are dynamically turned on/off depending on
2381 * context entry configurations from the guest. After migration,
2382 * we need to make sure the memory regions are still correct.
2384 vtd_switch_address_space_all(iommu
);
2389 static const VMStateDescription vtd_vmstate
= {
2390 .name
= "iommu-intel",
2392 .minimum_version_id
= 1,
2393 .priority
= MIG_PRI_IOMMU
,
2394 .post_load
= vtd_post_load
,
2395 .fields
= (VMStateField
[]) {
2396 VMSTATE_UINT64(root
, IntelIOMMUState
),
2397 VMSTATE_UINT64(intr_root
, IntelIOMMUState
),
2398 VMSTATE_UINT64(iq
, IntelIOMMUState
),
2399 VMSTATE_UINT32(intr_size
, IntelIOMMUState
),
2400 VMSTATE_UINT16(iq_head
, IntelIOMMUState
),
2401 VMSTATE_UINT16(iq_tail
, IntelIOMMUState
),
2402 VMSTATE_UINT16(iq_size
, IntelIOMMUState
),
2403 VMSTATE_UINT16(next_frcd_reg
, IntelIOMMUState
),
2404 VMSTATE_UINT8_ARRAY(csr
, IntelIOMMUState
, DMAR_REG_SIZE
),
2405 VMSTATE_UINT8(iq_last_desc_type
, IntelIOMMUState
),
2406 VMSTATE_BOOL(root_extended
, IntelIOMMUState
),
2407 VMSTATE_BOOL(dmar_enabled
, IntelIOMMUState
),
2408 VMSTATE_BOOL(qi_enabled
, IntelIOMMUState
),
2409 VMSTATE_BOOL(intr_enabled
, IntelIOMMUState
),
2410 VMSTATE_BOOL(intr_eime
, IntelIOMMUState
),
2411 VMSTATE_END_OF_LIST()
2415 static const MemoryRegionOps vtd_mem_ops
= {
2416 .read
= vtd_mem_read
,
2417 .write
= vtd_mem_write
,
2418 .endianness
= DEVICE_LITTLE_ENDIAN
,
2420 .min_access_size
= 4,
2421 .max_access_size
= 8,
2424 .min_access_size
= 4,
2425 .max_access_size
= 8,
2429 static Property vtd_properties
[] = {
2430 DEFINE_PROP_UINT32("version", IntelIOMMUState
, version
, 0),
2431 DEFINE_PROP_ON_OFF_AUTO("eim", IntelIOMMUState
, intr_eim
,
2433 DEFINE_PROP_BOOL("x-buggy-eim", IntelIOMMUState
, buggy_eim
, false),
2434 DEFINE_PROP_UINT8("x-aw-bits", IntelIOMMUState
, aw_bits
,
2435 VTD_HOST_ADDRESS_WIDTH
),
2436 DEFINE_PROP_BOOL("caching-mode", IntelIOMMUState
, caching_mode
, FALSE
),
2437 DEFINE_PROP_END_OF_LIST(),
2440 /* Read IRTE entry with specific index */
2441 static int vtd_irte_get(IntelIOMMUState
*iommu
, uint16_t index
,
2442 VTD_IR_TableEntry
*entry
, uint16_t sid
)
2444 static const uint16_t vtd_svt_mask
[VTD_SQ_MAX
] = \
2445 {0xffff, 0xfffb, 0xfff9, 0xfff8};
2446 dma_addr_t addr
= 0x00;
2447 uint16_t mask
, source_id
;
2448 uint8_t bus
, bus_max
, bus_min
;
2450 addr
= iommu
->intr_root
+ index
* sizeof(*entry
);
2451 if (dma_memory_read(&address_space_memory
, addr
, entry
,
2453 trace_vtd_err("Memory read failed for IRTE.");
2454 return -VTD_FR_IR_ROOT_INVAL
;
2457 trace_vtd_ir_irte_get(index
, le64_to_cpu(entry
->data
[1]),
2458 le64_to_cpu(entry
->data
[0]));
2460 if (!entry
->irte
.present
) {
2461 trace_vtd_err_irte(index
, le64_to_cpu(entry
->data
[1]),
2462 le64_to_cpu(entry
->data
[0]));
2463 return -VTD_FR_IR_ENTRY_P
;
2466 if (entry
->irte
.__reserved_0
|| entry
->irte
.__reserved_1
||
2467 entry
->irte
.__reserved_2
) {
2468 trace_vtd_err_irte(index
, le64_to_cpu(entry
->data
[1]),
2469 le64_to_cpu(entry
->data
[0]));
2470 return -VTD_FR_IR_IRTE_RSVD
;
2473 if (sid
!= X86_IOMMU_SID_INVALID
) {
2474 /* Validate IRTE SID */
2475 source_id
= le32_to_cpu(entry
->irte
.source_id
);
2476 switch (entry
->irte
.sid_vtype
) {
2481 mask
= vtd_svt_mask
[entry
->irte
.sid_q
];
2482 if ((source_id
& mask
) != (sid
& mask
)) {
2483 trace_vtd_err_irte_sid(index
, sid
, source_id
);
2484 return -VTD_FR_IR_SID_ERR
;
2489 bus_max
= source_id
>> 8;
2490 bus_min
= source_id
& 0xff;
2492 if (bus
> bus_max
|| bus
< bus_min
) {
2493 trace_vtd_err_irte_sid_bus(index
, bus
, bus_min
, bus_max
);
2494 return -VTD_FR_IR_SID_ERR
;
2499 trace_vtd_err_irte_svt(index
, entry
->irte
.sid_vtype
);
2500 /* Take this as verification failure. */
2501 return -VTD_FR_IR_SID_ERR
;
2509 /* Fetch IRQ information of specific IR index */
2510 static int vtd_remap_irq_get(IntelIOMMUState
*iommu
, uint16_t index
,
2511 VTDIrq
*irq
, uint16_t sid
)
2513 VTD_IR_TableEntry irte
= {};
2516 ret
= vtd_irte_get(iommu
, index
, &irte
, sid
);
2521 irq
->trigger_mode
= irte
.irte
.trigger_mode
;
2522 irq
->vector
= irte
.irte
.vector
;
2523 irq
->delivery_mode
= irte
.irte
.delivery_mode
;
2524 irq
->dest
= le32_to_cpu(irte
.irte
.dest_id
);
2525 if (!iommu
->intr_eime
) {
2526 #define VTD_IR_APIC_DEST_MASK (0xff00ULL)
2527 #define VTD_IR_APIC_DEST_SHIFT (8)
2528 irq
->dest
= (irq
->dest
& VTD_IR_APIC_DEST_MASK
) >>
2529 VTD_IR_APIC_DEST_SHIFT
;
2531 irq
->dest_mode
= irte
.irte
.dest_mode
;
2532 irq
->redir_hint
= irte
.irte
.redir_hint
;
2534 trace_vtd_ir_remap(index
, irq
->trigger_mode
, irq
->vector
,
2535 irq
->delivery_mode
, irq
->dest
, irq
->dest_mode
);
2540 /* Generate one MSI message from VTDIrq info */
2541 static void vtd_generate_msi_message(VTDIrq
*irq
, MSIMessage
*msg_out
)
2543 VTD_MSIMessage msg
= {};
2545 /* Generate address bits */
2546 msg
.dest_mode
= irq
->dest_mode
;
2547 msg
.redir_hint
= irq
->redir_hint
;
2548 msg
.dest
= irq
->dest
;
2549 msg
.__addr_hi
= irq
->dest
& 0xffffff00;
2550 msg
.__addr_head
= cpu_to_le32(0xfee);
2551 /* Keep this from original MSI address bits */
2552 msg
.__not_used
= irq
->msi_addr_last_bits
;
2554 /* Generate data bits */
2555 msg
.vector
= irq
->vector
;
2556 msg
.delivery_mode
= irq
->delivery_mode
;
2558 msg
.trigger_mode
= irq
->trigger_mode
;
2560 msg_out
->address
= msg
.msi_addr
;
2561 msg_out
->data
= msg
.msi_data
;
2564 /* Interrupt remapping for MSI/MSI-X entry */
2565 static int vtd_interrupt_remap_msi(IntelIOMMUState
*iommu
,
2567 MSIMessage
*translated
,
2571 VTD_IR_MSIAddress addr
;
2575 assert(origin
&& translated
);
2577 trace_vtd_ir_remap_msi_req(origin
->address
, origin
->data
);
2579 if (!iommu
|| !iommu
->intr_enabled
) {
2580 memcpy(translated
, origin
, sizeof(*origin
));
2584 if (origin
->address
& VTD_MSI_ADDR_HI_MASK
) {
2585 trace_vtd_err("MSI address high 32 bits non-zero when "
2586 "Interrupt Remapping enabled.");
2587 return -VTD_FR_IR_REQ_RSVD
;
2590 addr
.data
= origin
->address
& VTD_MSI_ADDR_LO_MASK
;
2591 if (addr
.addr
.__head
!= 0xfee) {
2592 trace_vtd_err("MSI addr low 32 bit invalid.");
2593 return -VTD_FR_IR_REQ_RSVD
;
2596 /* This is compatible mode. */
2597 if (addr
.addr
.int_mode
!= VTD_IR_INT_FORMAT_REMAP
) {
2598 memcpy(translated
, origin
, sizeof(*origin
));
2602 index
= addr
.addr
.index_h
<< 15 | le16_to_cpu(addr
.addr
.index_l
);
2604 #define VTD_IR_MSI_DATA_SUBHANDLE (0x0000ffff)
2605 #define VTD_IR_MSI_DATA_RESERVED (0xffff0000)
2607 if (addr
.addr
.sub_valid
) {
2608 /* See VT-d spec 5.1.2.2 and 5.1.3 on subhandle */
2609 index
+= origin
->data
& VTD_IR_MSI_DATA_SUBHANDLE
;
2612 ret
= vtd_remap_irq_get(iommu
, index
, &irq
, sid
);
2617 if (addr
.addr
.sub_valid
) {
2618 trace_vtd_ir_remap_type("MSI");
2619 if (origin
->data
& VTD_IR_MSI_DATA_RESERVED
) {
2620 trace_vtd_err_ir_msi_invalid(sid
, origin
->address
, origin
->data
);
2621 return -VTD_FR_IR_REQ_RSVD
;
2624 uint8_t vector
= origin
->data
& 0xff;
2625 uint8_t trigger_mode
= (origin
->data
>> MSI_DATA_TRIGGER_SHIFT
) & 0x1;
2627 trace_vtd_ir_remap_type("IOAPIC");
2628 /* IOAPIC entry vector should be aligned with IRTE vector
2629 * (see vt-d spec 5.1.5.1). */
2630 if (vector
!= irq
.vector
) {
2631 trace_vtd_warn_ir_vector(sid
, index
, vector
, irq
.vector
);
2634 /* The Trigger Mode field must match the Trigger Mode in the IRTE.
2635 * (see vt-d spec 5.1.5.1). */
2636 if (trigger_mode
!= irq
.trigger_mode
) {
2637 trace_vtd_warn_ir_trigger(sid
, index
, trigger_mode
,
2643 * We'd better keep the last two bits, assuming that guest OS
2644 * might modify it. Keep it does not hurt after all.
2646 irq
.msi_addr_last_bits
= addr
.addr
.__not_care
;
2648 /* Translate VTDIrq to MSI message */
2649 vtd_generate_msi_message(&irq
, translated
);
2652 trace_vtd_ir_remap_msi(origin
->address
, origin
->data
,
2653 translated
->address
, translated
->data
);
2657 static int vtd_int_remap(X86IOMMUState
*iommu
, MSIMessage
*src
,
2658 MSIMessage
*dst
, uint16_t sid
)
2660 return vtd_interrupt_remap_msi(INTEL_IOMMU_DEVICE(iommu
),
2664 static MemTxResult
vtd_mem_ir_read(void *opaque
, hwaddr addr
,
2665 uint64_t *data
, unsigned size
,
2671 static MemTxResult
vtd_mem_ir_write(void *opaque
, hwaddr addr
,
2672 uint64_t value
, unsigned size
,
2676 MSIMessage from
= {}, to
= {};
2677 uint16_t sid
= X86_IOMMU_SID_INVALID
;
2679 from
.address
= (uint64_t) addr
+ VTD_INTERRUPT_ADDR_FIRST
;
2680 from
.data
= (uint32_t) value
;
2682 if (!attrs
.unspecified
) {
2683 /* We have explicit Source ID */
2684 sid
= attrs
.requester_id
;
2687 ret
= vtd_interrupt_remap_msi(opaque
, &from
, &to
, sid
);
2689 /* TODO: report error */
2690 /* Drop this interrupt */
2694 apic_get_class()->send_msi(&to
);
2699 static const MemoryRegionOps vtd_mem_ir_ops
= {
2700 .read_with_attrs
= vtd_mem_ir_read
,
2701 .write_with_attrs
= vtd_mem_ir_write
,
2702 .endianness
= DEVICE_LITTLE_ENDIAN
,
2704 .min_access_size
= 4,
2705 .max_access_size
= 4,
2708 .min_access_size
= 4,
2709 .max_access_size
= 4,
2713 VTDAddressSpace
*vtd_find_add_as(IntelIOMMUState
*s
, PCIBus
*bus
, int devfn
)
2715 uintptr_t key
= (uintptr_t)bus
;
2716 VTDBus
*vtd_bus
= g_hash_table_lookup(s
->vtd_as_by_busptr
, &key
);
2717 VTDAddressSpace
*vtd_dev_as
;
2721 uintptr_t *new_key
= g_malloc(sizeof(*new_key
));
2722 *new_key
= (uintptr_t)bus
;
2723 /* No corresponding free() */
2724 vtd_bus
= g_malloc0(sizeof(VTDBus
) + sizeof(VTDAddressSpace
*) * \
2727 g_hash_table_insert(s
->vtd_as_by_busptr
, new_key
, vtd_bus
);
2730 vtd_dev_as
= vtd_bus
->dev_as
[devfn
];
2733 snprintf(name
, sizeof(name
), "intel_iommu_devfn_%d", devfn
);
2734 vtd_bus
->dev_as
[devfn
] = vtd_dev_as
= g_malloc0(sizeof(VTDAddressSpace
));
2736 vtd_dev_as
->bus
= bus
;
2737 vtd_dev_as
->devfn
= (uint8_t)devfn
;
2738 vtd_dev_as
->iommu_state
= s
;
2739 vtd_dev_as
->context_cache_entry
.context_cache_gen
= 0;
2742 * Memory region relationships looks like (Address range shows
2743 * only lower 32 bits to make it short in length...):
2745 * |-----------------+-------------------+----------|
2746 * | Name | Address range | Priority |
2747 * |-----------------+-------------------+----------+
2748 * | vtd_root | 00000000-ffffffff | 0 |
2749 * | intel_iommu | 00000000-ffffffff | 1 |
2750 * | vtd_sys_alias | 00000000-ffffffff | 1 |
2751 * | intel_iommu_ir | fee00000-feefffff | 64 |
2752 * |-----------------+-------------------+----------|
2754 * We enable/disable DMAR by switching enablement for
2755 * vtd_sys_alias and intel_iommu regions. IR region is always
2758 memory_region_init_iommu(&vtd_dev_as
->iommu
, sizeof(vtd_dev_as
->iommu
),
2759 TYPE_INTEL_IOMMU_MEMORY_REGION
, OBJECT(s
),
2762 memory_region_init_alias(&vtd_dev_as
->sys_alias
, OBJECT(s
),
2763 "vtd_sys_alias", get_system_memory(),
2764 0, memory_region_size(get_system_memory()));
2765 memory_region_init_io(&vtd_dev_as
->iommu_ir
, OBJECT(s
),
2766 &vtd_mem_ir_ops
, s
, "intel_iommu_ir",
2767 VTD_INTERRUPT_ADDR_SIZE
);
2768 memory_region_init(&vtd_dev_as
->root
, OBJECT(s
),
2769 "vtd_root", UINT64_MAX
);
2770 memory_region_add_subregion_overlap(&vtd_dev_as
->root
,
2771 VTD_INTERRUPT_ADDR_FIRST
,
2772 &vtd_dev_as
->iommu_ir
, 64);
2773 address_space_init(&vtd_dev_as
->as
, &vtd_dev_as
->root
, name
);
2774 memory_region_add_subregion_overlap(&vtd_dev_as
->root
, 0,
2775 &vtd_dev_as
->sys_alias
, 1);
2776 memory_region_add_subregion_overlap(&vtd_dev_as
->root
, 0,
2777 MEMORY_REGION(&vtd_dev_as
->iommu
),
2779 vtd_switch_address_space(vtd_dev_as
);
2784 /* Unmap the whole range in the notifier's scope. */
2785 static void vtd_address_space_unmap(VTDAddressSpace
*as
, IOMMUNotifier
*n
)
2787 IOMMUTLBEntry entry
;
2789 hwaddr start
= n
->start
;
2790 hwaddr end
= n
->end
;
2791 IntelIOMMUState
*s
= as
->iommu_state
;
2794 * Note: all the codes in this function has a assumption that IOVA
2795 * bits are no more than VTD_MGAW bits (which is restricted by
2796 * VT-d spec), otherwise we need to consider overflow of 64 bits.
2799 if (end
> VTD_ADDRESS_SIZE(s
->aw_bits
)) {
2801 * Don't need to unmap regions that is bigger than the whole
2802 * VT-d supported address space size
2804 end
= VTD_ADDRESS_SIZE(s
->aw_bits
);
2807 assert(start
<= end
);
2810 if (ctpop64(size
) != 1) {
2812 * This size cannot format a correct mask. Let's enlarge it to
2813 * suite the minimum available mask.
2815 int n
= 64 - clz64(size
);
2816 if (n
> s
->aw_bits
) {
2817 /* should not happen, but in case it happens, limit it */
2823 entry
.target_as
= &address_space_memory
;
2824 /* Adjust iova for the size */
2825 entry
.iova
= n
->start
& ~(size
- 1);
2826 /* This field is meaningless for unmap */
2827 entry
.translated_addr
= 0;
2828 entry
.perm
= IOMMU_NONE
;
2829 entry
.addr_mask
= size
- 1;
2831 trace_vtd_as_unmap_whole(pci_bus_num(as
->bus
),
2832 VTD_PCI_SLOT(as
->devfn
),
2833 VTD_PCI_FUNC(as
->devfn
),
2836 memory_region_notify_one(n
, &entry
);
2839 static void vtd_address_space_unmap_all(IntelIOMMUState
*s
)
2841 IntelIOMMUNotifierNode
*node
;
2842 VTDAddressSpace
*vtd_as
;
2845 QLIST_FOREACH(node
, &s
->notifiers_list
, next
) {
2846 vtd_as
= node
->vtd_as
;
2847 IOMMU_NOTIFIER_FOREACH(n
, &vtd_as
->iommu
) {
2848 vtd_address_space_unmap(vtd_as
, n
);
2853 static int vtd_replay_hook(IOMMUTLBEntry
*entry
, void *private)
2855 memory_region_notify_one((IOMMUNotifier
*)private, entry
);
2859 static void vtd_iommu_replay(IOMMUMemoryRegion
*iommu_mr
, IOMMUNotifier
*n
)
2861 VTDAddressSpace
*vtd_as
= container_of(iommu_mr
, VTDAddressSpace
, iommu
);
2862 IntelIOMMUState
*s
= vtd_as
->iommu_state
;
2863 uint8_t bus_n
= pci_bus_num(vtd_as
->bus
);
2867 * The replay can be triggered by either a invalidation or a newly
2868 * created entry. No matter what, we release existing mappings
2869 * (it means flushing caches for UNMAP-only registers).
2871 vtd_address_space_unmap(vtd_as
, n
);
2873 if (vtd_dev_to_context_entry(s
, bus_n
, vtd_as
->devfn
, &ce
) == 0) {
2874 trace_vtd_replay_ce_valid(bus_n
, PCI_SLOT(vtd_as
->devfn
),
2875 PCI_FUNC(vtd_as
->devfn
),
2876 VTD_CONTEXT_ENTRY_DID(ce
.hi
),
2878 vtd_page_walk(&ce
, 0, ~0ULL, vtd_replay_hook
, (void *)n
, false,
2881 trace_vtd_replay_ce_invalid(bus_n
, PCI_SLOT(vtd_as
->devfn
),
2882 PCI_FUNC(vtd_as
->devfn
));
2888 /* Do the initialization. It will also be called when reset, so pay
2889 * attention when adding new initialization stuff.
2891 static void vtd_init(IntelIOMMUState
*s
)
2893 X86IOMMUState
*x86_iommu
= X86_IOMMU_DEVICE(s
);
2895 memset(s
->csr
, 0, DMAR_REG_SIZE
);
2896 memset(s
->wmask
, 0, DMAR_REG_SIZE
);
2897 memset(s
->w1cmask
, 0, DMAR_REG_SIZE
);
2898 memset(s
->womask
, 0, DMAR_REG_SIZE
);
2901 s
->root_extended
= false;
2902 s
->dmar_enabled
= false;
2907 s
->qi_enabled
= false;
2908 s
->iq_last_desc_type
= VTD_INV_DESC_NONE
;
2909 s
->next_frcd_reg
= 0;
2910 s
->cap
= VTD_CAP_FRO
| VTD_CAP_NFR
| VTD_CAP_ND
|
2911 VTD_CAP_MAMV
| VTD_CAP_PSI
| VTD_CAP_SLLPS
|
2912 VTD_CAP_SAGAW_39bit
| VTD_CAP_MGAW(s
->aw_bits
);
2913 if (s
->aw_bits
== VTD_HOST_AW_48BIT
) {
2914 s
->cap
|= VTD_CAP_SAGAW_48bit
;
2916 s
->ecap
= VTD_ECAP_QI
| VTD_ECAP_IRO
;
2919 * Rsvd field masks for spte
2921 vtd_paging_entry_rsvd_field
[0] = ~0ULL;
2922 vtd_paging_entry_rsvd_field
[1] = VTD_SPTE_PAGE_L1_RSVD_MASK(s
->aw_bits
);
2923 vtd_paging_entry_rsvd_field
[2] = VTD_SPTE_PAGE_L2_RSVD_MASK(s
->aw_bits
);
2924 vtd_paging_entry_rsvd_field
[3] = VTD_SPTE_PAGE_L3_RSVD_MASK(s
->aw_bits
);
2925 vtd_paging_entry_rsvd_field
[4] = VTD_SPTE_PAGE_L4_RSVD_MASK(s
->aw_bits
);
2926 vtd_paging_entry_rsvd_field
[5] = VTD_SPTE_LPAGE_L1_RSVD_MASK(s
->aw_bits
);
2927 vtd_paging_entry_rsvd_field
[6] = VTD_SPTE_LPAGE_L2_RSVD_MASK(s
->aw_bits
);
2928 vtd_paging_entry_rsvd_field
[7] = VTD_SPTE_LPAGE_L3_RSVD_MASK(s
->aw_bits
);
2929 vtd_paging_entry_rsvd_field
[8] = VTD_SPTE_LPAGE_L4_RSVD_MASK(s
->aw_bits
);
2931 if (x86_iommu
->intr_supported
) {
2932 s
->ecap
|= VTD_ECAP_IR
| VTD_ECAP_MHMV
;
2933 if (s
->intr_eim
== ON_OFF_AUTO_ON
) {
2934 s
->ecap
|= VTD_ECAP_EIM
;
2936 assert(s
->intr_eim
!= ON_OFF_AUTO_AUTO
);
2939 if (x86_iommu
->dt_supported
) {
2940 s
->ecap
|= VTD_ECAP_DT
;
2943 if (x86_iommu
->pt_supported
) {
2944 s
->ecap
|= VTD_ECAP_PT
;
2947 if (s
->caching_mode
) {
2948 s
->cap
|= VTD_CAP_CM
;
2951 vtd_reset_context_cache(s
);
2954 /* Define registers with default values and bit semantics */
2955 vtd_define_long(s
, DMAR_VER_REG
, 0x10UL
, 0, 0);
2956 vtd_define_quad(s
, DMAR_CAP_REG
, s
->cap
, 0, 0);
2957 vtd_define_quad(s
, DMAR_ECAP_REG
, s
->ecap
, 0, 0);
2958 vtd_define_long(s
, DMAR_GCMD_REG
, 0, 0xff800000UL
, 0);
2959 vtd_define_long_wo(s
, DMAR_GCMD_REG
, 0xff800000UL
);
2960 vtd_define_long(s
, DMAR_GSTS_REG
, 0, 0, 0);
2961 vtd_define_quad(s
, DMAR_RTADDR_REG
, 0, 0xfffffffffffff000ULL
, 0);
2962 vtd_define_quad(s
, DMAR_CCMD_REG
, 0, 0xe0000003ffffffffULL
, 0);
2963 vtd_define_quad_wo(s
, DMAR_CCMD_REG
, 0x3ffff0000ULL
);
2965 /* Advanced Fault Logging not supported */
2966 vtd_define_long(s
, DMAR_FSTS_REG
, 0, 0, 0x11UL
);
2967 vtd_define_long(s
, DMAR_FECTL_REG
, 0x80000000UL
, 0x80000000UL
, 0);
2968 vtd_define_long(s
, DMAR_FEDATA_REG
, 0, 0x0000ffffUL
, 0);
2969 vtd_define_long(s
, DMAR_FEADDR_REG
, 0, 0xfffffffcUL
, 0);
2971 /* Treated as RsvdZ when EIM in ECAP_REG is not supported
2972 * vtd_define_long(s, DMAR_FEUADDR_REG, 0, 0xffffffffUL, 0);
2974 vtd_define_long(s
, DMAR_FEUADDR_REG
, 0, 0, 0);
2976 /* Treated as RO for implementations that PLMR and PHMR fields reported
2977 * as Clear in the CAP_REG.
2978 * vtd_define_long(s, DMAR_PMEN_REG, 0, 0x80000000UL, 0);
2980 vtd_define_long(s
, DMAR_PMEN_REG
, 0, 0, 0);
2982 vtd_define_quad(s
, DMAR_IQH_REG
, 0, 0, 0);
2983 vtd_define_quad(s
, DMAR_IQT_REG
, 0, 0x7fff0ULL
, 0);
2984 vtd_define_quad(s
, DMAR_IQA_REG
, 0, 0xfffffffffffff007ULL
, 0);
2985 vtd_define_long(s
, DMAR_ICS_REG
, 0, 0, 0x1UL
);
2986 vtd_define_long(s
, DMAR_IECTL_REG
, 0x80000000UL
, 0x80000000UL
, 0);
2987 vtd_define_long(s
, DMAR_IEDATA_REG
, 0, 0xffffffffUL
, 0);
2988 vtd_define_long(s
, DMAR_IEADDR_REG
, 0, 0xfffffffcUL
, 0);
2989 /* Treadted as RsvdZ when EIM in ECAP_REG is not supported */
2990 vtd_define_long(s
, DMAR_IEUADDR_REG
, 0, 0, 0);
2992 /* IOTLB registers */
2993 vtd_define_quad(s
, DMAR_IOTLB_REG
, 0, 0Xb003ffff00000000ULL
, 0);
2994 vtd_define_quad(s
, DMAR_IVA_REG
, 0, 0xfffffffffffff07fULL
, 0);
2995 vtd_define_quad_wo(s
, DMAR_IVA_REG
, 0xfffffffffffff07fULL
);
2997 /* Fault Recording Registers, 128-bit */
2998 vtd_define_quad(s
, DMAR_FRCD_REG_0_0
, 0, 0, 0);
2999 vtd_define_quad(s
, DMAR_FRCD_REG_0_2
, 0, 0, 0x8000000000000000ULL
);
3002 * Interrupt remapping registers.
3004 vtd_define_quad(s
, DMAR_IRTA_REG
, 0, 0xfffffffffffff80fULL
, 0);
3007 /* Should not reset address_spaces when reset because devices will still use
3008 * the address space they got at first (won't ask the bus again).
3010 static void vtd_reset(DeviceState
*dev
)
3012 IntelIOMMUState
*s
= INTEL_IOMMU_DEVICE(dev
);
3017 * When device reset, throw away all mappings and external caches
3019 vtd_address_space_unmap_all(s
);
3022 static AddressSpace
*vtd_host_dma_iommu(PCIBus
*bus
, void *opaque
, int devfn
)
3024 IntelIOMMUState
*s
= opaque
;
3025 VTDAddressSpace
*vtd_as
;
3027 assert(0 <= devfn
&& devfn
< PCI_DEVFN_MAX
);
3029 vtd_as
= vtd_find_add_as(s
, bus
, devfn
);
3033 static bool vtd_decide_config(IntelIOMMUState
*s
, Error
**errp
)
3035 X86IOMMUState
*x86_iommu
= X86_IOMMU_DEVICE(s
);
3037 /* Currently Intel IOMMU IR only support "kernel-irqchip={off|split}" */
3038 if (x86_iommu
->intr_supported
&& kvm_irqchip_in_kernel() &&
3039 !kvm_irqchip_is_split()) {
3040 error_setg(errp
, "Intel Interrupt Remapping cannot work with "
3041 "kernel-irqchip=on, please use 'split|off'.");
3044 if (s
->intr_eim
== ON_OFF_AUTO_ON
&& !x86_iommu
->intr_supported
) {
3045 error_setg(errp
, "eim=on cannot be selected without intremap=on");
3049 if (s
->intr_eim
== ON_OFF_AUTO_AUTO
) {
3050 s
->intr_eim
= (kvm_irqchip_in_kernel() || s
->buggy_eim
)
3051 && x86_iommu
->intr_supported
?
3052 ON_OFF_AUTO_ON
: ON_OFF_AUTO_OFF
;
3054 if (s
->intr_eim
== ON_OFF_AUTO_ON
&& !s
->buggy_eim
) {
3055 if (!kvm_irqchip_in_kernel()) {
3056 error_setg(errp
, "eim=on requires accel=kvm,kernel-irqchip=split");
3059 if (!kvm_enable_x2apic()) {
3060 error_setg(errp
, "eim=on requires support on the KVM side"
3061 "(X2APIC_API, first shipped in v4.7)");
3066 /* Currently only address widths supported are 39 and 48 bits */
3067 if ((s
->aw_bits
!= VTD_HOST_AW_39BIT
) &&
3068 (s
->aw_bits
!= VTD_HOST_AW_48BIT
)) {
3069 error_setg(errp
, "Supported values for x-aw-bits are: %d, %d",
3070 VTD_HOST_AW_39BIT
, VTD_HOST_AW_48BIT
);
3077 static void vtd_realize(DeviceState
*dev
, Error
**errp
)
3079 MachineState
*ms
= MACHINE(qdev_get_machine());
3080 PCMachineState
*pcms
= PC_MACHINE(ms
);
3081 PCIBus
*bus
= pcms
->bus
;
3082 IntelIOMMUState
*s
= INTEL_IOMMU_DEVICE(dev
);
3083 X86IOMMUState
*x86_iommu
= X86_IOMMU_DEVICE(dev
);
3085 x86_iommu
->type
= TYPE_INTEL
;
3087 if (!vtd_decide_config(s
, errp
)) {
3091 QLIST_INIT(&s
->notifiers_list
);
3092 memset(s
->vtd_as_by_bus_num
, 0, sizeof(s
->vtd_as_by_bus_num
));
3093 memory_region_init_io(&s
->csrmem
, OBJECT(s
), &vtd_mem_ops
, s
,
3094 "intel_iommu", DMAR_REG_SIZE
);
3095 sysbus_init_mmio(SYS_BUS_DEVICE(s
), &s
->csrmem
);
3096 /* No corresponding destroy */
3097 s
->iotlb
= g_hash_table_new_full(vtd_uint64_hash
, vtd_uint64_equal
,
3099 s
->vtd_as_by_busptr
= g_hash_table_new_full(vtd_uint64_hash
, vtd_uint64_equal
,
3102 sysbus_mmio_map(SYS_BUS_DEVICE(s
), 0, Q35_HOST_BRIDGE_IOMMU_ADDR
);
3103 pci_setup_iommu(bus
, vtd_host_dma_iommu
, dev
);
3104 /* Pseudo address space under root PCI bus. */
3105 pcms
->ioapic_as
= vtd_host_dma_iommu(bus
, s
, Q35_PSEUDO_DEVFN_IOAPIC
);
3108 static void vtd_class_init(ObjectClass
*klass
, void *data
)
3110 DeviceClass
*dc
= DEVICE_CLASS(klass
);
3111 X86IOMMUClass
*x86_class
= X86_IOMMU_CLASS(klass
);
3113 dc
->reset
= vtd_reset
;
3114 dc
->vmsd
= &vtd_vmstate
;
3115 dc
->props
= vtd_properties
;
3116 dc
->hotpluggable
= false;
3117 x86_class
->realize
= vtd_realize
;
3118 x86_class
->int_remap
= vtd_int_remap
;
3119 /* Supported by the pc-q35-* machine types */
3120 dc
->user_creatable
= true;
3123 static const TypeInfo vtd_info
= {
3124 .name
= TYPE_INTEL_IOMMU_DEVICE
,
3125 .parent
= TYPE_X86_IOMMU_DEVICE
,
3126 .instance_size
= sizeof(IntelIOMMUState
),
3127 .class_init
= vtd_class_init
,
3130 static void vtd_iommu_memory_region_class_init(ObjectClass
*klass
,
3133 IOMMUMemoryRegionClass
*imrc
= IOMMU_MEMORY_REGION_CLASS(klass
);
3135 imrc
->translate
= vtd_iommu_translate
;
3136 imrc
->notify_flag_changed
= vtd_iommu_notify_flag_changed
;
3137 imrc
->replay
= vtd_iommu_replay
;
3140 static const TypeInfo vtd_iommu_memory_region_info
= {
3141 .parent
= TYPE_IOMMU_MEMORY_REGION
,
3142 .name
= TYPE_INTEL_IOMMU_MEMORY_REGION
,
3143 .class_init
= vtd_iommu_memory_region_class_init
,
3146 static void vtd_register_types(void)
3148 type_register_static(&vtd_info
);
3149 type_register_static(&vtd_iommu_memory_region_info
);
3152 type_init(vtd_register_types
)