2 * QEMU IDE Emulation: MacIO support.
4 * Copyright (c) 2003 Fabrice Bellard
5 * Copyright (c) 2006 Openedhand Ltd.
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 #include "qemu/osdep.h"
28 #include "hw/ppc/mac_dbdma.h"
29 #include "hw/qdev-properties.h"
30 #include "migration/vmstate.h"
31 #include "qemu/module.h"
32 #include "hw/misc/macio/macio.h"
33 #include "sysemu/block-backend.h"
34 #include "sysemu/dma.h"
36 #include "hw/ide/internal.h"
39 // #define DEBUG_MACIO
42 static const int debug_macio
= 1;
44 static const int debug_macio
= 0;
47 #define MACIO_DPRINTF(fmt, ...) do { \
49 printf(fmt , ## __VA_ARGS__); \
54 /***********************************************************/
55 /* MacIO based PowerPC IDE */
57 #define MACIO_PAGE_SIZE 4096
59 static void pmac_ide_atapi_transfer_cb(void *opaque
, int ret
)
61 DBDMA_io
*io
= opaque
;
62 MACIOIDEState
*m
= io
->opaque
;
63 IDEState
*s
= ide_bus_active_if(&m
->bus
);
66 MACIO_DPRINTF("pmac_ide_atapi_transfer_cb\n");
69 MACIO_DPRINTF("DMA error: %d\n", ret
);
70 qemu_sglist_destroy(&s
->sg
);
71 ide_atapi_io_error(s
, ret
);
76 MACIO_DPRINTF("waiting for data (%#x - %#x - %x)\n",
77 s
->nsector
, io
->len
, s
->status
);
78 /* data not ready yet, wait for the channel to get restarted */
79 io
->processing
= false;
83 if (s
->io_buffer_size
<= 0) {
84 MACIO_DPRINTF("End of IDE transfer\n");
85 qemu_sglist_destroy(&s
->sg
);
87 m
->dma_active
= false;
92 MACIO_DPRINTF("End of DMA transfer\n");
97 /* Non-block ATAPI transfer - just copy to RAM */
98 s
->io_buffer_size
= MIN(s
->io_buffer_size
, io
->len
);
99 dma_memory_write(&address_space_memory
, io
->addr
, s
->io_buffer
,
100 s
->io_buffer_size
, MEMTXATTRS_UNSPECIFIED
);
103 m
->dma_active
= false;
107 /* Calculate current offset */
108 offset
= ((int64_t)s
->lba
<< 11) + s
->io_buffer_index
;
110 qemu_sglist_init(&s
->sg
, DEVICE(m
), io
->len
/ MACIO_PAGE_SIZE
+ 1,
111 &address_space_memory
);
112 qemu_sglist_add(&s
->sg
, io
->addr
, io
->len
);
113 s
->io_buffer_size
-= io
->len
;
114 s
->io_buffer_index
+= io
->len
;
117 s
->bus
->dma
->aiocb
= dma_blk_read(s
->blk
, &s
->sg
, offset
, 0x1,
118 pmac_ide_atapi_transfer_cb
, io
);
122 dma_memory_unmap(&address_space_memory
, io
->dma_mem
, io
->dma_len
,
123 io
->dir
, io
->dma_len
);
126 block_acct_failed(blk_get_stats(s
->blk
), &s
->acct
);
128 block_acct_done(blk_get_stats(s
->blk
), &s
->acct
);
131 ide_set_inactive(s
, false);
135 static void pmac_ide_transfer_cb(void *opaque
, int ret
)
137 DBDMA_io
*io
= opaque
;
138 MACIOIDEState
*m
= io
->opaque
;
139 IDEState
*s
= ide_bus_active_if(&m
->bus
);
142 MACIO_DPRINTF("pmac_ide_transfer_cb\n");
145 MACIO_DPRINTF("DMA error: %d\n", ret
);
146 qemu_sglist_destroy(&s
->sg
);
151 if (!m
->dma_active
) {
152 MACIO_DPRINTF("waiting for data (%#x - %#x - %x)\n",
153 s
->nsector
, io
->len
, s
->status
);
154 /* data not ready yet, wait for the channel to get restarted */
155 io
->processing
= false;
159 if (s
->io_buffer_size
<= 0) {
160 MACIO_DPRINTF("End of IDE transfer\n");
161 qemu_sglist_destroy(&s
->sg
);
162 s
->status
= READY_STAT
| SEEK_STAT
;
163 ide_bus_set_irq(s
->bus
);
164 m
->dma_active
= false;
169 MACIO_DPRINTF("End of DMA transfer\n");
173 /* Calculate number of sectors */
174 offset
= (ide_get_sector(s
) << 9) + s
->io_buffer_index
;
176 qemu_sglist_init(&s
->sg
, DEVICE(m
), io
->len
/ MACIO_PAGE_SIZE
+ 1,
177 &address_space_memory
);
178 qemu_sglist_add(&s
->sg
, io
->addr
, io
->len
);
179 s
->io_buffer_size
-= io
->len
;
180 s
->io_buffer_index
+= io
->len
;
183 switch (s
->dma_cmd
) {
185 s
->bus
->dma
->aiocb
= dma_blk_read(s
->blk
, &s
->sg
, offset
, 0x1,
186 pmac_ide_atapi_transfer_cb
, io
);
189 s
->bus
->dma
->aiocb
= dma_blk_write(s
->blk
, &s
->sg
, offset
, 0x1,
190 pmac_ide_transfer_cb
, io
);
193 s
->bus
->dma
->aiocb
= dma_blk_io(blk_get_aio_context(s
->blk
), &s
->sg
,
194 offset
, 0x1, ide_issue_trim
, s
,
195 pmac_ide_transfer_cb
, io
,
196 DMA_DIRECTION_TO_DEVICE
);
205 dma_memory_unmap(&address_space_memory
, io
->dma_mem
, io
->dma_len
,
206 io
->dir
, io
->dma_len
);
208 if (s
->dma_cmd
== IDE_DMA_READ
|| s
->dma_cmd
== IDE_DMA_WRITE
) {
210 block_acct_failed(blk_get_stats(s
->blk
), &s
->acct
);
212 block_acct_done(blk_get_stats(s
->blk
), &s
->acct
);
216 ide_set_inactive(s
, false);
220 static void pmac_ide_transfer(DBDMA_io
*io
)
222 MACIOIDEState
*m
= io
->opaque
;
223 IDEState
*s
= ide_bus_active_if(&m
->bus
);
227 if (s
->drive_kind
== IDE_CD
) {
228 block_acct_start(blk_get_stats(s
->blk
), &s
->acct
, io
->len
,
231 pmac_ide_atapi_transfer_cb(io
, 0);
235 switch (s
->dma_cmd
) {
237 block_acct_start(blk_get_stats(s
->blk
), &s
->acct
, io
->len
,
241 block_acct_start(blk_get_stats(s
->blk
), &s
->acct
, io
->len
,
248 pmac_ide_transfer_cb(io
, 0);
251 static void pmac_ide_flush(DBDMA_io
*io
)
253 MACIOIDEState
*m
= io
->opaque
;
254 IDEState
*s
= ide_bus_active_if(&m
->bus
);
256 if (s
->bus
->dma
->aiocb
) {
261 /* PowerMac IDE memory IO */
262 static uint64_t pmac_ide_read(void *opaque
, hwaddr addr
, unsigned size
)
264 MACIOIDEState
*d
= opaque
;
265 uint64_t retval
= 0xffffffff;
271 retval
= ide_data_readw(&d
->bus
, 0) & 0xFF;
272 } else if (size
== 2) {
273 retval
= ide_data_readw(&d
->bus
, 0);
274 } else if (size
== 4) {
275 retval
= ide_data_readl(&d
->bus
, 0);
280 retval
= ide_ioport_read(&d
->bus
, reg
);
286 retval
= ide_status_read(&d
->bus
, 0);
291 retval
= d
->timing_reg
;
295 /* This is an interrupt state register that only exists
296 * in the KeyLargo and later variants. Bit 0x8000_0000
297 * latches the DMA interrupt and has to be written to
298 * clear. Bit 0x4000_0000 is an image of the disk
299 * interrupt. MacOS X relies on this and will hang if
300 * we don't provide at least the disk interrupt
312 static void pmac_ide_write(void *opaque
, hwaddr addr
, uint64_t val
,
315 MACIOIDEState
*d
= opaque
;
321 ide_data_writew(&d
->bus
, 0, val
);
322 } else if (size
== 4) {
323 ide_data_writel(&d
->bus
, 0, val
);
328 ide_ioport_write(&d
->bus
, reg
, val
);
334 ide_ctrl_write(&d
->bus
, 0, val
);
344 if (val
& 0x80000000u
) {
345 d
->irq_reg
&= 0x7fffffff;
352 static const MemoryRegionOps pmac_ide_ops
= {
353 .read
= pmac_ide_read
,
354 .write
= pmac_ide_write
,
355 .valid
.min_access_size
= 1,
356 .valid
.max_access_size
= 4,
357 .endianness
= DEVICE_LITTLE_ENDIAN
,
360 static const VMStateDescription vmstate_pmac
= {
363 .minimum_version_id
= 0,
364 .fields
= (const VMStateField
[]) {
365 VMSTATE_IDE_BUS(bus
, MACIOIDEState
),
366 VMSTATE_IDE_DRIVES(bus
.ifs
, MACIOIDEState
),
367 VMSTATE_BOOL(dma_active
, MACIOIDEState
),
368 VMSTATE_UINT32(timing_reg
, MACIOIDEState
),
369 VMSTATE_UINT32(irq_reg
, MACIOIDEState
),
370 VMSTATE_END_OF_LIST()
374 static void macio_ide_reset(DeviceState
*dev
)
376 MACIOIDEState
*d
= MACIO_IDE(dev
);
378 ide_bus_reset(&d
->bus
);
381 static int ide_nop_int(const IDEDMA
*dma
, bool is_write
)
386 static int32_t ide_nop_int32(const IDEDMA
*dma
, int32_t l
)
391 static void ide_dbdma_start(const IDEDMA
*dma
, IDEState
*s
,
392 BlockCompletionFunc
*cb
)
394 MACIOIDEState
*m
= container_of(dma
, MACIOIDEState
, dma
);
396 s
->io_buffer_index
= 0;
397 if (s
->drive_kind
== IDE_CD
) {
398 s
->io_buffer_size
= s
->packet_transfer_size
;
400 s
->io_buffer_size
= s
->nsector
* BDRV_SECTOR_SIZE
;
403 MACIO_DPRINTF("\n\n------------ IDE transfer\n");
404 MACIO_DPRINTF("buffer_size: %x buffer_index: %x\n",
405 s
->io_buffer_size
, s
->io_buffer_index
);
406 MACIO_DPRINTF("lba: %x size: %x\n", s
->lba
, s
->io_buffer_size
);
407 MACIO_DPRINTF("-------------------------\n");
409 m
->dma_active
= true;
410 DBDMA_kick(m
->dbdma
);
413 static const IDEDMAOps dbdma_ops
= {
414 .start_dma
= ide_dbdma_start
,
415 .prepare_buf
= ide_nop_int32
,
416 .rw_buf
= ide_nop_int
,
419 static void macio_ide_realizefn(DeviceState
*dev
, Error
**errp
)
421 MACIOIDEState
*s
= MACIO_IDE(dev
);
423 ide_bus_init_output_irq(&s
->bus
, s
->ide_irq
);
425 /* Register DMA callbacks */
426 s
->dma
.ops
= &dbdma_ops
;
427 s
->bus
.dma
= &s
->dma
;
430 static void pmac_ide_irq(void *opaque
, int n
, int level
)
432 MACIOIDEState
*s
= opaque
;
433 uint32_t mask
= 0x80000000u
>> n
;
435 /* We need to reflect the IRQ state in the irq register */
443 qemu_set_irq(s
->real_ide_irq
, level
);
445 qemu_set_irq(s
->real_dma_irq
, level
);
449 static void macio_ide_initfn(Object
*obj
)
451 SysBusDevice
*d
= SYS_BUS_DEVICE(obj
);
452 MACIOIDEState
*s
= MACIO_IDE(obj
);
454 ide_bus_init(&s
->bus
, sizeof(s
->bus
), DEVICE(obj
), 0, 2);
455 memory_region_init_io(&s
->mem
, obj
, &pmac_ide_ops
, s
, "pmac-ide", 0x1000);
456 sysbus_init_mmio(d
, &s
->mem
);
457 sysbus_init_irq(d
, &s
->real_ide_irq
);
458 sysbus_init_irq(d
, &s
->real_dma_irq
);
459 s
->dma_irq
= qemu_allocate_irq(pmac_ide_irq
, s
, 0);
460 s
->ide_irq
= qemu_allocate_irq(pmac_ide_irq
, s
, 1);
462 object_property_add_link(obj
, "dbdma", TYPE_MAC_DBDMA
,
463 (Object
**) &s
->dbdma
,
464 qdev_prop_allow_set_link_before_realize
, 0);
467 static Property macio_ide_properties
[] = {
468 DEFINE_PROP_UINT32("channel", MACIOIDEState
, channel
, 0),
469 DEFINE_PROP_UINT32("addr", MACIOIDEState
, addr
, -1),
470 DEFINE_PROP_END_OF_LIST(),
473 static void macio_ide_class_init(ObjectClass
*oc
, void *data
)
475 DeviceClass
*dc
= DEVICE_CLASS(oc
);
477 dc
->realize
= macio_ide_realizefn
;
478 dc
->reset
= macio_ide_reset
;
479 device_class_set_props(dc
, macio_ide_properties
);
480 dc
->vmsd
= &vmstate_pmac
;
481 set_bit(DEVICE_CATEGORY_STORAGE
, dc
->categories
);
484 static const TypeInfo macio_ide_type_info
= {
485 .name
= TYPE_MACIO_IDE
,
486 .parent
= TYPE_SYS_BUS_DEVICE
,
487 .instance_size
= sizeof(MACIOIDEState
),
488 .instance_init
= macio_ide_initfn
,
489 .class_init
= macio_ide_class_init
,
492 static void macio_ide_register_types(void)
494 type_register_static(&macio_ide_type_info
);
497 /* hd_table must contain 2 block drivers */
498 void macio_ide_init_drives(MACIOIDEState
*s
, DriveInfo
**hd_table
)
502 for (i
= 0; i
< 2; i
++) {
504 ide_bus_create_drive(&s
->bus
, i
, hd_table
[i
]);
509 void macio_ide_register_dma(MACIOIDEState
*s
)
511 DBDMA_register_channel(s
->dbdma
, s
->channel
, s
->dma_irq
,
512 pmac_ide_transfer
, pmac_ide_flush
, s
);
515 type_init(macio_ide_register_types
)