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aspeed/smc: Wire CS lines at reset
[qemu/armbru.git] / hw / arm / aspeed.c
blobcd92cf9ce0bb770da104b1ec7235988427abb1c2
1 /*
2 * OpenPOWER Palmetto BMC
3 *
4 * Andrew Jeffery <andrew@aj.id.au>
5 *
6 * Copyright 2016 IBM Corp.
7 *
8 * This code is licensed under the GPL version 2 or later. See
9 * the COPYING file in the top-level directory.
10 */
11
12 #include "qemu/osdep.h"
13 #include "qapi/error.h"
14 #include "hw/arm/boot.h"
15 #include "hw/arm/aspeed.h"
16 #include "hw/arm/aspeed_soc.h"
17 #include "hw/arm/aspeed_eeprom.h"
18 #include "hw/i2c/i2c_mux_pca954x.h"
19 #include "hw/i2c/smbus_eeprom.h"
20 #include "hw/misc/pca9552.h"
21 #include "hw/nvram/eeprom_at24c.h"
22 #include "hw/sensor/tmp105.h"
23 #include "hw/misc/led.h"
24 #include "hw/qdev-properties.h"
25 #include "sysemu/block-backend.h"
26 #include "sysemu/reset.h"
27 #include "hw/loader.h"
28 #include "qemu/error-report.h"
29 #include "qemu/units.h"
30 #include "hw/qdev-clock.h"
31 #include "sysemu/sysemu.h"
32
33 static struct arm_boot_info aspeed_board_binfo = {
34 .board_id = -1, /* device-tree-only board */
35 };
36
37 struct AspeedMachineState {
38 /* Private */
39 MachineState parent_obj;
40 /* Public */
41
42 AspeedSoCState soc;
43 MemoryRegion boot_rom;
44 bool mmio_exec;
45 uint32_t uart_chosen;
46 char *fmc_model;
47 char *spi_model;
48 };
49
50 /* On 32-bit hosts, lower RAM to 1G because of the 2047 MB limit */
51 #if HOST_LONG_BITS == 32
52 #define ASPEED_RAM_SIZE(sz) MIN((sz), 1 * GiB)
53 #else
54 #define ASPEED_RAM_SIZE(sz) (sz)
55 #endif
56
57 /* Palmetto hardware value: 0x120CE416 */
58 #define PALMETTO_BMC_HW_STRAP1 ( \
59 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_256MB) | \
60 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2 /* DDR3 with CL=6, CWL=5 */) | \
61 SCU_AST2400_HW_STRAP_ACPI_DIS | \
62 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \
63 SCU_HW_STRAP_VGA_CLASS_CODE | \
64 SCU_HW_STRAP_LPC_RESET_PIN | \
65 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \
66 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
67 SCU_HW_STRAP_SPI_WIDTH | \
68 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
69 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
70
71 /* TODO: Find the actual hardware value */
72 #define SUPERMICROX11_BMC_HW_STRAP1 ( \
73 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \
74 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2) | \
75 SCU_AST2400_HW_STRAP_ACPI_DIS | \
76 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \
77 SCU_HW_STRAP_VGA_CLASS_CODE | \
78 SCU_HW_STRAP_LPC_RESET_PIN | \
79 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \
80 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
81 SCU_HW_STRAP_SPI_WIDTH | \
82 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
83 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
84
85 /* TODO: Find the actual hardware value */
86 #define SUPERMICRO_X11SPI_BMC_HW_STRAP1 ( \
87 AST2500_HW_STRAP1_DEFAULTS | \
88 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
89 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
90 SCU_AST2500_HW_STRAP_UART_DEBUG | \
91 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
92 SCU_HW_STRAP_SPI_WIDTH | \
93 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN))
94
95 /* AST2500 evb hardware value: 0xF100C2E6 */
96 #define AST2500_EVB_HW_STRAP1 (( \
97 AST2500_HW_STRAP1_DEFAULTS | \
98 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
99 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
100 SCU_AST2500_HW_STRAP_UART_DEBUG | \
101 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
102 SCU_HW_STRAP_MAC1_RGMII | \
103 SCU_HW_STRAP_MAC0_RGMII) & \
104 ~SCU_HW_STRAP_2ND_BOOT_WDT)
105
106 /* Romulus hardware value: 0xF10AD206 */
107 #define ROMULUS_BMC_HW_STRAP1 ( \
108 AST2500_HW_STRAP1_DEFAULTS | \
109 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
110 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
111 SCU_AST2500_HW_STRAP_UART_DEBUG | \
112 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
113 SCU_AST2500_HW_STRAP_ACPI_ENABLE | \
114 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER))
115
116 /* Sonorapass hardware value: 0xF100D216 */
117 #define SONORAPASS_BMC_HW_STRAP1 ( \
118 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
119 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
120 SCU_AST2500_HW_STRAP_UART_DEBUG | \
121 SCU_AST2500_HW_STRAP_RESERVED28 | \
122 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
123 SCU_HW_STRAP_VGA_CLASS_CODE | \
124 SCU_HW_STRAP_LPC_RESET_PIN | \
125 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \
126 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \
127 SCU_HW_STRAP_VGA_BIOS_ROM | \
128 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
129 SCU_AST2500_HW_STRAP_RESERVED1)
130
131 #define G220A_BMC_HW_STRAP1 ( \
132 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
133 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
134 SCU_AST2500_HW_STRAP_UART_DEBUG | \
135 SCU_AST2500_HW_STRAP_RESERVED28 | \
136 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
137 SCU_HW_STRAP_2ND_BOOT_WDT | \
138 SCU_HW_STRAP_VGA_CLASS_CODE | \
139 SCU_HW_STRAP_LPC_RESET_PIN | \
140 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \
141 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \
142 SCU_HW_STRAP_VGA_SIZE_SET(VGA_64M_DRAM) | \
143 SCU_AST2500_HW_STRAP_RESERVED1)
144
145 /* FP5280G2 hardware value: 0XF100D286 */
146 #define FP5280G2_BMC_HW_STRAP1 ( \
147 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
148 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
149 SCU_AST2500_HW_STRAP_UART_DEBUG | \
150 SCU_AST2500_HW_STRAP_RESERVED28 | \
151 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
152 SCU_HW_STRAP_VGA_CLASS_CODE | \
153 SCU_HW_STRAP_LPC_RESET_PIN | \
154 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \
155 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \
156 SCU_HW_STRAP_MAC1_RGMII | \
157 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
158 SCU_AST2500_HW_STRAP_RESERVED1)
159
160 /* Witherspoon hardware value: 0xF10AD216 (but use romulus definition) */
161 #define WITHERSPOON_BMC_HW_STRAP1 ROMULUS_BMC_HW_STRAP1
162
163 /* Quanta-Q71l hardware value */
164 #define QUANTA_Q71L_BMC_HW_STRAP1 ( \
165 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \
166 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2/* DDR3 with CL=6, CWL=5 */) | \
167 SCU_AST2400_HW_STRAP_ACPI_DIS | \
168 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_24M_IN) | \
169 SCU_HW_STRAP_VGA_CLASS_CODE | \
170 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_PASS_THROUGH) | \
171 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
172 SCU_HW_STRAP_SPI_WIDTH | \
173 SCU_HW_STRAP_VGA_SIZE_SET(VGA_8M_DRAM) | \
174 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
175
176 /* AST2600 evb hardware value */
177 #define AST2600_EVB_HW_STRAP1 0x000000C0
178 #define AST2600_EVB_HW_STRAP2 0x00000003
179
180 /* Tacoma hardware value */
181 #define TACOMA_BMC_HW_STRAP1 0x00000000
182 #define TACOMA_BMC_HW_STRAP2 0x00000040
183
184 /* Rainier hardware value: (QEMU prototype) */
185 #define RAINIER_BMC_HW_STRAP1 0x00422016
186 #define RAINIER_BMC_HW_STRAP2 0x80000848
187
188 /* Fuji hardware value */
189 #define FUJI_BMC_HW_STRAP1 0x00000000
190 #define FUJI_BMC_HW_STRAP2 0x00000000
191
192 /* Bletchley hardware value */
193 /* TODO: Leave same as EVB for now. */
194 #define BLETCHLEY_BMC_HW_STRAP1 AST2600_EVB_HW_STRAP1
195 #define BLETCHLEY_BMC_HW_STRAP2 AST2600_EVB_HW_STRAP2
196
197 /* Qualcomm DC-SCM hardware value */
198 #define QCOM_DC_SCM_V1_BMC_HW_STRAP1 0x00000000
199 #define QCOM_DC_SCM_V1_BMC_HW_STRAP2 0x00000041
200
201 #define AST_SMP_MAILBOX_BASE 0x1e6e2180
202 #define AST_SMP_MBOX_FIELD_ENTRY (AST_SMP_MAILBOX_BASE + 0x0)
203 #define AST_SMP_MBOX_FIELD_GOSIGN (AST_SMP_MAILBOX_BASE + 0x4)
204 #define AST_SMP_MBOX_FIELD_READY (AST_SMP_MAILBOX_BASE + 0x8)
205 #define AST_SMP_MBOX_FIELD_POLLINSN (AST_SMP_MAILBOX_BASE + 0xc)
206 #define AST_SMP_MBOX_CODE (AST_SMP_MAILBOX_BASE + 0x10)
207 #define AST_SMP_MBOX_GOSIGN 0xabbaab00
208
209 static void aspeed_write_smpboot(ARMCPU *cpu,
210 const struct arm_boot_info *info)
211 {
212 AddressSpace *as = arm_boot_address_space(cpu, info);
213 static const ARMInsnFixup poll_mailbox_ready[] = {
214 /*
215 * r2 = per-cpu go sign value
216 * r1 = AST_SMP_MBOX_FIELD_ENTRY
217 * r0 = AST_SMP_MBOX_FIELD_GOSIGN
218 */
219 { 0xee100fb0 }, /* mrc p15, 0, r0, c0, c0, 5 */
220 { 0xe21000ff }, /* ands r0, r0, #255 */
221 { 0xe59f201c }, /* ldr r2, [pc, #28] */
222 { 0xe1822000 }, /* orr r2, r2, r0 */
223
224 { 0xe59f1018 }, /* ldr r1, [pc, #24] */
225 { 0xe59f0018 }, /* ldr r0, [pc, #24] */
226
227 { 0xe320f002 }, /* wfe */
228 { 0xe5904000 }, /* ldr r4, [r0] */
229 { 0xe1520004 }, /* cmp r2, r4 */
230 { 0x1afffffb }, /* bne <wfe> */
231 { 0xe591f000 }, /* ldr pc, [r1] */
232 { AST_SMP_MBOX_GOSIGN },
233 { AST_SMP_MBOX_FIELD_ENTRY },
234 { AST_SMP_MBOX_FIELD_GOSIGN },
235 { 0, FIXUP_TERMINATOR }
236 };
237 static const uint32_t fixupcontext[FIXUP_MAX] = { 0 };
238
239 arm_write_bootloader("aspeed.smpboot", as, info->smp_loader_start,
240 poll_mailbox_ready, fixupcontext);
241 }
242
243 static void aspeed_reset_secondary(ARMCPU *cpu,
244 const struct arm_boot_info *info)
245 {
246 AddressSpace *as = arm_boot_address_space(cpu, info);
247 CPUState *cs = CPU(cpu);
248
249 /* info->smp_bootreg_addr */
250 address_space_stl_notdirty(as, AST_SMP_MBOX_FIELD_GOSIGN, 0,
251 MEMTXATTRS_UNSPECIFIED, NULL);
252 cpu_set_pc(cs, info->smp_loader_start);
253 }
254
255 static void write_boot_rom(BlockBackend *blk, hwaddr addr, size_t rom_size,
256 Error **errp)
257 {
258 g_autofree void *storage = NULL;
259 int64_t size;
260
261 /* The block backend size should have already been 'validated' by
262 * the creation of the m25p80 object.
263 */
264 size = blk_getlength(blk);
265 if (size <= 0) {
266 error_setg(errp, "failed to get flash size");
267 return;
268 }
269
270 if (rom_size > size) {
271 rom_size = size;
272 }
273
274 storage = g_malloc0(rom_size);
275 if (blk_pread(blk, 0, rom_size, storage, 0) < 0) {
276 error_setg(errp, "failed to read the initial flash content");
277 return;
278 }
279
280 rom_add_blob_fixed("aspeed.boot_rom", storage, rom_size, addr);
281 }
282
283 /*
284 * Create a ROM and copy the flash contents at the expected address
285 * (0x0). Boots faster than execute-in-place.
286 */
287 static void aspeed_install_boot_rom(AspeedMachineState *bmc, BlockBackend *blk,
288 uint64_t rom_size)
289 {
290 AspeedSoCState *soc = &bmc->soc;
291
292 memory_region_init_rom(&bmc->boot_rom, NULL, "aspeed.boot_rom", rom_size,
293 &error_abort);
294 memory_region_add_subregion_overlap(&soc->spi_boot_container, 0,
295 &bmc->boot_rom, 1);
296 write_boot_rom(blk, ASPEED_SOC_SPI_BOOT_ADDR, rom_size, &error_abort);
297 }
298
299 void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype,
300 unsigned int count, int unit0)
301 {
302 int i;
303
304 if (!flashtype) {
305 return;
306 }
307
308 for (i = 0; i < count; ++i) {
309 DriveInfo *dinfo = drive_get(IF_MTD, 0, unit0 + i);
310 DeviceState *dev;
311
312 dev = qdev_new(flashtype);
313 if (dinfo) {
314 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo));
315 }
316 qdev_prop_set_uint8(dev, "cs", i);
317 qdev_realize_and_unref(dev, BUS(s->spi), &error_fatal);
318 }
319 }
320
321 static void sdhci_attach_drive(SDHCIState *sdhci, DriveInfo *dinfo)
322 {
323 DeviceState *card;
324
325 if (!dinfo) {
326 return;
327 }
328 card = qdev_new(TYPE_SD_CARD);
329 qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo),
330 &error_fatal);
331 qdev_realize_and_unref(card,
332 qdev_get_child_bus(DEVICE(sdhci), "sd-bus"),
333 &error_fatal);
334 }
335
336 static void connect_serial_hds_to_uarts(AspeedMachineState *bmc)
337 {
338 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc);
339 AspeedSoCState *s = &bmc->soc;
340 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
341 int uart_chosen = bmc->uart_chosen ? bmc->uart_chosen : amc->uart_default;
342
343 aspeed_soc_uart_set_chr(s, uart_chosen, serial_hd(0));
344 for (int i = 1, uart = ASPEED_DEV_UART1; i < sc->uarts_num; i++, uart++) {
345 if (uart == uart_chosen) {
346 continue;
347 }
348 aspeed_soc_uart_set_chr(s, uart, serial_hd(i));
349 }
350 }
351
352 static void aspeed_machine_init(MachineState *machine)
353 {
354 AspeedMachineState *bmc = ASPEED_MACHINE(machine);
355 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine);
356 AspeedSoCClass *sc;
357 int i;
358 NICInfo *nd = &nd_table[0];
359
360 object_initialize_child(OBJECT(machine), "soc", &bmc->soc, amc->soc_name);
361
362 sc = ASPEED_SOC_GET_CLASS(&bmc->soc);
363
364 /*
365 * This will error out if the RAM size is not supported by the
366 * memory controller of the SoC.
367 */
368 object_property_set_uint(OBJECT(&bmc->soc), "ram-size", machine->ram_size,
369 &error_fatal);
370
371 for (i = 0; i < sc->macs_num; i++) {
372 if ((amc->macs_mask & (1 << i)) && nd->used) {
373 qemu_check_nic_model(nd, TYPE_FTGMAC100);
374 qdev_set_nic_properties(DEVICE(&bmc->soc.ftgmac100[i]), nd);
375 nd++;
376 }
377 }
378
379 object_property_set_int(OBJECT(&bmc->soc), "hw-strap1", amc->hw_strap1,
380 &error_abort);
381 object_property_set_int(OBJECT(&bmc->soc), "hw-strap2", amc->hw_strap2,
382 &error_abort);
383 object_property_set_link(OBJECT(&bmc->soc), "memory",
384 OBJECT(get_system_memory()), &error_abort);
385 object_property_set_link(OBJECT(&bmc->soc), "dram",
386 OBJECT(machine->ram), &error_abort);
387 if (machine->kernel_filename) {
388 /*
389 * When booting with a -kernel command line there is no u-boot
390 * that runs to unlock the SCU. In this case set the default to
391 * be unlocked as the kernel expects
392 */
393 object_property_set_int(OBJECT(&bmc->soc), "hw-prot-key",
394 ASPEED_SCU_PROT_KEY, &error_abort);
395 }
396 connect_serial_hds_to_uarts(bmc);
397 qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort);
398
399 aspeed_board_init_flashes(&bmc->soc.fmc,
400 bmc->fmc_model ? bmc->fmc_model : amc->fmc_model,
401 amc->num_cs, 0);
402 aspeed_board_init_flashes(&bmc->soc.spi[0],
403 bmc->spi_model ? bmc->spi_model : amc->spi_model,
404 1, amc->num_cs);
405
406 if (machine->kernel_filename && sc->num_cpus > 1) {
407 /* With no u-boot we must set up a boot stub for the secondary CPU */
408 MemoryRegion *smpboot = g_new(MemoryRegion, 1);
409 memory_region_init_ram(smpboot, NULL, "aspeed.smpboot",
410 0x80, &error_abort);
411 memory_region_add_subregion(get_system_memory(),
412 AST_SMP_MAILBOX_BASE, smpboot);
413
414 aspeed_board_binfo.write_secondary_boot = aspeed_write_smpboot;
415 aspeed_board_binfo.secondary_cpu_reset_hook = aspeed_reset_secondary;
416 aspeed_board_binfo.smp_loader_start = AST_SMP_MBOX_CODE;
417 }
418
419 aspeed_board_binfo.ram_size = machine->ram_size;
420 aspeed_board_binfo.loader_start = sc->memmap[ASPEED_DEV_SDRAM];
421
422 if (amc->i2c_init) {
423 amc->i2c_init(bmc);
424 }
425
426 for (i = 0; i < bmc->soc.sdhci.num_slots; i++) {
427 sdhci_attach_drive(&bmc->soc.sdhci.slots[i],
428 drive_get(IF_SD, 0, i));
429 }
430
431 if (bmc->soc.emmc.num_slots) {
432 sdhci_attach_drive(&bmc->soc.emmc.slots[0],
433 drive_get(IF_SD, 0, bmc->soc.sdhci.num_slots));
434 }
435
436 if (!bmc->mmio_exec) {
437 DriveInfo *mtd0 = drive_get(IF_MTD, 0, 0);
438
439 if (mtd0) {
440 uint64_t rom_size = memory_region_size(&bmc->soc.spi_boot);
441 aspeed_install_boot_rom(bmc, blk_by_legacy_dinfo(mtd0), rom_size);
442 }
443 }
444
445 arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo);
446 }
447
448 static void palmetto_bmc_i2c_init(AspeedMachineState *bmc)
449 {
450 AspeedSoCState *soc = &bmc->soc;
451 DeviceState *dev;
452 uint8_t *eeprom_buf = g_malloc0(32 * 1024);
453
454 /* The palmetto platform expects a ds3231 RTC but a ds1338 is
455 * enough to provide basic RTC features. Alarms will be missing */
456 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 0), "ds1338", 0x68);
457
458 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50,
459 eeprom_buf);
460
461 /* add a TMP423 temperature sensor */
462 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2),
463 "tmp423", 0x4c));
464 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
465 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
466 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
467 object_property_set_int(OBJECT(dev), "temperature3", 110000, &error_abort);
468 }
469
470 static void quanta_q71l_bmc_i2c_init(AspeedMachineState *bmc)
471 {
472 AspeedSoCState *soc = &bmc->soc;
473
474 /*
475 * The quanta-q71l platform expects tmp75s which are compatible with
476 * tmp105s.
477 */
478 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4c);
479 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4e);
480 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4f);
481
482 /* TODO: i2c-1: Add baseboard FRU eeprom@54 24c64 */
483 /* TODO: i2c-1: Add Frontpanel FRU eeprom@57 24c64 */
484 /* TODO: Add Memory Riser i2c mux and eeproms. */
485
486 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9546", 0x74);
487 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9548", 0x77);
488
489 /* TODO: i2c-3: Add BIOS FRU eeprom@56 24c64 */
490
491 /* i2c-7 */
492 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9546", 0x70);
493 /* - i2c@0: pmbus@59 */
494 /* - i2c@1: pmbus@58 */
495 /* - i2c@2: pmbus@58 */
496 /* - i2c@3: pmbus@59 */
497
498 /* TODO: i2c-7: Add PDB FRU eeprom@52 */
499 /* TODO: i2c-8: Add BMC FRU eeprom@50 */
500 }
501
502 static void ast2500_evb_i2c_init(AspeedMachineState *bmc)
503 {
504 AspeedSoCState *soc = &bmc->soc;
505 uint8_t *eeprom_buf = g_malloc0(8 * 1024);
506
507 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 3), 0x50,
508 eeprom_buf);
509
510 /* The AST2500 EVB expects a LM75 but a TMP105 is compatible */
511 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7),
512 TYPE_TMP105, 0x4d);
513 }
514
515 static void ast2600_evb_i2c_init(AspeedMachineState *bmc)
516 {
517 AspeedSoCState *soc = &bmc->soc;
518 uint8_t *eeprom_buf = g_malloc0(8 * 1024);
519
520 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50,
521 eeprom_buf);
522
523 /* LM75 is compatible with TMP105 driver */
524 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8),
525 TYPE_TMP105, 0x4d);
526 }
527
528 static void yosemitev2_bmc_i2c_init(AspeedMachineState *bmc)
529 {
530 AspeedSoCState *soc = &bmc->soc;
531
532 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 4), 0x51, 128 * KiB);
533 at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 128 * KiB,
534 yosemitev2_bmc_fruid, yosemitev2_bmc_fruid_len);
535 /* TMP421 */
536 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "tmp421", 0x1f);
537 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp421", 0x4e);
538 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp421", 0x4f);
539
540 }
541
542 static void romulus_bmc_i2c_init(AspeedMachineState *bmc)
543 {
544 AspeedSoCState *soc = &bmc->soc;
545
546 /* The romulus board expects Epson RX8900 I2C RTC but a ds1338 is
547 * good enough */
548 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32);
549 }
550
551 static void tiogapass_bmc_i2c_init(AspeedMachineState *bmc)
552 {
553 AspeedSoCState *soc = &bmc->soc;
554
555 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54, 128 * KiB);
556 at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 6), 0x54, 128 * KiB,
557 tiogapass_bmc_fruid, tiogapass_bmc_fruid_len);
558 /* TMP421 */
559 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "tmp421", 0x1f);
560 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp421", 0x4f);
561 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp421", 0x4e);
562 }
563
564 static void create_pca9552(AspeedSoCState *soc, int bus_id, int addr)
565 {
566 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, bus_id),
567 TYPE_PCA9552, addr);
568 }
569
570 static void sonorapass_bmc_i2c_init(AspeedMachineState *bmc)
571 {
572 AspeedSoCState *soc = &bmc->soc;
573
574 /* bus 2 : */
575 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x48);
576 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x49);
577 /* bus 2 : pca9546 @ 0x73 */
578
579 /* bus 3 : pca9548 @ 0x70 */
580
581 /* bus 4 : */
582 uint8_t *eeprom4_54 = g_malloc0(8 * 1024);
583 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54,
584 eeprom4_54);
585 /* PCA9539 @ 0x76, but PCA9552 is compatible */
586 create_pca9552(soc, 4, 0x76);
587 /* PCA9539 @ 0x77, but PCA9552 is compatible */
588 create_pca9552(soc, 4, 0x77);
589
590 /* bus 6 : */
591 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x48);
592 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x49);
593 /* bus 6 : pca9546 @ 0x73 */
594
595 /* bus 8 : */
596 uint8_t *eeprom8_56 = g_malloc0(8 * 1024);
597 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 8), 0x56,
598 eeprom8_56);
599 create_pca9552(soc, 8, 0x60);
600 create_pca9552(soc, 8, 0x61);
601 /* bus 8 : adc128d818 @ 0x1d */
602 /* bus 8 : adc128d818 @ 0x1f */
603
604 /*
605 * bus 13 : pca9548 @ 0x71
606 * - channel 3:
607 * - tmm421 @ 0x4c
608 * - tmp421 @ 0x4e
609 * - tmp421 @ 0x4f
610 */
611
612 }
613
614 static void witherspoon_bmc_i2c_init(AspeedMachineState *bmc)
615 {
616 static const struct {
617 unsigned gpio_id;
618 LEDColor color;
619 const char *description;
620 bool gpio_polarity;
621 } pca1_leds[] = {
622 {13, LED_COLOR_GREEN, "front-fault-4", GPIO_POLARITY_ACTIVE_LOW},
623 {14, LED_COLOR_GREEN, "front-power-3", GPIO_POLARITY_ACTIVE_LOW},
624 {15, LED_COLOR_GREEN, "front-id-5", GPIO_POLARITY_ACTIVE_LOW},
625 };
626 AspeedSoCState *soc = &bmc->soc;
627 uint8_t *eeprom_buf = g_malloc0(8 * 1024);
628 DeviceState *dev;
629 LEDState *led;
630
631 /* Bus 3: TODO bmp280@77 */
632 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60));
633 qdev_prop_set_string(dev, "description", "pca1");
634 i2c_slave_realize_and_unref(I2C_SLAVE(dev),
635 aspeed_i2c_get_bus(&soc->i2c, 3),
636 &error_fatal);
637
638 for (size_t i = 0; i < ARRAY_SIZE(pca1_leds); i++) {
639 led = led_create_simple(OBJECT(bmc),
640 pca1_leds[i].gpio_polarity,
641 pca1_leds[i].color,
642 pca1_leds[i].description);
643 qdev_connect_gpio_out(dev, pca1_leds[i].gpio_id,
644 qdev_get_gpio_in(DEVICE(led), 0));
645 }
646 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "dps310", 0x76);
647 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "max31785", 0x52);
648 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "tmp423", 0x4c);
649 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), "tmp423", 0x4c);
650
651 /* The Witherspoon expects a TMP275 but a TMP105 is compatible */
652 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), TYPE_TMP105,
653 0x4a);
654
655 /* The witherspoon board expects Epson RX8900 I2C RTC but a ds1338 is
656 * good enough */
657 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32);
658
659 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 11), 0x51,
660 eeprom_buf);
661 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60));
662 qdev_prop_set_string(dev, "description", "pca0");
663 i2c_slave_realize_and_unref(I2C_SLAVE(dev),
664 aspeed_i2c_get_bus(&soc->i2c, 11),
665 &error_fatal);
666 /* Bus 11: TODO ucd90160@64 */
667 }
668
669 static void g220a_bmc_i2c_init(AspeedMachineState *bmc)
670 {
671 AspeedSoCState *soc = &bmc->soc;
672 DeviceState *dev;
673
674 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3),
675 "emc1413", 0x4c));
676 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
677 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
678 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
679
680 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12),
681 "emc1413", 0x4c));
682 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
683 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
684 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
685
686 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 13),
687 "emc1413", 0x4c));
688 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
689 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
690 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
691
692 static uint8_t eeprom_buf[2 * 1024] = {
693 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0xfe,
694 0x01, 0x06, 0x00, 0xc9, 0x42, 0x79, 0x74, 0x65,
695 0x64, 0x61, 0x6e, 0x63, 0x65, 0xc5, 0x47, 0x32,
696 0x32, 0x30, 0x41, 0xc4, 0x41, 0x41, 0x42, 0x42,
697 0xc4, 0x43, 0x43, 0x44, 0x44, 0xc4, 0x45, 0x45,
698 0x46, 0x46, 0xc4, 0x48, 0x48, 0x47, 0x47, 0xc1,
699 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa7,
700 };
701 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x57,
702 eeprom_buf);
703 }
704
705 static void fp5280g2_bmc_i2c_init(AspeedMachineState *bmc)
706 {
707 AspeedSoCState *soc = &bmc->soc;
708 I2CSlave *i2c_mux;
709
710 /* The at24c256 */
711 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 1), 0x50, 32768);
712
713 /* The fp5280g2 expects a TMP112 but a TMP105 is compatible */
714 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), TYPE_TMP105,
715 0x48);
716 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), TYPE_TMP105,
717 0x49);
718
719 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2),
720 "pca9546", 0x70);
721 /* It expects a TMP112 but a TMP105 is compatible */
722 i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 0), TYPE_TMP105,
723 0x4a);
724
725 /* It expects a ds3232 but a ds1338 is good enough */
726 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "ds1338", 0x68);
727
728 /* It expects a pca9555 but a pca9552 is compatible */
729 create_pca9552(soc, 8, 0x30);
730 }
731
732 static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
733 {
734 AspeedSoCState *soc = &bmc->soc;
735 I2CSlave *i2c_mux;
736
737 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 0), 0x51, 32 * KiB);
738
739 create_pca9552(soc, 3, 0x61);
740
741 /* The rainier expects a TMP275 but a TMP105 is compatible */
742 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105,
743 0x48);
744 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105,
745 0x49);
746 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105,
747 0x4a);
748 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4),
749 "pca9546", 0x70);
750 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
751 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
752 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x52, 64 * KiB);
753 create_pca9552(soc, 4, 0x60);
754
755 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105,
756 0x48);
757 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105,
758 0x49);
759 create_pca9552(soc, 5, 0x60);
760 create_pca9552(soc, 5, 0x61);
761 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5),
762 "pca9546", 0x70);
763 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
764 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
765
766 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105,
767 0x48);
768 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105,
769 0x4a);
770 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105,
771 0x4b);
772 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6),
773 "pca9546", 0x70);
774 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
775 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
776 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x50, 64 * KiB);
777 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 3), 0x51, 64 * KiB);
778
779 create_pca9552(soc, 7, 0x30);
780 create_pca9552(soc, 7, 0x31);
781 create_pca9552(soc, 7, 0x32);
782 create_pca9552(soc, 7, 0x33);
783 create_pca9552(soc, 7, 0x60);
784 create_pca9552(soc, 7, 0x61);
785 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "dps310", 0x76);
786 /* Bus 7: TODO si7021-a20@20 */
787 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), TYPE_TMP105,
788 0x48);
789 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "max31785", 0x52);
790 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50, 64 * KiB);
791 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x51, 64 * KiB);
792
793 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105,
794 0x48);
795 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105,
796 0x4a);
797 at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x50,
798 64 * KiB, rainier_bb_fruid, rainier_bb_fruid_len);
799 at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51,
800 64 * KiB, rainier_bmc_fruid, rainier_bmc_fruid_len);
801 create_pca9552(soc, 8, 0x60);
802 create_pca9552(soc, 8, 0x61);
803 /* Bus 8: ucd90320@11 */
804 /* Bus 8: ucd90320@b */
805 /* Bus 8: ucd90320@c */
806
807 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4c);
808 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4d);
809 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 9), 0x50, 128 * KiB);
810
811 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4c);
812 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4d);
813 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 10), 0x50, 128 * KiB);
814
815 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105,
816 0x48);
817 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105,
818 0x49);
819 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11),
820 "pca9546", 0x70);
821 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
822 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
823 create_pca9552(soc, 11, 0x60);
824
825
826 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 13), 0x50, 64 * KiB);
827 create_pca9552(soc, 13, 0x60);
828
829 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 14), 0x50, 64 * KiB);
830 create_pca9552(soc, 14, 0x60);
831
832 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 15), 0x50, 64 * KiB);
833 create_pca9552(soc, 15, 0x60);
834 }
835
836 static void get_pca9548_channels(I2CBus *bus, uint8_t mux_addr,
837 I2CBus **channels)
838 {
839 I2CSlave *mux = i2c_slave_create_simple(bus, "pca9548", mux_addr);
840 for (int i = 0; i < 8; i++) {
841 channels[i] = pca954x_i2c_get_bus(mux, i);
842 }
843 }
844
845 #define TYPE_LM75 TYPE_TMP105
846 #define TYPE_TMP75 TYPE_TMP105
847 #define TYPE_TMP422 "tmp422"
848
849 static void fuji_bmc_i2c_init(AspeedMachineState *bmc)
850 {
851 AspeedSoCState *soc = &bmc->soc;
852 I2CBus *i2c[144] = {};
853
854 for (int i = 0; i < 16; i++) {
855 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i);
856 }
857 I2CBus *i2c180 = i2c[2];
858 I2CBus *i2c480 = i2c[8];
859 I2CBus *i2c600 = i2c[11];
860
861 get_pca9548_channels(i2c180, 0x70, &i2c[16]);
862 get_pca9548_channels(i2c480, 0x70, &i2c[24]);
863 /* NOTE: The device tree skips [32, 40) in the alias numbering */
864 get_pca9548_channels(i2c600, 0x77, &i2c[40]);
865 get_pca9548_channels(i2c[24], 0x71, &i2c[48]);
866 get_pca9548_channels(i2c[25], 0x72, &i2c[56]);
867 get_pca9548_channels(i2c[26], 0x76, &i2c[64]);
868 get_pca9548_channels(i2c[27], 0x76, &i2c[72]);
869 for (int i = 0; i < 8; i++) {
870 get_pca9548_channels(i2c[40 + i], 0x76, &i2c[80 + i * 8]);
871 }
872
873 i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4c);
874 i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4d);
875
876 /*
877 * EEPROM 24c64 size is 64Kbits or 8 Kbytes
878 * 24c02 size is 2Kbits or 256 bytes
879 */
880 at24c_eeprom_init(i2c[19], 0x52, 8 * KiB);
881 at24c_eeprom_init(i2c[20], 0x50, 256);
882 at24c_eeprom_init(i2c[22], 0x52, 256);
883
884 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x48);
885 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x49);
886 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x4a);
887 i2c_slave_create_simple(i2c[3], TYPE_TMP422, 0x4c);
888
889 at24c_eeprom_init(i2c[8], 0x51, 8 * KiB);
890 i2c_slave_create_simple(i2c[8], TYPE_LM75, 0x4a);
891
892 i2c_slave_create_simple(i2c[50], TYPE_LM75, 0x4c);
893 at24c_eeprom_init(i2c[50], 0x52, 8 * KiB);
894 i2c_slave_create_simple(i2c[51], TYPE_TMP75, 0x48);
895 i2c_slave_create_simple(i2c[52], TYPE_TMP75, 0x49);
896
897 i2c_slave_create_simple(i2c[59], TYPE_TMP75, 0x48);
898 i2c_slave_create_simple(i2c[60], TYPE_TMP75, 0x49);
899
900 at24c_eeprom_init(i2c[65], 0x53, 8 * KiB);
901 i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x49);
902 i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x48);
903 at24c_eeprom_init(i2c[68], 0x52, 8 * KiB);
904 at24c_eeprom_init(i2c[69], 0x52, 8 * KiB);
905 at24c_eeprom_init(i2c[70], 0x52, 8 * KiB);
906 at24c_eeprom_init(i2c[71], 0x52, 8 * KiB);
907
908 at24c_eeprom_init(i2c[73], 0x53, 8 * KiB);
909 i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x49);
910 i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x48);
911 at24c_eeprom_init(i2c[76], 0x52, 8 * KiB);
912 at24c_eeprom_init(i2c[77], 0x52, 8 * KiB);
913 at24c_eeprom_init(i2c[78], 0x52, 8 * KiB);
914 at24c_eeprom_init(i2c[79], 0x52, 8 * KiB);
915 at24c_eeprom_init(i2c[28], 0x50, 256);
916
917 for (int i = 0; i < 8; i++) {
918 at24c_eeprom_init(i2c[81 + i * 8], 0x56, 64 * KiB);
919 i2c_slave_create_simple(i2c[82 + i * 8], TYPE_TMP75, 0x48);
920 i2c_slave_create_simple(i2c[83 + i * 8], TYPE_TMP75, 0x4b);
921 i2c_slave_create_simple(i2c[84 + i * 8], TYPE_TMP75, 0x4a);
922 }
923 }
924
925 #define TYPE_TMP421 "tmp421"
926
927 static void bletchley_bmc_i2c_init(AspeedMachineState *bmc)
928 {
929 AspeedSoCState *soc = &bmc->soc;
930 I2CBus *i2c[13] = {};
931 for (int i = 0; i < 13; i++) {
932 if ((i == 8) || (i == 11)) {
933 continue;
934 }
935 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i);
936 }
937
938 /* Bus 0 - 5 all have the same config. */
939 for (int i = 0; i < 6; i++) {
940 /* Missing model: ti,ina230 @ 0x45 */
941 /* Missing model: mps,mp5023 @ 0x40 */
942 i2c_slave_create_simple(i2c[i], TYPE_TMP421, 0x4f);
943 /* Missing model: nxp,pca9539 @ 0x76, but PCA9552 works enough */
944 i2c_slave_create_simple(i2c[i], TYPE_PCA9552, 0x76);
945 i2c_slave_create_simple(i2c[i], TYPE_PCA9552, 0x67);
946 /* Missing model: fsc,fusb302 @ 0x22 */
947 }
948
949 /* Bus 6 */
950 at24c_eeprom_init(i2c[6], 0x56, 65536);
951 /* Missing model: nxp,pcf85263 @ 0x51 , but ds1338 works enough */
952 i2c_slave_create_simple(i2c[6], "ds1338", 0x51);
953
954
955 /* Bus 7 */
956 at24c_eeprom_init(i2c[7], 0x54, 65536);
957
958 /* Bus 9 */
959 i2c_slave_create_simple(i2c[9], TYPE_TMP421, 0x4f);
960
961 /* Bus 10 */
962 i2c_slave_create_simple(i2c[10], TYPE_TMP421, 0x4f);
963 /* Missing model: ti,hdc1080 @ 0x40 */
964 i2c_slave_create_simple(i2c[10], TYPE_PCA9552, 0x67);
965
966 /* Bus 12 */
967 /* Missing model: adi,adm1278 @ 0x11 */
968 i2c_slave_create_simple(i2c[12], TYPE_TMP421, 0x4c);
969 i2c_slave_create_simple(i2c[12], TYPE_TMP421, 0x4d);
970 i2c_slave_create_simple(i2c[12], TYPE_PCA9552, 0x67);
971 }
972
973 static void fby35_i2c_init(AspeedMachineState *bmc)
974 {
975 AspeedSoCState *soc = &bmc->soc;
976 I2CBus *i2c[16];
977
978 for (int i = 0; i < 16; i++) {
979 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i);
980 }
981
982 i2c_slave_create_simple(i2c[2], TYPE_LM75, 0x4f);
983 i2c_slave_create_simple(i2c[8], TYPE_TMP421, 0x1f);
984 /* Hotswap controller is actually supposed to be mp5920 or ltc4282. */
985 i2c_slave_create_simple(i2c[11], "adm1272", 0x44);
986 i2c_slave_create_simple(i2c[12], TYPE_LM75, 0x4e);
987 i2c_slave_create_simple(i2c[12], TYPE_LM75, 0x4f);
988
989 at24c_eeprom_init(i2c[4], 0x51, 128 * KiB);
990 at24c_eeprom_init(i2c[6], 0x51, 128 * KiB);
991 at24c_eeprom_init_rom(i2c[8], 0x50, 32 * KiB, fby35_nic_fruid,
992 fby35_nic_fruid_len);
993 at24c_eeprom_init_rom(i2c[11], 0x51, 128 * KiB, fby35_bb_fruid,
994 fby35_bb_fruid_len);
995 at24c_eeprom_init_rom(i2c[11], 0x54, 128 * KiB, fby35_bmc_fruid,
996 fby35_bmc_fruid_len);
997
998 /*
999 * TODO: There is a multi-master i2c connection to an AST1030 MiniBMC on
1000 * buses 0, 1, 2, 3, and 9. Source address 0x10, target address 0x20 on
1001 * each.
1002 */
1003 }
1004
1005 static void qcom_dc_scm_bmc_i2c_init(AspeedMachineState *bmc)
1006 {
1007 AspeedSoCState *soc = &bmc->soc;
1008
1009 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 15), "tmp105", 0x4d);
1010 }
1011
1012 static void qcom_dc_scm_firework_i2c_init(AspeedMachineState *bmc)
1013 {
1014 AspeedSoCState *soc = &bmc->soc;
1015 I2CSlave *therm_mux, *cpuvr_mux;
1016
1017 /* Create the generic DC-SCM hardware */
1018 qcom_dc_scm_bmc_i2c_init(bmc);
1019
1020 /* Now create the Firework specific hardware */
1021
1022 /* I2C7 CPUVR MUX */
1023 cpuvr_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7),
1024 "pca9546", 0x70);
1025 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 0), "pca9548", 0x72);
1026 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 1), "pca9548", 0x72);
1027 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 2), "pca9548", 0x72);
1028 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 3), "pca9548", 0x72);
1029
1030 /* I2C8 Thermal Diodes*/
1031 therm_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8),
1032 "pca9548", 0x70);
1033 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 0), TYPE_LM75, 0x4C);
1034 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 1), TYPE_LM75, 0x4C);
1035 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 2), TYPE_LM75, 0x48);
1036 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 3), TYPE_LM75, 0x48);
1037 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 4), TYPE_LM75, 0x48);
1038
1039 /* I2C9 Fan Controller (MAX31785) */
1040 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "max31785", 0x52);
1041 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "max31785", 0x54);
1042 }
1043
1044 static bool aspeed_get_mmio_exec(Object *obj, Error **errp)
1045 {
1046 return ASPEED_MACHINE(obj)->mmio_exec;
1047 }
1048
1049 static void aspeed_set_mmio_exec(Object *obj, bool value, Error **errp)
1050 {
1051 ASPEED_MACHINE(obj)->mmio_exec = value;
1052 }
1053
1054 static void aspeed_machine_instance_init(Object *obj)
1055 {
1056 ASPEED_MACHINE(obj)->mmio_exec = false;
1057 }
1058
1059 static char *aspeed_get_fmc_model(Object *obj, Error **errp)
1060 {
1061 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1062 return g_strdup(bmc->fmc_model);
1063 }
1064
1065 static void aspeed_set_fmc_model(Object *obj, const char *value, Error **errp)
1066 {
1067 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1068
1069 g_free(bmc->fmc_model);
1070 bmc->fmc_model = g_strdup(value);
1071 }
1072
1073 static char *aspeed_get_spi_model(Object *obj, Error **errp)
1074 {
1075 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1076 return g_strdup(bmc->spi_model);
1077 }
1078
1079 static void aspeed_set_spi_model(Object *obj, const char *value, Error **errp)
1080 {
1081 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1082
1083 g_free(bmc->spi_model);
1084 bmc->spi_model = g_strdup(value);
1085 }
1086
1087 static char *aspeed_get_bmc_console(Object *obj, Error **errp)
1088 {
1089 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1090 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc);
1091 int uart_chosen = bmc->uart_chosen ? bmc->uart_chosen : amc->uart_default;
1092
1093 return g_strdup_printf("uart%d", uart_chosen - ASPEED_DEV_UART1 + 1);
1094 }
1095
1096 static void aspeed_set_bmc_console(Object *obj, const char *value, Error **errp)
1097 {
1098 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1099 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc);
1100 AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(amc->soc_name));
1101 int val;
1102
1103 if (sscanf(value, "uart%u", &val) != 1) {
1104 error_setg(errp, "Bad value for \"uart\" property");
1105 return;
1106 }
1107
1108 /* The number of UART depends on the SoC */
1109 if (val < 1 || val > sc->uarts_num) {
1110 error_setg(errp, "\"uart\" should be in range [1 - %d]", sc->uarts_num);
1111 return;
1112 }
1113 bmc->uart_chosen = ASPEED_DEV_UART1 + val - 1;
1114 }
1115
1116 static void aspeed_machine_class_props_init(ObjectClass *oc)
1117 {
1118 object_class_property_add_bool(oc, "execute-in-place",
1119 aspeed_get_mmio_exec,
1120 aspeed_set_mmio_exec);
1121 object_class_property_set_description(oc, "execute-in-place",
1122 "boot directly from CE0 flash device");
1123
1124 object_class_property_add_str(oc, "bmc-console", aspeed_get_bmc_console,
1125 aspeed_set_bmc_console);
1126 object_class_property_set_description(oc, "bmc-console",
1127 "Change the default UART to \"uartX\"");
1128
1129 object_class_property_add_str(oc, "fmc-model", aspeed_get_fmc_model,
1130 aspeed_set_fmc_model);
1131 object_class_property_set_description(oc, "fmc-model",
1132 "Change the FMC Flash model");
1133 object_class_property_add_str(oc, "spi-model", aspeed_get_spi_model,
1134 aspeed_set_spi_model);
1135 object_class_property_set_description(oc, "spi-model",
1136 "Change the SPI Flash model");
1137 }
1138
1139 static int aspeed_soc_num_cpus(const char *soc_name)
1140 {
1141 AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(soc_name));
1142 return sc->num_cpus;
1143 }
1144
1145 static void aspeed_machine_class_init(ObjectClass *oc, void *data)
1146 {
1147 MachineClass *mc = MACHINE_CLASS(oc);
1148 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1149
1150 mc->init = aspeed_machine_init;
1151 mc->no_floppy = 1;
1152 mc->no_cdrom = 1;
1153 mc->no_parallel = 1;
1154 mc->default_ram_id = "ram";
1155 amc->macs_mask = ASPEED_MAC0_ON;
1156 amc->uart_default = ASPEED_DEV_UART5;
1157
1158 aspeed_machine_class_props_init(oc);
1159 }
1160
1161 static void aspeed_machine_palmetto_class_init(ObjectClass *oc, void *data)
1162 {
1163 MachineClass *mc = MACHINE_CLASS(oc);
1164 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1165
1166 mc->desc = "OpenPOWER Palmetto BMC (ARM926EJ-S)";
1167 amc->soc_name = "ast2400-a1";
1168 amc->hw_strap1 = PALMETTO_BMC_HW_STRAP1;
1169 amc->fmc_model = "n25q256a";
1170 amc->spi_model = "mx25l25635f";
1171 amc->num_cs = 1;
1172 amc->i2c_init = palmetto_bmc_i2c_init;
1173 mc->default_ram_size = 256 * MiB;
1174 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1175 aspeed_soc_num_cpus(amc->soc_name);
1176 };
1177
1178 static void aspeed_machine_quanta_q71l_class_init(ObjectClass *oc, void *data)
1179 {
1180 MachineClass *mc = MACHINE_CLASS(oc);
1181 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1182
1183 mc->desc = "Quanta-Q71l BMC (ARM926EJ-S)";
1184 amc->soc_name = "ast2400-a1";
1185 amc->hw_strap1 = QUANTA_Q71L_BMC_HW_STRAP1;
1186 amc->fmc_model = "n25q256a";
1187 amc->spi_model = "mx25l25635e";
1188 amc->num_cs = 1;
1189 amc->i2c_init = quanta_q71l_bmc_i2c_init;
1190 mc->default_ram_size = 128 * MiB;
1191 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1192 aspeed_soc_num_cpus(amc->soc_name);
1193 }
1194
1195 static void aspeed_machine_supermicrox11_bmc_class_init(ObjectClass *oc,
1196 void *data)
1197 {
1198 MachineClass *mc = MACHINE_CLASS(oc);
1199 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1200
1201 mc->desc = "Supermicro X11 BMC (ARM926EJ-S)";
1202 amc->soc_name = "ast2400-a1";
1203 amc->hw_strap1 = SUPERMICROX11_BMC_HW_STRAP1;
1204 amc->fmc_model = "mx25l25635e";
1205 amc->spi_model = "mx25l25635e";
1206 amc->num_cs = 1;
1207 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
1208 amc->i2c_init = palmetto_bmc_i2c_init;
1209 mc->default_ram_size = 256 * MiB;
1210 }
1211
1212 static void aspeed_machine_supermicro_x11spi_bmc_class_init(ObjectClass *oc,
1213 void *data)
1214 {
1215 MachineClass *mc = MACHINE_CLASS(oc);
1216 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1217
1218 mc->desc = "Supermicro X11 SPI BMC (ARM1176)";
1219 amc->soc_name = "ast2500-a1";
1220 amc->hw_strap1 = SUPERMICRO_X11SPI_BMC_HW_STRAP1;
1221 amc->fmc_model = "mx25l25635e";
1222 amc->spi_model = "mx25l25635e";
1223 amc->num_cs = 1;
1224 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
1225 amc->i2c_init = palmetto_bmc_i2c_init;
1226 mc->default_ram_size = 512 * MiB;
1227 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1228 aspeed_soc_num_cpus(amc->soc_name);
1229 }
1230
1231 static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, void *data)
1232 {
1233 MachineClass *mc = MACHINE_CLASS(oc);
1234 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1235
1236 mc->desc = "Aspeed AST2500 EVB (ARM1176)";
1237 amc->soc_name = "ast2500-a1";
1238 amc->hw_strap1 = AST2500_EVB_HW_STRAP1;
1239 amc->fmc_model = "mx25l25635e";
1240 amc->spi_model = "mx25l25635f";
1241 amc->num_cs = 1;
1242 amc->i2c_init = ast2500_evb_i2c_init;
1243 mc->default_ram_size = 512 * MiB;
1244 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1245 aspeed_soc_num_cpus(amc->soc_name);
1246 };
1247
1248 static void aspeed_machine_yosemitev2_class_init(ObjectClass *oc, void *data)
1249 {
1250 MachineClass *mc = MACHINE_CLASS(oc);
1251 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1252
1253 mc->desc = "Facebook YosemiteV2 BMC (ARM1176)";
1254 amc->soc_name = "ast2500-a1";
1255 amc->hw_strap1 = AST2500_EVB_HW_STRAP1;
1256 amc->hw_strap2 = 0;
1257 amc->fmc_model = "n25q256a";
1258 amc->spi_model = "mx25l25635e";
1259 amc->num_cs = 2;
1260 amc->i2c_init = yosemitev2_bmc_i2c_init;
1261 mc->default_ram_size = 512 * MiB;
1262 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1263 aspeed_soc_num_cpus(amc->soc_name);
1264 };
1265
1266 static void aspeed_machine_romulus_class_init(ObjectClass *oc, void *data)
1267 {
1268 MachineClass *mc = MACHINE_CLASS(oc);
1269 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1270
1271 mc->desc = "OpenPOWER Romulus BMC (ARM1176)";
1272 amc->soc_name = "ast2500-a1";
1273 amc->hw_strap1 = ROMULUS_BMC_HW_STRAP1;
1274 amc->fmc_model = "n25q256a";
1275 amc->spi_model = "mx66l1g45g";
1276 amc->num_cs = 2;
1277 amc->i2c_init = romulus_bmc_i2c_init;
1278 mc->default_ram_size = 512 * MiB;
1279 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1280 aspeed_soc_num_cpus(amc->soc_name);
1281 };
1282
1283 static void aspeed_machine_tiogapass_class_init(ObjectClass *oc, void *data)
1284 {
1285 MachineClass *mc = MACHINE_CLASS(oc);
1286 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1287
1288 mc->desc = "Facebook Tiogapass BMC (ARM1176)";
1289 amc->soc_name = "ast2500-a1";
1290 amc->hw_strap1 = AST2500_EVB_HW_STRAP1;
1291 amc->hw_strap2 = 0;
1292 amc->fmc_model = "n25q256a";
1293 amc->spi_model = "mx25l25635e";
1294 amc->num_cs = 2;
1295 amc->i2c_init = tiogapass_bmc_i2c_init;
1296 mc->default_ram_size = 1 * GiB;
1297 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1298 aspeed_soc_num_cpus(amc->soc_name);
1299 aspeed_soc_num_cpus(amc->soc_name);
1300 };
1301
1302 static void aspeed_machine_sonorapass_class_init(ObjectClass *oc, void *data)
1303 {
1304 MachineClass *mc = MACHINE_CLASS(oc);
1305 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1306
1307 mc->desc = "OCP SonoraPass BMC (ARM1176)";
1308 amc->soc_name = "ast2500-a1";
1309 amc->hw_strap1 = SONORAPASS_BMC_HW_STRAP1;
1310 amc->fmc_model = "mx66l1g45g";
1311 amc->spi_model = "mx66l1g45g";
1312 amc->num_cs = 2;
1313 amc->i2c_init = sonorapass_bmc_i2c_init;
1314 mc->default_ram_size = 512 * MiB;
1315 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1316 aspeed_soc_num_cpus(amc->soc_name);
1317 };
1318
1319 static void aspeed_machine_witherspoon_class_init(ObjectClass *oc, void *data)
1320 {
1321 MachineClass *mc = MACHINE_CLASS(oc);
1322 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1323
1324 mc->desc = "OpenPOWER Witherspoon BMC (ARM1176)";
1325 amc->soc_name = "ast2500-a1";
1326 amc->hw_strap1 = WITHERSPOON_BMC_HW_STRAP1;
1327 amc->fmc_model = "mx25l25635f";
1328 amc->spi_model = "mx66l1g45g";
1329 amc->num_cs = 2;
1330 amc->i2c_init = witherspoon_bmc_i2c_init;
1331 mc->default_ram_size = 512 * MiB;
1332 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1333 aspeed_soc_num_cpus(amc->soc_name);
1334 };
1335
1336 static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, void *data)
1337 {
1338 MachineClass *mc = MACHINE_CLASS(oc);
1339 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1340
1341 mc->desc = "Aspeed AST2600 EVB (Cortex-A7)";
1342 amc->soc_name = "ast2600-a3";
1343 amc->hw_strap1 = AST2600_EVB_HW_STRAP1;
1344 amc->hw_strap2 = AST2600_EVB_HW_STRAP2;
1345 amc->fmc_model = "mx66u51235f";
1346 amc->spi_model = "mx66u51235f";
1347 amc->num_cs = 1;
1348 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON |
1349 ASPEED_MAC3_ON;
1350 amc->i2c_init = ast2600_evb_i2c_init;
1351 mc->default_ram_size = 1 * GiB;
1352 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1353 aspeed_soc_num_cpus(amc->soc_name);
1354 };
1355
1356 static void aspeed_machine_tacoma_class_init(ObjectClass *oc, void *data)
1357 {
1358 MachineClass *mc = MACHINE_CLASS(oc);
1359 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1360
1361 mc->desc = "OpenPOWER Tacoma BMC (Cortex-A7)";
1362 amc->soc_name = "ast2600-a3";
1363 amc->hw_strap1 = TACOMA_BMC_HW_STRAP1;
1364 amc->hw_strap2 = TACOMA_BMC_HW_STRAP2;
1365 amc->fmc_model = "mx66l1g45g";
1366 amc->spi_model = "mx66l1g45g";
1367 amc->num_cs = 2;
1368 amc->macs_mask = ASPEED_MAC2_ON;
1369 amc->i2c_init = witherspoon_bmc_i2c_init; /* Same board layout */
1370 mc->default_ram_size = 1 * GiB;
1371 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1372 aspeed_soc_num_cpus(amc->soc_name);
1373 };
1374
1375 static void aspeed_machine_g220a_class_init(ObjectClass *oc, void *data)
1376 {
1377 MachineClass *mc = MACHINE_CLASS(oc);
1378 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1379
1380 mc->desc = "Bytedance G220A BMC (ARM1176)";
1381 amc->soc_name = "ast2500-a1";
1382 amc->hw_strap1 = G220A_BMC_HW_STRAP1;
1383 amc->fmc_model = "n25q512a";
1384 amc->spi_model = "mx25l25635e";
1385 amc->num_cs = 2;
1386 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
1387 amc->i2c_init = g220a_bmc_i2c_init;
1388 mc->default_ram_size = 1024 * MiB;
1389 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1390 aspeed_soc_num_cpus(amc->soc_name);
1391 };
1392
1393 static void aspeed_machine_fp5280g2_class_init(ObjectClass *oc, void *data)
1394 {
1395 MachineClass *mc = MACHINE_CLASS(oc);
1396 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1397
1398 mc->desc = "Inspur FP5280G2 BMC (ARM1176)";
1399 amc->soc_name = "ast2500-a1";
1400 amc->hw_strap1 = FP5280G2_BMC_HW_STRAP1;
1401 amc->fmc_model = "n25q512a";
1402 amc->spi_model = "mx25l25635e";
1403 amc->num_cs = 2;
1404 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
1405 amc->i2c_init = fp5280g2_bmc_i2c_init;
1406 mc->default_ram_size = 512 * MiB;
1407 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1408 aspeed_soc_num_cpus(amc->soc_name);
1409 };
1410
1411 static void aspeed_machine_rainier_class_init(ObjectClass *oc, void *data)
1412 {
1413 MachineClass *mc = MACHINE_CLASS(oc);
1414 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1415
1416 mc->desc = "IBM Rainier BMC (Cortex-A7)";
1417 amc->soc_name = "ast2600-a3";
1418 amc->hw_strap1 = RAINIER_BMC_HW_STRAP1;
1419 amc->hw_strap2 = RAINIER_BMC_HW_STRAP2;
1420 amc->fmc_model = "mx66l1g45g";
1421 amc->spi_model = "mx66l1g45g";
1422 amc->num_cs = 2;
1423 amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON;
1424 amc->i2c_init = rainier_bmc_i2c_init;
1425 mc->default_ram_size = 1 * GiB;
1426 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1427 aspeed_soc_num_cpus(amc->soc_name);
1428 };
1429
1430 #define FUJI_BMC_RAM_SIZE ASPEED_RAM_SIZE(2 * GiB)
1431
1432 static void aspeed_machine_fuji_class_init(ObjectClass *oc, void *data)
1433 {
1434 MachineClass *mc = MACHINE_CLASS(oc);
1435 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1436
1437 mc->desc = "Facebook Fuji BMC (Cortex-A7)";
1438 amc->soc_name = "ast2600-a3";
1439 amc->hw_strap1 = FUJI_BMC_HW_STRAP1;
1440 amc->hw_strap2 = FUJI_BMC_HW_STRAP2;
1441 amc->fmc_model = "mx66l1g45g";
1442 amc->spi_model = "mx66l1g45g";
1443 amc->num_cs = 2;
1444 amc->macs_mask = ASPEED_MAC3_ON;
1445 amc->i2c_init = fuji_bmc_i2c_init;
1446 amc->uart_default = ASPEED_DEV_UART1;
1447 mc->default_ram_size = FUJI_BMC_RAM_SIZE;
1448 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1449 aspeed_soc_num_cpus(amc->soc_name);
1450 };
1451
1452 #define BLETCHLEY_BMC_RAM_SIZE ASPEED_RAM_SIZE(2 * GiB)
1453
1454 static void aspeed_machine_bletchley_class_init(ObjectClass *oc, void *data)
1455 {
1456 MachineClass *mc = MACHINE_CLASS(oc);
1457 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1458
1459 mc->desc = "Facebook Bletchley BMC (Cortex-A7)";
1460 amc->soc_name = "ast2600-a3";
1461 amc->hw_strap1 = BLETCHLEY_BMC_HW_STRAP1;
1462 amc->hw_strap2 = BLETCHLEY_BMC_HW_STRAP2;
1463 amc->fmc_model = "w25q01jvq";
1464 amc->spi_model = NULL;
1465 amc->num_cs = 2;
1466 amc->macs_mask = ASPEED_MAC2_ON;
1467 amc->i2c_init = bletchley_bmc_i2c_init;
1468 mc->default_ram_size = BLETCHLEY_BMC_RAM_SIZE;
1469 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1470 aspeed_soc_num_cpus(amc->soc_name);
1471 }
1472
1473 static void fby35_reset(MachineState *state, ShutdownCause reason)
1474 {
1475 AspeedMachineState *bmc = ASPEED_MACHINE(state);
1476 AspeedGPIOState *gpio = &bmc->soc.gpio;
1477
1478 qemu_devices_reset(reason);
1479
1480 /* Board ID: 7 (Class-1, 4 slots) */
1481 object_property_set_bool(OBJECT(gpio), "gpioV4", true, &error_fatal);
1482 object_property_set_bool(OBJECT(gpio), "gpioV5", true, &error_fatal);
1483 object_property_set_bool(OBJECT(gpio), "gpioV6", true, &error_fatal);
1484 object_property_set_bool(OBJECT(gpio), "gpioV7", false, &error_fatal);
1485
1486 /* Slot presence pins, inverse polarity. (False means present) */
1487 object_property_set_bool(OBJECT(gpio), "gpioH4", false, &error_fatal);
1488 object_property_set_bool(OBJECT(gpio), "gpioH5", true, &error_fatal);
1489 object_property_set_bool(OBJECT(gpio), "gpioH6", true, &error_fatal);
1490 object_property_set_bool(OBJECT(gpio), "gpioH7", true, &error_fatal);
1491
1492 /* Slot 12v power pins, normal polarity. (True means powered-on) */
1493 object_property_set_bool(OBJECT(gpio), "gpioB2", true, &error_fatal);
1494 object_property_set_bool(OBJECT(gpio), "gpioB3", false, &error_fatal);
1495 object_property_set_bool(OBJECT(gpio), "gpioB4", false, &error_fatal);
1496 object_property_set_bool(OBJECT(gpio), "gpioB5", false, &error_fatal);
1497 }
1498
1499 static void aspeed_machine_fby35_class_init(ObjectClass *oc, void *data)
1500 {
1501 MachineClass *mc = MACHINE_CLASS(oc);
1502 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1503
1504 mc->desc = "Facebook fby35 BMC (Cortex-A7)";
1505 mc->reset = fby35_reset;
1506 amc->fmc_model = "mx66l1g45g";
1507 amc->num_cs = 2;
1508 amc->macs_mask = ASPEED_MAC3_ON;
1509 amc->i2c_init = fby35_i2c_init;
1510 /* FIXME: Replace this macro with something more general */
1511 mc->default_ram_size = FUJI_BMC_RAM_SIZE;
1512 }
1513
1514 #define AST1030_INTERNAL_FLASH_SIZE (1024 * 1024)
1515 /* Main SYSCLK frequency in Hz (200MHz) */
1516 #define SYSCLK_FRQ 200000000ULL
1517
1518 static void aspeed_minibmc_machine_init(MachineState *machine)
1519 {
1520 AspeedMachineState *bmc = ASPEED_MACHINE(machine);
1521 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine);
1522 Clock *sysclk;
1523
1524 sysclk = clock_new(OBJECT(machine), "SYSCLK");
1525 clock_set_hz(sysclk, SYSCLK_FRQ);
1526
1527 object_initialize_child(OBJECT(machine), "soc", &bmc->soc, amc->soc_name);
1528 qdev_connect_clock_in(DEVICE(&bmc->soc), "sysclk", sysclk);
1529
1530 object_property_set_link(OBJECT(&bmc->soc), "memory",
1531 OBJECT(get_system_memory()), &error_abort);
1532 connect_serial_hds_to_uarts(bmc);
1533 qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort);
1534
1535 aspeed_board_init_flashes(&bmc->soc.fmc,
1536 bmc->fmc_model ? bmc->fmc_model : amc->fmc_model,
1537 amc->num_cs,
1538 0);
1539
1540 aspeed_board_init_flashes(&bmc->soc.spi[0],
1541 bmc->spi_model ? bmc->spi_model : amc->spi_model,
1542 amc->num_cs, amc->num_cs);
1543
1544 aspeed_board_init_flashes(&bmc->soc.spi[1],
1545 bmc->spi_model ? bmc->spi_model : amc->spi_model,
1546 amc->num_cs, (amc->num_cs * 2));
1547
1548 if (amc->i2c_init) {
1549 amc->i2c_init(bmc);
1550 }
1551
1552 armv7m_load_kernel(ARM_CPU(first_cpu),
1553 machine->kernel_filename,
1554 0,
1555 AST1030_INTERNAL_FLASH_SIZE);
1556 }
1557
1558 static void ast1030_evb_i2c_init(AspeedMachineState *bmc)
1559 {
1560 AspeedSoCState *soc = &bmc->soc;
1561
1562 /* U10 24C08 connects to SDA/SCL Group 1 by default */
1563 uint8_t *eeprom_buf = g_malloc0(32 * 1024);
1564 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50, eeprom_buf);
1565
1566 /* U11 LM75 connects to SDA/SCL Group 2 by default */
1567 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4d);
1568 }
1569
1570 static void aspeed_minibmc_machine_ast1030_evb_class_init(ObjectClass *oc,
1571 void *data)
1572 {
1573 MachineClass *mc = MACHINE_CLASS(oc);
1574 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1575
1576 mc->desc = "Aspeed AST1030 MiniBMC (Cortex-M4)";
1577 amc->soc_name = "ast1030-a1";
1578 amc->hw_strap1 = 0;
1579 amc->hw_strap2 = 0;
1580 mc->init = aspeed_minibmc_machine_init;
1581 amc->i2c_init = ast1030_evb_i2c_init;
1582 mc->default_ram_size = 0;
1583 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1;
1584 amc->fmc_model = "sst25vf032b";
1585 amc->spi_model = "sst25vf032b";
1586 amc->num_cs = 2;
1587 amc->macs_mask = 0;
1588 }
1589
1590 static void aspeed_machine_qcom_dc_scm_v1_class_init(ObjectClass *oc,
1591 void *data)
1592 {
1593 MachineClass *mc = MACHINE_CLASS(oc);
1594 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1595
1596 mc->desc = "Qualcomm DC-SCM V1 BMC (Cortex A7)";
1597 amc->soc_name = "ast2600-a3";
1598 amc->hw_strap1 = QCOM_DC_SCM_V1_BMC_HW_STRAP1;
1599 amc->hw_strap2 = QCOM_DC_SCM_V1_BMC_HW_STRAP2;
1600 amc->fmc_model = "n25q512a";
1601 amc->spi_model = "n25q512a";
1602 amc->num_cs = 2;
1603 amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON;
1604 amc->i2c_init = qcom_dc_scm_bmc_i2c_init;
1605 mc->default_ram_size = 1 * GiB;
1606 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1607 aspeed_soc_num_cpus(amc->soc_name);
1608 };
1609
1610 static void aspeed_machine_qcom_firework_class_init(ObjectClass *oc,
1611 void *data)
1612 {
1613 MachineClass *mc = MACHINE_CLASS(oc);
1614 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1615
1616 mc->desc = "Qualcomm DC-SCM V1/Firework BMC (Cortex A7)";
1617 amc->soc_name = "ast2600-a3";
1618 amc->hw_strap1 = QCOM_DC_SCM_V1_BMC_HW_STRAP1;
1619 amc->hw_strap2 = QCOM_DC_SCM_V1_BMC_HW_STRAP2;
1620 amc->fmc_model = "n25q512a";
1621 amc->spi_model = "n25q512a";
1622 amc->num_cs = 2;
1623 amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON;
1624 amc->i2c_init = qcom_dc_scm_firework_i2c_init;
1625 mc->default_ram_size = 1 * GiB;
1626 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1627 aspeed_soc_num_cpus(amc->soc_name);
1628 };
1629
1630 static const TypeInfo aspeed_machine_types[] = {
1631 {
1632 .name = MACHINE_TYPE_NAME("palmetto-bmc"),
1633 .parent = TYPE_ASPEED_MACHINE,
1634 .class_init = aspeed_machine_palmetto_class_init,
1635 }, {
1636 .name = MACHINE_TYPE_NAME("supermicrox11-bmc"),
1637 .parent = TYPE_ASPEED_MACHINE,
1638 .class_init = aspeed_machine_supermicrox11_bmc_class_init,
1639 }, {
1640 .name = MACHINE_TYPE_NAME("supermicro-x11spi-bmc"),
1641 .parent = TYPE_ASPEED_MACHINE,
1642 .class_init = aspeed_machine_supermicro_x11spi_bmc_class_init,
1643 }, {
1644 .name = MACHINE_TYPE_NAME("ast2500-evb"),
1645 .parent = TYPE_ASPEED_MACHINE,
1646 .class_init = aspeed_machine_ast2500_evb_class_init,
1647 }, {
1648 .name = MACHINE_TYPE_NAME("romulus-bmc"),
1649 .parent = TYPE_ASPEED_MACHINE,
1650 .class_init = aspeed_machine_romulus_class_init,
1651 }, {
1652 .name = MACHINE_TYPE_NAME("sonorapass-bmc"),
1653 .parent = TYPE_ASPEED_MACHINE,
1654 .class_init = aspeed_machine_sonorapass_class_init,
1655 }, {
1656 .name = MACHINE_TYPE_NAME("witherspoon-bmc"),
1657 .parent = TYPE_ASPEED_MACHINE,
1658 .class_init = aspeed_machine_witherspoon_class_init,
1659 }, {
1660 .name = MACHINE_TYPE_NAME("ast2600-evb"),
1661 .parent = TYPE_ASPEED_MACHINE,
1662 .class_init = aspeed_machine_ast2600_evb_class_init,
1663 }, {
1664 .name = MACHINE_TYPE_NAME("yosemitev2-bmc"),
1665 .parent = TYPE_ASPEED_MACHINE,
1666 .class_init = aspeed_machine_yosemitev2_class_init,
1667 }, {
1668 .name = MACHINE_TYPE_NAME("tacoma-bmc"),
1669 .parent = TYPE_ASPEED_MACHINE,
1670 .class_init = aspeed_machine_tacoma_class_init,
1671 }, {
1672 .name = MACHINE_TYPE_NAME("tiogapass-bmc"),
1673 .parent = TYPE_ASPEED_MACHINE,
1674 .class_init = aspeed_machine_tiogapass_class_init,
1675 }, {
1676 .name = MACHINE_TYPE_NAME("g220a-bmc"),
1677 .parent = TYPE_ASPEED_MACHINE,
1678 .class_init = aspeed_machine_g220a_class_init,
1679 }, {
1680 .name = MACHINE_TYPE_NAME("qcom-dc-scm-v1-bmc"),
1681 .parent = TYPE_ASPEED_MACHINE,
1682 .class_init = aspeed_machine_qcom_dc_scm_v1_class_init,
1683 }, {
1684 .name = MACHINE_TYPE_NAME("qcom-firework-bmc"),
1685 .parent = TYPE_ASPEED_MACHINE,
1686 .class_init = aspeed_machine_qcom_firework_class_init,
1687 }, {
1688 .name = MACHINE_TYPE_NAME("fp5280g2-bmc"),
1689 .parent = TYPE_ASPEED_MACHINE,
1690 .class_init = aspeed_machine_fp5280g2_class_init,
1691 }, {
1692 .name = MACHINE_TYPE_NAME("quanta-q71l-bmc"),
1693 .parent = TYPE_ASPEED_MACHINE,
1694 .class_init = aspeed_machine_quanta_q71l_class_init,
1695 }, {
1696 .name = MACHINE_TYPE_NAME("rainier-bmc"),
1697 .parent = TYPE_ASPEED_MACHINE,
1698 .class_init = aspeed_machine_rainier_class_init,
1699 }, {
1700 .name = MACHINE_TYPE_NAME("fuji-bmc"),
1701 .parent = TYPE_ASPEED_MACHINE,
1702 .class_init = aspeed_machine_fuji_class_init,
1703 }, {
1704 .name = MACHINE_TYPE_NAME("bletchley-bmc"),
1705 .parent = TYPE_ASPEED_MACHINE,
1706 .class_init = aspeed_machine_bletchley_class_init,
1707 }, {
1708 .name = MACHINE_TYPE_NAME("fby35-bmc"),
1709 .parent = MACHINE_TYPE_NAME("ast2600-evb"),
1710 .class_init = aspeed_machine_fby35_class_init,
1711 }, {
1712 .name = MACHINE_TYPE_NAME("ast1030-evb"),
1713 .parent = TYPE_ASPEED_MACHINE,
1714 .class_init = aspeed_minibmc_machine_ast1030_evb_class_init,
1715 }, {
1716 .name = TYPE_ASPEED_MACHINE,
1717 .parent = TYPE_MACHINE,
1718 .instance_size = sizeof(AspeedMachineState),
1719 .instance_init = aspeed_machine_instance_init,
1720 .class_size = sizeof(AspeedMachineClass),
1721 .class_init = aspeed_machine_class_init,
1722 .abstract = true,
1723 }
1724 };
1725
1726 DEFINE_TYPES(aspeed_machine_types)
armbru's QEMU hackery