include/qom/cpu.h

   1 /*
   2  * QEMU CPU model
   3  *
   4  * Copyright (c) 2012 SUSE LINUX Products GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version 2
   9  * of the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, see
  18  * <http://www.gnu.org/licenses/gpl-2.0.html>
  19  */
  20 #ifndef QEMU_CPU_H
  21 #define QEMU_CPU_H
  22
  23 #include <signal.h>
  24 #include <setjmp.h>
  25 #include "hw/qdev-core.h"
  26 #include "disas/bfd.h"
  27 #include "exec/hwaddr.h"
  28 #include "exec/memattrs.h"
  29 #include "qemu/queue.h"
  30 #include "qemu/thread.h"
  31 #include "qemu/typedefs.h"
  32
  33 typedef int (*WriteCoreDumpFunction)(const void *buf, size_t size,
  34                                      void *opaque);
  35
  36 /**
  37  * vaddr:
  38  * Type wide enough to contain any #target_ulong virtual address.
  39  */
  40 typedef uint64_t vaddr;
  41 #define VADDR_PRId PRId64
  42 #define VADDR_PRIu PRIu64
  43 #define VADDR_PRIo PRIo64
  44 #define VADDR_PRIx PRIx64
  45 #define VADDR_PRIX PRIX64
  46 #define VADDR_MAX UINT64_MAX
  47
  48 /**
  49  * SECTION:cpu
  50  * @section_id: QEMU-cpu
  51  * @title: CPU Class
  52  * @short_description: Base class for all CPUs
  53  */
  54
  55 #define TYPE_CPU "cpu"
  56
  57 /* Since this macro is used a lot in hot code paths and in conjunction with
  58  * FooCPU *foo_env_get_cpu(), we deviate from usual QOM practice by using
  59  * an unchecked cast.
  60  */
  61 #define CPU(obj) ((CPUState *)(obj))
  62
  63 #define CPU_CLASS(class) OBJECT_CLASS_CHECK(CPUClass, (class), TYPE_CPU)
  64 #define CPU_GET_CLASS(obj) OBJECT_GET_CLASS(CPUClass, (obj), TYPE_CPU)
  65
  66 typedef struct CPUState CPUState;
  67
  68 typedef void (*CPUUnassignedAccess)(CPUState *cpu, hwaddr addr,
  69                                     bool is_write, bool is_exec, int opaque,
  70                                     unsigned size);
  71
  72 struct TranslationBlock;
  73
  74 /**
  75  * CPUClass:
  76  * @class_by_name: Callback to map -cpu command line model name to an
  77  * instantiatable CPU type.
  78  * @parse_features: Callback to parse command line arguments.
  79  * @reset: Callback to reset the #CPUState to its initial state.
  80  * @reset_dump_flags: #CPUDumpFlags to use for reset logging.
  81  * @has_work: Callback for checking if there is work to do.
  82  * @do_interrupt: Callback for interrupt handling.
  83  * @do_unassigned_access: Callback for unassigned access handling.
  84  * @do_unaligned_access: Callback for unaligned access handling, if
  85  * the target defines #ALIGNED_ONLY.
  86  * @virtio_is_big_endian: Callback to return %true if a CPU which supports
  87  * runtime configurable endianness is currently big-endian. Non-configurable
  88  * CPUs can use the default implementation of this method. This method should
  89  * not be used by any callers other than the pre-1.0 virtio devices.
  90  * @memory_rw_debug: Callback for GDB memory access.
  91  * @dump_state: Callback for dumping state.
  92  * @dump_statistics: Callback for dumping statistics.
  93  * @get_arch_id: Callback for getting architecture-dependent CPU ID.
  94  * @get_paging_enabled: Callback for inquiring whether paging is enabled.
  95  * @get_memory_mapping: Callback for obtaining the memory mappings.
  96  * @set_pc: Callback for setting the Program Counter register.
  97  * @synchronize_from_tb: Callback for synchronizing state from a TCG
  98  * #TranslationBlock.
  99  * @handle_mmu_fault: Callback for handling an MMU fault.
 100  * @get_phys_page_debug: Callback for obtaining a physical address.
 101  * @gdb_read_register: Callback for letting GDB read a register.
 102  * @gdb_write_register: Callback for letting GDB write a register.
 103  * @debug_excp_handler: Callback for handling debug exceptions.
 104  * @write_elf64_note: Callback for writing a CPU-specific ELF note to a
 105  * 64-bit VM coredump.
 106  * @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF
 107  * note to a 32-bit VM coredump.
 108  * @write_elf32_note: Callback for writing a CPU-specific ELF note to a
 109  * 32-bit VM coredump.
 110  * @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF
 111  * note to a 32-bit VM coredump.
 112  * @vmsd: State description for migration.
 113  * @gdb_num_core_regs: Number of core registers accessible to GDB.
 114  * @gdb_core_xml_file: File name for core registers GDB XML description.
 115  * @gdb_stop_before_watchpoint: Indicates whether GDB expects the CPU to stop
 116  *           before the insn which triggers a watchpoint rather than after it.
 117  * @cpu_exec_enter: Callback for cpu_exec preparation.
 118  * @cpu_exec_exit: Callback for cpu_exec cleanup.
 119  * @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec.
 120  * @disas_set_info: Setup architecture specific components of disassembly info
 121  *
 122  * Represents a CPU family or model.
 123  */
 124 typedef struct CPUClass {
 125     /*< private >*/
 126     DeviceClass parent_class;
 127     /*< public >*/
 128
 129     ObjectClass *(*class_by_name)(const char *cpu_model);
 130     void (*parse_features)(CPUState *cpu, char *str, Error **errp);
 131
 132     void (*reset)(CPUState *cpu);
 133     int reset_dump_flags;
 134     bool (*has_work)(CPUState *cpu);
 135     void (*do_interrupt)(CPUState *cpu);
 136     CPUUnassignedAccess do_unassigned_access;
 137     void (*do_unaligned_access)(CPUState *cpu, vaddr addr,
 138                                 int is_write, int is_user, uintptr_t retaddr);
 139     bool (*virtio_is_big_endian)(CPUState *cpu);
 140     int (*memory_rw_debug)(CPUState *cpu, vaddr addr,
 141                            uint8_t *buf, int len, bool is_write);
 142     void (*dump_state)(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
 143                        int flags);
 144     void (*dump_statistics)(CPUState *cpu, FILE *f,
 145                             fprintf_function cpu_fprintf, int flags);
 146     int64_t (*get_arch_id)(CPUState *cpu);
 147     bool (*get_paging_enabled)(const CPUState *cpu);
 148     void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list,
 149                                Error **errp);
 150     void (*set_pc)(CPUState *cpu, vaddr value);
 151     void (*synchronize_from_tb)(CPUState *cpu, struct TranslationBlock *tb);
 152     int (*handle_mmu_fault)(CPUState *cpu, vaddr address, int rw,
 153                             int mmu_index);
 154     hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr);
 155     int (*gdb_read_register)(CPUState *cpu, uint8_t *buf, int reg);
 156     int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg);
 157     void (*debug_excp_handler)(CPUState *cpu);
 158
 159     int (*write_elf64_note)(WriteCoreDumpFunction f, CPUState *cpu,
 160                             int cpuid, void *opaque);
 161     int (*write_elf64_qemunote)(WriteCoreDumpFunction f, CPUState *cpu,
 162                                 void *opaque);
 163     int (*write_elf32_note)(WriteCoreDumpFunction f, CPUState *cpu,
 164                             int cpuid, void *opaque);
 165     int (*write_elf32_qemunote)(WriteCoreDumpFunction f, CPUState *cpu,
 166                                 void *opaque);
 167
 168     const struct VMStateDescription *vmsd;
 169     int gdb_num_core_regs;
 170     const char *gdb_core_xml_file;
 171     bool gdb_stop_before_watchpoint;
 172
 173     void (*cpu_exec_enter)(CPUState *cpu);
 174     void (*cpu_exec_exit)(CPUState *cpu);
 175     bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request);
 176
 177     void (*disas_set_info)(CPUState *cpu, disassemble_info *info);
 178 } CPUClass;
 179
 180 #ifdef HOST_WORDS_BIGENDIAN
 181 typedef struct icount_decr_u16 {
 182     uint16_t high;
 183     uint16_t low;
 184 } icount_decr_u16;
 185 #else
 186 typedef struct icount_decr_u16 {
 187     uint16_t low;
 188     uint16_t high;
 189 } icount_decr_u16;
 190 #endif
 191
 192 typedef struct CPUBreakpoint {
 193     vaddr pc;
 194     int flags; /* BP_* */
 195     QTAILQ_ENTRY(CPUBreakpoint) entry;
 196 } CPUBreakpoint;
 197
 198 typedef struct CPUWatchpoint {
 199     vaddr vaddr;
 200     vaddr len;
 201     vaddr hitaddr;
 202     MemTxAttrs hitattrs;
 203     int flags; /* BP_* */
 204     QTAILQ_ENTRY(CPUWatchpoint) entry;
 205 } CPUWatchpoint;
 206
 207 struct KVMState;
 208 struct kvm_run;
 209
 210 #define TB_JMP_CACHE_BITS 12
 211 #define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS)
 212
 213 /**
 214  * CPUState:
 215  * @cpu_index: CPU index (informative).
 216  * @nr_cores: Number of cores within this CPU package.
 217  * @nr_threads: Number of threads within this CPU.
 218  * @numa_node: NUMA node this CPU is belonging to.
 219  * @host_tid: Host thread ID.
 220  * @running: #true if CPU is currently running (usermode).
 221  * @created: Indicates whether the CPU thread has been successfully created.
 222  * @interrupt_request: Indicates a pending interrupt request.
 223  * @halted: Nonzero if the CPU is in suspended state.
 224  * @stop: Indicates a pending stop request.
 225  * @stopped: Indicates the CPU has been artificially stopped.
 226  * @crash_occurred: Indicates the OS reported a crash (panic) for this CPU
 227  * @tcg_exit_req: Set to force TCG to stop executing linked TBs for this
 228  *           CPU and return to its top level loop.
 229  * @singlestep_enabled: Flags for single-stepping.
 230  * @icount_extra: Instructions until next timer event.
 231  * @icount_decr: Number of cycles left, with interrupt flag in high bit.
 232  * This allows a single read-compare-cbranch-write sequence to test
 233  * for both decrementer underflow and exceptions.
 234  * @can_do_io: Nonzero if memory-mapped IO is safe. Deterministic execution
 235  * requires that IO only be performed on the last instruction of a TB
 236  * so that interrupts take effect immediately.
 237  * @env_ptr: Pointer to subclass-specific CPUArchState field.
 238  * @current_tb: Currently executing TB.
 239  * @gdb_regs: Additional GDB registers.
 240  * @gdb_num_regs: Number of total registers accessible to GDB.
 241  * @gdb_num_g_regs: Number of registers in GDB 'g' packets.
 242  * @next_cpu: Next CPU sharing TB cache.
 243  * @opaque: User data.
 244  * @mem_io_pc: Host Program Counter at which the memory was accessed.
 245  * @mem_io_vaddr: Target virtual address at which the memory was accessed.
 246  * @kvm_fd: vCPU file descriptor for KVM.
 247  * @work_mutex: Lock to prevent multiple access to queued_work_*.
 248  * @queued_work_first: First asynchronous work pending.
 249  *
 250  * State of one CPU core or thread.
 251  */
 252 struct CPUState {
 253     /*< private >*/
 254     DeviceState parent_obj;
 255     /*< public >*/
 256
 257     int nr_cores;
 258     int nr_threads;
 259     int numa_node;
 260
 261     struct QemuThread *thread;
 262 #ifdef _WIN32
 263     HANDLE hThread;
 264 #endif
 265     int thread_id;
 266     uint32_t host_tid;
 267     bool running;
 268     struct QemuCond *halt_cond;
 269     bool thread_kicked;
 270     bool created;
 271     bool stop;
 272     bool stopped;
 273     bool crash_occurred;
 274     bool exit_request;
 275     uint32_t interrupt_request;
 276     int singlestep_enabled;
 277     int64_t icount_extra;
 278     sigjmp_buf jmp_env;
 279
 280     QemuMutex work_mutex;
 281     struct qemu_work_item *queued_work_first, *queued_work_last;
 282
 283     AddressSpace *as;
 284     struct AddressSpaceDispatch *memory_dispatch;
 285     MemoryListener *tcg_as_listener;
 286
 287     void *env_ptr; /* CPUArchState */
 288     struct TranslationBlock *current_tb;
 289     struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE];
 290     struct GDBRegisterState *gdb_regs;
 291     int gdb_num_regs;
 292     int gdb_num_g_regs;
 293     QTAILQ_ENTRY(CPUState) node;
 294
 295     /* ice debug support */
 296     QTAILQ_HEAD(breakpoints_head, CPUBreakpoint) breakpoints;
 297
 298     QTAILQ_HEAD(watchpoints_head, CPUWatchpoint) watchpoints;
 299     CPUWatchpoint *watchpoint_hit;
 300
 301     void *opaque;
 302
 303     /* In order to avoid passing too many arguments to the MMIO helpers,
 304      * we store some rarely used information in the CPU context.
 305      */
 306     uintptr_t mem_io_pc;
 307     vaddr mem_io_vaddr;
 308
 309     int kvm_fd;
 310     bool kvm_vcpu_dirty;
 311     struct KVMState *kvm_state;
 312     struct kvm_run *kvm_run;
 313
 314     /* TODO Move common fields from CPUArchState here. */
 315     int cpu_index; /* used by alpha TCG */
 316     uint32_t halted; /* used by alpha, cris, ppc TCG */
 317     union {
 318         uint32_t u32;
 319         icount_decr_u16 u16;
 320     } icount_decr;
 321     uint32_t can_do_io;
 322     int32_t exception_index; /* used by m68k TCG */
 323
 324     /* Used to keep track of an outstanding cpu throttle thread for migration
 325      * autoconverge
 326      */
 327     bool throttle_thread_scheduled;
 328
 329     /* Note that this is accessed at the start of every TB via a negative
 330        offset from AREG0.  Leave this field at the end so as to make the
 331        (absolute value) offset as small as possible.  This reduces code
 332        size, especially for hosts without large memory offsets.  */
 333     uint32_t tcg_exit_req;
 334 };
 335
 336 QTAILQ_HEAD(CPUTailQ, CPUState);
 337 extern struct CPUTailQ cpus;
 338 #define CPU_NEXT(cpu) QTAILQ_NEXT(cpu, node)
 339 #define CPU_FOREACH(cpu) QTAILQ_FOREACH(cpu, &cpus, node)
 340 #define CPU_FOREACH_SAFE(cpu, next_cpu) \
 341     QTAILQ_FOREACH_SAFE(cpu, &cpus, node, next_cpu)
 342 #define CPU_FOREACH_REVERSE(cpu) \
 343     QTAILQ_FOREACH_REVERSE(cpu, &cpus, CPUTailQ, node)
 344 #define first_cpu QTAILQ_FIRST(&cpus)
 345
 346 extern __thread CPUState *current_cpu;
 347
 348 /**
 349  * cpu_paging_enabled:
 350  * @cpu: The CPU whose state is to be inspected.
 351  *
 352  * Returns: %true if paging is enabled, %false otherwise.
 353  */
 354 bool cpu_paging_enabled(const CPUState *cpu);
 355
 356 /**
 357  * cpu_get_memory_mapping:
 358  * @cpu: The CPU whose memory mappings are to be obtained.
 359  * @list: Where to write the memory mappings to.
 360  * @errp: Pointer for reporting an #Error.
 361  */
 362 void cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
 363                             Error **errp);
 364
 365 /**
 366  * cpu_write_elf64_note:
 367  * @f: pointer to a function that writes memory to a file
 368  * @cpu: The CPU whose memory is to be dumped
 369  * @cpuid: ID number of the CPU
 370  * @opaque: pointer to the CPUState struct
 371  */
 372 int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
 373                          int cpuid, void *opaque);
 374
 375 /**
 376  * cpu_write_elf64_qemunote:
 377  * @f: pointer to a function that writes memory to a file
 378  * @cpu: The CPU whose memory is to be dumped
 379  * @cpuid: ID number of the CPU
 380  * @opaque: pointer to the CPUState struct
 381  */
 382 int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
 383                              void *opaque);
 384
 385 /**
 386  * cpu_write_elf32_note:
 387  * @f: pointer to a function that writes memory to a file
 388  * @cpu: The CPU whose memory is to be dumped
 389  * @cpuid: ID number of the CPU
 390  * @opaque: pointer to the CPUState struct
 391  */
 392 int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu,
 393                          int cpuid, void *opaque);
 394
 395 /**
 396  * cpu_write_elf32_qemunote:
 397  * @f: pointer to a function that writes memory to a file
 398  * @cpu: The CPU whose memory is to be dumped
 399  * @cpuid: ID number of the CPU
 400  * @opaque: pointer to the CPUState struct
 401  */
 402 int cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
 403                              void *opaque);
 404
 405 /**
 406  * CPUDumpFlags:
 407  * @CPU_DUMP_CODE:
 408  * @CPU_DUMP_FPU: dump FPU register state, not just integer
 409  * @CPU_DUMP_CCOP: dump info about TCG QEMU's condition code optimization state
 410  */
 411 enum CPUDumpFlags {
 412     CPU_DUMP_CODE = 0x00010000,
 413     CPU_DUMP_FPU  = 0x00020000,
 414     CPU_DUMP_CCOP = 0x00040000,
 415 };
 416
 417 /**
 418  * cpu_dump_state:
 419  * @cpu: The CPU whose state is to be dumped.
 420  * @f: File to dump to.
 421  * @cpu_fprintf: Function to dump with.
 422  * @flags: Flags what to dump.
 423  *
 424  * Dumps CPU state.
 425  */
 426 void cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
 427                     int flags);
 428
 429 /**
 430  * cpu_dump_statistics:
 431  * @cpu: The CPU whose state is to be dumped.
 432  * @f: File to dump to.
 433  * @cpu_fprintf: Function to dump with.
 434  * @flags: Flags what to dump.
 435  *
 436  * Dumps CPU statistics.
 437  */
 438 void cpu_dump_statistics(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
 439                          int flags);
 440
 441 #ifndef CONFIG_USER_ONLY
 442 /**
 443  * cpu_get_phys_page_debug:
 444  * @cpu: The CPU to obtain the physical page address for.
 445  * @addr: The virtual address.
 446  *
 447  * Obtains the physical page corresponding to a virtual one.
 448  * Use it only for debugging because no protection checks are done.
 449  *
 450  * Returns: Corresponding physical page address or -1 if no page found.
 451  */
 452 static inline hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr)
 453 {
 454     CPUClass *cc = CPU_GET_CLASS(cpu);
 455
 456     return cc->get_phys_page_debug(cpu, addr);
 457 }
 458 #endif
 459
 460 /**
 461  * cpu_reset:
 462  * @cpu: The CPU whose state is to be reset.
 463  */
 464 void cpu_reset(CPUState *cpu);
 465
 466 /**
 467  * cpu_class_by_name:
 468  * @typename: The CPU base type.
 469  * @cpu_model: The model string without any parameters.
 470  *
 471  * Looks up a CPU #ObjectClass matching name @cpu_model.
 472  *
 473  * Returns: A #CPUClass or %NULL if not matching class is found.
 474  */
 475 ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_model);
 476
 477 /**
 478  * cpu_generic_init:
 479  * @typename: The CPU base type.
 480  * @cpu_model: The model string including optional parameters.
 481  *
 482  * Instantiates a CPU, processes optional parameters and realizes the CPU.
 483  *
 484  * Returns: A #CPUState or %NULL if an error occurred.
 485  */
 486 CPUState *cpu_generic_init(const char *typename, const char *cpu_model);
 487
 488 /**
 489  * cpu_has_work:
 490  * @cpu: The vCPU to check.
 491  *
 492  * Checks whether the CPU has work to do.
 493  *
 494  * Returns: %true if the CPU has work, %false otherwise.
 495  */
 496 static inline bool cpu_has_work(CPUState *cpu)
 497 {
 498     CPUClass *cc = CPU_GET_CLASS(cpu);
 499
 500     g_assert(cc->has_work);
 501     return cc->has_work(cpu);
 502 }
 503
 504 /**
 505  * qemu_cpu_is_self:
 506  * @cpu: The vCPU to check against.
 507  *
 508  * Checks whether the caller is executing on the vCPU thread.
 509  *
 510  * Returns: %true if called from @cpu's thread, %false otherwise.
 511  */
 512 bool qemu_cpu_is_self(CPUState *cpu);
 513
 514 /**
 515  * qemu_cpu_kick:
 516  * @cpu: The vCPU to kick.
 517  *
 518  * Kicks @cpu's thread.
 519  */
 520 void qemu_cpu_kick(CPUState *cpu);
 521
 522 /**
 523  * cpu_is_stopped:
 524  * @cpu: The CPU to check.
 525  *
 526  * Checks whether the CPU is stopped.
 527  *
 528  * Returns: %true if run state is not running or if artificially stopped;
 529  * %false otherwise.
 530  */
 531 bool cpu_is_stopped(CPUState *cpu);
 532
 533 /**
 534  * run_on_cpu:
 535  * @cpu: The vCPU to run on.
 536  * @func: The function to be executed.
 537  * @data: Data to pass to the function.
 538  *
 539  * Schedules the function @func for execution on the vCPU @cpu.
 540  */
 541 void run_on_cpu(CPUState *cpu, void (*func)(void *data), void *data);
 542
 543 /**
 544  * async_run_on_cpu:
 545  * @cpu: The vCPU to run on.
 546  * @func: The function to be executed.
 547  * @data: Data to pass to the function.
 548  *
 549  * Schedules the function @func for execution on the vCPU @cpu asynchronously.
 550  */
 551 void async_run_on_cpu(CPUState *cpu, void (*func)(void *data), void *data);
 552
 553 /**
 554  * qemu_get_cpu:
 555  * @index: The CPUState@cpu_index value of the CPU to obtain.
 556  *
 557  * Gets a CPU matching @index.
 558  *
 559  * Returns: The CPU or %NULL if there is no matching CPU.
 560  */
 561 CPUState *qemu_get_cpu(int index);
 562
 563 /**
 564  * cpu_exists:
 565  * @id: Guest-exposed CPU ID to lookup.
 566  *
 567  * Search for CPU with specified ID.
 568  *
 569  * Returns: %true - CPU is found, %false - CPU isn't found.
 570  */
 571 bool cpu_exists(int64_t id);
 572
 573 /**
 574  * cpu_throttle_set:
 575  * @new_throttle_pct: Percent of sleep time. Valid range is 1 to 99.
 576  *
 577  * Throttles all vcpus by forcing them to sleep for the given percentage of
 578  * time. A throttle_percentage of 25 corresponds to a 75% duty cycle roughly.
 579  * (example: 10ms sleep for every 30ms awake).
 580  *
 581  * cpu_throttle_set can be called as needed to adjust new_throttle_pct.
 582  * Once the throttling starts, it will remain in effect until cpu_throttle_stop
 583  * is called.
 584  */
 585 void cpu_throttle_set(int new_throttle_pct);
 586
 587 /**
 588  * cpu_throttle_stop:
 589  *
 590  * Stops the vcpu throttling started by cpu_throttle_set.
 591  */
 592 void cpu_throttle_stop(void);
 593
 594 /**
 595  * cpu_throttle_active:
 596  *
 597  * Returns: %true if the vcpus are currently being throttled, %false otherwise.
 598  */
 599 bool cpu_throttle_active(void);
 600
 601 /**
 602  * cpu_throttle_get_percentage:
 603  *
 604  * Returns the vcpu throttle percentage. See cpu_throttle_set for details.
 605  *
 606  * Returns: The throttle percentage in range 1 to 99.
 607  */
 608 int cpu_throttle_get_percentage(void);
 609
 610 #ifndef CONFIG_USER_ONLY
 611
 612 typedef void (*CPUInterruptHandler)(CPUState *, int);
 613
 614 extern CPUInterruptHandler cpu_interrupt_handler;
 615
 616 /**
 617  * cpu_interrupt:
 618  * @cpu: The CPU to set an interrupt on.
 619  * @mask: The interupts to set.
 620  *
 621  * Invokes the interrupt handler.
 622  */
 623 static inline void cpu_interrupt(CPUState *cpu, int mask)
 624 {
 625     cpu_interrupt_handler(cpu, mask);
 626 }
 627
 628 #else /* USER_ONLY */
 629
 630 void cpu_interrupt(CPUState *cpu, int mask);
 631
 632 #endif /* USER_ONLY */
 633
 634 #ifdef CONFIG_SOFTMMU
 635 static inline void cpu_unassigned_access(CPUState *cpu, hwaddr addr,
 636                                          bool is_write, bool is_exec,
 637                                          int opaque, unsigned size)
 638 {
 639     CPUClass *cc = CPU_GET_CLASS(cpu);
 640
 641     if (cc->do_unassigned_access) {
 642         cc->do_unassigned_access(cpu, addr, is_write, is_exec, opaque, size);
 643     }
 644 }
 645
 646 static inline void cpu_unaligned_access(CPUState *cpu, vaddr addr,
 647                                         int is_write, int is_user,
 648                                         uintptr_t retaddr)
 649 {
 650     CPUClass *cc = CPU_GET_CLASS(cpu);
 651
 652     cc->do_unaligned_access(cpu, addr, is_write, is_user, retaddr);
 653 }
 654 #endif
 655
 656 /**
 657  * cpu_set_pc:
 658  * @cpu: The CPU to set the program counter for.
 659  * @addr: Program counter value.
 660  *
 661  * Sets the program counter for a CPU.
 662  */
 663 static inline void cpu_set_pc(CPUState *cpu, vaddr addr)
 664 {
 665     CPUClass *cc = CPU_GET_CLASS(cpu);
 666
 667     cc->set_pc(cpu, addr);
 668 }
 669
 670 /**
 671  * cpu_reset_interrupt:
 672  * @cpu: The CPU to clear the interrupt on.
 673  * @mask: The interrupt mask to clear.
 674  *
 675  * Resets interrupts on the vCPU @cpu.
 676  */
 677 void cpu_reset_interrupt(CPUState *cpu, int mask);
 678
 679 /**
 680  * cpu_exit:
 681  * @cpu: The CPU to exit.
 682  *
 683  * Requests the CPU @cpu to exit execution.
 684  */
 685 void cpu_exit(CPUState *cpu);
 686
 687 /**
 688  * cpu_resume:
 689  * @cpu: The CPU to resume.
 690  *
 691  * Resumes CPU, i.e. puts CPU into runnable state.
 692  */
 693 void cpu_resume(CPUState *cpu);
 694
 695 /**
 696  * qemu_init_vcpu:
 697  * @cpu: The vCPU to initialize.
 698  *
 699  * Initializes a vCPU.
 700  */
 701 void qemu_init_vcpu(CPUState *cpu);
 702
 703 #define SSTEP_ENABLE  0x1  /* Enable simulated HW single stepping */
 704 #define SSTEP_NOIRQ   0x2  /* Do not use IRQ while single stepping */
 705 #define SSTEP_NOTIMER 0x4  /* Do not Timers while single stepping */
 706
 707 /**
 708  * cpu_single_step:
 709  * @cpu: CPU to the flags for.
 710  * @enabled: Flags to enable.
 711  *
 712  * Enables or disables single-stepping for @cpu.
 713  */
 714 void cpu_single_step(CPUState *cpu, int enabled);
 715
 716 /* Breakpoint/watchpoint flags */
 717 #define BP_MEM_READ           0x01
 718 #define BP_MEM_WRITE          0x02
 719 #define BP_MEM_ACCESS         (BP_MEM_READ | BP_MEM_WRITE)
 720 #define BP_STOP_BEFORE_ACCESS 0x04
 721 /* 0x08 currently unused */
 722 #define BP_GDB                0x10
 723 #define BP_CPU                0x20
 724 #define BP_ANY                (BP_GDB | BP_CPU)
 725 #define BP_WATCHPOINT_HIT_READ 0x40
 726 #define BP_WATCHPOINT_HIT_WRITE 0x80
 727 #define BP_WATCHPOINT_HIT (BP_WATCHPOINT_HIT_READ | BP_WATCHPOINT_HIT_WRITE)
 728
 729 int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags,
 730                           CPUBreakpoint **breakpoint);
 731 int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags);
 732 void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *breakpoint);
 733 void cpu_breakpoint_remove_all(CPUState *cpu, int mask);
 734
 735 /* Return true if PC matches an installed breakpoint.  */
 736 static inline bool cpu_breakpoint_test(CPUState *cpu, vaddr pc, int mask)
 737 {
 738     CPUBreakpoint *bp;
 739
 740     if (unlikely(!QTAILQ_EMPTY(&cpu->breakpoints))) {
 741         QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
 742             if (bp->pc == pc && (bp->flags & mask)) {
 743                 return true;
 744             }
 745         }
 746     }
 747     return false;
 748 }
 749
 750 int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len,
 751                           int flags, CPUWatchpoint **watchpoint);
 752 int cpu_watchpoint_remove(CPUState *cpu, vaddr addr,
 753                           vaddr len, int flags);
 754 void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint);
 755 void cpu_watchpoint_remove_all(CPUState *cpu, int mask);
 756
 757 void QEMU_NORETURN cpu_abort(CPUState *cpu, const char *fmt, ...)
 758     GCC_FMT_ATTR(2, 3);
 759 void cpu_exec_exit(CPUState *cpu);
 760
 761 #ifdef CONFIG_SOFTMMU
 762 extern const struct VMStateDescription vmstate_cpu_common;
 763 #else
 764 #define vmstate_cpu_common vmstate_dummy
 765 #endif
 766
 767 #define VMSTATE_CPU() {                                                     \
 768     .name = "parent_obj",                                                   \
 769     .size = sizeof(CPUState),                                               \
 770     .vmsd = &vmstate_cpu_common,                                            \
 771     .flags = VMS_STRUCT,                                                    \
 772     .offset = 0,                                                            \
 773 }
 774
 775 #endif