4 * Copyright (c) 2003 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 #include "qemu/osdep.h"
25 #include "qapi/error.h"
28 #include "ui/console.h"
29 #include "hw/i386/pc.h"
30 #include "hw/pci/pci.h"
32 #include "ui/pixel_ops.h"
33 #include "qemu/timer.h"
34 #include "hw/xen/xen.h"
37 //#define DEBUG_VGA_MEM
38 //#define DEBUG_VGA_REG
40 /* 16 state changes per vertical frame @60 Hz */
41 #define VGA_TEXT_CURSOR_PERIOD_MS (1000 * 2 * 16 / 60)
44 * Video Graphics Array (VGA)
46 * Chipset docs for original IBM VGA:
47 * http://www.mcamafia.de/pdf/ibm_vgaxga_trm2.pdf
50 * http://www.osdever.net/FreeVGA/home.htm
52 * Standard VGA features and Bochs VBE extensions are implemented.
55 /* force some bits to zero */
56 const uint8_t sr_mask
[8] = {
67 const uint8_t gr_mask
[16] = {
86 #define cbswap_32(__x) \
88 (((uint32_t)(__x) & (uint32_t)0x000000ffUL) << 24) | \
89 (((uint32_t)(__x) & (uint32_t)0x0000ff00UL) << 8) | \
90 (((uint32_t)(__x) & (uint32_t)0x00ff0000UL) >> 8) | \
91 (((uint32_t)(__x) & (uint32_t)0xff000000UL) >> 24) ))
93 #ifdef HOST_WORDS_BIGENDIAN
94 #define PAT(x) cbswap_32(x)
99 #ifdef HOST_WORDS_BIGENDIAN
105 #ifdef HOST_WORDS_BIGENDIAN
106 #define GET_PLANE(data, p) (((data) >> (24 - (p) * 8)) & 0xff)
108 #define GET_PLANE(data, p) (((data) >> ((p) * 8)) & 0xff)
111 static const uint32_t mask16
[16] = {
132 #ifdef HOST_WORDS_BIGENDIAN
135 #define PAT(x) cbswap_32(x)
138 static uint32_t expand4
[256];
139 static uint16_t expand2
[256];
140 static uint8_t expand4to8
[16];
142 static void vbe_update_vgaregs(VGACommonState
*s
);
144 static inline bool vbe_enabled(VGACommonState
*s
)
146 return s
->vbe_regs
[VBE_DISPI_INDEX_ENABLE
] & VBE_DISPI_ENABLED
;
149 static inline uint8_t sr(VGACommonState
*s
, int idx
)
151 return vbe_enabled(s
) ? s
->sr_vbe
[idx
] : s
->sr
[idx
];
154 static void vga_update_memory_access(VGACommonState
*s
)
156 hwaddr base
, offset
, size
;
158 if (s
->legacy_address_space
== NULL
) {
162 if (s
->has_chain4_alias
) {
163 memory_region_del_subregion(s
->legacy_address_space
, &s
->chain4_alias
);
164 object_unparent(OBJECT(&s
->chain4_alias
));
165 s
->has_chain4_alias
= false;
166 s
->plane_updated
= 0xf;
168 if ((sr(s
, VGA_SEQ_PLANE_WRITE
) & VGA_SR02_ALL_PLANES
) ==
169 VGA_SR02_ALL_PLANES
&& sr(s
, VGA_SEQ_MEMORY_MODE
) & VGA_SR04_CHN_4M
) {
171 switch ((s
->gr
[VGA_GFX_MISC
] >> 2) & 3) {
179 offset
= s
->bank_offset
;
191 assert(offset
+ size
<= s
->vram_size
);
192 memory_region_init_alias(&s
->chain4_alias
, memory_region_owner(&s
->vram
),
193 "vga.chain4", &s
->vram
, offset
, size
);
194 memory_region_add_subregion_overlap(s
->legacy_address_space
, base
,
195 &s
->chain4_alias
, 2);
196 s
->has_chain4_alias
= true;
200 static void vga_dumb_update_retrace_info(VGACommonState
*s
)
205 static void vga_precise_update_retrace_info(VGACommonState
*s
)
208 int hretr_start_char
;
209 int hretr_skew_chars
;
213 int vretr_start_line
;
222 const int clk_hz
[] = {25175000, 28322000, 25175000, 25175000};
223 int64_t chars_per_sec
;
224 struct vga_precise_retrace
*r
= &s
->retrace_info
.precise
;
226 htotal_chars
= s
->cr
[VGA_CRTC_H_TOTAL
] + 5;
227 hretr_start_char
= s
->cr
[VGA_CRTC_H_SYNC_START
];
228 hretr_skew_chars
= (s
->cr
[VGA_CRTC_H_SYNC_END
] >> 5) & 3;
229 hretr_end_char
= s
->cr
[VGA_CRTC_H_SYNC_END
] & 0x1f;
231 vtotal_lines
= (s
->cr
[VGA_CRTC_V_TOTAL
] |
232 (((s
->cr
[VGA_CRTC_OVERFLOW
] & 1) |
233 ((s
->cr
[VGA_CRTC_OVERFLOW
] >> 4) & 2)) << 8)) + 2;
234 vretr_start_line
= s
->cr
[VGA_CRTC_V_SYNC_START
] |
235 ((((s
->cr
[VGA_CRTC_OVERFLOW
] >> 2) & 1) |
236 ((s
->cr
[VGA_CRTC_OVERFLOW
] >> 6) & 2)) << 8);
237 vretr_end_line
= s
->cr
[VGA_CRTC_V_SYNC_END
] & 0xf;
239 clocking_mode
= (sr(s
, VGA_SEQ_CLOCK_MODE
) >> 3) & 1;
240 clock_sel
= (s
->msr
>> 2) & 3;
241 dots
= (s
->msr
& 1) ? 8 : 9;
243 chars_per_sec
= clk_hz
[clock_sel
] / dots
;
245 htotal_chars
<<= clocking_mode
;
247 r
->total_chars
= vtotal_lines
* htotal_chars
;
249 r
->ticks_per_char
= NANOSECONDS_PER_SECOND
/ (r
->total_chars
* r
->freq
);
251 r
->ticks_per_char
= NANOSECONDS_PER_SECOND
/ chars_per_sec
;
254 r
->vstart
= vretr_start_line
;
255 r
->vend
= r
->vstart
+ vretr_end_line
+ 1;
257 r
->hstart
= hretr_start_char
+ hretr_skew_chars
;
258 r
->hend
= r
->hstart
+ hretr_end_char
+ 1;
259 r
->htotal
= htotal_chars
;
262 div2
= (s
->cr
[VGA_CRTC_MODE
] >> 2) & 1;
263 sldiv2
= (s
->cr
[VGA_CRTC_MODE
] >> 3) & 1;
273 "div2 = %d sldiv2 = %d\n"
274 "clocking_mode = %d\n"
275 "clock_sel = %d %d\n"
277 "ticks/char = %" PRId64
"\n"
279 (double) NANOSECONDS_PER_SECOND
/ (r
->ticks_per_char
* r
->total_chars
),
297 static uint8_t vga_precise_retrace(VGACommonState
*s
)
299 struct vga_precise_retrace
*r
= &s
->retrace_info
.precise
;
300 uint8_t val
= s
->st01
& ~(ST01_V_RETRACE
| ST01_DISP_ENABLE
);
302 if (r
->total_chars
) {
303 int cur_line
, cur_line_char
, cur_char
;
306 cur_tick
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
308 cur_char
= (cur_tick
/ r
->ticks_per_char
) % r
->total_chars
;
309 cur_line
= cur_char
/ r
->htotal
;
311 if (cur_line
>= r
->vstart
&& cur_line
<= r
->vend
) {
312 val
|= ST01_V_RETRACE
| ST01_DISP_ENABLE
;
314 cur_line_char
= cur_char
% r
->htotal
;
315 if (cur_line_char
>= r
->hstart
&& cur_line_char
<= r
->hend
) {
316 val
|= ST01_DISP_ENABLE
;
322 return s
->st01
^ (ST01_V_RETRACE
| ST01_DISP_ENABLE
);
326 static uint8_t vga_dumb_retrace(VGACommonState
*s
)
328 return s
->st01
^ (ST01_V_RETRACE
| ST01_DISP_ENABLE
);
331 int vga_ioport_invalid(VGACommonState
*s
, uint32_t addr
)
333 if (s
->msr
& VGA_MIS_COLOR
) {
335 return (addr
>= 0x3b0 && addr
<= 0x3bf);
338 return (addr
>= 0x3d0 && addr
<= 0x3df);
342 uint32_t vga_ioport_read(void *opaque
, uint32_t addr
)
344 VGACommonState
*s
= opaque
;
347 if (vga_ioport_invalid(s
, addr
)) {
352 if (s
->ar_flip_flop
== 0) {
359 index
= s
->ar_index
& 0x1f;
360 if (index
< VGA_ATT_C
) {
373 val
= s
->sr
[s
->sr_index
];
375 printf("vga: read SR%x = 0x%02x\n", s
->sr_index
, val
);
382 val
= s
->dac_write_index
;
385 val
= s
->palette
[s
->dac_read_index
* 3 + s
->dac_sub_index
];
386 if (++s
->dac_sub_index
== 3) {
387 s
->dac_sub_index
= 0;
401 val
= s
->gr
[s
->gr_index
];
403 printf("vga: read GR%x = 0x%02x\n", s
->gr_index
, val
);
412 val
= s
->cr
[s
->cr_index
];
414 printf("vga: read CR%x = 0x%02x\n", s
->cr_index
, val
);
419 /* just toggle to fool polling */
420 val
= s
->st01
= s
->retrace(s
);
428 trace_vga_std_read_io(addr
, val
);
432 void vga_ioport_write(void *opaque
, uint32_t addr
, uint32_t val
)
434 VGACommonState
*s
= opaque
;
437 /* check port range access depending on color/monochrome mode */
438 if (vga_ioport_invalid(s
, addr
)) {
441 trace_vga_std_write_io(addr
, val
);
445 if (s
->ar_flip_flop
== 0) {
449 index
= s
->ar_index
& 0x1f;
451 case VGA_ATC_PALETTE0
... VGA_ATC_PALETTEF
:
452 s
->ar
[index
] = val
& 0x3f;
455 s
->ar
[index
] = val
& ~0x10;
457 case VGA_ATC_OVERSCAN
:
460 case VGA_ATC_PLANE_ENABLE
:
461 s
->ar
[index
] = val
& ~0xc0;
464 s
->ar
[index
] = val
& ~0xf0;
466 case VGA_ATC_COLOR_PAGE
:
467 s
->ar
[index
] = val
& ~0xf0;
473 s
->ar_flip_flop
^= 1;
476 s
->msr
= val
& ~0x10;
477 s
->update_retrace_info(s
);
480 s
->sr_index
= val
& 7;
484 printf("vga: write SR%x = 0x%02x\n", s
->sr_index
, val
);
486 s
->sr
[s
->sr_index
] = val
& sr_mask
[s
->sr_index
];
487 if (s
->sr_index
== VGA_SEQ_CLOCK_MODE
) {
488 s
->update_retrace_info(s
);
490 vga_update_memory_access(s
);
493 s
->dac_read_index
= val
;
494 s
->dac_sub_index
= 0;
498 s
->dac_write_index
= val
;
499 s
->dac_sub_index
= 0;
503 s
->dac_cache
[s
->dac_sub_index
] = val
;
504 if (++s
->dac_sub_index
== 3) {
505 memcpy(&s
->palette
[s
->dac_write_index
* 3], s
->dac_cache
, 3);
506 s
->dac_sub_index
= 0;
507 s
->dac_write_index
++;
511 s
->gr_index
= val
& 0x0f;
515 printf("vga: write GR%x = 0x%02x\n", s
->gr_index
, val
);
517 s
->gr
[s
->gr_index
] = val
& gr_mask
[s
->gr_index
];
518 vbe_update_vgaregs(s
);
519 vga_update_memory_access(s
);
528 printf("vga: write CR%x = 0x%02x\n", s
->cr_index
, val
);
530 /* handle CR0-7 protection */
531 if ((s
->cr
[VGA_CRTC_V_SYNC_END
] & VGA_CR11_LOCK_CR0_CR7
) &&
532 s
->cr_index
<= VGA_CRTC_OVERFLOW
) {
533 /* can always write bit 4 of CR7 */
534 if (s
->cr_index
== VGA_CRTC_OVERFLOW
) {
535 s
->cr
[VGA_CRTC_OVERFLOW
] = (s
->cr
[VGA_CRTC_OVERFLOW
] & ~0x10) |
537 vbe_update_vgaregs(s
);
541 s
->cr
[s
->cr_index
] = val
;
542 vbe_update_vgaregs(s
);
544 switch(s
->cr_index
) {
545 case VGA_CRTC_H_TOTAL
:
546 case VGA_CRTC_H_SYNC_START
:
547 case VGA_CRTC_H_SYNC_END
:
548 case VGA_CRTC_V_TOTAL
:
549 case VGA_CRTC_OVERFLOW
:
550 case VGA_CRTC_V_SYNC_END
:
552 s
->update_retrace_info(s
);
564 * Sanity check vbe register writes.
566 * As we don't have a way to signal errors to the guest in the bochs
567 * dispi interface we'll go adjust the registers to the closest valid
570 static void vbe_fixup_regs(VGACommonState
*s
)
572 uint16_t *r
= s
->vbe_regs
;
573 uint32_t bits
, linelength
, maxy
, offset
;
575 if (!vbe_enabled(s
)) {
576 /* vbe is turned off -- nothing to do */
581 switch (r
[VBE_DISPI_INDEX_BPP
]) {
587 bits
= r
[VBE_DISPI_INDEX_BPP
];
593 bits
= r
[VBE_DISPI_INDEX_BPP
] = 8;
598 r
[VBE_DISPI_INDEX_XRES
] &= ~7u;
599 if (r
[VBE_DISPI_INDEX_XRES
] == 0) {
600 r
[VBE_DISPI_INDEX_XRES
] = 8;
602 if (r
[VBE_DISPI_INDEX_XRES
] > VBE_DISPI_MAX_XRES
) {
603 r
[VBE_DISPI_INDEX_XRES
] = VBE_DISPI_MAX_XRES
;
605 r
[VBE_DISPI_INDEX_VIRT_WIDTH
] &= ~7u;
606 if (r
[VBE_DISPI_INDEX_VIRT_WIDTH
] > VBE_DISPI_MAX_XRES
) {
607 r
[VBE_DISPI_INDEX_VIRT_WIDTH
] = VBE_DISPI_MAX_XRES
;
609 if (r
[VBE_DISPI_INDEX_VIRT_WIDTH
] < r
[VBE_DISPI_INDEX_XRES
]) {
610 r
[VBE_DISPI_INDEX_VIRT_WIDTH
] = r
[VBE_DISPI_INDEX_XRES
];
614 linelength
= r
[VBE_DISPI_INDEX_VIRT_WIDTH
] * bits
/ 8;
615 maxy
= s
->vbe_size
/ linelength
;
616 if (r
[VBE_DISPI_INDEX_YRES
] == 0) {
617 r
[VBE_DISPI_INDEX_YRES
] = 1;
619 if (r
[VBE_DISPI_INDEX_YRES
] > VBE_DISPI_MAX_YRES
) {
620 r
[VBE_DISPI_INDEX_YRES
] = VBE_DISPI_MAX_YRES
;
622 if (r
[VBE_DISPI_INDEX_YRES
] > maxy
) {
623 r
[VBE_DISPI_INDEX_YRES
] = maxy
;
627 if (r
[VBE_DISPI_INDEX_X_OFFSET
] > VBE_DISPI_MAX_XRES
) {
628 r
[VBE_DISPI_INDEX_X_OFFSET
] = VBE_DISPI_MAX_XRES
;
630 if (r
[VBE_DISPI_INDEX_Y_OFFSET
] > VBE_DISPI_MAX_YRES
) {
631 r
[VBE_DISPI_INDEX_Y_OFFSET
] = VBE_DISPI_MAX_YRES
;
633 offset
= r
[VBE_DISPI_INDEX_X_OFFSET
] * bits
/ 8;
634 offset
+= r
[VBE_DISPI_INDEX_Y_OFFSET
] * linelength
;
635 if (offset
+ r
[VBE_DISPI_INDEX_YRES
] * linelength
> s
->vbe_size
) {
636 r
[VBE_DISPI_INDEX_Y_OFFSET
] = 0;
637 offset
= r
[VBE_DISPI_INDEX_X_OFFSET
] * bits
/ 8;
638 if (offset
+ r
[VBE_DISPI_INDEX_YRES
] * linelength
> s
->vbe_size
) {
639 r
[VBE_DISPI_INDEX_X_OFFSET
] = 0;
644 /* update vga state */
645 r
[VBE_DISPI_INDEX_VIRT_HEIGHT
] = maxy
;
646 s
->vbe_line_offset
= linelength
;
647 s
->vbe_start_addr
= offset
/ 4;
650 /* we initialize the VGA graphic mode */
651 static void vbe_update_vgaregs(VGACommonState
*s
)
653 int h
, shift_control
;
655 if (!vbe_enabled(s
)) {
656 /* vbe is turned off -- nothing to do */
660 /* graphic mode + memory map 1 */
661 s
->gr
[VGA_GFX_MISC
] = (s
->gr
[VGA_GFX_MISC
] & ~0x0c) | 0x04 |
662 VGA_GR06_GRAPHICS_MODE
;
663 s
->cr
[VGA_CRTC_MODE
] |= 3; /* no CGA modes */
664 s
->cr
[VGA_CRTC_OFFSET
] = s
->vbe_line_offset
>> 3;
666 s
->cr
[VGA_CRTC_H_DISP
] =
667 (s
->vbe_regs
[VBE_DISPI_INDEX_XRES
] >> 3) - 1;
668 /* height (only meaningful if < 1024) */
669 h
= s
->vbe_regs
[VBE_DISPI_INDEX_YRES
] - 1;
670 s
->cr
[VGA_CRTC_V_DISP_END
] = h
;
671 s
->cr
[VGA_CRTC_OVERFLOW
] = (s
->cr
[VGA_CRTC_OVERFLOW
] & ~0x42) |
672 ((h
>> 7) & 0x02) | ((h
>> 3) & 0x40);
673 /* line compare to 1023 */
674 s
->cr
[VGA_CRTC_LINE_COMPARE
] = 0xff;
675 s
->cr
[VGA_CRTC_OVERFLOW
] |= 0x10;
676 s
->cr
[VGA_CRTC_MAX_SCAN
] |= 0x40;
678 if (s
->vbe_regs
[VBE_DISPI_INDEX_BPP
] == 4) {
680 s
->sr_vbe
[VGA_SEQ_CLOCK_MODE
] &= ~8; /* no double line */
683 /* set chain 4 mode */
684 s
->sr_vbe
[VGA_SEQ_MEMORY_MODE
] |= VGA_SR04_CHN_4M
;
685 /* activate all planes */
686 s
->sr_vbe
[VGA_SEQ_PLANE_WRITE
] |= VGA_SR02_ALL_PLANES
;
688 s
->gr
[VGA_GFX_MODE
] = (s
->gr
[VGA_GFX_MODE
] & ~0x60) |
689 (shift_control
<< 5);
690 s
->cr
[VGA_CRTC_MAX_SCAN
] &= ~0x9f; /* no double scan */
693 static uint32_t vbe_ioport_read_index(void *opaque
, uint32_t addr
)
695 VGACommonState
*s
= opaque
;
699 uint32_t vbe_ioport_read_data(void *opaque
, uint32_t addr
)
701 VGACommonState
*s
= opaque
;
704 if (s
->vbe_index
< VBE_DISPI_INDEX_NB
) {
705 if (s
->vbe_regs
[VBE_DISPI_INDEX_ENABLE
] & VBE_DISPI_GETCAPS
) {
706 switch(s
->vbe_index
) {
707 /* XXX: do not hardcode ? */
708 case VBE_DISPI_INDEX_XRES
:
709 val
= VBE_DISPI_MAX_XRES
;
711 case VBE_DISPI_INDEX_YRES
:
712 val
= VBE_DISPI_MAX_YRES
;
714 case VBE_DISPI_INDEX_BPP
:
715 val
= VBE_DISPI_MAX_BPP
;
718 val
= s
->vbe_regs
[s
->vbe_index
];
722 val
= s
->vbe_regs
[s
->vbe_index
];
724 } else if (s
->vbe_index
== VBE_DISPI_INDEX_VIDEO_MEMORY_64K
) {
725 val
= s
->vbe_size
/ (64 * 1024);
729 trace_vga_vbe_read(s
->vbe_index
, val
);
733 void vbe_ioport_write_index(void *opaque
, uint32_t addr
, uint32_t val
)
735 VGACommonState
*s
= opaque
;
739 void vbe_ioport_write_data(void *opaque
, uint32_t addr
, uint32_t val
)
741 VGACommonState
*s
= opaque
;
743 if (s
->vbe_index
<= VBE_DISPI_INDEX_NB
) {
744 trace_vga_vbe_write(s
->vbe_index
, val
);
745 switch(s
->vbe_index
) {
746 case VBE_DISPI_INDEX_ID
:
747 if (val
== VBE_DISPI_ID0
||
748 val
== VBE_DISPI_ID1
||
749 val
== VBE_DISPI_ID2
||
750 val
== VBE_DISPI_ID3
||
751 val
== VBE_DISPI_ID4
) {
752 s
->vbe_regs
[s
->vbe_index
] = val
;
755 case VBE_DISPI_INDEX_XRES
:
756 case VBE_DISPI_INDEX_YRES
:
757 case VBE_DISPI_INDEX_BPP
:
758 case VBE_DISPI_INDEX_VIRT_WIDTH
:
759 case VBE_DISPI_INDEX_X_OFFSET
:
760 case VBE_DISPI_INDEX_Y_OFFSET
:
761 s
->vbe_regs
[s
->vbe_index
] = val
;
763 vbe_update_vgaregs(s
);
765 case VBE_DISPI_INDEX_BANK
:
766 val
&= s
->vbe_bank_mask
;
767 s
->vbe_regs
[s
->vbe_index
] = val
;
768 s
->bank_offset
= (val
<< 16);
769 vga_update_memory_access(s
);
771 case VBE_DISPI_INDEX_ENABLE
:
772 if ((val
& VBE_DISPI_ENABLED
) &&
773 !(s
->vbe_regs
[VBE_DISPI_INDEX_ENABLE
] & VBE_DISPI_ENABLED
)) {
775 s
->vbe_regs
[VBE_DISPI_INDEX_VIRT_WIDTH
] = 0;
776 s
->vbe_regs
[VBE_DISPI_INDEX_X_OFFSET
] = 0;
777 s
->vbe_regs
[VBE_DISPI_INDEX_Y_OFFSET
] = 0;
778 s
->vbe_regs
[VBE_DISPI_INDEX_ENABLE
] |= VBE_DISPI_ENABLED
;
780 vbe_update_vgaregs(s
);
782 /* clear the screen */
783 if (!(val
& VBE_DISPI_NOCLEARMEM
)) {
784 memset(s
->vram_ptr
, 0,
785 s
->vbe_regs
[VBE_DISPI_INDEX_YRES
] * s
->vbe_line_offset
);
790 s
->dac_8bit
= (val
& VBE_DISPI_8BIT_DAC
) > 0;
791 s
->vbe_regs
[s
->vbe_index
] = val
;
792 vga_update_memory_access(s
);
800 /* called for accesses between 0xa0000 and 0xc0000 */
801 uint32_t vga_mem_readb(VGACommonState
*s
, hwaddr addr
)
803 int memory_map_mode
, plane
;
806 /* convert to VGA memory offset */
807 memory_map_mode
= (s
->gr
[VGA_GFX_MISC
] >> 2) & 3;
809 switch(memory_map_mode
) {
815 addr
+= s
->bank_offset
;
830 if (sr(s
, VGA_SEQ_MEMORY_MODE
) & VGA_SR04_CHN_4M
) {
831 /* chain 4 mode : simplest access */
832 assert(addr
< s
->vram_size
);
833 ret
= s
->vram_ptr
[addr
];
834 } else if (s
->gr
[VGA_GFX_MODE
] & 0x10) {
835 /* odd/even mode (aka text mode mapping) */
836 plane
= (s
->gr
[VGA_GFX_PLANE_READ
] & 2) | (addr
& 1);
837 addr
= ((addr
& ~1) << 1) | plane
;
838 if (addr
>= s
->vram_size
) {
841 ret
= s
->vram_ptr
[addr
];
843 /* standard VGA latched access */
844 if (addr
* sizeof(uint32_t) >= s
->vram_size
) {
847 s
->latch
= ((uint32_t *)s
->vram_ptr
)[addr
];
849 if (!(s
->gr
[VGA_GFX_MODE
] & 0x08)) {
851 plane
= s
->gr
[VGA_GFX_PLANE_READ
];
852 ret
= GET_PLANE(s
->latch
, plane
);
855 ret
= (s
->latch
^ mask16
[s
->gr
[VGA_GFX_COMPARE_VALUE
]]) &
856 mask16
[s
->gr
[VGA_GFX_COMPARE_MASK
]];
865 /* called for accesses between 0xa0000 and 0xc0000 */
866 void vga_mem_writeb(VGACommonState
*s
, hwaddr addr
, uint32_t val
)
868 int memory_map_mode
, plane
, write_mode
, b
, func_select
, mask
;
869 uint32_t write_mask
, bit_mask
, set_mask
;
872 printf("vga: [0x" TARGET_FMT_plx
"] = 0x%02x\n", addr
, val
);
874 /* convert to VGA memory offset */
875 memory_map_mode
= (s
->gr
[VGA_GFX_MISC
] >> 2) & 3;
877 switch(memory_map_mode
) {
883 addr
+= s
->bank_offset
;
898 if (sr(s
, VGA_SEQ_MEMORY_MODE
) & VGA_SR04_CHN_4M
) {
899 /* chain 4 mode : simplest access */
902 if (sr(s
, VGA_SEQ_PLANE_WRITE
) & mask
) {
903 assert(addr
< s
->vram_size
);
904 s
->vram_ptr
[addr
] = val
;
906 printf("vga: chain4: [0x" TARGET_FMT_plx
"]\n", addr
);
908 s
->plane_updated
|= mask
; /* only used to detect font change */
909 memory_region_set_dirty(&s
->vram
, addr
, 1);
911 } else if (s
->gr
[VGA_GFX_MODE
] & 0x10) {
912 /* odd/even mode (aka text mode mapping) */
913 plane
= (s
->gr
[VGA_GFX_PLANE_READ
] & 2) | (addr
& 1);
915 if (sr(s
, VGA_SEQ_PLANE_WRITE
) & mask
) {
916 addr
= ((addr
& ~1) << 1) | plane
;
917 if (addr
>= s
->vram_size
) {
920 s
->vram_ptr
[addr
] = val
;
922 printf("vga: odd/even: [0x" TARGET_FMT_plx
"]\n", addr
);
924 s
->plane_updated
|= mask
; /* only used to detect font change */
925 memory_region_set_dirty(&s
->vram
, addr
, 1);
928 /* standard VGA latched access */
929 write_mode
= s
->gr
[VGA_GFX_MODE
] & 3;
934 b
= s
->gr
[VGA_GFX_DATA_ROTATE
] & 7;
935 val
= ((val
>> b
) | (val
<< (8 - b
))) & 0xff;
939 /* apply set/reset mask */
940 set_mask
= mask16
[s
->gr
[VGA_GFX_SR_ENABLE
]];
941 val
= (val
& ~set_mask
) |
942 (mask16
[s
->gr
[VGA_GFX_SR_VALUE
]] & set_mask
);
943 bit_mask
= s
->gr
[VGA_GFX_BIT_MASK
];
949 val
= mask16
[val
& 0x0f];
950 bit_mask
= s
->gr
[VGA_GFX_BIT_MASK
];
954 b
= s
->gr
[VGA_GFX_DATA_ROTATE
] & 7;
955 val
= (val
>> b
) | (val
<< (8 - b
));
957 bit_mask
= s
->gr
[VGA_GFX_BIT_MASK
] & val
;
958 val
= mask16
[s
->gr
[VGA_GFX_SR_VALUE
]];
962 /* apply logical operation */
963 func_select
= s
->gr
[VGA_GFX_DATA_ROTATE
] >> 3;
964 switch(func_select
) {
984 bit_mask
|= bit_mask
<< 8;
985 bit_mask
|= bit_mask
<< 16;
986 val
= (val
& bit_mask
) | (s
->latch
& ~bit_mask
);
989 /* mask data according to sr[2] */
990 mask
= sr(s
, VGA_SEQ_PLANE_WRITE
);
991 s
->plane_updated
|= mask
; /* only used to detect font change */
992 write_mask
= mask16
[mask
];
993 if (addr
* sizeof(uint32_t) >= s
->vram_size
) {
996 ((uint32_t *)s
->vram_ptr
)[addr
] =
997 (((uint32_t *)s
->vram_ptr
)[addr
] & ~write_mask
) |
1000 printf("vga: latch: [0x" TARGET_FMT_plx
"] mask=0x%08x val=0x%08x\n",
1001 addr
* 4, write_mask
, val
);
1003 memory_region_set_dirty(&s
->vram
, addr
<< 2, sizeof(uint32_t));
1007 typedef void vga_draw_line_func(VGACommonState
*s1
, uint8_t *d
,
1008 const uint8_t *s
, int width
);
1010 #include "vga-helpers.h"
1012 /* return true if the palette was modified */
1013 static int update_palette16(VGACommonState
*s
)
1016 uint32_t v
, col
, *palette
;
1019 palette
= s
->last_palette
;
1020 for(i
= 0; i
< 16; i
++) {
1022 if (s
->ar
[VGA_ATC_MODE
] & 0x80) {
1023 v
= ((s
->ar
[VGA_ATC_COLOR_PAGE
] & 0xf) << 4) | (v
& 0xf);
1025 v
= ((s
->ar
[VGA_ATC_COLOR_PAGE
] & 0xc) << 4) | (v
& 0x3f);
1028 col
= rgb_to_pixel32(c6_to_8(s
->palette
[v
]),
1029 c6_to_8(s
->palette
[v
+ 1]),
1030 c6_to_8(s
->palette
[v
+ 2]));
1031 if (col
!= palette
[i
]) {
1039 /* return true if the palette was modified */
1040 static int update_palette256(VGACommonState
*s
)
1043 uint32_t v
, col
, *palette
;
1046 palette
= s
->last_palette
;
1048 for(i
= 0; i
< 256; i
++) {
1050 col
= rgb_to_pixel32(s
->palette
[v
],
1054 col
= rgb_to_pixel32(c6_to_8(s
->palette
[v
]),
1055 c6_to_8(s
->palette
[v
+ 1]),
1056 c6_to_8(s
->palette
[v
+ 2]));
1058 if (col
!= palette
[i
]) {
1067 static void vga_get_offsets(VGACommonState
*s
,
1068 uint32_t *pline_offset
,
1069 uint32_t *pstart_addr
,
1070 uint32_t *pline_compare
)
1072 uint32_t start_addr
, line_offset
, line_compare
;
1074 if (vbe_enabled(s
)) {
1075 line_offset
= s
->vbe_line_offset
;
1076 start_addr
= s
->vbe_start_addr
;
1077 line_compare
= 65535;
1079 /* compute line_offset in bytes */
1080 line_offset
= s
->cr
[VGA_CRTC_OFFSET
];
1083 /* starting address */
1084 start_addr
= s
->cr
[VGA_CRTC_START_LO
] |
1085 (s
->cr
[VGA_CRTC_START_HI
] << 8);
1088 line_compare
= s
->cr
[VGA_CRTC_LINE_COMPARE
] |
1089 ((s
->cr
[VGA_CRTC_OVERFLOW
] & 0x10) << 4) |
1090 ((s
->cr
[VGA_CRTC_MAX_SCAN
] & 0x40) << 3);
1092 *pline_offset
= line_offset
;
1093 *pstart_addr
= start_addr
;
1094 *pline_compare
= line_compare
;
1097 /* update start_addr and line_offset. Return TRUE if modified */
1098 static int update_basic_params(VGACommonState
*s
)
1101 uint32_t start_addr
, line_offset
, line_compare
;
1105 s
->get_offsets(s
, &line_offset
, &start_addr
, &line_compare
);
1107 if (line_offset
!= s
->line_offset
||
1108 start_addr
!= s
->start_addr
||
1109 line_compare
!= s
->line_compare
) {
1110 s
->line_offset
= line_offset
;
1111 s
->start_addr
= start_addr
;
1112 s
->line_compare
= line_compare
;
1119 static const uint8_t cursor_glyph
[32 * 4] = {
1120 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1121 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1122 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1123 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1124 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1125 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1126 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1127 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1128 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1129 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1130 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1131 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1132 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1133 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1134 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1135 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1138 static void vga_get_text_resolution(VGACommonState
*s
, int *pwidth
, int *pheight
,
1139 int *pcwidth
, int *pcheight
)
1141 int width
, cwidth
, height
, cheight
;
1143 /* total width & height */
1144 cheight
= (s
->cr
[VGA_CRTC_MAX_SCAN
] & 0x1f) + 1;
1146 if (!(sr(s
, VGA_SEQ_CLOCK_MODE
) & VGA_SR01_CHAR_CLK_8DOTS
)) {
1149 if (sr(s
, VGA_SEQ_CLOCK_MODE
) & 0x08) {
1150 cwidth
= 16; /* NOTE: no 18 pixel wide */
1152 width
= (s
->cr
[VGA_CRTC_H_DISP
] + 1);
1153 if (s
->cr
[VGA_CRTC_V_TOTAL
] == 100) {
1154 /* ugly hack for CGA 160x100x16 - explain me the logic */
1157 height
= s
->cr
[VGA_CRTC_V_DISP_END
] |
1158 ((s
->cr
[VGA_CRTC_OVERFLOW
] & 0x02) << 7) |
1159 ((s
->cr
[VGA_CRTC_OVERFLOW
] & 0x40) << 3);
1160 height
= (height
+ 1) / cheight
;
1166 *pcheight
= cheight
;
1177 static void vga_draw_text(VGACommonState
*s
, int full_update
)
1179 DisplaySurface
*surface
= qemu_console_surface(s
->con
);
1180 int cx
, cy
, cheight
, cw
, ch
, cattr
, height
, width
, ch_attr
;
1181 int cx_min
, cx_max
, linesize
, x_incr
, line
, line1
;
1182 uint32_t offset
, fgcol
, bgcol
, v
, cursor_offset
;
1183 uint8_t *d1
, *d
, *src
, *dest
, *cursor_ptr
;
1184 const uint8_t *font_ptr
, *font_base
[2];
1185 int dup9
, line_offset
;
1187 uint32_t *ch_attr_ptr
;
1188 int64_t now
= qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL
);
1190 /* compute font data address (in plane 2) */
1191 v
= sr(s
, VGA_SEQ_CHARACTER_MAP
);
1192 offset
= (((v
>> 4) & 1) | ((v
<< 1) & 6)) * 8192 * 4 + 2;
1193 if (offset
!= s
->font_offsets
[0]) {
1194 s
->font_offsets
[0] = offset
;
1197 font_base
[0] = s
->vram_ptr
+ offset
;
1199 offset
= (((v
>> 5) & 1) | ((v
>> 1) & 6)) * 8192 * 4 + 2;
1200 font_base
[1] = s
->vram_ptr
+ offset
;
1201 if (offset
!= s
->font_offsets
[1]) {
1202 s
->font_offsets
[1] = offset
;
1205 if (s
->plane_updated
& (1 << 2) || s
->has_chain4_alias
) {
1206 /* if the plane 2 was modified since the last display, it
1207 indicates the font may have been modified */
1208 s
->plane_updated
= 0;
1211 full_update
|= update_basic_params(s
);
1213 line_offset
= s
->line_offset
;
1215 vga_get_text_resolution(s
, &width
, &height
, &cw
, &cheight
);
1216 if ((height
* width
) <= 1) {
1217 /* better than nothing: exit if transient size is too small */
1220 if ((height
* width
) > CH_ATTR_SIZE
) {
1221 /* better than nothing: exit if transient size is too big */
1225 if (width
!= s
->last_width
|| height
!= s
->last_height
||
1226 cw
!= s
->last_cw
|| cheight
!= s
->last_ch
|| s
->last_depth
) {
1227 s
->last_scr_width
= width
* cw
;
1228 s
->last_scr_height
= height
* cheight
;
1229 qemu_console_resize(s
->con
, s
->last_scr_width
, s
->last_scr_height
);
1230 surface
= qemu_console_surface(s
->con
);
1231 dpy_text_resize(s
->con
, width
, height
);
1233 s
->last_width
= width
;
1234 s
->last_height
= height
;
1235 s
->last_ch
= cheight
;
1239 full_update
|= update_palette16(s
);
1240 palette
= s
->last_palette
;
1241 x_incr
= cw
* surface_bytes_per_pixel(surface
);
1244 s
->full_update_text
= 1;
1246 if (s
->full_update_gfx
) {
1247 s
->full_update_gfx
= 0;
1251 cursor_offset
= ((s
->cr
[VGA_CRTC_CURSOR_HI
] << 8) |
1252 s
->cr
[VGA_CRTC_CURSOR_LO
]) - s
->start_addr
;
1253 if (cursor_offset
!= s
->cursor_offset
||
1254 s
->cr
[VGA_CRTC_CURSOR_START
] != s
->cursor_start
||
1255 s
->cr
[VGA_CRTC_CURSOR_END
] != s
->cursor_end
) {
1256 /* if the cursor position changed, we update the old and new
1258 if (s
->cursor_offset
< CH_ATTR_SIZE
)
1259 s
->last_ch_attr
[s
->cursor_offset
] = -1;
1260 if (cursor_offset
< CH_ATTR_SIZE
)
1261 s
->last_ch_attr
[cursor_offset
] = -1;
1262 s
->cursor_offset
= cursor_offset
;
1263 s
->cursor_start
= s
->cr
[VGA_CRTC_CURSOR_START
];
1264 s
->cursor_end
= s
->cr
[VGA_CRTC_CURSOR_END
];
1266 cursor_ptr
= s
->vram_ptr
+ (s
->start_addr
+ cursor_offset
) * 4;
1267 if (now
>= s
->cursor_blink_time
) {
1268 s
->cursor_blink_time
= now
+ VGA_TEXT_CURSOR_PERIOD_MS
/ 2;
1269 s
->cursor_visible_phase
= !s
->cursor_visible_phase
;
1272 dest
= surface_data(surface
);
1273 linesize
= surface_stride(surface
);
1274 ch_attr_ptr
= s
->last_ch_attr
;
1276 offset
= s
->start_addr
* 4;
1277 for(cy
= 0; cy
< height
; cy
++) {
1279 src
= s
->vram_ptr
+ offset
;
1282 for(cx
= 0; cx
< width
; cx
++) {
1283 ch_attr
= *(uint16_t *)src
;
1284 if (full_update
|| ch_attr
!= *ch_attr_ptr
|| src
== cursor_ptr
) {
1289 *ch_attr_ptr
= ch_attr
;
1290 #ifdef HOST_WORDS_BIGENDIAN
1292 cattr
= ch_attr
& 0xff;
1294 ch
= ch_attr
& 0xff;
1295 cattr
= ch_attr
>> 8;
1297 font_ptr
= font_base
[(cattr
>> 3) & 1];
1298 font_ptr
+= 32 * 4 * ch
;
1299 bgcol
= palette
[cattr
>> 4];
1300 fgcol
= palette
[cattr
& 0x0f];
1302 vga_draw_glyph16(d1
, linesize
,
1303 font_ptr
, cheight
, fgcol
, bgcol
);
1304 } else if (cw
!= 9) {
1305 vga_draw_glyph8(d1
, linesize
,
1306 font_ptr
, cheight
, fgcol
, bgcol
);
1309 if (ch
>= 0xb0 && ch
<= 0xdf &&
1310 (s
->ar
[VGA_ATC_MODE
] & 0x04)) {
1313 vga_draw_glyph9(d1
, linesize
,
1314 font_ptr
, cheight
, fgcol
, bgcol
, dup9
);
1316 if (src
== cursor_ptr
&&
1317 !(s
->cr
[VGA_CRTC_CURSOR_START
] & 0x20) &&
1318 s
->cursor_visible_phase
) {
1319 int line_start
, line_last
, h
;
1320 /* draw the cursor */
1321 line_start
= s
->cr
[VGA_CRTC_CURSOR_START
] & 0x1f;
1322 line_last
= s
->cr
[VGA_CRTC_CURSOR_END
] & 0x1f;
1323 /* XXX: check that */
1324 if (line_last
> cheight
- 1)
1325 line_last
= cheight
- 1;
1326 if (line_last
>= line_start
&& line_start
< cheight
) {
1327 h
= line_last
- line_start
+ 1;
1328 d
= d1
+ linesize
* line_start
;
1330 vga_draw_glyph16(d
, linesize
,
1331 cursor_glyph
, h
, fgcol
, bgcol
);
1332 } else if (cw
!= 9) {
1333 vga_draw_glyph8(d
, linesize
,
1334 cursor_glyph
, h
, fgcol
, bgcol
);
1336 vga_draw_glyph9(d
, linesize
,
1337 cursor_glyph
, h
, fgcol
, bgcol
, 1);
1347 dpy_gfx_update(s
->con
, cx_min
* cw
, cy
* cheight
,
1348 (cx_max
- cx_min
+ 1) * cw
, cheight
);
1350 dest
+= linesize
* cheight
;
1351 line1
= line
+ cheight
;
1352 offset
+= line_offset
;
1353 if (line
< s
->line_compare
&& line1
>= s
->line_compare
) {
1378 static vga_draw_line_func
* const vga_draw_line_table
[VGA_DRAW_LINE_NB
] = {
1395 static int vga_get_bpp(VGACommonState
*s
)
1399 if (vbe_enabled(s
)) {
1400 ret
= s
->vbe_regs
[VBE_DISPI_INDEX_BPP
];
1407 static void vga_get_resolution(VGACommonState
*s
, int *pwidth
, int *pheight
)
1411 if (vbe_enabled(s
)) {
1412 width
= s
->vbe_regs
[VBE_DISPI_INDEX_XRES
];
1413 height
= s
->vbe_regs
[VBE_DISPI_INDEX_YRES
];
1415 width
= (s
->cr
[VGA_CRTC_H_DISP
] + 1) * 8;
1416 height
= s
->cr
[VGA_CRTC_V_DISP_END
] |
1417 ((s
->cr
[VGA_CRTC_OVERFLOW
] & 0x02) << 7) |
1418 ((s
->cr
[VGA_CRTC_OVERFLOW
] & 0x40) << 3);
1419 height
= (height
+ 1);
1425 void vga_invalidate_scanlines(VGACommonState
*s
, int y1
, int y2
)
1428 if (y1
>= VGA_MAX_HEIGHT
)
1430 if (y2
>= VGA_MAX_HEIGHT
)
1431 y2
= VGA_MAX_HEIGHT
;
1432 for(y
= y1
; y
< y2
; y
++) {
1433 s
->invalidated_y_table
[y
>> 5] |= 1 << (y
& 0x1f);
1437 static bool vga_scanline_invalidated(VGACommonState
*s
, int y
)
1439 if (y
>= VGA_MAX_HEIGHT
) {
1442 return s
->invalidated_y_table
[y
>> 5] & (1 << (y
& 0x1f));
1445 void vga_sync_dirty_bitmap(VGACommonState
*s
)
1447 memory_region_sync_dirty_bitmap(&s
->vram
);
1450 void vga_dirty_log_start(VGACommonState
*s
)
1452 memory_region_set_log(&s
->vram
, true, DIRTY_MEMORY_VGA
);
1455 void vga_dirty_log_stop(VGACommonState
*s
)
1457 memory_region_set_log(&s
->vram
, false, DIRTY_MEMORY_VGA
);
1463 static void vga_draw_graphic(VGACommonState
*s
, int full_update
)
1465 DisplaySurface
*surface
= qemu_console_surface(s
->con
);
1466 int y1
, y
, update
, linesize
, y_start
, double_scan
, mask
, depth
;
1467 int width
, height
, shift_control
, line_offset
, bwidth
, bits
;
1468 ram_addr_t page0
, page1
;
1469 DirtyBitmapSnapshot
*snap
= NULL
;
1470 int disp_width
, multi_scan
, multi_run
;
1472 uint32_t v
, addr1
, addr
;
1473 vga_draw_line_func
*vga_draw_line
= NULL
;
1475 pixman_format_code_t format
;
1476 #ifdef HOST_WORDS_BIGENDIAN
1477 bool byteswap
= !s
->big_endian_fb
;
1479 bool byteswap
= s
->big_endian_fb
;
1482 full_update
|= update_basic_params(s
);
1484 s
->get_resolution(s
, &width
, &height
);
1487 shift_control
= (s
->gr
[VGA_GFX_MODE
] >> 5) & 3;
1488 double_scan
= (s
->cr
[VGA_CRTC_MAX_SCAN
] >> 7);
1489 if (shift_control
!= 1) {
1490 multi_scan
= (((s
->cr
[VGA_CRTC_MAX_SCAN
] & 0x1f) + 1) << double_scan
)
1493 /* in CGA modes, multi_scan is ignored */
1494 /* XXX: is it correct ? */
1495 multi_scan
= double_scan
;
1497 multi_run
= multi_scan
;
1498 if (shift_control
!= s
->shift_control
||
1499 double_scan
!= s
->double_scan
) {
1501 s
->shift_control
= shift_control
;
1502 s
->double_scan
= double_scan
;
1505 if (shift_control
== 0) {
1506 if (sr(s
, VGA_SEQ_CLOCK_MODE
) & 8) {
1509 } else if (shift_control
== 1) {
1510 if (sr(s
, VGA_SEQ_CLOCK_MODE
) & 8) {
1515 depth
= s
->get_bpp(s
);
1518 * Check whether we can share the surface with the backend
1519 * or whether we need a shadow surface. We share native
1520 * endian surfaces for 15bpp and above and byteswapped
1521 * surfaces for 24bpp and above.
1523 format
= qemu_default_pixman_format(depth
, !byteswap
);
1525 share_surface
= dpy_gfx_check_format(s
->con
, format
)
1526 && !s
->force_shadow
;
1528 share_surface
= false;
1530 if (s
->line_offset
!= s
->last_line_offset
||
1531 disp_width
!= s
->last_width
||
1532 height
!= s
->last_height
||
1533 s
->last_depth
!= depth
||
1534 s
->last_byteswap
!= byteswap
||
1535 share_surface
!= is_buffer_shared(surface
)) {
1536 if (share_surface
) {
1537 surface
= qemu_create_displaysurface_from(disp_width
,
1538 height
, format
, s
->line_offset
,
1539 s
->vram_ptr
+ (s
->start_addr
* 4));
1540 dpy_gfx_replace_surface(s
->con
, surface
);
1542 qemu_console_resize(s
->con
, disp_width
, height
);
1543 surface
= qemu_console_surface(s
->con
);
1545 s
->last_scr_width
= disp_width
;
1546 s
->last_scr_height
= height
;
1547 s
->last_width
= disp_width
;
1548 s
->last_height
= height
;
1549 s
->last_line_offset
= s
->line_offset
;
1550 s
->last_depth
= depth
;
1551 s
->last_byteswap
= byteswap
;
1553 } else if (is_buffer_shared(surface
) &&
1554 (full_update
|| surface_data(surface
) != s
->vram_ptr
1555 + (s
->start_addr
* 4))) {
1556 pixman_format_code_t format
=
1557 qemu_default_pixman_format(depth
, !byteswap
);
1558 surface
= qemu_create_displaysurface_from(disp_width
,
1559 height
, format
, s
->line_offset
,
1560 s
->vram_ptr
+ (s
->start_addr
* 4));
1561 dpy_gfx_replace_surface(s
->con
, surface
);
1564 if (shift_control
== 0) {
1565 full_update
|= update_palette16(s
);
1566 if (sr(s
, VGA_SEQ_CLOCK_MODE
) & 8) {
1567 v
= VGA_DRAW_LINE4D2
;
1572 } else if (shift_control
== 1) {
1573 full_update
|= update_palette16(s
);
1574 if (sr(s
, VGA_SEQ_CLOCK_MODE
) & 8) {
1575 v
= VGA_DRAW_LINE2D2
;
1581 switch(s
->get_bpp(s
)) {
1584 full_update
|= update_palette256(s
);
1585 v
= VGA_DRAW_LINE8D2
;
1589 full_update
|= update_palette256(s
);
1594 v
= s
->big_endian_fb
? VGA_DRAW_LINE15_BE
: VGA_DRAW_LINE15_LE
;
1598 v
= s
->big_endian_fb
? VGA_DRAW_LINE16_BE
: VGA_DRAW_LINE16_LE
;
1602 v
= s
->big_endian_fb
? VGA_DRAW_LINE24_BE
: VGA_DRAW_LINE24_LE
;
1606 v
= s
->big_endian_fb
? VGA_DRAW_LINE32_BE
: VGA_DRAW_LINE32_LE
;
1611 vga_draw_line
= vga_draw_line_table
[v
];
1613 if (!is_buffer_shared(surface
) && s
->cursor_invalidate
) {
1614 s
->cursor_invalidate(s
);
1617 line_offset
= s
->line_offset
;
1619 printf("w=%d h=%d v=%d line_offset=%d cr[0x09]=0x%02x cr[0x17]=0x%02x linecmp=%d sr[0x01]=0x%02x\n",
1620 width
, height
, v
, line_offset
, s
->cr
[9], s
->cr
[VGA_CRTC_MODE
],
1621 s
->line_compare
, sr(s
, VGA_SEQ_CLOCK_MODE
));
1623 addr1
= (s
->start_addr
* 4);
1624 bwidth
= (width
* bits
+ 7) / 8;
1626 d
= surface_data(surface
);
1627 linesize
= surface_stride(surface
);
1631 vga_sync_dirty_bitmap(s
);
1632 snap
= memory_region_snapshot_and_clear_dirty(&s
->vram
, addr1
,
1633 line_offset
* height
,
1637 for(y
= 0; y
< height
; y
++) {
1639 if (!(s
->cr
[VGA_CRTC_MODE
] & 1)) {
1641 /* CGA compatibility handling */
1642 shift
= 14 + ((s
->cr
[VGA_CRTC_MODE
] >> 6) & 1);
1643 addr
= (addr
& ~(1 << shift
)) | ((y1
& 1) << shift
);
1645 if (!(s
->cr
[VGA_CRTC_MODE
] & 2)) {
1646 addr
= (addr
& ~0x8000) | ((y1
& 2) << 14);
1648 update
= full_update
;
1650 page1
= addr
+ bwidth
- 1;
1654 update
= memory_region_snapshot_get_dirty(&s
->vram
, snap
,
1655 page0
, page1
- page0
);
1657 /* explicit invalidation for the hardware cursor (cirrus only) */
1658 update
|= vga_scanline_invalidated(s
, y
);
1662 if (!(is_buffer_shared(surface
))) {
1663 vga_draw_line(s
, d
, s
->vram_ptr
+ addr
, width
);
1664 if (s
->cursor_draw_line
)
1665 s
->cursor_draw_line(s
, d
, y
);
1669 /* flush to display */
1670 dpy_gfx_update(s
->con
, 0, y_start
,
1671 disp_width
, y
- y_start
);
1676 mask
= (s
->cr
[VGA_CRTC_MODE
] & 3) ^ 3;
1677 if ((y1
& mask
) == mask
)
1678 addr1
+= line_offset
;
1680 multi_run
= multi_scan
;
1684 /* line compare acts on the displayed lines */
1685 if (y
== s
->line_compare
)
1690 /* flush to display */
1691 dpy_gfx_update(s
->con
, 0, y_start
,
1692 disp_width
, y
- y_start
);
1695 memset(s
->invalidated_y_table
, 0, sizeof(s
->invalidated_y_table
));
1698 static void vga_draw_blank(VGACommonState
*s
, int full_update
)
1700 DisplaySurface
*surface
= qemu_console_surface(s
->con
);
1706 if (s
->last_scr_width
<= 0 || s
->last_scr_height
<= 0)
1709 w
= s
->last_scr_width
* surface_bytes_per_pixel(surface
);
1710 d
= surface_data(surface
);
1711 for(i
= 0; i
< s
->last_scr_height
; i
++) {
1713 d
+= surface_stride(surface
);
1715 dpy_gfx_update(s
->con
, 0, 0,
1716 s
->last_scr_width
, s
->last_scr_height
);
1719 #define GMODE_TEXT 0
1720 #define GMODE_GRAPH 1
1721 #define GMODE_BLANK 2
1723 static void vga_update_display(void *opaque
)
1725 VGACommonState
*s
= opaque
;
1726 DisplaySurface
*surface
= qemu_console_surface(s
->con
);
1727 int full_update
, graphic_mode
;
1729 qemu_flush_coalesced_mmio_buffer();
1731 if (surface_bits_per_pixel(surface
) == 0) {
1735 if (!(s
->ar_index
& 0x20)) {
1736 graphic_mode
= GMODE_BLANK
;
1738 graphic_mode
= s
->gr
[VGA_GFX_MISC
] & VGA_GR06_GRAPHICS_MODE
;
1740 if (graphic_mode
!= s
->graphic_mode
) {
1741 s
->graphic_mode
= graphic_mode
;
1742 s
->cursor_blink_time
= qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL
);
1745 switch(graphic_mode
) {
1747 vga_draw_text(s
, full_update
);
1750 vga_draw_graphic(s
, full_update
);
1754 vga_draw_blank(s
, full_update
);
1760 /* force a full display refresh */
1761 static void vga_invalidate_display(void *opaque
)
1763 VGACommonState
*s
= opaque
;
1766 s
->last_height
= -1;
1769 void vga_common_reset(VGACommonState
*s
)
1772 memset(s
->sr
, '\0', sizeof(s
->sr
));
1773 memset(s
->sr_vbe
, '\0', sizeof(s
->sr_vbe
));
1775 memset(s
->gr
, '\0', sizeof(s
->gr
));
1777 memset(s
->ar
, '\0', sizeof(s
->ar
));
1778 s
->ar_flip_flop
= 0;
1780 memset(s
->cr
, '\0', sizeof(s
->cr
));
1786 s
->dac_sub_index
= 0;
1787 s
->dac_read_index
= 0;
1788 s
->dac_write_index
= 0;
1789 memset(s
->dac_cache
, '\0', sizeof(s
->dac_cache
));
1791 memset(s
->palette
, '\0', sizeof(s
->palette
));
1794 memset(s
->vbe_regs
, '\0', sizeof(s
->vbe_regs
));
1795 s
->vbe_regs
[VBE_DISPI_INDEX_ID
] = VBE_DISPI_ID5
;
1796 s
->vbe_start_addr
= 0;
1797 s
->vbe_line_offset
= 0;
1798 s
->vbe_bank_mask
= (s
->vram_size
>> 16) - 1;
1799 memset(s
->font_offsets
, '\0', sizeof(s
->font_offsets
));
1800 s
->graphic_mode
= -1; /* force full update */
1801 s
->shift_control
= 0;
1804 s
->line_compare
= 0;
1806 s
->plane_updated
= 0;
1811 s
->last_scr_width
= 0;
1812 s
->last_scr_height
= 0;
1813 s
->cursor_start
= 0;
1815 s
->cursor_offset
= 0;
1816 s
->big_endian_fb
= s
->default_endian_fb
;
1817 memset(s
->invalidated_y_table
, '\0', sizeof(s
->invalidated_y_table
));
1818 memset(s
->last_palette
, '\0', sizeof(s
->last_palette
));
1819 memset(s
->last_ch_attr
, '\0', sizeof(s
->last_ch_attr
));
1820 switch (vga_retrace_method
) {
1821 case VGA_RETRACE_DUMB
:
1823 case VGA_RETRACE_PRECISE
:
1824 memset(&s
->retrace_info
, 0, sizeof (s
->retrace_info
));
1827 vga_update_memory_access(s
);
1830 static void vga_reset(void *opaque
)
1832 VGACommonState
*s
= opaque
;
1833 vga_common_reset(s
);
1836 #define TEXTMODE_X(x) ((x) % width)
1837 #define TEXTMODE_Y(x) ((x) / width)
1838 #define VMEM2CHTYPE(v) ((v & 0xff0007ff) | \
1839 ((v & 0x00000800) << 10) | ((v & 0x00007000) >> 1))
1840 /* relay text rendering to the display driver
1841 * instead of doing a full vga_update_display() */
1842 static void vga_update_text(void *opaque
, console_ch_t
*chardata
)
1844 VGACommonState
*s
= opaque
;
1845 int graphic_mode
, i
, cursor_offset
, cursor_visible
;
1846 int cw
, cheight
, width
, height
, size
, c_min
, c_max
;
1848 console_ch_t
*dst
, val
;
1849 char msg_buffer
[80];
1850 int full_update
= 0;
1852 qemu_flush_coalesced_mmio_buffer();
1854 if (!(s
->ar_index
& 0x20)) {
1855 graphic_mode
= GMODE_BLANK
;
1857 graphic_mode
= s
->gr
[VGA_GFX_MISC
] & VGA_GR06_GRAPHICS_MODE
;
1859 if (graphic_mode
!= s
->graphic_mode
) {
1860 s
->graphic_mode
= graphic_mode
;
1863 if (s
->last_width
== -1) {
1868 switch (graphic_mode
) {
1870 /* TODO: update palette */
1871 full_update
|= update_basic_params(s
);
1873 /* total width & height */
1874 cheight
= (s
->cr
[VGA_CRTC_MAX_SCAN
] & 0x1f) + 1;
1876 if (!(sr(s
, VGA_SEQ_CLOCK_MODE
) & VGA_SR01_CHAR_CLK_8DOTS
)) {
1879 if (sr(s
, VGA_SEQ_CLOCK_MODE
) & 0x08) {
1880 cw
= 16; /* NOTE: no 18 pixel wide */
1882 width
= (s
->cr
[VGA_CRTC_H_DISP
] + 1);
1883 if (s
->cr
[VGA_CRTC_V_TOTAL
] == 100) {
1884 /* ugly hack for CGA 160x100x16 - explain me the logic */
1887 height
= s
->cr
[VGA_CRTC_V_DISP_END
] |
1888 ((s
->cr
[VGA_CRTC_OVERFLOW
] & 0x02) << 7) |
1889 ((s
->cr
[VGA_CRTC_OVERFLOW
] & 0x40) << 3);
1890 height
= (height
+ 1) / cheight
;
1893 size
= (height
* width
);
1894 if (size
> CH_ATTR_SIZE
) {
1898 snprintf(msg_buffer
, sizeof(msg_buffer
), "%i x %i Text mode",
1903 if (width
!= s
->last_width
|| height
!= s
->last_height
||
1904 cw
!= s
->last_cw
|| cheight
!= s
->last_ch
) {
1905 s
->last_scr_width
= width
* cw
;
1906 s
->last_scr_height
= height
* cheight
;
1907 qemu_console_resize(s
->con
, s
->last_scr_width
, s
->last_scr_height
);
1908 dpy_text_resize(s
->con
, width
, height
);
1910 s
->last_width
= width
;
1911 s
->last_height
= height
;
1912 s
->last_ch
= cheight
;
1918 s
->full_update_gfx
= 1;
1920 if (s
->full_update_text
) {
1921 s
->full_update_text
= 0;
1925 /* Update "hardware" cursor */
1926 cursor_offset
= ((s
->cr
[VGA_CRTC_CURSOR_HI
] << 8) |
1927 s
->cr
[VGA_CRTC_CURSOR_LO
]) - s
->start_addr
;
1928 if (cursor_offset
!= s
->cursor_offset
||
1929 s
->cr
[VGA_CRTC_CURSOR_START
] != s
->cursor_start
||
1930 s
->cr
[VGA_CRTC_CURSOR_END
] != s
->cursor_end
|| full_update
) {
1931 cursor_visible
= !(s
->cr
[VGA_CRTC_CURSOR_START
] & 0x20);
1932 if (cursor_visible
&& cursor_offset
< size
&& cursor_offset
>= 0)
1933 dpy_text_cursor(s
->con
,
1934 TEXTMODE_X(cursor_offset
),
1935 TEXTMODE_Y(cursor_offset
));
1937 dpy_text_cursor(s
->con
, -1, -1);
1938 s
->cursor_offset
= cursor_offset
;
1939 s
->cursor_start
= s
->cr
[VGA_CRTC_CURSOR_START
];
1940 s
->cursor_end
= s
->cr
[VGA_CRTC_CURSOR_END
];
1943 src
= (uint32_t *) s
->vram_ptr
+ s
->start_addr
;
1947 for (i
= 0; i
< size
; src
++, dst
++, i
++)
1948 console_write_ch(dst
, VMEM2CHTYPE(le32_to_cpu(*src
)));
1950 dpy_text_update(s
->con
, 0, 0, width
, height
);
1954 for (i
= 0; i
< size
; src
++, dst
++, i
++) {
1955 console_write_ch(&val
, VMEM2CHTYPE(le32_to_cpu(*src
)));
1963 for (; i
< size
; src
++, dst
++, i
++) {
1964 console_write_ch(&val
, VMEM2CHTYPE(le32_to_cpu(*src
)));
1971 if (c_min
<= c_max
) {
1972 i
= TEXTMODE_Y(c_min
);
1973 dpy_text_update(s
->con
, 0, i
, width
, TEXTMODE_Y(c_max
) - i
+ 1);
1982 s
->get_resolution(s
, &width
, &height
);
1983 snprintf(msg_buffer
, sizeof(msg_buffer
), "%i x %i Graphic mode",
1991 snprintf(msg_buffer
, sizeof(msg_buffer
), "VGA Blank mode");
1995 /* Display a message */
1997 s
->last_height
= height
= 3;
1998 dpy_text_cursor(s
->con
, -1, -1);
1999 dpy_text_resize(s
->con
, s
->last_width
, height
);
2001 for (dst
= chardata
, i
= 0; i
< s
->last_width
* height
; i
++)
2002 console_write_ch(dst
++, ' ');
2004 size
= strlen(msg_buffer
);
2005 width
= (s
->last_width
- size
) / 2;
2006 dst
= chardata
+ s
->last_width
+ width
;
2007 for (i
= 0; i
< size
; i
++)
2008 console_write_ch(dst
++, ATTR2CHTYPE(msg_buffer
[i
], QEMU_COLOR_BLUE
,
2009 QEMU_COLOR_BLACK
, 1));
2011 dpy_text_update(s
->con
, 0, 0, s
->last_width
, height
);
2014 static uint64_t vga_mem_read(void *opaque
, hwaddr addr
,
2017 VGACommonState
*s
= opaque
;
2019 return vga_mem_readb(s
, addr
);
2022 static void vga_mem_write(void *opaque
, hwaddr addr
,
2023 uint64_t data
, unsigned size
)
2025 VGACommonState
*s
= opaque
;
2027 vga_mem_writeb(s
, addr
, data
);
2030 const MemoryRegionOps vga_mem_ops
= {
2031 .read
= vga_mem_read
,
2032 .write
= vga_mem_write
,
2033 .endianness
= DEVICE_LITTLE_ENDIAN
,
2035 .min_access_size
= 1,
2036 .max_access_size
= 1,
2040 static int vga_common_post_load(void *opaque
, int version_id
)
2042 VGACommonState
*s
= opaque
;
2045 s
->graphic_mode
= -1;
2046 vbe_update_vgaregs(s
);
2050 static bool vga_endian_state_needed(void *opaque
)
2052 VGACommonState
*s
= opaque
;
2055 * Only send the endian state if it's different from the
2056 * default one, thus ensuring backward compatibility for
2057 * migration of the common case
2059 return s
->default_endian_fb
!= s
->big_endian_fb
;
2062 static const VMStateDescription vmstate_vga_endian
= {
2063 .name
= "vga.endian",
2065 .minimum_version_id
= 1,
2066 .needed
= vga_endian_state_needed
,
2067 .fields
= (VMStateField
[]) {
2068 VMSTATE_BOOL(big_endian_fb
, VGACommonState
),
2069 VMSTATE_END_OF_LIST()
2073 const VMStateDescription vmstate_vga_common
= {
2076 .minimum_version_id
= 2,
2077 .post_load
= vga_common_post_load
,
2078 .fields
= (VMStateField
[]) {
2079 VMSTATE_UINT32(latch
, VGACommonState
),
2080 VMSTATE_UINT8(sr_index
, VGACommonState
),
2081 VMSTATE_PARTIAL_BUFFER(sr
, VGACommonState
, 8),
2082 VMSTATE_UINT8(gr_index
, VGACommonState
),
2083 VMSTATE_PARTIAL_BUFFER(gr
, VGACommonState
, 16),
2084 VMSTATE_UINT8(ar_index
, VGACommonState
),
2085 VMSTATE_BUFFER(ar
, VGACommonState
),
2086 VMSTATE_INT32(ar_flip_flop
, VGACommonState
),
2087 VMSTATE_UINT8(cr_index
, VGACommonState
),
2088 VMSTATE_BUFFER(cr
, VGACommonState
),
2089 VMSTATE_UINT8(msr
, VGACommonState
),
2090 VMSTATE_UINT8(fcr
, VGACommonState
),
2091 VMSTATE_UINT8(st00
, VGACommonState
),
2092 VMSTATE_UINT8(st01
, VGACommonState
),
2094 VMSTATE_UINT8(dac_state
, VGACommonState
),
2095 VMSTATE_UINT8(dac_sub_index
, VGACommonState
),
2096 VMSTATE_UINT8(dac_read_index
, VGACommonState
),
2097 VMSTATE_UINT8(dac_write_index
, VGACommonState
),
2098 VMSTATE_BUFFER(dac_cache
, VGACommonState
),
2099 VMSTATE_BUFFER(palette
, VGACommonState
),
2101 VMSTATE_INT32(bank_offset
, VGACommonState
),
2102 VMSTATE_UINT8_EQUAL(is_vbe_vmstate
, VGACommonState
, NULL
),
2103 VMSTATE_UINT16(vbe_index
, VGACommonState
),
2104 VMSTATE_UINT16_ARRAY(vbe_regs
, VGACommonState
, VBE_DISPI_INDEX_NB
),
2105 VMSTATE_UINT32(vbe_start_addr
, VGACommonState
),
2106 VMSTATE_UINT32(vbe_line_offset
, VGACommonState
),
2107 VMSTATE_UINT32(vbe_bank_mask
, VGACommonState
),
2108 VMSTATE_END_OF_LIST()
2110 .subsections
= (const VMStateDescription
*[]) {
2111 &vmstate_vga_endian
,
2116 static const GraphicHwOps vga_ops
= {
2117 .invalidate
= vga_invalidate_display
,
2118 .gfx_update
= vga_update_display
,
2119 .text_update
= vga_update_text
,
2122 static inline uint32_t uint_clamp(uint32_t val
, uint32_t vmin
, uint32_t vmax
)
2133 void vga_common_init(VGACommonState
*s
, Object
*obj
, bool global_vmstate
)
2137 for(i
= 0;i
< 256; i
++) {
2139 for(j
= 0; j
< 8; j
++) {
2140 v
|= ((i
>> j
) & 1) << (j
* 4);
2145 for(j
= 0; j
< 4; j
++) {
2146 v
|= ((i
>> (2 * j
)) & 3) << (j
* 4);
2150 for(i
= 0; i
< 16; i
++) {
2152 for(j
= 0; j
< 4; j
++) {
2155 v
|= b
<< (2 * j
+ 1);
2160 s
->vram_size_mb
= uint_clamp(s
->vram_size_mb
, 1, 512);
2161 s
->vram_size_mb
= pow2ceil(s
->vram_size_mb
);
2162 s
->vram_size
= s
->vram_size_mb
<< 20;
2165 s
->vbe_size
= s
->vram_size
;
2168 s
->is_vbe_vmstate
= 1;
2169 memory_region_init_ram_nomigrate(&s
->vram
, obj
, "vga.vram", s
->vram_size
,
2171 vmstate_register_ram(&s
->vram
, global_vmstate
? NULL
: DEVICE(obj
));
2172 xen_register_framebuffer(&s
->vram
);
2173 s
->vram_ptr
= memory_region_get_ram_ptr(&s
->vram
);
2174 s
->get_bpp
= vga_get_bpp
;
2175 s
->get_offsets
= vga_get_offsets
;
2176 s
->get_resolution
= vga_get_resolution
;
2177 s
->hw_ops
= &vga_ops
;
2178 switch (vga_retrace_method
) {
2179 case VGA_RETRACE_DUMB
:
2180 s
->retrace
= vga_dumb_retrace
;
2181 s
->update_retrace_info
= vga_dumb_update_retrace_info
;
2184 case VGA_RETRACE_PRECISE
:
2185 s
->retrace
= vga_precise_retrace
;
2186 s
->update_retrace_info
= vga_precise_update_retrace_info
;
2191 * Set default fb endian based on target, could probably be turned
2192 * into a device attribute set by the machine/platform to remove
2193 * all target endian dependencies from this file.
2195 #ifdef TARGET_WORDS_BIGENDIAN
2196 s
->default_endian_fb
= true;
2198 s
->default_endian_fb
= false;
2200 vga_dirty_log_start(s
);
2203 static const MemoryRegionPortio vga_portio_list
[] = {
2204 { 0x04, 2, 1, .read
= vga_ioport_read
, .write
= vga_ioport_write
}, /* 3b4 */
2205 { 0x0a, 1, 1, .read
= vga_ioport_read
, .write
= vga_ioport_write
}, /* 3ba */
2206 { 0x10, 16, 1, .read
= vga_ioport_read
, .write
= vga_ioport_write
}, /* 3c0 */
2207 { 0x24, 2, 1, .read
= vga_ioport_read
, .write
= vga_ioport_write
}, /* 3d4 */
2208 { 0x2a, 1, 1, .read
= vga_ioport_read
, .write
= vga_ioport_write
}, /* 3da */
2209 PORTIO_END_OF_LIST(),
2212 static const MemoryRegionPortio vbe_portio_list
[] = {
2213 { 0, 1, 2, .read
= vbe_ioport_read_index
, .write
= vbe_ioport_write_index
},
2215 { 1, 1, 2, .read
= vbe_ioport_read_data
, .write
= vbe_ioport_write_data
},
2217 { 2, 1, 2, .read
= vbe_ioport_read_data
, .write
= vbe_ioport_write_data
},
2218 PORTIO_END_OF_LIST(),
2221 /* Used by both ISA and PCI */
2222 MemoryRegion
*vga_init_io(VGACommonState
*s
, Object
*obj
,
2223 const MemoryRegionPortio
**vga_ports
,
2224 const MemoryRegionPortio
**vbe_ports
)
2226 MemoryRegion
*vga_mem
;
2228 *vga_ports
= vga_portio_list
;
2229 *vbe_ports
= vbe_portio_list
;
2231 vga_mem
= g_malloc(sizeof(*vga_mem
));
2232 memory_region_init_io(vga_mem
, obj
, &vga_mem_ops
, s
,
2233 "vga-lowmem", 0x20000);
2234 memory_region_set_flush_coalesced(vga_mem
);
2239 void vga_init(VGACommonState
*s
, Object
*obj
, MemoryRegion
*address_space
,
2240 MemoryRegion
*address_space_io
, bool init_vga_ports
)
2242 MemoryRegion
*vga_io_memory
;
2243 const MemoryRegionPortio
*vga_ports
, *vbe_ports
;
2245 qemu_register_reset(vga_reset
, s
);
2249 s
->legacy_address_space
= address_space
;
2251 vga_io_memory
= vga_init_io(s
, obj
, &vga_ports
, &vbe_ports
);
2252 memory_region_add_subregion_overlap(address_space
,
2256 memory_region_set_coalescing(vga_io_memory
);
2257 if (init_vga_ports
) {
2258 portio_list_init(&s
->vga_port_list
, obj
, vga_ports
, s
, "vga");
2259 portio_list_set_flush_coalesced(&s
->vga_port_list
);
2260 portio_list_add(&s
->vga_port_list
, address_space_io
, 0x3b0);
2263 portio_list_init(&s
->vbe_port_list
, obj
, vbe_ports
, s
, "vbe");
2264 portio_list_add(&s
->vbe_port_list
, address_space_io
, 0x1ce);
2268 void vga_init_vbe(VGACommonState
*s
, Object
*obj
, MemoryRegion
*system_memory
)
2270 /* With pc-0.12 and below we map both the PCI BAR and the fixed VBE region,
2271 * so use an alias to avoid double-mapping the same region.
2273 memory_region_init_alias(&s
->vram_vbe
, obj
, "vram.vbe",
2274 &s
->vram
, 0, memory_region_size(&s
->vram
));
2275 /* XXX: use optimized standard vga accesses */
2276 memory_region_add_subregion(system_memory
,
2277 VBE_DISPI_LFB_PHYSICAL_ADDRESS
,