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qapi/dump: Indent bulleted lists consistently
[qemu/armbru.git] / hw / arm / xlnx-versal.c
blob69b1b99e937178e859bd4e49c64a75a703a98321
1 /*
2 * Xilinx Versal SoC model.
3 *
4 * Copyright (c) 2018 Xilinx Inc.
5 * Written by Edgar E. Iglesias
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 or
9 * (at your option) any later version.
10 */
11
12 #include "qemu/osdep.h"
13 #include "qemu/units.h"
14 #include "qapi/error.h"
15 #include "qemu/module.h"
16 #include "hw/sysbus.h"
17 #include "net/net.h"
18 #include "sysemu/sysemu.h"
19 #include "sysemu/kvm.h"
20 #include "hw/arm/boot.h"
21 #include "kvm_arm.h"
22 #include "hw/misc/unimp.h"
23 #include "hw/arm/xlnx-versal.h"
24 #include "qemu/log.h"
25
26 #define XLNX_VERSAL_ACPU_TYPE ARM_CPU_TYPE_NAME("cortex-a72")
27 #define XLNX_VERSAL_RCPU_TYPE ARM_CPU_TYPE_NAME("cortex-r5f")
28 #define GEM_REVISION 0x40070106
29
30 #define VERSAL_NUM_PMC_APB_IRQS 3
31 #define NUM_OSPI_IRQ_LINES 3
32
33 static void versal_create_apu_cpus(Versal *s)
34 {
35 int i;
36
37 object_initialize_child(OBJECT(s), "apu-cluster", &s->fpd.apu.cluster,
38 TYPE_CPU_CLUSTER);
39 qdev_prop_set_uint32(DEVICE(&s->fpd.apu.cluster), "cluster-id", 0);
40
41 for (i = 0; i < ARRAY_SIZE(s->fpd.apu.cpu); i++) {
42 Object *obj;
43
44 object_initialize_child(OBJECT(&s->fpd.apu.cluster),
45 "apu-cpu[*]", &s->fpd.apu.cpu[i],
46 XLNX_VERSAL_ACPU_TYPE);
47 obj = OBJECT(&s->fpd.apu.cpu[i]);
48 if (i) {
49 /* Secondary CPUs start in powered-down state */
50 object_property_set_bool(obj, "start-powered-off", true,
51 &error_abort);
52 }
53
54 object_property_set_int(obj, "core-count", ARRAY_SIZE(s->fpd.apu.cpu),
55 &error_abort);
56 object_property_set_link(obj, "memory", OBJECT(&s->fpd.apu.mr),
57 &error_abort);
58 qdev_realize(DEVICE(obj), NULL, &error_fatal);
59 }
60
61 qdev_realize(DEVICE(&s->fpd.apu.cluster), NULL, &error_fatal);
62 }
63
64 static void versal_create_apu_gic(Versal *s, qemu_irq *pic)
65 {
66 static const uint64_t addrs[] = {
67 MM_GIC_APU_DIST_MAIN,
68 MM_GIC_APU_REDIST_0
69 };
70 SysBusDevice *gicbusdev;
71 DeviceState *gicdev;
72 int nr_apu_cpus = ARRAY_SIZE(s->fpd.apu.cpu);
73 int i;
74
75 object_initialize_child(OBJECT(s), "apu-gic", &s->fpd.apu.gic,
76 gicv3_class_name());
77 gicbusdev = SYS_BUS_DEVICE(&s->fpd.apu.gic);
78 gicdev = DEVICE(&s->fpd.apu.gic);
79 qdev_prop_set_uint32(gicdev, "revision", 3);
80 qdev_prop_set_uint32(gicdev, "num-cpu", nr_apu_cpus);
81 qdev_prop_set_uint32(gicdev, "num-irq", XLNX_VERSAL_NR_IRQS + 32);
82 qdev_prop_set_uint32(gicdev, "len-redist-region-count", 1);
83 qdev_prop_set_uint32(gicdev, "redist-region-count[0]", nr_apu_cpus);
84 qdev_prop_set_bit(gicdev, "has-security-extensions", true);
85
86 sysbus_realize(SYS_BUS_DEVICE(&s->fpd.apu.gic), &error_fatal);
87
88 for (i = 0; i < ARRAY_SIZE(addrs); i++) {
89 MemoryRegion *mr;
90
91 mr = sysbus_mmio_get_region(gicbusdev, i);
92 memory_region_add_subregion(&s->fpd.apu.mr, addrs[i], mr);
93 }
94
95 for (i = 0; i < nr_apu_cpus; i++) {
96 DeviceState *cpudev = DEVICE(&s->fpd.apu.cpu[i]);
97 int ppibase = XLNX_VERSAL_NR_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS;
98 qemu_irq maint_irq;
99 int ti;
100 /* Mapping from the output timer irq lines from the CPU to the
101 * GIC PPI inputs.
102 */
103 const int timer_irq[] = {
104 [GTIMER_PHYS] = VERSAL_TIMER_NS_EL1_IRQ,
105 [GTIMER_VIRT] = VERSAL_TIMER_VIRT_IRQ,
106 [GTIMER_HYP] = VERSAL_TIMER_NS_EL2_IRQ,
107 [GTIMER_SEC] = VERSAL_TIMER_S_EL1_IRQ,
108 };
109
110 for (ti = 0; ti < ARRAY_SIZE(timer_irq); ti++) {
111 qdev_connect_gpio_out(cpudev, ti,
112 qdev_get_gpio_in(gicdev,
113 ppibase + timer_irq[ti]));
114 }
115 maint_irq = qdev_get_gpio_in(gicdev,
116 ppibase + VERSAL_GIC_MAINT_IRQ);
117 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt",
118 0, maint_irq);
119 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
120 sysbus_connect_irq(gicbusdev, i + nr_apu_cpus,
121 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
122 sysbus_connect_irq(gicbusdev, i + 2 * nr_apu_cpus,
123 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
124 sysbus_connect_irq(gicbusdev, i + 3 * nr_apu_cpus,
125 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
126 }
127
128 for (i = 0; i < XLNX_VERSAL_NR_IRQS; i++) {
129 pic[i] = qdev_get_gpio_in(gicdev, i);
130 }
131 }
132
133 static void versal_create_rpu_cpus(Versal *s)
134 {
135 int i;
136
137 object_initialize_child(OBJECT(s), "rpu-cluster", &s->lpd.rpu.cluster,
138 TYPE_CPU_CLUSTER);
139 qdev_prop_set_uint32(DEVICE(&s->lpd.rpu.cluster), "cluster-id", 1);
140
141 for (i = 0; i < ARRAY_SIZE(s->lpd.rpu.cpu); i++) {
142 Object *obj;
143
144 object_initialize_child(OBJECT(&s->lpd.rpu.cluster),
145 "rpu-cpu[*]", &s->lpd.rpu.cpu[i],
146 XLNX_VERSAL_RCPU_TYPE);
147 obj = OBJECT(&s->lpd.rpu.cpu[i]);
148 object_property_set_bool(obj, "start-powered-off", true,
149 &error_abort);
150
151 object_property_set_int(obj, "mp-affinity", 0x100 | i, &error_abort);
152 object_property_set_int(obj, "core-count", ARRAY_SIZE(s->lpd.rpu.cpu),
153 &error_abort);
154 object_property_set_link(obj, "memory", OBJECT(&s->lpd.rpu.mr),
155 &error_abort);
156 qdev_realize(DEVICE(obj), NULL, &error_fatal);
157 }
158
159 qdev_realize(DEVICE(&s->lpd.rpu.cluster), NULL, &error_fatal);
160 }
161
162 static void versal_create_uarts(Versal *s, qemu_irq *pic)
163 {
164 int i;
165
166 for (i = 0; i < ARRAY_SIZE(s->lpd.iou.uart); i++) {
167 static const int irqs[] = { VERSAL_UART0_IRQ_0, VERSAL_UART1_IRQ_0};
168 static const uint64_t addrs[] = { MM_UART0, MM_UART1 };
169 char *name = g_strdup_printf("uart%d", i);
170 DeviceState *dev;
171 MemoryRegion *mr;
172
173 object_initialize_child(OBJECT(s), name, &s->lpd.iou.uart[i],
174 TYPE_PL011);
175 dev = DEVICE(&s->lpd.iou.uart[i]);
176 qdev_prop_set_chr(dev, "chardev", serial_hd(i));
177 sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal);
178
179 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
180 memory_region_add_subregion(&s->mr_ps, addrs[i], mr);
181
182 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[irqs[i]]);
183 g_free(name);
184 }
185 }
186
187 static void versal_create_usbs(Versal *s, qemu_irq *pic)
188 {
189 DeviceState *dev;
190 MemoryRegion *mr;
191
192 object_initialize_child(OBJECT(s), "usb2", &s->lpd.iou.usb,
193 TYPE_XILINX_VERSAL_USB2);
194 dev = DEVICE(&s->lpd.iou.usb);
195
196 object_property_set_link(OBJECT(dev), "dma", OBJECT(&s->mr_ps),
197 &error_abort);
198 qdev_prop_set_uint32(dev, "intrs", 1);
199 qdev_prop_set_uint32(dev, "slots", 2);
200
201 sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal);
202
203 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
204 memory_region_add_subregion(&s->mr_ps, MM_USB_0, mr);
205
206 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[VERSAL_USB0_IRQ_0]);
207
208 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
209 memory_region_add_subregion(&s->mr_ps, MM_USB2_CTRL_REGS, mr);
210 }
211
212 static void versal_create_gems(Versal *s, qemu_irq *pic)
213 {
214 int i;
215
216 for (i = 0; i < ARRAY_SIZE(s->lpd.iou.gem); i++) {
217 static const int irqs[] = { VERSAL_GEM0_IRQ_0, VERSAL_GEM1_IRQ_0};
218 static const uint64_t addrs[] = { MM_GEM0, MM_GEM1 };
219 char *name = g_strdup_printf("gem%d", i);
220 NICInfo *nd = &nd_table[i];
221 DeviceState *dev;
222 MemoryRegion *mr;
223
224 object_initialize_child(OBJECT(s), name, &s->lpd.iou.gem[i],
225 TYPE_CADENCE_GEM);
226 dev = DEVICE(&s->lpd.iou.gem[i]);
227 /* FIXME use qdev NIC properties instead of nd_table[] */
228 if (nd->used) {
229 qemu_check_nic_model(nd, "cadence_gem");
230 qdev_set_nic_properties(dev, nd);
231 }
232 object_property_set_int(OBJECT(dev), "phy-addr", 23, &error_abort);
233 object_property_set_int(OBJECT(dev), "num-priority-queues", 2,
234 &error_abort);
235 object_property_set_link(OBJECT(dev), "dma", OBJECT(&s->mr_ps),
236 &error_abort);
237 sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal);
238
239 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
240 memory_region_add_subregion(&s->mr_ps, addrs[i], mr);
241
242 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[irqs[i]]);
243 g_free(name);
244 }
245 }
246
247 static void versal_create_admas(Versal *s, qemu_irq *pic)
248 {
249 int i;
250
251 for (i = 0; i < ARRAY_SIZE(s->lpd.iou.adma); i++) {
252 char *name = g_strdup_printf("adma%d", i);
253 DeviceState *dev;
254 MemoryRegion *mr;
255
256 object_initialize_child(OBJECT(s), name, &s->lpd.iou.adma[i],
257 TYPE_XLNX_ZDMA);
258 dev = DEVICE(&s->lpd.iou.adma[i]);
259 object_property_set_int(OBJECT(dev), "bus-width", 128, &error_abort);
260 object_property_set_link(OBJECT(dev), "dma",
261 OBJECT(get_system_memory()), &error_fatal);
262 sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal);
263
264 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
265 memory_region_add_subregion(&s->mr_ps,
266 MM_ADMA_CH0 + i * MM_ADMA_CH0_SIZE, mr);
267
268 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[VERSAL_ADMA_IRQ_0 + i]);
269 g_free(name);
270 }
271 }
272
273 #define SDHCI_CAPABILITIES 0x280737ec6481 /* Same as on ZynqMP. */
274 static void versal_create_sds(Versal *s, qemu_irq *pic)
275 {
276 int i;
277
278 for (i = 0; i < ARRAY_SIZE(s->pmc.iou.sd); i++) {
279 DeviceState *dev;
280 MemoryRegion *mr;
281
282 object_initialize_child(OBJECT(s), "sd[*]", &s->pmc.iou.sd[i],
283 TYPE_SYSBUS_SDHCI);
284 dev = DEVICE(&s->pmc.iou.sd[i]);
285
286 object_property_set_uint(OBJECT(dev), "sd-spec-version", 3,
287 &error_fatal);
288 object_property_set_uint(OBJECT(dev), "capareg", SDHCI_CAPABILITIES,
289 &error_fatal);
290 object_property_set_uint(OBJECT(dev), "uhs", UHS_I, &error_fatal);
291 sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal);
292
293 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
294 memory_region_add_subregion(&s->mr_ps,
295 MM_PMC_SD0 + i * MM_PMC_SD0_SIZE, mr);
296
297 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
298 pic[VERSAL_SD0_IRQ_0 + i * 2]);
299 }
300 }
301
302 static void versal_create_pmc_apb_irq_orgate(Versal *s, qemu_irq *pic)
303 {
304 DeviceState *orgate;
305
306 /*
307 * The VERSAL_PMC_APB_IRQ is an 'or' of the interrupts from the following
308 * models:
309 * - RTC
310 * - BBRAM
311 * - PMC SLCR
312 */
313 object_initialize_child(OBJECT(s), "pmc-apb-irq-orgate",
314 &s->pmc.apb_irq_orgate, TYPE_OR_IRQ);
315 orgate = DEVICE(&s->pmc.apb_irq_orgate);
316 object_property_set_int(OBJECT(orgate),
317 "num-lines", VERSAL_NUM_PMC_APB_IRQS, &error_fatal);
318 qdev_realize(orgate, NULL, &error_fatal);
319 qdev_connect_gpio_out(orgate, 0, pic[VERSAL_PMC_APB_IRQ]);
320 }
321
322 static void versal_create_rtc(Versal *s, qemu_irq *pic)
323 {
324 SysBusDevice *sbd;
325 MemoryRegion *mr;
326
327 object_initialize_child(OBJECT(s), "rtc", &s->pmc.rtc,
328 TYPE_XLNX_ZYNQMP_RTC);
329 sbd = SYS_BUS_DEVICE(&s->pmc.rtc);
330 sysbus_realize(SYS_BUS_DEVICE(sbd), &error_fatal);
331
332 mr = sysbus_mmio_get_region(sbd, 0);
333 memory_region_add_subregion(&s->mr_ps, MM_PMC_RTC, mr);
334
335 /*
336 * TODO: Connect the ALARM and SECONDS interrupts once our RTC model
337 * supports them.
338 */
339 sysbus_connect_irq(sbd, 1,
340 qdev_get_gpio_in(DEVICE(&s->pmc.apb_irq_orgate), 0));
341 }
342
343 static void versal_create_xrams(Versal *s, qemu_irq *pic)
344 {
345 int nr_xrams = ARRAY_SIZE(s->lpd.xram.ctrl);
346 DeviceState *orgate;
347 int i;
348
349 /* XRAM IRQs get ORed into a single line. */
350 object_initialize_child(OBJECT(s), "xram-irq-orgate",
351 &s->lpd.xram.irq_orgate, TYPE_OR_IRQ);
352 orgate = DEVICE(&s->lpd.xram.irq_orgate);
353 object_property_set_int(OBJECT(orgate),
354 "num-lines", nr_xrams, &error_fatal);
355 qdev_realize(orgate, NULL, &error_fatal);
356 qdev_connect_gpio_out(orgate, 0, pic[VERSAL_XRAM_IRQ_0]);
357
358 for (i = 0; i < ARRAY_SIZE(s->lpd.xram.ctrl); i++) {
359 SysBusDevice *sbd;
360 MemoryRegion *mr;
361
362 object_initialize_child(OBJECT(s), "xram[*]", &s->lpd.xram.ctrl[i],
363 TYPE_XLNX_XRAM_CTRL);
364 sbd = SYS_BUS_DEVICE(&s->lpd.xram.ctrl[i]);
365 sysbus_realize(sbd, &error_fatal);
366
367 mr = sysbus_mmio_get_region(sbd, 0);
368 memory_region_add_subregion(&s->mr_ps,
369 MM_XRAMC + i * MM_XRAMC_SIZE, mr);
370 mr = sysbus_mmio_get_region(sbd, 1);
371 memory_region_add_subregion(&s->mr_ps, MM_XRAM + i * MiB, mr);
372
373 sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(orgate, i));
374 }
375 }
376
377 static void versal_create_bbram(Versal *s, qemu_irq *pic)
378 {
379 SysBusDevice *sbd;
380
381 object_initialize_child_with_props(OBJECT(s), "bbram", &s->pmc.bbram,
382 sizeof(s->pmc.bbram), TYPE_XLNX_BBRAM,
383 &error_fatal,
384 "crc-zpads", "0",
385 NULL);
386 sbd = SYS_BUS_DEVICE(&s->pmc.bbram);
387
388 sysbus_realize(sbd, &error_fatal);
389 memory_region_add_subregion(&s->mr_ps, MM_PMC_BBRAM_CTRL,
390 sysbus_mmio_get_region(sbd, 0));
391 sysbus_connect_irq(sbd, 0,
392 qdev_get_gpio_in(DEVICE(&s->pmc.apb_irq_orgate), 1));
393 }
394
395 static void versal_realize_efuse_part(Versal *s, Object *dev, hwaddr base)
396 {
397 SysBusDevice *part = SYS_BUS_DEVICE(dev);
398
399 object_property_set_link(OBJECT(part), "efuse",
400 OBJECT(&s->pmc.efuse), &error_abort);
401
402 sysbus_realize(part, &error_abort);
403 memory_region_add_subregion(&s->mr_ps, base,
404 sysbus_mmio_get_region(part, 0));
405 }
406
407 static void versal_create_efuse(Versal *s, qemu_irq *pic)
408 {
409 Object *bits = OBJECT(&s->pmc.efuse);
410 Object *ctrl = OBJECT(&s->pmc.efuse_ctrl);
411 Object *cache = OBJECT(&s->pmc.efuse_cache);
412
413 object_initialize_child(OBJECT(s), "efuse-ctrl", &s->pmc.efuse_ctrl,
414 TYPE_XLNX_VERSAL_EFUSE_CTRL);
415
416 object_initialize_child(OBJECT(s), "efuse-cache", &s->pmc.efuse_cache,
417 TYPE_XLNX_VERSAL_EFUSE_CACHE);
418
419 object_initialize_child_with_props(ctrl, "xlnx-efuse@0", bits,
420 sizeof(s->pmc.efuse),
421 TYPE_XLNX_EFUSE, &error_abort,
422 "efuse-nr", "3",
423 "efuse-size", "8192",
424 NULL);
425
426 qdev_realize(DEVICE(bits), NULL, &error_abort);
427 versal_realize_efuse_part(s, ctrl, MM_PMC_EFUSE_CTRL);
428 versal_realize_efuse_part(s, cache, MM_PMC_EFUSE_CACHE);
429
430 sysbus_connect_irq(SYS_BUS_DEVICE(ctrl), 0, pic[VERSAL_EFUSE_IRQ]);
431 }
432
433 static void versal_create_pmc_iou_slcr(Versal *s, qemu_irq *pic)
434 {
435 SysBusDevice *sbd;
436
437 object_initialize_child(OBJECT(s), "versal-pmc-iou-slcr", &s->pmc.iou.slcr,
438 TYPE_XILINX_VERSAL_PMC_IOU_SLCR);
439
440 sbd = SYS_BUS_DEVICE(&s->pmc.iou.slcr);
441 sysbus_realize(sbd, &error_fatal);
442
443 memory_region_add_subregion(&s->mr_ps, MM_PMC_PMC_IOU_SLCR,
444 sysbus_mmio_get_region(sbd, 0));
445
446 sysbus_connect_irq(sbd, 0,
447 qdev_get_gpio_in(DEVICE(&s->pmc.apb_irq_orgate), 2));
448 }
449
450 static void versal_create_ospi(Versal *s, qemu_irq *pic)
451 {
452 SysBusDevice *sbd;
453 MemoryRegion *mr_dac;
454 qemu_irq ospi_mux_sel;
455 DeviceState *orgate;
456
457 memory_region_init(&s->pmc.iou.ospi.linear_mr, OBJECT(s),
458 "versal-ospi-linear-mr" , MM_PMC_OSPI_DAC_SIZE);
459
460 object_initialize_child(OBJECT(s), "versal-ospi", &s->pmc.iou.ospi.ospi,
461 TYPE_XILINX_VERSAL_OSPI);
462
463 mr_dac = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->pmc.iou.ospi.ospi), 1);
464 memory_region_add_subregion(&s->pmc.iou.ospi.linear_mr, 0x0, mr_dac);
465
466 /* Create the OSPI destination DMA */
467 object_initialize_child(OBJECT(s), "versal-ospi-dma-dst",
468 &s->pmc.iou.ospi.dma_dst,
469 TYPE_XLNX_CSU_DMA);
470
471 object_property_set_link(OBJECT(&s->pmc.iou.ospi.dma_dst),
472 "dma", OBJECT(get_system_memory()),
473 &error_abort);
474
475 sbd = SYS_BUS_DEVICE(&s->pmc.iou.ospi.dma_dst);
476 sysbus_realize(sbd, &error_fatal);
477
478 memory_region_add_subregion(&s->mr_ps, MM_PMC_OSPI_DMA_DST,
479 sysbus_mmio_get_region(sbd, 0));
480
481 /* Create the OSPI source DMA */
482 object_initialize_child(OBJECT(s), "versal-ospi-dma-src",
483 &s->pmc.iou.ospi.dma_src,
484 TYPE_XLNX_CSU_DMA);
485
486 object_property_set_bool(OBJECT(&s->pmc.iou.ospi.dma_src), "is-dst",
487 false, &error_abort);
488
489 object_property_set_link(OBJECT(&s->pmc.iou.ospi.dma_src),
490 "dma", OBJECT(mr_dac), &error_abort);
491
492 object_property_set_link(OBJECT(&s->pmc.iou.ospi.dma_src),
493 "stream-connected-dma",
494 OBJECT(&s->pmc.iou.ospi.dma_dst),
495 &error_abort);
496
497 sbd = SYS_BUS_DEVICE(&s->pmc.iou.ospi.dma_src);
498 sysbus_realize(sbd, &error_fatal);
499
500 memory_region_add_subregion(&s->mr_ps, MM_PMC_OSPI_DMA_SRC,
501 sysbus_mmio_get_region(sbd, 0));
502
503 /* Realize the OSPI */
504 object_property_set_link(OBJECT(&s->pmc.iou.ospi.ospi), "dma-src",
505 OBJECT(&s->pmc.iou.ospi.dma_src), &error_abort);
506
507 sbd = SYS_BUS_DEVICE(&s->pmc.iou.ospi.ospi);
508 sysbus_realize(sbd, &error_fatal);
509
510 memory_region_add_subregion(&s->mr_ps, MM_PMC_OSPI,
511 sysbus_mmio_get_region(sbd, 0));
512
513 memory_region_add_subregion(&s->mr_ps, MM_PMC_OSPI_DAC,
514 &s->pmc.iou.ospi.linear_mr);
515
516 /* ospi_mux_sel */
517 ospi_mux_sel = qdev_get_gpio_in_named(DEVICE(&s->pmc.iou.ospi.ospi),
518 "ospi-mux-sel", 0);
519 qdev_connect_gpio_out_named(DEVICE(&s->pmc.iou.slcr), "ospi-mux-sel", 0,
520 ospi_mux_sel);
521
522 /* OSPI irq */
523 object_initialize_child(OBJECT(s), "ospi-irq-orgate",
524 &s->pmc.iou.ospi.irq_orgate, TYPE_OR_IRQ);
525 object_property_set_int(OBJECT(&s->pmc.iou.ospi.irq_orgate),
526 "num-lines", NUM_OSPI_IRQ_LINES, &error_fatal);
527
528 orgate = DEVICE(&s->pmc.iou.ospi.irq_orgate);
529 qdev_realize(orgate, NULL, &error_fatal);
530
531 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pmc.iou.ospi.ospi), 0,
532 qdev_get_gpio_in(orgate, 0));
533 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pmc.iou.ospi.dma_src), 0,
534 qdev_get_gpio_in(orgate, 1));
535 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pmc.iou.ospi.dma_dst), 0,
536 qdev_get_gpio_in(orgate, 2));
537
538 qdev_connect_gpio_out(orgate, 0, pic[VERSAL_OSPI_IRQ]);
539 }
540
541 static void versal_create_crl(Versal *s, qemu_irq *pic)
542 {
543 SysBusDevice *sbd;
544 int i;
545
546 object_initialize_child(OBJECT(s), "crl", &s->lpd.crl,
547 TYPE_XLNX_VERSAL_CRL);
548 sbd = SYS_BUS_DEVICE(&s->lpd.crl);
549
550 for (i = 0; i < ARRAY_SIZE(s->lpd.rpu.cpu); i++) {
551 g_autofree gchar *name = g_strdup_printf("cpu_r5[%d]", i);
552
553 object_property_set_link(OBJECT(&s->lpd.crl),
554 name, OBJECT(&s->lpd.rpu.cpu[i]),
555 &error_abort);
556 }
557
558 for (i = 0; i < ARRAY_SIZE(s->lpd.iou.gem); i++) {
559 g_autofree gchar *name = g_strdup_printf("gem[%d]", i);
560
561 object_property_set_link(OBJECT(&s->lpd.crl),
562 name, OBJECT(&s->lpd.iou.gem[i]),
563 &error_abort);
564 }
565
566 for (i = 0; i < ARRAY_SIZE(s->lpd.iou.adma); i++) {
567 g_autofree gchar *name = g_strdup_printf("adma[%d]", i);
568
569 object_property_set_link(OBJECT(&s->lpd.crl),
570 name, OBJECT(&s->lpd.iou.adma[i]),
571 &error_abort);
572 }
573
574 for (i = 0; i < ARRAY_SIZE(s->lpd.iou.uart); i++) {
575 g_autofree gchar *name = g_strdup_printf("uart[%d]", i);
576
577 object_property_set_link(OBJECT(&s->lpd.crl),
578 name, OBJECT(&s->lpd.iou.uart[i]),
579 &error_abort);
580 }
581
582 object_property_set_link(OBJECT(&s->lpd.crl),
583 "usb", OBJECT(&s->lpd.iou.usb),
584 &error_abort);
585
586 sysbus_realize(sbd, &error_fatal);
587 memory_region_add_subregion(&s->mr_ps, MM_CRL,
588 sysbus_mmio_get_region(sbd, 0));
589 sysbus_connect_irq(sbd, 0, pic[VERSAL_CRL_IRQ]);
590 }
591
592 /* This takes the board allocated linear DDR memory and creates aliases
593 * for each split DDR range/aperture on the Versal address map.
594 */
595 static void versal_map_ddr(Versal *s)
596 {
597 uint64_t size = memory_region_size(s->cfg.mr_ddr);
598 /* Describes the various split DDR access regions. */
599 static const struct {
600 uint64_t base;
601 uint64_t size;
602 } addr_ranges[] = {
603 { MM_TOP_DDR, MM_TOP_DDR_SIZE },
604 { MM_TOP_DDR_2, MM_TOP_DDR_2_SIZE },
605 { MM_TOP_DDR_3, MM_TOP_DDR_3_SIZE },
606 { MM_TOP_DDR_4, MM_TOP_DDR_4_SIZE }
607 };
608 uint64_t offset = 0;
609 int i;
610
611 assert(ARRAY_SIZE(addr_ranges) == ARRAY_SIZE(s->noc.mr_ddr_ranges));
612 for (i = 0; i < ARRAY_SIZE(addr_ranges) && size; i++) {
613 char *name;
614 uint64_t mapsize;
615
616 mapsize = size < addr_ranges[i].size ? size : addr_ranges[i].size;
617 name = g_strdup_printf("noc-ddr-range%d", i);
618 /* Create the MR alias. */
619 memory_region_init_alias(&s->noc.mr_ddr_ranges[i], OBJECT(s),
620 name, s->cfg.mr_ddr,
621 offset, mapsize);
622
623 /* Map it onto the NoC MR. */
624 memory_region_add_subregion(&s->mr_ps, addr_ranges[i].base,
625 &s->noc.mr_ddr_ranges[i]);
626 offset += mapsize;
627 size -= mapsize;
628 g_free(name);
629 }
630 }
631
632 static void versal_unimp_area(Versal *s, const char *name,
633 MemoryRegion *mr,
634 hwaddr base, hwaddr size)
635 {
636 DeviceState *dev = qdev_new(TYPE_UNIMPLEMENTED_DEVICE);
637 MemoryRegion *mr_dev;
638
639 qdev_prop_set_string(dev, "name", name);
640 qdev_prop_set_uint64(dev, "size", size);
641 object_property_add_child(OBJECT(s), name, OBJECT(dev));
642 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
643
644 mr_dev = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
645 memory_region_add_subregion(mr, base, mr_dev);
646 }
647
648 static void versal_unimp_sd_emmc_sel(void *opaque, int n, int level)
649 {
650 qemu_log_mask(LOG_UNIMP,
651 "Selecting between enabling SD mode or eMMC mode on "
652 "controller %d is not yet implemented\n", n);
653 }
654
655 static void versal_unimp_qspi_ospi_mux_sel(void *opaque, int n, int level)
656 {
657 qemu_log_mask(LOG_UNIMP,
658 "Selecting between enabling the QSPI or OSPI linear address "
659 "region is not yet implemented\n");
660 }
661
662 static void versal_unimp_irq_parity_imr(void *opaque, int n, int level)
663 {
664 qemu_log_mask(LOG_UNIMP,
665 "PMC SLCR parity interrupt behaviour "
666 "is not yet implemented\n");
667 }
668
669 static void versal_unimp(Versal *s)
670 {
671 qemu_irq gpio_in;
672
673 versal_unimp_area(s, "psm", &s->mr_ps,
674 MM_PSM_START, MM_PSM_END - MM_PSM_START);
675 versal_unimp_area(s, "crf", &s->mr_ps,
676 MM_FPD_CRF, MM_FPD_CRF_SIZE);
677 versal_unimp_area(s, "apu", &s->mr_ps,
678 MM_FPD_FPD_APU, MM_FPD_FPD_APU_SIZE);
679 versal_unimp_area(s, "crp", &s->mr_ps,
680 MM_PMC_CRP, MM_PMC_CRP_SIZE);
681 versal_unimp_area(s, "iou-scntr", &s->mr_ps,
682 MM_IOU_SCNTR, MM_IOU_SCNTR_SIZE);
683 versal_unimp_area(s, "iou-scntr-seucre", &s->mr_ps,
684 MM_IOU_SCNTRS, MM_IOU_SCNTRS_SIZE);
685
686 qdev_init_gpio_in_named(DEVICE(s), versal_unimp_sd_emmc_sel,
687 "sd-emmc-sel-dummy", 2);
688 qdev_init_gpio_in_named(DEVICE(s), versal_unimp_qspi_ospi_mux_sel,
689 "qspi-ospi-mux-sel-dummy", 1);
690 qdev_init_gpio_in_named(DEVICE(s), versal_unimp_irq_parity_imr,
691 "irq-parity-imr-dummy", 1);
692
693 gpio_in = qdev_get_gpio_in_named(DEVICE(s), "sd-emmc-sel-dummy", 0);
694 qdev_connect_gpio_out_named(DEVICE(&s->pmc.iou.slcr), "sd-emmc-sel", 0,
695 gpio_in);
696
697 gpio_in = qdev_get_gpio_in_named(DEVICE(s), "sd-emmc-sel-dummy", 1);
698 qdev_connect_gpio_out_named(DEVICE(&s->pmc.iou.slcr), "sd-emmc-sel", 1,
699 gpio_in);
700
701 gpio_in = qdev_get_gpio_in_named(DEVICE(s), "qspi-ospi-mux-sel-dummy", 0);
702 qdev_connect_gpio_out_named(DEVICE(&s->pmc.iou.slcr),
703 "qspi-ospi-mux-sel", 0,
704 gpio_in);
705
706 gpio_in = qdev_get_gpio_in_named(DEVICE(s), "irq-parity-imr-dummy", 0);
707 qdev_connect_gpio_out_named(DEVICE(&s->pmc.iou.slcr),
708 SYSBUS_DEVICE_GPIO_IRQ, 0,
709 gpio_in);
710 }
711
712 static void versal_realize(DeviceState *dev, Error **errp)
713 {
714 Versal *s = XLNX_VERSAL(dev);
715 qemu_irq pic[XLNX_VERSAL_NR_IRQS];
716
717 versal_create_apu_cpus(s);
718 versal_create_apu_gic(s, pic);
719 versal_create_rpu_cpus(s);
720 versal_create_uarts(s, pic);
721 versal_create_usbs(s, pic);
722 versal_create_gems(s, pic);
723 versal_create_admas(s, pic);
724 versal_create_sds(s, pic);
725 versal_create_pmc_apb_irq_orgate(s, pic);
726 versal_create_rtc(s, pic);
727 versal_create_xrams(s, pic);
728 versal_create_bbram(s, pic);
729 versal_create_efuse(s, pic);
730 versal_create_pmc_iou_slcr(s, pic);
731 versal_create_ospi(s, pic);
732 versal_create_crl(s, pic);
733 versal_map_ddr(s);
734 versal_unimp(s);
735
736 /* Create the On Chip Memory (OCM). */
737 memory_region_init_ram(&s->lpd.mr_ocm, OBJECT(s), "ocm",
738 MM_OCM_SIZE, &error_fatal);
739
740 memory_region_add_subregion_overlap(&s->mr_ps, MM_OCM, &s->lpd.mr_ocm, 0);
741 memory_region_add_subregion_overlap(&s->fpd.apu.mr, 0, &s->mr_ps, 0);
742 memory_region_add_subregion_overlap(&s->lpd.rpu.mr, 0,
743 &s->lpd.rpu.mr_ps_alias, 0);
744 }
745
746 static void versal_init(Object *obj)
747 {
748 Versal *s = XLNX_VERSAL(obj);
749
750 memory_region_init(&s->fpd.apu.mr, obj, "mr-apu", UINT64_MAX);
751 memory_region_init(&s->lpd.rpu.mr, obj, "mr-rpu", UINT64_MAX);
752 memory_region_init(&s->mr_ps, obj, "mr-ps-switch", UINT64_MAX);
753 memory_region_init_alias(&s->lpd.rpu.mr_ps_alias, OBJECT(s),
754 "mr-rpu-ps-alias", &s->mr_ps, 0, UINT64_MAX);
755 }
756
757 static Property versal_properties[] = {
758 DEFINE_PROP_LINK("ddr", Versal, cfg.mr_ddr, TYPE_MEMORY_REGION,
759 MemoryRegion *),
760 DEFINE_PROP_END_OF_LIST()
761 };
762
763 static void versal_class_init(ObjectClass *klass, void *data)
764 {
765 DeviceClass *dc = DEVICE_CLASS(klass);
766
767 dc->realize = versal_realize;
768 device_class_set_props(dc, versal_properties);
769 /* No VMSD since we haven't got any top-level SoC state to save. */
770 }
771
772 static const TypeInfo versal_info = {
773 .name = TYPE_XLNX_VERSAL,
774 .parent = TYPE_SYS_BUS_DEVICE,
775 .instance_size = sizeof(Versal),
776 .instance_init = versal_init,
777 .class_init = versal_class_init,
778 };
779
780 static void versal_register_types(void)
781 {
782 type_register_static(&versal_info);
783 }
784
785 type_init(versal_register_types);
armbru's QEMU hackery