util/bufferiszero: Add simd acceleration for aarch64
[qemu/armbru.git] / tcg / i386 / tcg-target.opc.h
blobb5f403e35e1c0bf0369628fe93e26931bd363c8b
1 /*
2 * Copyright (c) 2019 Linaro
4 * Permission is hereby granted, free of charge, to any person obtaining a copy
5 * of this software and associated documentation files (the "Software"), to deal
6 * in the Software without restriction, including without limitation the rights
7 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
8 * copies of the Software, and to permit persons to whom the Software is
9 * furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
19 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
20 * THE SOFTWARE.
22 * Target-specific opcodes for host vector expansion. These will be
23 * emitted by tcg_expand_vec_op. For those familiar with GCC internals,
24 * consider these to be UNSPEC with names.
27 DEF(x86_shufps_vec, 1, 2, 1, IMPLVEC)
28 DEF(x86_vpblendvb_vec, 1, 3, 0, IMPLVEC)
29 DEF(x86_blend_vec, 1, 2, 1, IMPLVEC)
30 DEF(x86_packss_vec, 1, 2, 0, IMPLVEC)
31 DEF(x86_packus_vec, 1, 2, 0, IMPLVEC)
32 DEF(x86_psrldq_vec, 1, 1, 1, IMPLVEC)
33 DEF(x86_vperm2i128_vec, 1, 2, 1, IMPLVEC)
34 DEF(x86_punpckl_vec, 1, 2, 0, IMPLVEC)
35 DEF(x86_punpckh_vec, 1, 2, 0, IMPLVEC)
36 DEF(x86_vpshldi_vec, 1, 2, 1, IMPLVEC)
37 DEF(x86_vpshldv_vec, 1, 3, 0, IMPLVEC)
38 DEF(x86_vpshrdv_vec, 1, 3, 0, IMPLVEC)