tests/tcg/arm: Manually register allocate half-precision numbers
[qemu/armbru.git] / linux-user / user-internals.h
blob5c7f173ceb437562722d93f441521ed00b001d19
1 /*
2 * user-internals.h: prototypes etc internal to the linux-user implementation
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, see <http://www.gnu.org/licenses/>.
18 #ifndef LINUX_USER_USER_INTERNALS_H
19 #define LINUX_USER_USER_INTERNALS_H
21 #include "user/thunk.h"
22 #include "exec/exec-all.h"
23 #include "exec/tb-flush.h"
24 #include "qemu/log.h"
26 extern char *exec_path;
27 void init_task_state(TaskState *ts);
28 void task_settid(TaskState *);
29 void stop_all_tasks(void);
30 extern const char *qemu_uname_release;
31 extern unsigned long mmap_min_addr;
33 typedef struct IOCTLEntry IOCTLEntry;
35 typedef abi_long do_ioctl_fn(const IOCTLEntry *ie, uint8_t *buf_temp,
36 int fd, int cmd, abi_long arg);
38 struct IOCTLEntry {
39 int target_cmd;
40 unsigned int host_cmd;
41 const char *name;
42 int access;
43 do_ioctl_fn *do_ioctl;
44 const argtype arg_type[5];
47 extern IOCTLEntry ioctl_entries[];
49 #define IOC_R 0x0001
50 #define IOC_W 0x0002
51 #define IOC_RW (IOC_R | IOC_W)
54 * Returns true if the image uses the FDPIC ABI. If this is the case,
55 * we have to provide some information (loadmap, pt_dynamic_info) such
56 * that the program can be relocated adequately. This is also useful
57 * when handling signals.
59 int info_is_fdpic(struct image_info *info);
61 void target_set_brk(abi_ulong new_brk);
62 void syscall_init(void);
63 abi_long do_syscall(CPUArchState *cpu_env, int num, abi_long arg1,
64 abi_long arg2, abi_long arg3, abi_long arg4,
65 abi_long arg5, abi_long arg6, abi_long arg7,
66 abi_long arg8);
67 extern __thread CPUState *thread_cpu;
68 G_NORETURN void cpu_loop(CPUArchState *env);
69 abi_long get_errno(abi_long ret);
70 const char *target_strerror(int err);
71 int get_osversion(void);
72 void init_qemu_uname_release(void);
73 void fork_start(void);
74 void fork_end(pid_t pid);
76 /**
77 * probe_guest_base:
78 * @image_name: the executable being loaded
79 * @loaddr: the lowest fixed address within the executable
80 * @hiaddr: the highest fixed address within the executable
82 * Creates the initial guest address space in the host memory space.
84 * If @loaddr == 0, then no address in the executable is fixed, i.e.
85 * it is fully relocatable. In that case @hiaddr is the size of the
86 * executable minus one.
88 * This function will not return if a valid value for guest_base
89 * cannot be chosen. On return, the executable loader can expect
91 * target_mmap(loaddr, hiaddr - loaddr + 1, ...)
93 * to succeed.
95 void probe_guest_base(const char *image_name,
96 abi_ulong loaddr, abi_ulong hiaddr);
98 /* syscall.c */
99 int host_to_target_waitstatus(int status);
101 #ifdef TARGET_I386
102 /* vm86.c */
103 void save_v86_state(CPUX86State *env);
104 void handle_vm86_trap(CPUX86State *env, int trapno);
105 void handle_vm86_fault(CPUX86State *env);
106 int do_vm86(CPUX86State *env, long subfunction, abi_ulong v86_addr);
107 #elif defined(TARGET_SPARC64)
108 void sparc64_set_context(CPUSPARCState *env);
109 void sparc64_get_context(CPUSPARCState *env);
110 #endif
112 static inline int is_error(abi_long ret)
114 return (abi_ulong)ret >= (abi_ulong)(-4096);
117 #if (TARGET_ABI_BITS == 32) && !defined(TARGET_ABI_MIPSN32)
118 static inline uint64_t target_offset64(uint32_t word0, uint32_t word1)
120 #if TARGET_BIG_ENDIAN
121 return ((uint64_t)word0 << 32) | word1;
122 #else
123 return ((uint64_t)word1 << 32) | word0;
124 #endif
126 #else /* TARGET_ABI_BITS == 32 && !defined(TARGET_ABI_MIPSN32) */
127 static inline uint64_t target_offset64(uint64_t word0, uint64_t word1)
129 return word0;
131 #endif /* TARGET_ABI_BITS != 32 */
133 void print_termios(void *arg);
135 /* ARM EABI and MIPS expect 64bit types aligned even on pairs or registers */
136 #ifdef TARGET_ARM
137 static inline int regpairs_aligned(CPUArchState *cpu_env, int num)
139 return cpu_env->eabi;
141 #elif defined(TARGET_MIPS) && defined(TARGET_ABI_MIPSO32)
142 static inline int regpairs_aligned(CPUArchState *cpu_env, int num) { return 1; }
143 #elif defined(TARGET_PPC) && !defined(TARGET_PPC64)
145 * SysV AVI for PPC32 expects 64bit parameters to be passed on odd/even pairs
146 * of registers which translates to the same as ARM/MIPS, because we start with
147 * r3 as arg1
149 static inline int regpairs_aligned(CPUArchState *cpu_env, int num) { return 1; }
150 #elif defined(TARGET_SH4)
151 /* SH4 doesn't align register pairs, except for p{read,write}64 */
152 static inline int regpairs_aligned(CPUArchState *cpu_env, int num)
154 switch (num) {
155 case TARGET_NR_pread64:
156 case TARGET_NR_pwrite64:
157 return 1;
159 default:
160 return 0;
163 #elif defined(TARGET_XTENSA)
164 static inline int regpairs_aligned(CPUArchState *cpu_env, int num) { return 1; }
165 #elif defined(TARGET_HEXAGON)
166 static inline int regpairs_aligned(CPUArchState *cpu_env, int num) { return 1; }
167 #else
168 static inline int regpairs_aligned(CPUArchState *cpu_env, int num) { return 0; }
169 #endif
172 * preexit_cleanup: housekeeping before the guest exits
174 * env: the CPU state
175 * code: the exit code
177 void preexit_cleanup(CPUArchState *env, int code);
180 * Include target-specific struct and function definitions;
181 * they may need access to the target-independent structures
182 * above, so include them last.
184 #include "target_cpu.h"
185 #include "target_structs.h"
187 #endif